WO2024035391A1

WO2024035391A1 - Apparatus and method for determining whether to perform pre-synchronization while in discontinuous reception mode

Info

Publication number: WO2024035391A1
Application number: PCT/US2022/039750
Authority: WO
Inventors: Jian Gu; Lei KE; Xiao-An Wang
Original assignee: Zeku, Inc.
Priority date: 2022-08-08
Filing date: 2022-08-08
Publication date: 2024-02-15

Abstract

According to another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include identifying a reception condition associated with a discontinuous reception (DRX) cycle. The method may include, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a pre-synchronization period before an active period in the DRX cycle and not performing a pre-synchronization before the active period in the DRX cycle. The method may include, in response to the reception condition being identified as a second reception condition, exiting the sleep mode during the pre-synchronization period and performing a synchronization procedure before the active period in a DRX cycle. In some embodiments, the pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

Description

APPARATUS AND METHOD FOR DETERMINING WHETHER TO PERFORM PRE- SYNCHRONIZATION WHILE IN DISCONTINUOUS RECEPTION MODE

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-gen eration (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various operations for discontinuous reception (DRX).

SUMMARY

[0003] According to one aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include identifying a reception condition associated with a DRX cycle. The method may include, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a presynchronization period before an active period in the DRX cycle and not performing a presynchronization before the active period in the DRX cycle. The method may include, in response to the reception condition being identified as a second reception condition, exiting the sleep mode during the pre-synchronization period and performing a synchronization procedure before the active period in a DRX cycle. In some embodiments, the pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

[0004] According to another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include identifying a reception condition associated with a DRX cycle. The method may include, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a presynchronization period before an active period in the DRX cycle and not performing a presynchronization before the active period in the DRX cycle. The method may include, in response to the reception condition being identified as a second reception condition, exiting the sleep mode during the pre-synchronization period and performing a synchronization procedure before the active period in a DRX cycle. In some embodiments, the pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

[0005] According to yet another aspect of the present disclosure, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores instructions, which when executed by at least one processor, may cause the at least one processor to perform identifying a reception condition associated with a discontinuous reception (DRX) cycle. The non-transitory computer-readable medium stores instructions, which when executed by at least one processor, may cause the at least one processor to perform, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a presynchronization period before an active period in the DRX cycle and not performing a presynchronization before the active period in the DRX cycle. The non-transitory computer-readable medium stores instructions, which when executed by at least one processor, may cause the at least one processor to perform, in response to the reception condition being identified as a second reception condition, exiting the sleep mode during the pre-synchronization period and performing a synchronization procedure before the active period in a DRX cycle. The pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1A illustrates a first timing diagram of a first example DRX procedure that includes pre-synchronization.

[0009] FIG. IB illustrates a second timing diagram of a second example DRX procedure that includes pre-synchronization.

[0010] FIG. 1C illustrates a third timing diagram of a third example DRX procedure that includes pre-synchronization.

[0011] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0012] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0013] FIG. 4 illustrates a block diagram of an exemplary apparatus including a first baseband chip, a second baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0014] FIG. 5A illustrates a first timing diagram of a first exemplary DRX procedure that skips pre-synchronization under certain reception conditions, according to some embodiments of the present disclosure.

[0015] FIG. 5B illustrates a second timing diagram of a second exemplary DRX procedure that skips pre-synchronization under certain reception conditions, according to some embodiments of the present disclosure.

[0016] FIG. 5C illustrates a third timing diagram of a third exemplary DRX procedure that skips pre-synchronization under certain reception conditions, according to some embodiments of the present disclosure.

[0017] FIGs. 6A and 6B illustrate a flowchart of an exemplary method of wireless communication, according to certain embodiments of the present disclosure.

[0018] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0019] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0020] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. [0021] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0022] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0023] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0024] DRX is an important power saving technique for cellular user equipments (UEs). There are two types of DRX: connected mode DRX (CDRX) and idle mode DRX (IDRX). CDRX may be implemented to reduce power consumption by allowing the UE to periodically enter a deep-sleep state during which the physical downlink control channel (PDCCH) need not be monitored. In order to monitor for and receive possible downlink (DL) data packets data, the UE wakes up periodically and enters an awake-state during an active period (also referred to as an “On-duration” or a “paging occasion”) for a certain amount of time before returning to the deepsleep state. While operating in IDRX, the UE periodically wakes up to monitor for paging messages in a paging early indication (PEI) period and then returns to sleep mode if no paging message is received.

[0025] One issue that arises during either DRX mode is a loss of frequency/timing synchronization with the base station, which is also referred to as frequency/timing drift or frequency/timing misalignment. Various factors may contribute to such frequency/timing drift. Temperature change at the baseband chip is one such factor. For example, the timing error while operating in DRX may arise from the frequency drift of the secondary crystal (e.g., the 32kHz crystal) from one wake-up period and/or active period to the next. Thus, the frequency drift of the secondary crystal is usually calibrated during each wake-up period in the DRX cycle. The timing error is generally caused by a change in the ambient temperature surrounding the secondary crystal. The frequency error after wake-up comes from a change in the ambient temperature surrounding the main clock crystal (e.g., 38.4MHz crystal or 76.8MHz crystal) and/or UE mobility, which causes a Doppler shift. The main clock crystal is even more sensitive to changes in temperature than the secondary crystal. Even when the temperature of the main clock crystal and the secondary crystal is stable, the signal-to-noise (SNR) ratio of the communication channel may be unstable, and wireless communication under poor SNR conditions can be very sensitive to frequency/timing drift. To recover frequency/timing information, the UE may perform pre-synchronization after exiting a deep-sleep state (and before an active period in which a DL data packet or paging message may be received) by decoding a synchronization signal block (SSB). Various examples of DRX procedures that include pre-synchronization are described below in connection with FIGs. 1 A-1C. [0026] FIG. 1A illustrates a first timing diagram 100 of a first example DRX procedure that includes pre-synchronization. FIG. IB illustrates a second timing diagram 115 of a second example DRX procedure that includes pre-synchronization. FIG. 1C illustrates a third timing diagram 130 of a third example DRX procedure that includes pre-synchronization. Each of the timing diagrams of FIGs. 1A-1C illustrates various operations and/or states performed by a UE during a current DRX cycle n and a subsequent DRX cycle n+ .

[0027] Referring to FIG. 1 A, the first example DRX procedure includes a deep-sleep state 102, a wake-up period 104, a pre-synchronization period 106, a light-sleep state 108, and an active period 110. To counteract frequency/timing misalignment, the UE may exit the deep-sleep state 102 and enter wake-up period 104 during which the device boots up its various processors and restores information from external memory before pre-synchronization period 106. During wakeup period 104, the various components operating in reduced-power or fully powered down may be turned on. Because powering up the various components is not instantaneous, the wake-up period 104 may be configured with a duration long enough to enable the necessary components to be powered on prior to the pre-synchronization period 106. During pre-synchronization period 106, the UE may monitor for an SSB or other reference signal transmitted by the base station for use in performing frequency/timing synchronization. Once received, the UE may perform presynchronization to calibrate its frequency/timing to align with the base station prior to active period 110. Once pre-synchronization is complete, the UE may enter light-sleep mode 108 for the remainder of the DRX cycle until the start of active period 110. Light-sleep mode may include power-gating certain components to conserve power without fully shutting down the system or the power supply. Waking up from a deep-sleep state requires more time and power than from a lightsleep state. This is at least in part due to double data rate (DDR) data retrieval by the baseband chip when waking up from a deep-sleep state. Hence, using a light-sleep state between the presynchronization period 106 and the active period 108 may be more efficient in terms of energy consumption and latency. During active period 110, the UE may monitor and attempt to decode a signal indicating whether there is/are incoming DL data packet(s) using the frequency/timing adjustment performed during the pre-synchronization period. After receiving the indication signal and/or DL data packet, the UE may enter another deep-sleep state 102 at the start of the subsequent DRX cycle n+ .

[0028] Referring to FIGs. IB and 1C, these example DRX procedures additionally include a wake-up signal (WUS) period 112 (associated with CDRX) or paging early indication (PEI) period 112 (associated with IDRX) located before active period 110. Here, the UE exits light-sleep state 108 prior to the WUS/PEI period 112, during which it monitors for an indication signal when in CDRX mode or a paging indication when in IDRX mode. The base station may use the indication signal or paging indication to convey to the UE whether it has any incoming DL data packet(s) during active period 110. As shown in FIG. IB, when an indication signal or a paging indication is received during WUS/PEI period 112, the UE reenters light-sleep state 108 until active period 110. At the start of active period, the UE wakes up to receive the incoming DL data packet(s). On the other hand, as shown in FIG. 1C, the UE may enter deep-sleep state 102 until the next wake-up period 104 (not shown) in the subsequent DRX cycle n+ when no indication signal or paging indication is received during WUS/PEI period 112.

[0029] One challenge of DRX mode pre-synchronization relates to its power consumption. An undesirable amount of power is consumed by the UE during pre-synchronization period 106, which can have a duration greater than or equal to 20ms. Moreover, the duration of light-sleep state 108 between pre-synchronization period 106 and active period 110 can be greater than or equal to 10ms, and the amount of power consumed needlessly during this period can be around 15%~25% greater than what would be consumed during the same period if the UE were in deepsleep. This power consumption problem persists even under reception conditions in which frequency/timing drift is negligible.

[0030] Thus, there exists an unmet need for a DRX procedure that does not require presynchronization when reception conditions do not cause an undue amount of frequency/timing drift.

[0031] To overcome these and other challenges, the present disclosure provides an exemplary DRX procedure in which pre-synchronization using SSB may be skipped under certain reception conditions. The reception conditions under which the pre-synchronization may be skipped include, e.g., one or more of an SNR that meets or exceeds an SNR threshold, a UE temperature within a predetermined temperature range, a temperature change that is less than or equal to a temperature change threshold, a Doppler shift less than or equal to a Doppler shift threshold, and/or a duration of an extended deep-sleep state is less than or equal to a predetermined length of time, just to name a few. When operating under these reception conditions (referred to herein as “the first reception condition”), the frequency/timing drift may be small enough so as to not negatively impact the UE’ s ability to properly receive/ decode incoming DL data packets during the active period. In some embodiments, the UE may perform frequency/timing adjustment based on the physical downlink control channel (PDCCH) reference signal decoded during the WUS/PEI period when the UE monitors for a WUS or PEI. Additionally and/or alternatively, the UE may perform SSB synchronization during the active period rather than during a pre-synchronization in order to remain in the deep-sleep state longer. Also, during a DRX cycle’s active period, the UE may identify the reception condition for the subsequent DRX cycle. However, the UE may still perform SSB pre-synchronization under other reception conditions (referred to herein as “the second reception condition), e.g., such as those reception conditions that include one or more of poor SNR, high temperature, fast temperature rate of change, large Doppler shift, or a deep-sleep period of undue duration, since the frequency/timing drift may be problematic in those scenarios. [0032] In this way, the exemplary apparatus described herein provides flexibility and feasibility as compared to other mobile devices by supporting SSB pre-synchronization without depleting battery power unnecessarily during reception conditions that are less affected by frequency/timing drift. Additional details of the exemplary apparatus are provided below in connection with FIGs. 2, 3, 4, 5A, 5B, 5C, 6A, and 6B.

[0033] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0034] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0035] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as next generation radio access network (NG-RAN) in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0036] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation. [0037] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0038] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0039] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[0040] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0041] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0042] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0043] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, at least two of processor 302, memory 304, and transceiver 306 are integrated into a single system- on-chip (SoC) or a single system-in-package (SiP). In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0044] Referring back to FIG. 2, in some embodiments, user equipment 202 may perform the exemplary DRX procedure in which pre-synchronization using SSB is skipped under certain reception conditions, while opting to perform pre-synchronization when reception conditions negatively impact frequency/timing drift. Additional details of the exemplary DRX procedure implemented by user equipment 202 are provided below in connection with FIGs. 5A-5C.

[0045] FIG. 4 illustrates a block diagram of an apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some embodiments of the present disclosure. Apparatus 400 may be implemented as UE 202 of wireless network 200 in FIG. 2. As shown in FIG. 4, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 is implemented by a processor and a memory, and RF chip 404 is implemented by a processor, a memory, and a transceiver. Besides the on-chip memory 418 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC or one SiP; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC or one SiP; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC or one SiP, as described above.

[0046] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. Interface 414 of baseband chip 402 may receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via interface 414. RF chip 404, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 404.

[0047] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402.

[0048] As illustrated in FIG. 4, baseband chip 402 may include (in addition to on-chip memory 418) a processor 420, a sensor unit 430, and a DRX unit 440. Processor 420 may be implemented as software, firmware (e.g., a microcontroller), or a mix of both. Sensor unit 430 may include a plurality of different sensors each configured to obtain different sensor information, which may be sent to processor 420 for reception condition identification. DRX unit 440 may be configured to implement the exemplary DRX procedure that skips pre-synchronization under the first reception condition or to implement the example DRX procedure of FIGs. 1A-1C under a second reception condition. For instance, when processor 420 identifies the reception condition (e.g., based on the sensor information) for an upcoming DRX cycle as a first reception condition, processor 420 may send a signal instructing DRX unit 440 to implement the exemplary DRX procedure of FIGs. 5A-5C and skip pre-synchronization. However, when the reception condition is identified as a second reception condition, processor 420 may send a signal instructing DRX unit 440 to perform pre-synchronization, as described above in connection with FIGs. 1A-1C.

[0049] Processor 420 may identify the first reception condition for an upcoming (or current) DRX cycle based on the sensor information collected by sensor unit 430. For instance, the reception condition may be identified based on, e.g., the SNR of the communication channel, the temperature within baseband chip 402, the temperature’s rate of change, the Doppler shift/UE mobility, the length of time of an extended deep-sleep state, and/or when the frequency error from one DRX cycle to the next, just to name a few.

[0050] The first reception condition may be identified according to one or more of, e.g., the SNR being greater than an SNR threshold (e.g., meeting the SNR threshold condition), a temperature falling within a temperature range (e.g., meeting a temperature threshold condition), a rate of temperature change being less than or equal to a temperature change threshold (e.g., meeting a temperature change threshold condition), a Doppler shift being less than or equal to a Doppler shift threshold (e.g., meeting a Doppler shift threshold condition), duration of an extended deep-sleep state being less than a duration threshold (e.g., meeting a duration threshold condition), and/or a frequency error being less than or equal to a frequency error threshold, just to name a few. The second reception condition may be identified according to one or more of, e.g., the SNR being less than an SNR threshold (e.g., not meeting the SNR threshold condition), a temperature not falling within a temperature range (e.g., not meeting the temperature threshold condition), a rate of temperature change being greater than a temperature change threshold (e.g., not meeting the temperature change threshold condition), a Doppler shift being greater than a Doppler shift threshold (e.g., not meeting the Doppler shift threshold condition), duration of an extended deepsleep state being greater than or equal to a duration threshold (e.g., not meeting the duration threshold condition), and/or a frequency error being greater than a frequency error threshold (e.g., not meeting the frequency error threshold condition), etc. In some embodiments, at least one of the second reception conditions is the same as the first reception condition. In some embodiments, the first and second reception condition are different.

[0051] To that end, sensor unit 430 may include a temperature sensor configured to obtain temperature information associated with baseband chip 402 and/or apparatus 400; sensor unit 430 may include an accelerometer configured to obtain mobility information (e.g., speed, velocity and/or acceleration information) associated with a motion of apparatus 400. Processor 420 may use the temperature information to determine whether the temperature is within a temperature threshold range. In a non-limiting embodiment, the temperature threshold range may include, e.g., 10°C to 40°C. This range may be selected because when baseband chip 402 and/or apparatus 400 operates at one of the temperatures in this critical range, the clock frequency (and hence the timing) set by the main crystal may be relatively stable, which means that frequency/timing drift may be minimal. In some embodiments, processor 420 may use the temperature information received from sensor unit 430 in conjunction with temperature history information obtained from on-chip memory 418 to determine the rate of temperature change and/or to predict the temperature of the active period of the subsequent DRX cycle. The rate of temperature change and/or prediction of the temperature during the active period of the subsequent DRX cycle may be predicted based on machine learning regression-based algorithms, just to name a few. The temperature change threshold may be 0.5°C/sec. This may be a critical threshold value because when the temperature changes at a rate no greater than this value, the frequency/timing of the main clock crystal and/or the secondary crystal may be stable. Processor 420 may use the speed, velocity, and/or acceleration information to identify and/or a Doppler shift of signals received from the base station. The Doppler shift threshold may be less than or equal to, e.g., 5Hz. This value may be selected for the Doppler shift threshold because when the Doppler shift is no more than 5Hz, frequency/timing drift may not be significant enough to negatively impact communication with the base station.

[0052] Still further, processor 420 may determine whether the SNR of the communication channel with the base station is greater than or equal to an SNR threshold. By way of example and not limitation, the SNR threshold may be -3dB. When the SNR is greater than or equal to -3dB, any frequency/timing drift may be small enough so that the amount of power savings is preferable to the negligible increase in frequency/timing accuracy that would otherwise be gained by power- hungry pre-synchronization. In some embodiments, processor 420 may determine whether an extended deep-sleep state that skips pre-synchronization is less than a time threshold (e.g., 1ms, 5ms, 10ms, 0.1s, 0.5s, Is, 1.5s, 2s, 2.56s, 5s, etc.). When the extended deep-sleep state exceeds the time threshold, processor 420 may identify the second reception condition since remaining in a deep-sleep state longer than the time threshold may increase the chance of frequency/timing drift that negatively impacts communication with the base station. In some embodiments, processor 420 may determine whether the amount of frequency offset between two or more active periods of different DRX cycles is less than or equal to a frequency offset threshold (e.g., 10Hz, 100Hz, 150Hz, 300Hz, 400Hz, 500Hz, 1kHz, etc.), which indicates relatively stable frequency/timing from one DRX cycle to another. Various exemplary DRX procedures that skip pre-synchronization to remain in an extended deep-sleep state to conserve power are described below in connection with FIGs. 5A-5C.

[0053] FIG. 5A illustrates a first timing diagram 500 of a first exemplary DRX procedure that skips pre-synchronization under certain reception conditions, according to some embodiments of the present disclosure. FIG. 5B illustrates a second timing diagram 515 of a second exemplary DRX procedure that skips pre-synchronization under certain reception conditions, according to some embodiments of the present disclosure. FIG. 5C illustrates a third timing diagram 530 of a third exemplary DRX procedure that skips pre-synchronization under certain reception conditions, according to some embodiments of the present disclosure. As depicted in FIGs. 5A-5C, each of these timing diagrams illustrate various operations, periods, and states associated with DRX cycle n- (a previous DRX cycle), DRX cycle n (a current DRX cycle), and DRX cycle n+ (a subsequent DRX cycle) under the first reception condition in which pre-synchronization is skipped, and an extended deep-sleep state is performed. FIGs. 5A-5C will be described together with reference to FIG. 4.

[0054] Referring to FIGs. 4 and 5 A, during the active period 510 of DRX cycle n-1, processor 420 may identify (at 501a), for its subsequent DRX cycle (e.g., DRX cycle ri), the reception condition as the first reception condition. Processor 420 may identify the first reception condition based at least in part on one or more of the reception condition information (e.g., SNR, temperature, rate of temperature change, Doppler shift, frequency error, length of deep-sleep state when pre-synchronization is skipped, etc.) described above in connection with FIG. 4. Hence, processor 420 sends a signal, which instructs DRX unit 440 to extend deep-sleep state 502 and to skip pre-synchronization. Thus, rather than perform pre-synchronization followed by a light-sleep state (as shown in FIG. 1 A), baseband chip 402 may remain in deep-sleep state 502 until the wakeup period 504 that directly precedes the active period 510. Still referring to FIG. 5A, in some embodiments, processor 420 may perform synchronization (at 503) using an SSB or reference signal decoded/received during active period 510. By updating frequency/timing information when the UE has to be awake anyway, the UE may consume less power than if pre-synchronization is performed. While in active period 510 of DRX cycle n, processor 420 may identify (at 501b) the reception condition for the subsequent DRX cycle n+ based on new sensor information and/or other reception condition information estimated by processor 420. Based on whether the reception condition is the first or second reception condition, processor 420 may send a signal instructing DRX unit 440 to extend the deep-sleep state 502 during the subsequent DRX cycle n+ or to perform the DRX procedure described above in connection with FIG. 1 A.

[0055] Referring to FIGs. 5B and 5C, these exemplary DRX procedures additionally include a WUS period 512 (associated with CDRX) or PEI period 512 (associated with IDRX) followed by a light-sleep state 508 that directly precedes the active period 510. Here, processor 420 may instruct DRX unit 440 to extend the deep-sleep state 502 and to skip pre-synchronization based on identifying (at 501a) the first reception condition for DRX cycle n during the active period 510 DRX cycle n-1. The UE enters a wake-up period 504 in anticipation of the WUS/PEI period 512, during which the UE monitors for a WUS or PEI from the base station. FIG. 5B illustrates a scenario in which the WUS or PEI is received. In this scenario, the WUS or PEI indicates DL data packet(s) or a paging message(s) are incoming during the active period 510 of DRX cycle n. Hence, the UE enters a light-sleep state 508 to conserve power during the time period between WUS/PEI period 512 and the active period 510. At the start of the active period 510, the UE fully powers up and receives the DL data packet(s) and/or paging message(s). FIG. 5C illustrates the scenario in which no WUS or PEI is received or a scenario in which WUS or PEI is received and indicates the UE is not to continue receiving during WUS/PEI period 512. Here, the UE may return to the extended deep-sleep state 502 after the WUS/PEI period 512. In either scenario, the UE may update (at 505) frequency/timing synchronization information based on a PDCCH reference signal decoded during the WUS/PEI period 512. Additionally and/or alternatively, processor 420 may perform (at 503) synchronization using an SSB and/or reference signal decoded during the active period 510.

[0056] In this way, the exemplary apparatus described herein provides flexibility and feasibility as compared to other mobile devices by supporting SSB pre-synchronization without depleting battery power unnecessarily during reception conditions that are less affected by frequency/timing drift.

[0057] FIGs. 6A-6B illustrate a flowchart of an exemplary method 600 of wireless communication, according to embodiments of the disclosure. Exemplary method 600 may be performed by an apparatus for wireless communication, e.g., such as a user equipment, a node, an apparatus, a baseband chip, a processor, an on-chip memory, a sensor unit, and/or a DRX unit. Method 600 may include steps 602-626 as described below. It is to be appreciated that some of the steps may be optional (which may be shown in dashed lines), and some of the steps may be performed simultaneously, or in a different order than shown in FIGs. 6A-6B.

[0058] Referring to FIG. 6A, at 602, the apparatus may identify a reception condition. For example, referring to FIG. 4, processor 420 may identify the first reception condition for an upcoming (or current) DRX cycle based on the sensor information collected by sensor unit 430 or based on other information generated or obtained by processor 420. For instance, the reception condition may be identified based on, e.g., the SNR of the communication channel, the temperature within baseband chip 402, the temperature’s rate of change, the Doppler shift/UE mobility, the length of time of an extended deep-sleep state, and/or when the frequency error from one DRX cycle to the next, just to name a few. The first reception condition may be identified according to one or more of, e.g., the SNR meeting an SNR threshold, a temperature falling within a temperature range, a rate of temperature change being less than or equal to a temperature change threshold, a Doppler shift being less than or equal to a Doppler shift threshold, duration of an extended deepsleep state being less than a duration threshold, and/or a frequency error being less than or equal to a frequency error threshold, just to name a few. The second reception condition may be identified according to one or more of, e.g., the SNR not meeting an SNR threshold, a temperature not falling within a temperature range, a rate of temperature change being greater than a temperature change threshold, a Doppler shift being greater than a Doppler shift threshold, duration of an extended deep-sleep state being greater than or equal to a duration threshold, and/or a frequency error being greater than a frequency error threshold, etc. By way of another example, referring to FIG. 5 A, during the active period 510 of DRX cycle n-1, processor 420 may identify (at 501a), for its subsequent DRX cycle (e.g., DRX cycle n), the reception condition as the first reception condition. Processor 420 may identify the first reception condition based at least in part on one or more of the reception condition information (e.g., SNR, temperature, rate of temperature change, Doppler shift, frequency error, length of deep-sleep state when pre-synchronization is skipped, etc.) described above in connection with FIG. 4.

[0059] At 604, the apparatus may determine whether the reception condition is the first reception condition. In response to the reception condition being the first reception condition (YES: at 604), the operations may move to 606. Otherwise, in response to the reception condition being the second reception condition (NO: at 604), the operations may move to 624.

[0060] At 606, the apparatus may remain in a sleep mode during a pre-synchronization period before an active period in the DRX cycle. For example, referring to FIGs. 4 and 5A-5C, processor 420 sends a signal, which instructs DRX unit 440 to extend deep-sleep state 502 and to skip pre-synchronization. Thus, rather than perform pre-synchronization followed by a light-sleep state (as shown in FIG. 1 A), baseband chip 402 may remain in deep-sleep state 502 until the wakeup period 504 that directly precedes the active period 510.

[0061] At 608, the apparatus may skip a pre-synchronization procedure before the active period in the DRX cycle. For example, referring to FIGs. 4 and 5A-5C, processor 420 sends a signal, which instructs DRX unit 440 to extend deep-sleep state 502 and to skip presynchronization. Thus, rather than perform pre-synchronization followed by a light-sleep state (as shown in FIG. 1 A), baseband chip 402 may remain in deep-sleep state 502 until the wake-up period 504 that directly precedes the active period 510.

[0062] At 610, the apparatus may exit the sleep mode prior to a WUS period or PEI period to receive a WUS or PEI, respectively. For example, referring to FIGs. 5B and 5C, the UE exits deep-sleep state 502 and enters a wake-up period 504 in anticipation of the WUS/PEI period 512, during which the UE monitors for a WUS or PEI from the base station.

[0063] At 612, the apparatus may perform a frequency/timing synchronization using an SSB or reference signal received during the active period during the DRX cycle. For example, referring to FIGs. 4 and 5A-5C, processor 420 may perform synchronization (at 503) using an SSB or reference signal decoded/received during active period 510. By updating frequency/timing information when the UE has to be awake anyway, the UE may consume less power than if presynchronization is performed.

[0064] Referring to FIG. 6B, at 614, the apparatus may perform, during the WUS period or PEI period, a frequency/timing synchronization procedure using a PDCCH reference signal. For example, referring to FIGs. 5B and 5C, the UE may update (at 505) frequency/timing synchronization information based on a PDCCH reference signal decoded during the WUS/PEI period 512.

[0065] At 616, the apparatus may exit the sleep mode prior to a start of the active period during the DRX cycle. For example, referring to FIG. 5 A, rather than perform pre-synchronization followed by a light-sleep state (as shown in FIG. 1 A), baseband chip 402 may remain in deep-sleep state 502 until the wake-up period 504 that directly precedes the active period 510. Referring to FIGs. 5B and 5C, the UE enters a light-sleep state 508 to conserve power during the time period between WUS/PEI period 512 and the active period 510.

[0066] At 618, the apparatus may monitor for a DL transmission (e.g., DL data packet or paging message) during the active period of the DRX cycle. For example, referring to FIGs. 5A- 5C, at the start of the active period 510, the UE fully powers up and receives the DL data packet(s) and/or paging message(s).

[0067] At 620, the apparatus may perform, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle. For example, referring FIGs. 5A-5C, while in active period 510 of DRX cycle //, processor 420 may estimate reception conditions for the subsequent DRX cycle n+ based on temperature information, temperature history information, SNR history information (e.g., SNR information associated with location, time of day, UE mobility, etc.), among others.

[0068] At 622, the apparatus may identify subsequent reception conditions associated with the subsequent DRX cycle based on the reception condition estimation. For example, referring to FIGs. 5A-5C, while in active period 510 of DRX cycle //, processor 420 may identify (at 501b) the reception condition for the subsequent DRX cycle n+ based on new sensor information and/or other reception condition information estimated by processor 420. Based on whether the reception condition is the first or second reception condition, processor 420 may send a signal instructing DRX unit 440 to extend the deep-sleep state 502 during the subsequent DRX cycle n+ or to perform the DRX procedure described above in connection with FIG. 1 A.

[0069] Referring again to FIG. 6A, at 624, the apparatus may exit the sleep mode prior to the pre-synchronization period. For example, referring to FIGs. 1 A-1C, the UE may exit the deepsleep state 102 and enter wake-up period 104, during which the device boots up its various processors and restores information from external memory before pre-synchronization period 106. During wake-up period 104, the various components operating in reduced-power or fully powered down may be turned on. Because powering up the various components is not instantaneous, the wake-up period 104 may be configured with a duration long enough to enable the necessary components to be powered on prior to the pre-synchronization period 106.

[0070] At 626, the apparatus may perform the pre-synchronization procedure during the pre-synchronization period before the active period of the DRX cycle. For example, referring to FIGs. 1A-1C, during pre-synchronization period 106, the UE may monitor for an SSB or other reference signal transmitted by the base station for use in performing frequency/timing synchronization. Once received, the UE may perform pre-synchronization to calibrate its frequency/timing to align with the base station prior to active period 110. Once presynchronization is complete, the UE may enter light-sleep mode 108 for the remainder of the DRX cycle until the start of active period 108. [0071] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0072] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include at least one processor. The baseband chip may include a memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform identifying a reception condition associated with a DRX cycle. The baseband chip may include a memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a pre-synchronization period before an active period in the DRX cycle to skip a pre-synchronization procedure. The baseband chip may include a memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform, in response to the reception condition being identified as a second reception condition, exiting the sleep mode prior to the pre-synchronization period and performing the pre-synchronization procedure during the pre-synchronization period before the active period in a DRX cycle. The pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

[0073] In some embodiments, the first reception condition may include one or more of a first SNR that meets an SNR threshold condition, a first temperature that meets a temperature threshold condition, a first temperature change that meets a temperature change threshold condition, or a first Doppler shift that meets a Doppler shift threshold condition. In some embodiments, the second reception condition may include one or more of a second SNR that does not meet the SNR threshold condition, a second temperature that does not meet the temperature threshold condition, a second temperature change that does not meet the temperature change threshold condition, or a second Doppler shift that does not meet the Doppler shift threshold condition.

[0074] In some embodiments, the reception condition of the DRX cycle may be identified during a previous active period associated with a previous DRX cycle.

[0075] In some embodiments, in response to the first reception condition, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform performing a frequency/timing synchronization using an SSB or reference signal received during the active period in the DRX cycle.

[0076] In some embodiments, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform exiting the sleep mode prior to a WUS period or a PEI period to receive a WUS or PEI, respectively. In some embodiments, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform performing, during the WUS period or the PEI period, a frequency/timing synchronization procedure using a PDCCH reference signal.

[0077] In some embodiments, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform exiting the sleep mode prior to a start of the active period during the DRX cycle. In some embodiments, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform monitoring for a downlink transmission during the active period of the DRX cycle. In some embodiments, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform performing, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle. In some embodiments, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform identifying a subsequent reception condition associated with the subsequent DRX cycle based on the reception condition estimation. [0078] In some embodiments, the memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle by determining first temperature information associated with the DRX cycle. In some embodiments, the memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle by estimating second temperature information associated with the subsequent DRX cycle based on the first temperature information and temperature history information. In some embodiments, the subsequent reception condition may be identified based on the second temperature information.

[0079] According to another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include identifying a reception condition associated with a DRX cycle. The method may include, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a presynchronization period before an active period in the DRX cycle and not performing a presynchronization before the active period in the DRX cycle. The method may include, in response to the reception condition being identified as a second reception condition, exiting the sleep mode during the pre-synchronization period and performing a synchronization procedure before the active period in a DRX cycle. In some embodiments, pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

[0080] In some embodiments, the first reception condition may include one or more of a first SNR that meets an SNR threshold condition, a first temperature that meets a temperature threshold condition, a first temperature change that meets a temperature change threshold condition, or a first Doppler shift that meets a Doppler shift threshold condition. In some embodiments, the second reception condition may include one or more of a second SNR that does not meet the SNR threshold condition, a second temperature that does not meet the temperature threshold condition, a second temperature change that does not meet the temperature change threshold condition, or a second Doppler shift that does not meet the Doppler shift threshold condition.

[0081] In some embodiments, the method may include performing a frequency/timing synchronization using an SSB or reference signal received during the active period in the DRX cycle.

[0082] In some embodiments, the method may include exiting the sleep mode prior to a WUS period or a PEI period to receive a WUS or PEI, respectively. In some embodiments, the method may include performing, during the WUS period or the PEI period, a frequency/timing synchronization procedure using a PDCCH reference signal.

[0083] In some embodiments, the method may include exiting the sleep mode prior to a start of the active period during the DRX cycle. In some embodiments, the method may include monitoring for a downlink transmission during the active period of the DRX cycle. In some embodiments, the method may include performing, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle. In some embodiments, the method may include identifying a subsequent reception condition associated with the subsequent DRX cycle based on the reception condition estimation.

[0084] In some embodiments, the performing, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle may include determining first temperature information associated with the DRX cycle. In some embodiments, the performing, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle may include estimating second temperature information associated with the subsequent DRX cycle based on the first temperature information and temperature history information. In some embodiments, the subsequent reception condition may be identified based on the second temperature information.

[0085] According to yet another aspect of the present disclosure, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores instructions, which when executed by at least one processor, may cause the at least one processor to perform identifying a reception condition associated with a discontinuous reception (DRX) cycle. The non-transitory computer-readable medium stores instructions, which when executed by at least one processor, may cause the at least one processor to perform, in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a presynchronization period before an active period in the DRX cycle and not performing a presynchronization before the active period in the DRX cycle. The non-transitory computer-readable medium stores instructions, which when executed by at least one processor, may cause the at least one processor to perform, in response to the reception condition being identified as a second reception condition, exiting the sleep mode during the pre-synchronization period and performing a synchronization procedure before the active period in a DRX cycle. The pre-synchronization procedure may be associated with a frequency/timing synchronization procedure.

[0086] In some embodiments, the first reception condition may include one or more of a first SNR that meets an SNR threshold condition, a first temperature that meets a temperature threshold condition, a first temperature change that meets a temperature change threshold condition, a first Doppler shift that meets a Doppler shift threshold condition, a first length of an extended sleep state that meets a duration threshold condition, or a first frequency error that meets a frequency error threshold condition. In some embodiments, the second reception condition may include one or more of a second SNR that does not meet the SNR threshold condition, a second temperature that does not meet the temperature threshold condition, a second temperature change that does not meet the temperature change threshold condition, a second Doppler shift that does not meet the Doppler shift threshold condition, a second length of an extended sleep state that does not meet the duration threshold condition, or a second frequency error that does not meet the frequency error threshold condition.

[0087] In some embodiments, the reception condition of the DRX cycle may be identified during a previous active period associated with a previous DRX cycle.

[0088] In some embodiments, in response to the first reception condition, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform performing a frequency/timing synchronization using an SSB or reference signal received during the active period in the DRX cycle.

[0089] In some embodiments, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform exiting the sleep mode prior to a WUS period or a PEI period to receive a WUS or PEI, respectively. In some embodiments, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform performing, during the WUS period or the PEI period, a frequency/timing synchronization procedure using a PDCCH reference signal.

[0090] In some embodiments, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform exiting the sleep mode prior to a start of the active period during the DRX cycle. In some embodiments, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform monitoring for a downlink transmission during the active period of the DRX cycle. In some embodiments, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform performing, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle. In some embodiments, the instructions, which when executed by the at least one processor, may further cause the at least one processor to perform identifying a subsequent reception condition associated with the subsequent DRX cycle based on the reception condition estimation.

[0091] In some embodiments, the instructions, which when executed by the at least one processor, may cause the at least one processor to perform, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle by determining first temperature information associated with the DRX cycle. In some embodiments, the instructions, which when executed by the at least one processor, may cause the at least one processor to perform, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle by estimating second temperature information associated with the subsequent DRX cycle based on the first temperature information and temperature history information. In some embodiments, the subsequent reception condition may be identified based on the second temperature information.

[0092] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0093] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A baseband chip, comprising: at least one processor; and a memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform: identifying a reception condition associated with a discontinuous reception (DRX) cycle; in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a pre-synchronization period before an active period in the DRX cycle to skip a pre-synchronization procedure; and in response to the reception condition being identified as a second reception condition, exiting the sleep mode prior to the pre-synchronization period and performing the pre-synchronization procedure during the pre-synchronization period before the active period in a DRX cycle, wherein the pre-synchronization procedure is associated with a timing/frequency synchronization procedure.

2. The baseband chip of claim 1, wherein: the first reception condition includes one or more of a first signal-to-noise ratio (SNR) that meets an SNR threshold condition, a first temperature that meets a temperature threshold condition, a first temperature change that meets a temperature change threshold condition, a first Doppler shift that meets a Doppler shift threshold condition, a first length of an extended sleep state that meets a duration threshold condition, or a first frequency error that meets a frequency error threshold condition, and the second reception condition includes one or more of a second SNR that does not meet the SNR threshold condition, a second temperature that does not meet the temperature threshold condition, a second temperature change that does not meet the temperature change threshold condition, a second Doppler shift that does not meet the Doppler shift threshold condition, a second length of an extended sleep state that does not meet the duration threshold condition, or a second frequency error that does not meet the frequency error threshold condition.

3. The baseband chip of claim 1, wherein the reception condition of the DRX cycle is identified during a previous active period associated with a previous DRX cycle.

4. The baseband chip of claim 1, wherein, in response to the first reception condition, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform: performing a timing/frequency synchronization using a synchronization signal block (SSB) or reference signal received during the active period in the DRX cycle.

5. The baseband chip of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform: exiting the sleep mode prior to a wake-up signal (WUS) period or a paging early indication (PEI) period to receive a WUS or PEI, respectively; and performing, during the WUS period or the PEI period, a timing/frequency synchronization procedure using a physical downlink control channel (PDCCH) reference signal.

6. The baseband chip of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to perform: exiting the sleep mode prior to a start of the active period during the DRX cycle; monitoring for a downlink transmission during the active period of the DRX cycle; performing, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle; and identifying a subsequent reception condition associated with the subsequent DRX cycle based on the reception condition estimation.

7. The baseband chip of claim 6, wherein the memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle by: determining first temperature information associated with the DRX cycle; and estimating second temperature information associated with the subsequent DRX cycle based on the first temperature information and temperature history information, wherein the subsequent reception condition is identified based on the second temperature information.

8. A method of wireless communication of a baseband chip, comprising: identifying a reception condition associated with a discontinuous reception (DRX) cycle; in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a pre-synchronization period before an active period in the DRX cycle to skip a pre-synchronization procedure; and in response to the reception condition being identified as a second reception condition, exiting the sleep mode prior to the pre-synchronization period and performing the presynchronization procedure during the pre-synchronization period before the active period in a DRX cycle, wherein the pre-synchronization procedure is associated with a timing/frequency synchronization procedure.

9. The method of claim 8, wherein: the first reception condition includes one or more of a first signal-to-noise ratio (SNR) that meets an SNR threshold condition, a first temperature that meets a temperature threshold condition, a first temperature change that meets a temperature change threshold condition, a first Doppler shift that meets a Doppler shift threshold condition, a first length of an extended sleep state that meets a duration threshold condition, or a first frequency error that meets a frequency error threshold condition, and the second reception condition includes one or more of a second SNR that does not meet the SNR threshold condition, a second temperature that does not meet the temperature threshold condition, a second temperature change that does not meet the temperature change threshold condition, a second Doppler shift that does not meet the Doppler shift threshold condition, a second length of an extended sleep state that does not meet the duration threshold condition, or a second frequency error that does not meet the frequency error threshold condition.

10. The method of claim 8, further comprising: performing a timing/frequency synchronization using a synchronization signal block (SSB) or reference signal received during the active period in the DRX cycle.

11. The method of claim 8, further comprising: exiting the sleep mode prior to a wake-up signal (WUS) period or a paging early indication (PEI) period to receive a WUS or PEI, respectively; and performing, during the WUS period or the PEI period, a timing/frequency synchronization procedure using a physical downlink control channel (PDCCH) reference signal.

12. The method of claim 8, further comprising: exiting the sleep mode prior to a start of the active period during the DRX cycle; monitoring for a downlink transmission during the active period of the DRX cycle; performing, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle; and identifying a subsequent reception condition associated with the subsequent DRX cycle based on the reception condition estimation.

13. The method of claim 12, wherein the performing, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle comprises: determining first temperature information associated with the DRX cycle; and estimating second temperature information associated with the subsequent DRX cycle based on the first temperature information and temperature history information, wherein the subsequent reception condition is identified based on the second temperature information.

14. A non-transitory computer-readable medium storing instructions, which when executed by at least one processor, cause the at least one processor to perform: identifying a reception condition associated with a discontinuous reception (DRX) cycle; in response to the reception condition being identified as a first reception condition, remaining in a sleep mode during a pre-synchronization period before an active period in the DRX cycle to skip a pre-synchronization procedure; and in response to the reception condition being identified as a second reception condition, exiting the sleep mode prior to the pre-synchronization period and performing the presynchronization procedure during the pre-synchronization period before the active period in a DRX cycle, wherein the pre-synchronization procedure is associated with a timing/frequency synchronization procedure.

15. The non-transitory computer-readable medium of claim 14, wherein: the first reception condition includes one or more of a first signal-to-noise ratio (SNR) that meets an SNR threshold condition, a first temperature that meets a temperature threshold condition, a first temperature change that meets a temperature change threshold condition, a first Doppler shift that meets a Doppler shift threshold condition, a first length of an extended sleep state that meets a duration threshold condition, or a first frequency error that meets a frequency error threshold condition, and the second reception condition includes one or more of a second SNR that does not meet the SNR threshold condition, a second temperature that does not meet the temperature threshold condition, a second temperature change that does not meet the temperature change threshold condition, a second Doppler shift that does not meet the Doppler shift threshold condition, a second length of an extended sleep state that does not meet the duration threshold condition, or a second frequency error that does not meet the frequency error threshold condition.

16. The non-transitory computer-readable medium of claim 14, wherein the reception condition of the DRX cycle is identified during a previous active period associated with a previous DRX cycle.

17. The non-transitory computer-readable medium of claim 14, wherein, in response to the first reception condition, the instructions, which when executed by the at least one processor, further cause the at least one processor to perform: performing a timing/frequency synchronization using a synchronization signal block (SSB) or reference signal received during the active period in the DRX cycle.

18. The non-transitory computer-readable medium of claim 14, wherein the instructions, which when executed by the at least one processor, further cause the at least one processor to perform: exiting the sleep mode prior to a wake-up signal (WUS) period or a paging early indication (PEI) period to receive a WUS or PEI, respectively; and performing, during the WUS period or the PEI period, a timing/frequency synchronization procedure using a physical downlink control channel (PDCCH) reference signal.

19. The non-transitory computer-readable medium of claim 14, wherein the instructions, which when executed by the at least one processor, further cause the at least one processor to perform: exiting the sleep mode prior to a start of the active period during the DRX cycle; monitoring for a downlink transmission during the active period of the DRX cycle; performing, during the active period of the DRX cycle, reception condition estimation for a subsequent DRX cycle; and identifying a subsequent reception condition associated with the subsequent DRX cycle based on the reception condition estimation.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, which when executed by the at least one processor, cause the at least one processor to perform, during the active period of the DRX cycle, the reception condition estimation for the subsequent DRX cycle by: determining first temperature information associated with the DRX cycle; and estimating second temperature information associated with the subsequent DRX cycle based on the first temperature information and temperature history information, wherein the subsequent reception condition is identified based on the second temperature information.