WO2024024335A1 - Light detection device - Google Patents

Light detection device Download PDF

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Publication number
WO2024024335A1
WO2024024335A1 PCT/JP2023/022642 JP2023022642W WO2024024335A1 WO 2024024335 A1 WO2024024335 A1 WO 2024024335A1 JP 2023022642 W JP2023022642 W JP 2023022642W WO 2024024335 A1 WO2024024335 A1 WO 2024024335A1
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WO
WIPO (PCT)
Prior art keywords
light
logic chip
pixel array
resin material
light shielding
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PCT/JP2023/022642
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French (fr)
Japanese (ja)
Inventor
耕大 丸山
拓治 松本
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024024335A1 publication Critical patent/WO2024024335A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels

Definitions

  • the present technology relates to a photodetection device, and particularly relates to a photodetection device including a pixel array that converts incident light into an electrical signal according to the incident light.
  • a semiconductor device with a multi-chip structure in which a plurality of IC chips (silicon dies) are provided and packaged on one semiconductor substrate is known.
  • a semiconductor device manufactured by stacking a plurality of IC chips on a silicon wafer, dicing them into chips, and packaging the chips is called a COW (Chip on Wafer).
  • a COW type photodetecting device is a semiconductor substrate on which a pixel array consisting of an array of photoelectric conversion elements is formed, and a logic chip having one or more logic circuits formed thereon is arranged in close proximity to the pixel array. It is composed of
  • a photodetector having a structure in which a pixel array and a logic chip are arranged side by side
  • the pixel array receives light
  • the light reflected from the side surface of the logic chip on the pixel array side enters the light receiving surface of the pixel array, and as a result, the image Since flare and the like occur in the semiconductor device, the regions to be light-shielded, such as the top and side surfaces of the logic chip, are covered with a light-shielding resin material member (light-shielding member).
  • Patent Document 1 includes a substrate having a pixel area in which a plurality of pixels are arranged, and one or more chips flip-chip bonded to the substrate via connection terminals, and protects the back surface of the chip.
  • a semiconductor device is disclosed that includes a first resin material and a second resin material that protects the side surface of the chip.
  • a photodetector that supports color images has a color sensor layered on the light-receiving surface of each photoelectric conversion element so that each photoelectric conversion element receives only RGB (Red, Green, Blue) color light. Equipped with a filter. Further, the photodetector includes an on-chip lens on the color filter so that external light can be effectively coupled to the photoelectric conversion element.
  • RGB Red, Green, Blue
  • the thermal stress acts on the semiconductor substrate and the various material films formed on it, and due to the difference in linear expansion coefficient between the material films, separation occurs at the interface of the material films with low adhesion. is likely to occur.
  • the color filters and on-chip lenses used in photodetection devices are made of organic resin material films, their adhesion is relatively low, and due to the difference in linear expansion coefficient between them and the light-shielding material they are in contact with, these interfaces may be damaged. There was a risk that peeling would occur as a starting point, resulting in product defects.
  • the exposed area between the logic chip and the pixel array may be There is a problem in that a portion (for example, an inorganic oxide film) remains, and flare etc. occur due to reflection of light at the exposed portion.
  • the present disclosure provides a photodetection device that effectively suppresses reflected light from a logic chip to a pixel array, and also effectively suppresses peeling at the interface between various material films formed on a semiconductor substrate.
  • the present technology for solving the above problems is configured to include the following invention specific matters or technical features.
  • the present technology includes a semiconductor substrate including a pixel array section in which a plurality of photoelectric conversion elements are arranged in an array, and at least one semiconductor substrate placed on the semiconductor substrate with a space region apart from the pixel array section.
  • the light detection device includes a logic chip, and a light shielding member formed to cover at least a light shielding target region of the logic chip that is proximal to the pixel array section.
  • the pixel array section includes at least one organic resin material film formed on the light receiving surface of the plurality of photoelectric conversion elements. Further, the light shielding member is formed to cover from the light shielding target region of the logic chip to an edge of the organic resin material film formed on the pixel array portion beyond the space region.
  • the organic resin material with respect to the width of the light shielding member from one end of the space region on the light shielding target region side of the logic chip to the hem portion of the light shielding member that covers the edge on the organic resin material film. It is preferable that a width ratio of the light shielding member covering the edge on the resin material film is greater than 0 and less than or equal to 1/2.
  • the term "means” does not simply mean physical means, but also includes cases in which the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.
  • a “system” refers to a logical collection of multiple devices (or functional modules that realize a specific function), and whether each device or functional module is in a single housing or not. There is no particular question.
  • FIG. 1 is a plan view showing an example of a schematic configuration of a photodetecting device according to an embodiment of the present technology.
  • FIG. 2 is a partial cross-sectional view illustrating an example of a schematic configuration of main parts of a photodetection device according to an embodiment of the present technology.
  • FIG. 3 is a diagram for explaining the amount of overlap between an organic resin material film and a light shielding member in a photodetector according to an embodiment of the present technology.
  • FIG. 4 is a partial cross-sectional view for explaining an example of a method for forming a light shielding member on a semiconductor substrate in a manufacturing process of a photodetector according to an embodiment of the present technology.
  • FIG. 1 is a plan view showing an example of a schematic configuration of a photodetecting device according to an embodiment of the present technology.
  • FIG. 2 is a partial cross-sectional view illustrating an example of a schematic configuration of main parts of a photodetection device according to an embodiment of the present technology
  • FIG. 5 is a partial cross-sectional view for explaining an example of a method for forming a light shielding member on a semiconductor substrate in a manufacturing process of a photodetector according to an embodiment of the present technology.
  • FIG. 6 is a partial cross-sectional view for explaining an example of a method for forming a light shielding member on a semiconductor substrate in a manufacturing process of a photodetection device according to an embodiment of the present technology.
  • FIG. 7 is a plan view showing a first modified example of the schematic configuration of the photodetecting device according to an embodiment of the present technology.
  • FIG. 8 is a plan view showing a second modified example of the schematic configuration of the photodetecting device according to an embodiment of the present technology.
  • FIG. 9 is a plan view showing a third modified example of the schematic configuration of the photodetection device according to an embodiment of the present technology.
  • FIG. 10 is a plan view showing a fourth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology.
  • FIG. 11 is a plan view showing a fifth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology.
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an embodiment of the present technology. Further, FIG. 2 is a partial cross-sectional view of a main part of the photodetecting device shown in FIG.
  • the photodetecting device 1 includes a semiconductor substrate 10 on which a pixel array section 11 in which a plurality of photoelectric conversion elements constituting pixels are arranged in an array is formed, and a pixel array section on the semiconductor substrate 10. 11 and a logic chip 12 placed adjacent to the logic chip 11.
  • a photoelectric conversion element (no code) is a semiconductor element that outputs an electrical signal based on charges accumulated in response to incident light. The photoelectric conversion element defines an effective pixel area of the pixel array section 11.
  • the semiconductor substrate 10 includes a wiring layer (not shown) on which a wiring pattern is formed.
  • the logic chip 12 is a silicon die that is electrically connected to the pixel array section 11 via a wiring layer formed in the semiconductor substrate 10 and includes a logic circuit that processes electrical signals output from the pixel array section 11. .
  • this example shows a configuration in which one logic chip 12 is arranged adjacent to the pixel array section 11, the configuration is not limited to this, and as shown in a modified example, a plurality of logic chips 12 A configuration in which a plurality of pixels are arranged around the pixel array section 11 may be used.
  • the photodetection device 1 is assumed to be a back-illuminated CMOS image sensor, but is not limited thereto, and may be, for example, a front-illuminated CMOS image sensor.
  • a plurality of external pad electrodes 13 are formed on the outer periphery of the semiconductor substrate 10.
  • the external pad electrode 13 is used, for example, to contact a probe for semiconductor testing or to connect a wire by wire bonding (not shown).
  • a flattening film 111a is formed on the light receiving surface of the photoelectric conversion element constituting the pixel array section 11, a color filter 111b and an on-chip lens 111c are sequentially laminated thereon, and further, An oxide film 112 is laminated.
  • the flattening film 111a, the color filter 111b, and the on-chip lens 111c are typically made of an organic resin material.
  • the flattening film 111a, the color filter 111b, and/or the on-chip lens 111c made of an organic resin material may be referred to as an organic resin material film 111.
  • the organic resin material film 111 and oxide film 112 that are laminated on the pixel array section 11 are typically formed beyond the effective pixel area of the photoelectric conversion element due to the manufacturing process of the photodetector 1.
  • the edge of the pixel array section 11 near the logic chip 12 on which the organic resin material film 111 is layered is continuous with the light shielding member 14 formed to cover the light shielding target area of the logic chip 12. covered in.
  • the light shielding target area is an area where light reflected from the surface of the logic chip 12 may enter the pixel array section 11.
  • a plurality of dam portions 15 are formed in the shape of grooves at the edges of the organic resin material film 111 and the like (two rows in this example).
  • the dam part 15 dams up the light shielding member 14 and the underfill member 18 described below so that the excess does not reach the effective pixel area.
  • the dam portion 15 is shown as two rows of grooves, but is not limited to this, and may be formed so as to surround the logic chip 12.
  • the pixel array section 11 and the logic chip 12 are arranged side by side with a space region S in between.
  • the space region S is a region where the organic resin material film 111 is not formed (the oxide film 112 may be formed). More specifically, in the manufacturing process of the photodetector 1, the organic resin material film 111 such as the color filter 111b and the on-chip lens 111c is formed over the entire surface of the semiconductor substrate 10, and then the logic chip 12 is The area between the pixel array section 11 and the logic chip 12 as well as the area to be placed are removed by etching or the like. Thereafter, a space region S is defined by placing the logic chip 12 through the bump electrodes 16.
  • the surface shape of the space region S may be flat, or may be random or geometrically uneven.
  • the logic chip 12 is placed so as to be electrically connected to pad electrodes 17 formed on the semiconductor substrate 10 via bump electrodes 16.
  • the logic chip 12 is mounted, for example, by flip-chip mounting.
  • An underfill member 18 is injected into the space between the semiconductor substrate 10 and the logic chip 12, thereby protecting the wiring such as the bump electrodes 16 and fixing the logic chip 12 to the semiconductor substrate 10. .
  • the underfill member 18 protruding around the logic chip 12 is covered with the light shielding member 14.
  • the light-shielding target region of the logic chip 12 that is close to the pixel array section 11 is covered by the light-shielding member 14 .
  • the light shielding target area is an area where light reflected on the surface of the logic chip 12 may enter the pixel array section 11. ).
  • the region to be shaded may be the upper surface portion 12b of the logic chip 12.
  • the light shielding target area may be the corner portions at both ends of the side surface portion 12a and another side surface portion 12c (second side surface portion) orthogonal to the side surface portion 12a.
  • the light shielding member 14 is made of, for example, a thermosetting epoxy resin material or a silicon oxide resin material.
  • the heat applied for curing the light shielding member 14 may cause peeling of the organic resin material film 111 at the interface due to the difference in thermal expansion coefficients. Therefore, as will be described later, the covering ratio of the light shielding member 14 to the organic resin material film 111 is adjusted to suppress peeling of the organic resin material film 111 at the interface.
  • the light shielding member 14 is configured to have a reflectance lower than that of the logic chip 12 in order to prevent reflected light from entering the pixel array section 11 .
  • the light shielding member 14 contains a light absorbing material such as carbon black. Additionally or alternatively, the light shielding member 14 may contain a light diffusing material so that reflected light can be diffused, or its surface may be formed into an uneven shape.
  • the light shielding member 14 is applied from above the semiconductor substrate 10 in the manufacturing process of the photodetector 1, for example, after the logic chip 12 is placed on the semiconductor substrate 10 and fixed by the underfill member 18. Application of the light shielding member 14 is performed in one step or in multiple steps.
  • the applied light shielding member 14 covers the light shielding target region of the logic chip 12 and also covers the space region S, with its tip reaching the edge of the pixel array section 11.
  • the surplus portion of the light shielding member 14 that has reached the edge of the pixel array section 11 is dammed up by a dam section 15 formed at the edge.
  • the width of the bottom portion of the light shielding member 14 that has reached the edge of the pixel array section 11 is the amount of overlap with the organic resin material film 111.
  • the skirt portion of the light shielding member 14 is required to reach the edge of the pixel array portion 11 without fail and cover the organic resin material film 111 with an appropriate amount of covering. , the coverage rate is determined as described below.
  • FIG. 3 is a diagram for explaining the amount of overlap between the organic resin material film and the light shielding member in the photodetector according to an embodiment of the present technology.
  • the covering ratio of the light shielding member 14 at the edge of the pixel array section 11 is the width of the bottom portion of the light shielding member 14 on the edge of the pixel array section 11 relative to the overall width ⁇ of the light shielding member 14. It is defined by the ratio of ⁇ (coverage amount).
  • the overall width ⁇ of the light shielding member 14 is the width from one end of the space region S on the light shielding target area side of the logic chip 12 to the hem portion of the light shielding member 14 that covers the edge.
  • thermosetting material When a thermosetting material is used for the light shielding member 14, there is a risk that the interface of the organic resin material film 111 will peel off due to internal stress caused by the heat applied to harden the light shielding member 14. lead to product defects. Peeling at the interface between material films in the photodetector 1 can be evaluated, for example, by a thermal cycle test (TCC) in which thermal stress is repeatedly applied.
  • TCC thermal cycle test
  • the coverage ratio of the light shielding member 14 is preferably greater than 0 and 1/2 or less, more preferably greater than 0 and 1/3 or less.
  • the covering rate of the light shielding member 14 is adjusted by the coating amount of the light shielding member 14 and the layout of the space region S formed on the semiconductor substrate 10. That is, the space region S depends on the processing area of the flattening film 111a and the on-chip lens 111c, which are removed by a photolithography process after the color filter 111b material on the semiconductor substrate 10 is applied, and which are subjected to a dry etching process. .
  • the surface of the logic chip 12 is covered.
  • the occurrence of flare due to reflected light entering the pixel array section 11 can be suppressed, and peeling of the interface between material films due to thermal stress can be prevented.
  • the region to be shaded in the logic chip 12 is covered by the light blocking member 14, but this does not mean that the entire logic chip 12 is covered by the light blocking member 14. Further, a portion of the logic chip 12 other than the light-shielding target area may be covered with another light-shielding member (for example, a tape-shaped light-shielding member).
  • FIGS. 4 to 6 are partial cross-sectional views for explaining an example of a method of forming a light shielding member on a semiconductor substrate in the manufacturing process of a photodetection device according to an embodiment of the present technology.
  • a semiconductor substrate 10 as shown in FIG. 4(a) is prepared.
  • the semiconductor substrate 10 has various semiconductor elements including photoelectric conversion elements PD arranged in an array formed by finely processing a semiconductor layer formed by epitaxial growth on a base substrate, and further includes a wiring pattern.
  • the wiring layer 101 including the wiring layer 101 is laminated.
  • the photoelectric conversion elements arranged in an array define an effective pixel area.
  • a pad electrode 17 connected to a wiring layer is formed on the front surface of the semiconductor substrate 10.
  • a silicon nitride film 102 for example, is formed on the semiconductor substrate 10, and a flattening film 111a is further formed by, for example, spin coating.
  • a color filter 111b containing one of RGB coloring materials is formed on the planarization film 111a of the semiconductor substrate 10 (FIG. 2(b)).
  • the color filter 111b is formed by, for example, applying the material for each pixel corresponding to RGB, and performing exposure and development processing using a photolithography process.
  • the color filter 111b is formed slightly beyond the effective pixel area in which the photoelectric conversion element is formed, and is also formed on the semiconductor substrate 10 in order to form a space area S in a step (see (e) in the same figure) described later. It is formed in accordance with the position where the organic resin material film 111 is to be removed.
  • a resin material for lenses is formed into a film on the semiconductor substrate 10, and processed into an on-chip lens 111c (FIG. 3(c)).
  • the organic resin material film 111 is formed on the semiconductor substrate 10, in which the planarizing film 111a, the color filter 111b, and the on-chip lens 111c are laminated in this order.
  • a groove-shaped dam portion 15 is formed outside the effective pixel area on the side where the logic chip 12 is placed, for example, by etching process (FIG. 4(d)).
  • the dam portions 15 are formed in two rows along the edge of the color filter 111b.
  • the organic resin material film 111 in the area where the logic chip 12 is mounted and the space area S on the semiconductor substrate 10 is removed, for example, by etching treatment or the like (FIG. 5(e)).
  • the pixel array section 11 on the semiconductor substrate 10 is defined.
  • the range in which the organic resin material film 111 is removed is such that the coverage ratio between the organic resin material film 111 and the light shielding member 14 on the edge of the pixel array section 11 is at most 1/2 or less. stipulated.
  • the silicon nitride film 102 is exposed in the removed region on the semiconductor substrate 10.
  • an oxide film 112 is formed at a low temperature on the semiconductor substrate 10 from which the organic resin material film 111 has been partially removed (see (f) in the same figure), and is further etched to expose the pad electrode 17. ((g) in the same figure).
  • the bump electrode 16 is formed on the pad electrode 17, and the logic chip 12 is further placed thereon (FIG. 6(h)).
  • the logic chip 12 is placed with its position adjusted according to the alignment mark.
  • an underfill member 18 is injected into the space between the semiconductor substrate 10 and the logic chip 12 via the bump electrodes 16 ((i) in the same figure). A part of the underfill member 18 that protrudes from the space may enter the space region S. Thereby, the wiring such as the bump electrodes 16 is protected, and the logic chip 12 is fixed on the semiconductor substrate 10.
  • a light shielding member 14 is formed on the semiconductor substrate 10 (FIG. 6(j)). More specifically, the light shielding member 14 is coated on the logic chip 12 so as to cover the light shielding target area of the logic chip 12, and thereby a part of the light shielding member 14 coated on the light shielding target area of the logic chip 12 is coated.
  • the bottom portion (bottom portion) flows beyond the space region S to the edge of the organic resin material film 111.
  • the light shielding member 14 that has flowed into the edge of the organic resin material film 111 is blocked by a dam portion 15 in front of the effective pixel area where the photoelectric conversion element is formed.
  • the applied light shielding member 14 is heated and hardened, for example.
  • the light-shielding member 14 applied to the light-shielding target region of the logic chip 12 placed on the pixel array section 11 with the space region interposed therebetween covers the space region S from which the organic resin material film 111 has been removed. It is formed so as to cover the edges of the organic resin material film 111 of the pixel array section 11. This prevents flare from occurring due to light reflected from the surface of the logic chip 12 entering the pixel array section 11. Furthermore, since the amount of overlap between the organic resin material film 111 and the light shielding member 14 is greater than 0 and 1/2 or less, peeling of the interface between the material films due to thermal stress can be prevented.
  • the space region S is laid out so as to be formed between the pixel array section 11 and the logic chip 12, but the layout is not limited to this. Various layouts can be made depending on the area to which the logic chips 14 are applied and/or the number and arrangement of the logic chips 12.
  • FIG. 7 is a plan view showing a first modified example of the schematic configuration of a photodetection device according to an embodiment of the present technology.
  • the photodetecting device 1 shown in the figure includes two logic chips 12 facing a pixel array section 11. Also in such a photodetecting device 1, a space region S can be formed between the pixel array section 11 and each logic chip 12.
  • FIG. 8 is a plan view showing a second modified example of the schematic configuration of the photodetection device according to an embodiment of the present technology.
  • the space region S includes not only the first side surface portion 12a of the logic chip 12 facing the pixel array section 11 but also the second side surface portion orthogonal to the first side surface portion 12a. It is formed to include a region corresponding to 12c. That is, since the light shielding member 14 is applied to the first side surface portion 12a and the second side surface portion 12c from above the logic chip 12, the space region S is designed to include a region corresponding to the second side surface portion. laid out to form. In this way, by removing the organic resin material film 111 from the region corresponding to the second side surface portion 12c, the occurrence of delamination at the interface due to thermal stress in the region where the light shielding member 14 is formed is prevented. Ru.
  • FIG. 9 shows a third modification in which the layout of the space region S shown in FIG. 8 is applied to two logic chips 12. That is, the space region S is formed to include, in addition to the first side surface portion 12a of each logic chip 12, a region corresponding to the second side surface portion 12c orthogonal to the first side surface portion 12a.
  • FIG. 10 is a plan view showing a fourth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology.
  • the photodetector 1 shown in the figure includes four logic chips 12 facing a pixel array section 11.
  • space regions S are also continuously formed in regions between adjacent logic chips 12.
  • FIG. 11 is a plan view showing a fifth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology.
  • the photodetecting device 1 shown in the figure is formed to include a region portion 12c' corresponding to the outer side surface of the second side surface portion 12c of each logic chip 12.
  • the organic resin material film 111 is removed from the light shielding member 14 applied to the light shielding target area of the logic chip 12 mounted on the pixel array section 11 with a space region in between. It is formed so as to cover the edge of the organic resin material film 111 of the pixel array section 11 beyond the space region S that has been formed. This prevents flare from occurring due to light reflected from the surface of the logic chip 12 entering the pixel array section 11. Furthermore, since the amount of overlap between the organic resin material film 111 and the light shielding member 14 is greater than 0 and 1/2 or less, peeling of the interface between the material films due to thermal stress can be prevented.
  • steps, acts, or functions may be performed in parallel or in a different order unless the results are inconsistent.
  • the steps, acts, and functions described are provided by way of example only, and some of the steps, acts, and functions may be omitted or combined with each other without departing from the spirit of the art. It is also possible to add other steps, actions, or functions.
  • the present technology may be configured to include the following technical matters.
  • a semiconductor substrate including a pixel array section in which a plurality of photoelectric conversion elements are arranged in an array; at least one logic chip placed on the semiconductor substrate with a space region between the pixel array section and the pixel array section; a light-shielding member formed to at least cover a light-shielding target region of the logic chip proximal to the pixel array section;
  • the pixel array section includes at least one organic resin material film formed on the light receiving surface of the plurality of photoelectric conversion elements,
  • the light shielding member is formed to cover from the light shielding target region of the logic chip to an edge of the organic resin material film formed on the pixel array section beyond the space region. Photodetection device.
  • the light-shielding target region includes a first side portion of the logic chip proximal to the space region.
  • the light-shielding target region further includes an upper edge portion of the logic chip proximal to the space region.
  • the light-shielding target area is at least a portion of a second side surface perpendicular to the first side surface that is proximal to the space area.
  • the space region formed on the semiconductor substrate is a region from which the organic resin material film is removed.
  • the space region is covered with a silicon nitride film;
  • the surface of the space region includes an uneven portion.
  • the organic resin material film includes at least one of a color filter and an on-chip lens.
  • the photodetection device according to any one of (1) to (7) above. (9) At least one dam portion formed along the edge of the organic resin material film formed on the pixel array portion for damming the inflow of the light shielding member;
  • the light shielding member is made of a resin material having a lower reflectance than the light reflectance of the surface of the logic chip.
  • the photodetector according to any one of (1) to (9) above.
  • the logic chip is placed on the semiconductor substrate via bump electrodes, and is fixed by an underfill member injected between the semiconductor substrate and the logic chip.
  • the photodetection device according to any one of (1) to (10) above.
  • (12) The light detection device according to (10), wherein the light shielding member covers the underfill member protruding into the space area.
  • (12) The organic resin material film with respect to the width of the light shielding member from one end of the space region on the light shielding target area side of the logic chip to the bottom portion of the light shielding member that covers the edge on the organic resin material film.
  • the width ratio of the light shielding member covering the upper edge is greater than 0 and less than or equal to 1/2,
  • the photodetection device according to any one of (1) to (12) above.
  • Photodetection device 10 Semiconductor substrate 101... Wiring layer 102... Silicon nitride film 11... Pixel array section 111... Organic resin material film 111a... Flattening film 111b... Color filter 111c... On-chip lens 112... Oxide film 12... Logic chip 12a...First side surface portion 12b...Top surface portion 12c...Second side surface portion 13...External pad electrode 14...Light shielding member 15...Dam portion 16...Bump electrode 17...Pad electrode 18...Underfill member S...Space area

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Abstract

The present technology provides a light detection device comprising: a semiconductor substrate including a pixel array in which a plurality of photoelectric conversion elements are arranged in an array; at least one logic chip that is disposed on the semiconductor substrate, and that is separated by a space region from the pixel array; and a light blocking member that is formed so as to at least cover a light blocking target region of the logic chip near the pixel array. The pixel array includes at least one organic resin material film that is formed on light-receiving surfaces of the plurality of photoelectric conversion elements. Further, the light blocking member is formed so as to cover from the light blocking target region of the logic chip, past the space region, and up to the edge of the organic resin material film formed on the pixel array.

Description

光検出装置light detection device
　本技術は、光検出装置に関し、特に、入射した光に応じた電気信号に変換する画素アレイを備える光検出装置に関する。 The present technology relates to a photodetection device, and particularly relates to a photodetection device including a pixel array that converts incident light into an electrical signal according to the incident light.
　複数のＩＣチップ（シリコンダイ）を１つの半導体基板上に設けてパッケージ化したマルチチップ構造の半導体デバイスが知られている。例えば、複数のＩＣチップをシリコンウェハ上に積層して形成した後、ダイシングによりチップ化し、更にそれをパッケージ化することにより製造された半導体デバイスはＣＯＷ（Chip on Wafer）と呼ばれる。ＣＯＷ型の光検出装置は、アレイ状の光電変換素子からなる画素アレイが形成された半導体基板上に、例えば１つ以上のロジック回路を形成したロジックチップが画素アレイに近接して並置されるように構成されている。 A semiconductor device with a multi-chip structure in which a plurality of IC chips (silicon dies) are provided and packaged on one semiconductor substrate is known. For example, a semiconductor device manufactured by stacking a plurality of IC chips on a silicon wafer, dicing them into chips, and packaging the chips is called a COW (Chip on Wafer). A COW type photodetecting device is a semiconductor substrate on which a pixel array consisting of an array of photoelectric conversion elements is formed, and a logic chip having one or more logic circuits formed thereon is arranged in close proximity to the pixel array. It is composed of
　画素アレイとロジックチップとが並置された構造を有する光検出装置では、画素アレイによる受光の際、画素アレイ側のロジックチップの側面で反射した光が画素アレイの受光面に入り込み、この結果、画像にフレア等が発生してしまうため、ロジックチップの上面及び側面といった遮光対象領域は、遮光性の樹脂材料部材（遮光部材）で覆われる。 In a photodetector having a structure in which a pixel array and a logic chip are arranged side by side, when the pixel array receives light, the light reflected from the side surface of the logic chip on the pixel array side enters the light receiving surface of the pixel array, and as a result, the image Since flare and the like occur in the semiconductor device, the regions to be light-shielded, such as the top and side surfaces of the logic chip, are covered with a light-shielding resin material member (light-shielding member).
　例えば、下記特許文献１は、複数の画素が配置された画素領域を有する基板と、前記基板に接続端子を介してフリップチップ接合された１以上のチップとを備え、前記チップの裏面を保護する第１の樹脂材料と、前記チップの側面を保護する第２の樹脂材料とを含む、半導体装置を開示している。 For example, Patent Document 1 below includes a substrate having a pixel area in which a plurality of pixels are arranged, and one or more chips flip-chip bonded to the substrate via connection terminals, and protects the back surface of the chip. A semiconductor device is disclosed that includes a first resin material and a second resin material that protects the side surface of the chip.
　このような光検出装置は、例えばカメラ等の撮像デバイスに広く利用されている。カラー画像に対応した光検出装置は、各光電変換素子がＲＧＢ（Red, Green, Blue）いずれかの色の光のみを受光するように、各光電変換素子の受光面上に層状形成されたカラーフィルタを備えている。また、光検出装置は、外部からの光を効果的に光電変換素子に結合することができるよう、カラーフィルタ上にオンチップレンズを備えている。 Such photodetection devices are widely used, for example, in imaging devices such as cameras. A photodetector that supports color images has a color sensor layered on the light-receiving surface of each photoelectric conversion element so that each photoelectric conversion element receives only RGB (Red, Green, Blue) color light. Equipped with a filter. Further, the photodetector includes an on-chip lens on the color filter so that external light can be effectively coupled to the photoelectric conversion element.
ＷＯ２０２２／０５０１１９号公報WO2022/050119 publication
　光検出装置に熱ストレスが加わると、半導体基板及びその上に形成された各種の材料膜に熱応力が働き、材料膜間の線膨張係数の違いから、密着性が低い材料膜の界面で剥離が生じ易い。とりわけ、光検出装置に用いられるカラーフィルタやオンチップレンズは有機系樹脂材料膜からなるため密着性が比較的低く、接触している遮光部材等との線膨張係数の違いによって、これらの界面を起点として剥離が発生し、製品不良を来すおそれがあった。 When thermal stress is applied to the photodetector, the thermal stress acts on the semiconductor substrate and the various material films formed on it, and due to the difference in linear expansion coefficient between the material films, separation occurs at the interface of the material films with low adhesion. is likely to occur. In particular, since the color filters and on-chip lenses used in photodetection devices are made of organic resin material films, their adhesion is relatively low, and due to the difference in linear expansion coefficient between them and the light-shielding material they are in contact with, these interfaces may be damaged. There was a risk that peeling would occur as a starting point, resulting in product defects.
　一方で、上記のような剥離の発生を抑制するために、ロジックチップを覆う遮光部材をロジックチップに並置された画素アレイの縁部にまで延伸させない場合、ロジックチップと画素アレイとの間に露出部分（例えば、無機系酸化膜）が残り、該露出部分での光の反射によりフレア等が発生するという問題がある。 On the other hand, in order to suppress the occurrence of peeling as described above, if the light shielding member covering the logic chip is not extended to the edge of the pixel array juxtaposed to the logic chip, the exposed area between the logic chip and the pixel array may be There is a problem in that a portion (for example, an inorganic oxide film) remains, and flare etc. occur due to reflection of light at the exposed portion.
　そこで、本開示は、光検出装置において、画素アレイに対するロジックチップからの反射光を効果的に抑止しつつ、半導体基板上に形成された各種の材料膜どうしの界面での剥離を効果的に抑制する技術を提供する。 Therefore, the present disclosure provides a photodetection device that effectively suppresses reflected light from a logic chip to a pixel array, and also effectively suppresses peeling at the interface between various material films formed on a semiconductor substrate. We provide technology to
　上記課題を解決するための本技術は、以下に示す発明特定事項又は技術的特徴を含んで構成される。 The present technology for solving the above problems is configured to include the following invention specific matters or technical features.
　ある観点に従う本技術は、複数の光電変換素子がアレイ状に配列された画素アレイ部を含む半導体基板と、前記半導体基板上に、前記画素アレイ部とスペース領域を隔てて載置された少なくとも１つのロジックチップと、前記画素アレイ部に近位する前記ロジックチップの遮光対象領域を少なくとも覆うように形成された遮光部材とを備える光検出装置である。前記画素アレイ部は、前記複数の光電変換素子の受光面上に形成された少なくとも１つの有機系樹脂材料膜を含む。また、前記遮光部材は、前記ロジックチップの前記遮光対象領域から前記スペース領域を超えて前記画素アレイ部上に形成された前記有機系樹脂材料膜の縁部まで覆うように形成されている。 The present technology according to a certain aspect includes a semiconductor substrate including a pixel array section in which a plurality of photoelectric conversion elements are arranged in an array, and at least one semiconductor substrate placed on the semiconductor substrate with a space region apart from the pixel array section. The light detection device includes a logic chip, and a light shielding member formed to cover at least a light shielding target region of the logic chip that is proximal to the pixel array section. The pixel array section includes at least one organic resin material film formed on the light receiving surface of the plurality of photoelectric conversion elements. Further, the light shielding member is formed to cover from the light shielding target region of the logic chip to an edge of the organic resin material film formed on the pixel array portion beyond the space region.
　ここで、前記ロジックチップの前記遮光対象領域側の前記スペース領域の一端部から前記有機系樹脂材料膜上の前記縁部を覆う前記遮光部材の裾部分までの前記遮光部材の幅に対する前記有機系樹脂材料膜上の前記縁部を覆う前記遮光部材の幅の比は、０より大きく１／２以下であることが好ましい。 Here, the organic resin material with respect to the width of the light shielding member from one end of the space region on the light shielding target region side of the logic chip to the hem portion of the light shielding member that covers the edge on the organic resin material film. It is preferable that a width ratio of the light shielding member covering the edge on the resin material film is greater than 0 and less than or equal to 1/2.
　なお、本明細書等において、手段とは、単に物理的手段を意味するものではなく、その手段が有する機能をソフトウェアによって実現する場合も含む。また、１つの手段が有する機能が２つ以上の物理的手段により実現されても、２つ以上の手段の機能が１つの物理的手段により実現されても良い。また、「システム」とは、複数の装置（又は特定の機能を実現する機能モジュール）が論理的に集合した物のことをいい、各装置や機能モジュールが単一の筐体内にあるか否かは特に問わない。 Note that in this specification and the like, the term "means" does not simply mean physical means, but also includes cases in which the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means. In addition, a "system" refers to a logical collection of multiple devices (or functional modules that realize a specific function), and whether each device or functional module is in a single housing or not. There is no particular question.
　本技術の他の技術的特徴、目的、及び作用効果乃至は利点は、添付した図面を参照して説明される以下の実施形態により明らかにされる。本明細書に記載された効果はあくまで例示であって限定されるものではなく、また他の効果があっても良い。 Other technical features, objects, effects, and advantages of the present technology will be made clear by the following embodiments described with reference to the attached drawings. The effects described in this specification are merely examples and are not limiting, and other effects may also be present.
図１は、本技術の一実施形態に係る光検出装置の概略的構成の一例を示す平面図である。FIG. 1 is a plan view showing an example of a schematic configuration of a photodetecting device according to an embodiment of the present technology. 図２は、本技術の一実施形態に係る光検出装置の要部の概略的構成の一例を示す部分断面図である。FIG. 2 is a partial cross-sectional view illustrating an example of a schematic configuration of main parts of a photodetection device according to an embodiment of the present technology. 図３は、本技術の一実施形態に係る光検出装置における有機系樹脂材料膜と遮光部材との被り量を説明するための図である。FIG. 3 is a diagram for explaining the amount of overlap between an organic resin material film and a light shielding member in a photodetector according to an embodiment of the present technology. 図４は、本技術の一実施形態に係る光検出装置の製造工程における半導体基板上の遮光部材の形成方法の一例を説明するための部分断面図である。FIG. 4 is a partial cross-sectional view for explaining an example of a method for forming a light shielding member on a semiconductor substrate in a manufacturing process of a photodetector according to an embodiment of the present technology. 図５は、本技術の一実施形態に係る光検出装置の製造工程における半導体基板上の遮光部材の形成方法の一例を説明するための部分断面図である。FIG. 5 is a partial cross-sectional view for explaining an example of a method for forming a light shielding member on a semiconductor substrate in a manufacturing process of a photodetector according to an embodiment of the present technology. 図６は、本技術の一実施形態に係る光検出装置の製造工程における半導体基板上の遮光部材の形成方法の一例を説明するための部分断面図である。FIG. 6 is a partial cross-sectional view for explaining an example of a method for forming a light shielding member on a semiconductor substrate in a manufacturing process of a photodetection device according to an embodiment of the present technology. 図７は、本技術の一実施形態に係る光検出装置の概略的構成の第１の変形例を示す平面図である。FIG. 7 is a plan view showing a first modified example of the schematic configuration of the photodetecting device according to an embodiment of the present technology. 図８は、本技術の一実施形態に係る光検出装置の概略的構成の第２の変形例を示す平面図である。FIG. 8 is a plan view showing a second modified example of the schematic configuration of the photodetecting device according to an embodiment of the present technology. 図９は、本技術の一実施形態に係る光検出装置の概略的構成の第３の変形例を示す平面図である。FIG. 9 is a plan view showing a third modified example of the schematic configuration of the photodetection device according to an embodiment of the present technology. 図１０は、本技術の一実施形態に係る光検出装置の概略的構成の第４の変形例を示す平面図である。FIG. 10 is a plan view showing a fourth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology. 図１１は、本技術の一実施形態に係る光検出装置の概略的構成の第５の変形例を示す平面図である。FIG. 11 is a plan view showing a fifth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology.
　以下、図面を参照して本技術の実施の形態を説明する。ただし、以下に説明する実施形態は、あくまでも例示であり、以下に明示しない種々の変形や技術の適用を排除する意図はない。本技術は、その趣旨を逸脱しない範囲で種々変形（例えば各実施形態を組み合わせる等）して実施することができる。また、以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付して表している。図面は模式的なものであり、必ずしも実際の寸法や比率等とは一致しない。図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることがある。 Hereinafter, embodiments of the present technology will be described with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention to exclude the application of various modifications and techniques not specified below. The present technology can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the technology. In addition, in the description of the drawings below, the same or similar parts are denoted by the same or similar symbols. The drawings are schematic and do not necessarily correspond to actual dimensions or proportions. The drawings may also include portions that differ in dimensional relationships and ratios.
　図１は、本技術の一実施形態に係る光検出装置の概略的構成の一例を示す図である。また、図２は、図１に示す光検出装置の要部の部分断面図である。 FIG. 1 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an embodiment of the present technology. Further, FIG. 2 is a partial cross-sectional view of a main part of the photodetecting device shown in FIG.
　図１に示すように、光検出装置１は、画素を構成する複数の光電変換素子がアレイ状に配列された画素アレイ部１１が形成された半導体基板１０と、半導体基板１０上に画素アレイ部１１に隣接して載置されたロジックチップ１２とを含み構成される。光電変換素子（符号なし）は、入射した光に応じて蓄積される電荷に基づいて電気信号を出力する半導体素子である。光電変換素子は、画素アレイ部１１の有効画素領域を規定する。 As shown in FIG. 1, the photodetecting device 1 includes a semiconductor substrate 10 on which a pixel array section 11 in which a plurality of photoelectric conversion elements constituting pixels are arranged in an array is formed, and a pixel array section on the semiconductor substrate 10. 11 and a logic chip 12 placed adjacent to the logic chip 11. A photoelectric conversion element (no code) is a semiconductor element that outputs an electrical signal based on charges accumulated in response to incident light. The photoelectric conversion element defines an effective pixel area of the pixel array section 11.
　半導体基板１０は、配線パターンが形成された配線層（図示せず）を含む。ロジックチップ１２は、半導体基板１０内に形成された配線層を介して画素アレイ部１１に電気的に接続され、画素アレイ部１１から出力される電気信号を処理するロジック回路を含むシリコンダイである。本例では、１つのロジックチップ１２が、画素アレイ部１１に隣接して配置された構成が示されているが、これに限られず、変形例で示されるように、複数のロジックチップ１２が、画素アレイ部１１の周囲に複数配置された構成であっても良い。なお、本開示では、光検出装置１は、裏面照射型のＣＭＯＳイメージセンサであるものとするが、これに限られず、例えば、表面照射型のＣＭＯＳイメージセンサであっても良い。 The semiconductor substrate 10 includes a wiring layer (not shown) on which a wiring pattern is formed. The logic chip 12 is a silicon die that is electrically connected to the pixel array section 11 via a wiring layer formed in the semiconductor substrate 10 and includes a logic circuit that processes electrical signals output from the pixel array section 11. . Although this example shows a configuration in which one logic chip 12 is arranged adjacent to the pixel array section 11, the configuration is not limited to this, and as shown in a modified example, a plurality of logic chips 12 A configuration in which a plurality of pixels are arranged around the pixel array section 11 may be used. Note that in the present disclosure, the photodetection device 1 is assumed to be a back-illuminated CMOS image sensor, but is not limited thereto, and may be, for example, a front-illuminated CMOS image sensor.
　また、半導体基板１０の外周部には、複数の外部パッド電極１３が形成されている。外部パッド電極１３は、例えば、半導体テストのためのプローブの接触やワイヤーボンディングによるワイヤーの接続に利用される（図示せず）。 Furthermore, a plurality of external pad electrodes 13 are formed on the outer periphery of the semiconductor substrate 10. The external pad electrode 13 is used, for example, to contact a probe for semiconductor testing or to connect a wire by wire bonding (not shown).
　図２を参照して、画素アレイ部１１を構成する光電変換素子の受光面上には、平坦化膜１１１ａが形成され、その上にカラーフィルタ１１１ｂ及びオンチップレンズ１１１ｃが順に積層され、更に、酸化膜１１２が積層される。平坦化膜１１１ａ、カラーフィルタ１１１ｂ、及びオンチップレンズ１１１ｃは、典型的には、有機系樹脂材料からなる。本開示では、便宜上、有機系樹脂材料からなる平坦化膜１１１ａ、カラーフィルタ１１１ｂ、及び／又はオンチップレンズ１１１ｃを有機系樹脂材料膜１１１と称することがある。 Referring to FIG. 2, a flattening film 111a is formed on the light receiving surface of the photoelectric conversion element constituting the pixel array section 11, a color filter 111b and an on-chip lens 111c are sequentially laminated thereon, and further, An oxide film 112 is laminated. The flattening film 111a, the color filter 111b, and the on-chip lens 111c are typically made of an organic resin material. In this disclosure, for convenience, the flattening film 111a, the color filter 111b, and/or the on-chip lens 111c made of an organic resin material may be referred to as an organic resin material film 111.
　画素アレイ部１１上に積層形成される有機系樹脂材料膜１１１及び酸化膜１１２は、光検出装置１の製造工程上、典型的には、光電変換素子による有効画素領域を超えて形成される。後述するように、有機系樹脂材料膜１１１が積層形成されたロジックチップ１２に近い画素アレイ部１１の縁部は、ロジックチップ１２の遮光対象領域を覆うように形成された遮光部材１４により連続的に覆われている。遮光対象領域は、ロジックチップ１２の表面で反射した光が画素アレイ部１１へ入り込むおそれがある領域である。有機系樹脂材料膜１１１等の縁部には、複数のダム部１５が溝状に形成されている（本例では２列）。ダム部１５は、遮光部材１４や後述するアンダーフィル部材１８の余剰分が有効画素領域まで到達しないようにこれらを堰き止める。なお、本例では、ダム部１５は２列の溝として示されたが、これに限られず、ロジックチップ１２を囲むように形成されても良い。 The organic resin material film 111 and oxide film 112 that are laminated on the pixel array section 11 are typically formed beyond the effective pixel area of the photoelectric conversion element due to the manufacturing process of the photodetector 1. As will be described later, the edge of the pixel array section 11 near the logic chip 12 on which the organic resin material film 111 is layered is continuous with the light shielding member 14 formed to cover the light shielding target area of the logic chip 12. covered in. The light shielding target area is an area where light reflected from the surface of the logic chip 12 may enter the pixel array section 11. A plurality of dam portions 15 are formed in the shape of grooves at the edges of the organic resin material film 111 and the like (two rows in this example). The dam part 15 dams up the light shielding member 14 and the underfill member 18 described below so that the excess does not reach the effective pixel area. In this example, the dam portion 15 is shown as two rows of grooves, but is not limited to this, and may be formed so as to surround the logic chip 12.
　画素アレイ部１１とロジックチップ１２とはスペース領域Ｓを隔てて並置されている。スペース領域Ｓは、有機系樹脂材料膜１１１が形成されていない領域である（酸化膜１１２は形成されていても良い。）。より具体的には、光検出装置１の製造工程において、カラーフィルタ１１１ｂ及びオンチップレンズ１１１ｃといった有機系樹脂材料膜１１１は、半導体基板１０の表面全体に亘って形成された後、ロジックチップ１２が載置される領域とともに画素アレイ部１１とロジックチップ１２との間の領域がエッチング処理等により除去される。その後、ロジックチップ１２がバンプ電極１６を介して載置されることにより、スペース領域Ｓが画定される。スペース領域Ｓの表面形状は、平坦形状であっても良いし、ランダム又は幾何学的な凹凸形状であっても良い。 The pixel array section 11 and the logic chip 12 are arranged side by side with a space region S in between. The space region S is a region where the organic resin material film 111 is not formed (the oxide film 112 may be formed). More specifically, in the manufacturing process of the photodetector 1, the organic resin material film 111 such as the color filter 111b and the on-chip lens 111c is formed over the entire surface of the semiconductor substrate 10, and then the logic chip 12 is The area between the pixel array section 11 and the logic chip 12 as well as the area to be placed are removed by etching or the like. Thereafter, a space region S is defined by placing the logic chip 12 through the bump electrodes 16. The surface shape of the space region S may be flat, or may be random or geometrically uneven.
　ロジックチップ１２は、半導体基板１０上に形成されたパッド電極１７にバンプ電極１６を介して電気的に接続されるように載置される。ロジックチップ１２は、例えばフリップチップ実装により載置される。半導体基板１０とロジックチップ１２との間の空間には、アンダーフィル部材１８が注入され、これにより、バンプ電極１６等の配線が保護されるとともに、ロジックチップ１２は、半導体基板１０に固定される。ロジックチップ１２の周囲にはみ出たアンダーフィル部材１８は、遮光部材１４に覆われる。 The logic chip 12 is placed so as to be electrically connected to pad electrodes 17 formed on the semiconductor substrate 10 via bump electrodes 16. The logic chip 12 is mounted, for example, by flip-chip mounting. An underfill member 18 is injected into the space between the semiconductor substrate 10 and the logic chip 12, thereby protecting the wiring such as the bump electrodes 16 and fixing the logic chip 12 to the semiconductor substrate 10. . The underfill member 18 protruding around the logic chip 12 is covered with the light shielding member 14.
　また、画素アレイ部１１に近位するロジックチップ１２の遮光対象領域は、遮光部材１４によって覆われる。遮光対象領域は、ロジックチップ１２の表面で反射した光が画素アレイ部１１へ入り込むおそれがある領域であり、例えば、画素アレイ部１１に対向するロジックチップ１２の側面部分１２ａ（第１の側面部分）である。また、遮光対象領域は、ロジックチップ１２の上面部分１２ｂであり得る。更に、遮光対象領域は、該側面部分１２ａの両端の角部及び該側面部分１２ａに直交する他の側面部分１２ｃ（第２の側面部分）であり得る。 Furthermore, the light-shielding target region of the logic chip 12 that is close to the pixel array section 11 is covered by the light-shielding member 14 . The light shielding target area is an area where light reflected on the surface of the logic chip 12 may enter the pixel array section 11. ). Further, the region to be shaded may be the upper surface portion 12b of the logic chip 12. Furthermore, the light shielding target area may be the corner portions at both ends of the side surface portion 12a and another side surface portion 12c (second side surface portion) orthogonal to the side surface portion 12a.
　遮光部材１４は、例えば熱硬化型のエポキシ樹脂材料や酸化シリコーン樹脂材料からなる。遮光部材１４の硬化のために加えられる熱によって、熱膨張係数の違いから有機系樹脂材料膜１１１の界面での剥離が生じるおそれがある。したがって、後述するように、有機系樹脂材料膜１１１に対する遮光部材１４の被り率を調整し、有機系樹脂材料膜１１１の界面での剥離の抑制を図っている。遮光部材１４は、画素アレイ部１１への反射光の入り込みを防止するため、ロジックチップ１２の反射率よりも低い反射率となるように構成される。例えば、遮光部材１４は、カーボンブラック等の光吸収材を含有する。追加的に又は代替的に、遮光部材１４は、反射光が拡散し得るように光拡散材を含有しても良いし、その表面が凹凸形状に形成されても良い。 The light shielding member 14 is made of, for example, a thermosetting epoxy resin material or a silicon oxide resin material. The heat applied for curing the light shielding member 14 may cause peeling of the organic resin material film 111 at the interface due to the difference in thermal expansion coefficients. Therefore, as will be described later, the covering ratio of the light shielding member 14 to the organic resin material film 111 is adjusted to suppress peeling of the organic resin material film 111 at the interface. The light shielding member 14 is configured to have a reflectance lower than that of the logic chip 12 in order to prevent reflected light from entering the pixel array section 11 . For example, the light shielding member 14 contains a light absorbing material such as carbon black. Additionally or alternatively, the light shielding member 14 may contain a light diffusing material so that reflected light can be diffused, or its surface may be formed into an uneven shape.
　遮光部材１４は、光検出装置１の製造工程において、例えば、ロジックチップ１２が半導体基板１０に載置されてアンダーフィル部材１８により固定された後、半導体基板１０の上方から塗布される。遮光部材１４の塗布は、１回の工程で又は複数の工程に分けて行われる。塗布された遮光部材１４は、ロジックチップ１２の遮光対象領域を覆うとともに、スペース領域Ｓを覆って更にその先端が画素アレイ部１１の縁部まで達する。画素アレイ部１１の縁部に到達した遮光部材１４のうち余剰分は、縁部に形成されたダム部１５によって堰き止められる。画素アレイ部１１の縁部上にまで到達した遮光部材１４の裾部分の幅が有機系樹脂材料膜１１１との被り量となる。なお、遮光部材１４がスペース領域Ｓを覆っていない場合、つまり、遮光部材１４の裾部分が画素アレイ部１１の縁部まで達せずにスペース領域Ｓが露出した状態であると、露出した部分で反射した光が画素アレイ部１１に入り込むおそれがある。一方で、遮光部材１４と有機系樹脂材料膜１１１との被り量が大きすぎると、熱ストレスが加わった場合に熱応力によって界面での剥離が生じ易くなる。そこで、本開示では、遮光部材１４の裾部分は、画素アレイ部１１の縁部にまで確実に到達し、適度な被り量で有機系樹脂材料膜１１１を覆っていることが要求されることから、以下に述べるように被り率が定められる。 The light shielding member 14 is applied from above the semiconductor substrate 10 in the manufacturing process of the photodetector 1, for example, after the logic chip 12 is placed on the semiconductor substrate 10 and fixed by the underfill member 18. Application of the light shielding member 14 is performed in one step or in multiple steps. The applied light shielding member 14 covers the light shielding target region of the logic chip 12 and also covers the space region S, with its tip reaching the edge of the pixel array section 11. The surplus portion of the light shielding member 14 that has reached the edge of the pixel array section 11 is dammed up by a dam section 15 formed at the edge. The width of the bottom portion of the light shielding member 14 that has reached the edge of the pixel array section 11 is the amount of overlap with the organic resin material film 111. Note that when the light shielding member 14 does not cover the space region S, that is, when the bottom portion of the light shielding member 14 does not reach the edge of the pixel array section 11 and the space region S is exposed, the exposed portion There is a possibility that the reflected light may enter the pixel array section 11. On the other hand, if the amount of overlap between the light shielding member 14 and the organic resin material film 111 is too large, peeling at the interface is likely to occur due to thermal stress when thermal stress is applied. Therefore, in the present disclosure, the skirt portion of the light shielding member 14 is required to reach the edge of the pixel array portion 11 without fail and cover the organic resin material film 111 with an appropriate amount of covering. , the coverage rate is determined as described below.
　図３は、本技術の一実施形態に係る光検出装置における有機系樹脂材料膜と遮光部材との被り量を説明するための図である。同図に示すように、画素アレイ部１１の縁部での遮光部材１４の被り率は、遮光部材１４の全体幅Δに対する画素アレイ部１１の縁部上での遮光部材１４の裾部分の幅δ（被り量）の比で規定される。ここで、遮光部材１４の全体幅Δとは、ロジックチップ１２の遮光対象領域側のスペース領域Ｓの一端部から縁部を覆う遮光部材１４の裾部分までの幅である。 FIG. 3 is a diagram for explaining the amount of overlap between the organic resin material film and the light shielding member in the photodetector according to an embodiment of the present technology. As shown in the figure, the covering ratio of the light shielding member 14 at the edge of the pixel array section 11 is the width of the bottom portion of the light shielding member 14 on the edge of the pixel array section 11 relative to the overall width Δ of the light shielding member 14. It is defined by the ratio of δ (coverage amount). Here, the overall width Δ of the light shielding member 14 is the width from one end of the space region S on the light shielding target area side of the logic chip 12 to the hem portion of the light shielding member 14 that covers the edge.
　遮光部材１４に熱硬化型材料が用いられる場合、遮光部材１４の硬化のために加えられる熱によって生じる内部応力により有機系樹脂材料膜１１１での界面の剥離が生じるおそれがあり、光検出装置１の製品不良につながる。光検出装置１における材料膜間の界面の剥離は、例えば、熱ストレスを繰り返し加える温度サイクル試験（ＴＣＣ：Thermal Cycle Test）によって評価され得る。 When a thermosetting material is used for the light shielding member 14, there is a risk that the interface of the organic resin material film 111 will peel off due to internal stress caused by the heat applied to harden the light shielding member 14. lead to product defects. Peeling at the interface between material films in the photodetector 1 can be evaluated, for example, by a thermal cycle test (TCC) in which thermal stress is repeatedly applied.
　温度サイクル試験でのサンプルを評価したところ、遮光部材１４の被り率（δ／Δ）が約６０％を超えると、いくつかのサンプルで有機系樹脂材料膜１１１、とりわけ、上下層が有機系樹脂材料で挟まれたカラーフィルタ１１１ｂの界面での剥離が観測された。また、遮光部材１４の被り率が約２０％ではサンプルに界面の剥離は観測されなかった。 When the samples were evaluated in a temperature cycle test, it was found that when the coverage ratio (δ/Δ) of the light shielding member 14 exceeded about 60%, some samples showed that the organic resin material film 111, especially the upper and lower layers, were made of organic resin. Peeling was observed at the interface of the color filter 111b sandwiched between the materials. Further, when the covering rate of the light shielding member 14 was about 20%, no peeling at the interface was observed in the sample.
　したがって、遮光部材１４の被り率は、０より大きく１／２以下であることが好ましく、より好ましくは０より大きく１／３以下であることが好ましいと考えられる。このような遮光部材１４の被り率は、遮光部材１４の塗布量及び半導体基板１０上に形成されるスペース領域Ｓのレイアウトによって調整される。すなわち、スペース領域Ｓは、半導体基板１０上のカラーフィルタ１１１ｂ材料が塗布された後のフォトリソグラフィ工程による除去、並びにドライエッチング工程がなされる平坦化膜１１１ａ及びオンチップレンズ１１１ｃの加工領域に依存する。 Therefore, it is considered that the coverage ratio of the light shielding member 14 is preferably greater than 0 and 1/2 or less, more preferably greater than 0 and 1/3 or less. The covering rate of the light shielding member 14 is adjusted by the coating amount of the light shielding member 14 and the layout of the space region S formed on the semiconductor substrate 10. That is, the space region S depends on the processing area of the flattening film 111a and the on-chip lens 111c, which are removed by a photolithography process after the color filter 111b material on the semiconductor substrate 10 is applied, and which are subjected to a dry etching process. .
　以上のように、遮光部材１４がロジックチップ１２の遮光対象領域からスペース領域Ｓを超えて画素アレイ部１１の有機系樹脂材料膜１１１の縁部まで連続的に覆うことにより、ロジックチップ１２表面での反射光の画素アレイ部１１への入り込みによるフレアの発生を抑止するとともに、熱応力による材料膜間の界面の剥離を防止することができる。 As described above, by continuously covering the light shielding member 14 from the light shielding target area of the logic chip 12 over the space area S to the edge of the organic resin material film 111 of the pixel array section 11, the surface of the logic chip 12 is covered. The occurrence of flare due to reflected light entering the pixel array section 11 can be suppressed, and peeling of the interface between material films due to thermal stress can be prevented.
　なお、本例では、ロジックチップ１２における遮光対象領域は、遮光部材１４によって覆われるものとしたが、これは、ロジックチップ１２の全体が遮光部材１４によって覆われることを排除する趣旨ではない。また、ロジックチップ１２の遮光対象領域以外の部分が他の遮光部材（例えばテープ状の遮光部材）で覆われても良い。 Note that in this example, the region to be shaded in the logic chip 12 is covered by the light blocking member 14, but this does not mean that the entire logic chip 12 is covered by the light blocking member 14. Further, a portion of the logic chip 12 other than the light-shielding target area may be covered with another light-shielding member (for example, a tape-shaped light-shielding member).
　図４～図６は、本技術の一実施形態に係る光検出装置の製造工程における半導体基板上の遮光部材の形成方法の一例を説明するための部分断面図である。 4 to 6 are partial cross-sectional views for explaining an example of a method of forming a light shielding member on a semiconductor substrate in the manufacturing process of a photodetection device according to an embodiment of the present technology.
　まず、図４（ａ）に示すような半導体基板１０が準備される。半導体基板１０は、下地の基板上に例えばエピタキシャル成長により成膜された半導体層を微細加工することによりアレイ状に配列された光電変換素子ＰＤ等を含む各種の半導体素子が形成され、更に、配線パターンを含む配線層１０１が積層されて構成されている。アレイ状に配列された光電変換素子は、有効画素領域を確定する。半導体基板１０のおもて面には、配線層に接続されたパッド電極１７が形成されている。また、半導体基板１０上には、例えばシリコン窒化膜１０２が形成され、更に、例えばスピンコートにより平坦化膜１１１ａが形成される。 First, a semiconductor substrate 10 as shown in FIG. 4(a) is prepared. The semiconductor substrate 10 has various semiconductor elements including photoelectric conversion elements PD arranged in an array formed by finely processing a semiconductor layer formed by epitaxial growth on a base substrate, and further includes a wiring pattern. The wiring layer 101 including the wiring layer 101 is laminated. The photoelectric conversion elements arranged in an array define an effective pixel area. A pad electrode 17 connected to a wiring layer is formed on the front surface of the semiconductor substrate 10. Furthermore, a silicon nitride film 102, for example, is formed on the semiconductor substrate 10, and a flattening film 111a is further formed by, for example, spin coating.
　続いて、半導体基板１０の平坦化膜１１１ａ上には、ＲＧＢのいずれかの着色材を含有したカラーフィルタ１１１ｂが形成される（同図（ｂ））。カラーフィルタ１１１ｂは、例えば、ＲＧＢに対応した画素ごとにその材料が塗布されて、フォトリソグラフィ工程による露光及び現像処理により形成される。カラーフィルタ１１１ｂは、光電変換素子が形成された有効画素領域を僅かに超えて形成されるとともに、後述する工程（同図（ｅ）参照）によりスペース領域Ｓを形成するために半導体基板１０上の有機系樹脂材料膜１１１が除去される位置に合わせて形成される。 Subsequently, a color filter 111b containing one of RGB coloring materials is formed on the planarization film 111a of the semiconductor substrate 10 (FIG. 2(b)). The color filter 111b is formed by, for example, applying the material for each pixel corresponding to RGB, and performing exposure and development processing using a photolithography process. The color filter 111b is formed slightly beyond the effective pixel area in which the photoelectric conversion element is formed, and is also formed on the semiconductor substrate 10 in order to form a space area S in a step (see (e) in the same figure) described later. It is formed in accordance with the position where the organic resin material film 111 is to be removed.
　次に、半導体基板１０上にはレンズ用樹脂材料が成膜され、オンチップレンズ１１１ｃに加工される（同図（ｃ））。このように、半導体基板１０上には、平坦化膜１１１ａ、カラーフィルタ１１１ｂ、及びオンチップレンズ１１１ｃが順に積層された有機系樹脂材料膜１１１が形成される。 Next, a resin material for lenses is formed into a film on the semiconductor substrate 10, and processed into an on-chip lens 111c (FIG. 3(c)). In this way, the organic resin material film 111 is formed on the semiconductor substrate 10, in which the planarizing film 111a, the color filter 111b, and the on-chip lens 111c are laminated in this order.
　続いて、ロジックチップ１２が載置される側の有効画素領域の外側に、例えばエッチング処理により溝状のダム部１５が形成される（同図（ｄ））。本例では、ダム部１５は、カラーフィルタ１１１ｂの縁部に沿って２列に形成されている。 Subsequently, a groove-shaped dam portion 15 is formed outside the effective pixel area on the side where the logic chip 12 is placed, for example, by etching process (FIG. 4(d)). In this example, the dam portions 15 are formed in two rows along the edge of the color filter 111b.
　続いて、半導体基板１０上の、ロジックチップ１２が載置される領域及びスペース領域Ｓの有機系樹脂材料膜１１１が、例えばエッチング処理等により除去される（図５（ｅ））。これにより、半導体基板１０上の画素アレイ部１１が画定される。なお、有機系樹脂材料膜１１１が除去される範囲は、画素アレイ部１１の縁部上での有機系樹脂材料膜１１１と遮光部材１４との被り率が最大で１／２以下となるように規定される。半導体基板１０上の除去された領域は、シリコン窒化膜１０２が露出する。 Subsequently, the organic resin material film 111 in the area where the logic chip 12 is mounted and the space area S on the semiconductor substrate 10 is removed, for example, by etching treatment or the like (FIG. 5(e)). Thereby, the pixel array section 11 on the semiconductor substrate 10 is defined. Note that the range in which the organic resin material film 111 is removed is such that the coverage ratio between the organic resin material film 111 and the light shielding member 14 on the edge of the pixel array section 11 is at most 1/2 or less. stipulated. The silicon nitride film 102 is exposed in the removed region on the semiconductor substrate 10.
　続いて、有機系樹脂材料膜１１１が部分的に除去された半導体基板１０上に酸化膜１１２が低温成膜され（同図（ｆ））、更に、パッド電極１７が露出するようにエッチング処理される（同図（ｇ））。 Subsequently, an oxide film 112 is formed at a low temperature on the semiconductor substrate 10 from which the organic resin material film 111 has been partially removed (see (f) in the same figure), and is further etched to expose the pad electrode 17. ((g) in the same figure).
　続いて、パッド電極１７にバンプ電極１６が形成され、更に、その上にロジックチップ１２が載置される（図６（ｈ））。ロジックチップ１２は、例えば、アラインメントマークに従って位置調整されて載置される。 Subsequently, the bump electrode 16 is formed on the pad electrode 17, and the logic chip 12 is further placed thereon (FIG. 6(h)). For example, the logic chip 12 is placed with its position adjusted according to the alignment mark.
　続いて、バンプ電極１６を介した半導体基板１０とロジックチップ１２との空間にアンダーフィル部材１８が注入される（同図（ｉ））。該空間をはみ出したアンダーフィル部材１８の一部は、スペース領域Ｓに入り込んでも良い。これにより、バンプ電極１６等の配線が保護されるとともに、ロジックチップ１２は、半導体基板１０上に固定される。 Subsequently, an underfill member 18 is injected into the space between the semiconductor substrate 10 and the logic chip 12 via the bump electrodes 16 ((i) in the same figure). A part of the underfill member 18 that protrudes from the space may enter the space region S. Thereby, the wiring such as the bump electrodes 16 is protected, and the logic chip 12 is fixed on the semiconductor substrate 10.
　続いて、半導体基板１０上には遮光部材１４が形成される（同図（ｊ））。より具体的には、遮光部材１４は、ロジックチップ１２の遮光対象領域を覆うように、ロジックチップ１２上に塗布され、これにより、ロジックチップ１２の遮光対象領域に塗布された遮光部材１４の一部（裾部分）は、スペース領域Ｓを超えて有機系樹脂材料膜１１１の縁部にまで流れ込む。有機系樹脂材料膜１１１の縁部に流れ込んだ遮光部材１４は、光電変換素子が形成された有効画素領域の手前のダム部１５によって堰き止められる。塗布された遮光部材１４は、例えば加熱されて硬化される。 Subsequently, a light shielding member 14 is formed on the semiconductor substrate 10 (FIG. 6(j)). More specifically, the light shielding member 14 is coated on the logic chip 12 so as to cover the light shielding target area of the logic chip 12, and thereby a part of the light shielding member 14 coated on the light shielding target area of the logic chip 12 is coated. The bottom portion (bottom portion) flows beyond the space region S to the edge of the organic resin material film 111. The light shielding member 14 that has flowed into the edge of the organic resin material film 111 is blocked by a dam portion 15 in front of the effective pixel area where the photoelectric conversion element is formed. The applied light shielding member 14 is heated and hardened, for example.
　以上のようにして、画素アレイ部１１にスペース領域を挟んで載置されたロジックチップ１２の遮光対象領域に塗布された遮光部材１４は、有機系樹脂材料膜１１１が除去されたスペース領域Ｓを超えて画素アレイ部１１の有機系樹脂材料膜１１１の縁部まで覆うように形成される。これにより、ロジックチップ１２表面での反射光の画素アレイ部１１への入り込みによるフレアの発生を抑止する。また、有機系樹脂材料膜１１１と遮光部材１４との被り量は、０より大きく１／２以下としているため、熱ストレスによる材料膜間の界面の剥離を防止することができる。 As described above, the light-shielding member 14 applied to the light-shielding target region of the logic chip 12 placed on the pixel array section 11 with the space region interposed therebetween covers the space region S from which the organic resin material film 111 has been removed. It is formed so as to cover the edges of the organic resin material film 111 of the pixel array section 11. This prevents flare from occurring due to light reflected from the surface of the logic chip 12 entering the pixel array section 11. Furthermore, since the amount of overlap between the organic resin material film 111 and the light shielding member 14 is greater than 0 and 1/2 or less, peeling of the interface between the material films due to thermal stress can be prevented.
（変形例）
　上記の例では、スペース領域Ｓは、画素アレイ部１１とロジックチップ１２との間に形成されるようにレイアウトされたが、これに限られず、スペース領域Ｓは、以下に述べるように、遮光部材１４が塗布される領域、及び／又はロジックチップ１２の数・配置等との関係に応じて、種々にレイアウトされ得る。 (Modified example)
In the above example, the space region S is laid out so as to be formed between the pixel array section 11 and the logic chip 12, but the layout is not limited to this. Various layouts can be made depending on the area to which the logic chips 14 are applied and/or the number and arrangement of the logic chips 12.
　図７は、本技術の一実施形態に係る光検出装置の概略的構成の第１の変形例を示す平面図である。同図に示す光検出装置１は、画素アレイ部１１に対向する２つのロジックチップ１２を備えている。このような光検出装置１においても、画素アレイ部１１と各ロジックチップ１２との間にはスペース領域Ｓを形成することができる。 FIG. 7 is a plan view showing a first modified example of the schematic configuration of a photodetection device according to an embodiment of the present technology. The photodetecting device 1 shown in the figure includes two logic chips 12 facing a pixel array section 11. Also in such a photodetecting device 1, a space region S can be formed between the pixel array section 11 and each logic chip 12.
　したがって、上記の例と同様に、ロジックチップ１２表面での反射光の画素アレイ部１１への入り込みによるフレアの発生を抑止するとともに、熱ストレスによる材料膜間の界面の剥離を防止することができる。 Therefore, similarly to the above example, it is possible to suppress the occurrence of flare due to reflected light from the surface of the logic chip 12 entering the pixel array section 11, and also to prevent peeling of the interface between material films due to thermal stress. .
　図８は、本技術の一実施形態に係る光検出装置の概略的構成の第２の変形例を示す平面図である。同図に示す光検出装置１では、スペース領域Ｓが、画素アレイ部１１に対向するロジックチップ１２の第１の側面部分１２ａに加えて、第１の側面部分１２ａに直交する第２の側面部分１２ｃに対応する領域を含むように形成されている。つまり、遮光部材１４はロジックチップ１２の上方から第１の側面部分１２ａ及び第２の側面部分１２ｃに塗布されることから、スペース領域Ｓは、該第２の側面に対応する領域を含むように形成されるようにレイアウトされる。このように、第２の側面部分１２ｃに対応する領域は有機系樹脂材料膜１１１が除去されることにより、遮光部材１４が形成された該領域での熱ストレスによる界面の剥離の発生が防止される。 FIG. 8 is a plan view showing a second modified example of the schematic configuration of the photodetection device according to an embodiment of the present technology. In the photodetecting device 1 shown in the figure, the space region S includes not only the first side surface portion 12a of the logic chip 12 facing the pixel array section 11 but also the second side surface portion orthogonal to the first side surface portion 12a. It is formed to include a region corresponding to 12c. That is, since the light shielding member 14 is applied to the first side surface portion 12a and the second side surface portion 12c from above the logic chip 12, the space region S is designed to include a region corresponding to the second side surface portion. laid out to form. In this way, by removing the organic resin material film 111 from the region corresponding to the second side surface portion 12c, the occurrence of delamination at the interface due to thermal stress in the region where the light shielding member 14 is formed is prevented. Ru.
　また、図９は、図８に示したスペース領域Ｓのレイアウトを２つのロジックチップ１２に適用した第３の変形例を示している。すなわち、スペース領域Ｓは、各ロジックチップ１２第１の側面部分１２ａに加えて、第１の側面部分１２ａに直交する第２の側面部分１２ｃに対応する領域を含むように形成されている。 Further, FIG. 9 shows a third modification in which the layout of the space region S shown in FIG. 8 is applied to two logic chips 12. That is, the space region S is formed to include, in addition to the first side surface portion 12a of each logic chip 12, a region corresponding to the second side surface portion 12c orthogonal to the first side surface portion 12a.
　図１０は、本技術の一実施形態に係る光検出装置の概略的構成の第４の変形例を示す平面図である。同図に示す光検出装置１では、画素アレイ部１１に対向する４つのロジックチップ１２を備えている。本例では、隣接するロジックチップ１２どうしの間の領域にも、スペース領域Ｓが連続的に形成されている。 FIG. 10 is a plan view showing a fourth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology. The photodetector 1 shown in the figure includes four logic chips 12 facing a pixel array section 11. In this example, space regions S are also continuously formed in regions between adjacent logic chips 12.
　図１１は、本技術の一実施形態に係る光検出装置の概略的構成の第５の変形例を示す平面図である。同図に示す光検出装置１では、各ロジックチップ１２の第２の側面部分１２ｃのうち外側の側面に対応する領域部分１２ｃ’を含むように形成されている。 FIG. 11 is a plan view showing a fifth modification of the schematic configuration of the photodetection device according to an embodiment of the present technology. The photodetecting device 1 shown in the figure is formed to include a region portion 12c' corresponding to the outer side surface of the second side surface portion 12c of each logic chip 12.
　以上のように、本実施形態によれば、画素アレイ部１１にスペース領域を挟んで載置されたロジックチップ１２の遮光対象領域に塗布された遮光部材１４は、有機系樹脂材料膜１１１が除去されたスペース領域Ｓを超えて画素アレイ部１１の有機系樹脂材料膜１１１の縁部まで覆うように形成される。これにより、ロジックチップ１２表面での反射光の画素アレイ部１１への入り込みによるフレアの発生を抑止する。また、有機系樹脂材料膜１１１と遮光部材１４との被り量は、０より大きく１／２以下としているため、熱ストレスによる材料膜間の界面の剥離を防止することができる。 As described above, according to the present embodiment, the organic resin material film 111 is removed from the light shielding member 14 applied to the light shielding target area of the logic chip 12 mounted on the pixel array section 11 with a space region in between. It is formed so as to cover the edge of the organic resin material film 111 of the pixel array section 11 beyond the space region S that has been formed. This prevents flare from occurring due to light reflected from the surface of the logic chip 12 entering the pixel array section 11. Furthermore, since the amount of overlap between the organic resin material film 111 and the light shielding member 14 is greater than 0 and 1/2 or less, peeling of the interface between the material films due to thermal stress can be prevented.
　上記各実施形態は、本技術を説明するための例示であり、本技術をこれらの実施形態にのみ限定する趣旨ではない。本技術は、その要旨を逸脱しない限り、さまざまな形態で実施することができる。 The embodiments described above are examples for explaining the present technology, and are not intended to limit the present technology only to these embodiments. The present technology can be implemented in various forms without departing from the gist thereof.
　例えば、本明細書に開示される方法においては、その結果に矛盾が生じない限り、ステップ、動作又は機能を並行して又は異なる順に実施しても良い。説明されたステップ、動作及び機能は、単なる例として提供されており、ステップ、動作及び機能のうちのいくつかは、技術の要旨を逸脱しない範囲で、省略でき、また、互いに結合させることで一つのものとしてもよく、また、他のステップ、動作又は機能を追加してもよい。 For example, in the methods disclosed herein, steps, acts, or functions may be performed in parallel or in a different order unless the results are inconsistent. The steps, acts, and functions described are provided by way of example only, and some of the steps, acts, and functions may be omitted or combined with each other without departing from the spirit of the art. It is also possible to add other steps, actions, or functions.
　また、本明細書では、さまざまな実施形態が開示されているが、一の実施形態における特定のフィーチャ（技術的事項）を、適宜改良しながら、他の実施形態に追加し、又は該他の実施形態における特定のフィーチャと置換することができ、そのような形態も本技術の要旨に含まれる。 Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment may be added to other embodiments while improving them as appropriate, or Certain features in the embodiments may be replaced and such forms are also within the scope of the present technology.
　また、本技術は、以下のような技術的事項を含み構成されても良い。
（１）
　複数の光電変換素子がアレイ状に配列された画素アレイ部を含む半導体基板と、
　前記半導体基板上に、前記画素アレイ部とスペース領域を隔てて載置された少なくとも１つのロジックチップと、
　前記画素アレイ部に近位する前記ロジックチップの遮光対象領域を少なくとも覆うように形成された遮光部材と、を備え、
　前記画素アレイ部は、前記複数の光電変換素子の受光面上に形成された少なくとも１つの有機系樹脂材料膜を含み、
　前記遮光部材は、前記ロジックチップの前記遮光対象領域から前記スペース領域を超えて前記画素アレイ部上に形成された前記有機系樹脂材料膜の縁部まで覆うように形成されている、
光検出装置。
（２）
　前記遮光対象領域は、前記スペース領域に近位する前記ロジックチップの第１の側面部分を含む、
前記（１）に記載の光検出装置。
（３）
　前記遮光対象領域は、前記スペース領域に近位する前記ロジックチップの上面縁部分を更に含む、
前記（２）に記載の光検出装置。
（４）
　前記遮光対象領域は、前記第１の側面部分と直交する第２の側面部分における少なくとも前記スペース領域に近位する部分である、
前記（２）又は（３）に記載の光検出装置。
（５）
　前記半導体基板上に形成された前記スペース領域は、前記有機系樹脂材料膜が除去された領域である、
前記（１）から（４）のいずれか一つに記載の光検出装置。
（６）
　前記スペース領域は、シリコン窒化膜で覆われている、
前記（４）に記載の光検出装置。
（７）
　前記スペース領域の表面は、凹凸形状部分を含む、
前記（１）から（６）のいずれか一つに記載の光検出装置。
（８）
　前記有機系樹脂材料膜は、カラーフィルタ及びオンチップレンズの少なくともいずれかを含む、
前記（１）から（７）のいずれか一つに記載の光検出装置。
（９）
　前記画素アレイ部上に形成された前記有機系樹脂材料膜の前記縁部において、前記縁部に沿って形成された、前記遮光部材の流入を堰き止めるための少なくとも１つのダム部を有する、
前記（１）から（８）のいずれか一つに記載の光検出装置。
（１０）
　前記遮光部材は、前記ロジックチップの表面の光の反射率よりも低い反射率を有する樹脂材料からなる、
前記（１）から（９）のいずれか一つに記載の光検出装置。
（１１）
　前記ロジックチップは、前記半導体基板上にバンプ電極を介して載置されるとともに、前記半導体基板と前記ロジックチップとの間に注入されたアンダーフィル部材により固定される、
前記（１）から（１０）のいずれか一つに記載の光検出装置。
（１２）
　前記遮光部材は、前記スペース領域にはみ出た前記アンダーフィル部材を覆っている、前記（１０）に記載の光検出装置。
（１３）
　前記ロジックチップの前記遮光対象領域側の前記スペース領域の一端部から前記有機系樹脂材料膜上の前記縁部を覆う前記遮光部材の裾部分までの前記遮光部材の幅に対する前記有機系樹脂材料膜上の前記縁部を覆う前記遮光部材の幅の比は、０より大きく１／２以下である、
前記（１）から（１２）のいずれか一つに記載の光検出装置。 Further, the present technology may be configured to include the following technical matters.
(1)
a semiconductor substrate including a pixel array section in which a plurality of photoelectric conversion elements are arranged in an array;
at least one logic chip placed on the semiconductor substrate with a space region between the pixel array section and the pixel array section;
a light-shielding member formed to at least cover a light-shielding target region of the logic chip proximal to the pixel array section;
The pixel array section includes at least one organic resin material film formed on the light receiving surface of the plurality of photoelectric conversion elements,
The light shielding member is formed to cover from the light shielding target region of the logic chip to an edge of the organic resin material film formed on the pixel array section beyond the space region.
Photodetection device.
(2)
The light-shielding target region includes a first side portion of the logic chip proximal to the space region.
The photodetection device according to (1) above.
(3)
The light-shielding target region further includes an upper edge portion of the logic chip proximal to the space region.
The photodetection device according to (2) above.
(4)
The light-shielding target area is at least a portion of a second side surface perpendicular to the first side surface that is proximal to the space area.
The photodetection device according to (2) or (3) above.
(5)
The space region formed on the semiconductor substrate is a region from which the organic resin material film is removed.
The photodetector according to any one of (1) to (4) above.
(6)
the space region is covered with a silicon nitride film;
The photodetection device according to (4) above.
(7)
The surface of the space region includes an uneven portion.
The photodetector according to any one of (1) to (6) above.
(8)
The organic resin material film includes at least one of a color filter and an on-chip lens.
The photodetection device according to any one of (1) to (7) above.
(9)
At least one dam portion formed along the edge of the organic resin material film formed on the pixel array portion for damming the inflow of the light shielding member;
The photodetector according to any one of (1) to (8) above.
(10)
The light shielding member is made of a resin material having a lower reflectance than the light reflectance of the surface of the logic chip.
The photodetector according to any one of (1) to (9) above.
(11)
The logic chip is placed on the semiconductor substrate via bump electrodes, and is fixed by an underfill member injected between the semiconductor substrate and the logic chip.
The photodetection device according to any one of (1) to (10) above.
(12)
The light detection device according to (10), wherein the light shielding member covers the underfill member protruding into the space area.
(13)
The organic resin material film with respect to the width of the light shielding member from one end of the space region on the light shielding target area side of the logic chip to the bottom portion of the light shielding member that covers the edge on the organic resin material film. The width ratio of the light shielding member covering the upper edge is greater than 0 and less than or equal to 1/2,
The photodetection device according to any one of (1) to (12) above.
１…光検出装置
１０…半導体基板
　１０１…配線層
　１０２…シリコン窒化膜
１１…画素アレイ部
　１１１…有機系樹脂材料膜
　　１１１ａ…平坦化膜
　　１１１ｂ…カラーフィルタ
　　１１１ｃ…オンチップレンズ
　　１１２…酸化膜
１２…ロジックチップ
　１２ａ…第１の側面部分
　１２ｂ…上面部分
　１２ｃ…第２の側面部分
１３…外部パッド電極
１４…遮光部材
１５…ダム部
１６…バンプ電極
１７…パッド電極
１８…アンダーフィル部材
Ｓ…スペース領域 1... Photodetection device 10... Semiconductor substrate 101... Wiring layer 102... Silicon nitride film 11... Pixel array section 111... Organic resin material film 111a... Flattening film 111b... Color filter 111c... On-chip lens 112... Oxide film 12... Logic chip 12a...First side surface portion 12b...Top surface portion 12c...Second side surface portion 13...External pad electrode 14...Light shielding member 15...Dam portion 16...Bump electrode 17...Pad electrode 18...Underfill member S...Space area

Claims (13)

  1. 　複数の光電変換素子がアレイ状に配列された画素アレイ部を含む半導体基板と、
    　前記半導体基板上に、前記画素アレイ部とスペース領域を隔てて載置された少なくとも１つのロジックチップと、
    　前記画素アレイ部に近位する前記ロジックチップの遮光対象領域を少なくとも覆うように形成された遮光部材と、を備え、
    　前記画素アレイ部は、前記複数の光電変換素子の受光面上に形成された少なくとも１つの有機系樹脂材料膜を含み、
    　前記遮光部材は、前記ロジックチップの前記遮光対象領域から前記スペース領域を超えて前記画素アレイ部上に形成された前記有機系樹脂材料膜の縁部まで覆うように形成されている、
    光検出装置。     a semiconductor substrate including a pixel array section in which a plurality of photoelectric conversion elements are arranged in an array;
    at least one logic chip placed on the semiconductor substrate with a space region between the pixel array section and the pixel array section;
    a light-shielding member formed to at least cover a light-shielding target region of the logic chip proximal to the pixel array section;
    The pixel array section includes at least one organic resin material film formed on the light receiving surface of the plurality of photoelectric conversion elements,
    The light shielding member is formed to cover from the light shielding target region of the logic chip to an edge of the organic resin material film formed on the pixel array section beyond the space region.
    Photodetection device.
  2. 　前記遮光対象領域は、前記スペース領域に近位する前記ロジックチップの第１の側面部分を含む、
    請求項１に記載の光検出装置。     The light-shielding target region includes a first side portion of the logic chip proximal to the space region.
    The photodetection device according to claim 1.
  3. 　前記遮光対象領域は、前記スペース領域に近位する前記ロジックチップの上面縁部分を更に含む、
    請求項２に記載の光検出装置。     The light-shielding target region further includes an upper edge portion of the logic chip proximal to the space region.
    The photodetection device according to claim 2.
  4. 　前記遮光対象領域は、前記第１の側面部分と直交する第２の側面部分における少なくとも前記スペース領域に近位する部分である、
    請求項２に記載の光検出装置。     The light-shielding target area is at least a portion of a second side surface perpendicular to the first side surface that is proximal to the space area.
    The photodetection device according to claim 2.
  5. 　前記半導体基板上に形成された前記スペース領域は、前記有機系樹脂材料膜が除去された領域である、
    請求項１に記載の光検出装置。     The space region formed on the semiconductor substrate is a region from which the organic resin material film is removed.
    The photodetection device according to claim 1.
  6. 　前記スペース領域は、シリコン窒化膜で覆われている、
    請求項４に記載の光検出装置。     the space region is covered with a silicon nitride film;
    The photodetection device according to claim 4.
  7. 　前記スペース領域の表面は、凹凸形状部分を含む、
    請求項４に記載の光検出装置。     The surface of the space region includes an uneven portion.
    The photodetection device according to claim 4.
  8. 　前記有機系樹脂材料膜は、カラーフィルタ及びオンチップレンズの少なくともいずれかを含む、
    請求項１に記載の光検出装置。     The organic resin material film includes at least one of a color filter and an on-chip lens.
    The photodetection device according to claim 1.
  9. 　前記画素アレイ部上に形成された前記有機系樹脂材料膜の前記縁部において、前記縁部に沿って形成された、前記遮光部材の流入を堰き止めるための少なくとも１つのダム部を有する、
    請求項１に記載の光検出装置。     At least one dam portion formed along the edge of the organic resin material film formed on the pixel array portion for damming the inflow of the light shielding member;
    The photodetection device according to claim 1.
  10. 　前記遮光部材は、前記ロジックチップの表面の光の反射率よりも低い反射率を有する樹脂材料からなる、
    請求項１に記載の光検出装置。     The light shielding member is made of a resin material having a lower reflectance than the light reflectance of the surface of the logic chip.
    The photodetection device according to claim 1.
  11. 　前記ロジックチップは、前記半導体基板上にバンプ電極を介して載置されるとともに、前記半導体基板と前記ロジックチップとの間に注入されたアンダーフィル部材により固定される、
    請求項１に記載の光検出装置。     The logic chip is placed on the semiconductor substrate via bump electrodes, and is fixed by an underfill member injected between the semiconductor substrate and the logic chip.
    The photodetection device according to claim 1.
  12. 　前記遮光部材は、前記スペース領域にはみ出た前記アンダーフィル部材を覆っている、請求項１１に記載の光検出装置。 The light detection device according to claim 11, wherein the light shielding member covers the underfill member protruding into the space area.
  13. 　前記ロジックチップの前記遮光対象領域側の前記スペース領域の一端部から前記有機系樹脂材料膜上の前記縁部を覆う前記遮光部材の裾部分までの前記遮光部材の幅に対する前記有機系樹脂材料膜上の前記縁部を覆う前記遮光部材の幅の比は、０より大きく１／２以下である、
    請求項１に記載の光検出装置。     The organic resin material film with respect to the width of the light shielding member from one end of the space region on the light shielding target region side of the logic chip to the bottom portion of the light shielding member that covers the edge on the organic resin material film. The width ratio of the light shielding member covering the upper edge is greater than 0 and less than or equal to 1/2,
    The photodetection device according to claim 1.
PCT/JP2023/022642 2022-07-26 2023-06-19 Light detection device WO2024024335A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016163011A (en) * 2015-03-05 2016-09-05 ソニー株式会社 Semiconductor device and manufacturing method, and electronic apparatus
JP2018147974A (en) * 2017-03-03 2018-09-20 ソニーセミコンダクタソリューションズ株式会社 Solid state imaging device, electronic apparatus, and semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016163011A (en) * 2015-03-05 2016-09-05 ソニー株式会社 Semiconductor device and manufacturing method, and electronic apparatus
JP2018147974A (en) * 2017-03-03 2018-09-20 ソニーセミコンダクタソリューションズ株式会社 Solid state imaging device, electronic apparatus, and semiconductor device

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