WO2024016889A1

WO2024016889A1 - Three-dimensional semiconductor structure and manufacturing method therefor

Info

Publication number: WO2024016889A1
Application number: PCT/CN2023/099549
Authority: WO
Inventors: 肖剑锋
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-07-18
Filing date: 2023-06-09
Publication date: 2024-01-25
Also published as: CN115084145A

Abstract

The present disclosure provides a three-dimensional semiconductor structure and a manufacturing method therefor. The three-dimensional semiconductor structure comprises: a substrate; and a stacked structure, comprising a plurality of memory cell arrays stacked in the thickness direction of the substrate, each memory cell array comprising a plurality of transistors and a plurality of connecting pads which are arranged in an array in the plane direction of the substrate, wherein the transistors comprise semiconductor layers extending in the plane direction of the substrate, and the connecting pads are arranged on the sides of the semiconductor layers in the width direction and are connected to the semiconductor layers.

Description

三维半导体结构及其制作方法Three-dimensional semiconductor structure and manufacturing method

本申请要求于2022年07月18日提交中国专利局、申请号为202210842918.5、申请名称为“三维半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to the Chinese patent application filed with the China Patent Office on July 18, 2022, with the application number 202210842918.5 and the application title "Three-dimensional semiconductor structure and manufacturing method thereof", the entire content of which is incorporated into this application by reference. .

技术领域Technical field

本公开涉及半导体集成电路技术领域，尤其涉及一种三维半导体结构及其制作方法。The present disclosure relates to the technical field of semiconductor integrated circuits, and in particular, to a three-dimensional semiconductor structure and a manufacturing method thereof.

背景技术Background technique

随着半导体技术的发展，半导体器件逐步走向更高集成度，同时，希望半导体器件具有更低的制造成本，以满足消费者对半导体器件的优越性能和低廉价格的需求。With the development of semiconductor technology, semiconductor devices are gradually moving toward higher integration. At the same time, semiconductor devices are expected to have lower manufacturing costs to meet consumer demand for superior performance and low prices of semiconductor devices.

对于典型的二维(平面)半导体器件的集成度，主要由在平面上阵列排布的存储单元的面积决定，存储单元的面积越小，半导体器件的集成度越高。存储单元的面积受精细图案形成技术的水平影响，然而，用于提高图案精细度的昂贵的工艺设备，极大的限制了二维半导体器件集成度的提高。因此，现已提出了具有三维架构的存储单元的三维半导体器件。For a typical two-dimensional (planar) semiconductor device, the integration level is mainly determined by the area of the memory cells arranged in an array on the plane. The smaller the area of the memory unit, the higher the integration level of the semiconductor device. The area of a memory cell is affected by the level of fine patterning technology. However, the expensive process equipment used to improve pattern fineness greatly limits the improvement of the integration of two-dimensional semiconductor devices. Therefore, three-dimensional semiconductor devices having memory cells with a three-dimensional architecture have been proposed.

然而，现有的三维半导体器件中，由于晶体管悬空而存在浮体效应，严重影响半导体器件的性能。However, in existing three-dimensional semiconductor devices, the floating body effect exists due to the floating transistors, which seriously affects the performance of the semiconductor devices.

发明内容Contents of the invention

为了解决背景技术中提到的至少一个问题，本公开提供一种三维半导体结构及其制作方法，能够解决晶体管的浮体效应，提升三维半导体结构的性能。In order to solve at least one of the problems mentioned in the background art, the present disclosure provides a three-dimensional semiconductor structure and a manufacturing method thereof, which can solve the floating body effect of transistors and improve the performance of the three-dimensional semiconductor structure.

为了实现上述目的，本公开提供如下技术方案：In order to achieve the above objectives, the present disclosure provides the following technical solutions:

一方面，本公开提供一种三维半导体结构，包括：In one aspect, the present disclosure provides a three-dimensional semiconductor structure including:

衬底； substrate;

堆叠结构，位于衬底上，包括沿衬底的厚度方向堆叠的多个存储单元阵列，每个存储单元阵列包括沿衬底的平面方向阵列排布的多个晶体管和多个连接垫；其中，The stacked structure is located on the substrate and includes a plurality of memory cell arrays stacked along the thickness direction of the substrate, and each memory cell array includes a plurality of transistors and a plurality of connection pads arranged in an array along the plane direction of the substrate; wherein,

晶体管包括沿衬底的平面方向延伸的半导体层，半导体层沿其长度方向依次设置有源极区、沟道区和漏极区；连接垫设置于半导体层的宽度方向的侧方并与半导体层连接，连接垫与沟道区电连接，且连接垫与衬底电连接。The transistor includes a semiconductor layer extending along the plane direction of the substrate. The semiconductor layer is sequentially provided with a source region, a channel region and a drain region along its length direction; the connection pad is provided on the side of the semiconductor layer in the width direction and is in contact with the semiconductor layer. Connection, the connection pad is electrically connected to the channel region, and the connection pad is electrically connected to the substrate.

在一种可能的实施方式中，沿半导体层的宽度方向，连接垫与半导体层交替设置。In a possible implementation, the connection pads and the semiconductor layer are alternately arranged along the width direction of the semiconductor layer.

在一种可能的实施方式中，连接垫与位于其两侧的半导体层相对的侧面分别为第一侧面和第二侧面，第一侧面与相对的半导体层连接，第二侧面与相对的半导体层之间具有间隙。In a possible implementation, the sides of the connection pad that are opposite to the semiconductor layers located on both sides thereof are a first side and a second side respectively. The first side is connected to the opposite semiconductor layer, and the second side is connected to the opposite semiconductor layer. There is a gap in between.

在一种可能的实施方式中，连接垫与位于其两侧的半导体层均连接。In a possible implementation, the connection pad is connected to the semiconductor layers located on both sides of the connection pad.

在一种可能的实施方式中，每两个半导体层之间设有一个连接垫，连接垫与位于其两侧的半导体层均连接。In a possible implementation, a connection pad is provided between every two semiconductor layers, and the connection pad is connected to the semiconductor layers on both sides thereof.

在一种可能的实施方式中，三维半导体结构还包括：In a possible implementation, the three-dimensional semiconductor structure further includes:

连接立柱，沿衬底的平面方向阵列排布，连接立柱连接在衬底上并沿衬底的厚度方向延伸，连接立柱与其延伸方向上的各连接垫连接。The connection columns are arranged in an array along the plane direction of the substrate. The connection columns are connected to the substrate and extend along the thickness direction of the substrate. The connection columns are connected to each connection pad in the direction in which they extend.

在一种可能的实施方式中，连接垫包括主体部和连接部，主体部与沟道区对应，沿半导体层的长度方向，连接部连接于主体部的侧方，连接立柱贯穿连接部。In a possible implementation, the connection pad includes a main body part and a connecting part. The main body part corresponds to the channel region. The connecting part is connected to the side of the main body part along the length direction of the semiconductor layer, and the connecting post penetrates the connecting part.

在一种可能的实施方式中，连接部与源极区对应，或者，连接部与漏极区对应。In a possible implementation, the connection part corresponds to the source region, or the connection part corresponds to the drain region.

在一种可能的实施方式中，连接部包括第一连接部和第二连接部，第一连接部与源极区对应，第二连接部与漏极区对应，第一连接部和第二连接部中的至少一者与连接立柱连接。In a possible implementation, the connection part includes a first connection part and a second connection part, the first connection part corresponds to the source region, the second connection part corresponds to the drain region, the first connection part and the second connection part At least one of the parts is connected to the connecting column.

在一种可能的实施方式中，晶体管还包括栅极结构，栅极结构覆盖沟道区的厚度方向的至少一侧表面。In a possible implementation, the transistor further includes a gate structure covering at least one side surface in the thickness direction of the channel region.

在一种可能的实施方式中，栅极结构覆盖沟道区的厚度方向的两侧表面。 In a possible implementation, the gate structure covers both sides of the channel region in the thickness direction.

在一种可能的实施方式中，栅极结构延伸至覆盖连接垫的部分表面。In a possible implementation, the gate structure extends to cover part of the surface of the connection pad.

多条字线，字线覆盖对应的栅极结构并沿半导体层的宽度方向延伸，且字线沿衬底的厚度方向堆叠。There are multiple word lines, the word lines cover corresponding gate structures and extend along the width direction of the semiconductor layer, and the word lines are stacked along the thickness direction of the substrate.

在一种可能的实施方式中，沿衬底的厚度方向，连接垫的厚度与半导体层的厚度相同。In a possible implementation, along the thickness direction of the substrate, the thickness of the connection pad is the same as the thickness of the semiconductor layer.

另一方面，本公开提供一种三维半导体结构的制作方法，包括：On the other hand, the present disclosure provides a method for manufacturing a three-dimensional semiconductor structure, including:

提供衬底；Provide a substrate;

形成堆叠结构，堆叠结构位于衬底上；堆叠结构包括沿衬底的厚度方向堆叠的多个存储单元阵列，每个存储单元阵列包括沿衬底的平面方向阵列排布的多个晶体管和多个连接垫；其中，A stacked structure is formed, and the stacked structure is located on the substrate; the stacked structure includes a plurality of memory cell arrays stacked along the thickness direction of the substrate, and each memory cell array includes a plurality of transistors arranged in an array along the plane direction of the substrate and a plurality of connection pad; where,

晶体管包括沿衬底的平面方向延伸的半导体层，半导体层沿其长度方向依次设置有源极区、沟道区和漏极区；连接垫设置于半导体层的宽度方向的侧方并与半导体层连接，连接垫与衬底电连接，且连接垫与沟道区电连接。The transistor includes a semiconductor layer extending along the plane direction of the substrate. The semiconductor layer is sequentially provided with a source region, a channel region and a drain region along its length direction; the connection pad is provided on the side of the semiconductor layer in the width direction and is in contact with the semiconductor layer. Connection, the connection pad is electrically connected to the substrate, and the connection pad is electrically connected to the channel region.

本公开提供的三维半导体结构及其制作方法，三维半导体结构通过在堆叠结构中的每层存储单元阵列中设置多个连接垫，连接垫在存储单元阵列中阵列排布，每个晶体管均有对应的连接垫与其连接，连接垫和半导体层的沟道区电连接，并且，连接垫与衬底电连接，连接垫用于使沟道区内残留的电荷流动至衬底，通过接地的衬底排出，解决晶体管的浮体效应，提升三维半导体结构的性能。其中，对于沿衬底的平面方向延伸的半导体层，通过将连接垫同层设置在半导体层的宽度方向的侧方，便于连接垫的形成，且连接垫不占据单独的厚度空间，有利于提升三维半导体结构的集成度。The present disclosure provides a three-dimensional semiconductor structure and a manufacturing method thereof. The three-dimensional semiconductor structure is provided with multiple connection pads in each layer of memory cell array in the stacked structure. The connection pads are arranged in an array in the memory cell array, and each transistor has a corresponding The connection pad is connected to it, the connection pad is electrically connected to the channel area of the semiconductor layer, and the connection pad is electrically connected to the substrate. The connection pad is used to allow the residual charge in the channel area to flow to the substrate, through the grounded substrate Discharge, solve the floating body effect of transistors, and improve the performance of three-dimensional semiconductor structures. Among them, for the semiconductor layer extending along the plane direction of the substrate, by arranging the connection pads on the side of the width direction of the semiconductor layer in the same layer, the formation of the connection pads is facilitated, and the connection pads do not occupy a separate thickness space, which is beneficial to the improvement of the The degree of integration of three-dimensional semiconductor structures.

本公开的构造以及它的其他发明目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。The construction of the present disclosure, as well as its other inventive objects and beneficial effects, will become more apparent from the description of the preferred embodiments in conjunction with the accompanying drawings.

附图说明Description of drawings

为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作以简单介绍，显而易见地，下面描述中的附图是本公开的一些实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings needed to describe the embodiments or the prior art. Obviously, the following The drawings in the description illustrate some embodiments of the disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

图1为一种三维半导体器件的透视图；Figure 1 is a perspective view of a three-dimensional semiconductor device;

图2为图1中所示的三维半导体器件的晶体管的结构示意图；Figure 2 is a schematic structural diagram of a transistor of the three-dimensional semiconductor device shown in Figure 1;

图3为图2中的晶体管在A-A处的截面示意图；Figure 3 is a schematic cross-sectional view of the transistor in Figure 2 at A-A;

图4为本公开实施例提供的三维半导体结构的透视图；Figure 4 is a perspective view of a three-dimensional semiconductor structure provided by an embodiment of the present disclosure;

图5为图4中的三维半导体结构的存储单元的透视图；Figure 5 is a perspective view of the memory cell of the three-dimensional semiconductor structure in Figure 4;

图6为图4中的三维半导体结构的B-B处的剖视图；Figure 6 is a cross-sectional view of the three-dimensional semiconductor structure taken along line B-B in Figure 4;

图7为本公开实施例提供的另一种三维半导体结构对应图4中B-B处的剖视图；Figure 7 is a cross-sectional view corresponding to B-B in Figure 4 of another three-dimensional semiconductor structure provided by an embodiment of the present disclosure;

图8为本公开实施例提供的第三种三维半导体结构对应图4中B-B处的剖视图；Figure 8 is a cross-sectional view corresponding to B-B in Figure 4 of the third three-dimensional semiconductor structure provided by an embodiment of the present disclosure;

图9为另一种三维半导体结构的存储单元的透视图；Figure 9 is a perspective view of a memory cell of another three-dimensional semiconductor structure;

图10为本公开实施例提供的三维半导体结构的制作方法的步骤流程图。FIG. 10 is a flowchart of steps of a method for manufacturing a three-dimensional semiconductor structure provided by an embodiment of the present disclosure.

附图标记说明：
1-三维半导体结构；
100-衬底；
200-堆叠结构；300-字线；400-位线；500-连接立柱；
201-存储单元阵列；
210-晶体管；220-连接垫；220a-第一侧面；220b-第二侧面；230-电容；
211-半导体层；212-栅极结构；221-主体部；222-连接部；
2111-源极区；2112-沟道区；2113-漏极区；2221-第一连接部；2222-第二
连接部；
10-三维半导体器件；
11-晶体管；12-字线；13-位线；14-电容；15-接触立柱；
111-半导体柱；111a-源极区；111b-沟道区；111c-漏极区；112-栅极结构；
112a-栅极介电层；112b-栅电极层。Explanation of reference symbols:
1-Three-dimensional semiconductor structure;
100-substrate;
200-stacked structure; 300-word line; 400-bit line; 500-connection column;
201-storage cell array;
210-transistor; 220-connection pad; 220a-first side; 220b-second side; 230-capacitor;
211-semiconductor layer; 212-gate structure; 221-main part; 222-connection part;
2111-source region; 2112-channel region; 2113-drain region; 2221-first connection part; 2222-second connection part;
10-Three-dimensional semiconductor devices;
11-Transistor; 12-Word line; 13-Bit line; 14-Capacitor; 15-Contact pillar;
111-semiconductor pillar; 111a-source region; 111b-channel region; 111c-drain region; 112-gate structure;
112a-gate dielectric layer; 112b-gate electrode layer.

具体实施方式Detailed ways

正如背景技术中所述，二维半导体器件由于器件图案是在平面方向上布局延伸的，其集成度主要是由在平面上阵列排布的存储单元的面积决定的，想要提高二维半导体器件的集成度，需减小存储单元的面积。然而，存储单元的面积受精细图案形成技术的水平影响，现有的大部分工艺设备均无法制作出精细的器件图案，能够提高器件图案的精细度的工艺设备稀少且昂贵，这对二维半导体器件的集成度的提高造成了极大限制。As mentioned in the background art, two-dimensional semiconductor devices have device patterns that are laid out in the plane direction. Locally extended, its integration level is mainly determined by the area of memory cells arranged in an array on a plane. If you want to improve the integration level of two-dimensional semiconductor devices, you need to reduce the area of memory cells. However, the area of a memory cell is affected by the level of fine pattern formation technology. Most of the existing process equipment cannot produce fine device patterns. Process equipment that can improve the precision of device patterns is rare and expensive. This is a problem for two-dimensional semiconductors. The increase in the integration level of devices has caused great limitations.

由于二维半导体器件的集成度有限，为了提高半导体器件的集成度，提升半导体器件的性能，并使半导体器件具有较低的制作成本，现已提出了三维半导体器件。顾名思义，三维半导体器件具有在器件的厚度方向上堆叠的存储单元，以在器件的单位面积内设置更多的存储单元，提升半导体器件的集成度。Since the integration level of two-dimensional semiconductor devices is limited, in order to improve the integration level of semiconductor devices, improve the performance of semiconductor devices, and make semiconductor devices have lower manufacturing costs, three-dimensional semiconductor devices have been proposed. As the name suggests, a three-dimensional semiconductor device has memory cells stacked in the thickness direction of the device to provide more memory cells per unit area of the device and improve the integration of the semiconductor device.

图1为一种三维半导体器件的透视图。参照图1所示，以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，图中所示的X方向和Y方向构成的平面为三维半导体器件10的平面方向，图中所示的Z方向为三维半导体器件10的厚度方向。三维半导体器件10的晶体管11沿其厚度方向(Z方向)堆叠在衬底(图中未示出)上，以其中一个晶体管11而言，晶体管11包括半导体柱111和栅极结构112，半导体柱111沿三维半导体器件10的平面方向(例如图中所示的X方向)延伸，半导体柱111沿其延伸方向依次为源极区111a、沟道区(图中未示出)和漏极区111c，栅极结构112环设在沟道区的外周，栅极结构112可以包括包裹沟道区的外侧壁的栅极介电层112a和层叠在栅极介电层112a外侧的栅电极层112b。Figure 1 is a perspective view of a three-dimensional semiconductor device. Referring to FIG. 1 , taking a dynamic random access memory (DRAM) as an example, the plane formed by the X direction and the Y direction shown in the figure is the plane direction of the three-dimensional semiconductor device 10 . The Z direction is the thickness direction of the three-dimensional semiconductor device 10 . The transistors 11 of the three-dimensional semiconductor device 10 are stacked on a substrate (not shown in the figure) along its thickness direction (Z direction). For one of the transistors 11, the transistor 11 includes a semiconductor pillar 111 and a gate structure 112. The semiconductor pillar 111 extends along the plane direction of the three-dimensional semiconductor device 10 (for example, the X direction shown in the figure). The semiconductor pillar 111 along its extending direction is the source region 111a, the channel region (not shown in the figure) and the drain region 111c. The gate structure 112 is arranged around the outer periphery of the channel region. The gate structure 112 may include a gate dielectric layer 112a wrapping the outer wall of the channel region and a gate electrode layer 112b stacked outside the gate dielectric layer 112a.

三维半导体器件10还包括字线12、位线13和电容14。字线12沿三维半导体器件10的平面方向延伸，具体可以沿晶体管11的排列方向(例如与晶体管11的延伸方向垂直的方向)延伸，字线12包裹在其延长方向上的所有晶体管11的栅极结构112的外部。并且，沿字线12的堆叠方向(Z方向)，下层的字线12的端部依次伸出上层的字线12的端部而形成台阶部，利用各字线12的台阶部在字线12上连接接触立柱15，接触立柱15沿三维半导体器件10的厚度方向(Z方向)延伸，通过各接触立柱15将各字线12电连接至***的驱动电路(图中未示出)上。位线13沿三维半导体器件10的厚度方向延伸，并与其延伸方向上的各晶体管11的半导体柱111的一端连接。电容14连接在半导体柱111的另一端。 The three-dimensional semiconductor device 10 also includes a word line 12, a bit line 13, and a capacitor 14. The word line 12 extends along the plane direction of the three-dimensional semiconductor device 10 , specifically, it may extend along the arrangement direction of the transistors 11 (for example, the direction perpendicular to the extension direction of the transistors 11 ). The word line 12 wraps around the gates of all the transistors 11 in its extension direction. exterior of the pole structure 112 . Furthermore, along the stacking direction (Z direction) of the word lines 12 , the end portions of the lower layer word lines 12 sequentially extend from the end portions of the upper layer word lines 12 to form step portions. The contact pillars 15 are connected to the top. The contact pillars 15 extend along the thickness direction (Z direction) of the three-dimensional semiconductor device 10. Each word line 12 is electrically connected to a peripheral driving circuit (not shown in the figure) through each contact pillar 15. The bit line 13 extends along the thickness direction of the three-dimensional semiconductor device 10 and is connected to one end of the semiconductor pillar 111 of each transistor 11 in the extending direction. The capacitor 14 is connected to the other end of the semiconductor pillar 111 .

然而，由于沿三维半导体器件10的厚度方向堆叠的晶体管11悬空在衬底上方，因而，晶体管11会产生浮体效应。图2为图1中所示的三维半导体器件的晶体管的结构示意图；图3为图2中的晶体管在A-A处的截面示意图。参照图2和图3所示，所谓浮体效应，是三维半导体器件10在工作过程中，晶体管11会频繁开关，晶体管11开关过程中半导体柱111的沟道区111b形成耗尽区，电荷会反复注入沟道区111b和从沟道区111b排出，长此以往，沟道区111b中会残留一部分电荷，由于晶体管11悬空在衬底上方(晶体管11和衬底之间存在绝缘的介质层)，电荷会在沟道区111b内积累，由此而造成诸多不利效应，例如，产生寄生双晶体管效应而造成漏电流，引起较高电流损耗，阈值电压漂移，翘曲效应等。However, since the transistors 11 stacked along the thickness direction of the three-dimensional semiconductor device 10 are suspended above the substrate, the transistors 11 may produce a floating body effect. FIG. 2 is a schematic structural diagram of a transistor of the three-dimensional semiconductor device shown in FIG. 1 ; FIG. 3 is a schematic cross-sectional view of the transistor in FIG. 2 at A-A. Referring to Figures 2 and 3, the so-called floating body effect means that during the operation of the three-dimensional semiconductor device 10, the transistor 11 will switch frequently. During the switching process of the transistor 11, the channel region 111b of the semiconductor pillar 111 forms a depletion region, and the charge will repeatedly After being injected into the channel region 111b and discharged from the channel region 111b, in the long run, a part of the charge will remain in the channel region 111b. Since the transistor 11 is suspended above the substrate (there is an insulating dielectric layer between the transistor 11 and the substrate), the charge will Accumulation in the channel region 111b results in many adverse effects, such as parasitic double transistor effect resulting in leakage current, higher current loss, threshold voltage drift, warping effect, etc.

有鉴于此，本公开实施例提供一种三维半导体结构及其制作方法，三维半导体结构通过在晶体管的半导体层的侧方设置连接垫，通过连接垫将半导体层的沟道区电连接至衬底，从而，将沟道区内积存的电荷释放至衬底中，进而排出，以解决晶体管的浮体效应，提升三维半导体结构的性能。In view of this, embodiments of the present disclosure provide a three-dimensional semiconductor structure and a manufacturing method thereof. The three-dimensional semiconductor structure is provided with connection pads on the sides of the semiconductor layer of the transistor, and the channel region of the semiconductor layer is electrically connected to the substrate through the connection pads. , thereby releasing the charges accumulated in the channel region into the substrate and then discharging them to solve the floating body effect of the transistor and improve the performance of the three-dimensional semiconductor structure.

为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments These are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of this disclosure.

本实施例提供一种三维半导体结构，三维半导体结构可以为存储器件或非存储器件。存储器件例如可以包括动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(Static Random Access Memory，SRAM)、快闪存储器、电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、相变随机存取存储器(Phase Change Random Access Memory，PRAM)或磁阻随机存取存储器(Magnetoresistive Random Access Memory，MRAM)。非存储器件可以是逻辑器件(例如微处理器、数字信号处理器或微型控制器)或与其类似的器件。以下均以三维半导体结构为DRAM为例进行说明。This embodiment provides a three-dimensional semiconductor structure, which can be a memory device or a non-memory device. Storage devices may include, for example, dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), flash memory, and electrically erasable programmable read-only memory (Electrically Erasable Programmable Read). -Only Memory (EEPROM), Phase Change Random Access Memory (PRAM) or Magnetoresistive Random Access Memory (MRAM). The non-memory device may be a logic device (such as a microprocessor, digital signal processor, or microcontroller) or similar device. The following description takes the three-dimensional semiconductor structure as DRAM as an example.

图4为本公开实施例提供的三维半导体结构的透视图。参照图4所示，三维半导体结构1包括衬底100和堆叠结构200，堆叠结构200设置在衬底100上，衬底100可以为堆叠结构200提供支撑基础。制作三维半导体结构1时，通常是在衬底100之上设置叠层，在叠层内制作图案，以形成堆叠结构200，堆叠结构200即为所需的器件图形，以实现三维半导体结构1的功能。4 is a perspective view of a three-dimensional semiconductor structure provided by an embodiment of the present disclosure. Referring to Figure 4, the three-dimensional semiconductor structure 1 includes a substrate 100 and a stacked structure 200. The stacked structure 200 is disposed on the substrate 100, The substrate 100 may provide a supporting base for the stacked structure 200 . When making the three-dimensional semiconductor structure 1, a stack is usually provided on the substrate 100, and patterns are made in the stack to form a stacked structure 200. The stacked structure 200 is the required device pattern to realize the three-dimensional semiconductor structure 1. Function.

示例性的，构成衬底100的材料可以包括单晶硅、多晶硅、无定型硅、硅锗化合物或绝缘体上硅(silicon-on-insulator，简称SOI)中的一种或多种，或者，构成衬底100的材料还可以为本领域技术人员已知的其他材料。Exemplarily, the material constituting the substrate 100 may include one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, or silicon-on-insulator (SOI), or may consist of The material of the substrate 100 may also be other materials known to those skilled in the art.

需要说明的是，图4中所示的X方向和Y方向构成的平面方向，为三维半导体结构1的平面方向，例如，该平面方向可以指示衬底100的平面方向；图4中所示的Z方向为三维半导体结构1的厚度方向，例如Z方向可以指示衬底100的厚度方向。以下均以此坐标系作为三维半导体结构1的参照，不再赘述。It should be noted that the plane direction formed by the X direction and the Y direction shown in Figure 4 is the plane direction of the three-dimensional semiconductor structure 1. For example, the plane direction can indicate the plane direction of the substrate 100; shown in Figure 4 The Z direction is the thickness direction of the three-dimensional semiconductor structure 1 . For example, the Z direction may indicate the thickness direction of the substrate 100 . This coordinate system is used as a reference for the three-dimensional semiconductor structure 1 in the following and will not be described again.

堆叠结构200包括沿衬底100的厚度方向(Z方向)堆叠的多层，每层构成一个存储单元阵列201，也就是说，堆叠结构200包括沿衬底100的厚度方向堆叠的多个存储单元阵列201。每层的存储单元阵列201均包括沿衬底100的平面方向阵列排布的多个存储单元，示例性的，存储单元可以沿X方向和Y方向阵列排布，例如，X方向为存储单元排列的行方向，Y方向为存储单元排列的列方向。The stacked structure 200 includes multiple layers stacked along the thickness direction (Z direction) of the substrate 100 , and each layer constitutes a memory cell array 201 . That is to say, the stacked structure 200 includes multiple memory cells stacked along the thickness direction of the substrate 100 . array201. The memory cell array 201 of each layer includes a plurality of memory cells arranged in an array along the plane direction of the substrate 100. For example, the memory cells can be arranged in an array along the X direction and the Y direction. For example, the memory cells are arranged in the X direction. The row direction, and the Y direction is the column direction in which the memory cells are arranged.

另外，参照图4所示，三维半导体结构1还包括多条字线300和多条位线400。各字线300相互平行且沿第一方向延伸，各字线300之间可以等间距间隔设置；与字线300类似的，各位线400相互平行且沿第二方向延伸，各位线400之间可以等间距间隔设置。位线400和字线300与各存储单元电连接，用于控制各存储单元的工作状态。其中，第一方向和第二方向相交错，示例性的，第一方向和第二方向可以相互垂直。In addition, referring to FIG. 4 , the three-dimensional semiconductor structure 1 also includes a plurality of word lines 300 and a plurality of bit lines 400 . The word lines 300 are parallel to each other and extend along the first direction. The word lines 300 can be arranged at equal intervals. Similar to the word lines 300 , the bit lines 400 are parallel to each other and extend along the second direction. The bit lines 400 can be spaced apart from each other. Set equally spaced intervals. The bit line 400 and the word line 300 are electrically connected to each memory cell and are used to control the working state of each memory cell. The first direction and the second direction intersect. For example, the first direction and the second direction may be perpendicular to each other.

其中，每个存储单元均包括晶体管210和电容230，电容230与晶体管210电连接。字线300和位线400均与各存储单元内的晶体管210连接，字线300与存储单元阵列201***的驱动电路电连接，驱动电路向字线300中输入电压信号，通过字线300上的电压信号控制晶体管210的打开或关闭，晶体管210打开时，通过位线400读取存储在电容230中的数据信息，或者，通过位线400将数据信息写入到电容230中进行存储。Each memory cell includes a transistor 210 and a capacitor 230, and the capacitor 230 is electrically connected to the transistor 210. The word line 300 and the bit line 400 are both connected to the transistor 210 in each memory cell. The word line 300 is electrically connected to the driving circuit on the periphery of the memory cell array 201. The driving circuit inputs a voltage signal into the word line 300, and passes the voltage signal on the word line 300. The voltage signal controls the opening or closing of the transistor 210. When the transistor 210 is turned on, the data information stored in the capacitor 230 is read through the bit line 400, or the data information is written into the capacitor 230 through the bit line 400 for storage.

继续参照图4所示，对于三维半导体结构1，本实施例中，各存储单元内的晶体管210可以平行于衬底100的平面方向布置，这样，每层的存储单元阵列201中可以沿衬底100的平面方向阵列排布有多个晶体管210，并且，在衬底100上沿其厚度方向堆叠有多层存储单元阵列201，也就是说，阵列排布的晶体管210在衬底100上沿其厚度方向(Z方向)堆叠有多层。Continuing to refer to FIG. 4 , for the three-dimensional semiconductor structure 1 , in this embodiment, the transistors 210 in each memory unit can be arranged parallel to the plane direction of the substrate 100 , so that the memory unit array of each layer A plurality of transistors 210 may be arranged in an array in the column 201 along the plane direction of the substrate 100, and a multi-layer memory cell array 201 is stacked on the substrate 100 along its thickness direction, that is, the transistors 210 are arranged in an array. A plurality of layers are stacked on the substrate 100 along its thickness direction (Z direction).

如此，在三维半导体结构1的平面方向的面积维持不变的基础上，原有的阵列排布的晶体管210由于在三维半导体结构1的厚度方向上堆叠了多层，因而，增加了单位面积内晶体管210的数量，增大了三维半导体结构1的集成度，提高了三维半导体结构1的存储密度，进而，提升了三维半导体结构1的性能。In this way, on the basis that the area of the three-dimensional semiconductor structure 1 in the plane direction remains unchanged, the original array-arranged transistors 210 have multiple layers stacked in the thickness direction of the three-dimensional semiconductor structure 1, thus increasing the area per unit area. The number of transistors 210 increases the integration level of the three-dimensional semiconductor structure 1, improves the storage density of the three-dimensional semiconductor structure 1, and further improves the performance of the three-dimensional semiconductor structure 1.

由于三维半导体结构1增加了单位面积内晶体管210的数量，在实际应用中，对于存储量、存储读取速率要求较低的情况，三维半导体结构1在其中设计的晶体管210数量与二维半导体结构中的晶体管210数量相当基础上，可以缩减三维半导体结构1的平面尺寸，使得三维半导体结构1更加微型化。而对于存储量、存储读取速率要求较高的情况，三维半导体结构1可以维持与二维半导体结构的平面尺寸相当，但其中的晶体管210数量远多于二维半导体结构的晶体管210数量，由此可以显著提升三维半导体结构1的性能。Since the three-dimensional semiconductor structure 1 increases the number of transistors 210 per unit area, in practical applications, when the storage capacity and storage and read rate requirements are low, the number of transistors 210 designed in the three-dimensional semiconductor structure 1 is the same as that of the two-dimensional semiconductor structure. On the basis that the number of transistors 210 in the three-dimensional semiconductor structure 1 is relatively small, the plane size of the three-dimensional semiconductor structure 1 can be reduced, making the three-dimensional semiconductor structure 1 more miniaturized. For situations where the storage capacity and storage and read rate requirements are high, the three-dimensional semiconductor structure 1 can maintain a planar size equivalent to that of the two-dimensional semiconductor structure, but the number of transistors 210 in it is much greater than the number of transistors 210 in the two-dimensional semiconductor structure. This can significantly improve the performance of the three-dimensional semiconductor structure 1 .

可以理解的是，图4示例性的示出了每层存储单元阵列201中相邻的两个存储单元，并且，示出了三维半导体结构1中位于衬底100之上的两层存储单元阵列201。实际应用中，三维半导体结构1中，每层存储单元阵列201中排布的晶体管210例如具有m行n列(m为≥2的正整数，n为≥2的正整数)，且堆叠的存储单元阵列201可以为两层、三层、四层甚至更多层，本实施例对此不作限制。It can be understood that FIG. 4 exemplarily shows two adjacent memory cells in each layer of memory cell array 201, and shows a two-layer memory cell array located above the substrate 100 in the three-dimensional semiconductor structure 1. 201. In practical applications, in the three-dimensional semiconductor structure 1, the transistors 210 arranged in each layer of the memory cell array 201 have, for example, m rows and n columns (m is a positive integer ≥ 2, n is a positive integer ≥ 2), and the stacked memory The cell array 201 may have two layers, three layers, four layers or even more layers, which is not limited in this embodiment.

图5为图4中的三维半导体结构的存储单元的透视图。参照图5所示，图中示出了三维半导体结构1的一个存储单元的结构，以一个存储单元为例，具体的，晶体管210可以包括半导体层211和栅极结构212。FIG. 5 is a perspective view of the memory cell of the three-dimensional semiconductor structure in FIG. 4 . Referring to FIG. 5 , the figure shows the structure of a memory unit of the three-dimensional semiconductor structure 1 . Taking a memory unit as an example, specifically, the transistor 210 may include a semiconductor layer 211 and a gate structure 212 .

半导体层211包括源极区2111、沟道区(图中未示出)和漏极区2113，源极区2111、沟道区和漏极区2113沿半导体层211的长度方向依次设置，以半导体层211沿图中的X方向延伸为例，源极区2111、沟道区和漏极区2113可以沿X方向依次设置。栅极结构212与半导体层211的沟道区接触，且栅极结构212与字线300电连接，字线300通过栅极结构212控制晶体管210的打开与关闭。示例性的，栅极结构212可以连接在半导体层211的沟道区的外壁面，字线300与栅极结构212的背离半导体层211的一侧表面，即，栅极结构212设置在半导体层211和字线300之间。The semiconductor layer 211 includes a source region 2111, a channel region (not shown in the figure) and a drain region 2113. The source region 2111, the channel region and the drain region 2113 are sequentially arranged along the length direction of the semiconductor layer 211 to form a semiconductor layer. For example, the layer 211 extends along the X direction in the figure. The source region 2111, the channel region and the drain region 2113 can be arranged sequentially along the X direction. The gate structure 212 is in contact with the channel region of the semiconductor layer 211, and the gate structure 212 is electrically connected to the word line 300. The word line 300 controls the turning on and off of the transistor 210 through the gate structure 212. For example, the gate structure 212 may be connected to the outer wall surface of the channel region of the semiconductor layer 211, the word line 300 and the side surface of the gate structure 212 away from the semiconductor layer 211, that is, the gate structure 212 is disposed on the semiconductor layer 211. between body layer 211 and word line 300.

其中，栅极结构212例如可以包括栅极介电层(图中未示出)和栅电极层(图中未示出)，栅极介电层为绝缘层，栅电极层例如为金属层，栅极介质层覆盖在沟道区的外壁面，栅电极层覆盖在栅极介质层的外壁面，字线300与栅电极层连接。The gate structure 212 may include, for example, a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure). The gate dielectric layer is an insulating layer, and the gate electrode layer is, for example, a metal layer. The gate dielectric layer covers the outer wall surface of the channel region, the gate electrode layer covers the outer wall surface of the gate dielectric layer, and the word line 300 is connected to the gate electrode layer.

应说明，本实施例以字线300通过栅极结构212控制晶体管210的打开与关闭为例，进行说明。在实际应用中，晶体管210中也可以不设置栅极结构212，而是通过字线300直接控制晶体管210的打开与关闭，本实施例对此不作限制。It should be noted that in this embodiment, the word line 300 controls the turning on and off of the transistor 210 through the gate structure 212 as an example for description. In practical applications, the gate structure 212 may not be provided in the transistor 210, but the opening and closing of the transistor 210 may be directly controlled through the word line 300. This embodiment does not limit this.

示例性的，制作半导体层211时，以初始的层结构为P型掺杂的硅层为例，可以对层结构的两侧对应源极区2111和漏极区2113的部位进行N型掺杂，以初始的层结构为N型掺杂的硅层为例，可以对层结构的中间对应沟道区的部位进行P型掺杂，以形成两侧为N型掺杂的源极区2111和漏极区2113、中间为P型掺杂的沟道区的半导体层211，以使半导体层211具有半导体性质。For example, when making the semiconductor layer 211, taking the initial layer structure as a P-type doped silicon layer, N-type doping can be performed on both sides of the layer structure corresponding to the source region 2111 and the drain region 2113. Taking the initial layer structure as an N-type doped silicon layer as an example, the middle portion of the layer structure corresponding to the channel region can be P-type doped to form source regions 2111 and 2111 with N-type doping on both sides. The drain region 2113 has a semiconductor layer 211 with a P-type doped channel region in the middle, so that the semiconductor layer 211 has semiconductor properties.

至于字线300和位线400与平行于衬底100的平面方向的晶体管210的电连接，字线300可以与栅极结构212的外壁面连接，半导体层211的源极区2111与位线400连接，漏极与电容230连接。字线300上的电压信号作用于栅极结构212，通过栅极结构212向沟道区中注入电荷，导通源极区2111和漏极区2113，将半导体层211导体化，晶体管210打开，将位线400和电容230电连接，通过位线400读取存储在电容230中的数据，或者，通过位线400将数据写入到电容230中进行存储。As for the electrical connection between the word line 300 and the bit line 400 and the transistor 210 parallel to the plane direction of the substrate 100, the word line 300 can be connected to the outer wall surface of the gate structure 212, and the source region 2111 of the semiconductor layer 211 is connected to the bit line 400. connection, the drain is connected to capacitor 230. The voltage signal on the word line 300 acts on the gate structure 212, injects charges into the channel region through the gate structure 212, conducts the source region 2111 and the drain region 2113, conducts the semiconductor layer 211, and turns on the transistor 210. The bit line 400 and the capacitor 230 are electrically connected, and the data stored in the capacitor 230 is read through the bit line 400, or the data is written into the capacitor 230 through the bit line 400 for storage.

参照图5所示，作为一种实施方式，字线300可以与衬底100的平面方向平行，且字线300与栅极结构212的表面接触，以实现字线300与栅极结构212的电连接；此时，位线400可以沿三维半导体结构1的厚度方向(Z方向)延伸，且位线400与半导体层211的源极区2111的外壁面连接，电容230与漏极区2113的外壁面连接。结合图4所示，以半导体层211的长度方向为图中的X方向为例，字线300可以沿图中的Y方向延伸，即，字线300延伸的第一方向为Y方向，字线300与Y方向上的所有晶体管210的栅极结构212连接。Referring to FIG. 5 , as an embodiment, the word line 300 may be parallel to the plane direction of the substrate 100 , and the word line 300 may be in contact with the surface of the gate structure 212 to achieve electrical connection between the word line 300 and the gate structure 212 . connection; at this time, the bit line 400 can extend along the thickness direction (Z direction) of the three-dimensional semiconductor structure 1, and the bit line 400 is connected to the outer wall surface of the source region 2111 of the semiconductor layer 211, and the capacitor 230 is connected to the outer wall surface of the drain region 2113. Wall connection. As shown in FIG. 4 , taking the length direction of the semiconductor layer 211 as the X direction in the figure as an example, the word line 300 can extend along the Y direction in the figure. That is, the first direction in which the word line 300 extends is the Y direction. 300 is connected to the gate structures 212 of all transistors 210 in the Y direction.

作为另一种实施方式，对于栅极结构212覆盖沟道区的沿图中所示Z方向延伸的侧壁面的情况，字线300也可以沿三维半导体结构1的厚度方向(Z方向)延伸，字线300与Z方向上的所有晶体管210的栅极结构212的侧壁面连接。此时，位线400可以沿三维半导体结构1的水平方向延伸，例如，位线400沿图中所示的Y方向延伸，位线400与Y方向上所有晶体管210的源极区2111连接。As another embodiment, when the gate structure 212 covers the sidewall surface of the channel region extending along the Z direction in the figure, the word line 300 may also extend along the thickness direction (Z direction) of the three-dimensional semiconductor structure 1, The word line 300 is connected to the sidewall surfaces of the gate structures 212 of all transistors 210 in the Z direction. this , the bit line 400 may extend along the horizontal direction of the three-dimensional semiconductor structure 1. For example, the bit line 400 extends along the Y direction shown in the figure, and the bit line 400 is connected to the source regions 2111 of all transistors 210 in the Y direction.

其中，为了便于设置位线400和电容230，对于字线300连接于半导体层211的长度方向中间的沟道区的方式，位线400和电容230可以分别连接于半导体层211的长度方向的两端，如此，字线300与位线400之间、字线300与电容230之间均具有适当的间隙，以免相互干扰，此时，电容230可以沿三维半导体结构1的水平方向延伸。沿水平方向延伸的电容230占据的三维半导体结构1的厚度空间较小，可以增大晶体管210在三维半导体结构1的厚度方向上的堆叠密度，提升三维半导体结构1的集成度。Among them, in order to facilitate the arrangement of the bit line 400 and the capacitor 230, in the manner that the word line 300 is connected to the channel region in the middle of the length direction of the semiconductor layer 211, the bit line 400 and the capacitor 230 can be respectively connected to both sides of the length direction of the semiconductor layer 211. In this way, there are appropriate gaps between the word line 300 and the bit line 400 and between the word line 300 and the capacitor 230 to avoid mutual interference. At this time, the capacitor 230 can extend along the horizontal direction of the three-dimensional semiconductor structure 1 . The capacitor 230 extending in the horizontal direction occupies a smaller thickness space of the three-dimensional semiconductor structure 1, which can increase the stacking density of the transistors 210 in the thickness direction of the three-dimensional semiconductor structure 1 and improve the integration level of the three-dimensional semiconductor structure 1.

由于晶体管210悬空在衬底100上方，因而，如前所述，晶体管210容易出现浮体效应，对此，继续参照图5所示，本实施例中，每层存储单元阵列201中均设置有多个连接垫220，连接垫220在存储单元阵列201中也阵列排布，每个晶体管210均有对应的连接垫220与其连接，连接垫220和半导体层211的沟道区电连接，并且，连接垫220与衬底100电连接，连接垫220用于使沟道区内残留的电荷流动至衬底100，通过接地的衬底100排出，解决晶体管210的浮体效应，提升三维半导体结构1的性能。Since the transistor 210 is suspended above the substrate 100, as mentioned above, the transistor 210 is prone to a floating body effect. In this regard, continue to refer to FIG. 5. In this embodiment, each layer of the memory cell array 201 is provided with multiple The connection pads 220 are also arranged in an array in the memory cell array 201. Each transistor 210 has a corresponding connection pad 220 connected to it. The connection pads 220 are electrically connected to the channel region of the semiconductor layer 211, and are connected The pad 220 is electrically connected to the substrate 100. The connection pad 220 is used to allow the residual charges in the channel region to flow to the substrate 100 and be discharged through the grounded substrate 100, thereby solving the floating body effect of the transistor 210 and improving the performance of the three-dimensional semiconductor structure 1. .

具体的，对于沿衬底100的水平方向延伸的半导体层211，为了便于连接垫220的设置和形成，连接垫220可以与半导体层211同层设置，例如，连接垫220可以设置在半导体层211的宽度方向的侧方，并且，连接垫220与半导体层211的侧壁连接，以此实现与半导体层211的沟道区的电连接，将沟道区残留的电荷引导至衬底100并排出。Specifically, for the semiconductor layer 211 extending along the horizontal direction of the substrate 100, in order to facilitate the arrangement and formation of the connection pad 220, the connection pad 220 can be provided on the same layer as the semiconductor layer 211. For example, the connection pad 220 can be provided on the semiconductor layer 211. side of the width direction, and the connection pads 220 are connected to the sidewalls of the semiconductor layer 211 to achieve electrical connection with the channel region of the semiconductor layer 211, and guide the residual charges in the channel region to the substrate 100 and discharge them .

通过使连接垫220与半导体层211同层设置，连接垫220不占据三维半导体结构1的额外的厚度空间(Z向空间)，在保持三维半导体结构1的厚度不变的情况下，可以叠设更多层存储单元阵列201，可以提高三维半导体结构1的集成度，提升三维半导体结构1的性能。By arranging the connection pads 220 and the semiconductor layer 211 in the same layer, the connection pads 220 do not occupy the extra thickness space (Z-direction space) of the three-dimensional semiconductor structure 1, and can be stacked while keeping the thickness of the three-dimensional semiconductor structure 1 unchanged. More layers of memory cell arrays 201 can increase the integration level of the three-dimensional semiconductor structure 1 and improve the performance of the three-dimensional semiconductor structure 1 .

至于连接垫220的形成，示例性的，连接垫220可以和半导体层211同步形成，例如，连接垫220和半导体层211为一体成型结构，连接垫220也可以为P型掺杂的硅层，形成连接垫220和半导体层211时，可以先整体形成P型掺杂的硅层，之后，对源极区2111和漏极区2113所在的部位进行N型掺杂，以形成半导体层211的源极区2111和漏极区2113，源极区2111和漏极区2113之间的区域作为沟道区，沟道区侧方的区域作为连接垫220。As for the formation of the connection pad 220, for example, the connection pad 220 can be formed simultaneously with the semiconductor layer 211. For example, the connection pad 220 and the semiconductor layer 211 are an integrally formed structure, and the connection pad 220 can also be a P-type doped silicon layer. When forming the connection pad 220 and the semiconductor layer 211, a P-type doped silicon layer can be formed as a whole first, and then N-type doping is performed on the source region 2111 and the drain region 2113 to form the source of the semiconductor layer 211. The area between the electrode region 2111 and the drain region 2113, and the source region 2111 and the drain region 2113 The region serves as the channel region, and the area on the side of the channel region serves as the connection pad 220 .

其中，连接垫220应保持较为均匀的低浓度的P型掺杂，在半导体层211的源极区2111和漏极区2113与连接垫220之间具有界面时，以免形成PN结。示例性的，对半导体层211的源极区2111和漏极区2113对应的区域进行N型掺杂时，可以遮盖住连接垫220的表面，以免对连接垫220的掺杂性质造成影响。The connection pad 220 should maintain a relatively uniform low-concentration P-type doping to avoid forming a PN junction when there is an interface between the source region 2111 and the drain region 2113 of the semiconductor layer 211 and the connection pad 220 . For example, when N-type doping is performed on the regions corresponding to the source region 2111 and the drain region 2113 of the semiconductor layer 211 , the surface of the connection pad 220 may be covered to avoid affecting the doping properties of the connection pad 220 .

另外，连接垫220的厚度可以和半导体层211的厚度相同，即，沿衬底100的厚度方向(Z方向)，连接垫220的高度和半导体层211的高度相同。如此，对于和半导体层211为一体成型结构的连接垫220，便于连接垫220的成型，并且，对于形成在半导体层211和连接垫220上的栅极结构212和字线300，也便于栅极结构212和字线300的形成。In addition, the thickness of the connection pad 220 may be the same as the thickness of the semiconductor layer 211 , that is, along the thickness direction (Z direction) of the substrate 100 , the height of the connection pad 220 and the height of the semiconductor layer 211 are the same. In this way, for the connection pad 220 that is an integrally formed structure with the semiconductor layer 211, it is convenient to form the connection pad 220, and for the gate structure 212 and the word line 300 formed on the semiconductor layer 211 and the connection pad 220, it is also convenient to form the gate electrode. Formation of structure 212 and word line 300.

图6为图4中的三维半导体结构的B-B处的剖视图。结合图4和图6所示，设置连接垫220时，可以对每个半导体层211均设置单独的连接垫220，即，连接垫220与半导体层211一一对应设置，各连接垫220与对应的半导体层211的宽度方向的侧壁面连接。此时，对于沿半导体层211的宽度方向(Y方向)间隔排列的各半导体层211，在半导体层211的宽度方向(Y方向)上，半导体层211和连接垫220交替设置。FIG. 6 is a cross-sectional view along B-B of the three-dimensional semiconductor structure in FIG. 4 . As shown in FIG. 4 and FIG. 6 , when the connection pads 220 are provided, a separate connection pad 220 can be provided for each semiconductor layer 211 , that is, the connection pads 220 and the semiconductor layers 211 are provided in one-to-one correspondence, and each connection pad 220 is corresponding to the corresponding connection pad 220 . The side wall surfaces of the semiconductor layer 211 in the width direction are connected. At this time, for each of the semiconductor layers 211 arranged at intervals along the width direction of the semiconductor layer 211 (Y direction), the semiconductor layers 211 and the connection pads 220 are alternately provided in the width direction of the semiconductor layer 211 (Y direction).

以下将连接垫220的宽度方向的两侧表面分别定义为其第一侧面220a和其第二侧面220b，即，连接垫220的第一侧面220a与位于其一侧的半导体层211相对，连接垫220的第二侧面220b与位于其另一侧的半导体层211相对。In the following, the two sides of the connection pad 220 in the width direction are respectively defined as the first side 220a and the second side 220b. That is, the first side 220a of the connection pad 220 is opposite to the semiconductor layer 211 on one side thereof. The second side 220b of 220 is opposite to the semiconductor layer 211 located on the other side thereof.

为了实现连接垫220与半导体层211一一对应连接，各连接垫220均与位于其同一侧的半导体层211的侧壁面连接，例如图6中所示方向为例，连接垫220的左侧为其第一侧面220a，连接垫220的右侧为其第二侧面220b，可以是连接垫220的第一侧面220a与位于其左侧的半导体层211连接，连接垫220的第二侧面220b与位于其右侧的半导体层211之间具有间隙。当然，也可以是连接垫220的第二侧面220b与位于其右侧的半导体层211连接，连接垫220的第一侧面220a与位于其左侧的半导体层211之间具有间隙，本实施例对此不作限制。In order to achieve a one-to-one connection between the connection pads 220 and the semiconductor layer 211, each connection pad 220 is connected to the side wall surface of the semiconductor layer 211 located on the same side. For example, in the direction shown in FIG. 6, the left side of the connection pad 220 is The first side 220a of the connection pad 220 is the second side 220b on the right side of the connection pad 220. The first side 220a of the connection pad 220 is connected to the semiconductor layer 211 on the left side, and the second side 220b of the connection pad 220 is connected to the semiconductor layer 211 on the left side. There is a gap between the semiconductor layers 211 on the right side. Of course, it is also possible that the second side 220b of the connection pad 220 is connected to the semiconductor layer 211 on the right side, and there is a gap between the first side 220a of the connection pad 220 and the semiconductor layer 211 on the left side. In this embodiment, This is not a restriction.

图7为本公开实施例提供的另一种三维半导体结构对应图4中B-B处的剖视图。参照图7所示，在一些实施方式中，半导体层211和连接垫220依然可以交替设置，但连接垫220并非和半导体层211一一对应连接，此时，连接垫220的宽度可以延伸至与位于其两侧的半导体层211均连接，即，连接垫220的第一侧面220a和第二侧面220b分别与两侧的半导体层211的相应侧壁面连接，连接垫220可以将位于其两侧的半导体层211的沟道区2112中残留的电荷均引导至衬底100并排出。FIG. 7 is a cross-sectional view corresponding to BB in FIG. 4 of another three-dimensional semiconductor structure provided by an embodiment of the present disclosure. Referring to FIG. 7 , in some embodiments, the semiconductor layer 211 and the connection pad 220 can still be arranged alternately, but the connection pad 220 is not connected to the semiconductor layer 211 in a one-to-one correspondence. At this time, the width of the connection pad 220 can extend to The semiconductor layers 211 located on both sides thereof are connected, that is, the third connection pad 220 One side 220a and the second side 220b are respectively connected to the corresponding sidewall surfaces of the semiconductor layer 211 on both sides. The connection pad 220 can guide the remaining charges in the channel region 2112 of the semiconductor layer 211 on both sides to the substrate 100 and discharge.

图8为本公开实施例提供的第三种三维半导体结构对应图4中B-B处的剖视图。参照图8所示，在其他实施方式中，连接垫220也可以不用和半导体层211交替设置，可以是每两个半导体层211之间设置一个连接垫220，连接垫220与两侧的半导体层211均连接，即，连接垫220的第一侧面220a和第二侧面220b分别与两侧的半导体层211的相应侧壁面连接，连接垫220将位于其两侧的半导体层211的沟道区2112中残留的电荷均引导至衬底100并排出。FIG. 8 is a cross-sectional view corresponding to B-B in FIG. 4 of the third three-dimensional semiconductor structure provided by an embodiment of the present disclosure. Referring to FIG. 8 , in other embodiments, the connection pads 220 do not need to be provided alternately with the semiconductor layers 211 . Instead, one connection pad 220 may be provided between every two semiconductor layers 211 , and the connection pads 220 are connected to the semiconductor layers on both sides. 211 are connected, that is, the first side 220a and the second side 220b of the connection pad 220 are respectively connected to the corresponding side wall surfaces of the semiconductor layer 211 on both sides, and the connection pad 220 connects the channel regions 2112 of the semiconductor layer 211 on both sides of it. The remaining charges are guided to the substrate 100 and discharged.

由于连接垫220沿三维半导体结构1的水平方向同层设置在半导体层211的宽度方向的侧方，半导体层211的至少沟道区2112的宽度方向的侧壁面用于和连接垫220连接，对于半导体层211的宽度方向的两侧壁面均与连接垫220连接的情况，沟道区2112的宽度方向的侧壁面无法覆盖栅极结构212，对于半导体层211的宽度方向的一侧壁面与连接垫220连接的情况，处于提高集成度的密度，连接垫220与相邻的半导体层211之间的间隙也较小，为便于栅极结构212的形成，也可使栅极结构212不覆盖沟道区2112的侧壁面。Since the connection pads 220 are arranged in the same layer on the sides of the semiconductor layer 211 in the width direction along the horizontal direction of the three-dimensional semiconductor structure 1, at least the sidewall surfaces of the channel region 2112 in the width direction of the semiconductor layer 211 are used to connect with the connection pads 220. When both side wall surfaces in the width direction of the semiconductor layer 211 are connected to the connection pads 220, the side wall surfaces in the width direction of the channel region 2112 cannot cover the gate structure 212. For one side wall surface in the width direction of the semiconductor layer 211 and the connection pads In the case of 220 connection, the density of integration is increased, and the gap between the connection pad 220 and the adjacent semiconductor layer 211 is also small. In order to facilitate the formation of the gate structure 212, the gate structure 212 can also be made not to cover the channel. The side wall surface of area 2112.

其中，栅极结构212可以仅覆盖半导体层211沟道区2112的厚度方向的表面，或者，栅极结构212也可以延伸至覆盖连接垫220的部分表面。应说明，参照图6所示，对于连接垫220与相邻的半导体层211之间具有间距的情况，栅极结构212可以延伸至覆盖连接垫220的部分宽度区域，或者栅极结构212也可以延伸至覆盖连接垫220的整个宽度区域。参照图7所示，对于连接垫220的第一侧面220a和第二侧面220b分别与两侧的半导体层211连接的情况，栅极结构212只能延伸至覆盖连接垫220的部分宽度区域，以将相邻晶体管210的栅极结构212之间隔离开。The gate structure 212 may only cover the surface of the channel region 2112 of the semiconductor layer 211 in the thickness direction, or the gate structure 212 may also extend to cover part of the surface of the connection pad 220 . It should be noted that, referring to FIG. 6 , when there is a gap between the connection pad 220 and the adjacent semiconductor layer 211 , the gate structure 212 can extend to cover part of the width area of the connection pad 220 , or the gate structure 212 can also Extending to cover the entire width area of the connection pad 220 . Referring to FIG. 7 , when the first side 220 a and the second side 220 b of the connection pad 220 are respectively connected to the semiconductor layers 211 on both sides, the gate structure 212 can only extend to cover part of the width area of the connection pad 220 . Gate structures 212 of adjacent transistors 210 are isolated from each other.

因此，参照图5所示，本实施例中，栅极结构212可以覆盖在沟道区的厚度方向的表面，也就是说，栅极结构212覆盖在沟道区的朝向衬底100的一侧表面和背离衬底100的一侧表面中的至少一者。为了使字线300能够与沿晶体管210的宽度方向(Y方向)间隔的各晶体管210栅极结构212连接，本实施例中，字线300可以沿三维半导体结构1的平面方向延伸，具体可以沿字线300的宽度方向(Y方向)延伸，相应的，位线400可以沿三维半导体的厚度方向 (Z方向)延伸。Therefore, as shown in FIG. 5 , in this embodiment, the gate structure 212 may cover the surface of the channel region in the thickness direction, that is, the gate structure 212 covers the side of the channel region facing the substrate 100 At least one of the surface and the side surface facing away from the substrate 100 . In order to enable the word line 300 to be connected to the gate structures 212 of each transistor 210 spaced along the width direction (Y direction) of the transistor 210, in this embodiment, the word line 300 can extend along the plane direction of the three-dimensional semiconductor structure 1, specifically along the The word line 300 extends in the width direction (Y direction). Correspondingly, the bit line 400 can extend along the thickness direction of the three-dimensional semiconductor. (Z direction) extension.

以图5中所示的三维半导体结构1为例，栅极结构212覆盖在半导体层211的背离衬底100的一侧表面，相应的，字线300设置在晶体管210的背离衬底100的一侧表面，字线300连接在栅极结构212上方。在其他实施方式中，栅极结构212也可以覆盖在半导体层211的朝向衬底100的一侧表面，相应的，字线300设置在晶体管210的朝向衬底100的一侧表面，字线300连接在栅极结构212下方。或者，半导体层211的厚度方向的两侧表面均设置有栅极结构212，相应的，对应沿晶体管210的宽度方向(Y方向)间隔设置的一排晶体管210可以设置两条字线300，一条字线300连接在背离衬底100的栅极结构212上方，另一条字线300连接在朝向衬底100的栅极结构212下方。Taking the three-dimensional semiconductor structure 1 shown in FIG. 5 as an example, the gate structure 212 covers the side surface of the semiconductor layer 211 facing away from the substrate 100. Correspondingly, the word line 300 is disposed on a side of the transistor 210 facing away from the substrate 100. On the side surface, the word line 300 is connected above the gate structure 212 . In other embodiments, the gate structure 212 may also cover the side surface of the semiconductor layer 211 facing the substrate 100 . Correspondingly, the word line 300 is disposed on the side surface of the transistor 210 facing the substrate 100 . The word line 300 connected beneath gate structure 212 . Alternatively, gate structures 212 can be provided on both sides of the semiconductor layer 211 in the thickness direction. Correspondingly, two word lines 300 can be provided corresponding to a row of transistors 210 spaced along the width direction (Y direction) of the transistors 210 . The word line 300 is connected above the gate structure 212 facing away from the substrate 100 , and the other word line 300 is connected below the gate structure 212 facing the substrate 100 .

继续参照图5所示，为了实现连接垫220与衬底100的电连接，三维半导体结构1中还设置有阵列排布有多个连接立柱500，结合图4所示，连接立柱500的底部连接在衬底100上，连接立柱500可以沿三维半导体结构1的厚度方向(Z方向)延伸，并沿三维半导体结构1的平面方向阵列排布。例如，各连接立柱500与沿衬底100的平面方向阵列的各连接垫220对应，且连接立柱500贯穿堆叠结构200，连接立柱500的相应部位与Z方向上的各连接垫220连接，以将Z方向上的各连接垫220电连接至衬底100，实现将Z方向上的各半导体层211的沟道区的残留电荷引导至衬底100并排出。Continuing to refer to FIG. 5 , in order to achieve electrical connection between the connection pads 220 and the substrate 100 , the three-dimensional semiconductor structure 1 is also provided with a plurality of connection posts 500 arranged in an array. As shown in FIG. 4 , the bottom connections of the connection posts 500 are On the substrate 100 , the connection pillars 500 may extend along the thickness direction (Z direction) of the three-dimensional semiconductor structure 1 and be arranged in an array along the plane direction of the three-dimensional semiconductor structure 1 . For example, each connection post 500 corresponds to each connection pad 220 arrayed along the plane direction of the substrate 100, and the connection post 500 penetrates the stacked structure 200, and the corresponding part of the connection post 500 is connected to each connection pad 220 in the Z direction to connect Each connection pad 220 in the Z direction is electrically connected to the substrate 100 to guide the residual charges in the channel region of each semiconductor layer 211 in the Z direction to the substrate 100 and discharge them.

其中，为了提高三维半导体结构1的集成度，本实施例中，连接立柱500可以不占据单独的平面空间，例如，在三维半导体结构1的平面方向上，连接立柱500可以位于连接垫220所在的平面空间内。此时，连接立柱500可以贯穿连接垫220设置，即，连接立柱500***连接垫220内，连接垫220包裹在连接立柱500的外周，以此实现连接垫220和连接立柱500的连接。In order to improve the integration of the three-dimensional semiconductor structure 1, in this embodiment, the connection pillars 500 may not occupy a separate plane space. For example, in the plane direction of the three-dimensional semiconductor structure 1, the connection pillars 500 may be located where the connection pads 220 are located. in flat space. At this time, the connecting column 500 can be disposed through the connecting pad 220 , that is, the connecting column 500 is inserted into the connecting pad 220 , and the connecting pad 220 is wrapped around the outer periphery of the connecting column 500 , thereby realizing the connection between the connecting pad 220 and the connecting column 500 .

对此，继续参照图5所示，由于连接垫220连接在半导体层211的宽度方向的侧方，为减小连接垫220占据的平面空间，提高三维半导体结构1的集成度，连接垫220可以沿半导体层211的长度方向延伸，连接垫220的延伸长度可以小于半导体层211的长度，或者，连接垫220也可以延伸至其两端与半导体层211的两端平齐。In this regard, continuing to refer to FIG. 5 , since the connection pads 220 are connected to the sides in the width direction of the semiconductor layer 211 , in order to reduce the plane space occupied by the connection pads 220 and improve the integration of the three-dimensional semiconductor structure 1 , the connection pads 220 can be Extending along the length direction of the semiconductor layer 211 , the extension length of the connection pad 220 may be less than the length of the semiconductor layer 211 , or the connection pad 220 may also extend until its two ends are flush with the two ends of the semiconductor layer 211 .

其中，连接垫220可以包括主体部221和连接部222，主体部221对应位于沟道区的侧方，连接部222位于主体部221的侧方，主体部221用于实现和沟道区的电连接，字线300覆盖在主体部221上，连接部222暴露在字线300之外，连接部222用于和连接立柱500连接，例如，连接立柱500可以贯穿连接部222，以实现将沟道区内残留的电荷引导至衬底100。The connection pad 220 may include a main body 221 and a connecting part 222. The main part 221 is located on the side of the channel area, and the connecting part 222 is located on the side of the main part 221. The main part 221 is used to realize the connection with the channel. The word line 300 covers the main body part 221, and the connection part 222 is exposed outside the word line 300. The connection part 222 is used to connect with the connection post 500. For example, the connection post 500 can penetrate the connection part 222 to achieve Charges remaining in the channel region are guided to the substrate 100 .

图5中示出了连接垫220延伸至其两端与半导体层211的两端平齐的情况，连接垫220的主体部221两侧的区域均为连接部222，为便于说明，将连接垫220上与半导体层211的源极区2111对应的区域定义为第一连接部2221，将连接垫220上与半导体层211的漏极区2113对应的区域定义为第二连接部2222。由于连接垫220具有位于主体部221两侧的第一连接部2221和第二连接部2222，因此，连接垫220可以通过第一连接部2221和第二连接部2222中的至少一者与衬底100电连接。例如，对应Z方向上的各连接垫220可以设置一根连接立柱500，连接立柱500贯穿第一连接部2221或第二连接部2222；或者，对应Z方向上的连接垫220可以设置两根连接立柱500，两根连接立柱500分别贯穿第一连接部2221和第二连接部2222。FIG. 5 shows the connection pad 220 extending until its two ends are flush with the two ends of the semiconductor layer 211 . The areas on both sides of the main body 221 of the connection pad 220 are connection parts 222 . For the convenience of explanation, the connection pads are The region on the connection pad 220 corresponding to the source region 2111 of the semiconductor layer 211 is defined as the first connection portion 2221, and the region on the connection pad 220 corresponding to the drain region 2113 of the semiconductor layer 211 is defined as the second connection portion 2222. Since the connection pad 220 has the first connection part 2221 and the second connection part 2222 located on both sides of the main body part 221, the connection pad 220 can be connected to the substrate through at least one of the first connection part 2221 and the second connection part 2222. 100 electrical connections. For example, one connection post 500 can be provided corresponding to each connection pad 220 in the Z direction, and the connection post 500 penetrates the first connection part 2221 or the second connection part 2222; or, two connection posts 500 can be provided corresponding to the connection pads 220 in the Z direction. The upright column 500 and the two connecting upright columns 500 respectively penetrate the first connecting part 2221 and the second connecting part 2222.

图9为另一种三维半导体结构的存储单元的透视图。参照图9所示，图中示出了连接垫220的延伸长度小于半导体层211的长度的情况，具体的，连接垫220沿其长度方向上对应半导体层211的沟道区和漏极区2113，也就是说，连接垫220的连接部222仅与漏极区2113对应，此时，对应Z方向的连接垫220可以设置一根连接立柱500，该连接立柱500贯穿连接垫220的对应漏极区2113的连接部222。Figure 9 is a perspective view of a memory cell of another three-dimensional semiconductor structure. Referring to FIG. 9 , the figure shows a situation where the extension length of the connection pad 220 is less than the length of the semiconductor layer 211 . Specifically, the connection pad 220 corresponds to the channel region and the drain region 2113 of the semiconductor layer 211 along its length direction. , that is to say, the connection portion 222 of the connection pad 220 only corresponds to the drain region 2113. At this time, the connection pad 220 corresponding to the Z direction can be provided with a connection column 500, and the connection column 500 penetrates the corresponding drain of the connection pad 220. Connection portion 222 of area 2113.

在其他实施方式中，连接垫220沿其长度方向也可以对应半导体层211的源极区2111和漏极区2113，也就是说，连接垫220的连接部222仅与源极区2111对应，此时，对应Z方向的连接垫220可以设置一根连接柱，该连接柱贯穿连接垫220的对应源极区2111的连接部222。In other embodiments, the connection pad 220 may also correspond to the source region 2111 and the drain region 2113 of the semiconductor layer 211 along its length direction. That is to say, the connection portion 222 of the connection pad 220 only corresponds to the source region 2111. When the connection pad 220 corresponds to the Z direction, a connection post may be provided, and the connection post penetrates the connection portion 222 of the connection pad 220 corresponding to the source region 2111.

另外，图4中未示出的是，堆叠结构200还包括多个支撑层(图中未示出)和多个隔离层(图中未示出)。支撑层和存储单元阵列201沿三维半导体结构1的厚度方向(Z方向)依次交替的堆叠在衬底100上；隔离层沿三维半导体结构1的平面方向阵列排布，且隔离层沿三维半导体结构1的厚度方向(Z方向)间隔设置，隔离层位于相邻晶体管210之间，并填充堆叠结构200的剩余间隙。In addition, what is not shown in FIG. 4 is that the stacked structure 200 also includes a plurality of support layers (not shown in the figure) and a plurality of isolation layers (not shown in the figure). The support layer and the memory cell array 201 are alternately stacked on the substrate 100 along the thickness direction (Z direction) of the three-dimensional semiconductor structure 1; the isolation layer is arranged in an array along the plane direction of the three-dimensional semiconductor structure 1, and the isolation layer is arranged along the plane direction of the three-dimensional semiconductor structure 1. 1 is spaced apart in the thickness direction (Z direction), and the isolation layer is located between adjacent transistors 210 and fills the remaining gaps of the stacked structure 200 .

需要说明的是，设置支撑层，一方面便于存储单元阵列201在三维半导体结构1的厚度方向(Z方向)上堆叠，以便于对存储单元阵列201进行支撑；另一方面，可以使相邻存储单元阵列201之间电性隔离。设置隔离层，可以使相邻晶体管210之间电性隔离，避免晶体管210相互干扰。It should be noted that the support layer is provided to facilitate stacking of the memory cell array 201 in the thickness direction (Z direction) of the three-dimensional semiconductor structure 1 on the one hand and to support the memory cell array 201 on the other hand; On the one hand, adjacent memory cell arrays 201 can be electrically isolated. Providing an isolation layer can electrically isolate adjacent transistors 210 and prevent the transistors 210 from interfering with each other.

本实施例还提供一种三维半导体结构1的制作方法，该三维半导体结构1的制作方法可以用于制作上述的三维半导体结构1。This embodiment also provides a method for manufacturing the three-dimensional semiconductor structure 1. The method for manufacturing the three-dimensional semiconductor structure 1 can be used to manufacture the above-mentioned three-dimensional semiconductor structure 1.

图10为本公开实施例提供的三维半导体结构的制作方法的步骤流程图。参照图10所示，该三维半导体结构1的制作方法包括：FIG. 10 is a flowchart of steps of a method for manufacturing a three-dimensional semiconductor structure provided by an embodiment of the present disclosure. Referring to FIG. 10 , the manufacturing method of the three-dimensional semiconductor structure 1 includes:

S100、提供衬底。S100. Provide a substrate.

结合图4所示，首先提供一衬底100，衬底100的材料可以是单晶硅、多晶硅、无定型硅、硅锗化合物或绝缘体上硅等，或者，衬底100的材料还可以是本领域技术人员已知的其他材料。As shown in FIG. 4 , a substrate 100 is first provided. The material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon on insulator. Alternatively, the material of the substrate 100 can also be the present invention. Other materials known to those skilled in the art.

S200、在衬底上形成堆叠结构；堆叠结构包括沿衬底的厚度方向堆叠的多个存储单元阵列，每个存储单元阵列包括沿衬底的平面方向阵列排布的多个晶体管和多个连接垫；其中，S200. Form a stacked structure on the substrate; the stacked structure includes multiple memory cell arrays stacked along the thickness direction of the substrate, and each memory cell array includes multiple transistors and multiple connections arranged in an array along the plane direction of the substrate. pad; among them,

结合图4所示，形成堆叠结构200时，可以先在衬底100上依次形成叠设的多个叠层，以三维半导体结构1包括层叠的四层存储单元阵列201为例，可以在衬底100上依次形成四层叠层，每层叠层例如可以包括依次层叠的绝缘层和半导体材料层，半导体材料层可以由半导体材料(例如硅、锗或硅锗)形成，绝缘层可以由硅氧化物、硅氮化物或硅氮氧化物中的至少一种形成。As shown in FIG. 4 , when forming the stacked structure 200 , multiple stacked layers may be formed sequentially on the substrate 100 . Taking the three-dimensional semiconductor structure 1 including a stacked four-layer memory cell array 201 as an example, the stacked structure 200 may be formed on the substrate 100 . Four stacked layers are sequentially formed on 100. Each stacked layer may include, for example, a sequentially stacked insulating layer and a semiconductor material layer. The semiconductor material layer may be formed of a semiconductor material (such as silicon, germanium or silicon germanium), and the insulating layer may be made of silicon oxide, At least one of silicon nitride or silicon oxynitride is formed.

其中，绝缘层例如可以作为间隔在各层存储单元阵列201之间的支撑层，半导体材料层用于形成各晶体管210的半导体层211。The insulating layer can, for example, serve as a support layer between each layer of the memory cell array 201 , and the semiconductor material layer is used to form the semiconductor layer 211 of each transistor 210 .

结合图4所示，形成多个叠层之后，通过光刻工艺使半导体材料层图案化，形成各晶体管210的半导体层211和各连接垫220，其中，每层半导体材料层图案化为沿衬底100的平面方向阵列排布的多个半导体层211和多个连接垫220，沿衬底100的厚度方向层叠的各层半导体材料层图案化形成的各半导体层211和各连接垫220沿衬底100的厚度方向(Z方向)间隔设置。As shown in FIG. 4 , after forming multiple stacked layers, the semiconductor material layer is patterned through a photolithography process to form the semiconductor layer 211 of each transistor 210 and the connection pads 220 , wherein each layer of semiconductor material layer is patterned along the substrate. A plurality of semiconductor layers 211 and a plurality of connection pads 220 are arranged in an array in the plane direction of the substrate 100. Each semiconductor layer 211 and each connection pad 220 are patterned and formed by stacking semiconductor material layers along the thickness direction of the substrate 100 along the substrate 100. The bottom 100 is provided at intervals in the thickness direction (Z direction).

示例性的，半导体材料层图案化后，形成的每个图案包括对应晶体管210的半导体层211的区域和对应连接垫220的区域，以半导体材料层为P型掺杂的硅层为例，半导体材料层图案化后，可以在遮盖住每个图案对应晶体管210的半导体层211的区域和对应连接垫220的区域，在图案上对应半导体层211的源极区2111和漏极区2113的区域进行N型掺杂，以形成半导体层211的源极区2111和漏极区2113。Exemplarily, after the semiconductor material layer is patterned, each pattern formed includes an area corresponding to the semiconductor layer 211 of the transistor 210 and an area corresponding to the connection pad 220, and the semiconductor material layer is P-type doped. Taking the silicon layer as an example, after the semiconductor material layer is patterned, the area of the semiconductor layer 211 corresponding to the transistor 210 and the area corresponding to the connection pad 220 of each pattern can be covered, and the source region 2111 and drain region of the semiconductor layer 211 can be patterned. The area of the electrode region 2113 is N-type doped to form the source region 2111 and the drain region 2113 of the semiconductor layer 211 .

形成晶体管210的半导体层211和连接垫220之后，再在堆叠结构200中形成连接在各晶体管210的栅极结构212，栅极结构212连接在半导体层211朝向衬底100的一侧表面和背离衬底100的一侧表面中的至少一者，以在堆叠结构200中形成各晶体管210。形成各晶体管210之后，在各晶体管210之间的间隙填充绝缘材料，以使晶体管210之间保持电性隔离。After forming the semiconductor layer 211 and the connection pad 220 of the transistor 210, a gate structure 212 connected to each transistor 210 is formed in the stacked structure 200. The gate structure 212 is connected to the side surface of the semiconductor layer 211 facing the substrate 100 and away from the substrate 100. At least one of one side surfaces of the substrate 100 to form each transistor 210 in the stacked structure 200 . After each transistor 210 is formed, an insulating material is filled in the gap between the transistors 210 to maintain electrical isolation between the transistors 210 .

之后，再形成与各晶体管210的栅极结构212连接的各字线300，并且，形成贯穿堆叠结构200的各位线400和连接立柱500。最后，再在堆叠结构200中形成各电容230，使电容230与各晶体管210的半导体层211的漏极区2113连接。Afterwards, each word line 300 connected to the gate structure 212 of each transistor 210 is formed, and each bit line 400 and connection pillar 500 penetrating the stacked structure 200 are formed. Finally, each capacitor 230 is formed in the stacked structure 200 so that the capacitor 230 is connected to the drain region 2113 of the semiconductor layer 211 of each transistor 210 .

在本公开的描述中，需要说明的是，文中使用的术语“层”可以指包括具有一定厚度的区域的材料部分。层可以在整个的下层结构或上覆结构之上延伸，或者可以具有比下层或上覆结构的范围小的范围。此外，层可以是匀质或者非匀质的连续结构的一个区域，其厚度小于该连续结构的厚度。例如，层可以位于连续结构的顶表面和底表面之间或者顶表面和底表面处的任何成对的横向平面之间。层可以横向延伸、垂直延伸和/或沿锥形表面延伸。衬底可以是层，可以在其中包括一个或多个层，和/或可以具有位于其上、其以上和/或其以下的一个或多个层。层可以包括多个层。例如，互连层可以包括一个或多个导体和接触层(在其内形成触点、互连线和/或过孔)以及一个或多个电介质层。In the description of the present disclosure, it should be noted that the term "layer" used herein may refer to a material portion including a region having a certain thickness. A layer may extend over the entire underlying or overlying structure, or may have an extent that is smaller than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pairs of transverse planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers on, above, and/or below it. A layer may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers within which contacts, interconnect lines, and/or vias are formed, and one or more dielectric layers.

需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。It should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", The orientations or positional relationships indicated by "right", "vertical", "horizontal", "top", "bottom", "inside", "outer", etc. are based on the orientations or positional relationships shown in the accompanying drawings and are only for The disclosure is facilitated and simplified, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as a limitation on the disclosure.

最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。 Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it; although the present disclosure has been described in detail with reference to the foregoing embodiments, those in the art Those of ordinary skill should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions. Disclose the scope of the technical solutions of each embodiment.

Claims

一种三维半导体结构，包括：A three-dimensional semiconductor structure including:

衬底(100)；substrate(100);

堆叠结构(200)，位于所述衬底(100)上，包括沿所述衬底(100)的厚度方向堆叠的多个存储单元阵列(201)，每个所述存储单元阵列(201)包括沿所述衬底(100)的平面方向阵列排布的多个晶体管(210)和多个连接垫(220)；其中，A stacked structure (200), located on the substrate (100), includes a plurality of memory cell arrays (201) stacked along the thickness direction of the substrate (100), each of the memory cell arrays (201) includes A plurality of transistors (210) and a plurality of connection pads (220) arranged in an array along the plane direction of the substrate (100); wherein,

所述晶体管(210)包括沿所述衬底(100)的平面方向延伸的半导体层(211)，所述半导体层(211)沿其长度方向依次设置有源极区(2111)、沟道区(2112)和漏极区(2113)；所述连接垫(220)设置于所述半导体层(211)的宽度方向的侧方并与所述半导体层(211)连接，所述连接垫(220)与所述沟道区(2112)电连接，且所述连接垫(220)与所述衬底(100)电连接。The transistor (210) includes a semiconductor layer (211) extending along the plane direction of the substrate (100). The semiconductor layer (211) is sequentially provided with a source region (2111) and a channel region along its length direction. (2112) and the drain region (2113); the connection pad (220) is disposed on the side of the semiconductor layer (211) in the width direction and is connected to the semiconductor layer (211). The connection pad (220) ) is electrically connected to the channel region (2112), and the connection pad (220) is electrically connected to the substrate (100).
根据权利要求1所述的三维半导体结构，其中，沿所述半导体层(211)的宽度方向，所述连接垫(220)与所述半导体层(211)交替设置。The three-dimensional semiconductor structure according to claim 1, wherein the connection pads (220) and the semiconductor layer (211) are alternately arranged along the width direction of the semiconductor layer (211).
根据权利要求2所述的三维半导体结构，其中，所述连接垫(220)与位于其两侧的所述半导体层(211)相对的侧面分别为第一侧面(220a)和第二侧面(220b)，所述第一侧面(220a)与相对的所述半导体层(211)连接，所述第二侧面(220b)与相对的所述半导体层(211)之间具有间隙。The three-dimensional semiconductor structure according to claim 2, wherein the sides of the connection pad (220) opposite to the semiconductor layer (211) located on both sides thereof are a first side (220a) and a second side (220b) respectively. ), the first side (220a) is connected to the opposite semiconductor layer (211), and there is a gap between the second side (220b) and the opposite semiconductor layer (211).
根据权利要求2所述的三维半导体结构，其中，所述连接垫(220)与位于其两侧的所述半导体层(211)均连接。The three-dimensional semiconductor structure according to claim 2, wherein the connection pad (220) is connected to the semiconductor layer (211) on both sides thereof.
根据权利要求1所述的三维半导体结构，其中，每两个所述半导体层(211)之间设有一个所述连接垫(220)，所述连接垫(220)与位于其两侧的所述半导体层(211)均连接。The three-dimensional semiconductor structure according to claim 1, wherein one connection pad (220) is disposed between each two semiconductor layers (211), and the connection pad (220) is connected to all the connection pads located on both sides thereof. The semiconductor layers (211) are all connected.
根据权利要求1-5任一项所述的三维半导体结构，其中，还包括：The three-dimensional semiconductor structure according to any one of claims 1-5, further comprising:

连接立柱(500)，沿所述衬底(100)的平面方向阵列排布，所述连接立柱(500)连接在所述衬底(100)上并沿所述衬底(100)的厚度方向延伸，所述连接立柱(500)与其延伸方向上的各所述连接垫(220)连接。 The connecting pillars (500) are arranged in an array along the plane direction of the substrate (100). The connecting pillars (500) are connected to the substrate (100) and along the thickness direction of the substrate (100). Extend, the connecting column (500) is connected to each of the connecting pads (220) in its extending direction.
根据权利要求6所述的三维半导体结构，其中，所述连接垫(220)包括主体部(221)和连接部(222)，所述主体部(221)与所述沟道区(2112)对应，沿所述半导体层(211)的长度方向，所述连接部(222)连接于所述主体部(221)的侧方，所述连接立柱(500)贯穿所述连接部(222)。The three-dimensional semiconductor structure according to claim 6, wherein the connection pad (220) includes a main body portion (221) and a connecting portion (222), the main body portion (221) corresponding to the channel region (2112) , along the length direction of the semiconductor layer (211), the connecting portion (222) is connected to the side of the main body portion (221), and the connecting column (500) penetrates the connecting portion (222).
根据权利要求7所述的三维半导体结构，其中，所述连接部(222)与所述源极区(2111)对应，或者，所述连接部(222)与所述漏极区(2113)对应。The three-dimensional semiconductor structure according to claim 7, wherein the connection portion (222) corresponds to the source region (2111), or the connection portion (222) corresponds to the drain region (2113) .
根据权利要求7所述的三维半导体结构，其中，所述连接部(222)包括第一连接部(2221)和第二连接部(2222)，所述第一连接部(2221)与所述源极区(2111)对应，所述第二连接部(2222)与所述漏极区(2113)对应，所述第一连接部(2221)和所述第二连接部(2222)中的至少一者与所述连接立柱(500)连接。The three-dimensional semiconductor structure according to claim 7, wherein the connection part (222) includes a first connection part (2221) and a second connection part (2222), the first connection part (2221) and the source The second connection part (2222) corresponds to the drain region (2113), and at least one of the first connection part (2221) and the second connection part (2222) The one is connected to the connecting column (500).
根据权利要求1-9任一项所述的三维半导体结构，其中，所述晶体管(210)还包括栅极结构(212)，所述栅极结构(212)覆盖所述沟道区(2112)的厚度方向的至少一侧表面。The three-dimensional semiconductor structure according to any one of claims 1-9, wherein the transistor (210) further includes a gate structure (212) covering the channel region (2112) At least one side surface in the thickness direction.
根据权利要求10所述的三维半导体结构，其中，所述栅极结构(212)覆盖所述沟道区(2112)的厚度方向的两侧表面。The three-dimensional semiconductor structure according to claim 10, wherein the gate structure (212) covers both side surfaces of the channel region (2112) in the thickness direction.
根据权利要求10所述的三维半导体结构，其中，所述栅极结构(212)延伸至覆盖所述连接垫(220)的部分表面。The three-dimensional semiconductor structure of claim 10, wherein the gate structure (212) extends to cover a portion of the surface of the connection pad (220).
根据权利要求10所述的三维半导体结构，其中，还包括：The three-dimensional semiconductor structure according to claim 10, further comprising:

多条字线(300)，所述字线(300)覆盖对应的所述栅极结构(212)并沿所述半导体层(211)的宽度方向延伸，且所述字线(300)沿所述衬底(100)的厚度方向堆叠。A plurality of word lines (300), the word lines (300) cover the corresponding gate structures (212) and extend along the width direction of the semiconductor layer (211), and the word lines (300) extend along the corresponding gate structures (212). The substrates (100) are stacked in the thickness direction.
根据权利要求1-13任一项所述的三维半导体结构，其中，沿所述衬底(100)的厚度方向，所述连接垫(220)的厚度与所述半导体层(211)的厚度相同。The three-dimensional semiconductor structure according to any one of claims 1 to 13, wherein the thickness of the connection pad (220) is the same as the thickness of the semiconductor layer (211) along the thickness direction of the substrate (100). .
一种三维半导体结构的制作方法，包括：A method for manufacturing a three-dimensional semiconductor structure, including:

提供衬底(100)；provide substrate(100);

形成堆叠结构(200)，所述堆叠结构(200)位于所述衬底(100) 上；所述堆叠结构(200)包括沿所述衬底(100)的厚度方向堆叠的多个存储单元阵列(201)，每个所述存储单元阵列(201)包括沿所述衬底(100)的平面方向阵列排布的多个晶体管(210)和多个连接垫(220)；其中，Forming a stack structure (200), the stack structure (200) is located on the substrate (100) Above; the stacked structure (200) includes a plurality of memory cell arrays (201) stacked along the thickness direction of the substrate (100), each of the memory cell arrays (201) includes a plurality of memory cell arrays (201) stacked along the thickness direction of the substrate (100). ) and a plurality of transistors (210) and a plurality of connection pads (220) arranged in a plane direction array; wherein,

所述晶体管(210)包括沿所述衬底(100)的平面方向延伸的半导体层(211)，所述半导体层(211)沿其长度方向依次设置有源极区(2111)、沟道区(2112)和漏极区(2113)；所述连接垫(220)设置于所述半导体层(211)的宽度方向的侧方并与所述半导体层(211)连接，所述连接垫(220)与所述衬底(100)电连接，且所述连接垫(220)与所述沟道区(2112)电连接。 The transistor (210) includes a semiconductor layer (211) extending along the plane direction of the substrate (100). The semiconductor layer (211) is sequentially provided with a source region (2111) and a channel region along its length direction. (2112) and the drain region (2113); the connection pad (220) is disposed on the side of the semiconductor layer (211) in the width direction and is connected to the semiconductor layer (211). The connection pad (220) ) is electrically connected to the substrate (100), and the connection pad (220) is electrically connected to the channel region (2112).