WO2024016617A1 - 高速缓存管理方法、装置、***、设备及介质 - Google Patents

高速缓存管理方法、装置、***、设备及介质 Download PDF

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Publication number
WO2024016617A1
WO2024016617A1 PCT/CN2023/071904 CN2023071904W WO2024016617A1 WO 2024016617 A1 WO2024016617 A1 WO 2024016617A1 CN 2023071904 W CN2023071904 W CN 2023071904W WO 2024016617 A1 WO2024016617 A1 WO 2024016617A1
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Prior art keywords
target
cache
operation request
hash value
request
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PCT/CN2023/071904
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English (en)
French (fr)
Inventor
崔健
王江
李树青
李幸远
巨新刚
吴睿振
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苏州元脑智能科技有限公司
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Publication of WO2024016617A1 publication Critical patent/WO2024016617A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Definitions

  • the present application relates to the technical field of cache management, and more specifically, to a cache management method, device, system, equipment and non-volatile readable storage medium.
  • Cache In computer systems, Cache (cache memory) is a type of memory used to store a small amount of temporary data that needs to be accessed quickly. For example, it is commonly located between the CPU (central processing unit, central processing unit) and the main memory. CPU Cache between.
  • CPU central processing unit
  • main memory main memory
  • CPU Cache between.
  • magnetic disks or solid-state drives have different access latencies due to the physical characteristics of their storage media. This delay is generally much greater than the access delay of main memory.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Raid Redundant Arrays of Independent Disks, disk array
  • an external storage Cache management system generally needs to support at least the following functions:
  • Cache line is a cache line and is the basic unit of Cache operation;
  • Cache entry specifically refers to the node that manages Cache Line in the storage Cache system, which corresponds to Cache Line one-to-one and points to Cache Line;
  • Cache hit/miss judgment among them, Cache Hit is a Cache hit, indicating that the data that needs to be operated is found in the Cache during a certain access; Cache Miss is a Cache miss, indicating that the data that needs to be operated during a certain access is The data was not found in the Cache;
  • Cache management systems implemented based on CPU software are more common.
  • Cache Entries are generally organized and stored in the form of hash tables. See Figure 1 for a hash representation; as shown in Figure 1, multiple Cache Entries are stored in a hash table (Hash Table).
  • the Hash value (hash) is to pass the input data (key) of any length through the hash Column algorithm is converted into fixed-length output, which is a compressed mapping)
  • the same Cache Entry is stored in the same doubly linked list.
  • Cache Entries belonging to the same storage medium such as hard drive HDD_0 or Logic Drive 0
  • Each Cache Entry in the hash table points to a Cache line.
  • Cache management responsible for software including allocation, release and Cache hit/miss detection, often requires traversing the linked list, resulting in long time consumption and jittery delay, and real-time performance cannot be guaranteed.
  • the purpose of the embodiments of this application is to provide a cache management method, device, system, equipment and non-volatile readable storage medium, so as to reduce the delay of Cache operations and improve the real-time performance of Cache management.
  • the cache management method is applied to the storage system cache manager.
  • the cache management method includes:
  • the processing result of the target operation request is fed back to the target user, and the corresponding cache maintenance operation is performed according to the processing result through the software cache manager.
  • the target operation request is used to perform corresponding processing operations on the cache line, including:
  • the corresponding query result is output; if the target address is found, the corresponding cache entry table is searched according to the target address, and the retrieved key value is matched with the key value requested by the target operation. Compare and output the corresponding query results;
  • the target hash value before calculating the target hash value based on the key value in the target operation request, it also includes:
  • Arbitration rules are used to prioritize each target operation request.
  • arbitration rules after using arbitration rules to prioritize each target operation request, it also includes:
  • the target operation request is an allocation request, determine whether the allocation request exceeds the remaining quota
  • allocation request does not exceed the remaining quota, continue to perform the step of calculating the target hash value based on the key value in the target operation request; if the allocation request exceeds the remaining quota, process the target operation request according to the over-provisioning mode.
  • judging whether the allocation request exceeds the remaining quota includes:
  • the cache count plus one is greater than the corresponding first threshold value, it is determined that the allocation request exceeds the remaining quota; if the cache count plus one is less than or equal to the corresponding first threshold value, then the global count after the cache count plus one is determined Whether it is greater than the corresponding second threshold value;
  • target operation requests are processed according to the over-provisioning mode, including:
  • over-provisioning mode is warning mode, continue to calculate the target hash value based on the key value in the target operation request, and generate corresponding event information and send it to the software cache manager;
  • the over-provisioning mode is blocking mode, a processing failure result will be generated directly.
  • the method further includes:
  • the target operation request is an operation request initiated by a software cache user, reporting the response information to the software cache manager, where the target user includes the software cache user;
  • the target operation request is an operation request initiated by a hardware cache user
  • the response information is reported to the hardware cache user
  • the event information is copied and reported to the software cache manager, where the target user includes the hardware cache manager. Cache users.
  • the target hash value is calculated based on the key value in the target operation request, and the target hash value is used to perform table lookup in the target data table, including:
  • the target operation request and the corresponding target hash value corresponding to the notification information are deleted from the second target queue.
  • calculating the corresponding target hash value based on the key value in each target operation request includes:
  • the key values in the target operation request are sequentially sent to three hash function calculation modules for calculation to obtain the target hash value, where the target hash value includes row, sig and CAM val.
  • the target queue includes a first target queue and a second target queue;
  • target hash value does not collide with the hash value of the operation request in the target queue, continue to perform the step of storing the target operation request and the corresponding target hash value in the first target queue;
  • the target operation request and the corresponding target hash value will be temporarily stored in the first target queue. If it is detected that the target hash value does not exist in the target queue, If the collision hash value is found, continue to perform the step of storing the target operation request and the corresponding target hash value into the first target queue.
  • the step of determining whether the target hash value collides with the hash value of the operation request in the target queue includes:
  • the target hash value is the same as the hash value of the operation request in the target queue, it is determined that the target hash value collides with the hash value of the operation request in the target queue;
  • the target operation request is any one of the following requests: allocation request, release request, check request, lock request, unlock request, and set request.
  • receiving target operation requests sent by target users includes:
  • the processing results of the target operation request are fed back to the target user, and the corresponding cache maintenance operations are performed according to the processing results through the software cache manager, including:
  • the target operation request is a request sent by the hardware cache user
  • the response information of the target operation request is sent to the hardware cache user. user, and generate event information corresponding to the response information and send it to the software cache manager, so that the software cache manager can perform corresponding cache maintenance operations based on the event information;
  • the target operation request is a request sent by the software cache user
  • the response information of the target operation request is sent to the software cache user so that the software cache manager can perform corresponding cache maintenance operations based on the response information.
  • the event information corresponding to the response information is generated and sent to the software cache manager, including:
  • the event information is asynchronously notified to the software cache manager through event reporting, where the event information includes information on cache allocation, usage, query and other behaviors.
  • the cache management device is applied to a storage system cache manager.
  • the cache management device includes:
  • the receiving module is used to receive the target operation request sent by the target user
  • the processing module is used to process the target operation request in a pipeline manner, so as to use the target operation request to perform corresponding processing operations on the cache line;
  • the sending module is used to feed back the processing results of the target operation request to the target user, and perform corresponding cache maintenance operations according to the processing results through the software cache manager.
  • the processing modules include:
  • a table lookup unit configured to calculate a target hash value based on the key value in the target operation request, and use the target hash value to perform a table lookup in the target data table;
  • the output unit is set to output the corresponding query result when the corresponding target address is not found; when the target address is found, the corresponding cache entry table is retrieved according to the target address, and the retrieved key value is compared with the Compare the key values requested by the above target operation and output the corresponding query results;
  • the first processing unit is configured to perform corresponding processing operations according to the query results and the target operation request.
  • a cache management system including:
  • the storage system cache manager is used to receive the target operation request sent by the target user, process the target operation request in a pipeline manner, so as to use the target operation request to perform the corresponding processing operation on the cache line; feedback the processing result of the target operation request to the target user;
  • the software cache manager is used to perform corresponding cache maintenance operations based on the processing results.
  • an electronic device including:
  • Memory used to store computer programs
  • a processor is used to implement the steps of the above cache management method when executing a computer program.
  • embodiments of the present application provide a computer non-volatile readable storage medium.
  • a computer program is stored on the computer non-volatile readable storage medium.
  • the above cache management method is implemented. A step of.
  • the cache management method is applied to the cache manager of the storage system and includes the following content: receiving a target operation request sent by a target user; through a pipeline method Process the target operation request to use the target operation request to perform corresponding processing operations on the cache line; feed back the processing results of the target operation request to the target user, and perform corresponding cache maintenance operations based on the processing results through the software cache manager.
  • cache maintenance operations with low real-time requirements can be implemented through the software cache manager, and operation requests with high real-time requirements can be implemented in a hardware pipeline manner through the storage system cache manager.
  • Parallel processing reduces the processing delay of cache line operations and improves the real-time performance of cache management.
  • This solution also discloses a cache management device, system, equipment and non-volatile readable storage medium, which can also achieve the above technical effects.
  • Figure 1 shows the hash representation
  • Figure 2 is a schematic flow chart of a cache management method disclosed in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a Cache management system disclosed in the embodiment of the present application.
  • Figure 4a is a format definition diagram of an operation request disclosed in the embodiment of the present application.
  • Figure 4b is a format definition diagram of a processing result disclosed in the embodiment of the present application.
  • Figure 5 is a schematic diagram of the corresponding relationship between operation requests and response information disclosed in the embodiment of the present application.
  • Figure 6 is a schematic diagram of state transition disclosed in the embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a target operation request processing disclosed in the embodiment of the present application.
  • Figure 8 is a schematic diagram of the overall structure of a hardware Cache manager disclosed in the embodiment of the present application.
  • Figure 9 is a schematic diagram of the work flow of the quota module disclosed in the embodiment of this application.
  • FIG. 10 is a schematic structural diagram of the Cache Line Lookup engine disclosed in the embodiment of this application.
  • Figure 11 is a schematic structural diagram of the request throttling module disclosed in the embodiment of the present application.
  • Figure 12 is a schematic structural diagram of the Multibin hash table disclosed in the embodiment of the present application.
  • Figure 13a is a schematic diagram of processing operation requests in a pipeline manner disclosed in the embodiment of the present application.
  • Figure 13b is another schematic diagram of processing operation requests in a pipeline manner disclosed in the embodiment of the present application.
  • Figure 14 is a schematic structural diagram of a software Cache manager disclosed in the embodiment of the present application.
  • Figure 15 is a schematic structural diagram of a cache management device disclosed in an embodiment of the present application.
  • Figure 16 is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.
  • Data that needs to be written to the storage medium can be arranged in the Cache in a way that is more friendly to the storage medium, and written in batches to improve throughput.
  • the Cache system can also selectively pre-read data that may be accessed from the storage medium and put it into the Cache based on the characteristics of the read data, thereby increasing the probability of a Cache hit.
  • the Cache system divides the data into hot and cold data based on the characteristics of the data accessed by the host. Keep hot data that is frequently accessed in the cache, and drop cold data that is rarely used to disk. Improve Cache usage efficiency.
  • Cache management systems based on CPU software are more common.
  • the software has no limit on the length of the linked list and is highly flexible; Cache Entry can be dynamically allocated and has high utilization; the cold storage of Cache Entry The hot relationship can be represented by the position in the linked list; however, the cache management method implemented through CPU software has problems such as long operation time, real-time performance cannot be guaranteed, and throughput rate is affected.
  • this application provides a cache management method, device, system, equipment and non-volatile readable storage medium to reduce the delay of Cache operations and improve the real-time performance of Cache management.
  • FIG. 2 a schematic flow chart of a cache management method provided by an embodiment of the present application is applied to a storage system cache manager.
  • the cache management method includes the following steps:
  • the Cache is mainly managed through two parts: the storage system cache manager and the software cache manager.
  • the cache is the Cache.
  • the storage system cache manager can be understood as a hardware cache manager, which is mainly responsible for high real-time and relatively simple logical tasks, such as: processing operations performed on cache lines, including: Cache allocation, release, and Cache hit /miss query, etc.
  • the software cache manager is a software cache manager, which mainly handles Cache maintenance operations with relatively low real-time requirements but complex logic, such as the maintenance of hot and cold data, the implementation of Cache disk placement strategies, etc.
  • the Cache management system includes a hardware Cache manager and a software Cache manager.
  • the hardware Cache manager is used to receive target operation requests sent by hardware cache users. , or a target operation request sent by the software cache user through the software cache manager, where the hardware cache user is a hardware Cache user and is an external hardware module that can initiate Cache service requests, and the software cache user is a software Cache user, It is an external software module that can initiate Cache business requests.
  • the hardware Cache manager provides request and response signal or register interfaces to the hardware Cache user and the software Cache manager respectively, and initiates requests and receives responses according to the format defined by the Cache management system.
  • the software Cache manager provides a Cache operation API (Application Programming Interface) interface to software Cache users. Operation requests initiated by software Cache users are sent to the hardware Cache manager through the software Cache manager.
  • Cache operation API Application Programming Interface
  • the cache requests sent by hardware cache users or software cache users received by the hardware cache manager are all operation requests.
  • the operation request currently received by the hardware cache manager is called a target operation request.
  • the Cache management system uses device_id (drive device number) and lba (Logical block addressing, logical block address) to establish an index of the cache line, and only supports fixed-size Cache Line.
  • Device represents a logical or physical storage device.
  • Requester identifies the request initiator, including User_type and User_id;
  • User_type used to distinguish hardware Cache users and software Cache users
  • User_id When there are multiple hardware Cache users/software Cache users, use User_id to distinguish;
  • Request Seq The request sequence number of the request sent by each hardware Cache user/software Cache user, starting from 0 and increasing by 1 for each request;
  • parameter data tuple used for Cache operation including device_id and lba; in this embodiment, the specific value of the Key is represented by the key value;
  • device_id drive device number
  • Action Indicates what kind of operation the request is, which may be one of the following operations:
  • Lock Lock the Cache Line. It cannot be freed after locking, and Check returns locked;
  • this application can determine what type of operation request the target operation request is based on the Action in the operation request.
  • the target operation request is any one of the following requests: allocation request, release request, Check request, lock request, unlock request, set request.
  • S102 Process the target operation request in a pipeline manner, so as to use the target operation request to perform corresponding processing operations on the cache line;
  • the hardware cache manager in this embodiment allows software cache users and hardware cache users to submit multiple operation requests in an asynchronous manner.
  • the hardware cache manager receives operation requests initiated by software cache users and hardware cache users, it uses a hardware pipeline to process these requests to achieve high throughput of cache request processing.
  • the processing results in this solution include: response information and event information. If the target operation request is a request sent by the hardware cache user, the response information of the target operation request is sent to the hardware cache user, and the response information is generated. The corresponding event information is sent to the software cache manager so that the software cache manager can perform corresponding cache maintenance operations based on the event information; if the target operation request is a request sent by the software cache user, the response information of the target operation request is Sent to the software cache user so that the software cache manager can perform corresponding cache maintenance operations based on the response information.
  • the hardware Cache manager in this application responds to the operation request of the software Cache user, it notifies the software Cache manager through the response information.
  • the hardware Cache manager responds to the request initiated by the hardware Cache user, it not only needs to send the response information
  • the software cache manager also needs to be notified asynchronously through event reporting, including cache allocation, usage, query and other behaviors. In this way, the software cache manager can extract useful information from the response/event.
  • Complete various complex Cache maintenance tasks For example: sorting hot and cold data in the Cache Line of a certain Device, or connecting Cache Lines with consecutive addresses, etc.
  • FIG. 4b is a format definition diagram of a processing result disclosed in the embodiment of the present application.
  • the same fields in Figure 4a and Figure 4b will not be described again here.
  • Each field in the processing result is defined as follows:
  • SW Hash Value calculated by the hardware Cache manager, and the hash value of the Cache Entry is retrieved by the software Cache manager;
  • Type used to distinguish response information or event information
  • Event Indicates that the processing result is event information
  • Fail Indicates that the request processing failed
  • Invalid/Modified Indicates that there is a corresponding Cache Line in the Cache system, and the status is one of Invalid (invalid) or Modified (modified);
  • Miss means Cache miss, that is, the corresponding Cache Line is not found
  • Qouta Indicates that the requested Cache Line request exceeds the limit of a certain quota rule.
  • Locked/Unlocked Indicates that there is a corresponding Cache Line in the Cache system, and the status is one of locked or unlocked;
  • Response/Event Data Length The length of the additional data in the response or event
  • Response/Event Data Additional data for the response or event.
  • the content is Cache Entry; only when the Alloc application block exceeds the limit, the content is the corresponding over-limit entry in the quota module.
  • Figure 5 is a schematic diagram of the corresponding relationship between operation requests and response information disclosed in the embodiment of the present application. It can be seen that different operation requests generate different response information based on the operation results. Of course, the correspondence relationship shown in Figure 5 is only the correspondence relationship between the request and the possible received response. In practical applications, this solution is not limited to the correspondence relationship shown in Figure 5.
  • Figure 6 is a schematic diagram of state transition provided by the embodiment of the present application.
  • the possible states include: Not Cached, Invalid, Invalid&locked, Modify, Modify&locked, through external input operations Request, control the status of Cache Line to jump between multiple states.
  • Not Cache indicates the status of the Cache Line that has not been included in the management of the Cache Manager and is not recorded in the Cache Manager; after applying for the Cache Line, the status changes to Invalid, indicating that the Cache Line has been applied for but the data in the Cache Line is invalid; if If hardware or software cache users need to monopolize a certain Cache Line, they can use the lock command to change the Cache Line to the Lock state, such as: Invalid&locked and Modify&locked. When in the Lock state, the Cache Line does not support Free and cannot be locked again. If you need to mark whether the data in the Cache Line has been modified, you can use the Set State Modify command to convert the Cache Line to Modify. Cache Line does not support Free when in Modify state.
  • Lock state and Modify state is entirely determined by the user of the Cache manager. In actual applications, users can only use a subset of Action and Cache Line states according to actual needs. For example:
  • the Cache is managed through a combination of software and hardware.
  • Cache maintenance operations with low real-time requirements can be implemented through the software Cache manager.
  • Operation requests with high real-time requirements can be implemented , which can be processed in parallel in a pipeline manner through the hardware Cache manager, reducing the processing delay of cache line operations and improving the real-time nature of Cache management.
  • FIG 7 is a schematic diagram of a target operation request processing flow diagram provided by an embodiment of the present application. As shown in Figure 7, this embodiment explains the process of S102 using the target operation request to perform corresponding processing operations on the cache line. This process Includes the following steps:
  • FIG 8 is a schematic diagram of the overall structure of a hardware Cache manager provided by an embodiment of the present application.
  • multi-channel Cache Line operation requests initiated by hardware and software Cache users will be processed in the hardware Cache manager. It first enters the FIFO (First Input First Output) queue for buffering, and then is arbitrated according to certain rules in the arbiter and then output to the quota module.
  • the arbitration rules set in the arbiter can be set according to actual needs.
  • the priority of the operation request sent by the hardware Cache user is set to be higher than the priority of the operation request sent by the software Cache user, then the priority is When sorting, the operation requests sent by the hardware cache users need to be sorted before the operation requests sent by the software cache users, so that according to the priority of each operation request, each operation request can be input into the quota module in turn, and the subsequent steps can be continued.
  • the allocation request when determining whether the allocation request exceeds the remaining quota in S202, it is necessary to determine the key value of the allocation request; determine the corresponding cache count according to the key value of the allocation request; determine whether the cache count plus one is greater than the corresponding first threshold value; If the cache count plus one is greater than the corresponding first threshold value, it is determined that the allocation request exceeds the remaining quota; if the cache count plus one is less than or equal to the corresponding first threshold value, then the global count after the cache count plus one is determined Whether it is greater than the corresponding second threshold value; if it is greater than the corresponding second threshold value, it is determined that the allocation request exceeds the remaining quota; if it is not greater than the corresponding second threshold value, it is determined that the allocation request does not exceed the remaining quota.
  • the quota module in this solution is responsible for the management of each Device and the global Cache quota.
  • the quota module forwards the allocation request to the cache line lookup engine (i.e., the Cache Line lookup engine in Figure 10). If exceeded, the quota module intercepts this allocation request and sends a quota exceeded response to the responder.
  • the quota module in this solution implements several disk-by-disk Cache counter and threshold entries, as well as several global Cache threshold entries.
  • Figure 9 is a schematic diagram of the workflow of the quota module provided in the embodiment of this application. It can be seen from Figure 9 that after receiving the operation request Request, for the allocation request Alloc, the quota module extracts the device id item in the key of the Alloc allocation request. And read the corresponding cache counter Cache counter in the quota table entry. Calculate whether the cache count Cache Counter plus 1 is greater than the first threshold value Threshold (T_hold). In the same way, all global entries are checked in parallel. If the calculation results are all less than the corresponding second threshold value, the allocation request is allowed to pass and forwarded to the Cache Line lookup engine, otherwise a Fail response is returned to the responder.
  • Threshold Threshold
  • the over-provisioning mode can be used to determine how to handle the operation request.
  • the oversubscription mode of each table entry can be configured as Warning mode or Blocking mode. If the over-configuration mode is the warning mode, S204 will continue to be executed, and corresponding event information will be generated and sent to the software expressway. Cache manager; if the over-provisioning mode is blocking mode, a processing failure result will be generated directly. That is to say: in warning mode, when the detection exceeds the threshold, the request will still be forwarded backwards, but at the same time, the event will be reported to the software Cache manager through the responder.
  • the quota In blocking mode, the quota directly returns a Fail response to the responder.
  • the responder receives the Fail sent from the quota module, if it is an operation request initiated by a software Cache user, it will report the response information to the software Cache manager. If it is a hardware Cache user, When an operation request is initiated, after the response information is reported to the hardware cache user, a copy of the event information needs to be copied and reported to the software cache manager.
  • S204 and S205 in this embodiment include the following content: calculate the corresponding target hash value according to the key value in each target operation request, and store the target operation request and the corresponding target hash value in the first target queue; Obtain the target hash value of the target operation request that has not been looked up from the first target queue, and perform a table lookup in the target data table based on the obtained target hash value; combine the table-looked target operation request and the corresponding target hash The value is deleted from the first target queue and added to the second target queue; if notification information that the target operation request has been processed is received, the target operation request corresponding to the notification information and the corresponding target hash value are removed from the second target queue. Delete from queue.
  • this solution in order to avoid hash collisions, after calculating the corresponding target hash value based on the key value in each target operation request, this solution also needs to determine the target hash value and the hash of the operation request in the target queue. Whether the values collide; the target queue includes the first target queue and the second target queue; if the target hash value does not collide with the hash value of the operation request in the target queue, continue to store the target operation request and the corresponding target hash value to the first target queue; if the target hash value collides with the hash value of the operation request in the target queue, the target operation request and the corresponding target hash value are temporarily stored in the first target queue. If there is a hash value that collides with the target hash value, the target operation request and the corresponding target hash value continue to be stored in the first target queue.
  • the Cache Line lookup engine is mainly responsible for looking up tables and outputting query results, and outputting operation requests and query results to the command processing engine.
  • Figure 10 is a schematic structural diagram of the Cache Line Lookup engine provided by the embodiment of the present application.
  • the Cache Line Lookup engine after receiving the operation request, the Cache Line Lookup engine first sends it to its internal request throttling module to buffer the operation request.
  • the request throttling module is responsible for controlling the timing of command issuance to ensure that at any time , there is no hash collision between the subsequent input operation request and all the requests queued in the request throttling module, where: hash collision means that the output value obtained by two keys with different contents is the same after hash calculation.
  • the request throttling module also calculates the target hash value used for table lookup from the key pointer.
  • the target hash value includes: row, signature and CAM val. Used to check Multibin hash table and CAM table respectively.
  • FIG 11 is a schematic structural diagram of the request throttling module provided by the embodiment of the present application. It can be seen from Figure 11 that after receiving the operation request from the quota module, the request throttling module sends it to the request FIFO queue.
  • the Key of the operation request buffered by the FIFO queue is sent to three hash function calculation modules in sequence to calculate the target hash value.
  • the target hash value includes the three values of row, sig and CAM val. These three values are related to The original request is merged as a lookup element LE (lookup element). Under the control of the Throttle throttling sub-module, it is forwarded to LE Send Queue (lookup table element send queue).
  • the LE output module (lookup table element output module) will read LE from the LE Send Queue under the control of the next_stage_ready signal (ready for the next stage), and send the LE to the target data table for table lookup.
  • the target data table includes the mutilbin hash table and CAM; at the same time, the LE output module will send a copy of the LE sent to the table lookup to the LE response Queue (lookup table element response queue).
  • the command processing engine processes an operation request, it will send the ID information of the completed request to the Sink module.
  • the Sink module compares the request ID information with the head element of the LE response Queue. If they match, then Read a LE from the LE response Queue and discard it.
  • this solution needs to detect whether the target hash value collides with the hash value of the operation request in the target queue (the first target queue and the second target queue) at any time.
  • the target hash value refers to The hash value in the LE to be entered into the LE Send Queue.
  • the target queue refers to the LE Send Queue (the first target queue) and the LE response Queue (the second target queue). That is, this solution requires the LE Send Queue and the LE response All elements of the Queue are compared with the LE to be entered into the LE Send Queue. Only when the Row, Sig and CAM val do not conflict, the LE is allowed to enter the LE Send Queue through the Throttle module.
  • the corresponding query result is output; if the target address is found, the corresponding cache entry table is retrieved according to the target address, and the retrieved key value is compared with the target operation request. Compare the key values and output the corresponding query results;
  • the target data table includes: Multibin hash table and CAM table.
  • Multibin hash table After requesting the three hash values requested by the throttling output operation, a table lookup needs to be performed in the Multibin hash table and the CAM table.
  • Figure 12 which is a schematic structural diagram of a Multibin hash table provided by an embodiment of the present application.
  • the Multibin hash table is a two-dimensional hash table with 2 ⁇ m rows and 2 ⁇ n columns. When performing a table lookup, you need to select rows based on the input Row value with a width of m, and then match each row of data based on the input signature value.
  • the matching output results include the following three items:
  • pointer 0 as an illegal value, and all elements in the bin are initialized to 0 during initialization.
  • a pointer can be output from the matching result, which can point to the target address in the Cache Entry Table.
  • the target address can be obtained. If no matching target address is found in both tables, it means that the Cache Line misses; if the pointer/address is found, the target address is The address is retrieved in the corresponding Cache Entry Table, and the value of the Key in the search result is compared with the value of the original Key in the operation request. If a complete matching item is found after the comparison, it means that the Cache Line is hit. If not, then It means that the Cache Line is not hit.
  • the query results of the Cache Line and the original operation request will be sent to the command processing engine after splicing.
  • the command processing engine will perform corresponding processing operations based on the Cache Line query results sent by the Cache Line Lookup engine and the Action in the target operation request, including applying for or releasing Cache Line from the Cache Line allocator, updating Multibin hash table and CAM, update Cache Entry table, organize responses and events to be sent to responders, update quota module count.
  • the command processing engine cooperates with the Cache Line Lookup engine to complete the processing of each operation request in parallel in a multi-stage pipeline manner.
  • Each level of the command processing engine pipeline is implemented by a state machine. When the work of this level is completed, the processed results are transferred to the next level of the pipeline.
  • Figure 13a is a schematic diagram of processing operation requests in a pipeline manner provided by an embodiment of the present application. The naming and function description of each stage in the pipeline in Figure 13a is as follows:
  • Execute Responsible for processing requests, extracting Actions and executing corresponding operations. Generate instructions for subsequent pipelines.
  • Update LK Update the Multibin hash table and CAM in the Cache Line Lookup engine.
  • Update CL Update Cache Entry Table.
  • Update quota Update the counter and global counter corresponding to the device id in the quota module.
  • Update CPL Notifies the Cache Line Lookup engine that the request has been processed.
  • FIG. 13b is another schematic diagram of processing operation requests in a pipeline manner provided by the embodiment of the present application. As shown in Figure 13b, if some commands do not require a certain level of pipeline, a NOP instruction is generated during execution to skip That’s it.
  • the Cache Line allocator manages the application and release of Cache Line.
  • the command processing engine sends an Alloc operation command
  • the Cache Line allocator's internal Cache Line resource pool obtains a Cache Line and returns it to the command processing engine.
  • the released Cache Line is stored in the internal resource pool.
  • the Cache Line allocator is implemented by a traditional ring queue, with internal head and tail pointers pointing to the first node and the last node respectively. All Cache Lines are filled in by the software Cache manager during system initialization.
  • an Alloc request is received, an element is read from the head pointer, and then the head pointer is increased modulo 1.
  • a Free request is received, the input element is placed in the tail pointer, and then the tail pointer is incremented modulo 1.
  • the queue is empty, the Alloc request returns failure.
  • the Free request returns failure.
  • the responder is responsible for receiving responses and events from the quota and command processing engines, and distinguishes whether to send to hardware or software based on the information in the response. If it needs to be sent to hardware, it will be sent directly through the hardware Cache user interface. The signal is sent to the corresponding hardware Cache user. If it needs to be sent to the software, the response is forwarded to the software interface logic.
  • the software and hardware interface logic is internally responsible for receiving the Cache operation request issued by the software Cache manager, sending the operation request to the hardware Cache manager, and aggregating the response information sent by the responder in the hardware Cache manager and the command processing engine. Event information is collected and reported to the software Cache manager.
  • the software and hardware interface uses a single request and response queue, and the interaction process is the same as the I0 (Input/0utput, input/output) queue protocol of NVMe (Non Volatile Memory Express, non-volatile fast memory).
  • FIG 14 is a schematic structural diagram of a software Cache manager provided by an embodiment of the present application.
  • the software Cache manager is an implementation based on a traditional software Cache management mechanism.
  • the software Hash table part in Figure 14 has the same management logic as the traditional software Cache Hash table.
  • the software Cache manager adds a request processing module, which is used to receive API calls from software Cache users, organize Cache operation requests and receive responses.
  • the response event offload module is responsible for obtaining response information and event information from the response and event queue.
  • the response information and event information in the queue are issued by the hardware Cache manager.
  • the response information and event information are distinguished and processed within the software Cache manager. Diversion.
  • the event information is directly routed to the software Hash table for updating entries, while the response information is handed over to the request processing module. After the request processing module processes the response, it is also changed to the event notification software Hash table for update.
  • the hardware cache user sends a Cache Line operation request and sends it to the quota module through Arbiter_0;
  • the quota module checks the Device and Global threshold items of the Alloc request and finds that the remaining quota is not exceeded.
  • the quota module forwards the request to the downstream Cache Line lookup module;
  • Cache Line lookup completes the Key search and finds that there is no Cache hit in the multibin hash table, and outputs the result to the command processing engine module;
  • the command processing engine found that it was an Alloc command and the multibin hash table missed. Apply to Alloc Engine and obtain Cache Line;
  • the command processing engine updates the Cache Line Entry of the Multibin hash table corresponding to the Row's first_free_bin address to signature and pointer;
  • the command processing engine updates the Cache Entry Table, including the Cache Line address obtained by Alloc allocation;
  • the command processing engine sends response information to the responder
  • the responder sends the corresponding Device ID quota Entry instruction to increase by 1 to the quota module
  • the command processing engine sends the completion Req ID to the Cache Line lookup module
  • the responder sends a response to the hardware Cache user.
  • the software Cache user sends a Cache Line operation request and sends it to the quota module through Arbiter_0;
  • the quota module checks the Device and Global threshold items of the Alloc request and finds that the remaining quota is not exceeded.
  • the quota module forwards the request to the downstream Cache Line lookup module;
  • Cache Line lookup After Cache Line lookup receives the request, it completes the Key search and finds that the multibin hash table has conflicted and there is no free entry in the continuous read address. However, there is no matching item in CAM, and the result is output to the command processing engine module;
  • the command processing engine applies to the Alloc Engine and obtains the Cache Line based on the Cache Line query results;
  • the command processing engine updates the CAM table and adds Cache Entry to the CAM table
  • the command processing engine updates the CAM Cache Entry Table
  • the command processing engine sends response information to the responder
  • the command processing engine sends the completion Req ID to the Cache Line lookup module
  • the command processing engine sends response information to the software interface
  • the software Cache manager reads the response from the interface, calculates the hash value and adds the Cache Entry to the software Hash table.
  • a Cache management solution that combines software and hardware is disclosed.
  • This solution uses hardware to implement the query, allocation and release logic of Cache Line, which reduces the delay of Cache Line operations and satisfies high throughput. efficiency and high flexibility requirements.
  • This solution also supports concurrent access to Cache Line initiated by hardware and software, and ensures the consistency of Cache Line through the mechanism of Cache Line lock and Cache Line status.
  • This solution implements real-time threshold detection and interception through the quota module.
  • This solution uses conflict detection and avoidance technology to achieve pipeline processing of Cache Line requests while ensuring Cache consistency.
  • the cache management device, system, equipment and non-volatile readable storage medium provided by the embodiments of the present application are introduced below.
  • the cache management device, system, equipment and non-volatile readable storage medium described below are the same as those described above.
  • the cache management methods described can be cross-referenced.
  • the cache management device includes:
  • the receiving module 11 is used to receive the target operation request sent by the target user;
  • the processing module 12 is used to process the target operation request in a pipeline manner, so as to use the target operation request to perform corresponding processing operations on the cache line;
  • the sending module 13 is used to feed back the processing results of the target operation request to the target user, and perform corresponding cache maintenance operations according to the processing results through the software Cache manager.
  • the processing module 12 includes:
  • the table lookup unit is used to calculate the target hash value based on the key value in the target operation request, and use the target hash value to perform table lookup in the target data table;
  • the output unit is used to output the corresponding query results when the corresponding target address is not found; when the target address is found, the corresponding cache entry table is retrieved according to the target address, and the retrieved key value is combined with the target operation Compare the requested key values and output the corresponding query results;
  • the first processing unit is used to perform corresponding processing operations according to the query results and target operation requests.
  • the processing module 12 also includes:
  • the sorting unit is used to prioritize each target operation request using arbitration rules
  • the first judgment unit is used to judge whether the allocation request exceeds the remaining quota when the target operation request is an allocation request; if the allocation request does not exceed the remaining quota, trigger the calculation unit to calculate the target hash value according to the key value in the target operation request; If the allocation request exceeds the remaining quota, the target operation request is processed by the second processing unit according to the over-provisioning mode.
  • the first judgment unit is used to: determine the key value of the allocation request; determine the corresponding cache count according to the key value of the allocation request; determine whether the cache count is greater than the corresponding first threshold value after adding one; if the cache count is increased by one, If it is greater than the corresponding first threshold value, it is determined that the allocation request exceeds the remaining quota; if the cache count is increased by one and is less than or equal to the corresponding first threshold value, it is determined whether the global count after the cache count is increased by one is greater than the corresponding second threshold value.
  • Threshold value if it is greater than the corresponding second threshold value, it is determined that the allocation request exceeds the remaining quota; if it is not greater than the corresponding second threshold value, it is determined that the allocation request does not exceed the remaining quota.
  • the second processing unit is used to: if the over-configuration mode is the warning mode, continue to calculate the target hash value according to the key value in the target operation request, and generate corresponding event information and send it to the software cache manager; if the over-configuration If the mode is blocking mode, a processing failure result will be generated directly.
  • the table lookup unit is used to: calculate the corresponding target hash value according to the key value in each target operation request, and store the target operation request and the corresponding target hash value into the first target queue; Obtain the target hash value of the target operation request that has not been looked up, and perform table lookup in the target data table based on the obtained target hash value; remove the target operation request and the corresponding target hash value that have been looked up from the first target queue Delete from the request and add it to the second target queue; if notification information that the target operation request has been processed is received, the target operation request and the corresponding target hash value corresponding to the notification information are deleted from the second target queue.
  • the table lookup unit is also used to: determine whether the target hash value collides with the hash value of the operation request in the target queue; the target queue includes the first target queue and the second target queue; if the target hash value collides with the operation request in the target queue, If the requested hash value does not collide, the target operation request and the corresponding target hash value will continue to be stored in the first target queue; if the target hash value collides with the hash value of the operation request in the target queue, the target operation request will be suspended.
  • the request and the corresponding target hash value are stored in the first target queue. If it is detected that there is no hash value that collides with the target hash value in the target queue, the target operation request and the corresponding target hash value will continue to be stored in the third target queue.
  • a target queue is also used to: determine whether the target hash value collides with the hash value of the operation request in the target queue; the target queue includes the first target queue and the second target queue; if the target hash value collides
  • the target operation request is any one of the following requests: allocation request, release request, check request, lock request, unlock request, and set request.
  • the receiving module 11 is used to receive a target operation request sent by a hardware cache user, or a target operation request sent by a software cache user through a software cache manager.
  • the sending module 13 includes:
  • the first sending unit is configured to send the response information of the target operation request to the hardware cache user when the target operation request is a request sent by the hardware cache user, and generate event information corresponding to the response information and send it to the software cache. Manager so that the software Cache manager can perform corresponding cache maintenance operations based on event information;
  • the second sending unit is configured to send the response information of the target operation request to the software cache user when the target operation request is a request sent by the software cache user, so that the software Cache manager can perform corresponding cache maintenance based on the response information. operate.
  • the embodiment of the present application also discloses a cache management system, which includes:
  • the storage system cache manager is used to receive the target operation request sent by the target user, process the target operation request in a pipeline manner, so as to use the target operation request to perform the corresponding processing operation on the cache line; feedback the processing result of the target operation request to the target user;
  • the software cache manager is used to perform corresponding cache maintenance operations based on the processing results.
  • the storage system cache manager is used to: calculate the target hash value according to the key value in the target operation request, use the target hash value to perform a table lookup in the target data table, and if the corresponding target address is not found, output Corresponding query results; if the target address is found, search in the corresponding cache entry table according to the target address, compare the retrieved key value with the target operation request, and output the corresponding query results. According to the query results and The target operation requests execution of the corresponding processing operation.
  • the storage system cache manager is also used to use arbitration rules to prioritize each target operation request.
  • the storage system cache manager is also used to: if the target operation request is an allocation request, determine whether the allocation request exceeds the remaining quota; if the allocation request does not exceed the remaining quota, continue to calculate the target based on the key value in the target operation request The step of hashing the value; if the allocation request exceeds the remaining quota, the target operation request is processed according to the over-provisioning mode.
  • the storage system cache manager is used to: determine the key value of the allocation request; determine the corresponding cache count according to the key value of the allocation request; determine whether the cache count is greater than the corresponding first threshold after adding one; if the cache count is increased by If the cache count after adding one is less than or equal to the corresponding first threshold, then it is judged whether the global count after adding one is greater than the corresponding The second threshold value; if it is greater than the corresponding second threshold value, it is determined that the allocation request exceeds the remaining quota; if it is not greater than the corresponding second threshold value, it is determined that the allocation request does not exceed the remaining quota.
  • the storage system cache manager is used to: if the over-provisioning mode is the warning mode, continue to calculate the target hash value based on the key value in the target operation request, and generate corresponding event information and send it to the software cache manager; if If the over-provisioning mode is blocking mode, a processing failure result will be generated directly.
  • the storage system cache manager is used to: calculate the corresponding target hash value according to the key value in each target operation request, and store the target operation request and the corresponding target hash value to the first target queue; from the first Obtain the target hash value of the target operation request that has not been looked up in the target queue, and perform a table lookup in the target data table based on the obtained target hash value; the target operation request that has been looked up and the corresponding target hash value are retrieved from the target hash value. Delete it from the first target queue and add it to the second target queue; if the notification information that the target operation request has been processed is received, the target operation request and the corresponding target hash value corresponding to the notification information are deleted from the second target queue. .
  • the storage system cache manager is also used to: determine whether the target hash value collides with the hash value of the operation request in the target queue; the target queue includes a first target queue and a second target queue; if the target hash value matches If the hash value of the operation request in the target queue does not collide, the target operation request and the corresponding target hash value will continue to be stored in the first target queue; if the target hash value collides with the hash value of the operation request in the target queue, then Suspend the storage of the target operation request and the corresponding target hash value to the first target queue. If it is detected that there is no hash value in the target queue that collides with the target hash value, continue to store the target operation request and the corresponding target hash value. The value is stored in the first destination queue.
  • the target operation request is any one of the following requests: allocation request, release request, check request, lock request, unlock request, and set request.
  • the storage system cache manager is used to: receive target operation requests sent by hardware cache users, or software cache Target operation request sent by the user through the software cache manager.
  • the storage system cache manager is used to: if the target operation request is a request sent by a hardware cache user, send the response information of the target operation request to the hardware cache user, and generate event information corresponding to the response information and send it to
  • the software cache manager allows the software cache manager to perform corresponding cache maintenance operations based on the event information; if the target operation request is a request sent by the software cache user, the response information of the target operation request is sent to the software cache user. , so that the software cache manager can perform corresponding cache maintenance operations based on the response information.
  • a schematic structural diagram of an electronic device provided by an embodiment of the present application includes:
  • Memory used to store computer programs
  • a processor configured to implement the steps of the cache management method of the above method embodiment when executing a computer program.
  • the device may be a PC (Personal Computer), or a terminal device such as a smart phone, a tablet computer, a handheld computer, or a portable computer.
  • PC Personal Computer
  • terminal device such as a smart phone, a tablet computer, a handheld computer, or a portable computer.
  • the device may include a memory 21, a processor 22 and a bus 23.
  • the memory 21 includes at least one type of non-volatile readable storage medium.
  • the non-volatile readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (for example, SD or DX memory, etc.), magnetic memory. , disks, CDs, etc.
  • the memory 21 may in some embodiments be an internal storage unit of the device, such as a hard disk of the device. In other embodiments, the memory 21 may also be an external storage device of the device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, or a flash memory card equipped on the device. (Flash Card) etc.
  • Memory 21 may also include both internal storage units of the device and external storage devices.
  • the memory 21 can not only be used to store application software and various types of data installed on the device, such as program codes for executing cache management methods, but can also be used to temporarily store data that has been output or is to be output.
  • the processor 22 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor or other data processing chips for running program codes or processes stored in the memory 21 Data, such as program code that executes cache management methods, etc.
  • CPU central processing unit
  • controller a controller
  • microcontroller a microprocessor or other data processing chips for running program codes or processes stored in the memory 21 Data, such as program code that executes cache management methods, etc.
  • the bus 23 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 16, but it does not mean that there is only one bus or one type of bus.
  • the device may also include a network interface 24.
  • the network interface 24 may optionally include a wired interface and/or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which are generally used to establish communication connections between the device and other electronic devices. .
  • the device may also include a user interface 25.
  • the user interface 25 may include a display (Display) and an input unit such as a keyboard (Keyboard).
  • the optional user interface 25 may also include a standard wired interface and a wireless interface.
  • the display may be an LED display, a liquid crystal display, a touch-controlled liquid crystal display, an OLED (Organic Light-Emitting Diode, organic light-emitting diode) touch device, etc.
  • the display may also be appropriately referred to as a display screen or a display unit, and is used for displaying information processed in the device and for displaying a visualized user interface.
  • Figure 16 only shows the device with components 21-25. Those skilled in the art can understand that the structure shown in Figure 16 does not constitute a limitation on the device, and may include fewer or more components than shown in the figure. Or combining certain parts, or different parts arrangements.
  • Embodiments of the present application also disclose a computer non-volatile readable storage medium.
  • a computer program is stored on the computer non-volatile readable storage medium.
  • the cache management of the above method embodiments is implemented. Method steps.
  • the non-volatile readable storage medium can include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
  • U disk mobile hard disk
  • read-only memory Read-Only Memory
  • RAM random access memory
  • magnetic disk or optical disk etc.

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Abstract

一种高速缓存管理方法、装置、***、设备及非易失性可读存储介质，包括：存储***高速缓存管理器接收目标用户发送的目标操作请求（S101），通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作（S102）；将目标操作请求的处理结果反馈至目标用户，并通过软件高速缓存管理器根据处理结果执行对应的高速缓存维护操作（S103）。可见，针对实时性要求较低的高速缓存维护操作，可通过软件高速缓存管理器实现，针对实时性要求较高的操作请求，可通过存储***高速缓存管理器以流水线方式并行处理，降低缓存行操作的处理延迟，提高高速缓存管理的实时性。

Description

高速缓存管理方法、装置、***、设备及介质
相关申请的交叉引用
本申请要求于2022年07月21日提交中国专利局，申请号为202210856082.4，申请名称为“一种高速缓存管理方法、装置、***、设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及缓存管理技术领域，更具体地说，涉及一种高速缓存管理方法、装置、***、设备及非易失性可读存储介质。
背景技术
在计算机***中，Cache(高速缓存存储器)是一种用于存放少量，且需要被快速访问的临时数据的一种存储器，例如常见的位于CPU(central processinq unit，中央处理器)和主存储器之间的CPU Cache。而在外部存储***中，磁盘或者固态硬盘由于其存储介质的物理特性，拥有各自不同的访问延迟。这个延迟一般是远远大于主存储器的访问延迟的。为了加快外部存储的访问速度，磁盘或者固态硬盘上一般使用DRAM(Dynamic Random Access Memory，动态随机存取存储器)作为盘上数据Cache。对于位置处于磁盘、固态盘和主机CPU之间的存储加速卡，例如Raid(Redundant Arrays of Independent Disks，磁盘阵列)卡这类设备，为了提高整个存储***的性能，也需要具备Cache。
在实践中，一个外部存储的Cache管理***一般至少需要支持以下功能：
1、Cache entry和Cache line的申请和释放；其中，Cache line为缓存行，是Cache操作的基本单位；Cache entry特指在存储Cache***中管理Cache Line的节点，与Cache Line一一对应且指向Cache Line；
2、Cache entry到Cache line的映射；
3、Cache hit/miss的判断；其中，Cache Hit为Cache命中，表示某次访问时，需要***作的数据在Cache中被找到；Cache Miss为Cache未命中，表示某次访问时，需要***作的数据未在Cache中被找到；
4、保证Cache Line和外部存储数据的一致性。
在外部存储***中，基于CPU软件实现的Cache管理***较为常见。一般使用哈希表的形式来组织和存储Cache Entry。参见图1，为哈希表示意图；如图1所示，多个Cache Entry存放在一个哈希表(Hash Table)中，Hash值(散列，是把任意长度的输入数据(key)通过散列算法变换成固定长度的输出，是一种压缩映射)相同的Cache Entry存放在同一个双向链表中。而属于同一个存储介质的(例如硬盘驱动器HDD_0或Logic Drive 0)的Cache Entry使用则使用另外一个双向链表(虚线)连接。哈希表中的每个Cache Entry都指向一条Cache line。
但是，该方案的主要缺点有：
1、软件负责的Cache管理，包括分配，释放和Cache hit/miss检测，往往需要遍历链表，导致耗时较长且时延抖动，对实时性无法保证。
2、当有多个Cache访问者进行Cache操作时，往往需要软件使用互斥锁等机制来串行进行，由于被保护的临界区耗时较长，使得多个请求需排队等待，影响了吞吐率，CPU单核性能成为了***性能瓶颈。
因此，如何降低Cache操作的延迟，提高Cache管理的实时性，是本领域技术人员需要解决的问题。
发明内容
本申请实施例的目的在于提供一种高速缓存管理方法、装置、***、设备及非易失性可读存储介质，以降低Cache操作的延迟，提高Cache管理的实时性。
为实现上述目的，本申请实施例提供一种高速缓存管理方法，高速缓存管理方法应用于存储***高速缓存管理器，高速缓存管理方法包括：
接收目标用户发送的目标操作请求；
通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；
将目标操作请求的处理结果反馈至目标用户，并通过软件高速缓存管理器根据处理结果执行对应的高速缓存维护操作。
其中，利用目标操作请求对缓存行执行对应的处理操作，包括：
根据目标操作请求中的键值计算目标哈希值；
利用目标哈希值在目标数据表中进行查表；
若未查找到对应的目标地址，则输出对应的查询结果；若查找到目标地址，则根据目标地址在对应的缓存条目表中进行检索，并将检索到的键值与目标操作请求的键值进行比较，输出对应的查询结果；
根据查询结果及目标操作请求执行对应的处理操作。
其中，根据目标操作请求中的键值计算目标哈希值之前，还包括：
利用仲裁规则对各目标操作请求进行优先级排序。
其中，利用仲裁规则对各目标操作请求进行优先级排序之后，还包括：
若目标操作请求为分配请求，则判断分配请求是否超出剩余配额；
若分配请求未超出剩余配额，则继续执行根据目标操作请求中的键值计算目标哈希值的步骤；若分配请求超出剩余配额，则根据超额配置模式处理目标操作请求。
其中，判断分配请求是否超出剩余配额，包括：
确定分配请求的键值；
根据分配请求的键值确定对应的缓存计数；
判断缓存计数加一后是否大于对应的第一门限值；
若缓存计数加一后大于对应的第一门限值，则判定分配请求超出剩余配额；若缓存计数加一后小于或等于对应的第一门限值，则判断缓存计数加一后的全局计数是否大于对应的第二门限值；
若大于对应的第二门限值，则判定分配请求超出剩余配额；若不大于对应的第二门限值，则判定分配请求未超出剩余配额。
其中，根据超额配置模式处理目标操作请求，包括：
若超额配置模式为警告模式，则继续根据目标操作请求中的键值计算目标哈希值，并生成对应的事件信息发送至软件高速缓存管理器；
若超额配置模式为阻塞模式，则直接生成处理失败的处理结果。
其中，在所述直接生成处理失败的处理结果之后，所述方法还包括：
在所述目标操作请求为软件高速缓存用户发起的操作请求的情况下，上报响应信息给软件高速缓存管理器，其中，所述目标用户包括所述软件高速缓存用户；
在所述目标操作请求为硬件高速缓存用户发起的操作请求，则上报响应信息给硬件高速缓存用户，并复制事件信息上报给所述软件高速缓存管理器，其中，所述目标用户包括所述硬件高速缓存用户。
其中，根据目标操作请求中的键值计算目标哈希值，利用目标哈希值在目标数据表中进行查表，包括：
根据各目标操作请求中的键值计算对应的目标哈希值，并将目标操作请求及对应的目标哈希值存储至第一目标队列；
从第一目标队列中获取未查表的目标操作请求的目标哈希值，根据获取的目标哈希值在目标数据表中进行查表；
将已查表的目标操作请求及对应的目标哈希值从第一目标队列中删除，并添加至第二目标队列；
若接收到目标操作请求已处理的通知信息，则将与通知信息对应的目标操作请求及对应的目标哈希值从第二目标队列中删除。
其中，所述根据各目标操作请求中的键值计算对应的目标哈希值，包括：
将所述目标操作请求中的键值依次送入三个哈希函数计算模块进行计算，得到所述目标哈希值，其中，所述目标哈希值包括row，sig和CAM val。
其中，根据各目标操作请求中的键值计算对应的目标哈希值之后，还包括：
判断目标哈希值与目标队列中操作请求的哈希值是否碰撞；目标队列包括第一目标队列及第二目标队列；
若目标哈希值与目标队列中操作请求的哈希值未碰撞，则继续执行将目标操作请求及对应的目标哈希值存储至第一目标队列的步骤；
若目标哈希值与目标队列中操作请求的哈希值碰撞，则暂缓将目标操作请求及对应的目标哈希值存储至第一目标队列，若检测到目标队列中不存在与目标哈希值碰撞的哈希值，则继续执行将目标操作请求及对应的目标哈希值存储至第一目标队列的步骤。
其中，所述判断所述目标哈希值与目标队列中操作请求的哈希值是否碰撞，包括：
在所述目标哈希值与所述目标队列中操作请求的哈希值相同的情况下，确定所述目标哈希值与所述目标队列中操作请求的哈希值发生碰撞；
在所述目标哈希值与所述目标队列中操作请求的哈希值不同的情况下，确定所述目标哈希值与所述目标队列中操作请求的哈希值未发生碰撞。
其中，目标操作请求为以下请求中的任意一者：分配请求、释放请求、检查请求、锁定请求、解锁请求、设置请求。
其中，接收目标用户发送的目标操作请求，包括：
接收硬件高速缓存用户发送的目标操作请求，或者软件高速缓存用户通过软件高速缓存管理器发送的目标操作请求。
其中，将目标操作请求的处理结果反馈至目标用户，并通过软件高速缓存管理器根据处理结果执行对应的高速缓存维护操作，包括：
若目标操作请求为硬件高速缓存用户发送的请求，则将目标操作请求的响应信息发送至硬件高速缓存用 户，并生成与响应信息对应的事件信息发送至软件高速缓存管理器，以便软件高速缓存管理器根据事件信息执行对应的高速缓存维护操作；
若目标操作请求为软件高速缓存用户发送的请求，则将目标操作请求的响应信息发送至软件高速缓存用户，以便软件高速缓存管理器根据响应信息执行对应的高速缓存维护操作。
其中生成与所述响应信息对应的事件信息发送至所述软件高速缓存管理器，包括：
将所述事件信息通过事件上报的方式异步通知所述软件高速缓存管理器，其中，所述事件信息包括高速缓存分配、使用、查询等行为的信息。
为实现上述目的，本申请实施例提供一种高速缓存管理装置，高速缓存管理装置应用于存储***高速缓存管理器，高速缓存管理装置包括：
接收模块，用于接收目标用户发送的目标操作请求；
处理模块，用于通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；
发送模块，用于将目标操作请求的处理结果反馈至目标用户，并通过软件高速缓存管理器根据处理结果执行对应的高速缓存维护操作。
其中，处理模块包括：
查表单元，被设置为根据所述目标操作请求中的键值计算目标哈希值，利用所述目标哈希值在目标数据表中进行查表；
输出单元，被设置为在未查找到对应的目标地址时，输出对应的查询结果；查找到目标地址时，根据目标地址在对应的缓存条目表中进行检索，并将检索到的键值与所述目标操作请求的键值进行比较，输出对应的查询结果；
第一处理单元，被设置为根据查询结果及所述目标操作请求执行对应的处理操作。
为实现上述目的，本申请实施例提供一种高速缓存管理***，包括：
存储***高速缓存管理器，用于接收目标用户发送的目标操作请求，通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；将目标操作请求的处理结果反馈至目标用户；
软件高速缓存管理器，用于根据处理结果执行对应的高速缓存维护操作。
为实现上述目的，本申请实施例提供一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序时实现上述高速缓存管理方法的步骤。
为实现上述目的，本申请实施例提供一种计算机非易失性可读存储介质，计算机非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述高速缓存管理方法的步骤。
通过以上方案可知，本申请实施例实施例提供的一种高速缓存管理方法，该高速缓存管理方法应用于存储***高速缓存管理器，包括如下内容：接收目标用户发送的目标操作请求；通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；将目标操作请求的处理结果反馈至目标用户，并通过软件高速缓存管理器根据处理结果执行对应的高速缓存维护操作。
可见，在本方案中，针对实时性要求较低的高速缓存维护操作，可通过软件高速缓存管理器实现，针对实时性要求较高的操作请求，可通过存储***高速缓存管理器以硬件流水线方式并行处理，降低缓存行操作的处理延迟，提高高速缓存管理的实时性。
本方案还公开了一种高速缓存管理装置、***、设备及非易失性可读存储介质，同样能实现上述技术效果。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为哈希表示意图；
图2为本申请实施例公开的一种高速缓存管理方法流程示意图；
图3为本申请实施例公开的一种Cache管理***结构示意图；
图4a为本申请实施例公开的一种操作请求的格式定义图；
图4b为本申请实施例公开的一种处理结果的格式定义图；
图5为本申请实施例公开的操作请求与响应信息对应关系示意图；
图6为本申请实施例公开的状态转换示意图；
图7为本申请实施例公开的一种目标操作请求处理流程示意图；
图8为本申请实施例公开的一种硬件Cache管理器的整体结构示意图；
图9为本申请实施例公开的限额模块工作流程示意图；
图10为本申请实施例公开的Cache Line Lookup引擎结构示意图；
图11为本申请实施例公开的请求节流模块结构示意图；
图12为本申请实施例公开的Multibin哈希表结构示意图；
图13a为本申请实施例公开的一种以流水线的方式处理操作请求的示意图；
图13b为本申请实施例公开的另一种以流水线的方式处理操作请求的示意图；
图14为本申请实施例公开的一种软件Cache管理器的结构示意图；
图15为本申请实施例公开的一种高速缓存管理装置结构示意图；
图16为本申请实施例公开的一种电子设备结构示意图。
具体实施方式
目前，外部存储设备中的Cache能够为存储***带来以下优点：
1.当主机向外部存储***写入数据时，数据可以先写入Cache进行暂存并立即向主机返回“写成功”，减少访问延迟。
2.需要写入存储介质的数据，可以在Cache中排列成对存储介质更友好的方式，批量写入，提升吞吐率。
3.主机读取数据时，如果Cache hit，则直接从Cache中把读取的数据返回。减少访问延迟。而且，Cache***还可以根据读取数据的特征，从存储介质中选择性的预先读取可能将要被访问的数据放入Cache中，提升Cache hit的概率。
4.Cache***根据主机访问数据的特征，把数据区分为冷热数据。把经常被访问的热数据保留在Cache中，而把很少使用的冷数据落盘。提升Cache的使用效率。
在外部存储***中，基于CPU软件实现的Cache管理***较为常见，虽然该方案具有如下优点：软件对链表的长度没有限制，灵活性高；Cache Entry可以动态分配，利用率高；Cache Entry的冷热关系可以由链表中的位置表示；但是，通过CPU软件实现的Cache管理的方式，存在操作耗时较长、对实时性无法保证、影响了吞吐率等问题。
因此本申请提供了一种高速缓存管理方法、装置、***、设备及非易失性可读存储介质，以降低Cache操作的延迟，提高Cache管理的实时性。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参见图2，本申请实施例提供的一种高速缓存管理方法流程示意图，该高速缓存管理方法应用于存储***高速缓存管理器，该高速缓存管理方法包括如下步骤：
S101、接收目标用户发送的目标操作请求；
在本实施例中，对Cache进行管理主要通过存储***高速缓存管理器和软件高速缓存管理器两部分，在本实施例中，高速缓存即为Cache。其中，存储***高速缓存管理器可以理解为硬件Cache管理器，其主要负责高实时性的、逻辑相对简单的任务，例如：对缓存行执行的处理操作，包括：Cache分配、释放，以及Cache hit/miss查询等。而软件高速缓存管理器即为软件Cache管理器，其主要处理实时性要求相对较低，但逻辑复杂的Cache维护操作，例如冷热数据的维护，Cache落盘策略实现等。
参见图3，为本申请实施例公开的一种Cache管理***结构示意图，该Cache管理***包括硬件Cache管理器及软件Cache管理器，该硬件Cache管理器用于接收硬件高速缓存用户发送的目标操作请求，或者软件高速缓存用户通过软件高速缓存管理器发送的目标操作请求，其中，该硬件高速缓存用户为硬件Cache用户，是可以发起Cache业务请求的外部硬件模块，软件高速缓存用户为软件Cache用户，是可以发起Cache业务请求的外部软件模块。硬件Cache管理器向硬件Cache用户和软件Cache管理器分别提供请求和响应的信号或寄存器接口，并按照Cache管理***定义的格式发起请求和接收响应。软件Cache管理器向软件Cache用户提供Cache操作API(Application Programming Interface，应用程序编程接口)接口，软件Cache用户发起的操作请求通过软件Cache管理器发送给硬件Cache管理器。
需要说明的是，硬件Cache管理器所接收的硬件Cache用户或软件Cache用户发送的Cache请求均为操作请求，在本实施例中，将硬件Cache管理器当前接收的操作请求称为目标操作请求。并且，Cache管理***以device_id(驱动器设备号)和lba(Logical block addressing，逻辑区块地址)建立对缓存行Cache Line的索引，仅支持固定大小的Cache Line。Device代表一个逻辑或者物理存储设备。参见图4a，为本申请实施例公开的一种操作请求的格式定义图，在图4a中，各字段定义如下：
Requester：标识请求发起方，包括User_type及User_id；
User_type：用来区分硬件Cache用户及软件Cache用户；
User_id：有多个硬件Cache用户/软件Cache用户时，使用User_id区分；
Request Seq：每个硬件Cache用户/软件Cache用户发送请求的请求序号，从0开始，每个请求加1；
Key：用来进行Cache操作的参数数据元组，包括device_id及lba；在本实施例中，该Key的具体数值通过键值表示；
device_id：驱动器设备号；
lba：Cache Line对应的Device LBA地址；
Action：表示请求是哪种操作，可能是以下操作中的一种：
alloc：分配Cache Line；
free：释放Cache Line；
check：检测数据是否在Cache Line；
Lock：锁定Cache Line，锁定后不能free，且Check返回locked；
Unlock：解锁Cache Line；
Set Modify：设置Cache数据状态为“已修改”；
Set Invalid：设置Cache Line数据状态为“无效”。
可以看出，本申请可根据操作请求中的Action确定目标操作请求为哪种类型的操作请求，在本实施例中，该目标操作请求为以下请求中的任意一者：分配请求、释放请求、检查请求、锁定请求、解锁请求、设置请求。
S102、通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；
本实施例中的硬件Cache管理器允许软件Cache用户和硬件Cache用户以异步的方式提交多个操作请求。硬件Cache管理器接收到软件Cache用户和硬件Cache用户发起的操作请求时，使用硬件流水线的方式处理这些请求，以达到Cache请求处理的高吞吐率。
S103、将目标操作请求的处理结果反馈至目标用户，并通过软件高速缓存管理器根据处理结果执行对应的高速缓存维护操作。
由于本方案中的目标用户可以为硬件Cache用户及软件Cache用户，因此本方案在反馈处理结果时，需要确定目标操作请求具体是哪个用户发送的，然后将操作结果反馈至对应用户。本方案中的处理结果包括：响应信息及事件信息两种，若目标操作请求为硬件高速缓存用户发送的请求，则将目标操作请求的响应信息发送至硬件高速缓存用户，并生成与该响应信息对应的事件信息发送至软件高速缓存管理器，以便软件高速缓存管理器根据事件信息执行对应的高速缓存维护操作；若目标操作请求为软件高速缓存用户发送的请求，则将目标操作请求的响应信息发送至软件高速缓存用户，以便软件高速缓存管理器根据响应信息执行对应的高速缓存维护操作。也就是说，本申请中的硬件Cache管理器在响应软件Cache用户的操作请求时，通过响应信息通知软件Cache管理器，硬件Cache管理器在响应硬件Cache用户发起的请求时，不仅需要将响应信息发送给硬件Cache用户，还需要通过事件上报的方式异步通知软件Cache管理器，包括Cache分配、使用、查询等行为，通过该方式，使得软件Cache管理器可从响应/事件中提取有用的信息，完成各种复杂的Cache维护工作。如：对某个Device的Cache Line进行冷热数据排序，或者对连续地址的Cache Line进行连接等等。
参见图4b，为本申请实施例公开的一种处理结果的格式定义图，图4a与图4b中相同字段在此并不赘述。处理结果中各字段定义如下：
SW Hash Value：由硬件Cache管理器代为计算的，由软件Cache管理器检索Cache Entry的哈希值；
Type：用来区分响应信息还是事件信息；
Response：表示处理结果为响应信息；
Event：表示处理结果为事件信息；
Result：表示请求成功或失败；
Ok：表示请求处理成功；
Fail：表示请求处理失败；
Status：表示成功或失败的原因，是一个数据元组，包括：Invalid/Modified、Miss、Col、Qouta及Locked/Unlocked；
Invalid/Modified：表示Cache***中有对应的Cache Line，且状态为Invalid(无效)或Modified(被修改)两种状态之一；
Miss：表示Cache miss，即未找到对应的Cache Line；
Col：collision，表示硬件Cache管理器中由于哈希冲突，导致无法分配Cache Line；
Qouta：表示请求的Cache Line请求超过了某个配额规则的限制。
Locked/Unlocked：表示Cache***中有对应的Cache Line，且状态为locked或unlocked两种状态之一；
Response/Event Data Length：响应或者事件的附加数据的长度；
Response/Event Data：响应或者事件的附加数据。对于Alloc、hit、check命令的响应和事件，其内容为Cache Entry；仅当Alloc申请block超过限额的响应或事件，其内容为限额模块内对应的超限表项。
参见图5，为本申请实施例公开的操作请求与响应信息对应关系示意图。可以看出，不同的操作请求根据操作结果生成不同的响应信息。当然，图5所示的对应关系仅仅为请求和可能收到的响应之间的对应关系，在实际应用中，本方案并不仅仅局限于图5所示的对应关系。
参见图6，为本申请实施例提供的状态转换示意图，如图6所示，对于每个Cache Line来说，可能的状态包括：Not Cached、Invalid、Invalid&locked、Modify、Modify&locked，通过外部输入的操作请求，控制Cache Line的状态在多个状态间跳转。其中，Not Cache表示尚未纳入Cache管理器管理的Cache Line的状态，并不在Cache管理器中记录；申请Cache Line后状态变为Invalid，表示Cache Line已申请但是Cache Line中的数据是无效的；如果硬件或软件Cache用户需要独占某个Cache Line，则可以通过lock命令把Cache Line改变为Lock状态，如：Invalid&locked及Modify&locked，处于Lock状态时Cache Line不支持Free，也不能被再次lock。如果需要标记Cache Line中的数据是否被改写，则可以通过Set State Modify命令转换Cache Line为Modify。处于Modify状态时Cache Line不支持Free。
需要说明的是，对Lock状态和Modify状态的使用完全是由Cache管理器的用户决定的。在实际的应用中，用户可根据实际的需求，仅使用Action和Cache Line状态的子集。例如：
1、仅支持最基本的Cache分配，释放和hit/miss check功能。
Action：Alloc/Free/Check；
State：Not Cached/Invalid；
2、在最基本的Cache功能上，增加对Cache Line锁的支持。
Action：Alloc/Free/Check/Lock/Unlock；
State：Not Cached/Invalid/Invalid locked；
3、在最基本的Cache功能上，增加对Cache Line Modify和Invalid状态的支持。
Action：Alloc/Free/Check/Set M/Set I；
State：Not Cached/Invalid/Modified；
4、全功能模式，包括所有的Action和State。
综上可见，在本方案中，通过软件和硬件相结合的方式对Cache进行管理，针对实时性要求较低的Cache维护操作，可通过软件Cache管理器实现，针对实时性要求较高的操作请求，可通过硬件Cache管理器以流水线方式并行处理，降低缓存行操作的处理延迟，提高Cache管理的实时性。
参见图7，为本申请实施例提供的一种目标操作请求处理流程示意图，如图7所示，本实施例对S102利用目标操作请求对缓存行执行对应的处理操作的过程进行说明，该过程包括如下步骤：
S201、利用仲裁规则对各目标操作请求进行优先级排序；
参见图8，为本申请实施例提供的一种硬件Cache管理器的整体结构示意图，在本实施例中，对于硬件和软件Cache用户发起的多路Cache Line操作请求，会在硬件Cache管理器内先进入FIFO(First Input First Output，先进先出)队列进行缓冲，之后在仲裁器内通过一定的规则仲裁后，输出到限额模块。在本实施例中，仲裁器中设置的仲裁规则可根据实际需求进行设定，如：设置硬件Cache用户发送的操作请求的优先级高于软件Cache用户发送的操作请求的优先级，那么进行优先级排序时，需要将硬件Cache用户发送的操作请求排在软件Cache用户发送的操作请求之前，以便根据各操作请求的优先级排序，依次将各操作请求输入限额模块，继续执行后续步骤。
S202、若目标操作请求为分配请求，则判断分配请求是否超出剩余配额；
若分配请求超出剩余配额，则执行S203；若分配请求未超出剩余配额，则执行S204；
S203、根据超额配置模式处理目标操作请求；
其中，在S202中判断分配请求是否超出剩余配额时，需要确定分配请求的键值；根据分配请求的键值确定对应的缓存计数；判断缓存计数加一后是否大于对应的第一门限值；若缓存计数加一后大于对应的第一门限值，则判定分配请求超出剩余配额；若缓存计数加一后小于或等于对应的第一门限值，则判断缓存计数加一后的全局计数是否大于对应的第二门限值；若大于对应的第二门限值，则判定分配请求超出剩余配额；若不大于对应的第二门限值，则判定分配请求未超出剩余配额。
本方案中的限额模块负责各Device和全局的Cache配额管理，当输入的Alloc分配请求没有超过剩余配额时，限额模块转发该分配请求到缓存行查找引擎(即图10的Cache Line lookup引擎)，如果超出，则限额模块拦截此分配请求，并发送超出限额响应到响应器。
本方案中的限额模块实现了若干个逐盘的Cache计数器和门限值的表项，以及若干个全局Cache门限表项。参见图9，为本申请实施例提供的限额模块工作流程示意图，通过图9可以看出，接收到操作请求Request后，对于分配请求Alloc，限额模块提取Alloc分配请求的key中的device id项，并在限额表项中读取对应的缓存计数Cache counter。计算缓存计数Cache Counter加1后的值是否大于第一门限值Threshold(T_hold)。同理，并行检查所有的全局表项。如果计算结果均小于对应的第二门限值，则允许该分配请求通过，并转发给Cache Line lookup引擎，否则返回Fail的响应给响应器。
需要说明的是，若Cache Counter加1后的值大于门限，或者所有的全局表项的值大于门限，此时可根据超额配置模式来决定如何处理该操作请求。每个表项的超额配置模式可配置为警告(Warning)模式或阻塞(Blocking)模式。若超额配置模式为警告模式，则继续执行S204，并生成对应的事件信息发送至软件高速 缓存管理器；若超额配置模式为阻塞模式，则直接生成处理失败的处理结果。也就是说：在警告模式下，当检测超过门限后，仍会向后转发请求，但同时会通过响应器上报事件给软件Cache管理器。在阻塞模式下，限额向响应器直接返回Fail响应，响应器收到从限额模块发来的Fail后，若是软件Cache用户发起的操作请求，则上报响应信息给软件Cache管理器，若是硬件Cache用户发起的操作请求，则上报响应信息给硬件Cache用户后，还需要复制一份事件信息上报给软件Cache管理器。
S204、根据目标操作请求中的键值计算目标哈希值；
S205、利用目标哈希值在目标数据表中进行查表；
其中，本实施例中的S204和S205包括如下内容：根据各目标操作请求中的键值计算对应的目标哈希值，并将目标操作请求及对应的目标哈希值存储至第一目标队列；从第一目标队列中获取未查表的目标操作请求的目标哈希值，根据获取的目标哈希值在目标数据表中进行查表；将已查表的目标操作请求及对应的目标哈希值从第一目标队列中删除，并添加至第二目标队列；若接收到目标操作请求已处理的通知信息，则将与通知信息对应的目标操作请求及对应的目标哈希值从第二目标队列中删除。
在本实施例中，为了避免出现哈希碰撞现象，本方案根据各目标操作请求中的键值计算对应的目标哈希值之后，还需要判断目标哈希值与目标队列中操作请求的哈希值是否碰撞；该目标队列包括第一目标队列及第二目标队列；若目标哈希值与目标队列中操作请求的哈希值未碰撞，则继续将目标操作请求及对应的目标哈希值存储至第一目标队列；若目标哈希值与目标队列中操作请求的哈希值碰撞，则暂缓将目标操作请求及对应的目标哈希值存储至第一目标队列，若检测到目标队列中不存在与目标哈希值碰撞的哈希值，则继续将目标操作请求及对应的目标哈希值存储至第一目标队列。
在本实施例中，Cache Line lookup引擎主要负责查表并输出查询结果，并将操作请求及查询结果输出给命令处理引擎。参见图10，为本申请实施例提供的Cache Line Lookup引擎结构示意图。通过图10可以看出，Cache Line Lookup引擎收到操作请求后，先送往其内部的请求节流模块对操作请求进行缓冲，请求节流模块负责控制命令下发的时机，保证在任意的时刻，在其后的输入的操作请求与请求节流模块中排队等待的所有请求没有哈希碰撞，其中：哈希碰撞是指两个内容不相同的key通过hash计算后，获得的输出值一样，则是一个哈希碰撞(Collision)。同时，该请求节流模块也从key指计算出了用于查表的目标哈希值，在本实施例中，该目标哈希值包括：row，signature和CAM val。用于分别查Multibin hash table和CAM表。
参见图11，为本申请实施例提供的请求节流模块结构示意图，通过图11可以看出，请求节流模块从限额模块接收到操作请求后，送入请求FIFO队列。经过FIFO队列缓冲过的操作请求的Key被依次送入三个哈希函数计算模块进行计算得到目标哈希值，目标哈希值包括row，sig和CAM val这三个值，这三个值与原始的请求合并作为一个查表元素LE(lookup element)。在Throttle节流子模块的控制下，转发至LE Send Queue(查表元素发送队列)。LE Send Queue中暂存的是待送往下游模块查表的LE。LE output模块(查表元素输出模块)会在next_stage_ready信号(下一阶段就绪)的控制下，从LE Send Queue中读取去LE，并把LE送往目标数据表进行查表，在本方案中，目标数据表包括mutilbin哈希表和CAM进行；同时，LE output模块会把送去查表的LE拷贝一份送往LE response Queue(查表元素响应队列)。需要说明的是，命令处理引擎每处理完一个操作请求会，便会向Sink模块发送完成请求的ID信息，Sink模块将该请求ID信息与LE response Queue的队首元素进行对比，如果匹配，则从LE response Queue读出一个LE并丢弃。
通过上述内容可以看出，本方案在任意时刻均需要检测目标哈希值与目标队列(第一目标队列及第二目标队列)中操作请求的哈希值是否碰撞，该目标哈希值是指待进入LE Send Queue的LE中的哈希值，目标队列是指LE Send Queue(第一目标队列)和LE response Queue(第二目标队列)，也即：本方案需要将LE Send Queue和LE response Queue的所有元素与待进入LE Send Queue的LE进行对比，仅当Row，Sig和CAM val不冲突的情况下，才允许LE通过Throttle模块进入LE Send Queue。否则，则阻塞当前LE，并等待LE Send Queue和LE response Queue中相冲突的LE服务完毕，即被Sink丢弃后才放行。通过此机制，能够保证有冲突的多个请求的从查表到执行(命令处理引擎)的过程是串行的，而不冲突的请求是按照流水的方式并发执行的。
S206、若未查找到对应的目标地址，则输出对应的查询结果；若查找到目标地址，则根据目标地址在对应的缓存条目表中进行检索，并将检索到的键值与目标操作请求的键值进行比较，输出对应的查询结果；
本实施例中的Cache Line Lookup引擎的内部有两个查表机制，该目标数据表包括：Multibin哈希表和CAM表。参见图10，请求节流输出操作请求的三个哈希值后，需要在Multibin哈希表和CAM表中进行查表。参见图12，为本申请实施例提供的Multibin哈希表结构示意图，Multibin哈希表是一个二维的哈希表，有2^m行和2^n列。当进行查表时，需要现根据输入的宽度为m的Row值来选定行，然后根据输入的signature值来进行每行数据的匹配。匹配输出的结果包括以下三项：
1.matched。为1表示匹配到了相同的signature值。
2.pointer。匹配上的signature的bin里，存放的pointer(指针)值。
3.first_free_bin。表示该行第一个空闲的bin的index。用于命令处理引擎***新的表项时使用。
定义pointer＝0为非法值，在初始化时所有bin中元素初始化为0。
如图10所示，根据Row值和signature值在Multibin哈希表中查表后，可从匹配结果中输出指针，该指针可指向Cache Entry Table(缓存条目表)中的目标地址，同样的，根据CAM val值在CAM表进行查表后，可得出目标地址，若在这两个表中均未找到匹配的目标地址，则说明Cache Line未命中；若查找到指针/地址，则根据目标地址在对应的Cache Entry Table中进行检索，将检索结果中的Key的数值与操作请求中原始的Key的数值进行对比，如果对比后发现有完全匹配的项，则说明Cache Line命中，如果没有则说明Cache Line未命中，Cache Line的查询结果和原始操作请求会在拼接后发送给命令处理引擎。
S207、根据查询结果及目标操作请求执行对应的处理操作。
在本实施例中，命令处理引擎会根据Cache Line Lookup引擎发送的Cache Line查询结果，以及目标操作请求中的Action来做出对应的处理操作，包括从Cache Line分配器申请或释放Cache Line，更新Multibin哈希表和CAM，更新Cache Entry表，组织响应和事件发送给响应器，更新限额模块的计数。
需要说明的是，在本实施例中，命令处理引擎与Cache Line Lookup引擎配合，以多级流水线的方式并行完成各操作请求的处理。命令处理引擎流水线的每一级由一个状态机实现，当本级工作完成后，传递处理完的结果到流水线的下一级。参见图13a，为本申请实施例提供的一种以流水线的方式处理操作请求的示意图，图13a流水线中每一级的命名和功能描述如下：
Lookup：Cache Line查表，由Cache Line Lookup引擎实现。
Execute：负责处理请求，提取Action并执行对应的操作。为后续流水线生成指令。
Update LK：更新Cache Line Lookup引擎中的Multibin哈希表和CAM。
Update CL：更新Cache Entry Table。
Update限额：更新限额模块中对应device id的counter和global counter。
Update CPL：通知Cache Line Lookup引擎请求已经处理完毕。
响应：把响应送往响应器。
需要说明的是，并不是所有类型的命令都需要每级流水线参与处理。参见图13b，为本申请实施例提供的另一种以流水线的方式处理操作请求的示意图，通过图13b所示，若某些命令不需要某一级流水线，则在执行时生成NOP指令跳过即可。
在本实施例中，Cache Line分配器管理Cache Line的申请和释放，当命令处理引擎发送Alloc操作命令时，Cache Line分配器其内部的Cache Line资源池获取一个Cache Line返回给命令处理引擎。当收到释放命令时，把释放的Cache Line存储内部的资源池。Cache Line分配器是由一个传统的环形队列实现的，内部有头尾指针分别指向首节点和尾结点。在***初始化时由软件Cache管理器填入所有的Cache Line。当收到有Alloc请求时，从头指针读出一个元素，之后头指针模加1。当收到Free请求时，把输入的元素放到尾指针，之后尾指针模加1。当队列空时，对Alloc请求返回失败。当队列满时，对Free请求返回失败。
在本实施例中，响应器负责接收限额和命令处理引擎发来的响应和事件，并根据响应中的信息区分是发送给硬件还是软件，如果需要发送给硬件，则直接通过硬件Cache用户的接口信号发送给对应的硬件Cache用户。如果需要发送给软件，则把响应转发给软件接口逻辑。软硬件接口逻辑内部负责接收软件Cache管理器下发的Cache操作请求，并将该操作请求发送至硬件Cache管理器，并汇聚硬件Cache管理器中的响应器发送的响应信息以及命令处理引擎发送的事件信息，并上报给软件Cache管理器。软硬件接口使用单一请求和响应队列，交互流程与NVMe(Non Volatile Memory Express，非易失性快速存储器)的I0(Input/0utput，输入/输出)队列协议相同。
参见图14，为本申请实施例提供的一种软件Cache管理器的结构示意图，在本实施例中，软件Cache管理器是基于传统的软件Cache管理机制的一种实现。图14中软件Hash表部分与传统软件Cache Hash表管理逻辑相同。在此基础之上，软件Cache管理器增加了请求处理模块，该请求处理模块用于接收软件Cache用户的API调用，组织Cache操作请求和接收响应。响应事件分流模块负责从响应，事件队列中获取响应信息及事件信息，队列中的响应信息及事件信息是硬件Cache管理器下发的，该响应信息及事件信息在软件Cache管理器内部区分并进行分流。事件信息直接路由给软件Hash表进行表项的更新，而响应信息则交由请求处理模块，在请求处理模块处理完响应后，也改为事件通知软件Hash表进行更新。
需要说明的是，本方案可适用于存储加速中，需要对存储介质进行Cache缓冲，而且硬件加速引擎和软件任务需要并行操作Cache的场景。为了对本方案进行详细说明，在此，分别对硬件Cache用户及软件Cache用户发起的操作请求进行处理的流程进行举例说明：
若以操作请求为硬件Cache用户发起的，在multibin哈希表中分配Cache Line的Alloc请求为例，则完整操作步骤如下：
1.硬件Cache用户发送Cache Line操作请求，通过Arbiter_0发送给限额模块；
2.限额模块检查Alloc请求的Device和Global门限项，发现没有超过剩余配额，限额模块转发请求到下游的Cache Line lookup模块；
3.Cache Line lookup收到请求后，完成Key的查找，发现multibin hash table没有Cache hit，输出结果到命令处理引擎模块；
5.命令处理引擎发现是Alloc命令，而且multibin哈希表未命中。向Alloc Engine申请并获得Cache Line；
6.命令处理引擎更新Multibin哈希表对应Row的fir st_free_bin地址的Cache Line Entry为signature和pointer；
7.命令处理引擎更新Cache Entry Table，内容包括Alloc分配获得的Cache Line地址；
8.命令处理引擎向响应器发送响应信息；
9.响应器向限额模块发送对应的Device ID限额Entry加1的指令；
10.命令处理引擎向Cache Line lookup模块发送completion Req ID；
11.响应器向硬件Cache用户发送响应。
若以一个软件Cache用户发起的，在CAM中分配Cache Line的Alloc请求为例，则完整操作步骤如下：
1.软件Cache用户发送Cache Line操作请求，通过Arbiter_0发送给限额模块；
2.限额模块检查Alloc请求的Device和Global门限项，发现没有超过剩余配额，限额模块转发请求到下游的Cache Line lookup模块；
3.Cache Line lookup收到请求后，完成Key的查找，发现multibin hash table已经冲突，且连读地址中没有空闲的entry。但是CAM中没有匹配项，输出结果到命令处理引擎模块；
5.命令处理引擎根据Cache Line查询结果，向Alloc Engine申请并获得Cache Line；
6.命令处理引擎更新CAM表，增加Cache Entry到CAM表；
7.命令处理引擎更新CAM Cache Entry Table；
8.命令处理引擎向响应器发送响应信息；
9.命令处理引擎向Cache Line lookup模块发送completion Req ID；
10.命令处理引擎向软件接口发送给响应信息；
11.软件Cache管理器从接口读取响应，计算哈希值并把Cache Entry加入软件Hash表。
综上可以看出，在本方案中，公开了一种软硬件结合的Cache管理方案，本方案使用硬件实现Cache Line的查询、分配和释放逻辑，使得Cache Line操作的延迟降低，满足了高吞吐率和高灵活性的要求。本方案还支持硬件和软件发起的Cache Line并发访问，并且通过Cache Line锁和Cache Line状态的机制保证了Cache Line的一致性。本方案通过限额模块，实现了实时的门限检测和拦截，本方案通过冲突检测和规避的技术，实现了保证Cache一致性的前提下的Cache Line请求的流水线处理。
下面对本申请实施例提供的高速缓存管理装置、***、设备及非易失性可读存储介质进行介绍，下文描述的高速缓存管理装置、***、设备及非易失性可读存储介质与上文描述的高速缓存管理方法可以相互参照。
参见图15，本申请实施例提供的一种高速缓存管理装置结构示意图，该高速缓存管理装置应用于存储***高速缓存管理器，该高速缓存管理装置包括：
接收模块11，用于接收目标用户发送的目标操作请求；
处理模块12，用于通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；
发送模块13，用于将目标操作请求的处理结果反馈至目标用户，并通过软件Cache管理器根据处理结果执行对应的高速缓存维护操作。
其中，处理模块12包括：
查表单元，用于根据目标操作请求中的键值计算目标哈希值，利用目标哈希值在目标数据表中进行查表；
输出单元，用于在未查找到对应的目标地址时，输出对应的查询结果；查找到目标地址时，根据目标地址在对应的缓存条目表中进行检索，并将检索到的键值与目标操作请求的键值进行比较，输出对应的查询结果；
第一处理单元，用于根据查询结果及目标操作请求执行对应的处理操作。
其中，处理模块12还包括：
排序单元，用于利用仲裁规则对各目标操作请求进行优先级排序；
第一判断单元，用于在目标操作请求为分配请求时，判断分配请求是否超出剩余配额；若分配请求未超出剩余配额，则触发计算单元根据目标操作请求中的键值计算目标哈希值；若分配请求超出剩余配额，则通过第二处理单元根据超额配置模式处理目标操作请求。
其中，第一判断单元用于：确定分配请求的键值；根据分配请求的键值确定对应的缓存计数；判断缓存计数加一后是否大于对应的第一门限值；若缓存计数加一后大于对应的第一门限值，则判定分配请求超出剩余配额；若缓存计数加一后小于或等于对应的第一门限值，则判断缓存计数加一后的全局计数是否大于对应的第二门限值；若大于对应的第二门限值，则判定分配请求超出剩余配额；若不大于对应的第二门限值，则判定分配请求未超出剩余配额。
其中，第二处理单元用于：若超额配置模式为警告模式，则继续根据目标操作请求中的键值计算目标哈希值，并生成对应的事件信息发送至软件高速缓存管理器；若超额配置模式为阻塞模式，则直接生成处理失败的处理结果。
其中，查表单元用于：根据各目标操作请求中的键值计算对应的目标哈希值，并将目标操作请求及对应的目标哈希值存储至第一目标队列；从第一目标队列中获取未查表的目标操作请求的目标哈希值，根据获取的目标哈希值在目标数据表中进行查表；将已查表的目标操作请求及对应的目标哈希值从第一目标队列中删除，并添加至第二目标队列；若接收到目标操作请求已处理的通知信息，则将与通知信息对应的目标操作请求及对应的目标哈希值从第二目标队列中删除。
其中，查表单元还用于：判断目标哈希值与目标队列中操作请求的哈希值是否碰撞；目标队列包括第一目标队列及第二目标队列；若目标哈希值与目标队列中操作请求的哈希值未碰撞，则继续将目标操作请求及对应的目标哈希值存储至第一目标队列；若目标哈希值与目标队列中操作请求的哈希值碰撞，则暂缓将目标操作请求及对应的目标哈希值存储至第一目标队列，若检测到目标队列中不存在与目标哈希值碰撞的哈希值，则继续将目标操作请求及对应的目标哈希值存储至第一目标队列。
其中，目标操作请求为以下请求中的任意一者：分配请求、释放请求、检查请求、锁定请求、解锁请求、设置请求。
其中，接收模块11用于接收硬件高速缓存用户发送的目标操作请求，或者软件高速缓存用户通过软件高速缓存管理器发送的目标操作请求。
其中，发送模块13包括：
第一发送单元，用于在目标操作请求为硬件高速缓存用户发送的请求时，则将目标操作请求的响应信息发送至硬件高速缓存用户，并生成与响应信息对应的事件信息发送至软件高速缓存管理器，以便软件Cache管理器根据事件信息执行对应的高速缓存维护操作；
第二发送单元，用于在目标操作请求为软件高速缓存用户发送的请求时，则将目标操作请求的响应信息发送至软件高速缓存用户，以便软件Cache管理器根据响应信息执行对应的高速缓存维护操作。
本申请实施例还公开了一种高速缓存管理***，该***包括：
存储***高速缓存管理器，用于接收目标用户发送的目标操作请求，通过流水线方式处理目标操作请求，以便利用目标操作请求对缓存行执行对应的处理操作；将目标操作请求的处理结果反馈至目标用户；
软件高速缓存管理器，用于根据处理结果执行对应的高速缓存维护操作。
其中，该存储***高速缓存管理器用于：根据目标操作请求中的键值计算目标哈希值，利用目标哈希值在目标数据表中进行查表，若未查找到对应的目标地址，则输出对应的查询结果；若查找到目标地址，则根据目标地址在对应的缓存条目表中进行检索，并将检索到的键值与目标操作请求的进行比较，输出对应的查询结果，根据查询结果及目标操作请求执行对应的处理操作。
其中，该存储***高速缓存管理器还用于：利用仲裁规则对各目标操作请求进行优先级排序。
其中，该存储***高速缓存管理器还用于：若目标操作请求为分配请求，则分配请求是否超出剩余配额；若分配请求未超出剩余配额，则继续执行根据目标操作请求中的键值计算目标哈希值的步骤；若分配请求超出剩余配额，则根据超额配置模式处理目标操作请求。
其中，该存储***高速缓存管理器用于：确定分配请求的键值；根据分配请求的键值确定对应的缓存计数；判断缓存计数加一后是否大于对应的第一门限值；若缓存计数加一后大于对应的第一门限值，则判定分配请求超出剩余配额；若缓存计数加一后小于或等于对应的第一门限值，则判断缓存计数加一后的全局计数是否大于对应的第二门限值；若大于对应的第二门限值，则判定分配请求超出剩余配额；若不大于对应的第二门限值，则判定分配请求未超出剩余配额。
其中，该存储***高速缓存管理器用于：若超额配置模式为警告模式，则继续根据目标操作请求中的键值计算目标哈希值，并生成对应的事件信息发送至软件高速缓存管理器；若超额配置模式为阻塞模式，则直接生成处理失败的处理结果。
其中，该存储***高速缓存管理器用于：根据各目标操作请求中的键值计算对应的目标哈希值，并将目标操作请求及对应的目标哈希值存储至第一目标队列；从第一目标队列中获取未查表的目标操作请求的目标哈希值，根据获取的目标哈希值在目标数据表中进行查表；将已查表的目标操作请求及对应的目标哈希值从第一目标队列中删除，并添加至第二目标队列；若接收到目标操作请求已处理的通知信息，则将与通知信息对应的目标操作请求及对应的目标哈希值从第二目标队列中删除。
其中，该存储***高速缓存管理器还用于：判断目标哈希值与目标队列中操作请求的哈希值是否碰撞；目标队列包括第一目标队列及第二目标队列；若目标哈希值与目标队列中操作请求的哈希值未碰撞，则继续将目标操作请求及对应的目标哈希值存储至第一目标队列；若目标哈希值与目标队列中操作请求的哈希值碰撞，则暂缓将目标操作请求及对应的目标哈希值存储至第一目标队列，若检测到目标队列中不存在与目标哈希值碰撞的哈希值，则继续将目标操作请求及对应的目标哈希值存储至第一目标队列。
其中，目标操作请求为以下请求中的任意一者：分配请求、释放请求、检查请求、锁定请求、解锁请求、设置请求。
其中，该存储***高速缓存管理器用于：接收硬件高速缓存用户发送的目标操作请求，或者软件高速缓存 用户通过软件高速缓存管理器发送的目标操作请求。
其中，该存储***高速缓存管理器用于：若目标操作请求为硬件高速缓存用户发送的请求，则将目标操作请求的响应信息发送至硬件高速缓存用户，并生成与响应信息对应的事件信息发送至软件高速缓存管理器，以便软件高速缓存管理器根据事件信息执行对应的高速缓存维护操作；若目标操作请求为软件高速缓存用户发送的请求，则将目标操作请求的响应信息发送至软件高速缓存用户，以便软件高速缓存管理器根据响应信息执行对应的高速缓存维护操作。
参见图16，本申请实施例提供的一种电子设备结构示意图，包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序时实现上述方法实施例的高速缓存管理方法的步骤。
在本实施例中，设备可以是PC(Personal Computer，个人电脑)，也可以是智能手机、平板电脑、掌上电脑、便携计算机等终端设备。
该设备可以包括存储器21、处理器22和总线23。
其中，存储器21至少包括一种类型的非易失性可读存储介质，非易失性可读存储介质包括闪存、硬盘、多媒体卡、卡型存储器(例如，SD或DX存储器等)、磁性存储器、磁盘、光盘等。存储器21在一些实施例中可以是设备的内部存储单元，例如该设备的硬盘。存储器21在另一些实施例中也可以是设备的外部存储设备，例如设备上配备的插接式硬盘，智能存储卡(Smart Media Card，SMC)，安全数字(Secure Digital，SD)卡，闪存卡(Flash Card)等。存储器21还可以既包括设备的内部存储单元也包括外部存储设备。存储器21不仅可以用于存储安装于设备的应用软件及各类数据，例如执行高速缓存管理方法的程序代码等，还可以用于暂时地存储已经输出或者将要输出的数据。
处理器22在一些实施例中可以是一中央处理器(Central Processing Unit，CPU)、控制器、微控制器、微处理器或其他数据处理芯片，用于运行存储器21中存储的程序代码或处理数据，例如执行高速缓存管理方法的程序代码等。
该总线23可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图16中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
设备还可以包括网络接口24，网络接口24可选的可以包括有线接口和/或无线接口(如WI-FI接口、蓝牙接口等)，通常用于在该设备与其他电子设备之间建立通信连接。
可选地，该设备还可以包括用户接口25，用户接口25可以包括显示器(Display)、输入单元比如键盘(Keyboard)，可选的用户接口25还可以包括标准的有线接口、无线接口。可选地，在一些实施例中，显示器可以是LED显示器、液晶显示器、触控式液晶显示器以及OLED(0rganic Light-Emitting Diode，有机发光二极管)触摸器等。其中，显示器也可以适当的称为显示屏或显示单元，用于显示在设备中处理的信息以及用于显示可视化的用户界面。
图16仅示出了具有组件21-25的设备，本领域技术人员可以理解的是，图16示出的结构并不构成对设备的限定，可以包括比图示更少或者更多的部件，或者组合某些部件，或者不同的部件布置。
本申请实施例还公开了一种计算机非易失性可读存储介质，计算机非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述方法实施例的高速缓存管理方法的步骤。
其中，该非易失性可读存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种高速缓存管理方法，其特征在于，所述高速缓存管理方法应用于存储***高速缓存管理器，所述高速缓存管理方法包括：
    接收目标用户发送的目标操作请求；
    通过流水线方式处理所述目标操作请求，以便利用所述目标操作请求对缓存行执行对应的处理操作；
    将所述目标操作请求的处理结果反馈至所述目标用户，并通过软件高速缓存管理器根据所述处理结果执行对应的高速缓存维护操作。
  2. 根据权利要求1所述的高速缓存管理方法，其特征在于，利用所述目标操作请求对缓存行执行对应的处理操作，包括：
    根据所述目标操作请求中的键值计算目标哈希值；
    利用所述目标哈希值在目标数据表中进行查表；
    若未查找到对应的目标地址，则输出对应的查询结果；若查找到目标地址，则根据所述目标地址在对应的缓存条目表中进行检索，并将检索到的键值与所述目标操作请求的键值进行比较，输出对应的查询结果；
    根据查询结果及所述目标操作请求执行对应的处理操作。
  3. 根据权利要求2所述的高速缓存管理方法，其特征在于，根据所述目标操作请求中的键值计算目标哈希值之前，还包括：
    利用仲裁规则对各目标操作请求进行优先级排序。
  4. 根据权利要求3所述的高速缓存管理方法，其特征在于，所述利用仲裁规则对各目标操作请求进行优先级排序之后，还包括：
    若所述目标操作请求为分配请求，则判断所述分配请求是否超出剩余配额；
    若所述分配请求未超出所述剩余配额，则继续执行根据所述目标操作请求中的键值计算目标哈希值的步骤；若所述分配请求超出所述剩余配额，则根据超额配置模式处理所述目标操作请求。
  5. 根据权利要求4所述的高速缓存管理方法，其特征在于，所述判断所述分配请求是否超出剩余配额，包括：
    确定所述分配请求的键值；
    根据所述分配请求的键值确定对应的缓存计数；
    判断所述缓存计数加一后是否大于对应的第一门限值；
    若所述缓存计数加一后大于对应的所述第一门限值，则判定所述分配请求超出剩余配额；若所述缓存计数加一后小于或等于对应的所述第一门限值，则判断所述缓存计数加一后的全局计数是否大于对应的第二门限值；
    若大于对应的第二门限值，则判定所述分配请求超出剩余配额；若不大于对应的第二门限值，则判定所述分配请求未超出剩余配额。
  6. 根据权利要求4所述的高速缓存管理方法，其特征在于，所述根据超额配置模式处理所述目标操作请求，包括：
    若所述超额配置模式为警告模式，则继续根据所述目标操作请求中的键值计算目标哈希值，并生成对应的事件信息发送至所述软件高速缓存管理器；
    若所述超额配置模式为阻塞模式，则直接生成处理失败的处理结果。
  7. 根据权利要求6所述的高速缓存管理方法，其特征在于，在所述直接生成处理失败的处理结果之后，所述方法还包括：
    在所述目标操作请求为软件高速缓存用户发起的操作请求的情况下，上报响应信息给软件高速缓存管理器，其中，所述目标用户包括所述软件高速缓存用户；
    在所述目标操作请求为硬件高速缓存用户发起的操作请求的情况下，上报响应信息给硬件高速缓存用户，并复制事件信息上报给所述软件高速缓存管理器，其中，所述目标用户包括所述硬件高速缓存用户。
  8. 根据权利要求2所述的高速缓存管理方法，其特征在于，根据所述目标操作请求中的键值计算目标哈希值，利用所述目标哈希值在目标数据表中进行查表，包括：
    根据各目标操作请求中的键值计算对应的目标哈希值，并将目标操作请求及对应的目标哈希值存储至第一目标队列；
    从所述第一目标队列中获取未查表的目标操作请求的目标哈希值，根据获取的目标哈希值在目标数据表中进行查表；
    将已查表的目标操作请求及对应的目标哈希值从所述第一目标队列中删除，并添加至第二目标队列；
    若接收到目标操作请求已处理的通知信息，则将与所述通知信息对应的目标操作请求及对应的目标哈希值从所述第二目标队列中删除。
  9. 根据权利要求8所述的高速缓存管理方法，其特征在于，所述根据各目标操作请求中的键值计算对应的目标哈希值，包括：
    将所述目标操作请求中的键值依次送入三个哈希函数计算模块进行计算，得到所述目标哈希值，其中，所述目标哈希值包括row，sig和CAM val。
  10. 根据权利要求8所述的高速缓存管理方法，其特征在于，所述根据各目标操作请求中的键值计算对应的目标哈希值之后，还包括：
    判断所述目标哈希值与目标队列中操作请求的哈希值是否碰撞；所述目标队列包括所述第一目标队列及所述第二目标队列；
    若所述目标哈希值与所述目标队列中操作请求的哈希值未碰撞，则继续执行将目标操作请求及对应的目标哈希值存储至第一目标队列的步骤；
    若所述目标哈希值与所述目标队列中操作请求的哈希值碰撞，则暂缓将目标操作请求及对应的目标哈希值存储至第一目标队列，若检测到所述目标队列中不存在与所述目标哈希值碰撞的哈希值，则继续执行将目标操作请求及对应的目标哈希值存储至第一目标队列的步骤。
  11. 根据权利要求10所述的高速缓存管理方法，其特征在于，所述判断所述目标哈希值与目标队列中操作请求的哈希值是否碰撞，包括：
    在所述目标哈希值与所述目标队列中操作请求的哈希值相同的情况下，确定所述目标哈希值与所述目标队列中操作请求的哈希值发生碰撞；
    在所述目标哈希值与所述目标队列中操作请求的哈希值不同的情况下，确定所述目标哈希值与所述目标队列中操作请求的哈希值未发生碰撞。
  12. 根据权利要求1所述的高速缓存管理方法，其特征在于，所述目标操作请求为以下请求中的任意一者：分配请求、释放请求、检查请求、锁定请求、解锁请求、设置请求。
  13. 根据权利要求1至12中任意一项所述的高速缓存管理方法，其特征在于，所述接收目标用户发送的目标操作请求，包括：
    接收硬件高速缓存用户发送的目标操作请求，或者软件高速缓存用户通过所述软件高速缓存管理器发送的目标操作请求。
  14. 根据权利要求13所述的高速缓存管理方法，其特征在于，将所述目标操作请求的处理结果反馈至所述目标用户，并通过软件高速缓存管理器根据所述处理结果执行对应的高速缓存维护操作，包括：
    若所述目标操作请求为所述硬件高速缓存用户发送的请求，则将所述目标操作请求的响应信息发送至所述硬件高速缓存用户，并生成与所述响应信息对应的事件信息发送至所述软件高速缓存管理器，以便所述软件高速缓存管理器根据所述事件信息执行对应的高速缓存维护操作；
    若所述目标操作请求为所述软件高速缓存用户发送的请求，则将所述目标操作请求的响应信息发送至所述软件高速缓存用户，以便所述软件高速缓存管理器根据所述响应信息执行对应的高速缓存维护操作。
  15. 根据权利要求14所述的高速缓存管理方法，其特征在于，生成与所述响应信息对应的事件信息发送至所述软件高速缓存管理器，包括：
    将所述事件信息通过事件上报的方式异步通知所述软件高速缓存管理器，其中，所述事件信息包括高速缓存分配行为、使用行为和查询行为的信息。
  16. 一种高速缓存管理装置，其特征在于，所述高速缓存管理装置应用于存储***高速缓存管理器，所述高速缓存管理装置包括：
    接收模块，被设置为接收目标用户发送的目标操作请求；
    处理模块，被设置为通过流水线方式处理所述目标操作请求，以便利用所述目标操作请求对缓存行执行对应的处理操作；
    发送模块，被设置为将所述目标操作请求的处理结果反馈至所述目标用户，并通过软件高速缓存管理器根据所述处理结果执行对应的高速缓存维护操作。
  17. 根据权利要求16所述的高速缓存管理装置，其特征在于，所述处理模块包括：
    查表单元，被设置为根据所述目标操作请求中的键值计算目标哈希值，利用所述目标哈希值在目标数据表中进行查表；
    输出单元，被设置为在未查找到对应的目标地址时，输出对应的查询结果；查找到目标地址时，根据目标地址在对应的缓存条目表中进行检索，并将检索到的键值与所述目标操作请求的键值进行比较，输出对应的查询结果；
    第一处理单元，被设置为根据查询结果及所述目标操作请求执行对应的处理操作。
  18. 一种高速缓存管理***，其特征在于，包括：
    存储***高速缓存管理器，被设置为接收目标用户发送的目标操作请求，通过流水线方式处理所述目标操作请求，以便利用所述目标操作请求对缓存行执行对应的处理操作；将所述目标操作请求的处理结果反馈至所述目标用户；
    软件高速缓存管理器，被设置为根据所述处理结果执行对应的高速缓存维护操作。
  19. 一种电子设备，其特征在于，包括：
    存储器，被设置为存储计算机程序；
    处理器，被设置为执行所述计算机程序时实现如权利要求1至15任一项所述的高速缓存管理方法的步 骤。
  20. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至15任一项所述的高速缓存管理方法的步骤。
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Publication number Priority date Publication date Assignee Title
CN114924999B (zh) * 2022-07-21 2022-12-09 苏州浪潮智能科技有限公司 一种高速缓存管理方法、装置、***、设备及介质
CN115442443A (zh) * 2022-11-03 2022-12-06 之江实验室 一种数据处理方法、装置、存储介质及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080209127A1 (en) * 2007-02-23 2008-08-28 Daniel Alan Brokenshire System and method for efficient implementation of software-managed cache
CN105453056A (zh) * 2013-09-19 2016-03-30 英特尔公司 用于在多高速缓存环境中管理高速缓冲存储器的方法和装置
US20180285275A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Apparatus, computer program product, and method to perform cache operations in a solid state drive
US20200192805A1 (en) * 2018-12-18 2020-06-18 Western Digital Technologies, Inc. Adaptive Cache Commit Delay for Write Aggregation
CN113032293A (zh) * 2019-12-24 2021-06-25 北京忆芯科技有限公司 缓存管理器及控制部件
CN114924999A (zh) * 2022-07-21 2022-08-19 苏州浪潮智能科技有限公司 一种高速缓存管理方法、装置、***、设备及介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6263302B1 (en) * 1999-10-29 2001-07-17 Vast Systems Technology Corporation Hardware and software co-simulation including simulating the cache of a target processor
CN104536911B (zh) * 2014-12-31 2018-01-02 华为技术有限公司 一种多路组相联的高速缓冲存储器及其处理方法
US11194722B2 (en) * 2018-03-15 2021-12-07 Intel Corporation Apparatus and method for improved cache utilization and efficiency on a many core processor
US10678691B2 (en) * 2018-09-07 2020-06-09 Apple Inc. Coherence flows for dual-processing pipelines
CN110147254A (zh) * 2019-05-23 2019-08-20 苏州浪潮智能科技有限公司 一种数据缓存处理方法、装置、设备及可读存储介质
CN110688160B (zh) * 2019-09-04 2021-11-19 苏州浪潮智能科技有限公司 一种指令流水线处理方法、***、设备及计算机存储介质

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080209127A1 (en) * 2007-02-23 2008-08-28 Daniel Alan Brokenshire System and method for efficient implementation of software-managed cache
CN105453056A (zh) * 2013-09-19 2016-03-30 英特尔公司 用于在多高速缓存环境中管理高速缓冲存储器的方法和装置
US20180285275A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Apparatus, computer program product, and method to perform cache operations in a solid state drive
US20200192805A1 (en) * 2018-12-18 2020-06-18 Western Digital Technologies, Inc. Adaptive Cache Commit Delay for Write Aggregation
CN113032293A (zh) * 2019-12-24 2021-06-25 北京忆芯科技有限公司 缓存管理器及控制部件
CN114924999A (zh) * 2022-07-21 2022-08-19 苏州浪潮智能科技有限公司 一种高速缓存管理方法、装置、***、设备及介质

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