WO2024010694A1 - Vias including an unsymmetric tapered through-hole, devices including the vias, and methods for fabricating the vias - Google Patents

Vias including an unsymmetric tapered through-hole, devices including the vias, and methods for fabricating the vias Download PDF

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Publication number
WO2024010694A1
WO2024010694A1 PCT/US2023/025926 US2023025926W WO2024010694A1 WO 2024010694 A1 WO2024010694 A1 WO 2024010694A1 US 2023025926 W US2023025926 W US 2023025926W WO 2024010694 A1 WO2024010694 A1 WO 2024010694A1
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WO
WIPO (PCT)
Prior art keywords
hole
diameter
waist
vias
substrate
Prior art date
Application number
PCT/US2023/025926
Other languages
French (fr)
Inventor
Sean Matthew Garner
Dhananjay Joshi
Joo Sok Kim
Chukwudi Azubuike Okoro
Seong-Ho Seok
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Corning Incorporated
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Publication date
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Publication of WO2024010694A1 publication Critical patent/WO2024010694A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • VIAS INCLUDING AN UNS YMMETRIC TAPERED THROUGH-HOLE, DEVICES INCLUDING THE VIAS, AND METHODS FOR FABRICATING THE VIAS
  • the present disclosure relates generally to vias. More particularly, it relates to vias including unsymmetric tapered through-holes.
  • TGV through-glass vias
  • CTE coefficient of thermal expansion
  • the formation of TGVs presents thermo-mechanical challenges that arise due to the CTE mismatch between the glass matrix (e.g., about 0.6 ppm/°C for fused silica) and the metal fill (e.g., copper is about 16.7 ppm/°C).
  • This CTE difference leads to high stress buildup during thermal cycling that results in different failure modes, such as cracks in the substrate, via voiding, sidewall delamination, etc.
  • the via includes a substrate including a first surface and a second surface opposite to the first surface.
  • the substrate includes an unsymmetric tapered through-hole extending from the first surface to the second surface.
  • the through-hole includes a first opening at the first surface including a first diameter and a second opening at the second surface including a second diameter greater than the first diameter.
  • the through-hole includes a waist between the first surface and the second surface and closer to the first surface than the second surface. The waist includes a third diameter less than or equal to the first diameter.
  • the device includes a substrate including a first surface and a second surface opposite to the first surface and a plurality of unsymmetric tapered vias extending through the substrate from the first surface to the second surface.
  • Each via of the plurality of vias includes a through-hole including a first opening, a second opening, and a waist, and an electrically conductive material.
  • the through-hole extends through the substrate from the first surface to the second surface.
  • the first opening of the through-hole is at the first surface and includes a first diameter.
  • the second opening of the through-hole is at the second surface and includes a second diameter greater than the first diameter.
  • the waist of the through-hole is between the first surface and the second surface and closer to the first surface than the second surface.
  • the waist includes a third diameter less than or equal to the first diameter.
  • the electrically conductive material extends through the through-hole.
  • inventions of the present disclosure relate to a method for fabricating a via.
  • the method includes preferentially etching a substrate to form an unsymmetric tapered through-hole through the substrate from a first surface of the substrate to a second surface of the substrate opposite to the first surface such that a first opening of the through-hole at the first surface includes a first diameter, a second opening of the through-hole at the second surface includes a second diameter greater than the first diameter, and a waist of the through- hole is closer to the first surface than the second surface and includes a third diameter less than or equal to the first diameter.
  • the method includes applying an electrically conductive material in the through-hole.
  • the unsymmetric tapered vias disclosed herein may be used to form low residual stress backplane substrates for thin-film transistor (TFT) processing (e.g., for indium gallium zinc oxide (IGZO) processing) and/or for other high temperature processing conditions.
  • TFT thin-film transistor
  • IGZO indium gallium zinc oxide
  • the final residual stress in the substrates may be about 140 megapascal or lower.
  • the unsymmetric tapered vias enable a planar metal fill inside a small diameter via opening having a high electrical conductance and a low residual stress distribution around the via at the substrate surface.
  • a substrate including the unsymmetric tapered vias disclosed herein enable continuous barrier, redistribution, and/or passivation layers to be formed on the substrate surface and ease downstream TFT fabrication on the substrate.
  • FIG. 1 is a cross-sectional view of an exemplary through-hole for a via
  • FIGS. 2-5 are cross-sectional views of exemplary vias
  • FIG. 6 is atop view of an exemplary interposer including a plurality of vias
  • FIGS. 7A and 7B are simplified cross-sectional views of exemplary devices including a plurality of vias.
  • FIGS. 8A-8C are flow diagrams illustrating an exemplary method for fabricating a via. DETAILED DESCRIPTION
  • Ranges can be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
  • Metallized through-holes e.g., vias
  • microelectronic devices e.g., displays, photovoltaics, sensors, lighting
  • the metallized through-holes such as through-silicon vias (TSVs) and through-glass vias (TGVs) form the shortest electrical path between the two major surfaces of the substrates, thereby dramatically improving the electrical performance of microelectronic devices.
  • TSVs through-silicon vias
  • TSVs through-glass vias
  • TGVs enable electrical connections between a first surface and a second surface of a glass backplane substrate.
  • TGVs may be fabricated by forming a through-hole in the glass substrate and metalizing the inner surface of the through- hole such that a continuous electrical connection is formed between the first surface and the second surface.
  • the electrical connections enable driving of integrated circuits (ICs), microdriver ICs, electronic elements and conductor lines, and/or thin-fdm transistors (TFTs) from the backside of the microelectronic devices. These electrical connections may enable superior performance for tiled displays or borderless devices in certain embodiments.
  • Metallized TGVs face challenges including high stress created due to coefficient of thermal expansion (CTE) mismatch between the conducting material and the substrate during TFT fabrication and/or other high temperature processing.
  • CTE coefficient of thermal expansion
  • the magnitude of the stress depends upon the size and shape of the vias.
  • the through-hole or via geometry plays an important role in stress reduction.
  • disclosed herein are vias including geometries to mitigate the stress issue.
  • the disclosed vias include an unsymmetric tapered shape that has lower magnitude of stresses due to CTE mismatch at high temperatures during TFT fabrication or other electronic device fabrication, processing, or integration (e.g., IGZO processing with a maximum temperature of about 450 degrees Celsius, or processing temperatures greater than about 300 degrees Celsius, greater than about 500 degrees Celsius, or greater than about 600 degrees Celsius).
  • an unsymmetric tapered through-hole may be defined as a through-hole having at least a first portion and a second portion having different dimensions, where the first portion and the second portion meet at a waist of the through-hole.
  • the through-hole 100 includes a waist 118 between the first surface 104 and the second surface 106 and closer to the first surface 104 than the second surface 106.
  • the waist 118 includes a third diameter 120 less than or equal to the first diameter 112.
  • the sidewalls 101 a of the through-hole 100 extend from the first surface 104 to the waist 118 and may be tapered from the first surface 104 to the waist 118.
  • the distance between the first surface 104 and the waist 118 is indicated at 122.
  • the angle between the first surface 104 and the sidewalls 101a is indicated at 124.
  • the sidewalls 101b of the through-hole 100 extend from the second surface 106 to the waist 118 and are tapered from the second surface 106 to the waist 118.
  • the sidewalls 101a and the sidewalls 101b meet at the waist 118.
  • the first diameter 112 may be within a range between about 10 micrometers and about 20 micrometers
  • the second diameter 116 may be within a range between about 50 micrometers and about 160 micrometers
  • the third diameter 120 may be within a range between about 10 micrometers and about 20 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be within a range between about 10 micrometers and about 20 micrometers.
  • the angle 124 between the first surface 104 and sidewalls 101a may be within a range between about 90 degrees and about 95 degrees. In other embodiments, the angle 124 between the first surface 104 and sidewalls 101a may be within a range between about 90 degrees and about 91 degrees.
  • the first diameter 112 may be about 10 micrometers
  • the second diameter 116 may be about 125 micrometers
  • the third diameter 120 may be about 10 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
  • the first diameter 112 may be about 10 micrometers
  • the second diameter 116 may be about 50 micrometers
  • the third diameter 120 may be about 10 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
  • the first diameter 112 may be about 15.3 micrometers
  • the second diameter 116 may be about 50 micrometers
  • the third diameter 120 may be about 10 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
  • the first diameter 112 may be about 14.8 micrometers
  • the second diameter 116 may be about 50 micrometers
  • the third diameter 120 may be about 10 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
  • the first diameter 112 may be about 15.3 micrometers
  • the second diameter 116 may be about 125 micrometers
  • the third diameter 120 may be about 10 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
  • the first diameter 112 may be about 14.8 micrometers
  • the second diameter 116 may be about 125 micrometers
  • the third diameter 120 may be about 10 micrometers
  • the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
  • FIG. 2 is a cross-sectional view of an exemplary via 200.
  • Via 200 includes the through-hole 100 previously described and illustrated with reference to FIG. 1.
  • via 200 includes an electrically conductive material 210 extending through the through-hole 100.
  • the electrically conductive material 210 fills the through-hole 100 from the first surface 104 to the waist 118 on the sidewalls 101a and conformally metallizes sidewalls 101b of the through-hole 100 from the second surface 106 to the waist 118.
  • the electrically conductive material 210 may include copper or another suitable material.
  • the predetermined distance from the second surface may be greater than or equal to about 50 micrometers.
  • the adhesion layer 410 may include metallic titanium and/or titanium oxide and/or another suitable material.
  • the adhesion layer 410 contacts (e.g., directly contacts) the substrate 102 on sidewalls 101a and 101b of the through-hole 100.
  • the adhesion layer 410 may include a thickness (e.g., measured in a direction perpendicular to the sidewalls of the through-hole 100) within a range between about 0.02 micrometers and about 0.2 micrometers.
  • FIG. 5 is a cross-sectional view of an exemplary via 500.
  • Via 500 includes the through-hole 100, the electrically conductive material 210, and the compliant material 310 as previously described and illustrated with reference to FIGS. 1-3.
  • via 500 includes an adhesion layer 510 between sidewalls 101a and 101b of the through-hole 100 and the electrically conductive material 210.
  • the adhesion layer 510 may be applied to completely cover sidewalls lOla and 101b of the through-hole 100 from the first surface 104 to the second surface 106.
  • the adhesion layer 510 may include metallic titanium and/or titanium oxide and/or another suitable material.
  • the adhesion layer 510 contacts (e.g., directly contacts) the substrate 102 on sidewalls 101a and 101b of the through-hole 100.
  • the adhesion layer 510 may include a thickness (e.g., measured in a direction perpendicular to the sidewalls of the through-hole 100) within a range between about 0.02 micrometers and about 0.2 micrometers.
  • FIG. 6 is a top view of an exemplary interposer 600.
  • Interposer 600 includes a substrate 102 and a plurality of vias 610. Each of the plurality of vias 610 extends through the substrate 102 from the first surface 104 to the second surface 106 (not visible in FIG. 6). Each of the plurality of vias 610 may be a via 200 of FIG. 2, a via 300 of FIG. 3, a via 400 of FIG. 4, or a via 500 of FIG. 5. While the vias 610 of interposer 600 are arranged in rows and columns and nine vias are illustrated in FIG. 6, in other embodiments the vias may be arranged in any suitable symmetric or non-symmetric pattern and interposer 600 may include any suitable number of vias.
  • interposer 600 may include additional layers (not shown), such as a conductive layer on the first surface 104 and/or on the second surface 106 (not visible in FIG. 6) to electrically couple selected vias to each other and/or to other circuitry.
  • FIG. 7A is a simplified cross-sectional view of an exemplary device 700a.
  • Device 700a may be a display device or photovoltaic, sensor, or lighting.
  • Device 700a includes an interposer 600 as previously described and illustrated with reference to FIG. 6. While in this example, interposer 600 includes a plurality of vias 300 as previously described and illustrated with reference to FIG. 3, in other examples, interposer 600 of FIG. 7A may include a plurality of vias 200 of FIG.
  • Device 700a also includes a barrier layer 710, a passivation layer 712, an array of thin-fdm transistors (TFTs) 714, and a plurality of light sources 716.
  • interposer 600 may be a small die that is then integrated onto a larger device substrate, or interposer 600 may be the actual device substrate itself.
  • some of the vias 300 may be oriented in different directions so that the first opening of one via is on the same substrate surface as the second opening of a second via.
  • the plurality of vias 300 may have different geometries, metallization (or no metallization), and/or filling.
  • electronic elements e.g., semiconductor, conductor, dielectric structures
  • the barrier layer 710 is proximate the first surface 104, such as directly contacting the first surface 104.
  • the barrier layer 710 may include a metal, a metal nitrides, a carbide, a boride, or another suitable material.
  • the barrier layer 710 may have a thickness within a range between about 10 nanometers and about 1000 nanometers.
  • the passivation layer 712 is proximate the first surface 104, such as directly contacting the upper surface of the barrier layer 710.
  • the passivation layer 712 may include a nitride or another suitable material.
  • the passivation layer 712 may have a thickness within a range between about 10 nanometers and about 1000 nanometers.
  • a barrier layer may be proximate the second surface 106, such as directly on the second surface 106. This barrier layer may extend into each via 300 and contact the electrically conductive material 210, such that the barrier layer within each via is between the electrically conductive material 210 and the compliant material 310.
  • the array of TFTs 714 or other devices are proximate the first surface 104, such as directly contacting the upper surface of the passivation layer 712.
  • the array of TFTs 714 or other devices may be electrically coupled to the plurality of vias 300 through a plurality of electrical connections 718.
  • the plurality of light sources 716 are proximate the first surface 104, such as directly contacting the upper surface of the passivation layer 712.
  • the plurality of light sources 716 may be electrically coupled to the plurality of vias 300, such as through respective TFTs 714 and electrical connections 718.
  • Lights sources 716 may be light emitting diode (LED) light sources, such as mini-LED light sources or micro-LED light sources.
  • Each light source 716 may include multiple light emitting elements (e.g., red, green, blue elements) as shown in FIG. 7A or a single light emitting element.
  • FIG. 7B is a simplified cross-sectional view of another device 700b.
  • Device 700b is similar to device 700a including interposer 600, barrier layer 710, passivation layer 712, TFTs 714, and light sources 716.
  • the barrier layer 710 may form a redistribution layer electrically coupled to the plurality of vias 300.
  • the redistribution layer may have a thickness within a range between about 10 nanometers and about 10,000 nanometers.
  • the redistribution layer may electrically couple vias 300 to TFTs 714, which may be electrically coupled to light sources 716.
  • FIGS. 8A-8C are flow diagrams illustrating an exemplary method 800 for fabricating a via, such as via 200 of FIG. 2, via 300 of FIG. 3, via 400 of FIG. 4, or via 500 of FIG. 5.
  • method 800 may include preferentially etching a substrate (e.g., 102 of FIGS. 1-5) to form an unsymmetric tapered through-hole (e.g., 100 of FIGS. 1-5) through the substrate from a first surface (e.g., 104 of FIGS. 1-5) of the substrate to a second surface (e.g., 106 of FIGS. 1-5) of the substrate opposite to the first surface such that a first opening (e.g., 110 of FIGS.
  • etching processes may be wet etchant, vapor etchant, plasma etchant, or other. The etching parameters may be adjusted to form the unsymmetric tapered through-hole having the desired shape.
  • method 800 may include applying an electrically conductive material (e.g., 210 of FIGS. 2-5) in the through-hole.
  • the electrically conductive material may include copper or another suitable material.
  • applying the electrically conductive material in the through-hole may include metallizing to fill the through-hole from the first surface to the waist and conformally metallizing the through-hole from the second surface to the waist.
  • the electrically conductive material may be applied by an electroplating process, a sputtering process, and/or another suitable process. Applying the electrically conductive material may leave a layer of overburden on the first surface and the second surface. After applying the electrically conductive material, the electrically conductive material may be annealed. The overburden on the first surface and the second surface may be removed by a chemical mechanical planarization (CMP) process or another suitable process.
  • CMP chemical mechanical planarization
  • method 800 may further include applying an adhesion layer (e.g., 410 of FIG. 4 or 510 of FIG. 5) on sidewalls (e.g., 10 la and 101b of FIGS. 1-5) of the through-hole prior to applying the electrically conductive material.
  • the adhesion layer may include metallic titanium and/or titanium oxide and/or another suitable material.
  • the adhesion layer may be applied on sidewalls of the through-hole via sputtering or another suitable process.
  • method 800 may further include fdling the through-hole from the second surface to the waist with a compliant material (e.g., 310 of FIGS. 3-5).
  • the compliant material may include a dielectric material (e.g., polymer, sol-gel), aporous conductor, a composite, or another suitable material.

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Abstract

A via includes a substrate including a first surface and a second surface opposite to the first surface. The substrate includes an unsymmetric tapered through-hole extending from the first surface to the second surface. The through-hole includes a first opening at the first surface including a first diameter and a second opening at the second surface including a second diameter greater than the first diameter. The through-hole includes a waist between the first surface and the second surface and closer to the first surface than the second surface. The waist includes a third diameter less than or equal to the first diameter.

Description

Attorney Docket No.: SP22-164
VIAS INCLUDING AN UNS YMMETRIC TAPERED THROUGH-HOLE, DEVICES INCLUDING THE VIAS, AND METHODS FOR FABRICATING THE VIAS
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of priority under 35 U.S.C. §119 of U.S. Provisional Application Serial No. 63/367829 filed on July 7, 2022, the content of which is relied upon and incorporated herein by reference in its entirety.
BACKGROUND
Field
[0002] The present disclosure relates generally to vias. More particularly, it relates to vias including unsymmetric tapered through-holes.
Technical Background
[0003] The desire for miniaturization and improved electrical performance has resulted in the emergence of 3D and 2.5D chip stacking architectures, which use vertical electrical interconnects. These vertical interconnects may be fabricated by forming holes through substrates and forming a conductive path within each hole, resulting in short interconnects having a high electrical performance. Through-silicon via (TSV) has been the most prominent vertical interconnect. The challenges associated with 3D stacking of chips, however, has shifted attention to 2.5D chip stacking architectures, as 2.5D chip stacking architectures are less expensive and present fewer integration challenges. The 2.5D chip stacking architectures may be realized by the use of non-active substrates (having no integrated front end devices) with vertical interconnects, which are often referred to as interposers. Interposer substrates may be made of silicon or glass.
[0004] Glass interposers with through-glass vias (TGV) are attractive due to the many advantages of glass over silicon that includes lower cost, tunable coefficient of thermal expansion (CTE), and superior high frequency performance. The formation of TGVs, however, presents thermo-mechanical challenges that arise due to the CTE mismatch between the glass matrix (e.g., about 0.6 ppm/°C for fused silica) and the metal fill (e.g., copper is about 16.7 ppm/°C). This CTE difference leads to high stress buildup during thermal cycling that results in different failure modes, such as cracks in the substrate, via voiding, sidewall delamination, etc.
SUMMARY
[0005] Some embodiments of the present disclosure relate to a via. The via includes a substrate including a first surface and a second surface opposite to the first surface. The substrate includes an unsymmetric tapered through-hole extending from the first surface to the second surface. The through-hole includes a first opening at the first surface including a first diameter and a second opening at the second surface including a second diameter greater than the first diameter. The through-hole includes a waist between the first surface and the second surface and closer to the first surface than the second surface. The waist includes a third diameter less than or equal to the first diameter.
[0006] Yet other embodiments of the present disclosure relate to a device. The device includes a substrate including a first surface and a second surface opposite to the first surface and a plurality of unsymmetric tapered vias extending through the substrate from the first surface to the second surface. Each via of the plurality of vias includes a through-hole including a first opening, a second opening, and a waist, and an electrically conductive material. The through-hole extends through the substrate from the first surface to the second surface. The first opening of the through-hole is at the first surface and includes a first diameter. The second opening of the through-hole is at the second surface and includes a second diameter greater than the first diameter. The waist of the through-hole is between the first surface and the second surface and closer to the first surface than the second surface. The waist includes a third diameter less than or equal to the first diameter. The electrically conductive material extends through the through-hole.
[0007] Yet other embodiments of the present disclosure relate to a method for fabricating a via. The method includes preferentially etching a substrate to form an unsymmetric tapered through-hole through the substrate from a first surface of the substrate to a second surface of the substrate opposite to the first surface such that a first opening of the through-hole at the first surface includes a first diameter, a second opening of the through-hole at the second surface includes a second diameter greater than the first diameter, and a waist of the through- hole is closer to the first surface than the second surface and includes a third diameter less than or equal to the first diameter. The method includes applying an electrically conductive material in the through-hole.
[0008] The unsymmetric tapered vias disclosed herein may be used to form low residual stress backplane substrates for thin-film transistor (TFT) processing (e.g., for indium gallium zinc oxide (IGZO) processing) and/or for other high temperature processing conditions. The final residual stress in the substrates may be about 140 megapascal or lower. The unsymmetric tapered vias enable a planar metal fill inside a small diameter via opening having a high electrical conductance and a low residual stress distribution around the via at the substrate surface. Thus, a substrate including the unsymmetric tapered vias disclosed herein enable continuous barrier, redistribution, and/or passivation layers to be formed on the substrate surface and ease downstream TFT fabrication on the substrate.
[0009] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.
[0010] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description explain principles and operation of the various embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a cross-sectional view of an exemplary through-hole for a via;
[0012] FIGS. 2-5 are cross-sectional views of exemplary vias;
[0013] FIG. 6 is atop view of an exemplary interposer including a plurality of vias;
[0014] FIGS. 7A and 7B are simplified cross-sectional views of exemplary devices including a plurality of vias; and
[0015] FIGS. 8A-8C are flow diagrams illustrating an exemplary method for fabricating a via. DETAILED DESCRIPTION
[0016] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
[0017] Ranges can be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
[0018] Directional terms as used herein - for example up, down, right, left, front, back, top, bottom, vertical, horizontal - are made only with reference to the figures as drawn and are not intended to imply absolute orientation.
[0019] Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order, nor that with any apparatus, specific orientations be required. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or that any apparatus claim does not actually recite an order or orientation to individual components, or it is not otherwise specifically stated in the claims or description that the steps are to be limited to a specific order, or that a specific order or orientation to components of an apparatus is not recited, it is in no way intended that an order or orientation be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps, operational flow, order of components, or orientation of components; plain meaning derived from grammatical organization or punctuation, and; the number or type of embodiments described in the specification.
[0020] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a” component includes aspects having two or more such components, unless the context clearly indicates otherwise. [0021] Metallized through-holes (e.g., vias), which run through the thickness of substrates, may be used to fabricate microelectronic devices (e.g., displays, photovoltaics, sensors, lighting) having improved electrical performance. The metallized through-holes, such as through-silicon vias (TSVs) and through-glass vias (TGVs) form the shortest electrical path between the two major surfaces of the substrates, thereby dramatically improving the electrical performance of microelectronic devices. TGVs enable electrical connections between a first surface and a second surface of a glass backplane substrate. TGVs may be fabricated by forming a through-hole in the glass substrate and metalizing the inner surface of the through- hole such that a continuous electrical connection is formed between the first surface and the second surface. The electrical connections enable driving of integrated circuits (ICs), microdriver ICs, electronic elements and conductor lines, and/or thin-fdm transistors (TFTs) from the backside of the microelectronic devices. These electrical connections may enable superior performance for tiled displays or borderless devices in certain embodiments.
[0022] Metallized TGVs face challenges including high stress created due to coefficient of thermal expansion (CTE) mismatch between the conducting material and the substrate during TFT fabrication and/or other high temperature processing. The magnitude of the stress depends upon the size and shape of the vias. Thus, the through-hole or via geometry plays an important role in stress reduction. Accordingly, disclosed herein are vias including geometries to mitigate the stress issue. The disclosed vias include an unsymmetric tapered shape that has lower magnitude of stresses due to CTE mismatch at high temperatures during TFT fabrication or other electronic device fabrication, processing, or integration (e.g., IGZO processing with a maximum temperature of about 450 degrees Celsius, or processing temperatures greater than about 300 degrees Celsius, greater than about 500 degrees Celsius, or greater than about 600 degrees Celsius). As used herein, an unsymmetric tapered through-hole may be defined as a through-hole having at least a first portion and a second portion having different dimensions, where the first portion and the second portion meet at a waist of the through-hole.
[0023] Referring now to FIG. 1, a cross-sectional view of an exemplary through-hole 100 for a via is depicted. The through-hole 100 is formed in a substrate 102 and includes sidewalls 101a and 101b. The substrate 102 includes a first surface 104 and a second surface 106 opposite to the first surface 104. The substrate 102 includes unsymmetric tapered through-hole 100 extending from the first surface 104 to the second surface 106. In certain exemplary embodiments, the substrate 102 may be a silicon substrate. In other embodiments, the substrate 102 may be a non-silicon substrate, such as a glass substrate, a ceramic substrate, or a glassceramic substrate. In yet other embodiments, the substrate 102 may include Alumina, AIN, Quartz (Sapphire), InGaN, GaAs, InGaAs, GaP, GaSb, InP, InAs, InSb, GaN on Sapphire, SOI, SIMOX, Ge, crystal aluminum oxide (Garnet), or another suitable material or combination thereof. The substrate 102 may have a thickness between the first surface 104 and the second surface 106 within a range, for example, from about 0. 1 millimeters to about 2 millimeters. [0024] The through-hole 100 includes a first opening 110 at the first surface 104 including a first diameter 112. The through-hole 100 includes a second opening 114 at the second surface 106 including a second diameter 116 greater than the first diameter 112. The through-hole 100 includes a waist 118 between the first surface 104 and the second surface 106 and closer to the first surface 104 than the second surface 106. The waist 118 includes a third diameter 120 less than or equal to the first diameter 112. The sidewalls 101 a of the through-hole 100 extend from the first surface 104 to the waist 118 and may be tapered from the first surface 104 to the waist 118. The distance between the first surface 104 and the waist 118 is indicated at 122. The angle between the first surface 104 and the sidewalls 101a is indicated at 124. The sidewalls 101b of the through-hole 100 extend from the second surface 106 to the waist 118 and are tapered from the second surface 106 to the waist 118. The sidewalls 101a and the sidewalls 101b meet at the waist 118.
[0025] In some embodiments, the first diameter 112 may be within a range between about 10 micrometers and about 20 micrometers, the second diameter 116 may be within a range between about 50 micrometers and about 160 micrometers, the third diameter 120 may be within a range between about 10 micrometers and about 20 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be within a range between about 10 micrometers and about 20 micrometers. In certain exemplary embodiments, the angle 124 between the first surface 104 and sidewalls 101a may be within a range between about 90 degrees and about 95 degrees. In other embodiments, the angle 124 between the first surface 104 and sidewalls 101a may be within a range between about 90 degrees and about 91 degrees. [0026] In other embodiments, the first diameter 112 may be about 10 micrometers, the second diameter 116 may be about 125 micrometers, the third diameter 120 may be about 10 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers. In yet other embodiments, the first diameter 112 may be about 10 micrometers, the second diameter 116 may be about 50 micrometers, the third diameter 120 may be about 10 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers. In yet other embodiments, the first diameter 112 may be about 15.3 micrometers, the second diameter 116 may be about 50 micrometers, the third diameter 120 may be about 10 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers. In yet other embodiments, the first diameter 112 may be about 14.8 micrometers, the second diameter 116 may be about 50 micrometers, the third diameter 120 may be about 10 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers. In yet other embodiments, the first diameter 112 may be about 15.3 micrometers, the second diameter 116 may be about 125 micrometers, the third diameter 120 may be about 10 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers. In yet other embodiments, the first diameter 112 may be about 14.8 micrometers, the second diameter 116 may be about 125 micrometers, the third diameter 120 may be about 10 micrometers, and the distance 122 between the first surface 104 and the waist 118 may be about 10 micrometers.
[0027] FIG. 2 is a cross-sectional view of an exemplary via 200. Via 200 includes the through-hole 100 previously described and illustrated with reference to FIG. 1. In addition, via 200 includes an electrically conductive material 210 extending through the through-hole 100. The electrically conductive material 210 fills the through-hole 100 from the first surface 104 to the waist 118 on the sidewalls 101a and conformally metallizes sidewalls 101b of the through-hole 100 from the second surface 106 to the waist 118. The electrically conductive material 210 may include copper or another suitable material. In certain exemplary embodiments, the electrically conductive material 210 may include athickness (e.g., measured in a direction perpendicular to the sidewalls 101b of the through-hole 100) of less than about 10 micrometers or less than about 5 micrometers.
[0028] FIG. 3 is a cross-sectional view of an exemplary via 300. Via 300 includes the through-hole 100 and the electrically conductive material 210 as previously described and illustrated with reference to FIGS. 1 and 2. In addition, via 300 includes a compliant material 310 filling the through-hole 100 from the second surface 106 to the waist 118. The compliant material 310 may include a dielectric material (e.g., polymer, sol-gel), a porous conductor, a composite, or another suitable material including material properties (e.g., CTE and E- Modulus) that minimizes increased stresses in the substrate 102.
[0029] FIG. 4 is a cross-sectional view of an exemplary via 400. Via 400 includes the through-hole 100, the electrically conductive material 210, and the compliant material 310 as previously described and illustrated with reference to FIGS. 1-3. In addition, via 400 includes an adhesion layer 410 between sidewalls 101a and 101b of the through-hole 100 and the electrically conductive material 210. The adhesion layer 410 may be applied to completely cover sidewalls 101a of the through-hole 100 from the first surface 104 to the waist 118 and partially cover sidewalls 101b from the second surface 106 toward the waist 118 to a predetermined distance from the second surface 106. In certain exemplary embodiments, the predetermined distance from the second surface may be greater than or equal to about 50 micrometers. The adhesion layer 410 may include metallic titanium and/or titanium oxide and/or another suitable material. The adhesion layer 410 contacts (e.g., directly contacts) the substrate 102 on sidewalls 101a and 101b of the through-hole 100. In certain exemplary embodiments, the adhesion layer 410 may include a thickness (e.g., measured in a direction perpendicular to the sidewalls of the through-hole 100) within a range between about 0.02 micrometers and about 0.2 micrometers.
[0030] FIG. 5 is a cross-sectional view of an exemplary via 500. Via 500 includes the through-hole 100, the electrically conductive material 210, and the compliant material 310 as previously described and illustrated with reference to FIGS. 1-3. In addition, via 500 includes an adhesion layer 510 between sidewalls 101a and 101b of the through-hole 100 and the electrically conductive material 210. The adhesion layer 510 may be applied to completely cover sidewalls lOla and 101b of the through-hole 100 from the first surface 104 to the second surface 106. The adhesion layer 510 may include metallic titanium and/or titanium oxide and/or another suitable material. The adhesion layer 510 contacts (e.g., directly contacts) the substrate 102 on sidewalls 101a and 101b of the through-hole 100. In certain exemplary embodiments, the adhesion layer 510 may include a thickness (e.g., measured in a direction perpendicular to the sidewalls of the through-hole 100) within a range between about 0.02 micrometers and about 0.2 micrometers.
[0031] FIG. 6 is a top view of an exemplary interposer 600. Interposer 600 includes a substrate 102 and a plurality of vias 610. Each of the plurality of vias 610 extends through the substrate 102 from the first surface 104 to the second surface 106 (not visible in FIG. 6). Each of the plurality of vias 610 may be a via 200 of FIG. 2, a via 300 of FIG. 3, a via 400 of FIG. 4, or a via 500 of FIG. 5. While the vias 610 of interposer 600 are arranged in rows and columns and nine vias are illustrated in FIG. 6, in other embodiments the vias may be arranged in any suitable symmetric or non-symmetric pattern and interposer 600 may include any suitable number of vias. In certain exemplary embodiments, interposer 600 may include additional layers (not shown), such as a conductive layer on the first surface 104 and/or on the second surface 106 (not visible in FIG. 6) to electrically couple selected vias to each other and/or to other circuitry. [0032] FIG. 7A is a simplified cross-sectional view of an exemplary device 700a. Device 700a may be a display device or photovoltaic, sensor, or lighting. Device 700a includes an interposer 600 as previously described and illustrated with reference to FIG. 6. While in this example, interposer 600 includes a plurality of vias 300 as previously described and illustrated with reference to FIG. 3, in other examples, interposer 600 of FIG. 7A may include a plurality of vias 200 of FIG. 2, a plurality of vias 400 of FIG. 4, or a plurality of vias 500 of FIG. 5. Device 700a also includes a barrier layer 710, a passivation layer 712, an array of thin-fdm transistors (TFTs) 714, and a plurality of light sources 716. In other examples, interposer 600 may be a small die that is then integrated onto a larger device substrate, or interposer 600 may be the actual device substrate itself. In other examples, some of the vias 300 may be oriented in different directions so that the first opening of one via is on the same substrate surface as the second opening of a second via. In other examples, the plurality of vias 300 may have different geometries, metallization (or no metallization), and/or filling. In other examples, electronic elements (e.g., semiconductor, conductor, dielectric structures) may exist on either the first surface 104, the second surface 106, or both surfaces 104 and 106.
[0033] The barrier layer 710 is proximate the first surface 104, such as directly contacting the first surface 104. The barrier layer 710 may include a metal, a metal nitrides, a carbide, a boride, or another suitable material. The barrier layer 710 may have a thickness within a range between about 10 nanometers and about 1000 nanometers. The passivation layer 712 is proximate the first surface 104, such as directly contacting the upper surface of the barrier layer 710. The passivation layer 712 may include a nitride or another suitable material. The passivation layer 712 may have a thickness within a range between about 10 nanometers and about 1000 nanometers. In other examples (not shown), a barrier layer may be proximate the second surface 106, such as directly on the second surface 106. This barrier layer may extend into each via 300 and contact the electrically conductive material 210, such that the barrier layer within each via is between the electrically conductive material 210 and the compliant material 310.
[0034] The array of TFTs 714 or other devices are proximate the first surface 104, such as directly contacting the upper surface of the passivation layer 712. The array of TFTs 714 or other devices may be electrically coupled to the plurality of vias 300 through a plurality of electrical connections 718. The plurality of light sources 716 are proximate the first surface 104, such as directly contacting the upper surface of the passivation layer 712. The plurality of light sources 716 may be electrically coupled to the plurality of vias 300, such as through respective TFTs 714 and electrical connections 718. Lights sources 716 may be light emitting diode (LED) light sources, such as mini-LED light sources or micro-LED light sources. Each light source 716 may include multiple light emitting elements (e.g., red, green, blue elements) as shown in FIG. 7A or a single light emitting element.
[0035] FIG. 7B is a simplified cross-sectional view of another device 700b. Device 700b is similar to device 700a including interposer 600, barrier layer 710, passivation layer 712, TFTs 714, and light sources 716. In this embodiment, however, the barrier layer 710 may form a redistribution layer electrically coupled to the plurality of vias 300. The redistribution layer may have a thickness within a range between about 10 nanometers and about 10,000 nanometers. The redistribution layer may electrically couple vias 300 to TFTs 714, which may be electrically coupled to light sources 716.
[0036] FIGS. 8A-8C are flow diagrams illustrating an exemplary method 800 for fabricating a via, such as via 200 of FIG. 2, via 300 of FIG. 3, via 400 of FIG. 4, or via 500 of FIG. 5. As illustrated in FIG. 8A at 802, method 800 may include preferentially etching a substrate (e.g., 102 of FIGS. 1-5) to form an unsymmetric tapered through-hole (e.g., 100 of FIGS. 1-5) through the substrate from a first surface (e.g., 104 of FIGS. 1-5) of the substrate to a second surface (e.g., 106 of FIGS. 1-5) of the substrate opposite to the first surface such that a first opening (e.g., 110 of FIGS. 1-5) of the through-hole at the first surface comprises a first diameter (e.g., 112 of FIGS. 1-5), a second opening (e.g., 114 of FIGS. 1-5) of the through- hole at the second surface comprises a second diameter (e.g., 116 of FIGS. 1-5) greater than the first diameter, and a waist (e.g., 118 of FIGS. 1-5) of the through-hole is closer to the first surface than the second surface and comprises a third diameter (e.g., 120 of FIGS. 1-5) less than or equal to the first diameter. Depending on the substrate material, utilized etching processes may be wet etchant, vapor etchant, plasma etchant, or other. The etching parameters may be adjusted to form the unsymmetric tapered through-hole having the desired shape.
[0037] At 804, method 800 may include applying an electrically conductive material (e.g., 210 of FIGS. 2-5) in the through-hole. The electrically conductive material may include copper or another suitable material. In certain exemplary embodiments, applying the electrically conductive material in the through-hole may include metallizing to fill the through-hole from the first surface to the waist and conformally metallizing the through-hole from the second surface to the waist. In certain exemplary embodiments, the electrically conductive material may be applied by an electroplating process, a sputtering process, and/or another suitable process. Applying the electrically conductive material may leave a layer of overburden on the first surface and the second surface. After applying the electrically conductive material, the electrically conductive material may be annealed. The overburden on the first surface and the second surface may be removed by a chemical mechanical planarization (CMP) process or another suitable process.
[0038] As illustrated in FIG. 8B at 806, method 800 may further include applying an adhesion layer (e.g., 410 of FIG. 4 or 510 of FIG. 5) on sidewalls (e.g., 10 la and 101b of FIGS. 1-5) of the through-hole prior to applying the electrically conductive material. The adhesion layer may include metallic titanium and/or titanium oxide and/or another suitable material. The adhesion layer may be applied on sidewalls of the through-hole via sputtering or another suitable process. As illustrated in FIG. 8C at 808, method 800 may further include fdling the through-hole from the second surface to the waist with a compliant material (e.g., 310 of FIGS. 3-5). The compliant material may include a dielectric material (e.g., polymer, sol-gel), aporous conductor, a composite, or another suitable material.
[0039] It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

What is claimed is:
1 . A via comprising : a substrate comprising a first surface and a second surface opposite to the first surface, the substrate comprising an unsymmetric tapered through-hole extending from the first surface to the second surface, wherein the through-hole comprises: a first opening at the first surface comprising a first diameter; a second opening at the second surface comprising a second diameter greater than the first diameter; and a waist between the first surface and the second surface and closer to the first surface than the second surface, the waist comprising a third diameter less than or equal to the first diameter.
2. The via of claim 1, further comprising: an electrically conductive material extending through the through-hole.
3. The via of claim 2, wherein the electrically conductive material fills the through-hole from the first surface to the waist and conformally metallizes sidewalls of the through-hole from the second surface to the waist.
4. The via of claim 3, further comprising: a compliant material filling the through-hole from the second surface to the waist.
5. The via of claim 2, further comprising: an adhesion layer between sidewalls of the through-hole and the electrically conductive material.
6. The via of claim 2, wherein the electrically conductive material comprises copper.
7. The via of claim 1, wherein the substrate comprises a glass, a glass-ceramic, or a ceramic.
8. The via of claim 1, wherein the first diameter is within a range between about 10 micrometers and about 20 micrometers, the second diameter is within a range between about 50 micrometers and about 160 micrometers, the third diameter is within a range between about 10 micrometers and about 20 micrometers, and a distance between the first surface and the waist is within a range between about 10 micrometers and about 20 micrometers.
9. A device comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a plurality of unsymmetric tapered vias extending through the substrate from the first surface to the second surface, wherein each via of the plurality of vias comprises: a through-hole extending through the substrate from the first surface to the second surface; a first opening of the through-hole at the first surface comprising a first diameter; a second opening of the through-hole at the second surface comprising a second diameter greater than the first diameter; a waist of the through-hole between the first surface and the second surface and closer to the first surface than the second surface, the waist comprising a third diameter less than or equal to the first diameter; and an electrically conductive material extending through the through-hole.
10. The device of claim 9, wherein the electrically conductive material fills each through- hole from the first surface to the waist and conformally metallizes sidewalls of each through- hole from the second surface to the waist.
11. The device of claim 9, further comprising: a redistribution layer proximate the first surface and electrically coupled to the plurality of vias.
12. The device of claim 9, further comprising: an array of thin-film transistors proximate the first surface and electrically coupled to the plurality of vias.
13. The device of claim 9, further comprising: a plurality of light sources proximate the first surface and electrically coupled to the plurality of vias.
14. The device of claim 9, further comprising: a barrier layer proximate the first surface.
15. The device of claim 9, further comprising: a passivation layer proximate the first surface.
16. The device of claim 9, wherein the device comprises a display device.
17. A method for fabricating a via, the method comprising: preferentially etching a substrate to form an unsymmetric tapered through-hole through the substrate from a first surface of the substrate to a second surface of the substrate opposite to the first surface such that a first opening of the through-hole at the first surface comprises a first diameter, a second opening of the through-hole at the second surface comprises a second diameter greater than the first diameter, and a waist of the through-hole is closer to the first surface than the second surface and comprises a third diameter less than or equal to the first diameter; and applying an electrically conductive material in the through-hole.
18. The method of claim 17, wherein applying the electrically conductive material in the through-hole comprises metallizing to fill the through-hole from the first surface to the waist and conformally metallizing the through-hole from the second surface to the waist.
19. The method of claim 17, further comprising: applying an adhesion layer on sidewalls of the through-hole prior to applying the electrically conductive material.
20. The method of claim 17, further comprising: filling the through-hole from the second surface to the waist with a compliant material.
PCT/US2023/025926 2022-07-07 2023-06-22 Vias including an unsymmetric tapered through-hole, devices including the vias, and methods for fabricating the vias WO2024010694A1 (en)

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US20180342451A1 (en) * 2017-05-25 2018-11-29 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US20200152564A1 (en) * 2013-11-21 2020-05-14 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate
US20200227277A1 (en) * 2019-01-10 2020-07-16 Corning Incorporated Interposer with manganese oxide adhesion layer
US20210111119A1 (en) * 2017-11-14 2021-04-15 Taiwan Semiconductor Manufacturing Co., Ltd. Via Structure and Methods Thereof
US20210359185A1 (en) * 2018-10-19 2021-11-18 Corning Incorporated Device including vias and method and material for fabricating vias

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US20200152564A1 (en) * 2013-11-21 2020-05-14 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate
US20180342451A1 (en) * 2017-05-25 2018-11-29 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US20210111119A1 (en) * 2017-11-14 2021-04-15 Taiwan Semiconductor Manufacturing Co., Ltd. Via Structure and Methods Thereof
US20210359185A1 (en) * 2018-10-19 2021-11-18 Corning Incorporated Device including vias and method and material for fabricating vias
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