WO2024000230A1 - 电感及其制备方法、滤波器、电子设备 - Google Patents
电感及其制备方法、滤波器、电子设备 Download PDFInfo
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- H—ELECTRICITY
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- H01F17/00—Fixed inductances of the signal type
- H01F17/04—Fixed inductances of the signal type with magnetic core
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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Definitions
- the present disclosure belongs to the technical field of electronic components, and specifically relates to an inductor and a preparation method thereof, filters, and electronic equipment.
- the rapid development of microelectronics process technology has caused the size of various electronic devices to decrease rapidly.
- new technologies continue to emerge, such as IPD technology, MEMS technology, nanotechnology, etc.
- the improvement of technology has once again promoted the progress of device design.
- the design size of electronic structures is getting smaller and smaller, and chip size, wiring interconnection, and packaging structure are all constantly developing. Therefore, various types of equipment in industry and daily life are pursuing miniaturization development, such as common mobile terminals, notebooks and other equipment. Therefore, the miniaturization of devices is an inevitable trend.
- the size of devices has developed from the macroscale of meters and centimeters to the microscale of micrometers and nanometers.
- a common inductor is an inductor composed of multiple turns of wire surrounding a ring magnet.
- the inductor performance is greatly improved through the function of the magnetic core.
- smaller-sized planar spiral inductors gradually become a common type, and the coil size is reduced to the order of millimeters and microns.
- the inductor coil will occupy a large area and cannot carry a large amount of space. It has a magnetic core structure; at the same time, when used in combination with other devices, it will also cause a large trace distance and serious mutual inductance between traces.
- the present invention aims to solve at least one of the technical problems existing in the prior art and provide an inductor and a preparation method thereof, a filter, and an electronic device.
- An embodiment of the present disclosure provides an inductor, which includes:
- the first dielectric substrate includes a first surface and a second surface oppositely arranged along the thickness direction thereof, the first dielectric substrate has a first connection via hole penetrating along the thickness direction, and a first connection via hole penetrating the first dielectric substrate. at least part of the first groove portion;
- a first substructure arranged on the first surface
- a first connection electrode is arranged in the first connection via hole, and sequentially connects the first substructure and the second substructure to form the coil structure of the inductor;
- a magnetic core is disposed in the first groove portion, is insulated from the first substructure and the second substructure, and is located in the coil structure.
- the first groove part is a blind groove
- the magnetic core fills the first groove part
- a first interlayer insulating layer is provided on the first surface
- the first interlayer insulating layer has a
- the first connection via hole is provided with a second connection via hole
- the first substructure is electrically connected to the first connection electrode through the second connection via hole.
- the first groove part is a blind groove, and there is a certain distance between the surface of the magnetic core facing away from the second substructure and the first surface; a groove covering the first groove part is provided in the first groove part.
- a surface of the first interlayer insulating layer facing away from the magnetic core is flush with the first surface.
- the first groove part is a through groove, and the magnetic core fills the first groove part; a first interlayer insulating layer is provided on the first surface, and a third interlayer insulating layer is provided on the second surface.
- the third connection via hole; the first substructure is electrically connected to the first connection electrode through the second connection via hole; the second substructure is electrically connected to the first connection electrode through the third connection via hole
- the connecting electrodes are electrically connected.
- the first dielectric substrate includes a first sub-dielectric substrate and a second sub-dielectric substrate arranged in a stack; the surface of the first sub-dielectric substrate facing away from the second sub-dielectric substrate serves as the first surface, so A surface of the second sub-dielectric substrate facing away from the first sub-dielectric substrate is used as the second surface;
- the first connection via hole includes a first sub-connection via hole formed on the first sub-dielectric substrate, and a second sub-connection via hole formed on the second sub-dielectric substrate;
- the first groove The portion includes a first sub-groove portion formed on the first sub-dielectric substrate, and a second sub-groove portion formed on the second sub-dielectric substrate; the first sub-groove portion and the second sub-groove Both parts are blind slots, and the opening of the first sub-slot part and the opening of the second sub-slot part are opposite and connected;
- the magnetic core includes a first part and a second part, and the first part fills the first part. sub-groove part, the second part fills the second groove part, and the first part and the second part are in contact.
- the first dielectric substrate includes a first sub-dielectric substrate and a second sub-dielectric substrate arranged in a stack; the surface of the first sub-dielectric substrate facing away from the second sub-dielectric substrate serves as the first surface, so A surface of the second sub-dielectric substrate facing away from the first sub-dielectric substrate is used as the second surface;
- the first connection via hole includes a first sub-connection via hole formed on the first sub-dielectric substrate, and a second sub-connection via hole formed on the second sub-dielectric substrate;
- the first groove The portion includes a first sub-groove portion formed on the first sub-dielectric substrate, and a second sub-groove portion formed on the second sub-dielectric substrate;
- the first sub-groove portion and the second sub-groove Both parts are blind slots, and the opening of the first sub-slot part and the opening of the second sub-slot part are opposite and connected;
- the magnetic core includes a first part and a second part, and the first part is arranged on the In a sub-groove part, the second part is disposed in the second groove part, and a third interlayer insulating layer is disposed between the first part and the second part.
- the first dielectric substrate includes a first sub-dielectric substrate and a second sub-dielectric substrate arranged in a stack;
- the first connection via hole includes a first sub-connection via hole formed on the first sub-dielectric substrate.
- the first groove portion includes a first sub-groove portion formed on the first sub-dielectric substrate, and a first sub-trough portion formed on the first sub-dielectric substrate.
- the magnetic core includes a first part and a second part; the first part fills the first sub-slot part, the second part fills the second slot part, and the first part and the second part are in contact;
- the surface of the first sub-dielectric substrate facing away from the second sub-dielectric substrate is used as the first surface, and the surface of the second sub-dielectric substrate facing away from the first sub-dielectric substrate is used as the second surface;
- a first interlayer insulating layer is provided on the first surface, and a second interlayer insulating layer is provided on the second surface; the first interlayer insulating layer has a structure corresponding to the first connection via hole.
- a second connection via hole is provided, and the second interlayer insulating layer has a third connection via hole corresponding to the first connection via hole; the first substructure is connected to the first connection via hole through the second connection via hole.
- the first connection electrode is electrically connected; the second substructure is electrically connected to the first connection electrode through the third connection via hole.
- a first protective layer is provided on a side of the first substructure facing away from the first dielectric substrate.
- a first protective layer is provided on a side of the second substructure facing away from the first dielectric substrate.
- the first groove part is a blind groove, and the opening of the first groove part faces away from the first substructure;
- the inductor also includes a second dielectric substrate; the second substructure is arranged on the first substructure.
- a fourth interlayer insulating layer is provided on a side of the second substructure away from the second dielectric substrate, and a layer connected to the first interlayer is provided in the fourth interlayer insulating layer.
- the connection via hole is corresponding to a fourth connection via hole, and the second substructure is electrically connected to the first connection electrode through the fourth connection via hole.
- the first groove part is a blind groove, and the opening of the first groove part faces away from the first substructure;
- the inductor also includes a second dielectric substrate; the second substructure is arranged on the first substructure.
- a fourth interlayer insulating layer is provided on a side of the second substructure away from the second dielectric substrate, and a layer connected to the first interlayer is provided in the fourth interlayer insulating layer.
- a fourth connection via hole is provided corresponding to the connection via hole, and the second substructure is electrically connected to the first connection electrode through the fourth connection via hole;
- a fifth insulating layer is also provided in the first groove portion and is located on the side of the magnetic core facing away from the first substructure; the surface of the fifth insulating layer facing away from the magnetic core is flush with the second surface. .
- the first groove part is a through groove, and the magnetic core fills the first groove part; a first interlayer insulating layer is provided on the first surface; the first interlayer insulating layer has a A second connection via hole is provided corresponding to the first connection via hole; the first substructure is electrically connected to the first connection electrode through the second connection via hole;
- the inductor further includes a second dielectric substrate; the second substructure is provided on the second dielectric substrate, and a fourth interlayer is provided on a side of the second substructure away from the second dielectric substrate. Insulation layer, and a fourth connection via hole corresponding to the first connection via hole is provided in the fourth interlayer insulating layer, and the second substructure is connected to the second substructure through the fourth connection via hole.
- the first connection electrode is electrically connected.
- a transfer electrode is provided in the fourth connection via hole, and the second substructure is electrically connected to the first connection electrode through the transfer electrode.
- a first protective layer is provided on a side of the first substructure facing away from the first dielectric substrate.
- An embodiment of the present disclosure provides a method for manufacturing an inductor, which includes:
- a first dielectric substrate is provided, the first dielectric substrate includes a first surface and a second surface arranged oppositely along its thickness direction, the first dielectric substrate has a first connection via hole penetrating along its thickness direction, and a first groove portion penetrating at least part of the first dielectric substrate;
- a first substructure is formed on the first surface, the second substructure is formed on the second surface, a first connection electrode is formed in the first connection via hole, and a first connection electrode is formed in the first groove portion.
- the two substructures are insulated and located within the coil structure.
- the first groove part is a blind groove, and the opening of the first groove part faces the first substructure; before the step of forming the first substructure on the first surface, it also includes:
- the first interlayer insulating layer is formed on the first surface to insulate the magnetic core and the first substructure.
- the first groove portion is a through groove; before the step of forming the first substructure on the first surface, the method further includes:
- the method further includes:
- the second interlayer insulating layer is formed on the second surface to insulate the magnetic core and the second substructure.
- the first dielectric substrate includes a first sub-dielectric substrate and a second sub-dielectric substrate arranged in a stack;
- the first connection via hole includes a first sub-connection via hole formed on the first sub-dielectric substrate.
- the first groove portion includes a first sub-groove portion formed on the first sub-dielectric substrate, and a first sub-trough portion formed on the first sub-dielectric substrate.
- the second sub-groove part on the second sub-media substrate; the first sub-groove part and the second sub-groove part are both blind grooves, and the first sub-groove part and the second sub-groove part are opposite and connected ;
- the surface of the first sub-dielectric substrate facing away from the second sub-dielectric substrate is used as the first surface, and the surface of the second sub-dielectric substrate facing away from the first sub-dielectric substrate is used as the second surface ;
- Forming the magnetic core includes:
- the preparation method also includes:
- a third insulating layer is formed between the first part and the second part.
- the first dielectric substrate includes a first sub-dielectric substrate and a second sub-dielectric substrate arranged in a stack;
- the first connection via hole includes a first sub-connection via hole formed on the first sub-dielectric substrate.
- the first groove portion includes a first sub-groove portion formed on the first sub-dielectric substrate, and a second sub-connection via hole formed on the first sub-dielectric substrate.
- first sub-groove part and the second sub-groove part are both through-groove parts, and the first sub-groove part and the second sub-groove part are opposite and connected ;
- the surface of the first sub-dielectric substrate facing away from the second sub-dielectric substrate is used as the first surface, and the surface of the second sub-dielectric substrate facing away from the first sub-dielectric substrate is used as the second surface ;
- Forming the magnetic core includes:
- a first portion of the magnetic core formed in the first sub-slot portion fills the first sub-slot portion, a second portion of the magnetic core is formed in the second sub-slot portion, and the first portion and Part II Contact;
- the step of forming the first substructure also includes:
- the method further includes:
- the second interlayer insulating layer is formed on the second surface to insulate the magnetic core and the second substructure.
- An embodiment of the present disclosure provides a filter, which includes any of the above inductors.
- the filter further includes a capacitor electrically connected to the inductor, and the first plate of the capacitor is connected to the first substructure of the inductor to form an integrated structure.
- An embodiment of the present disclosure provides an electronic device, which includes the above-mentioned filter.
- FIG. 1 is a top view of an inductor according to an embodiment of the present disclosure.
- FIG. 2 is a perspective view of an inductor according to an embodiment of the present disclosure.
- FIG. 3 is a cross-sectional view of an inductor according to a first example of an embodiment of the present disclosure.
- FIG. 4 is a cross-sectional view of an intermediate product formed in step S11 of the method for manufacturing an inductor according to the first example of the embodiment of the present disclosure.
- FIG. 5 is a cross-sectional view of an intermediate product formed in step S12 of the first example of the inductor manufacturing method according to the embodiment of the present disclosure.
- FIG. 6 is a cross-sectional view of an intermediate product formed in step S13 of the first example of the inductor manufacturing method according to the embodiment of the present disclosure.
- FIG. 7 is a cross-sectional view of an intermediate product formed in step S14 of the first example of the inductor manufacturing method according to the embodiment of the present disclosure.
- FIG. 8 is a cross-sectional view of an intermediate product formed in step S15 of the first example of the inductor manufacturing method according to the embodiment of the present disclosure.
- FIG. 9 is a cross-sectional view of an intermediate product formed in step S16 of the first example of the inductor manufacturing method according to the embodiment of the present disclosure.
- Figure 10 is a cross-sectional view of an intermediate product formed in step S17 of the first example of the inductor manufacturing method according to the embodiment of the present disclosure.
- FIG. 11 is a cross-sectional view of an inductor according to a second example of an embodiment of the present disclosure.
- FIG. 12 is a cross-sectional view of an inductor according to a third example of an embodiment of the present disclosure.
- FIG. 13 is a cross-sectional view of an inductor according to a fourth example of an embodiment of the present disclosure.
- FIG. 14 is a cross-sectional view of an inductor according to a fifth example of an embodiment of the present disclosure.
- FIG. 15 is a cross-sectional view of an inductor according to a sixth example of an embodiment of the present disclosure.
- FIG. 16 is a cross-sectional view of an inductor according to a seventh example of an embodiment of the present disclosure.
- FIG. 17 is a cross-sectional view of an inductor according to an eighth example of the embodiment of the present disclosure.
- FIG. 18 is a cross-sectional view of an inductor according to a ninth example of an embodiment of the present disclosure.
- FIG. 1 is a top view of an inductor according to an embodiment of the present disclosure.
- each first substructure 21 of the inductor extends along the first direction and is arranged side by side along the second direction; each second substructure 22 of the inductor extends along the first direction. extending in three directions and arranged side by side along the second direction.
- the first direction, the second direction, and the third direction are all different directions.
- the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are not vertically arranged as example.
- the inductor includes N first substructures 21 and N-1 second substructures 22 as an example for description, where N ⁇ 2, and N is an integer.
- the first end and the second end of the first substructure 21 each at least partially overlap with a first connection via 11 in orthographic projection on the first dielectric substrate 10 .
- the first end and the second end of a first substructure 21 correspond to different first connection vias 11, that is, a first substructure 21 and two first connection vias 11 are orthogonally projected on the first dielectric substrate. At least partially overlap.
- the first end of the i-th second substructure 22 of the inductor is connected to the first end of the i-th first substructure 21 and the second end of the i+1th first substructure 21, forming a coil structure of the inductor.
- 1 ⁇ i ⁇ N-1, and i is an integer.
- first lead terminal 22 is connected to the second end of the first first substructure 21 of the inductor coil
- second lead terminal 23 is connected to the first end of the Nth first substructure 21. connect.
- first lead terminal 22 and the second lead terminal 23 can be arranged on the same layer as the second substructure 22 and use the same material.
- the first lead terminal 22 can be connected to the first lead terminal 22 through the first connection via 11
- the second end of the first substructure 21 is connected.
- the second lead end 23 can be connected to the first end of the Nth first substructure 21 through the first connection via 11 .
- Figure 2 is a perspective view of an inductor according to an embodiment of the present disclosure; as shown in Figure 2, the inductor according to an embodiment of the present disclosure not only includes the various structures introduced above, but also includes a magnetic core 3 integrated on the first dielectric substrate 10, and the magnetic core 3Through the coil structure of the inductor. Adding the magnetic core 3 structure to the inductor in the embodiment of the present disclosure can achieve a multiple increase in the inductance value, reduce the device packaging volume, facilitate the development of device miniaturization, and at the same time help reduce the preparation cost of the device.
- ⁇ 0 is the vacuum magnetic permeability
- ⁇ r is the material magnetic permeability
- K is the nanometer coefficient
- N is the number of winding turns
- A is the coil cross-sectional area
- l is the coil length.
- the material of the first dielectric substrate 10 can be selected from non-ferromagnetic materials such as silicon, ceramics, glass, etc.
- the magnetic permeability is close to the vacuum magnetic permeability. If ferromagnetic materials and alloys such as iron, cobalt, nickel, etc. are added as the material of the magnetic core 3, Most of their magnetic permeabilities are much greater than 1000. Therefore, the inductance value per unit area will be improved, which is conducive to wider use of devices and small and medium-sized packaging applications.
- Figure 3 is a cross-sectional view of an inductor according to a first example of an embodiment of the present disclosure; as shown in Figure 3, the inductor includes a first dielectric substrate 10, a first substructure 21, a second substructure 22, a magnetic Core 3, first connecting electrode, and first interlayer insulating layer 41.
- the first dielectric substrate 10 of the inductor has a first surface (upper surface) and a second surface (lower surface) oppositely arranged along the thickness direction thereof.
- the first dielectric substrate 10 of the inductor has a first connection path penetrating along the thickness direction.
- the hole 11, and the first groove portion 12 that penetrates part of the first dielectric substrate 10 in the thickness direction, the first groove portion 12 is a blind groove, and the opening is away from the second surface.
- the first substructure 21 is disposed on the first surface of the first dielectric substrate 10
- the second substructure 22 is disposed on the second surface of the first dielectric substrate 10
- the first connection electrode 25 is disposed in the first connection via hole 11
- the magnetic core 3 is disposed in the first groove 12 and fills the first groove 12 , that is, the first groove 12 is away from the second surface and the first surface. Flush.
- the first interlayer insulating layer is disposed on the first surface to separate the first substructure 21 and the magnetic core 3 to prevent short circuit between the two.
- a second connection via hole is provided on the first insulating layer, and the second connection via hole is arranged in one-to-one correspondence with the first connection via hole 11.
- the second substructure 22 is connected to the first connection electrode 25 through the second connection via hole,
- the first substructure 21 and the second substructure 22 sequentially form a coil structure of the inductor through the first connection electrode 25, and the magnetic core 3 is limited within the coil structure.
- a first protective layer 51 is provided on the side of the first substructure 21 facing away from the first dielectric substrate 10
- a second protective layer 52 is provided on the side of the second substructure 22 facing away from the first dielectric substrate 10 .
- the first protective layer 51 and the second protective layer 52 are respectively used to isolate the first substructure 21 and the second substructure 22 from external water and oxygen to avoid device damage.
- the method for preparing the above inductor may specifically include the following steps.
- the first dielectric substrate 10 includes but is not limited to a glass substrate, and its thickness is about 0.2mm-2mm.
- Step S11 may specifically include: first cleaning the first dielectric substrate 10 and performing ultrasonic cleaning using organic solvents such as deionized water and ethanol, for example, ultrasonic cleaning in each solvent for 15 minutes.
- organic solvents such as deionized water and ethanol
- Step S11 may specifically include: first cleaning the first dielectric substrate 10 and performing ultrasonic cleaning using organic solvents such as deionized water and ethanol, for example, ultrasonic cleaning in each solvent for 15 minutes.
- organic solvents such as deionized water and ethanol
- Step S11 may specifically include: first cleaning the first dielectric substrate 10 and performing ultrasonic cleaning using organic solvents such as deionized water and ethanol, for example, ultrasonic cleaning in each solvent for 15 minutes.
- the cross-sectional shape of the first groove portion 12 may be square, trapezoidal or hourglass-shaped.
- the length of the first groove portion 12 is approximately equal to the length of the inductor (that is, the first connection via holes 11 form two groups arranged side by side, and the length of each group of the first connection via holes 11 is also the length of the inductor coil).
- the length of the first slot 12 ensures that the magnetic core 3 can be in the coil structure of the inductor.
- the width of the first slot 12 is less than half the distance between the two sets of first connection via holes, ensuring that the magnetic core 3 is connected to the first connection via hole. There is sufficient distance between the electrodes 25.
- the depth of the first groove portion 12 may range from 10 ⁇ m to 500 ⁇ m depending on the design.
- step S12 may include preparing a first seed layer 100 in the first connection via hole 11 and the first groove part 12 by including but not limited to sputtering.
- the first seed layer 100 may select Ti, W, Cu, Mo, Ni, etc.
- the first shielding structure 61 is formed by spin coating, exposure, and development.
- the first seed layer 100 in the first connection via hole 11 is electroplated to form the first connection electrode 25, and the first shielding structure 61 is removed to form a second shielding structure 62 located on the first connection via hole 11, as shown in Figure 6 shown.
- the first connection electrode 25 is a component of the inductor, and is made of a metal with good conductivity, such as Cu, Au, Ag, Al, or other metals.
- the metallization process of the first connection via hole 11 can be realized by electroplating and chemical plating to ensure that the formed first connection electrode 25 can be connected with the subsequently formed first substructure 21 and second substructure 22. conduction.
- the second shielding structure 62 is formed by spin coating, exposure, and development.
- the material of the magnetic core 3 in the first groove part 12 can be selected from ferromagnetic materials, specifically Ni, Co, Fe, permalloy, ferrite and other high magnetic permeability materials.
- the step In S14 you can choose chemical plating, PVD or CVD and other process preparation.
- the second shielding structure 62 is removed. It should be noted that since excess structures will be left on the first surface of the first dielectric substrate 10 during electroplating, PVD and other processes, excess metal and substances on the surface of the substrate are removed through chemical mechanical polishing, and the metal in the first connection hole is ensured. It is flat to ensure that the metal in the first connection via hole 11 realizes electrical conduction between the first surface and the second surface of the first dielectric substrate 10 .
- the material of the magnetic core 3 may be a conductor, in order to avoid the influence of the magnetic core 3 on the inductance, the surface of the magnetic core 3 needs to be isolated by preparing a first interlayer insulating layer 41 on the first surface.
- the material of the first interlayer insulating layer 41 may be inorganic materials, such as silicon nitride, silicon oxide, etc., and the thickness of the first interlayer insulating layer 41 is between 0.5 ⁇ m and 2 ⁇ m.
- the first interlayer insulating layer 41 can be formed by PVD or CVD, and then etched and developed to form a second connection via hole.
- the first interlayer insulating layer 41 can also be made of organic materials, such as polyimide (PI) or other resin materials. In this case, the first interlayer insulating layer 41 can be patterned through glue spreading, exposure and development, etc. , forming a second connection via.
- PI polyimide
- step S16 may include forming a second seed layer by a method including but not limited to sputtering, and then spin-coating photoresist, exposing and developing, and electroplating the second seed layer to form the first substructure 21 of the inductor.
- the material of the second seed layer is generally metal materials such as Au, Al, and Cu.
- the thickness of the first substructure 21 is generally between 1 ⁇ m and 10 ⁇ m. In order to ensure the flatness of the first substructure 21 of the inductor, the surface can be subsequently processed by chemical mechanical polishing.
- the material of the first protective layer 51 can be inorganic materials, such as silicon nitride, silicon oxide, etc., with a thickness of 0.5 ⁇ m-5 ⁇ m. At this time, the first protective layer 51 is prepared by PVD or CVD.
- the first protective layer 51 may also be made of organic material, such as polyimide (PI) or other resin materials, and the first protective layer 51 is realized through a glue dispersion process.
- PI polyimide
- step S17 may include forming a third seed layer by a method including but not limited to sputtering, and then spin-coating photoresist, exposing and developing, and electroplating the third seed layer to form the second substructure 22 of the inductor.
- the material of the third seed layer is generally metal materials such as Au, Al, and Cu.
- the thickness of the second substructure 22 is generally between 1 ⁇ m and 10 ⁇ m. In order to ensure the flatness of the second substructure 22 of the inductor, the surface can be subsequently processed by chemical mechanical polishing.
- the material of the second protective layer 52 may be an inorganic material, such as silicon nitride, silicon oxide, etc., with a thickness of 0.5 ⁇ m-5 ⁇ m. At this time, the second protective layer 52 is prepared by PVD or CVD.
- the second protective layer 52 may also be made of organic material, such as polyimide (PI) or other resin materials, and the second protective layer 52 is realized through a glue dispersion process.
- PI polyimide
- Figure 11 is a cross-sectional view of an inductor according to the second example of the embodiment of the present disclosure; as shown in Figure 11, the structure of the inductor in this example is roughly the same as that in the first example, and the only difference is that, In this example, the magnetic core 3 in the first groove portion 12 does not completely fill the first groove portion 12 .
- the first interlayer insulating layer 41 covering the magnetic core 3 is provided in the first groove portion 12 .
- the surface of the first interlayer insulating layer 41 covering the magnetic core 3 facing away from the second substructure 22 is flush with the first surface of the first dielectric substrate 10 .
- the preparation method of the inductor in the second example is roughly the same as that in the first example. The only difference is that when forming the magnetic core 3, the magnetic core 3 is partially filled. On the one hand, it can save materials; Speed up the process. For patterning, the first interlayer insulating layer 41 only covers the magnetic core 3. The remaining steps can be the same as the first example, so they will not be repeated here.
- Figure 12 is a cross-sectional view of an inductor according to the third example of the embodiment of the present disclosure.
- the inductor structure in this example is roughly the same as the first inductor structure. The difference is that the first The first groove portion 12 in the dielectric substrate 10 is a through groove, and the magnetic core 3 fills the first groove portion 12 at this time.
- a second interlayer insulating layer 42 is provided on the second surface; the second interlayer insulating layer 42 has a third connection via hole corresponding to the first connection via hole 11; the second substructure 22 passes through the third connection via hole 11.
- the connection via hole is electrically connected to the first connection electrode 25 .
- the other parts of the structure of the inductor in this example are the same as those in the first example, so the description will not be repeated here.
- the preparation method of the inductor in the third example is substantially the same as that in the first example, and the only difference is that the first groove portion 12 formed in the first dielectric substrate 10 is a through groove. Therefore, when forming the first connection electrode 25 located in the first connection via hole 11 , it is necessary to form the first shielding structure 61 on both the first surface and the second surface of the first dielectric substrate 10 to shield the first groove portion 12 . Moreover, before forming the second substructure 22 , a second interlayer insulating layer 42 and a third connection via hole penetrating the second interlayer insulating layer 42 need to be formed. The formation process of the second interlayer insulating layer 42 and the first interlayer insulating layer 41 is the same, so the description will not be repeated here. The preparation method of other structures of the inductor of the third example is roughly the same as that of the first example, so the description thereof will not be repeated here.
- Figure 13 is a cross-sectional view of an inductor according to a fourth example of the embodiment of the present disclosure; as shown in Figure 13, the inductor in this example is the same as the first example, including a first dielectric substrate 10,
- the difference between the first connection electrode 25, the first substructure 21 and the second substructure 22 is that in this example, the first dielectric substrate 10 includes a first sub-dielectric substrate 101 and a second sub-dielectric substrate 102 arranged in a stack;
- the surface of one sub-dielectric substrate 101 facing away from the second sub-dielectric substrate 102 is used as the first surface
- the surface of the second sub-dielectric substrate 102 facing away from the first sub-dielectric substrate 101 is used as the second surface.
- the first substructure 21 is provided on the surface of the first sub-dielectric substrate 101 facing away from the second sub-dielectric substrate 102; the second sub-structure 22 is provided on the surface of the second sub-dielectric substrate 102 facing away from the first sub-dielectric substrate 101.
- the first connection via hole 11 includes a first sub-connection via hole formed on the first sub-dielectric substrate 101 and a second sub-connection via hole formed on the second sub-dielectric substrate 102; the first groove portion 12 includes a first sub-connection via hole formed on the second sub-dielectric substrate 102.
- a first protective layer 51 is provided on the side of the first substructure 21 facing away from the first dielectric substrate 10
- a second protective layer 52 is provided on the side of the second substructure 22 facing away from the first dielectric substrate 10 .
- the first protective layer 51 and the second protective layer 52 are respectively used to isolate the first substructure 21 and the second substructure 22 from external water and oxygen to avoid device damage.
- the manufacturing method of the inductor in the fourth example is the same as the manufacturing method in the first example.
- the first sub-connection via hole and the second sub-connection via hole can be formed in the same manner as the first connection via hole 11 in the first example;
- the two sub-groove parts may be formed in the same manner as the first groove part 12 in the first example;
- the first sub-connection electrode 251 and the second sub-connection electrode 252 may be formed in the same manner as the first connection electrode 25 in the first example.
- the first part 31 and the second part 32 of the magnetic core 3 can be formed in the same way as the magnetic core 3 in the first example.
- the formation methods of the first substructure 21 , the second substructure 22 , the first protective layer 51 and the second protective layer 52 are also the same as in the first example. Therefore, the preparation process of each layer structure in the embodiment of the present disclosure will not be described in detail.
- the first dielectric substrate 10 and the second sub-dielectric substrate 102 need to be The dielectric substrate 102 is formed into an integrated structure through a bonding process to achieve conduction between the first sub-connection electrode 251 and the second sub-connection electrode 252 to form an inductor structure.
- the first sub-dielectric substrate 101 and the second sub-dielectric substrate 102 are combined through a bonding process, which can effectively reduce the stress problem in a single substrate.
- an inductor with a larger cross-sectional area can be prepared, realizing the preparation of a large inductor and reducing the need for drilling holes. Technical difficulty.
- Figure 14 is a cross-sectional view of an inductor according to a fifth example of the embodiment of the present disclosure; as shown in Figure 14, the inductor structure of this example is roughly the same as that of the fourth example, and the only difference is that the magnetic core 3
- the first part 31 does not fully fill the first sub-slot
- the second part 32 of the magnetic core 3 does not fully fill the second sub-slot.
- a third interlayer insulating layer 43 is provided in between.
- the preparation and material selection of the third interlayer insulating layer 43 can be the same as the above-mentioned first interlayer insulating layer 41. Therefore, the description will not be repeated here.
- the structure of the inductor in the fifth example is roughly the same as that in the fourth example, so the preparation methods of the two can also be the same, so the description will not be repeated here.
- Figure 15 is a cross-sectional view of an inductor according to a sixth example of the embodiment of the present disclosure; as shown in Figure 15, the inductor in this example is roughly the same as the fourth example, and the only difference is that the first sub-slot The first part 31 and the second sub-slot part are both through-slots. At this time, the first part 31 of the magnetic core 3 fills the first sub-slot part, and the second part 32 fills the second sub-slot part.
- the surface of the first sub-dielectric substrate 101 facing away from the second sub-dielectric substrate 102 is used as the first surface
- the surface of the second sub-dielectric substrate 102 facing away from the first sub-dielectric substrate 101 is used as the second surface
- the first interlayer insulating layer 41 has a second connection via hole corresponding to the first connection via hole 11
- the second interlayer insulating layer 42 is provided on the second surface.
- the interlayer insulating layer 42 has a third connection via hole corresponding to the first connection via hole 11; the first substructure 21 is electrically connected to the first connection electrode 25 through the second connection via hole; the second substructure 22 is electrically connected through the third connection via hole.
- the via hole is electrically connected to the first connection electrode 25 .
- the preparation method of the inductor in the sixth example is substantially the same as that in the fourth example, and the only difference is that the first sub-slot part and the second sub-slot part are through-slots.
- a first interlayer insulating layer 41 is formed on the side of the first sub-dielectric substrate 101 facing away from the second sub-dielectric substrate 102
- a second interlayer insulating layer 42 is formed on the side of the second sub-dielectric substrate facing away from the first sub-dielectric substrate 101 ;
- the first interlayer insulating layer 41 is formed with a second connection via hole corresponding to the first connection via hole 11
- the second interlayer insulating layer 42 is formed with a third connection via hole corresponding to the first connection via hole 11.
- first substructure 21 is electrically connected to the first connection electrode 25 through the second connection via hole
- second substructure 22 is electrically connected to the first connection electrode 25 through the third connection via hole.
- the formation of the first interlayer insulating layer 41 and the second interlayer insulating layer 42 is the same as the third example, so the description will not be repeated here.
- Figure 16 is a cross-sectional view of an inductor according to a seventh example of the embodiment of the present disclosure; as shown in Figure 16, the structure of the inductor in this example is roughly the same as that in the first example, and the only difference is that in The inductor includes a second dielectric substrate 20, a second substructure 22 is disposed on the second dielectric substrate 20, and a fourth interlayer insulating layer 44 is disposed on the side of the second substructure 22 away from the second dielectric substrate 20. And the fourth interlayer insulating layer 44 is provided with a fourth connection via hole corresponding to the first connection via hole 11 , and the second substructure 22 is connected to the first connection via the transfer electrode 7 located in the fourth connection via hole.
- the electrode 25 is electrically connected.
- the second substructure 22 of the inductor can be formed on the second dielectric substrate 20, which effectively reduces the difficulty of process preparation, facilitates the accuracy of patterning preparation and reduces the film stress problem of the substrate.
- Each structure on the first dielectric substrate 10 in this example can be prepared in the same process as the structure on the first sub-dielectric substrate 101 in the fourth example, so the details will not be repeated here.
- Figure 17 is a cross-sectional view of an inductor according to an eighth example of the embodiment of the present disclosure; as shown in Figure 17, the structure of the inductor in this example is roughly the same as that in the seventh example, and the only difference is that the magnetic The core 3 does not fill the first groove portion 12 completely, and a fifth interlayer insulating layer 45 located between the magnetic core 3 and the fourth interlayer insulating layer 44 is also provided in the first groove portion 12.
- the remaining structures are the same as those of the fourth interlayer insulating layer 44.
- the structures of the seven examples are the same, so they will not be repeated here.
- the preparation method of the inductor in the eighth example is roughly the same as that in the seventh example. The only difference is that in the eighth example, a fifth interlayer insulating layer needs to be formed in the first groove portion 12 .
- the preparation method and materials of the interlayer insulating layer 45 are the same as the preparation method and materials of the first interlayer insulating layer 41 in the second example, so the details are not repeated here.
- Figure 18 is a cross-sectional view of an inductor according to a ninth example of the embodiment of the present disclosure; as shown in Figure 18, the structure of the inductor in this example is roughly the same as that in the seventh example, and the only difference is that in In this example, the first groove 12 is a through groove, the magnetic core 3 fills the first groove 12, and a first interlayer insulation layer 41 is provided on the first surface of the first dielectric substrate 10; the first interlayer insulation The layer 41 has second connection vias arranged in one-to-one correspondence with the first connection vias 11; the first substructure 21 is electrically connected to the first connection electrode 25 through the second connection vias. After the structures on the first dielectric substrate 10 and the second dielectric substrate 20 are prepared, they are bonded to form an inductor structure.
- Each structure on the first dielectric substrate 10 in this example can be prepared in the same process as the structure on the first sub-dielectric substrate 101 in the fifth example, so the details will not be repeated here.
- An embodiment of the present disclosure also provides a filter, which includes any one of the above inductors.
- the filter may also include a capacitor electrically connected to the inductor to form an LC filter.
- the coil structure of the inductor in the embodiment of the present disclosure is provided with magnets, its magnetic permeability is mostly much greater than 1000. Therefore, the inductance value per unit area will be improved, which is conducive to wider use of the device and miniaturization of the package. application.
- the first plate of the capacitor can be connected to the first substructure of the inductor to form an integrated structure, that is, the first plate of the capacitor is formed at the same time as the first substructure of the inductor is formed, which does not increase the process cost. .
- capacitors and inductors in the filter in the embodiment of the present disclosure may be one or multiple, and the number of capacitors and inductors in the filter is not limited here.
- resistors and other devices can also be installed in the filter, which will not be listed here.
- An embodiment of the present disclosure provides an electronic device, which includes the above-mentioned filter.
- the electronic device may be a mobile terminal, a notebook computer, and other devices. It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.
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Abstract
本公开提供一种电感及其制备方法、滤波器、电子设备,属于电子元件技术领域。本公开的电感,其包括:第一介质基板(10),包括沿其厚度方向相对设置的第一表面和第二表面,第一介质基板(10)具有沿其厚度方向上贯穿的第一连接过孔(11),以及贯穿第一介质基板(10)的至少部分的第一槽部(12);第一子结构(21),设置在第一表面;第二子结构(22),设置在第二表面;第一连接电极(25),设置在第一连接过孔(11)内,并将第一子结构(21)和第二子结构(22)顺次连接形成电感的线圈结构;磁芯(3)设置在第一槽部(12)内,且磁芯(3)与第一子结构(21)和第二子结构(22)绝缘设置,且位于线圈结构内。
Description
本公开属于电子元件技术领域,具体涉及一种电感及其制备方法、滤波器、电子设备。
微电子工艺技术飞速发展,使得各类电子器件的尺寸快速下降。随着器件尺寸的减小,新技术不断涌现,如IPD技术、MEMS技术、纳米技术等。工艺的提升,也再次促进了器件设计的进步,电子结构的设计尺寸越来越小,芯片尺寸、走线互联、封装结构都在不断的发展。因此,工业和日常生活中各类设备都在追求小型化发展,如常见的移动终端、笔记本等设备。因此,器件的小型化发展是必然趋势。器件的尺寸已经从宏观米和厘米量级向微观的微米和纳米量级发展。
无源器件是各类设备中都必不可少的基础元件,包括电阻、电容和电感。常见的电感是在环形磁铁上环绕多圈导线组成电感,通过磁芯的作用大幅提高电感性能。但随着尺寸的下降,较小尺寸的平面螺旋电感逐渐成为常见类型,线圈尺寸减小到毫米和微米量级,但由于其螺旋线的环绕特性,电感线圈会较大占据面积,同时无法带有磁芯结构;与此同时,与其他器件组合使用时也会造成走线距离较大,走线间互感严重。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一,提供一种电感及其制备方法、滤波器、电子设备。
本公开实施例提供一种电感,其包括:
第一介质基板,包括沿其厚度方向相对设置的第一表面和第二表面,所述第一介质基板具有沿其厚度方向上贯穿的第一连接过孔,以及贯穿所述第一介质基板的至少部分的第一槽部;
第一子结构,设置在所述第一表面;
第二子结构,设置在所述第二表面;
第一连接电极,设置在所述第一连接过孔内,并将第一子结构和所述第二子结构顺次连接形成所述电感的线圈结构;
磁芯,设置在所述第一槽部内,且所述磁芯与所述第一子结构和所述第二子结构绝缘设置,且位于所述线圈结构内。
其中,所述第一槽部为盲槽,所述磁芯填充所述第一槽部,在所述第一表面上设置有第一层间绝缘层,所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔,所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接。
其中,所述第一槽部为盲槽,所述磁芯背离所述第二子结构的表面与所述第一表面之间具有一定的间距;在所述第一槽部内设置有覆盖所述磁芯背离第二子结构的表面的第一层间绝缘层。
其中,所述第一层间绝缘层背离所述磁芯的表面与所述第一表面平齐。
其中,所述第一槽部为通槽,所述磁芯填充所述第一槽部;在所述第一表面上设置有第一层间绝缘层,在所述第二表面上设置有第二层间绝缘层;所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔,所述第二层间绝缘层具有与所述第一连接过孔对应的第三连接过孔;所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接;所述第二子结构通过所述第三连接过孔与所述第一连接电极电连接。
其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一子介质基板背离所述第二子介质基板的表面作为所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;
所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为盲槽,且所述 第一子槽部的开口和所述第二子槽部开口相对且连通;所述磁芯包括第一部分和第二部分,所述第一部分填充所述第一子槽部,所述第二部分填充所述第二槽部,且所述第一部分和第二部分接触。
其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一子介质基板背离所述第二子介质基板的表面作为所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;
所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为盲槽,且所述第一子槽部的开口和所述第二子槽部开口相对且连通;所述磁芯包括第一部分和第二部分,所述第一部分设置在所述第一子槽部内,所述第二部分设置在所述第二槽部内,且所述第一部分和第二部分之间设置第三层间绝缘层。
其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为通槽,且所述第一子槽部和所述第二子槽部相对且连通;所述磁芯包括第一部分和第二部分;所述第一部分填充所述第一子槽部,所述第二部分填充所述第二槽部,且所述第一部分和第二部分接触;
所述第一子介质基板背离所述第二子介质基板的表面用作所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;
在所述第一表面上设置有第一层间绝缘层,在所述第二表面上设置有第二层间绝缘层;所述第一层间绝缘层具有与所述第一连接过孔对应设置的第 二连接过孔,所述第二层间绝缘层具有与所述第一连接过孔对应的第三连接过孔;所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接;所述第二子结构通过所述第三连接过孔与所述第一连接电极电连接。
其中,在所述第一子结构背离所述第一介质基板的一侧设置有第一保护层。
其中,在所述第二子结构背离所述第一介质基板的一侧设置有第一保护层。
其中,所述第一槽部为盲槽,且所述第一槽部的开口背离所述第一子结构;所述电感还包括第二介质基板;所述第二子结构设置在所述第二介质基板上,且在所述第二子结构背离所述第二介质基板的一侧设置有第四层间绝缘层,且在所述第四层间绝缘层中设置有与所述第一连接过孔对应设置的第四连接过孔,所述第二子结构通过所述第四连接过孔与所述第一连接电极电连接。
其中,所述第一槽部为盲槽,且所述第一槽部的开口背离所述第一子结构;所述电感还包括第二介质基板;所述第二子结构设置在所述第二介质基板上,且在所述第二子结构背离所述第二介质基板的一侧设置有第四层间绝缘层,且在所述第四层间绝缘层中设置有与所述第一连接过孔对应设置的第四连接过孔,所述第二子结构通过所述第四连接过孔与所述第一连接电极电连接;
所述第一槽部内还设置有位于所述磁芯背离所述第一子结构一侧的第五绝缘层;所述第五绝缘层背离所述磁芯的表面与所述第二表面平齐。
其中,所述第一槽部为通槽,所述磁芯填充所述第一槽部;在所述第一表面上设置有第一层间绝缘层;所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔;所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接;
所述电感还包括第二介质基板;所述第二子结构设置在所述第二介质基板上,且在所述第二子结构背离所述第二介质基板的一侧设置有第四层间绝 缘层,且在所述第四层间绝缘层中设置有与所述第一连接过孔对应设置的第四连接过孔,所述第二子结构通过所述第四连接过孔与所述第一连接电极电连接。
其中,在所述第四连接过孔内设置有转接电极,所述第二子结构通过所述转接电极与所述第一连接电极电连接。
其中,在所述第一子结构背离所述第一介质基板的一侧设置有第一保护层。
本公开实施例提供一种电感的制备方法,其包括:
提供一第一介质基板,所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面,所述第一介质基板具有沿其厚度方向上贯穿的第一连接过孔,以及贯穿所述第一介质基板的至少部分的第一槽部;
在所述第一表面上形成第一子结构,在所述第二表面上形成所述第二子结构,在所述第一连接过孔内形成第一连接电极,在所述第一槽部内形成磁芯;其中,苏搜狐第一连接电极将第一子结构和所述第二子结构顺次连接形成所述电感的线圈结构,所述磁芯与所述第一子结构和所述第二子结构绝缘设置,且位于所述线圈结构内。
其中,所述第一槽部为盲槽,且所述第一槽部的开口朝向所述第一子结构;在所述第一表面上形成所述第一子结构的步骤之前,还包括:
在所述第一表面形成所述第一层间绝缘层,以使所述磁芯和所述第一子结构绝缘设置。
其中,所述第一槽部为通槽;在所述第一表面上形成所述第一子结构的步骤之前,还包括:
在所述第一表面形成所述第一层间绝缘层,以使所述磁芯和所述第一子结构绝缘设置;
在所述第二表面上形成所述第二子结构的步骤之后,还包括:
在所述第二表面形成所述第二层间绝缘层,以使所述磁芯和所述第二子 结构绝缘设置。
其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为盲槽,且所述第一子槽部和所述第二子槽部相对且连通;所述第一子介质基板背离所述第二子介质基板的表面用作所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;
形成所述磁芯包括:
在所述第一子槽部中形成所述磁芯的第一部分填充所述第一子槽部,在所述第二子槽部中形成所述磁芯第二部分;
所述制备方法还包括:
在所述第一部分和第二部分之间形成第三绝缘层。
其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为通槽,且所述第一子槽部和所述第二子槽部相对且连通;所述第一子介质基板背离所述第二子介质基板的表面用作所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;
形成所述磁芯包括:
在所述第一子槽部中形成所述磁芯的第一部分填充所述第一子槽部,在所述第二子槽部中形成所述磁芯第二部分,且所述第一部分和第二部分接触;
在形成所述第一子结构的步骤之后还包括:
在所述第一表面形成所述第一层间绝缘层,以使所述磁芯和所述第一子结构绝缘设置;
在所述第二表面上形成所述第二子结构的步骤之后,还包括:
在所述第二表面形成所述第二层间绝缘层,以使所述磁芯和所述第二子结构绝缘设置。
本公开实施例提供一种滤波器,其包括上述的任一电感。
其中,所述滤波器还包括与所述电感电连接的电容,且所述电容的第一极板与所述电感的第一子结构连接为一体结构。
本公开实施例提供一种电子设备,其包括上述的滤波器。
图1为本公开实施例的电感的俯视图。
图2为本公开实施例的电感的立体图。
图3为本公开实施例的第一种示例的电感的截面图。
图4为本公开实施例的第一种示例的电感的制备方法的步骤S11所形成的中间产品的截面图。
图5为本公开实施例的第一种示例的电感的制备方法的步骤S12所形成的中间产品的截面图。
图6为本公开实施例的第一种示例的电感的制备方法的步骤S13所形成的中间产品的截面图。
图7为本公开实施例的第一种示例的电感的制备方法的步骤S14所形成的中间产品的截面图。
图8为本公开实施例的第一种示例的电感的制备方法的步骤S15所形成的中间产品的截面图。
图9为本公开实施例的第一种示例的电感的制备方法的步骤S16所形成的中间产品的截面图。
图10为本公开实施例的第一种示例的电感的制备方法的步骤S17所形 成的中间产品的截面图。
图11为本公开实施例的第二种示例的电感的截面图。
图12为本公开实施例的第三种示例的电感的截面图。
图13为本公开实施例的第四种示例的电感的截面图。
图14为本公开实施例的第五种示例的电感的截面图。
图15为本公开实施例的第六种示例的电感的截面图。
图16为本公开实施例的第七种示例的电感的截面图。
图17为本公开实施例的第八种示例的电感的截面图。
图18为本公开实施例的第九种示例的电感的截面图。
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”、“一”或者“该”等类似词语也不表示数量限制,而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
图1为本公开实施例的电感的俯视图,参照图1,电感的各第一子结构21均沿第一方向延伸,且沿第二方向并排设置;电感的各第二子结构22均沿第三方向延伸,且沿第二方向并排设置。其中,第一方向、第二方向、第三方向均为不同的方向,在本公开实施例中,以第一方向和第二方向相互垂 直,第一方向和第三方向相交且非垂直设置为例。当然,第一子结构21和第二子结构22的延伸方向也可以互换,均在本公开实施例的保护范围内。另外,在本公实施例中以电感包括N个第一子结构21和N-1个第二子结构22为例进行说明,其中,N≥2,且N为整数。第一子结构21的第一端和第二端分别与一个第一连接过孔11在第一介质基板10上正投影至少部分交叠。且一个第一子结构21的第一端和第二端对应不同的第一连接过孔11,也即一个第一子结构21与两个第一连接过孔11在第一介质基板上正投影至少部分交叠。此时,电感的第i个第二子结构22第一端连接第i个第一子结构21的第一端和第i+1个第一子结构21的第二端,形成电感的线圈结构,其中,1≤i≤N-1,且i为整数。
在此需要说明的是,其中,第一引线端22与电感线圈的第一个第一子结构21的第二端,第二引线端23则与第N个第一子结构21的第一端连接。进一步的,第一引线端22和第二引线端23可以与第二子结构22同层设置,且采用相同的材料,此时第一引线端22可以通过第一连接过孔11与第一个第一子结构21的第二端连接,相应的,第二引线端23则可以通过第一连接过孔11与第N个第一子结构21的第一端连接。
图2为本公开实施例的电感的立体图;如图2所示,本公开实施例电感不仅包括上述介绍的各个结构,而且还包括集成在第一介质基板10上的磁芯3,且磁芯3贯穿电感的线圈结构。在本公开实施例的电感中增加磁芯3结构,实现电感感值多倍增加,降低器件封装体积,有利于器件小型化的发展,同时有利于降低器件的制备成本。
具体的,根据电感计算公式
L=μ
0μ
rKN
2A/l
其中μ
0为真空磁导率,μ
r为材料磁导率,K为纳高卡系数,N为绕线匝数,A为线圈截面积,l为线圈长度。根据公式可知,在电感结构同样的情况下,电感中如果加入磁芯3将根据磁导率倍数增加电感。第一介质基板10的材料可以选用如硅、陶瓷、玻璃等非铁磁材料磁导率与真空磁导率接 近,如果加入如铁、钴、镍等铁磁材料和合金作为磁芯3材料,其磁导率大多远大于1000,因此,单位面积下的电感值将得到提高,有利于器件更广泛的使用以及封装中小型化应用。
以下几种具体示例对本公开实施例中的电感及其电感的制备方法。
第一种示例:图3为本公开实施例的第一种示例的电感的截面图;如图3所示,电感包括第一介质基板10、第一子结构21、第二子结构22、磁芯3、第一连电极、第一层间绝缘层41。电感的第一介质基板10具有沿其厚度方向相对设置的第一表面(上表面)和第二表面(下表面。)电感的第一介质基板10具有沿其厚度方向上贯穿的第一连接过孔11,以及在厚度方向上贯穿部分第一介质基板10的第一槽部12,第一槽部12为盲槽,且开口背离第二表面。第一子结构21设置在第一介质基板10的第一表面上,第二子结构22设置在第一介质基板10的第二表面上。第一连接电极25设置在第一连接过孔11内,磁芯3设置在第一槽部12内,且填充第一槽部12,也即第一槽部12背离第二表面与第一表面平齐。第一层间绝缘层设置在第一表面上用以将第一子结构21和磁芯3隔开,避免二者短接。第一绝缘层上设置有第二连接过孔,且第二连接过孔与第一连接过孔11一一对应设置,第二子结构22通过第二连接过孔与第一连接电极25连接,从而实现第一子结构21和第二子结构22通过第一连接电极25顺次形成电感的线圈结构,磁芯3被限定在线圈结构内。
进一步的,在第一子结构21背离第一介质基板10的一侧还设置有第一保护层51,在第二子结构22背离第一介质基板10的一侧还设置有第二保护层52。第一保护层51和第二保护层52分别用于将第一子结构21和第二子结构22与外界水氧隔离,避免器件损坏。
对于该种示例中的电感的各层结构的材料和厚度均结合下述制备方法一同进行说明。
对于上述电感的制备方法具体可以包括如下步骤。
S11、提供一第一介质基板10,并在第一介质基板10上形成第一连接 过孔11和第一槽部12,如图4所示。
在一些示例中,第一介质基板10包括但不限于玻璃基,其厚度在0.2mm-2mm左右。
步骤S11具体可以包括:首先对第一介质基板10进行清洗,通过去离子水、乙醇等有机溶剂进行超声清洗,例如:每种溶剂中分别超声15min。根据电感的设计要求,在对应的位置进行打孔和沟槽的刻蚀,形成第一连接过孔11和第一槽部12。根据第一介质基板10的厚度以及设计要求,第一连接过孔11的直径可以在50μm-1000μm,根据孔径的大小可以选择激光打孔、喷砂打孔、聚焦放电打孔等方式形成第一连接过孔11。由于刻蚀工艺的不同第一槽部12的截面形状可以为方形、梯形和沙漏形。第一槽部12根据设计要求第一槽部12的长度约等于电感线圈的长度(也即第一连接过孔11形成并排设置的两组,每组第一连接过孔11的长度也即第一槽部12的长度),保证磁芯3可以在电感的线圈结构中,第一槽部12的宽度小于两组第一连接过过孔之间的间距一半,保证磁芯3与第一连接电极25之间有足够的距离。第一槽部12的深度根据设计可以在10μm-500μm。
S12、形成覆盖第一连接过孔11侧壁和第一槽部12侧壁的第一种子层100,并通过第一遮挡结构61对第一槽部12进行遮挡,如图5所示。
在一些示例中,步骤S12可以包括通过包括但不限于溅射在第一连接过孔11和第一槽部12内进行第一种子层100的制备,第一种子层100可以选择Ti、W、Cu、Mo、Ni等。通过旋涂、曝光、显影形成第一遮挡结构61。
S13、第一连接过孔11内的第一种子层100进行电镀形成第一连接电极25,将第一遮挡结构61去除,形成位于第一连接过孔11上的第二遮挡结构62,如图6所示。
在一些示例中,第一连接电极25为电感的组成部分,其选择导电性较好的金属,可以为Cu、Au、Ag、Al等金属。在步骤S13中可以通过电镀和化学镀的方式实现第一连接过孔11金属化的过程,保证所形成的第一连接电极25可以与后续形成的第一子结构21和第二子结构22可以导通。通过 旋涂、曝光、显影形成第二遮挡结构62。
S14、形成位于第一槽部12内的磁芯3,并去除第二遮挡结构62,如图7所示。
在一些示例中,第一槽部12内的磁芯3材料可以选用铁磁材料,具体可以为Ni、Co、Fe、坡莫合金、铁氧体等高磁导材料,根据材料可以选择在步骤S14中可以选择化学镀、PVD或CVD等工艺制备。磁芯3结构制备后去除第二遮挡结构62。需要说明的是,由于电镀、PVD等工艺制备中在第一介质基板10的第一表面会留有多余结构,通过化学机械研磨去除基底表面多余的金属和物质,并且保证第一连接孔内金属平整,确保第一连接过孔11内金属实现第一介质基板10的第一表面和第二表面的电气导通。
S15、在第一介质基板10的第一表面形成第一层间绝缘层41,并形成贯穿第一层间绝缘层41的第二连接过孔,且第二连接过孔与第一连接过孔11一一对应设置,如图8所示。
由于磁芯3材料可能为导体,为避免磁芯3对电感的影响,在磁芯3表面需要通过制备第一表面上的第一层间绝缘层41进行隔离。第一层间绝缘层41的材料可以为无机材料,如氮化硅、氧化硅等,第一层间绝缘层41的厚度在0.5μm-2μm。第一层间绝缘层41的形成可以通过PVD或者CVD的方法制备,之后刻蚀、显影形成第二连接过孔。第一层间绝缘层41也可以为有机材料,如聚酰亚胺(PI)或其他树脂材料,此时第一层间绝缘层41可以通过匀胶、曝光显影等工艺实现绝缘层的图形化,形成第二连接过孔。
S16、在第一层间绝缘层41背离第一介质基板10的一层,通过构图工艺形成包括第一子结构21的图形,并在第一子结构21背离第一介质基板10的表面形成第一保护层51,如图9所示。
在一些示例中,在步骤S16可以包括通过包括但不限于溅射的方式形成第二种子层,之后旋涂光刻胶、曝光显影、电镀第二种子层形成电感的第一子结构21。第二种子层的材料一般为Au、Al、Cu等金属材料。第一子结构21的厚度一般在1μm-10μm。为了保证电感的第一子结构21的平整性可 以后续通过化学机械研磨处理表面。
第一保护层51材料可以为无机材料,如氮化硅、氧化硅等,厚度在0.5μm-5μm。此时第一保护层51通过PVD或者CVD的方法制备。第一保护层51也可以为有机材料,如聚酰亚胺(PI)或其他树脂材料,通过匀胶工艺实现第一保护层51。
S17、将第一介质基板10翻转,在第一介质基板10的第二表面形成第二子结构22,并在第二子结构22背离第一介质基板10的表面形成第二保护层52,如图10所示。
在一些示例中,步骤S17可以包括通过包括但不限于溅射的方式形成第三种子层,之后旋涂光刻胶、曝光显影、电镀第三种子层形成电感的第二子结构22。第三种子层的材料一般为Au、Al、Cu等金属材料。第二子结构22的厚度一般在1μm-10μm。为了保证电感的第二子结构22的平整性可以后续通过化学机械研磨处理表面。
第二保护层52材料可以为无机材料,如氮化硅、氧化硅等,厚度在0.5μm-5μm。此时第二保护层52通过PVD或者CVD的方法制备。第二保护层52也可以为有机材料,如聚酰亚胺(PI)或其他树脂材料,通过匀胶工艺实现第二保护层52。
至此完成第一种示例中的电感各层结构的制备。
第二种示例:图11为本公开实施例的第二种示例的电感的截面图;如图11所示,该示例中的电感与第一种示例中的电感结构大致相同,区别仅在于,在该种示例中,第一槽部12内的磁芯3并未将第一槽部12填充满。此时在第一槽部12内设置覆盖磁芯3的第一层间绝缘层41。例如:覆盖磁芯3的第一层间绝缘层41背离第二子结构22的表面与第一介质基板10的第一表面平齐。
对于第二种示例中的电感的制备方法与第一种示例中的制备方法大致相同,区别仅在于,在形成磁芯3时,磁芯3选择部分填充,一方面可以节省材料,一方面可以加快工艺。对于图案化的第一层间绝缘层41仅覆盖磁 芯3。其余步骤均可以与第一种示例相同,故在此不再重复描述。
第三种示例,图12为本公开实施例的第三种示例的电感的截面图;如图12所示,该种示例中的电感结构与第一种电感结构大致相同,区别在于,第一介质基板10中的第一槽部12为通槽,此时磁芯3填充第一槽部12。在第二表面上设置有第二层间绝缘层42;第二层间绝缘层42具有与第一连接过孔11一一对应的第三连接过孔;第二子结构22通过所述第三连接过孔与第一连接电极25电连接。对于该种示例中的电感的其他部分结构均与第一种示例中相同,故在此不再重复描述。
对于第三种示例中的电感的制备方法与第一种示例中的制备方法大致相同,区别仅在于,第一介质基板10中所形成的第一槽部12为通槽。因此在形成位于第一连接过孔11中的第一连接电极25时,需要在第一介质基板10的第一表面和第二表面均形成遮挡第一槽部12的第一遮挡结构61。而且在形成第二子结构22之前还需要形成第二层间绝缘层42,以及贯穿第二层间绝缘层42的第三连接过孔。对于第二层间绝缘层42与第一层间绝缘层41的形成工艺相同,故在此不再重复描述。对于第三种示例的电感的其他结构的制备方法均与第一种示例中大致相同故在此不再重复描述。
第四种示例:图13为本公开实施例的第四种示例的电感的截面图;如图13所示,该种示例的电感与第一种示例中相同,均包括第一介质基板10、第一连接电极25、第一子结构21和第二子结构22,区别在于,在该示例中第一介质基板10包括叠层设置的第一子介质基板101和第二子介质基板102;第一子介质基板101背离第二子介质基板102的表面作为第一表面,第二子介质基板102背离第一子介质基板101的表面用作第二表面。也就是说,第一子结构21设置在第一子介质基板101背离第二子介质基板102的表面;第二子结构22设置在第二子介质基板102背离第一子介质基板101的表面。第一连接过孔11包括形成在第一子介质基板101上的第一子连接过孔,以及在第二子介质基板102上的第二子连接过孔;第一槽部12包括设置形成在第一子介质基板101上的第一子槽部,以及形成在第二子介质基板102上的第二子槽部;第一子槽部和第二子槽部均为盲槽,且第一子槽部 的开口和第二子槽部开口相对且连通;磁芯3包括第一部分31和第二部分32,第一部分31填充第一子槽部,第二部分32填充第二槽部,且第一部分31和第二部分32接触。
进一步的,在第一子结构21背离第一介质基板10的一侧还设置有第一保护层51,在第二子结构22背离第一介质基板10的一侧还设置有第二保护层52。第一保护层51和第二保护层52分别用于将第一子结构21和第二子结构22与外界水氧隔离,避免器件损坏。
对于第四种示例中的电感的制备方法与第一种示例中的制备方法中所采用的工艺相同。具体的,在第四种示例中,第一子连接过孔、第二子连接过孔的形成方式可以第一种示例中的第一连接过孔11形成方式相同;第一子槽部和第二子槽部可以与第一种示例中的第一槽部12形成方式相同;第一子连接电极251和第二子连接电极252可以与第一种示例中的第一连接电极25的形成方式相同;磁芯3的第一部分31和第二部分32可以与第一种示例中的磁芯3的形成方式相同。而对于第一子结构21、第二子结构22、第一保护层51和第二保护层52的形成方式也均与第一种示例中相同。故对于本公开实施例中的各层结构的制备工艺不再进行详细描述。
需要说明的是,在本公开实施的电感的第一子介质基板101上的各层结构和第二子介质基板102上的各层结构均形成之后,需要将第一介质基板10和第二子介质基板102通过键合工艺形成为一体结构,实现第一子连接电极251和第二子连接电极252的导通,以形成电感结构。第一子介质基板101和第二子介质基板102通过键合工艺结合,可以有效的降低单衬底中应力问题,同时可以制备更大截面积的电感,实现大电感的制备,降低了打孔技术的难度。
第五种示例:图14为本公开实施例的第五种示例的电感的截面图;如图14所示,该示例的电感结构与第四种示例大致相同,区别仅在于,磁芯3的第一部分31并为将第一子槽部填充满,磁芯3的第二部分32也并未将第二子槽部填充满,此时在磁芯3的第一部分31和第二部分32之间设置第三层间绝缘层43。其中,第三层间绝缘层43的制备和材料选择均可以与上 述的第一层间绝缘层41相同。故在在此不再重复描述。
对于第五种示例中的电感的结构与第四种示例大致相同,故二者的制备方法也是可以相同的,故在此不再重复描述。
第六种示例:图15为本公开实施例的第六种示例的电感的截面图;如图15所示,该示例中的电感与第四种示例大致相同,区别仅在于,第一子槽部和第二子槽部均为通槽,此时磁芯3的第一部分31填充第一子槽部,第二部分32填充第二子槽部。另外,第一子介质基板101背离第二子介质基板102的表面用作第一表面,第二子介质基板102背离第一子介质基板101的表面用作第二表面;在第一表面上设置有第一层间绝缘层41,在第二表面上设置有第二层间绝缘层42;第一层间绝缘层41具有与第一连接过孔11对应设置的第二连接过孔,第二层间绝缘层42具有与第一连接过孔11对应的第三连接过孔;第一子结构21通过第二连接过孔与第一连接电极25电连接;第二子结构22通过第三连接过孔与第一连接电极25电连接。
在第六种示例中的电感的制备方法与第四种示例大致相同,区别仅在于,第一子槽部和第二子槽部为通槽。在第一子介质基板101背离第二子介质基板102的一侧形成有第一层间绝缘层41,在二子介质基板背离第一子介质基板101的一侧形成有第二层间绝缘层42;第一层间绝缘层41中形成有与第一连接过孔11对应设置的第二连接过孔,第二层间绝缘层42中形成有与第一连接过孔11对应的第三连接过孔;第一子结构21通过第二连接过孔与第一连接电极25电连接;第二子结构22通过第三连接过孔与第一连接电极25电连接。而对于第一层间绝缘层41和第二层间绝缘层42的形成与第三种示例相同,故在此不再重复描述。
第七种示例:图16为本公开实施例的第七种示例的电感的截面图;如图16所示,该种示例中的电感与第一种示例的结构大致相同,区别仅在于,在该电感中包括第二介质基板20,第二子结构22设置在第二介质基板20上,且在第二子结构22背离第二介质基板20的一侧设置有第四层间绝缘层44,且在第四层间绝缘层44中设置有与第一连接过孔11对应设置的第四连接过孔,第二子结构22通过位于第四连接过孔内的转接电极7与第一连接 电极25电连接。在该种结构中,电感的第二子结构22可以设置有形成在第二介质基板20上,有效降低了工艺制备难度,有利于图形化制备的准确性同时降低衬底的膜层应力问题。在第一介质基板10和第二介质基板20上的结构制备完成将二者键合,以形成电感结构。
对于该种示例中的第一介质基板10上的各结构可以与第四种示例中的第一子介质基板101上的结构的制备工艺相同,故在此不再重复赘述。
第八种示例:图17为本公开实施例的第八种示例的电感的截面图;如图17所示,该种示例中的电感与第七种示例的结构大致相同,区别仅在于,磁芯3未将第一槽部12填充满,在第一槽部12内还设置有位于磁芯3和第四层间绝缘层44之间的第五层间绝缘层45,其余结构均与第七种示例的结构相同,故在此不再重复赘述。
对于第八种示例中的电感的制备方法与第七种示例中大致相同,区别仅在于在第八种示例中需要形成第一槽部12内的第五层层间绝缘层,该第五层间绝缘层45的制备方式和材料与第二种示例中的第一层间绝缘层41的制备方式和材料相同,故在此不再重复赘述。
第九种示例:图18为本公开实施例的第九种示例的电感的截面图;如图18所示,该种示例中的电感与第七种示例的结构大致相同,区别仅在于,在该种示例中,第一槽部12为通槽,磁芯3填充第一槽部12,在第一介质基板10的第一表面上设置有第一层间绝缘层41;第一层间绝缘层41具有与第一连接过孔11一一对应设置的第二连接过孔;第一子结构21通过第二连接过孔与第一连接电极25电连接。在第一介质基板10和第二介质基板20上的结构制备完成将二者键合,以形成电感结构。
对于该种示例中的第一介质基板10上的各结构可以与第五种示例中的第一子介质基板101上的结构的制备工艺相同,故在此不再重复赘述。
需要说明的是以上仅给出几种示例中的电感及其制备方法,但这并不构成对本公开实施例保护范围的限制,只要是在第一介质基板10中集成磁芯3的电感均在本公开实施例保护范围内。
本公开实施例还提供一种滤波器,其包括上述任意一种电感,当然该滤波器还可以包括与电感电连接的电容,以形成LC滤波器。
由于在本公开实施例中的电感的线圈结构内设置有磁,其磁导率大多远大于1000,因此,单位面积下的电感值将得到提高,有利于器件更广泛的使用以及封装中小型化应用。
在一些示例中,电容的第一极板可以与电感的第一子结构连接为一体结构,也即在形成电感的第一子结构的同时形成电容的第一极板,这样不会增加工艺成本。
需要说明的是,本公开实施例中的滤波器中的电容和电感的数量可以均为一个,也可以为多个,在此并不对滤波器中的电容和电感的数量进行限定。当然在滤波器中还可以设置电阻等器件,在此不再一一列举。
本公开实施例提供一种电子设备,其包括上述的滤波器,该电子设备可以为移动终端、笔记本电脑等设备。可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (23)
- 一种电感,其包括:第一介质基板,包括沿其厚度方向相对设置的第一表面和第二表面,所述第一介质基板具有沿其厚度方向上贯穿的第一连接过孔,以及贯穿所述第一介质基板的至少部分的第一槽部;第一子结构,设置在所述第一表面;第二子结构,设置在所述第二表面;第一连接电极,设置在所述第一连接过孔内,并将第一子结构和所述第二子结构顺次连接形成所述电感的线圈结构;磁芯,设置在所述第一槽部内,且所述磁芯与所述第一子结构和所述第二子结构绝缘设置,且位于所述线圈结构内。
- 根据权利要求1所述的电感,其中,所述第一槽部为盲槽,所述磁芯填充所述第一槽部,在所述第一表面上设置有第一层间绝缘层,所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔,所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接。
- 根据权利要求1所述的电感,其中,所述第一槽部为盲槽,所述磁芯背离所述第二子结构的表面与所述第一表面之间具有一定的间距;在所述第一槽部内设置有覆盖所述磁芯背离第二子结构的表面的第一层间绝缘层。
- 根据权利要求3所述的电感,其中,所述第一层间绝缘层背离所述磁芯的表面与所述第一表面平齐。
- 根据权利要求1所述的电感,其中,所述第一槽部为通槽,所述磁芯填充所述第一槽部;在所述第一表面上设置有第一层间绝缘层,在所述第二表面上设置有第二层间绝缘层;所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔,所述第二层间绝缘层具有与所述第一连接过孔对应的第三连接过孔;所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接;所述第二子结构通过所述第三连接过孔与所述第一连接电极电连接。
- 根据权利要求1所述的电感,其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一子介质基板背离所述第二子介质基板的表面作为所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为盲槽,且所述第一子槽部的开口和所述第二子槽部开口相对且连通;所述磁芯包括第一部分和第二部分,所述第一部分填充所述第一子槽部,所述第二部分填充所述第二槽部,且所述第一部分和第二部分接触。
- 根据权利要求1所述的电感,其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一子介质基板背离所述第二子介质基板的表面作为所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为盲槽,且所述第一子槽部的开口和所述第二子槽部开口相对且连通;所述磁芯包括第一部分和第二部分,所述第一部分设置在所述第一子槽部内,所述第二部分设置在所述第二槽部内,且所述第一部分和第二部分之间设置第三层间绝缘层。
- 根据权利要求1所述的电感,其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为通槽,且所述第一子槽部和所述第二子槽部相对且连 通;所述磁芯包括第一部分和第二部分;所述第一部分填充所述第一子槽部,所述第二部分填充所述第二槽部,且所述第一部分和第二部分接触;所述第一子介质基板背离所述第二子介质基板的表面用作所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;在所述第一表面上设置有第一层间绝缘层,在所述第二表面上设置有第二层间绝缘层;所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔,所述第二层间绝缘层具有与所述第一连接过孔对应的第三连接过孔;所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接;所述第二子结构通过所述第三连接过孔与所述第一连接电极电连接。
- 根据权利要求2-8中任一项所述的电感,其中,在所述第一子结构背离所述第一介质基板的一侧设置有第一保护层。
- 根据权利要求2-8中任一项所述的电感,其中,在所述第二子结构背离所述第一介质基板的一侧设置有第一保护层。
- 根据权利要求1所述的电感,其中,所述第一槽部为盲槽,且所述第一槽部的开口背离所述第一子结构;所述电感还包括第二介质基板;所述第二子结构设置在所述第二介质基板上,且在所述第二子结构背离所述第二介质基板的一侧设置有第四层间绝缘层,且在所述第四层间绝缘层中设置有与所述第一连接过孔对应设置的第四连接过孔,所述第二子结构通过所述第四连接过孔与所述第一连接电极电连接。
- 根据权利要求1所述的电感,其中,所述第一槽部为盲槽,且所述第一槽部的开口背离所述第一子结构;所述电感还包括第二介质基板;所述第二子结构设置在所述第二介质基板上,且在所述第二子结构背离所述第二介质基板的一侧设置有第四层间绝缘层,且在所述第四层间绝缘层中设置有与所述第一连接过孔对应设置的第四连接过孔,所述第二子结构通过所述第四连接过孔与所述第一连接电极电连接;所述第一槽部内还设置有位于所述磁芯背离所述第一子结构一侧的第 五绝缘层;所述第五绝缘层背离所述磁芯的表面与所述第二表面平齐。
- 根据权利要求1所述的电感,其中,所述第一槽部为通槽,所述磁芯填充所述第一槽部;在所述第一表面上设置有第一层间绝缘层;所述第一层间绝缘层具有与所述第一连接过孔对应设置的第二连接过孔;所述第一子结构通过所述第二连接过孔与所述第一连接电极电连接;所述电感还包括第二介质基板;所述第二子结构设置在所述第二介质基板上,且在所述第二子结构背离所述第二介质基板的一侧设置有第四层间绝缘层,且在所述第四层间绝缘层中设置有与所述第一连接过孔对应设置的第四连接过孔,所述第二子结构通过所述第四连接过孔与所述第一连接电极电连接。
- 根据权利要求11-13中任一项所述的电感,其中,在所述第四连接过孔内设置有转接电极,所述第二子结构通过所述转接电极与所述第一连接电极电连接。
- 根据权利要求11-13中任一项所述的电感,其中,在所述第一子结构背离所述第一介质基板的一侧设置有第一保护层。
- 一种电感的制备方法,其包括:提供一第一介质基板,所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面,所述第一介质基板具有沿其厚度方向上贯穿的第一连接过孔,以及贯穿所述第一介质基板的至少部分的第一槽部;在所述第一表面上形成第一子结构,在所述第二表面上形成所述第二子结构,在所述第一连接过孔内形成第一连接电极,在所述第一槽部内形成磁芯;其中,苏搜狐第一连接电极将第一子结构和所述第二子结构顺次连接形成所述电感的线圈结构,所述磁芯与所述第一子结构和所述第二子结构绝缘设置,且位于所述线圈结构内。
- 根据权利要求16所述的电感的制备方法,其中,所述第一槽部为盲槽,且所述第一槽部的开口朝向所述第一子结构;在所述第一表面上形成所述第一子结构的步骤之前,还包括:在所述第一表面形成所述第一层间绝缘层,以使所述磁芯和所述第一子结构绝缘设置。
- 根据权利要求16所述的电感的制备方法,其中,所述第一槽部为通槽;在所述第一表面上形成所述第一子结构的步骤之前,还包括:在所述第一表面形成所述第一层间绝缘层,以使所述磁芯和所述第一子结构绝缘设置;在所述第二表面上形成所述第二子结构的步骤之后,还包括:在所述第二表面形成所述第二层间绝缘层,以使所述磁芯和所述第二子结构绝缘设置。
- 根据权利要求16所述的电感的制备方法,其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为盲槽,且所述第一子槽部和所述第二子槽部相对且连通;所述第一子介质基板背离所述第二子介质基板的表面用作所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;形成所述磁芯包括:在所述第一子槽部中形成所述磁芯的第一部分填充所述第一子槽部,在所述第二子槽部中形成所述磁芯第二部分;所述制备方法还包括:在所述第一部分和第二部分之间形成第三绝缘层。
- 根据权利要求16所述的电感的制备方法,其中,所述第一介质基板包括叠层设置的第一子介质基板和第二子介质基板;所述第一连接过孔包括形成在所述第一子介质基板上的第一子连接过孔,以及形成在所述第二子介质基板上的第二子连接过孔;所述第一槽部包括设置形成在所述第一子介 质基板上的第一子槽部,以及形成在所述第二子介质基板上的第二子槽部;所述第一子槽部和第二子槽部均为通槽,且所述第一子槽部和所述第二子槽部相对且连通;所述第一子介质基板背离所述第二子介质基板的表面用作所述第一表面,所述第二子介质基板背离所述第一子介质基板的表面用作所述第二表面;形成所述磁芯包括:在所述第一子槽部中形成所述磁芯的第一部分填充所述第一子槽部,在所述第二子槽部中形成所述磁芯第二部分,且所述第一部分和第二部分接触;在形成所述第一子结构的步骤之后还包括:在所述第一表面形成所述第一层间绝缘层,以使所述磁芯和所述第一子结构绝缘设置;在所述第二表面上形成所述第二子结构的步骤之后,还包括:在所述第二表面形成所述第二层间绝缘层,以使所述磁芯和所述第二子结构绝缘设置。
- 一种滤波器,其包括权利要求1-15中任一项所述的电感。
- 根据要求21所述的滤波器,其中,还包括与所述电感电连接的电容,且所述电容的第一极板与所述电感的第一子结构连接为一体结构。
- 一种电子设备,其包括权利要求21或22所述的滤波器。
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