WO2023272838A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023272838A1
WO2023272838A1 PCT/CN2021/108425 CN2021108425W WO2023272838A1 WO 2023272838 A1 WO2023272838 A1 WO 2023272838A1 CN 2021108425 W CN2021108425 W CN 2021108425W WO 2023272838 A1 WO2023272838 A1 WO 2023272838A1
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WIPO (PCT)
Prior art keywords
display area
display
sub
pixel circuit
along
Prior art date
Application number
PCT/CN2021/108425
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English (en)
French (fr)
Inventor
王美红
Original Assignee
武汉天马微电子有限公司
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Application filed by 武汉天马微电子有限公司 filed Critical 武汉天马微电子有限公司
Priority to US17/756,374 priority Critical patent/US20240203311A1/en
Publication of WO2023272838A1 publication Critical patent/WO2023272838A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the display field, in particular to a display panel and a display device.
  • the display area of the display panel is reused as a photosensitive element integration area.
  • the photosensitive elements such as the front camera and infrared sensing element can be arranged on the back of the photosensitive element integrated area of the display panel, and the light can pass through the photosensitive element integrated area to reach the photosensitive element to realize corresponding functions such as front camera and infrared sensing. .
  • the luminance of the light-emitting elements in a part of the display area multiplexed as the photosensitive element integration area is usually lower than the luminance of the light-emitting elements in other display areas, resulting in uneven brightness display.
  • the invention provides a display panel and a display device, which improve the uniformity of display brightness.
  • an embodiment of the present invention provides a display panel, which includes: a first display area, a second display area, a third display area, and a fourth display area, the third display area is located at the edge of the first display area along a first direction At least one side, the second display area at least partially surrounds the first display area and the third display area, the first display area is multiplexed as a photosensitive element integration area, and the fourth display area is located between the third display area and the second display area along the second direction.
  • the second direction crosses the first direction; the first pixel circuit and the first light-emitting element are electrically connected to each other, the first light-emitting element is located in the first display region, and the first light-emitting element is located in the first display region.
  • a pixel circuit is located in the third display area; the second pixel circuit and the second light emitting element electrically connected to each other are located in the second display area; the third pixel circuit and the third light emitting element electrically connected to each other are located in the third display area; Electrically connected fourth pixel circuits and fourth light-emitting elements are located in the fourth display area, and the fourth pixel circuits are arranged in at least one row in the fourth display area, and each row of fourth pixel circuits includes at least one first pixel circuit arranged along the first direction.
  • each first arrangement unit includes N fourth pixel circuits and a first interval space, N is a positive integer, wherein, N fourth pixel circuits are arranged adjacently in sequence along the first direction, and the first interval The space is located on one side of the N fourth pixel circuits along the first direction; and a plurality of first data lines, each first data line is electrically connected to at least one first pixel circuit and at least one second pixel circuit, wherein at least A first data line passes through the first space.
  • an embodiment of the present invention provides a display device, which includes the display panel according to any one of the foregoing implementation manners in one aspect of the present invention.
  • the fourth pixel circuits are arranged in at least one row in the fourth display area, and each row of fourth pixel circuits includes a first arrangement unit, and each first arrangement unit includes a first arrangement unit.
  • the separation space is to remove at least part of the pixel circuits in the fourth display area that do not need to be connected to the light-emitting element, so as to obtain the first separation space.
  • the first interval space can be used as a winding space for the first data line. At least one first data line passes through the first interval space, thereby reducing or even preventing the first data line from passing through the first display area, and reducing the number of first data lines passing through the first display area.
  • the overlapping of the orthographic projection on the surface and the orthographic projection of the wiring connected to the first display area on the display surface weakens the load impact of these wirings on the first data line. At this time, the load difference between the part of the first data line in the third display area and the part in the second display area is reduced, so that the luminance of the first light-emitting element and the second light-emitting element tend to be more the same, which improves the display.
  • the panel and the display device display brightness uniformity.
  • FIG. 1 is a schematic top view of a display panel provided according to an embodiment of the present invention.
  • FIG. 2 is a partially enlarged schematic diagram of a display panel provided according to an embodiment of the present invention.
  • FIG. 3 is a partially enlarged schematic diagram of a display panel provided according to another embodiment of the present invention.
  • FIG. 4 is a partially enlarged schematic diagram of a fourth display area in a display panel provided according to an embodiment of the present invention.
  • FIG. 5 is a partially enlarged schematic diagram of a display panel provided according to another embodiment of the present invention.
  • FIG. 6 is a partially enlarged schematic diagram of a display panel provided according to another embodiment of the present invention.
  • FIG. 7 is a partially enlarged schematic diagram of a display panel provided according to another embodiment of the present invention.
  • Fig. 8 is a schematic structural diagram after the light-emitting element in Fig. 7 is hidden;
  • FIG. 9 is a partially enlarged schematic diagram of a display panel provided according to another embodiment of the present invention.
  • Fig. 10 is a schematic structural diagram after the light-emitting element in Fig. 9 is hidden;
  • FIG. 11 is a partially enlarged schematic diagram of a display panel provided according to yet another embodiment of the present invention.
  • FIG. 12 is a schematic structural view of the light-emitting element in FIG. 11 hidden.
  • FIG. 1 is a schematic top view of a display panel provided according to an embodiment of the present invention
  • FIG. 2 is a partially enlarged schematic view of a display panel provided according to an embodiment of the present invention, wherein FIG. 2 is for example It is a partially enlarged illustration of the Q1 area in Figure 1.
  • the display panel 100 includes a first display area DA1 , a second display area DA2 , a third display area DA3 and a fourth display area DA4 .
  • the third display area DA3 is located on at least one side of the first display area DA1 along the first direction X.
  • the second display area DA2 at least partially surrounds the first display area DA1 and the third display area DA3.
  • the first display area DA1 is multiplexed as a photosensitive element integration area.
  • the fourth display area DA4 is located between the third display area DA3 and the second display area DA2 and between the first display area DA1 and the second display area DA2 along the second direction Y, and the second direction Y crosses the first direction X.
  • the display panel 100 further includes a non-display area (not shown) surrounding the first display area DA1 , the second display area DA2 , the third display area DA3 and the fourth display area DA4 .
  • the display panel 100 further includes a first pixel circuit C1 and a first light emitting element P1 electrically connected to each other, a second pixel circuit C2 and a second light emitting element P2 electrically connected to each other, a third pixel circuit C3 and a third light emitting element electrically connected to each other.
  • the element P3, the fourth pixel circuit C4 and the fourth light emitting element P4 are electrically connected to each other.
  • the first light emitting element P1 is located in the first display area DA1, and the first pixel circuit C1 is located in the third display area DA3.
  • each first pixel circuit C1 is electrically connected to at least one first light emitting element P1 through a corresponding connection line CL.
  • the second pixel circuit C2 and the second light emitting element P2 electrically connected to each other are located in the second display area DA2.
  • the third pixel circuit C3 and the third light emitting element P3 electrically connected to each other are located in the third display area DA3.
  • the fourth pixel circuit C4 and the fourth light emitting element P4 electrically connected to each other are located in the fourth display area DA4.
  • a dummy pixel circuit CD in addition to the first pixel circuit C1 and the third pixel circuit C3, a dummy pixel circuit CD may also be arranged, and the dummy pixel circuit CD can balance different display areas.
  • the etching pattern density can improve the etching uniformity or display uniformity.
  • the dummy pixel circuit CD may not be set in the third display area DA3. It can be understood that in order to ensure that the first display area DA1 can display images normally, the number of light-emitting elements in the first display area DA1 needs to meet a certain number, so the number of connecting lines CL is large, and the first display area DA1 and the third display The adjacent positions of the area DA3 will be arranged relatively densely.
  • the fourth pixel circuits C4 are arranged in at least one row in the fourth display area DA4.
  • Each row of fourth pixel circuits C4 includes at least one first arrangement unit U1 arranged along the first direction X.
  • Each first arrangement unit U1 includes N fourth pixel circuits C4 and a first space K1, where N is a positive integer.
  • the N fourth pixel circuits C4 are adjacently arranged in sequence along the first direction X, and the first space K1 is located on one side of the N fourth pixel circuits C4 along the first direction X.
  • the display panel 100 also includes a plurality of first data lines 110 .
  • Each first data line 110 is electrically connected to at least one first pixel circuit C1 and at least one second pixel circuit C2. Wherein, at least one first data line 110 passes through the first space K1, so that the orthographic projections of the plurality of first data lines 110 on the display surface do not overlap with the orthographic projections of the connection line CL on the display surface.
  • the fourth pixel circuits C4 are arranged in at least one row in the fourth display area DA4, and each row of fourth pixel circuits C4 includes a first arrangement unit U1, and each first arrangement unit U1 Including the first interval space K1, that is, removing at least part of the pixel circuits in the fourth display area DA4 that do not need to be connected to light-emitting elements, so as to obtain the first interval space K1 vacantly.
  • the first interval space K1 can be used as a winding space for the first data line 110, and at least one first data line 110 passes through the first interval space K1, thereby reducing or even preventing the first data line 110 from passing through the first display area DA1, reducing multiple
  • the overlapping of the orthographic projection of the first data line 110 on the display surface and the orthographic projection of the wiring (such as the connection line CL) connected to the first display area on the display surface avoids dense and overlapping with the first data line 110.
  • the wiring has a load effect on the first data line 110 and affects the data signal.
  • the load difference between the part of the first data line 110 in the third display area DA3 and the part in the second display area DA2 is greatly reduced, and at the same time, the load difference of the data lines between different display areas can also be reduced.
  • the influence of wiring such as the connection line CL on the coupling crosstalk of the first data line 110 is reduced, so that the luminance of the first light-emitting element P1 and the second light-emitting element P2 tend to be more the same, and the uniformity of the display luminance of the display panel 100 is improved.
  • the driving current corresponding to the light-emitting element with lower brightness will be increased, but increasing the driving current will reduce the life of the light-emitting element, thereby affecting the life of the entire display panel and the display effect.
  • the load difference between the part of the first data line 110 in the third display area DA3 and the part in the second display area DA2 can be reduced, and the connection between the first light emitting element P1 and the second display area DA2 can be reduced.
  • the difference in luminous brightness between the two light-emitting elements P2 improves the display brightness uniformity of the display panel 100 , and at the same time can improve the service life of the first light-emitting element P1 and increase the service life of the display panel 100 .
  • the fourth pixel circuits C4 are arranged in one row in the fourth display area DA4, and in some other embodiments, the fourth pixel circuits C4 may be arranged in two rows, three rows, etc. in the fourth display area DA4. other number of rows.
  • Each row of fourth pixel circuits C4 includes at least one first arrangement unit U1.
  • Each first arrangement unit U1 includes a first interval K1.
  • the number of the first arrangement unit U1 is multiple, so that the number of the first space K1 is also multiple.
  • FIG. 3 is a partially enlarged schematic diagram of a display panel provided according to another embodiment of the present invention, wherein FIG. 3 is, for example, a partially enlarged schematic diagram of the area Q1 in FIG. 1 .
  • each row of fourth pixel circuits C4 includes one first arrangement unit U1, so that the number of first interval spaces K1 in each row of fourth pixel circuits C4 is also one.
  • the number of the first interval spaces K1 in the fourth pixel circuits C4 in each row may be two, three or any other number.
  • At least one fourth pixel circuit C4 in each row of fourth pixel circuits C4 may be replaced with a dummy pixel circuit that is not used to realize light emitting elements.
  • each first pixel circuit C1 is electrically connected to at least one first light emitting element P1 through a corresponding connection line CL.
  • Each first data line 110 includes a first sub-data line 111, a second sub-data line 112, and a third sub-data line 113.
  • the first sub-data line 111 extends in the third display area DA3 along the second direction Y, and is connected with At least one first pixel circuit C1 is electrically connected
  • the second sub-data line 112 extends in the second display area DA2 along the second direction Y, and is electrically connected to a plurality of second pixel circuits C2
  • the third sub-data line 113 passes through the fourth
  • the display area DA4 is electrically connected to the first sub-data line 111 and the second sub-data line 112, wherein at least one third sub-data line 113 passes through the first interval space K1.
  • the third sub-data line 113 electrically connects the first sub-data line 111 and the second sub-data line 112, so that the first pixel circuit C1 and the second pixel circuit C2 can supply data signals through the same first data line 110, extending to the second sub-data line.
  • the third sub-data line 113 of the four-display area DA4 passes through the first space K1, avoiding the overlapping of the orthographic projection of the third sub-data line 113 on the display surface and the orthographic projection of the connection line CL on the display surface, avoiding the overlap of the connection line
  • the CL has a load effect on the first data line 110 , so as to improve the uniformity of display brightness of the display panel 100 .
  • the first light emitting element P1 electrically connected to the first pixel circuit C1 and the second light emitting element P2 electrically connected to the second pixel circuit C2 are located in the same column.
  • FIG. 4 is a partially enlarged schematic diagram of a fourth display area in a display panel provided according to an embodiment of the present invention.
  • the display panel 100 includes a plurality of first pixel units PU1 located in the fourth display area DA4.
  • Each first pixel unit PU1 includes M fourth light emitting elements P4, wherein N is a positive integer multiple of M.
  • each first pixel unit PU1 includes three fourth light emitting elements P4, which may be red fourth light emitting elements P4, green fourth light emitting elements P4 and blue fourth light emitting elements P4.
  • Each first arrangement unit U1 includes three fourth pixel circuits C4.
  • each first arrangement unit U1 may include six, nine or other fourth pixel circuits C4.
  • the first space K1 of the first arrangement unit U1 may be based on the structure in which pixel circuits are arranged without intervals, and at least part of the fourth display area DA4 that does not need to be connected to light-emitting elements may be removed. The pixel circuit, so that the first interval space K1 is obtained free.
  • the fourth pixel circuits C4 adjacent to the first pixel unit PU1 can be The pixel circuit C4 is retained, and the remaining pixel circuits are removed, so that the physical position of the fourth pixel circuit C4 and the corresponding fourth light-emitting element P4 is closer, and the space occupied by the wire between the fourth pixel circuit C4 and the fourth light-emitting element P4 is shortened , so that the first interval space K1 with a larger area and a more regular shape can be left unoccupied.
  • the length of the first interval space K1 along the first direction X is equal to 0.5 to 3 times the length of the fourth pixel circuit C4 along the first direction X.
  • the length of the first interval space K1 along the first direction X is 0.5 times the length of a single fourth pixel circuit C4 along the first direction X.
  • the length of the first interval space K1 along the first direction X is three times the length of a single fourth pixel circuit C4 along the first direction X.
  • the arrangement space of the fourth pixel circuit C4 will be squeezed, so that the number of the fourth pixel circuit C4 in the fourth display area DA4 is too small, which is not conducive to realizing high Pixel density display panel driver.
  • the length of the first interval space K1 along the first direction X is 0.5 to 3 times the length of a single fourth pixel circuit C4 along the first direction X, the winding space of the first data line 110 and the fourth pixel circuit can be balanced.
  • the arrangement space of the pixel circuit C4 reduces the load influence of other wirings on the first data line 110 while ensuring better driving performance.
  • FIG. 5 is a partially enlarged schematic diagram of a display panel provided according to yet another embodiment of the present invention, wherein FIG. 5 is, for example, a partially enlarged schematic diagram of the area Q1 in FIG. 1 .
  • a plurality of row units RX are provided in the third display area DA3, and in each row unit RX, the first pixel circuit C1 and/or the third pixel circuit C3 and/or the dummy pixel circuit are arranged according to a preset rule Arranged in sequence along the first direction X, and a plurality of row units RX are arranged along the second direction Y.
  • the plurality of row units RX includes at least one first row unit R1 adjacent to the fourth display area DA4.
  • Each first row unit R1 includes a plurality of second arrangement units U2 arranged along the first direction X.
  • Each second arrangement unit U2 includes P first preset pixel circuits and a second space K2, where P is a positive integer.
  • the first preset pixel circuit includes at least one of the first pixel circuit C1, the third pixel circuit C3, or the first dummy pixel circuit.
  • the P first preset pixel circuits are adjacently arranged in sequence along the first direction X
  • the second space K2 is located on one side of the P first preset pixel circuits along the first direction X.
  • each second arrangement unit U2 includes three first preset pixel circuits, some of the first preset circuits in the second arrangement unit U2 are the first pixel circuit C1, and some of the second The first preset circuit in the arrangement unit U2 is the third pixel circuit C3. Due to the existence of the second space K2 in the third display area DA3, the first data line 110 can also pass through the second space K2, further increasing the wiring space of the first data line 110, thereby reducing the display time of the first data line 110. The overlapping area of the orthographic projection on the surface and the orthographic projection of the connection line CL on the display surface.
  • the first data line 110 is arranged through the second interval space K, that is, the first sub-data line 111 in the first data line 110 can be at least partially arranged in the second interval space K, and the first data line can be increased.
  • the distance between the line 110 and the data line electrically connected to the third pixel circuit C3 located in the third display area D3 reduces coupling crosstalk between adjacent data signal lines and improves the display effect of the display panel.
  • the second compartment K2 communicates with the first compartment K1, so that the second compartment K2 and the first compartment K1 are connected as a strip-shaped wiring space, which is convenient for the first The wiring of the data lines 110 in the second space K2 and the first space K1 .
  • the length of the second interval space K2 along the first direction X is equal to 0.5 to 3 times the length of the first pixel circuit C1 along the first direction X.
  • the length of the second interval space K2 along the first direction X is 0.5 times the length of a single first pixel circuit C1 along the first direction X.
  • the length of the second interval space K2 along the first direction X is three times the length of a single first pixel circuit C1 along the first direction X.
  • the length of the second space K2 along the first direction X When the length of the second space K2 along the first direction X is too large, it will squeeze the layout space of the first pixel circuit C1 and the third pixel circuit C3, reducing the number of pixels in the first display area DA1 and the third display area DA3. Density, which is not conducive to realizing the drive of high pixel density display panel.
  • the length of the second spacing space K2 along the first direction X to 0.5 to 3 times the length of a single first pixel circuit C1 along the first direction X, it is possible to balance the winding space of the first data line 110 and the first
  • the arrangement space of the pixel circuit C1 and the third pixel circuit C3 can reduce the load influence of other wirings on the first data line 110 while ensuring better driving performance.
  • the length of the second spacing space K2 along the first direction X is equivalent to the length of the first spacing space K1 along the first direction X, and the second spacing space K2 communicates with the first spacing space K1, it is convenient to form regular wiring
  • the space is convenient for accommodating more winding structures of the first data lines 110 .
  • FIG. 6 is a partially enlarged schematic diagram of a display panel provided according to yet another embodiment of the present invention, wherein FIG. 6 is, for example, a partially enlarged schematic diagram of the area Q1 in FIG. 1 .
  • the plurality of row units RX further includes at least one second row unit R2, and the second row unit R2 is located on a side of the first row unit R1 away from the fourth display area DA4.
  • each second row unit R2 a plurality of second preset pixel circuits are adjacently arranged in sequence along the first direction X, and the second preset pixel circuits include the first pixel circuit C1, the third pixel circuit C3, or the second dummy pixel circuit At least one of the pixel circuits.
  • the second preset pixel circuit in each second row unit R2 includes the first pixel circuit C1 , the third pixel circuit C3 and the second dummy pixel circuit CD2 at the same time.
  • the first row unit R1 can be obtained by selectively removing part of the pixel circuits from the original structure of the display panel, and the second row unit R2 does not need to be screened to remove pixel circuits.
  • the display panel 100 still includes some second
  • the process of screening pixel circuits to be removed can be omitted, thereby improving layout design efficiency.
  • each third display area DA3 the number of first row units R1 is equal to the number of fourth display area DA4 adjacent to the third display area DA3, and each first row unit R1 is adjacent to a corresponding fourth display area DA4.
  • a fourth display area DA4 is provided on one side of the third display area DA3 along the second direction, that is, for the third display area DA3, the fourth display area adjacent to it If the number of DA4 is one, then the third display area DA3 includes a first row unit R1, and the first row unit R1 is arranged adjacent to the corresponding fourth display area DA4.
  • fourth display areas DA4 are provided on both sides of the third display area DA3 along the second direction, that is, for the third display area DA3, the number of adjacent fourth display areas DA4 is If there are two, the third display area DA3 includes two first row units R1, and each first row unit R1 is correspondingly arranged adjacent to a fourth display area DA4.
  • FIG. 7 is a partially enlarged schematic diagram of a display panel provided according to yet another embodiment of the present invention, wherein FIG. 7 is, for example, a partially enlarged schematic diagram of the area Q1 in FIG. 1 .
  • FIG. 8 is a schematic structural diagram with the light emitting element in FIG. 7 hidden.
  • each first data line 110 includes a first sub-data line 111 , a second sub-data line 112 and a third sub-data line 113 .
  • the first sub-data lines 111 extend in the third display area DA3 along the second direction Y, and are electrically connected to a plurality of first pixel circuits C1.
  • the second sub-data line 112 extends in the second display area DA2 along the second direction Y, and is electrically connected to a plurality of second pixel circuits C2.
  • the third sub-data lines 113 pass through the fourth display area DA4 and electrically connect the first sub-data lines 111 and the second sub-data lines 112 , wherein at least one third sub-data line 113 passes through the first interval space K1 .
  • a first row unit R1 adjacent to the fourth display area DA4 includes opposite first sides E1 and second sides E2, the first side E1 facing the fourth display area DA4.
  • all the third sub-data lines 113 electrically connected to all the second sub-data lines 112 in the same fourth display area DA4 are located in the first row unit R1 adjacent to the fourth display area DA4.
  • FIG. 9 is a partially enlarged schematic diagram of a display panel provided according to yet another embodiment of the present invention, wherein FIG. 9 is, for example, a partially enlarged schematic diagram of the area Q1 in FIG. 1 .
  • FIG. 10 is a schematic structural diagram with the light emitting element in FIG. 9 hidden.
  • the third sub-data line 113 is electrically connected to the first sub-data line 111 through the first connection point D1, wherein the first connection point D1 to which at least one third sub-data line 113 is connected is located on the second side E2.
  • the inside of the three display areas DA3 is close to and away from the fourth display area DA4, which reduces the occupation of the third sub-data line 113 to the fourth display area DA4 to a certain extent, facilitates the reduction of the width of the fourth display area DA4, and improves the second display area as a normal display area.
  • a first boundary line F1 is set between each third display area DA3 and the first display area DA1.
  • the plurality of first pixel circuits C1 corresponding to the plurality of first light-emitting elements P1 arranged in sequence along the direction away from the first boundary line F1 are displayed in the third display area DA3.
  • the areas DA3 are sequentially arranged in a direction away from the first dividing line F1.
  • At least one third sub-data line 113 corresponding to the first sub-data line 111 farthest from the first display area DA1 extends to the second side E2 .
  • At least one third sub-data line 113 extends in a stair shape.
  • the third sub-data line 113 extending in a ladder shape can prevent its orthographic projection on the display surface from overlapping with the orthographic projection of the connection line CL on the display surface, and avoid the load impact of the connection line CL on the third sub-data line 113, Therefore, the impact of the connection line CL on the load of the first data line 110 is reduced.
  • FIG. 9 it is illustrated by taking a plurality of row units RX including a plurality of second row units R2 and at least one first row unit R1 adjacent to the fourth display area DA4.
  • the plurality of row units RX may be arranged in other manners, for example, the plurality of row units RX includes a plurality of first row units R1 but does not include the second row unit R2.
  • connection line CL is electrically connected to the first pixel circuit C1 through the second connection point D2 .
  • first row of cells R1 at least one second connection point D2 is located on the second side E2.
  • each second connection point D2 in the first row unit R1 adjacent to the fourth display area DA4 is located on the second side E2.
  • a part of the second connection points D2 may be located on the second side E2, and another part of the second connection points D2 may be located on the first side E1.
  • connection line CL is connected to the pixel circuit from the second side E2, and the connection line CL can be arranged on the second side E2, thereby reducing the connection line CL on the first side E1.
  • the space is occupied, thereby facilitating the arrangement of part of the third sub-data lines 113 on the first side E1.
  • each third display area DA3 the number of the fourth display area DA4 adjacent to the third display area DA3 is one.
  • each second connection point D2 in the first row unit R1 adjacent to the fourth display area DA4 is located on the second side E2, so that a plurality of connection lines connected to the first row unit R1 CLs are all located on a side of the first row unit R1 away from the fourth display area DA4 .
  • a plurality of connection lines CL connected to each remaining row unit RX are all located on the side of the row unit RX facing the fourth display area DA4 .
  • connection lines CL connected to the row units RX are located on the side of the row unit RX away from the fourth display area DA4 .
  • the plurality of connection lines CL connected to each row unit RX in the third display area DA3 are all located on the side of the row unit RX away from the fourth display area DA4, thereby avoiding the existence of gaps between adjacent row units RX.
  • the connection lines CL corresponding to the two row units RX need to be arranged between each row unit RX, so that the spacing between the row units RX is more balanced.
  • At least one first pixel circuit C1 in the first row unit R1 is mirrored with at least one first pixel circuit C1 in the remaining row units RX about a preset axis of symmetry, and the preset axis of symmetry is parallel to the first Direction X.
  • the preset symmetry axis is mirrored, and the preset symmetry axis is parallel to the first direction X.
  • the second connection point D2 is located on the lower side of the first pixel circuit C1 along the second direction Y, then in the first pixel circuit C1 of the first row unit R1 , the second connection point D2 is located on the upper side of the first pixel circuit C1 along the second direction Y.
  • the at least one first pixel circuit C1 in the first row unit R1 is equivalent to being set upside down along the second direction X, so as to facilitate the setting of its corresponding second connection point D2 On the side away from the fourth display area DA4 , the possibility that the connection line CL crosses the first data line 110 is reduced.
  • FIG. 11 is a partially enlarged schematic diagram of a display panel provided according to yet another embodiment of the present invention, wherein FIG. 11 is, for example, a partially enlarged schematic diagram of the area Q1 in FIG. 1 .
  • FIG. 12 is a schematic structural view of the light-emitting element in FIG. 11 hidden.
  • at least one third sub-data line 113 corresponding to at least one first sub-data line 111 closest to the first display area DA1 extends to the second side E2 and passes through the corresponding first sub-data line.
  • 111 is the second space K2 on the side away from the first display area DA1.
  • the third sub-data lines 113 bypasses the second space K2 on the side away from the first display area DA1, which can reduce the length of the third sub-data lines 113 of the plurality of first data lines 110 The difference is to perform corresponding load compensation on the plurality of first data lines 110 respectively, so as to improve the load consistency of the plurality of first data lines 110 , thereby improving the uniformity of display brightness.
  • FIG. 12 related to the embodiment take a plurality of row units RX including a plurality of second row units R2 and at least one first row unit R1 adjacent to the fourth display area DA4 as an example for illustration, in some other
  • the plurality of row units RX may be arranged in other manners, for example, the plurality of row units RX includes a plurality of first row units R1 but does not include the second row unit R2.
  • An embodiment of the present invention also provides a display device, which includes the display panel 100 according to any one of the above-mentioned embodiments of the present invention.
  • the display panel 100 includes a first display area DA1 , a second display area DA2 , a third display area DA3 and a fourth display area DA4 .
  • the third display area DA3 is located on at least one side of the first display area DA1 along the first direction X.
  • the second display area DA2 at least partially surrounds the first display area DA1 and the third display area DA3.
  • the first display area DA1 is multiplexed as a photosensitive element integration area.
  • the fourth display area DA4 is located between the third display area DA3 and the second display area DA2 and between the first display area DA1 and the second display area DA2 along the second direction Y, and the second direction Y crosses the first direction X.
  • the display panel 100 further includes a first pixel circuit C1 and a first light emitting element P1 electrically connected to each other, a second pixel circuit C2 and a second light emitting element P2 electrically connected to each other, a third pixel circuit C3 and a third light emitting element electrically connected to each other.
  • the element P3, the fourth pixel circuit C4 and the fourth light emitting element P4 are electrically connected to each other.
  • the first light-emitting element P1 is located in the first display area DA1, the first pixel circuit C1 is located in the third display area DA3, and each first pixel circuit C1 is electrically connected to at least one first light-emitting element P1 through a corresponding connection line CL.
  • the second pixel circuit C2 and the second light emitting element P2 electrically connected to each other are located in the second display area DA2.
  • the third pixel circuit C3 and the third light emitting element P3 electrically connected to each other are located in the third display area DA3.
  • the fourth pixel circuit C4 and the fourth light emitting element P4 electrically connected to each other are located in the fourth display area DA4.
  • the fourth pixel circuits C4 are arranged in at least one row in the fourth display area DA4.
  • Each row of fourth pixel circuits C4 includes at least one first arrangement unit U1 arranged along the first direction X.
  • Each first arrangement unit U1 includes N fourth pixel circuits C4 and a first space K1, where N is a positive integer.
  • the N fourth pixel circuits C4 are adjacently arranged in sequence along the first direction X, and the first space K1 is located on one side of the N fourth pixel circuits C4 along the first direction X.
  • the display panel 100 also includes a plurality of first data lines 110 .
  • Each first data line 110 is electrically connected to at least one first pixel circuit C1 and at least one second pixel circuit C2. Wherein, at least one first data line 110 passes through the first space K1, so that the orthographic projections of the plurality of first data lines 110 on the display surface do not overlap with the orthographic projections of the connection line CL on the display surface.
  • the fourth pixel circuits C4 are arranged in at least one row in the fourth display area DA4, and each row of fourth pixel circuits C4 includes a first arrangement unit U1, each The first arranging unit U1 includes a first interval space K1 , that is, removing at least part of the pixel circuits in the fourth display area DA4 that do not need to be connected to light-emitting elements, so as to obtain the first interval space K1 .
  • the first interval space K1 can be used as a wiring space for the first data line 110, at least one first data line 110 passes through the first interval space K1, thereby reducing or even avoiding the passage of the first data line 110 through the first display area DA1, so that multiple first data lines 110 pass through the first display area DA1.
  • the orthographic projection of a data line 110 on the display surface does not overlap with the orthographic projection of the connection line CL on the display surface, so as to prevent the connection line CL from exerting a load on the first data line 110 .
  • the difference in load of the first data line 110 between the part of the third display area DA3 and the part of the second display area DA2 is reduced, so that the luminance of the first light-emitting element P1 and the second light-emitting element P2 tends to be closer to Similarly, the uniformity of display brightness of the display panel 100 and the display device is improved.

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Abstract

种显示面板（100）及显示装置，提高了显示面板（100）显示亮度的均一'性。其中，显示面板（100）包括：第一显示区（DA1）、第二显示区（DA2）、第三显示区（DA3）以及第四显示区（DA4）;第一像素电路（C1）和第一发光元件（P1）;第二像素电路（C2）和第二发光元件（P2）；第三像素电路（C3）和第三发光元件（P3）；第四像素电路（C4）和第四发光元件（P4），每行第四像素电路（C4）包括沿第一方向（X）排列的至少一个第一排布单元（U1），每个第一排布单元（U1）包括N个第四像素电路（C4）以及第一间隔空间（Kl），N为正整数，其中，N个第四像素电路（C4）沿第一方向（X）依次相邻设置，第一间隔空间（K1）沿第一方向（X）位于N个第四像素电路（C4）的一侧；以及多条第一数据线（110），至少一条第一数据线（110）经过第一间隔空间（K1)。

Description

显示面板及显示装置 技术领域
本发明涉及显示领域，具体涉及一种显示面板及显示装置。
背景技术
在包括显示面板的电子设备中，对具有更优视觉体验的高屏占比的追求已成为当前显示技术发展的潮流之一。
以手机、平板电脑等为例，在目前的全面屏方案中，显示面板至少部分显示区复用为感光元件集成区。此时，诸如前置摄像头、红外感应元件的感光元件可以设置在显示面板的感光元件集成区的背部，光线能够穿过感光元件集成区到达感光元件，实现前置摄像、红外感应等相应的功能。
在上述方案中，复用为感光元件集成区的一部分显示区的发光元件亮度通常小于其它显示区的发光元件的亮度，产生亮度显示不均现象。
发明内容
本发明提供一种显示面板及显示装置，提高显示亮度的均一性。
一方面，本发明实施例提供一种显示面板，其包括：第一显示区、第二显示区、第三显示区以及第四显示区，第三显示区沿第一方向位于第一显示区的至少一侧，第二显示区至少部分包围第一显示区和第三显示区，第一显示区复用为感光元件集成区，第四显示区沿第二方向位于第三显示区与第二显示区之间以及第一显示区与第二显示区之间，第二方向与第一方向交叉；相互电连接的第一像素电路和第一发光元件，第一发光元件位于第一显示区，第一像素电路位于第三显示区；相互电连接的第二像素电路和第二发光元件， 位于第二显示区；相互电连接的第三像素电路和第三发光元件，位于第三显示区；相互电连接的第四像素电路和第四发光元件，位于第四显示区，第四像素电路在第四显示区排布为至少一行，每行第四像素电路包括沿第一方向排列的至少一个第一排布单元，每个第一排布单元包括N个第四像素电路以及第一间隔空间，N为正整数，其中，N个第四像素电路沿第一方向依次相邻设置，第一间隔空间沿第一方向位于N个第四像素电路的一侧；以及多条第一数据线，每条第一数据线与至少一个第一像素电路以及至少一个第二像素电路电连接，其中，至少一条第一数据线经过第一间隔空间。
另一方面，本发明实施例提供一种显示装置，其包括根据本发明一方面的前述任一实施方式的显示面板。
根据本发明实施例的显示面板及显示装置，第四像素电路在第四显示区排布为至少一行，每行第四像素电路包括第一排布单元，每个第一排布单元包括第一间隔空间，即去掉第四显示区中至少部分无需连接发光元件的像素电路，从而空余得到第一间隔空间。第一间隔空间可以作为第一数据线的绕线空间，至少一条第一数据线经过第一间隔空间，从而减少甚至避免第一数据线经过第一显示区，减少多条第一数据线在显示面上的正投影与连接至第一显示区的布线在显示面上的正投影的交叠，减弱这些布线对第一数据线产生负载影响。此时，第一数据线在第三显示区的部分与在第二显示区的部分之间负载差异减小，使得第一发光元件与第二发光元件的发光亮度更趋于相同，提高了显示面板及显示装置显示亮度的均一性。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1是根据本发明一种实施例提供的显示面板的俯视示意图；
图2根据本发明一种实施例提供的显示面板的局部放大示意图；
图3根据本发明另一种实施例提供的显示面板的局部放大示意图；
图4根据本发明一种实施例提供的显示面板中第四显示区的局部放大示意图；
图5根据本发明又一种实施例提供的显示面板的局部放大示意图；
图6根据本发明又一种实施例提供的显示面板的局部放大示意图；
图7根据本发明又一种实施例提供的显示面板的局部放大示意图；
图8是将图7中发光元件隐去后的结构示意图；
图9根据本发明又一种实施例提供的显示面板的局部放大示意图；
图10是将图9中发光元件隐去后的结构示意图；
图11根据本发明又一种实施例提供的显示面板的局部放大示意图；
图12是将图11中发光元件隐去后的结构示意图。
具体实施方式
下面将详细描述本发明的各个方面的特征和示例性实施例，为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本发明进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本发明，并不被配置为限定本发明。对于本领域技术人员来说，本发明可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本发明的示例来提供对本发明更好的理解。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或 者顺序。
应当理解，在描述部件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将部件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
本发明实施例提供一种显示面板，图1是根据本发明一种实施例提供的显示面板的俯视示意图，图2根据本发明一种实施例提供的显示面板的局部放大示意图，其中图2例如是将图1中Q1区域局部放大示意。
显示面板100包括第一显示区DA1、第二显示区DA2、第三显示区DA3以及第四显示区DA4。第三显示区DA3沿第一方向X位于第一显示区DA1的至少一侧。第二显示区DA2至少部分包围第一显示区DA1和第三显示区DA3。第一显示区DA1复用为感光元件集成区。第四显示区DA4沿第二方向Y位于第三显示区DA3与第二显示区DA2之间以及第一显示区DA1与第二显示区DA2之间，第二方向Y与第一方向X交叉。在一些实施例中，显示面板100还包括围绕第一显示区DA1、第二显示区DA2、第三显示区DA3以及第四显示区DA4的非显示区(图中未示出)。
显示面板100还包括相互电连接的第一像素电路C1和第一发光元件P1、相互电连接的第二像素电路C2和第二发光元件P2、相互电连接的第三像素电路C3和第三发光元件P3、相互电连接的第四像素电路C4和第四发光元件P4。
第一发光元件P1位于第一显示区DA1，第一像素电路C1位于第三显示区DA3。在一些实施例中，每个第一像素电路C1通过对应的连接线CL与至少一个第一发光元件P1电连接。相互电连接的第二像素电路C2和第二发光元件P2位于第二显示区DA2。相互电连接的第三像素电路C3和第三发光元件P3位于第三显示区DA3。相互电连接的第四像素电路C4和第四发光元件P4，位于第四显示 区DA4。在一些实施例中，在第三显示区DA3中，除排布有第一像素电路C1、第三像素电路C3外，还可以排布有虚拟像素电路CD，虚拟像素电路CD可以均衡不同显示区的刻蚀图案密度，提升刻蚀均一性或者显示均一。在一些实施例中，第三显示区DA3中也可以不设置虚拟像素电路CD。可以理解的，为了保障第一显示区DA1能正常显示画面，第一显示区DA1中的发光元件需要满足一定数量，因此连接线CL的数量较多，且在第一显示区DA1和第三显示区DA3相邻位置处会设置的比较密集集中。
第四像素电路C4在第四显示区DA4排布为至少一行。每行第四像素电路C4包括沿第一方向X排列的至少一个第一排布单元U1。每个第一排布单元U1包括N个第四像素电路C4以及第一间隔空间K1，N为正整数。其中，N个第四像素电路C4沿第一方向X依次相邻设置，第一间隔空间K1沿第一方向X位于N个第四像素电路C4的一侧。
显示面板100还包括多条第一数据线110。每条第一数据线110与至少一个第一像素电路C1以及至少一个第二像素电路C2电连接。其中，至少一条第一数据线110经过第一间隔空间K1，使得多条第一数据线110在显示面上的正投影与连接线CL在显示面上的正投影无交叠。
根据本发明实施例的显示面板100，第四像素电路C4在第四显示区DA4排布为至少一行，每行第四像素电路C4包括第一排布单元U1，每个第一排布单元U1包括第一间隔空间K1，即去掉第四显示区DA4中至少部分无需连接发光元件的像素电路，从而空余得到第一间隔空间K1。第一间隔空间K1可以作为第一数据线110的绕线空间，至少一条第一数据线110经过第一间隔空间K1，从而减少甚至避免第一数据线110经过第一显示区DA1，减少多条第一数据线110在显示面上的正投影与连接至第一显示区的布线(例如连接线CL)在显示面上的正投影的交叠，避免密集且与第一数据线110交叠的布线对第一数据线110产生负载影响，影响数据信号。此时， 第一数据线110在第三显示区DA3的部分与在第二显示区DA2的部分之间负载差异大大减小，同时也能减小不同显示区之间的数据线的负载差异，降低诸如连接线CL的布线对第一数据线110耦合串扰的影响，使得第一发光元件P1与第二发光元件P2的发光亮度更趋于相同，提高了显示面板100显示亮度的均一性。一般情况下，为了使不同区域的发光元件亮度匹配，会提高亮度较低的发光元件对应的驱动电流，但是提高驱动电流会降低发光元件的寿命，从而影响整个显示面板的使用寿命以及显示效果，此时，通过改变显示面板结构设计，可以减小第一数据线110在第三显示区DA3的部分与在第二显示区DA2的部分之间的负载差异，减小第一发光元件P1与第二发光元件P2之间的发光亮度差异，提高显示面板100的显示亮度均一性，同时还可以改善第一发光元件P1点寿命问题，提高显示面板100的使用寿命。
在一些实施例中，第四像素电路C4在第四显示区DA4排布为一行，在其它一些实施例中，第四像素电路C4可以在第四显示区DA4排布为两行、三行等其它数量的行。
每行第四像素电路C4包括至少一个第一排布单元U1。每个第一排布单元U1包括第一间隔空间K1。在一些实施例中，每行第四像素电路C4中，第一排布单元U1的数量为多个，使得第一间隔空间K1的数量也为多个。
图3根据本发明另一种实施例提供的显示面板的局部放大示意图，其中图3例如是将图1中Q1区域局部放大示意。在另一种实施例中，每行第四像素电路C4包括一个第一排布单元U1，使得每行第四像素电路C4中第一间隔空间K1的数量也为一个。在其它一些实施例中，每行第四像素电路C4中第一间隔空间K1的数量可以是两个、三个等其它任意数量。
在一些实施例中，每行第四像素电路C4中的至少一个第四像素电路C4可以替换为不用于实现发光元件发光的虚拟像素电路。
如图2或图3，在一些实施例中，每个第一像素电路C1通过对 应的连接线CL与至少一个第一发光元件P1电连接。每条第一数据线110包括第一子数据线111、第二子数据线112以及第三子数据线113，第一子数据线111沿第二方向Y延伸于第三显示区DA3，并与至少一个第一像素电路C1电连接，第二子数据线112沿第二方向Y延伸于第二显示区DA2，并与多个第二像素电路C2电连接，第三子数据线113经过第四显示区DA4，并将第一子数据线111与第二子数据线112电连接，其中至少一条第三子数据线113经过第一间隔空间K1。第三子数据线113将第一子数据线111与第二子数据线112电连接，使得第一像素电路C1与第二像素电路C2能够经由同一第一数据线110供应数据信号，延伸于第四显示区DA4的第三子数据线113经过第一间隔空间K1，避免第三子数据线113在显示面上的正投影与连接线CL在显示面上的正投影产生交叠，避免连接线CL对第一数据线110产生负载影响，便于提高显示面板100显示亮度的均一性。需要说明的是，考虑到IC以及显示画面匹配性的因素，与同一条第一数据线110电连接的第一像素电路C1和第二像素电路C2中，在第二方向Y上，至少部分与第一像素电路C1电连接的第一发光元件P1和第二像素电路C2电连接的第二发光元件P2位于同一列。
图4根据本发明一种实施例提供的显示面板中第四显示区的局部放大示意图。在一些实施例中，显示面板100包括位于第四显示区DA4的多个第一像素单元PU1。每个第一像素单元PU1包括M个第四发光元件P4，其中，N为M的正整数倍。例如，每个第一像素单元PU1包括三个第四发光元件P4，可以分别为红色第四发光元件P4、绿色第四发光元件P4以及蓝色第四发光元件P4。每个第一排布单元U1包括三个第四像素电路C4。在其它一些实施例中，当每个第一像素单元PU1包括三个第四发光元件P4时，每个第一排布单元U1可以包括六个、九个等其它数量的第四像素电路C4。本发明实施例的显示面板100中，第一排布单元U1的第一间隔空间K1，可以是在像素电路无间隔排布的结构基础上，去掉第四显示区 DA4中至少部分无需连接发光元件的像素电路，从而空余得到第一间隔空间K1。当第一排布单元U1中依次相邻设置的第四像素电路C4的数量N为M的正整数倍时，形成第一排布单元U1时，可以将与第一像素单元PU1邻近的第四像素电路C4保留，去除其余像素电路，使得第四像素电路C4与对应第四发光元件P4的物理位置更近，减短第四像素电路C4与第四发光元件P4之间的导线对空间的占用，从而能够空余面积更大且形状更规则的第一间隔空间K1。
可选地，第一间隔空间K1沿第一方向X的长度，等于第四像素电路C4沿第一方向X的长度的0.5倍至3倍。例如在一个实施例中，第一间隔空间K1沿第一方向X的长度为单个第四像素电路C4沿第一方向X的长度的0.5倍。例如在另一个实施例中，第一间隔空间K1沿第一方向X的长度为单个第四像素电路C4沿第一方向X的长度的3倍。当第一间隔空间K1沿第一方向X的长度过小时，无法形成有效的布线容纳空间，从而难以将第一数据线110配置为经过第一间隔空间K1。当第一间隔空间K1沿第一方向X的长度过大时，将会挤压第四像素电路C4的布置空间，使得第四显示区DA4中第四像素电路C4数量过少，不利于实现高像素密度显示面板的驱动。通过将第一间隔空间K1沿第一方向X的长度设置为单个第四像素电路C4沿第一方向X的长度的0.5倍至3倍，能够平衡第一数据线110的绕线空间和第四像素电路C4的布置空间，在保证具有较佳驱动性能的同时减小其它布线对第一数据线110的负载影响。
图5根据本发明又一种实施例提供的显示面板的局部放大示意图，其中图5例如是将图1中Q1区域局部放大示意。在一些实施例中，第三显示区DA3中设有多个行单元RX，每个行单元RX中，第一像素电路C1和/或第三像素电路C3和/或虚拟像素电路以预设规则沿第一方向X依次排布，多个行单元RX沿第二方向Y排列。
多个行单元RX包括与第四显示区DA4相邻的至少一个第一行单元R1。每个第一行单元R1包括沿第一方向X排列的多个第二排布单元U2。每个第二排布单元U2包括P个第一预设像素电路以及 第二间隔空间K2，P为正整数。第一预设像素电路包括第一像素电路C1、第三像素电路C3、或第一虚拟像素电路中的至少一者。其中，P个第一预设像素电路沿第一方向X依次相邻设置，第二间隔空间K2沿第一方向X位于P个第一预设像素电路的一侧。例如在本实施例中，每个第二排布单元U2包括三个第一预设像素电路，有的第二排布单元U2中第一预设电路为第一像素电路C1，有的第二排布单元U2中第一预设电路为第三像素电路C3。由于第三显示区DA3中存在第二间隔空间K2，使得第一数据线110也可以经过第二间隔空间K2，进一步增大第一数据线110的布线空间，从而减少第一数据线110在显示面上的正投影与连接线CL在显示面上的正投影的交叠面积。同时，将第一数据线110经过第二间隔空间K设置，即，可以将第一数据线110中的第一子数据线111至少部分设在第二间隔空间K中，可以增大第一数据线110与位于第三显示区D3中的第三像素电路C3电连接的数据线之间的距离，降低相邻数据信号线之间的耦合串扰，提高显示面板的显示效果。
在一些实施例中，沿第二方向Y，至少部分第二间隔空间K2与第一间隔空间K1连通，使得第二间隔空间K2与第一间隔空间K1连接为带状的布线空间，便于第一数据线110在第二间隔空间K2与第一间隔空间K1的布线。
可选地，第二间隔空间K2沿第一方向X的长度，等于第一像素电路C1沿第一方向X的长度的0.5倍至3倍。例如在一个实施例中，第二间隔空间K2沿第一方向X的长度为单个第一像素电路C1沿第一方向X的长度的0.5倍。例如在另一个实施例中，第二间隔空间K2沿第一方向X的长度为单个第一像素电路C1沿第一方向X的长度的3倍。当第二间隔空间K2沿第一方向X的长度过小时，无法形成有效的布线容纳空间，从而难以将第一数据线110配置为经过第二间隔空间K2。当第二间隔空间K2沿第一方向X的长度过大时，将会挤压第一像素电路C1以及第三像素电路C3的布置空间，降低第一显示区DA1、第三显示区DA3的像素密度，不利于实现高 像素密度显示面板的驱动。通过将第二间隔空间K2沿第一方向X的长度设置为单个第一像素电路C1沿第一方向X的长度的0.5倍至3倍，能够平衡第一数据线110的绕线空间和第一像素电路C1以及第三像素电路C3的布置空间，在保证具有较佳驱动性能的同时减小其它布线对第一数据线110的负载影响。另外，当第二间隔空间K2沿第一方向X的长度与第一间隔空间K1沿第一方向X的长度相当，且第二间隔空间K2与第一间隔空间K1连通时，便于形成规则的布线空间，便于容纳更多的第一数据线110的绕线结构。
图6根据本发明又一种实施例提供的显示面板的局部放大示意图，其中图6例如是将图1中Q1区域局部放大示意。在一些实施例中，多个行单元RX还包括至少一个第二行单元R2，第二行单元R2位于第一行单元R1背离第四显示区DA4的一侧。
每个第二行单元R2中，多个第二预设像素电路沿第一方向X依次相邻设置，第二预设像素电路包括第一像素电路C1、第三像素电路C3、或第二虚拟像素电路中的至少一者。例如在本实施例中，每个第二行单元R2中的第二预设像素电路同时包括第一像素电路C1、第三像素电路C3以及第二虚拟像素电路CD2。在上述实施例中，第一行单元R1可以是在显示面板原有结构上选择性去掉部分像素电路得到，而第二行单元R2无需进行筛选去除像素电路，当显示面板100仍然包括一些第二行单元R2时，可以省去筛选待去除的像素电路的过程，提高版图设计效率。
在一些实施例中，其特征在于，每个第三显示区DA3中，第一行单元R1的数量等于与第三显示区DA3相邻的第四显示区DA4的数量，每个第一行单元R1与对应一个第四显示区DA4相邻。例如在图6涉及的实施例中，第三显示区DA3沿第二方向的其中一侧设有一个第四显示区DA4，即对于该第三显示区DA3，与之相邻的第四显示区DA4的数量为一个，则该第三显示区DA3包括一个第一行单元R1，且该第一行单元R1与对应第四显示区DA4相邻设置。
在其它一些实施例中，第三显示区DA3沿第二方向的两侧均设 有第四显示区DA4，即对于该第三显示区DA3，与之相邻的第四显示区DA4的数量为两个，则该第三显示区DA3包括两个第一行单元R1，每个第一行单元R1对应相邻一个第四显示区DA4设置。
图7根据本发明又一种实施例提供的显示面板的局部放大示意图，其中图7例如是将图1中Q1区域局部放大示意。图8是将图7中发光元件隐去后的结构示意图。在一些实施例中，每条第一数据线110包括第一子数据线111、第二子数据线112以及第三子数据线113。第一子数据线111沿第二方向Y延伸于第三显示区DA3，并与多个第一像素电路C1电连接。第二子数据线112沿第二方向Y延伸于第二显示区DA2，并与多个第二像素电路C2电连接。第三子数据线113经过第四显示区DA4，并将第一子数据线111与第二子数据线112电连接，其中至少一条第三子数据线113经过第一间隔空间K1。与第四显示区DA4相邻的一个第一行单元R1包括相对的第一侧E1和第二侧E2，第一侧E1朝向第四显示区DA4。
在本实施例中，同一第四显示区DA4中全部第二子数据线112所电连接的全部第三子数据线113，均位于与第四显示区DA4相邻的第一行单元R1的第一侧E1。
图9根据本发明又一种实施例提供的显示面板的局部放大示意图，其中图9例如是将图1中Q1区域局部放大示意。图10是将图9中发光元件隐去后的结构示意图。在一些实施例中，第三子数据线113通过第一连接点D1与第一子数据线111电连接，其中，至少一条第三子数据线113所连接的第一连接点D1位于第二侧E2。此时，显示面板100的至少一条第三子数据线113连接至第一行单元R1远离第四显示区DA4的一侧，使得至少一条第三子数据线113对应的第一连接点D1向第三显示区DA3内部靠拢而远离第四显示区DA4，一定程度减少第三子数据线113对第四显示区DA4的占用，便于缩减第四显示区DA4的宽度，提高作为正常显示区的第二显示区DA2的占比。
在一些实施例中，每个第三显示区DA3与第一显示区DA1之 间设有第一分界线F1。在每个第三显示区DA3与第一显示区DA1之间，沿远离第一分界线F1方向依次排列的多个第一发光元件P1所对应的多个第一像素电路C1，在第三显示区DA3沿远离第一分界线F1的方向依次排列。
如图9，在一些实施例中，最远离第一显示区DA1的第一子数据线111所对应的至少一条第三子数据线113，延伸至第二侧E2。至少一条第三子数据线113呈阶梯状延伸。呈阶梯状延伸的第三子数据线113可以避免其在显示面上的正投影与连接线CL在显示面上的正投影交叠，避免连接线CL对第三子数据线113产生负载影响，从而降低连接线CL对第一数据线110负载的影响。
在图9涉及实施例中，以多个行单元RX包括多个第二行单元R2以及与第四显示区DA4相邻的至少一个第一行单元R1为例进行说明，在其它一些实施例中，多个行单元RX可以是其它设置方式，例如，多个行单元RX包括多个第一行单元R1而不包括第二行单元R2。
如图9，在一些实施例中，连接线CL通过第二连接点D2与第一像素电路C1电连接。在第一行单元R1中，至少一个第二连接点D2位于第二侧E2。例如本实施例中，与第四显示区DA4相邻的第一行单元R1中的各第二连接点D2均位于第二侧E2。在其它一些实施例中，与第四显示区DA4相邻的第一行单元R1中，可以一部分第二连接点D2位于第二侧E2，另一部分第二连接点D2位于第一侧E1。当至少一个第二连接点D2位于第二侧E2时，连接线CL从第二侧E2接入像素电路，连接线CL可以布置在第二侧E2，从而减少连接线CL在第一侧E1的空间占用，从而便于部分第三子数据线113在第一侧E1的布置。
在本实施例中，对于每个第三显示区DA3，与该第三显示区DA3相邻的第四显示区DA4的数量为单个。第三显示区DA3中，与第四显示区DA4相邻的第一行单元R1中的各第二连接点D2均位于第二侧E2，使得与该第一行单元R1连接的多个连接线CL均位于该第 一行单元R1的远离第四显示区DA4的一侧。在本实施例中，第三显示区DA3中，与剩余的每个行单元RX连接的多个连接线CL均位于该行单元RX的朝向第四显示区DA4的一侧。在其它一些实施例中，在第三显示区DA3中，剩余的行单元RX中，至少部分行单元RX连接的多个连接线CL位于该行单元RX的远离第四显示区DA4的一侧。在一个示例中，第三显示区DA3中的每个行单元RX连接的多个连接线CL均位于该行单元RX的远离第四显示区DA4的一侧，从而避免存在相邻行单元RX之间需要布置两个行单元RX对应的连接线CL，使得各行单元RX之间的间距更均衡。
在一些实施例中，第一行单元R1中的至少一个第一像素电路C1，与剩余行单元RX中的至少一个第一像素电路C1关于预设对称轴镜像，预设对称轴平行于第一方向X。例如本实施例中，多个行单元RX第一行单元R1和第二行单元R2，其中第一行单元R1中的第一像素电路C1与第二行单元R2中的第一像素电路C1关于预设对称轴镜像，预设对称轴平行于第一方向X。例如，在第二行单元R2的第一像素电路C1中，第二连接点D2位于第一像素电路C1沿第二方向Y的下侧，则在第一行单元R1的第一像素电路C1中，第二连接点D2位于第一像素电路C1沿第二方向Y的上侧。第一行单元R1中的至少一个第一像素电路C1与剩余行单元RX中的第一像素电路C1相比，相当于沿第二方向X倒置设置，便于将其对应的第二连接点D2设置在远离第四显示区DA4的一侧，降低连接线CL与第一数据线110交叉的可能。
图11根据本发明又一种实施例提供的显示面板的局部放大示意图，其中图11例如是将图1中Q1区域局部放大示意。图12是将图11中发光元件隐去后的结构示意图。在一些实施例中，最靠近第一显示区DA1的至少一条第一子数据线111所对应的至少一条第三子数据线113，延伸至第二侧E2，并经过位于对应第一子数据线111的远离第一显示区DA1一侧的第二间隔空间K2。在上述实施例中，至少部分第三子数据线113从远离第一显示区DA1一侧的第二间隔 空间K2绕过，能够缩小多条第一数据线110的第三子数据线113的长度差异，对多条第一数据线110分别进行对应的负载补偿，提高多条第一数据线110的负载一致性，进而提高显示亮度的均一性。
在图11、图12涉及实施例中，以多个行单元RX包括多个第二行单元R2以及与第四显示区DA4相邻的至少一个第一行单元R1为例进行说明，在其它一些实施例中，多个行单元RX可以是其它设置方式，例如，多个行单元RX包括多个第一行单元R1而不包括第二行单元R2。
本发明实施例还提供一种显示装置，其包括根据本发明上述任一实施方式的显示面板100。显示面板100包括第一显示区DA1、第二显示区DA2、第三显示区DA3以及第四显示区DA4。第三显示区DA3沿第一方向X位于第一显示区DA1的至少一侧。第二显示区DA2至少部分包围第一显示区DA1和第三显示区DA3。第一显示区DA1复用为感光元件集成区。第四显示区DA4沿第二方向Y位于第三显示区DA3与第二显示区DA2之间以及第一显示区DA1与第二显示区DA2之间，第二方向Y与第一方向X交叉。
显示面板100还包括相互电连接的第一像素电路C1和第一发光元件P1、相互电连接的第二像素电路C2和第二发光元件P2、相互电连接的第三像素电路C3和第三发光元件P3、相互电连接的第四像素电路C4和第四发光元件P4。
第一发光元件P1位于第一显示区DA1，第一像素电路C1位于第三显示区DA3，每个第一像素电路C1通过对应的连接线CL与至少一个第一发光元件P1电连接。相互电连接的第二像素电路C2和第二发光元件P2位于第二显示区DA2。相互电连接的第三像素电路C3和第三发光元件P3位于第三显示区DA3。相互电连接的第四像素电路C4和第四发光元件P4，位于第四显示区DA4。
第四像素电路C4在第四显示区DA4排布为至少一行。每行第四像素电路C4包括沿第一方向X排列的至少一个第一排布单元U1。每个第一排布单元U1包括N个第四像素电路C4以及第一间隔空间 K1，N为正整数。其中，N个第四像素电路C4沿第一方向X依次相邻设置，第一间隔空间K1沿第一方向X位于N个第四像素电路C4的一侧。
显示面板100还包括多条第一数据线110。每条第一数据线110与至少一个第一像素电路C1以及至少一个第二像素电路C2电连接。其中，至少一条第一数据线110经过第一间隔空间K1，使得多条第一数据线110在显示面上的正投影与连接线CL在显示面上的正投影无交叠。
根据本发明实施例的及显示装置，在显示面板100中，第四像素电路C4在第四显示区DA4排布为至少一行，每行第四像素电路C4包括第一排布单元U1，每个第一排布单元U1包括第一间隔空间K1，即去掉第四显示区DA4中至少部分无需连接发光元件的像素电路，从而空余得到第一间隔空间K1。第一间隔空间K1可以作为第一数据线110的接线空间，至少一条第一数据线110经过第一间隔空间K1，从而减少甚至避免第一数据线110经过第一显示区DA1，使得多条第一数据线110在显示面上的正投影与连接线CL在显示面上的正投影无交叠，避免连接线CL对第一数据线110产生负载影响。此时，第一数据线110在第三显示区DA3的部分与在第二显示区DA2的部分之间负载差异减小，使得第一发光元件P1与第二发光元件P2的发光亮度更趋于相同，提高了显示面板100及显示装置显示亮度的均一性。
依照本发明如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (18)

  1. 一种显示面板，其特征在于，包括：
    第一显示区、第二显示区、第三显示区以及第四显示区，所述第三显示区沿第一方向位于所述第一显示区的至少一侧，所述第二显示区至少部分包围所述第一显示区和所述第三显示区，所述第一显示区复用为感光元件集成区，所述第四显示区沿第二方向位于所述第三显示区与所述第二显示区之间以及所述第一显示区与所述第二显示区之间，所述第二方向与所述第一方向交叉；
    相互电连接的第一像素电路和第一发光元件，所述第一发光元件位于所述第一显示区，所述第一像素电路位于所述第三显示区；
    相互电连接的第二像素电路和第二发光元件，位于所述第二显示区；
    相互电连接的第三像素电路和第三发光元件，位于所述第三显示区；
    相互电连接的第四像素电路和第四发光元件，位于所述第四显示区，所述第四像素电路在所述第四显示区排布为至少一行，每行所述第四像素电路包括沿所述第一方向排列的至少一个第一排布单元，每个所述第一排布单元包括N个所述第四像素电路以及第一间隔空间，N为正整数，其中，N个所述第四像素电路沿所述第一方向依次相邻设置，所述第一间隔空间沿所述第一方向位于N个所述第四像素电路的一侧；以及
    多条第一数据线，每条所述第一数据线与至少一个所述第一像素电路以及至少一个第二像素电路电连接，其中，至少一条所述第一数据线经过所述第一间隔空间。
  2. 根据权利要求1所述的显示面板，其特征在于，每个所述第一像素电路通过对应的连接线与至少一个所述第一发光元件电连接，
    每条所述第一数据线包括第一子数据线、第二子数据线以及第三子数据线，所述第一子数据线沿所述第二方向延伸于所述第三显示区，并与至少一个所述第一像素电路电连接，所述第二子数据线沿所述第二方向延伸于所述第二显示区，并与多个所述第二像素电路电连接，所述第三子数据线经过所述第四显示区，并将所述第一子数据线与所述第二子数据线电连接，其中至少一条所述第三子数据线经过所述第一间隔空间，使得至少一条所述第三子数据线在显示面上的正投影与所述连接线在显示面上的正投影无交叠。
  3. 根据权利要求1所述的显示面板，其特征在于，所述显示面板包括位于所述第四显示区的多个第一像素单元，每个第一像素单元包括M个所述第四发光元件，
    其中，N为M的正整数倍。
  4. 根据权利要求1所述的显示面板，其特征在于，所述第一间隔空间沿所述第一方向的长度，等于所述第四像素电路沿所述第一方向的长度的0.5倍至3倍。
  5. 根据权利要求2所述的显示面板，其特征在于，所述第三显示区中设有多个行单元，每个所述行单元中，所述第一像素电路和/或所述第三像素电路和/或所述虚拟像素电路以预设规则沿所述第一方向依次排布，所述多个行单元沿所述第二方向排列，
    所述多个行单元包括与所述第四显示区相邻的至少一个第一行单元，
    每个所述第一行单元包括沿所述第一方向排列的多个第二排布单元，每个所述第二排布单元包括P个第一预设像素电路以及第二间隔空间，P为正整数，所述第一预设像素电路包括所述第一像素电路、所述第三像素电路、或第一虚拟像素电路中的至少一者，其中，P个所述第一预设像素电路沿所述第一方向依次相邻设置，所述第二间隔空间沿所述第一方向位于P个所述第一预设像素电路的一侧。
  6. 根据权利要求5所述的显示面板，其特征在于，沿所述第二方向，至少部分所述第二间隔空间与所述第一间隔空间连通。
  7. 根据权利要求5所述的显示面板，其特征在于，所述第二间隔空间沿所述第一方向的长度，等于所述第一像素电路沿所述第一方向的长度的0.5倍至3倍。
  8. 根据权利要求5所述的显示面板，其特征在于，所述多个行单元包括还包括至少一个第二行单元，所述第二行单元位于所述第一行单元背离所述第四显示区的一侧，
    每个所述第二行单元中，多个第二预设像素电路沿所述第一方向依次相邻设置，所述第二预设像素电路包括所述第一像素电路、所述第三像素电路、或第二虚拟像素电路中的至少一者。
  9. 根据权利要求5所述的显示面板，其特征在于，每个所述第三显 示区中，所述第一行单元的数量等于与所述第三显示区相邻的所述第四显示区的数量，每个所述第一行单元与对应一个所述第四显示区相邻。
  10. 根据权利要求5所述的显示面板，其特征在于，与所述第四显示区相邻的一个所述第一行单元包括相对的第一侧和第二侧，所述第一侧朝向所述第四显示区。
  11. 根据权利要求10所述的显示面板，其特征在于，同一所述第四显示区中全部所述第二子数据线所电连接的全部所述第三子数据线，均位于与所述第四显示区相邻的所述第一行单元的所述第一侧。
  12. 根据权利要求10所述的显示面板，其特征在于，所述第三子数据线通过第一连接点与所述第一子数据线电连接，其中，至少一条所述第三子数据线所连接的所述第一连接点位于所述第二侧。
  13. 根据权利要求12所述的显示面板，其特征在于，每个第三显示区与所述第一显示区之间设有第一分界线，在每个所述第三显示区与所述第一显示区之间，沿远离所述第一分界线方向依次排列的多个所述第一发光元件所对应的多个所述第一像素电路，在所述第三显示区沿远离所述第一分界线的方向依次排列。
  14. 根据权利要求13所述的显示面板，其特征在于，最远离所述第一显示区的所述第一子数据线所对应的至少一条所述第三子数据线，延伸至所述第二侧，
    至少一条所述第三子数据线呈阶梯状延伸。
  15. 根据权利要求13所述的显示面板，其特征在于，最靠近所述第一显示区的至少一条所述第一子数据线所对应的至少一条所述第三子数据线，延伸至所述第二侧，并经过位于对应所述第一子数据线的远离所述第一显示区一侧的所述第二间隔空间。
  16. 根据权利要求10所述的显示面板，其特征在于，所述连接线通过第二连接点与所述第一像素电路电连接，
    在所述第一行单元中，至少一个所述第二连接点位于所述第二侧。
  17. 根据权利要求16所述的显示面板，其特征在于，所述第一行单元中的至少一个所述第一像素电路，与剩余所述行单元中的至少一个所述第一像素电路关于预设对称轴镜像，所述预设对称轴平行于所述第一方向。
  18. 一种显示装置，其特征在于，包括根据权利要求1至17任一项所述的显示面板。
PCT/CN2021/108425 2021-06-30 2021-07-26 显示面板及显示装置 WO2023272838A1 (zh)

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