WO2023246437A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2023246437A1
WO2023246437A1 PCT/CN2023/097074 CN2023097074W WO2023246437A1 WO 2023246437 A1 WO2023246437 A1 WO 2023246437A1 CN 2023097074 W CN2023097074 W CN 2023097074W WO 2023246437 A1 WO2023246437 A1 WO 2023246437A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
thin film
film transistor
area
electrode
Prior art date
Application number
PCT/CN2023/097074
Other languages
English (en)
French (fr)
Inventor
王晶
田宏伟
李然
陈善韬
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023246437A1 publication Critical patent/WO2023246437A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate, a preparation method thereof, and a display device.
  • the circuit layer includes a driving circuit located in the island area and a via hole located in the hole area; the circuit layer also includes at least one photoelectric sensor electrically connected to the driving circuit; the photoelectric sensor includes a stacked arrangement The first electrode layer, the photoelectric structure layer and the second electrode layer;
  • the photoelectric sensor is located in the island area, and the first electrode layer, the photoelectric structure layer and the second electrode layer of the photoelectric sensor are arranged in sequence along the direction from the island area to the bridge area. ; and/or, the photoelectric sensor is located in the bridge area, and the first electrode layer, the photoelectric structure layer and the second electrode layer of the photoelectric sensor point along the bridge area to the island area set in sequence.
  • the driving circuit includes a first thin film transistor for driving the photosensor, and a drain of the first thin film transistor is electrically connected to the first electrode layer of the photosensor.
  • the drain electrode of the first thin film transistor is multiplexed as the first electrode layer.
  • the gate electrode of the first thin film transistor is multiplexed as the first electrode layer.
  • a light-emitting device is provided on the side of the circuit layer facing away from the base substrate; the light-emitting device includes a third electrode layer and a fourth electrode layer, and is provided on the third electrode layer and the third electrode layer. The light-emitting layer between the four electrode layers;
  • the third electrode layer is multiplexed as the first electrode layer of the photosensor, and the fourth electrode layer is multiplexed as the second electrode layer of the photosensor.
  • the photoelectric sensor is located in the island area;
  • the circuit layer includes a first thin film transistor located in the island area, and a buffer layer, a buffer layer, and a first thin film transistor located in the island area and sequentially disposed on the base substrate. an insulating layer, a second insulating layer and a third insulating layer;
  • the source electrode and the drain electrode of the first thin film transistor are arranged On a side of the second insulating layer facing away from the base substrate, the source is connected to the source of the active layer through a first connection via that penetrates the first insulating layer and the second insulating layer.
  • the drain region is electrically connected to the drain region of the active layer through a second connection via penetrating the first insulating layer and the second insulating layer;
  • the first electrode layer includes a first substructure, a second substructure, and a third substructure connecting the first substructure and the second substructure;
  • the first substructure, the third substructure and the second substructure are arranged sequentially along the direction in which the substrate substrate points to the circuit layer.
  • the second substructure and the third substructure are electrically connected to the drain of the first thin film transistor. Further, the drain of the first thin film transistor is multiplexed as the third thin film transistor.
  • the second substructure and the third substructure; the first substructure is electrically connected to the third electrode layer, and further, the third electrode layer is multiplexed into the first substructure.
  • the first electrode layer is arranged in a rectangular structure.
  • the photosensor is located in the bridge area;
  • the circuit layer includes a buffer layer, a first insulating layer and a third insulating layer located in the bridge area and sequentially disposed on the base substrate;
  • the driving circuit includes a first thin film transistor for driving the photosensor; a third connection via is provided in the first insulating layer;
  • the drain of the first thin film transistor is electrically connected to the first electrode layer through the third connection via hole, and further, the drain of the first thin film transistor is reused as the first electrode layer; or , the gate electrode of the first thin film transistor is electrically connected to the first electrode layer through a third connection via hole, and further, the gate electrode of the first thin film transistor is multiplexed as the first electrode layer.
  • the via hole of the hole area is located between the island area and the bridge area; the photoelectric sensor is located on the side wall of each film layer between the island area and the bridge area; The side wall and the base substrate form a preset inclination angle.
  • the via hole of the hole area is located between the island area and the bridge area;
  • the photoelectric sensor includes a multi-level optoelectronic structure;
  • the multi-level optoelectronic structure is located between the island area and the bridge area.
  • the angle range between the first sub-optoelectronic structure of the i-th level optoelectronic structure and the second sub-optoelectronic structure of the i-1 level optoelectronic structure is between 85° and 105°; the i-th level optoelectronic structure
  • the angle range between the second sub-optoelectronic structure of the structure and the first sub-optoelectronic structure of the i+1-th level optoelectronic structure is located at 85° ⁇ 105°;
  • the angle range between the first sub-optoelectronic structure of the i-th level optoelectronic structure and the second sub-optoelectronic structure of the i-th level optoelectronic structure is between 85° and 105°.
  • embodiments of the present disclosure also provide a method of manufacturing a display substrate, wherein the display substrate has an island region, a hole region and a bridge region, and the method of manufacturing the display substrate includes:
  • At least one photoelectric sensor electrically connected to the driving circuit is also formed on the circuit layer;
  • the photoelectric sensor includes a first electrode layer, a photoelectric structure layer and a second electrode layer arranged in a stack;
  • an embodiment of the present disclosure further provides a display device, which includes the display substrate as described in any one of the examples in the first aspect.
  • Figure 3 is a schematic diagram of a photoelectric sensor located in the bridge area provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram showing each film layer of the substrate when the photoelectric sensor provided by the embodiment of the present disclosure is located in the island area;
  • Figure 5 is a schematic diagram of a driving circuit of a photoelectric sensor provided by an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of a driving circuit of another photoelectric sensor provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the connection structure between the gate of the first thin film transistor and the photoelectric sensor when the photoelectric sensor provided by the embodiment of the present disclosure is located in the island area;
  • Figure 12 is a schematic structural diagram of the sidewall of each film layer between the island area and the bridge area of a photoelectric sensor provided by an embodiment of the present disclosure
  • Figure 13 is a schematic structural diagram of another photoelectric sensor located in the side walls of each film layer between the island area and the bridge area according to an embodiment of the present disclosure
  • the reference numbers are: display substrate 100; substrate substrate 01; circuit layer 02; photoelectric sensor 03; first electrode layer 31; first substructure 311; second substructure 312; third substructure 313; optoelectronic structure layer 32; second electrode layer 33; first thin film transistor T1; via Via0 in the hole area; buffer layer 21; first insulating layer 22; second insulating layer 23; third insulating layer 24; first thin film transistor T1 Source layer T11; gate electrode T12 of the first thin film transistor T1; source electrode T13 of the first thin film transistor T1; drain electrode T14 of the first thin film transistor T1; source region T11a of the active layer T11 of the first thin film transistor T1; The drain region T11b of the active layer T11 of a thin film transistor T1; the first connection via Via1; the second connection via Via2; the glass sub-substrate 11; the flexible sub-substrate 12; the modulus material 13; the light-emitting device 04; the third electrode Layer 41; light-emitting
  • the circuit layer 02 includes the drive circuit located in the island area and the via Via0 located in the hole area; the circuit layer 02 also It includes at least one photoelectric sensor 03 electrically connected to the driving circuit; the photoelectric sensor 03 includes a first electrode layer 31, a photoelectric structure layer 32 and a second electrode layer 33 arranged in a stack.
  • the photoelectric sensor 03 is located in the island area, and the first electrode layer 31 , the photoelectric structure layer 32 and the second electrode layer 33 of the photoelectric sensor 03 are arranged in sequence along the direction from the island area to the bridge area.
  • the photoelectric sensor 03 is located in the bridge area, and the first electrode layer 31 , the photoelectric structure layer 32 and the second electrode layer 33 of the photoelectric sensor 03 are arranged in sequence along the direction from the bridge area to the island area.
  • the via Via0 in the hole area is located between the island area and the bridge area, and the via Via0 in the hole area penetrates the circuit layer 02 in the direction vertical to the base substrate 01 .
  • the photoelectric sensor 03 is located close to the hole area on the circuit layer 02, and the first electrode layer 31, the photoelectric structure layer 32 and the second electrode layer 33 are successively close to the via Via0 of the hole area.
  • the photoelectric sensor 03 may be an organic photodiode (Organic-Photo-Diode, OPD).
  • the material of the active layer of the first thin film transistor T1 provided by the embodiment of the present disclosure may be a semiconductor material, for example, it may include low-temperature polysilicon, or oxide, etc., and may be limited according to requirements in actual applications. The embodiment of the present disclosure will not provide details. limited.
  • the purpose of setting an opening on the buffer layer 21 through the via Via0 can release the accumulated energy of the buffer layer 21 during stretching. stress to avoid cracks in the buffer layer 21 due to stretching, thereby avoiding damage to the display substrate 100 and improving the stretchability of the display substrate 100.
  • the material of the first insulating layer 22 only needs to be a material that can satisfy the insulation between the active layer T11 and the gate electrode T12 of the first thin film transistor T1, and is not specifically limited in the embodiment of the present disclosure.
  • the first insulating layer 22 may be a first gate insulator (Gate Insulator, GI for short) layer GI1.
  • the second insulating layer 23 is used to protect the insulation between the gate electrode T12 of the first thin film transistor T1 and other metal structures (such as the source electrode T13 and the drain electrode T14 of the first thin film transistor T1).
  • the second insulating layer 23 can be a single layer. Insulating layer, such as the second gate insulating layer GI2; alternatively, a multi-layer stacked sub-insulating layer can also be used, such as a stacked second gate insulating layer GI2 and an inter-layer dielectric (ILD) layer. .
  • ILD inter-layer dielectric
  • the embodiment of the present disclosure does not specifically limit the material of the second insulating layer 23 .
  • the driving circuit includes a first thin film transistor for driving the photosensor 03.
  • Figure 5 is a schematic diagram of a driving circuit of a photosensor provided by an embodiment of the present disclosure.
  • the first thin film transistor The source T13 of T1 is electrically connected to an external signal source (not shown in FIG. 5 , the external signal source may be a signal source capable of providing a fixed voltage), and the drain T14 of the first thin film transistor T1 is connected to the third terminal of the photoelectric sensor 03 An electrode layer 31 is electrically connected.
  • the photoelectric structure layer 32 of the photoelectric sensor 03 includes a photodiode PIN and a capacitor C.
  • the drain of the first thin film transistor is a titanium (Ti)-aluminum (Al)-titanium (Ti) metal composite layer, that is, the first electrode layer 31 is titanium (Ti)-aluminum (Al)-titanium. (Ti) metal composite layer.
  • the embodiment of the present disclosure does not limit the material of the drain electrode of the first thin film transistor.
  • it can also be other feasible materials. , which can be specifically limited based on experience and actual scenarios, and the embodiments of this disclosure will not list them one by one.
  • the driving circuit includes a first thin film transistor for driving the photoelectric sensor 03.
  • Figure 7 is a schematic diagram of a driving circuit of another photoelectric sensor provided by an embodiment of the present disclosure, as shown in Figure 7, wherein the first thin film transistor
  • the source T13 and the drain T14 of the transistor T1 are respectively electrically connected to an external signal source (not shown in FIG. 7 , the external signal source may be a signal source capable of providing a fixed voltage), and the gate T12 of the first thin film transistor T1 It is electrically connected to the first electrode layer 31 of the photoelectric sensor 03.
  • the photoelectric structure layer 32 of the photoelectric sensor 03 includes a photodiode PIN and a capacitor C.
  • the photodiode PIN and the capacitor C are connected in parallel, and the parallel first terminal N1 is connected to the first electrode layer 31.
  • the parallel second terminal N2 is connected to the second electrode layer 33 .
  • the first electrode layer 31 is the anode of the photoelectric sensor 03
  • the second electrode layer 33 is the cathode of the photoelectric sensor 03, and is connected to the low power supply voltage VSS.
  • Figure 8 is a schematic diagram of the connection structure between the gate electrode of the first thin film transistor and the photoelectric sensor when the photoelectric sensor provided by the embodiment of the present disclosure is located in the island area.
  • the gate electrode T12 of the first thin film transistor T1 and the photoelectric sensor The first electrode layer 31 of the sensor 03 is electrically connected.
  • the gate electrode of the first thin film transistor is multiplexed as the first electrode layer 31.
  • Figure 8 shows the gate electrode T12 of the first thin film transistor T1 and the photoelectric sensor 03. A schematic diagram of the connection relationship between them.
  • FIG. 8 does not show the specific connection structure between the gate T12 of the first thin film transistor T1 and the first electrode layer 31 .
  • the gate T12 of the first thin film transistor T1 can be directly reused as the first electrode layer 31 of the photosensor 03, a gate layer can be directly prepared during the process preparation stage, which can improve the preparation efficiency.
  • the photoelectric sensor 03 and the gate T12 of the first thin film transistor T1 may be on the same layer. As shown in FIG. 8 , the photoelectric sensor 03 is disposed on the side of the first insulating layer 22 facing away from the base substrate 01 , that is, it is disposed in the second gate insulating layer GI2 in the second insulating layer 23 .
  • the photosensor 03 can also be in the same layer as other layers except the second gate insulating layer GI2 in the second insulating layer 23, such as the first insulating layer 22, the interlayer insulating layer ILD in the second insulating layer 23, and the second gate insulating layer GI2 in the second insulating layer 23.
  • any one of the passivation layer PVX in the three insulating layers 24 , the first flat layer PLN1 in the third insulating layer 24 and the second flat layer PLN2 in the third insulating layer 24 is in the same layer, that is, the photoelectric sensor is arranged In this layer, other ways of setting up the same layer are not listed one by one in this disclosed embodiment.
  • the photoelectric sensor 03 may also be located in the first insulating layer 22 , the second gate insulating layer GI2 in the second insulating layer 23 , the interlayer insulating layer ILD in the second insulating layer 23 , and the passivation layer in the third insulating layer 24 .
  • the active layers T1 of the two thin film transistors T2 at least partially overlap in orthographic projection on the base substrate 01; the source electrode T23 of the second thin film transistor T2 and the drain electrode T24 of the second thin film transistor T2 are arranged on the second insulating layer 23 away from the substrate.
  • the first end of the source electrode T23 of the second thin film transistor T2 is electrically connected to the source region T21a of the active layer T21 of the second thin film transistor T2 through the fourth connection via Via4.
  • the second thin film transistor T2 The drain T24 of the second thin film transistor T2 is electrically connected to the drain region T21b of the active layer T21 of the second thin film transistor T2 through the fifth connection via Via5;
  • the third electrode layer 41 is electrically connected.
  • the third electrode layer 41 can be directly multiplexed as the first electrode layer 31 of the photosensor 03
  • the fourth electrode layer 43 can be directly multiplexed as the second electrode layer 33 of the photosensor 03, therefore, in the process preparation stage,
  • the mutually multiplexed electrode layers can be directly prepared as one layer, which can improve the preparation efficiency.
  • the first electrode layer 31 and the second electrode layer 33 can also be prepared separately without reusing the third electrode layer 41 and the fourth electrode layer 43 of the light-emitting device.
  • the OPD material can be flexible and can withstand the deformation of the bridge area, so it can be
  • the photoelectric sensor 03 is arranged on the circuit layer 02 located in the bridge area.
  • Figure 10 is a schematic structural diagram of each film layer of the display substrate when the photoelectric sensor provided by the embodiment of the present disclosure is located in the bridge area.
  • the photoelectric sensor 03 is located in the bridge area; circuit Layer 02 includes located in the bridge area and is located in sequence The buffer layer 21, the first insulating layer 22 and the third insulating layer 24 on the base substrate 01.
  • the photoelectric sensor 03 is in the same layer as the first insulating layer 22 or the third insulating layer 24; alternatively, the photoelectric sensor 03 is located between the first insulating layer 22 and the third insulating layer 24, that is, the first insulating layer 22 is located away from the substrate. 01 on the surface.
  • FIG. 10 shows a schematic diagram of the photoelectric sensor 03 and the first insulating layer 22 being on the same layer.
  • At least one third connection via Via3 is provided in the first insulating layer 22 located in the bridge region.
  • the drain T14 of the first thin film transistor T1 is in the same layer as the first insulating layer 22 located in the bridge region, and the first electrode layer 31 of the photoelectric sensor 03 is electrically connected to the drain T14 of the first thin film transistor T1.
  • the drain electrode T14 of the first thin film transistor T1 is multiplexed as the first electrode layer 31 of the photosensor 03 .
  • the gate of the first thin film transistor is provided at the third connection via hole, at this time, the gate of the first thin film transistor is in the same layer as the first insulating layer 22 in the bridge area, and the first electrode layer 31 of the photoelectric sensor 03 It may be electrically connected to the gate T12 of the first thin film transistor T1.
  • the gate T12 of the first thin film transistor T1 is multiplexed as the first electrode layer 31 of the photosensor 03.
  • FIG. 11 is a schematic structural diagram of a first electrode layer provided by an embodiment of the present disclosure. As shown in FIG. 11 , it is a preferred arrangement that the photoelectric sensor 03 and the third insulating layer 24 are in the same layer. Taking the example between the first planar layer PLN1 and the second planar layer PLN2, the third insulating layer 24 here may be the third insulating layer 24 located in the island region or the third insulating layer 24 located in the bridge region.
  • the first electrode layer 31 includes a first substructure 311, a second substructure 312 and a third substructure 313 connecting the first substructure 311 and the second substructure 312; the first substructure 311, the third substructure 313 and the third substructure 313.
  • the two substructures 312 are arranged sequentially along the direction in which the base substrate 01 points to the circuit layer 02 .
  • the first substructure 311 and the second substructure 312 are trapezoidal structures, wherein the first substructure 311 is a right-angled trapezoid, the second substructure 312 is an inverted direct trapezoid, and the third substructure 313 is a rectangle. Structure, such an arrangement can enhance the signal, prevent the signal light from scattering up and down, and increase the signal-to-noise ratio.
  • the first planar layer PLN1 and the second planar layer PLN2 can be etched into a trapezoidal structure by exposure, and then the trapezoidal first substructure 311 and the second substructure 312 shown in FIG. 11 can be deposited.
  • the right-angled sides of the first substructure 311 and the second substructure 312 and the long side of the third substructure 313 are arranged on the same side to form a plane, so that the first substructure 311 and the second substructure 312 are arranged on the same side.
  • the hypotenuse and the other long side of the third substructure 313 are disposed on the same side, so one side of the formed first electrode layer 31 is a concave surface.
  • Example 1 The second substructure 312 and the third substructure 313 are electrically connected to the drain T14 of the first thin film transistor T1.
  • the drain T14 of the first thin film transistor T1 is multiplexed into the second substructure 312 and the third substructure. 313.
  • the first substructure 311 is electrically connected to the third electrode layer 41 , and the third electrode layer 41 is multiplexed into the first substructure 311 .
  • Example 2 The first substructure 311, the second substructure 312 and the third substructure 313 are all electrically connected to the third electrode layer 41, and the third electrode layer 41 is simultaneously multiplexed into the first substructure 311 and the second substructure. 312 and third substructure 313.
  • Example 3 The drain T14 of the first thin film transistor T1 is multiplexed into the first substructure 311, the second substructure 312, and the third substructure 313 at the same time.
  • the following uses the photoelectric sensor 03 prepared by the evaporation method as an example to describe the display substrate 100 provided by the embodiment of the present disclosure. Each structure is described in detail.
  • Figure 12 is a schematic structural diagram of a photoelectric sensor provided by an embodiment of the present disclosure located on the side walls of each film layer between the island area and the bridge area. As shown in Figure 12, the via Via0 of the hole area is located Between the island area and the bridge area; the photoelectric sensor 03 is located on the side wall of each film layer between the island area and the bridge area; the side wall and the substrate substrate 01 are at a preset inclination angle.
  • the preset inclination angle can be set based on experience, and is not specifically limited in the embodiment of the present disclosure.
  • each film layer between the island area and the bridge area include the side walls of each film layer located in the island area and the side walls of each film layer located in the bridge area.
  • the first electrode layer 31, the photoelectric structure layer 32 and the second electrode layer 33 are sequentially stacked along the island region toward the bridge region, and/or on each film located in the bridge region
  • the first electrode layer 31, the photoelectric structure layer 32 and the second electrode layer 33 are stacked in sequence along the bridge area and toward the island area.
  • the drain T14 of the first thin film transistor T1 can be multiplexed as the first The electrode layer 31; or the gate T12 of the first thin film transistor T1 is multiplexed as the first electrode layer 31; or the third electrode layer 41 is multiplexed as the first electrode layer 31.
  • the drain T14 of the first thin film transistor T1 is electrically connected to the first electrode layer 31 , and the drain T14 of the first thin film transistor T1 is multiplexed as the first Electrode layer 31.
  • Figure 13 is a schematic structural diagram of another photoelectric sensor provided by an embodiment of the present disclosure located on the side walls of each film layer between the island area and the bridge area.
  • the via hole in the hole area is located Between the island area and the bridge area; the photoelectric sensor 03 includes a multi-level photoelectric structure; the multi-level photoelectric structure is located on the side wall of each film layer between the island area and the bridge area; the first sub-photoelectric structure of the i-th level photoelectric structure and The second sub-optoelectronic structure of the i-1 level optoelectronic structure is connected; the second sub-optoelectronic structure of the i-level optoelectronic structure is connected to the first sub-optoelectronic structure of the i+1 level optoelectronic structure; 0 ⁇ i ⁇ N, N is A positive integer greater than or equal to 2.
  • the photoelectric sensor 03 located on the side wall of the island area includes 4-level photoelectric structures I-IV, where the I-level photoelectric structure includes a first sub-photoelectric structure I1 and a second photoelectric structure I2, and the II-level photoelectric structure includes a first sub-photoelectric structure I1 and a second photoelectric structure I2.
  • the level III optoelectronic structure includes a first sub-optoelectronic structure II1 and a second optoelectronic structure II2, the level III optoelectronic structure includes a first sub-optoelectronic structure III1 and a second optoelectronic structure III2, and the level IV optoelectronic structure includes a first sub-optoelectronic structure IV1.
  • the first sub-optoelectronic structure II1 of the level II optoelectronic structure is connected to the second sub-optoelectronic structure I2 of the level I optoelectronic structure
  • the second sub-optoelectronic structure II2 of the level II optoelectronic structure is connected to the first sub-optoelectronic structure of the level III optoelectronic structure. Structure III1 connection.
  • the angle between the first sub-optoelectronic structure of the i-th level optoelectronic structure and the second sub-optoelectronic structure of the i-1 level optoelectronic structure is between 85° and 105°; the second sub-optoelectronic structure of the i-th level optoelectronic structure
  • the angle range between the first sub-optoelectronic structure of the i+1-th level optoelectronic structure and the first sub-optoelectronic structure of the i-th level optoelectronic structure is between 85° and 105°;
  • the angle between the photoelectric structures is between 85° and 105°.
  • the angle between any connected first sub-optoelectronic structure and second sub-optoelectronic structure may be set to 90°.
  • the corner formed between any connected first sub-optoelectronic structure and the second sub-optoelectronic structure may be located within the allowable error range of the 90° corner.
  • the multi-level optoelectronic structure forms a ladder-like optoelectronic structure.
  • each film layer located between the island area and the bridge area The side walls are also set into a stepped structure to adapt to the stepped multi-level optoelectronic structure.
  • a light-emitting layer is provided on the side of the circuit layer 02 facing away from the base substrate 01; the light-emitting layer includes a first hole transport layer HTL1 and a first exciton blocking layer ETL1; the optoelectronic structure layer 32 includes a light-emitting layer along the first electrode layer 31 Pointing to the second electrode layer 33, the second hole transport layer HTL2, the second exciton blocking layer ETL2 and the optoelectronic material layer (that is, the OPD material layer) are stacked in sequence; the first hole transport layer HTL1 and the second hole transport layer HTL2 are stacked in sequence.
  • the hole transport layer HTL2 is connected, and the first hole transport layer HTL1 is multiplexed into the second hole transport layer HTL2; the first exciton blocking layer ETL1 is connected to the second exciton blocking layer ETL2, and the first exciton blocking layer ETL1 Multiplexed into the second exciton blocking layer ETL2.
  • the first hole transport layer HTL1 and the first exciton blocking layer ETL1 in the light-emitting layer are stacked in sequence in the direction from the third electrode layer to the fourth electrode layer.
  • the second hole transport layer HTL2, the second exciton blocking layer ETL2 and the optoelectronic material layer in the optoelectronic structure layer 32 together form the photodiode PIN and the capacitor C.
  • the first hole transport layer HTL1 is multiplexed into the second hole transport layer HTL2, and the first exciton blocking layer ETL1 is multiplexed into the second exciton blocking layer ETL2, which can save costs such as equipment and materials.
  • an encapsulation film layer 05 is provided on the outside of the display substrate 100 , that is, on the outer walls of each film layer located in the island area and the bridge area.
  • the encapsulation film layer 05 is, for example, a film layer of tetrafluoroethylene TFE material. Only the encapsulating film layer 05 disposed outside the island area is shown in Figure 14o.
  • the embodiment of the disclosure also provides a method for preparing the display substrate 100. Since the principle of the problem solved by the method of preparing the display substrate 100 in the embodiment of the disclosure is similar to the above-mentioned display substrate 100 in the embodiment of the disclosure, Therefore, various structures of the display substrate 100 in the preparation method of the display substrate 100 can be referred to the display substrate 100 provided in the above embodiments, and repeated descriptions will not be repeated.
  • a method of manufacturing a display substrate 100 wherein the display substrate 100 has an island area, a hole area and a bridge area, and the method of manufacturing the display substrate 100 includes: forming a circuit on the base substrate 01 Layer 02; on the circuit layer 02, a driving circuit located in the island area and a drive circuit located in the hole area are formed.
  • the photoelectric sensor 03 electrically connected to the driving circuit is also formed on the circuit layer 02;
  • the photoelectric sensor 03 includes a stacked first electrode layer 31, a photoelectric structure layer 32 and a second electrode layer 33; the photoelectric sensor 03 is located in the island area, and the first electrode layer 31, the photoelectric structure layer 32 and the second electrode layer 33 of the photoelectric sensor 03 are sequentially arranged in the direction from the island area to the bridge area; and/or the photoelectric sensor 03 is located in the bridge area, and The first electrode layer 31, the photoelectric structure layer 32 and the second electrode layer 33 of the photoelectric sensor 03 are arranged in sequence in the direction from the bridge area to the island area.
  • the photosensor 03 is integrated into the display substrate 100 located in the stretchable island area and/or the bridge area, and the display substrate 100 is stretched.
  • the photosensor 03 can be stretched using the via Via0 in the hole area.
  • the illumination changes after the stretching change can be used to monitor the stretching state, which can be used for stretchable displays, electronic skins and other displays.
  • the first electrode layer 31, the photoelectric structure layer 32 and the second electrode layer 33 in the photoelectric sensor 03 are stacked along the direction between the island area and the bridge area, that is, the structures of the photoelectric sensor 03 are arranged horizontally, which can reduce the occupation area, thereby improving the display resolution and aperture ratio.
  • the photoelectric sensor 03 is prepared by a solution method.
  • the driving circuit in Figure 5 is taken as an example. Steps S1 to S15 will be described in detail below.
  • Figures 14a to 14o are Schematic diagram of the preparation process of a display substrate provided by an embodiment of the present disclosure:
  • the substrate substrate 01 includes a glass sub-substrate 11 and a flexible sub-substrate 12.
  • the orthographic projection of the hole area on the substrate substrate 01 forms a via hole penetrating the flexible sub-substrate 12, and the via hole is formed through the flexible sub-substrate 12.
  • the via holes are filled with low modulus material 13.
  • the buffer layer 21 located in the island area and the bridge area is prepared at the same time.
  • a semiconductor layer is deposited on the base substrate 01; then, a photoresist is coated on the side of the semiconductor layer facing away from the base substrate 01 and is prepared by exposure, development, etching, stripping and other processes.
  • the active layer T11 of the first thin film transistor T1 and the active layer T21 of the second thin film transistor T2 are obtained.
  • the semiconductor layer can be deposited on the base substrate 01 using CVD or ALD.
  • a first connection via Via1 and a second connection via Via2 are formed penetrating the first insulating layer 22; in the source region T21a and the drain region of the active layer T21 of the second thin film transistor T2 In the area where the orthographic projection of the area T21b is located, the fourth connection via hole Via4 and the fifth connection via hole Via5 that penetrate the first insulating layer 22 are formed, as shown in FIG. 14c.
  • the first insulating layer 22 may be a first gate insulating layer GI1 for protecting the active layer T11 of the first thin film transistor T1.
  • the final display substrate has multiple insulating layers, and the multiple insulating layers have a relatively deep depth, it is difficult to drill holes through the multiple insulating layers at one time. Therefore, in the embodiment of the present disclosure, the same connection via holes are used in batches. The way to get through. In one case, in order to reduce the difficulty of the drilling process, each time an insulating layer is deposited, a sub-connection via is formed through the insulating layer.
  • a first connection via Via1 and a second connection via Via2 penetrating the first insulating layer 22 are formed, and so on.
  • a first connection via hole Via1 and a second connection via hole penetrating the insulating layer are formed in the area where the source region T11a and the drain region T11b of the active layer T11 of the first thin film transistor T1 are orthogonally projected. Via2.
  • the hole preparation process is performed.
  • the specific drilling preparation process may refer to the above-mentioned drilling process performed for each layer of insulating layer deposited.
  • the first insulating layer 22 located in the island area and the bridge area is prepared at the same time.
  • the gate T12 of the first thin film transistor T1 and the gate T22 of the second thin film transistor T2 are formed on the side of the first insulating layer 22 away from the base substrate 01, and the gate electrode of the first thin film transistor T1 T12 overlaps with the orthographic projection of the active layer T11 of the first thin film transistor T1 on the base substrate 01 ; the gate T22 of the second thin film transistor T2 and the active layer T21 of the second thin film transistor T2 overlap on the base substrate 01 The orthographic projections overlap, as shown in Figure 14d.
  • the second gate insulating layer GI2 is used to protect the gate electrode T12 of the first thin film transistor T1 and the gate electrode T22 of the second thin film transistor T2.
  • the drain region T11b of the second thin film transistor T2 is electrically connected to the source region T21a of the second thin film transistor T2 through the fourth connection via Via4, and the drain electrode T24 of the second thin film transistor T2 is electrically connected through the fifth connection via Via4.
  • the hole Via5 is electrically connected to the drain region T21b of the second thin film transistor T2, as shown in Figure 14g.
  • the source electrode T13 and the drain electrode T14 of the first thin film transistor T1 are formed on the side of the source electrode T23 and the drain electrode T24 of the thin film transistor T2 away from the base substrate 01, as shown in Figure 14h.
  • the passivation layer PVX covers the source electrode T13 and the drain electrode T14 of the first thin film transistor T1 and the source electrode T23 and the drain electrode T24 of the second thin film transistor T2, and is used to protect the source electrode T13 and the drain electrode T14 of the first thin film transistor T1 and The source electrode T23 and the drain electrode T24 of the second thin film transistor T2.
  • first planar layer PLN1 on the side of the passivation layer PVX facing away from the base substrate 01, and form a first planar layer PLN1 penetrating the first planar layer PLN1 in the area where the orthographic projection of the source electrode T13 and the drain electrode T14 of the first thin film transistor T1 is located.
  • the first connection via hole Via1 and the second connection via hole Via2 are formed in the area where the orthographic projection of the source electrode T23 and the drain electrode T24 of the second thin film transistor T2 is located, and the fourth connection via hole Via4 and the fourth connection via hole Via4 penetrating the first planarization layer PLN1 are formed.
  • the first flat layer PLN1 located in the island region and the bridge region is simultaneously prepared, wherein in the bridge region, a first gate insulating layer GI1 is formed on the side facing away from the base substrate 01.
  • the drain T14 of the first thin film transistor T1 located at the passivation layer PVX is electrically connected; the source T23 of the second thin film transistor T2 is connected to the source of the second thin film transistor T2 located at the passivation layer PVX through the fourth connection via Via4.
  • the electrode T23 is electrically connected, and the drain electrode T24 of the second thin film transistor T2 is electrically connected to the drain electrode T24 of the second thin film transistor T2 located at the passivation layer PVX through the fifth connection via Via5.
  • the drain electrode T14 of the first thin film transistor T1 is multiplexed as the first electrode layer 31 of the photosensor 03 .
  • the photosensor 03 is located on the side of the first flat layer PLN1 away from the base substrate 01, that is, on the same layer as the second flat layer PLN2 described below, as shown in Figure 14j.
  • a second planar layer PLN2 is formed on the side of the source electrode T13 and the drain electrode T14 of the first thin film transistor T1 prepared in S10 away from the base substrate 01, and after exposure, etching and patterning on the second planar layer PLN2 , leaving the via hole 321 of the photoelectric structure layer 32 to be coated for the photoelectric sensor 03 and the second electrode
  • the via hole 331 of the pole layer 33 is shown in Figure 14k.
  • the optoelectronic structure layer 32 of the photoelectric sensor 03 is coated in the reserved via hole.
  • the optoelectronic structure layer 32 includes the second hole transport layer HTL2, the optoelectronic material layer (OPD material) and the second excitation layer.
  • Sub-blocking layer ETL2 in which the second exciton blocking layer can also be an ink material, which can be printed directly with ink. After that, photoresist cloth is coated, etched with oxygen to form a pattern, and finally ITO or Mg or Ag is deposited. material as the second electrode layer 33 .
  • the second flat layer PLN2 located in the island area and the bridge area is simultaneously prepared; and the photoelectric sensor 03 can be separately prepared in the island area and the bridge area at the same time.
  • a sixth connection via Via6 is formed through the second planar layer PLN2 in the area where the orthographic projection of the source T23 of the second thin film transistor T2 prepared in S10 is formed, and is formed on the side of the second planar layer PLN2 away from the base substrate 01
  • the third electrode layer 41 of the light-emitting device is electrically connected to the source T23 of the second thin film transistor T2 through the sixth connection via Via6, as shown in FIG. 14l.
  • the pixel definition layer PDL is only formed on the side of the second planar layer PLN2 located in the island region facing away from the base substrate 01 .
  • the light-emitting device 04 includes a third electrode layer 41 , a fourth electrode layer 43 and a light-emitting layer 42 .
  • the third electrode layer 41 is an anode
  • the fourth electrode layer 43 is a cathode
  • the light-emitting layer 42 includes a first hole transport layer HTL1 and a first exciton blocking layer ETL1, wherein a portion of the pixel definition layer PDL facing away from the base substrate 01
  • the first hole transport layer HTL1, the first exciton blocking layer ETL1 and the fourth electrode layer 43 are sequentially deposited on the side.
  • the first hole transport layer HTL1 is multiplexed as the second hole transport layer HTL2 of the photoelectric sensor 03.
  • the sub-blocking layer ETL1 is multiplexed as the second exciton blocking layer ETL2 of the photoelectric sensor 03, and the specific multiplexed connection structure is not shown in Figure 14n.
  • the photoelectric structure layer 32 and the second electrode layer 33 of the photoelectric sensor 03 are coated at the same time.
  • the specific preparation process is as described in S11.
  • the photoelectric sensor 03 is prepared by evaporation.
  • the driving circuit of Figure 5 as an example, and follow the preparation process of steps S1 to S14.
  • the photoelectric sensor 03 is evaporated on the side wall of each film layer between the island area and the bridge area.
  • the photoelectric sensor 03 located in the island area includes a first electrode layer 31, a second hole transport layer HTL2 (for example, HTL material), an optoelectronic material layer (for example, OPD luminescent material), and a second electrode layer 31 stacked sequentially along the island area to the bridge area.
  • HTL2 for example, HTL material
  • an optoelectronic material layer for example, OPD luminescent material
  • the photoelectric sensor 03 located in the bridge area includes a first electrode layer 31, a second hole transport layer HTL2, a photoelectric material layer, a second exciton blocking layer ETL2 and a second electrode layer 33 sequentially stacked along the bridge area to the island area.
  • the drain T14 of the first thin film transistor T1 is multiplexed as the first electrode layer 31 (anode) of the photosensor 03
  • the first hole transport layer HTL1 of the light-emitting device 04 is multiplexed as the first hole transport layer of the photosensor 03 Layer HTL1
  • the first exciton blocking layer ETL1 of the light-emitting device 04 is multiplexed as the second exciton blocking layer ETL2 of the photoelectric sensor 03, emitting light
  • the fourth electrode layer 43 of the device 04 is multiplexed as the second electrode layer 33 of the photosensor 03 .
  • the photoelectric sensor 03 formed by evaporation will be in the shape of a large slope; if it is located between the island area and the bridge area If the side walls of each film layer are in a stepped shape, the photoelectric sensor 03 formed by evaporation will be in a stepped shape.
  • the photoelectric sensor 03 has a stepped structure in the above embodiments, as shown in Figure 13 .
  • an embodiment of the present disclosure also provides a display device, including the display substrate 100 in the above embodiment. Since the principle of the problem solved by the display device in the embodiment of the present disclosure is similar to that of the above-mentioned display substrate 100 in the embodiment of the present disclosure, the various structures of the display substrate 100 included in the display device can be referred to the display substrate 100 provided in the above-mentioned embodiment. Repeated points No longer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Sustainable Development (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本公开提供一种显示基板及其制备方法、显示装置，属于显示技术领域，显示基板包括衬底基板和设置在衬底基板上的电路层，并且具有岛区、孔区和桥区；电路层包括位于岛区的驱动电路、位于孔区的过孔；电路层还包括与驱动电路电连接的至少一个光电传感器；光电传感器包括叠层设置的第一电极层、光电结构层和第二电极层；光电传感器位于岛区，且光电传感器的第一电极层、光电结构层和第二电极层沿岛区指向桥区的方向上依次设置；和/或，光电传感器位于桥区，且光电传感器的第一电极层、光电结构层和第二电极层沿桥区指向岛区的方向上依次设置。

Description

显示基板及其制备方法、显示装置 技术领域
本公开显示技术领域，具体涉及显示基板及其制备方法、显示装置。
背景技术
在显示装置中集成有机光电传感器(Organic-Photo-Diode，OPD)，通过OPD检测应用环境下的光照变化，确定显示装置的当前状态。以“电子皮肤”为例，OPD检测显示装置被拉伸下的光照变化，判断显示装置的拉伸状态，进而确定人体皮肤的变化状态。但是，传统OPD的集成方式占用显示装置较大的显示区域，从而降低显示装置的开口率，进而降低显示装置整体的分辨率。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及其制备方法、显示装置。
第一方面，本公开实施例提供了一种显示基板，包括衬底基板和设置在衬底基板上的电路层，并且具有岛区、孔区和桥区；
所述电路层包括位于所述岛区的驱动电路、位于所述孔区的过孔；所述电路层还包括与所述驱动电路电连接的至少一个光电传感器；所述光电传感器包括叠层设置的第一电极层、光电结构层和第二电极层；
所述光电传感器位于所述岛区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述岛区指向所述桥区的方向上依次设置；和/或，所述光电传感器位于所述桥区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述桥区指向所述岛区的方向上依次设置。
在一些示例中，所述驱动电路包括用于驱动所述光电传感器的第一薄膜晶体管，所述第一薄膜晶体管的漏极与所述光电传感器的第一电极层电连接。
在一些示例中，所述第一薄膜晶体管的漏极复用为所述第一电极层。
在一些示例中，所述驱动电路包括用于驱动所述光电传感器的第一薄膜晶体管，所述第一薄膜晶体管的栅极与所述光电传感器的第一电极层电连接。
在一些示例中，所述第一薄膜晶体管的栅极复用为所述第一电极层。
在一些示例中，所述电路层背离所述衬底基板一侧设置有发光器件；所述发光器件包括第三电极层、第四电极层，以及设置在所述第三电极层和所述第四电极层之间的发光层；
所述第三电极层复用为所述所述光电传感器的第一电极层，所述第四电极层复用为所述所述光电传感器的第二电极层。
在一些示例中，所述光电传感器位于所述岛区；所述电路层包括位于岛区的第一薄膜晶体管，和位于所述岛区且依次设置在所述衬底基板上的缓冲层、第一绝缘层、第二绝缘层和第三绝缘层；
所述第一薄膜晶体管包括有源层、栅极、源极和漏极；所述有源层设置在所述缓冲层背离所述衬底基板的一侧；所述第一绝缘层设置在所述缓冲层背离所述衬底基板的一侧且覆盖所述第一薄膜晶体管的有源层；所述第一薄膜晶体管的栅极设置在所述第一绝缘层背离所述衬底基板的一侧，且所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的有源层在所述衬底基板上正投影至少部分交叠；所述第一薄膜晶体管的源极和漏极设置在所述第二绝缘层背离所述衬底基板的一侧，所述源极通过贯穿所述第一绝缘层和所述第二绝缘层的第一连接过孔与所述有源层的源区电连接，所述漏极通过贯穿所述第一绝缘层和所述第二绝缘层的第二连接过孔与所述有源层的漏区电连接；
所述光电传感器与所述第一绝缘层、所述第二绝缘层或所述第三绝缘层中的任意一层同层；或者，所述光电传感器位于所述第一绝缘层、所述第二绝缘层和所述第三绝缘层中的任意相邻两层之间。
在一些示例中，所述第一电极层包括第一子结构、第二子结构以及连接所述第一子结构和第二子结构的第三子结构；
所述第一子结构、所述第三子结构和所述第二子结构沿所述衬底基板指向所述电路层的方向依次设置。
在一些示例中，所述第一子结构为正梯形结构，所述第二子结构为倒梯形结构，以及第三子结构为长方形结构。
在一些示例中，所述第二子结构和所述第三子结构，与所述第一薄膜晶体管的漏极电连接，进一步地，所述第一薄膜晶体管的漏极复用为所述第二子结构和所述第三子结构；所述第一子结构与第三电极层电连接，进一步地，所述第三电极层复用为所述第一子结构。
在一些示例中，所述第一电极层设置为长方形结构。
在一些示例中，所述光电传感器位于所述桥区；所述电路层包括位于所述桥区且依次设置在所述衬底基板上的缓冲层、第一绝缘层和第三绝缘层；
所述光电传感器与所述第一绝缘层或所述第三绝缘层同层；或者，所述光电传感器位于所述第一绝缘层与所述第三绝缘层之间。
在一些示例中，所述驱动电路包括用于驱动所述光电传感器的第一薄膜晶体管；所述第一绝缘层中设置有第三连接过孔；
所述第一薄膜晶体管的漏极通过所述第三连接过孔与所述第一电极层电连接，进一步地，所述第一薄膜晶体管的漏极复用为所述第一电极层；或者，所述第一薄膜晶体管的栅极通过第三连接过孔与所述第一电极层电连接，进一步的，所述第一薄膜晶体管的栅极复用为所述第一电极层。
在一些示例中，所述孔区的过孔位于所述岛区和所述桥区之间；所述光电传感器位于所述岛区和所述桥区之间的各膜层的侧壁上；所述侧壁与所述衬底基板呈预设倾角。
在一些示例中，所述孔区的过孔位于所述岛区和所述桥区之间；所述光电传感器包括多级光电结构；所述多级光电结构位于所述岛区和所述桥区之间的各膜层的侧壁；
第i级光电结构的第一子光电结构与第i-1级光电结构的第二子光电结构连接；所述第i级光电结构的第二子光电结构与第i+1级光电结构的第一子光电结构连接；0＜i≤N，N为大于或等于2的正整数；
所述第i级光电结构的第一子光电结构与所述第i-1级光电结构的第二子光电结构之间的夹角范围位于85°～105°之间；所述第i级光电结构的第二子光电结构与所述第i+1级光电结构的第一子光电结构之间的夹角范围位于85° ～105°之间；所述第i级光电结构的第一子光电结构与所述第i级光电结构的第二子光电结构之间的夹角范围位于85°～105°之间。
第二方面，本公开实施例还提供了一种显示基板的制备方法，其中，所述显示基板具有岛区、孔区和桥区，所述显示基板的制备方法包括：
在衬底基板上形成电路层；在所述电路层上形成位于所述岛区的驱动电路、以及位于所述孔区的过孔；
在所述电路层上还形成与所述驱动电路电连接的至少一个光电传感器；所述光电传感器包括叠层设置的第一电极层、光电结构层和第二电极层；
所述光电传感器位于所述岛区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述岛区指向所述桥区的方向上依次设置；和/或，所述光电传感器位于所述桥区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述桥区指向所述岛区的方向上依次设置。
第三方面，本公开实施例还提供了一种显示装置，其中，包括如第一方面中任一项示例所述的显示基板。
附图说明
图1为本公开实施例提供的一种显示基板的各区结构示意图；
图2为本公开实施例提供的一种光电传感器位于岛区的示意图；
图3为本公开实施例提供的一种光电传感器位于桥区的示意图；
图4为本公开实施例提供的光电传感器位于岛区时，显示基板各膜层的结构示意图；
图5为本公开实施例提供的一种光电传感器的驱动电路示意图；
图6为本公开实施例提供的光电传感器位于岛区时，第一薄膜晶体管的漏极与光电传感器之间的连接结构示意图；
图7为本公开实施例提供的另一种光电传感器的驱动电路示意图；
图8为本公开实施例提供的光电传感器位于岛区时，第一薄膜晶体管的栅极与光电传感器之间的连接结构示意图；
图9为本公开实施例提供的光电传感器位于岛区时，发光器件与光电传感器之间的连接结构示意图；
图10为本公开实施例提供的光电传感器位于桥区时，显示基板各膜层的结构示意图；
图11为本公开实施例提供的一种第一电极层的具体结构示意图；
图12为本公开实施例提供的一种光电传感器位于岛区和桥区之间的各膜层的侧壁的结构示意图；
图13为本公开实施例提供的另一种光电传感器位于岛区和桥区之间的各膜层的侧壁的结构示意图；
图14a～图14o为本公开实施例提供的显示基板的制备流程示意图。
其中附图标记为：显示基板100；衬底基板01；电路层02；光电传感器03；第一电极层31；第一子结构311；第二子结构312；第三子结构313；光电结构层32；第二电极层33；第一薄膜晶体管T1；孔区的过孔Via0；缓冲层21；第一绝缘层22；第二绝缘层23；第三绝缘层24；第一薄膜晶体管T1的有源层T11；第一薄膜晶体管T1的栅极T12；第一薄膜晶体管T1的源极T13；第一薄膜晶体管T1的漏极T14；第一薄膜晶体管T1的有源层T11的源区T11a；第一薄膜晶体管T1的有源层T11的漏区T11b；第一连接过孔Via1；第二连接过孔Via2；玻璃子基底11；柔性子基底12；模量材料13；发光器件04；第三电极层41；发光层42；第四电极层43；第二薄膜晶体管T2的有源层T21；第二薄膜晶体管T2的栅极T22；第二薄膜晶体管T2的源极T23；第二薄膜晶体管T2的漏极T24；第二薄膜晶体管T2的有源层T21的源区T21a；第一薄膜晶体管T2的有源层T21的漏区T21b；第四连接过孔Via4；第五连接过孔Via5；第六连接过孔Via6；封装膜层05。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要说明的是，在本公开中，两结构“同层设置”是指二者是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们与衬底基板间的距离相等，也不代表它们与衬底基板间的其它层结构完全相同。
以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
图1为本公开实施例提供的一种显示基板的各区结构示意图，图2为本公开实施例提供的一种光电传感器位于岛区的示意图，图3为本公开实施例提供的一种光电传感器位于桥区的示意图；如图1、图2和图3所示，显示基板具有岛区、孔区和桥区；显示基板100包括衬底基板01，设置在衬底基板01上的电路层02。
本公开实施例提供的显示基板为一种可拉伸的显示基板100。可拉伸的显示基板设置有一系列的微孔结构，也即位于孔区的过孔Via0。该过孔Via0将可拉伸的显示基板100分为岛区和桥区。岛区用于图像显示；过孔Via0用于在显示基板100被拉伸时提供变形空间，同时，还用于透过光线；桥区用于走线和传递拉力。如图1所示，其中，OLED(Organic light-emitting diode)以及光电传感器的驱动电路位于岛区，沿着垂直于可拉伸的显示面板100的方向施加外力时，桥区发生形变而实现拉伸，同时透过过孔Via0的光线发生改变。
电路层02包括位于岛区的驱动电路、位于孔区的过孔Via0；电路层02还 包括与驱动电路电连接的至少一个光电传感器03；光电传感器03包括叠层设置的第一电极层31、光电结构层32和第二电极层33。
如图2所示，光电传感器03位于岛区，且光电传感器03的第一电极层31、光电结构层32和第二电极层33沿岛区指向桥区的方向上依次设置。
如图3所示，光电传感器03位于桥区，且光电传感器03的第一电极层31、光电结构层32和第二电极层33沿桥区指向岛区的方向上依次设置。
需要说明的是，孔区的过孔Via0位于岛区和桥区之间，且孔区的过孔Via0沿垂直衬底基板01方向贯穿电路层02。光电传感器03在电路层02的位置靠近孔区，且第一电极层31、光电结构层32和第二电极层33依次靠近孔区的过孔Via0。示例性的，光电传感器03可以为有机光电二极管(Organic-Photo-Diode，OPD)。第一电极层31为光电传感器03的阳极，第二电极层33为光电传感器03的阴极，且第二电极层33为透明电极层，可以透过第二电极层33接收到来自孔区过孔Via0的光线。
在本公开的实施例中，将光电传感器03集成到可拉伸显示基板100的可拉伸岛区和/或桥区内，光电传感器03能够利用孔区内过孔Via0经拉伸变化后的光照变化，实现拉伸状态监测，而显示基板100可用于可拉伸显示，电子皮肤等显示。另外，光电传感器03的第一电极层31、光电结构层32和第二电极层33沿从岛区指向桥区的方向层叠设置，也即光电传感器03各结构横向排布，不仅能够适用于可拉伸背板，而且能够降低占用面积，与传统OPD集成方式(通常OPD与有机发光电致二极管(Organic Light-Emitting Diode，OLED)同层设置)相比，能够提高显示分辨率，提高开口率。
在满足第二电极层33能够接收到孔区的过孔Via0的光线的条件下，光电传感器03可以设置在岛区或桥区的任意位置。但是，为了能够更充分的降低占用面积，提高光学传感器的灵敏度，将光电传感器03设置在电路层02靠近孔区的位置，例如，可以嵌入在电路层02中，也可以铺设在位于岛区或位于桥区各膜层的侧壁等。
在本公开的实施例中，设置在显示基板100上的光电传感器03可以通过不 同的方式进行制备，下面以利用溶液法制备得到的光电传感器03为例对本公开实施例提供的显示基板100的各个结构进行详细说明。
在一些示例中，由于岛区不易变形，且设置有多种不同的薄膜晶体管，为了便于电路连接，将光电传感器03设置在位于岛区的电路层02中。图4为本公开实施例提供的光电传感器位于岛区时，显示基板各膜层的结构示意图，如图4所示，光电传感器03位于岛区；电路层02包括位于岛区的第一薄膜晶体管T1，位于岛区且依次设置在衬底基板01上的缓冲层21、第一绝缘层22、第二绝缘层23和第三绝缘层24。第一薄膜晶体管T1包括有源层T11、栅极T12、源极T13和漏极T14；有源层T11设置在缓冲层21背离衬底基板01的一侧；栅极T12设置在第一绝缘层22背离衬底基板01的一侧，且栅极T12与有源层T11在衬底基板01上的正投影至少部分交叠；源极T13和漏极T14设置在第二绝缘层23背离衬底基板01的一侧，源极T13通过第一连接过孔Via1与有源层T11的源区T11a电连接，漏极T11b通过第二连接过孔Via2与有源层T11的漏区T11b电连接。
本公开实施例提供的第一薄膜晶体管T1的有源层的材料可以为半导体材料，例如可以包括低温多晶硅，或者氧化物等，而在实际应用中可以根据需求限定，本公开实施例不进行具体限定。
光电传感器03与第一绝缘层22、第二绝缘层23或第三绝缘层24中的任意一层同层；或者，光电传感器03位于第一绝缘层22、第二绝缘层23和第三绝缘层24中的任意相邻两层之间，例如，位于第一绝缘层22背离衬底基板01的表面上，换言之，嵌入在第二绝缘层23中。其中，图4仅示出了光电传感器03与第一绝缘层22同层的示意图。
本公开实施例提供的衬底基板01可以为柔性基板，该衬底基板01可以采用单层基底，也可以采用多层基底。若采用多层基底，衬底基板01包括叠层设置的玻璃子基底11和柔性子基底12(采用柔性材料热塑性聚酰亚胺(Polyimide，PI)材料的基底)。
在一个示例中，孔区过孔Via0除了贯穿电路层02之外，还贯穿缓冲层21和衬底基板01的柔性子基底12。在另一个示例中，如图4所示，孔区过孔Via0 除了贯穿电路层02之外，还贯穿缓冲层21和衬底基板01的柔性子基底12，并在柔性子基底12的过孔处填充低模量材料13，能够提高显示基板100的拉伸性能。
缓冲层21通常采用无机材料制作，例如氧化硅、氮化硅等材料，以达到阻水氧和阻隔碱性离子的效果，因此缓冲层21的硬度较大且厚度较大，在显示基板100被拉伸时，缓冲层21较难被拉伸，且缓冲层21具有较大的应力，尤其容易在缓冲层21对应岛区和桥区的边缘产生裂纹，若裂纹的数量较多，缓冲层21将受损从而导致显示基板100受损，在本公开实施例提供的显示基板100中，通过过孔Via0以达到在缓冲层21上设置开口的目的，能够释放缓冲层21在拉伸时累积的应力，避免缓冲层21因拉伸产生裂纹，从而避免显示基板100受损，提高显示基板100的可拉伸性。
第一绝缘层22的材料只要是能满足第一薄膜晶体管T1的有源层T11和栅极T12之间绝缘的材料即可，本公开实施例不进行具体限定。第一绝缘层22可以为第一栅绝缘(Gate Insulator，简称GI)层GI1。
第二绝缘层23用于保护第一薄膜晶体管T1的栅极T12与其他金属结构(例如第一薄膜晶体管T1的源极T13和漏极T14)之间绝缘，第二绝缘层23可以采用单层绝缘层，例如第二栅绝缘层GI2；或者，也可以采用多层叠层设置的子绝缘层，例如叠层设置的第二栅绝缘层GI2和层间绝缘(Inter-Layer Dielectric，简称ILD)层。本公开的实施例对第二绝缘层23的材料不进行具体限定。
第三绝缘层24用于保护第一薄膜晶体管T1的源极T13和漏极T14。第三绝缘层24可以采用两层绝缘层，例如叠层设置的一层钝化(Passivation，简称PVX)层和一层第一平坦层PLN1；或者，也可以采用更多层叠层设置的子绝缘层，例如叠层设置的钝化层PVX、第一平坦(Plain，简称PLN)层PLN1和第二平坦层PLN2。
需要说明的是，不同光电传感器03可以与不同绝缘层同层，多个光电传感器03接收拉伸孔区变化后的光线，能够提高检测精度。不同的光电传感器03可以设置在不同高度的位置，用以检测孔区过孔Via0不同位置的光线。
在一些示例中，驱动电路包括用于驱动光电传感器03的第一薄膜晶体管，图5为本公开实施例提供的一种光电传感器的驱动电路示意图，如图5所示，其中，第一薄膜晶体管T1的源极T13与外部信号源电连接(未在图5中示出，该外部信号源可以是能够提供固定电压的信号源)，第一薄膜晶体管T1的漏极T14与光电传感器03的第一电极层31电连接，光电传感器03的光电结构层32包括光电二极管PIN和电容C，光电二极管PIN和电容C并联，且并联第一端N1与第一电极层31连接，并联第二端N2与第二电极层33连接。示例性的，第一电极层31为光电传感器03的阳极，第二电极层33为光电传感器03的阴极，接入低电源电压VSS。
图6为本公开实施例提供的光电传感器位于岛区时，第一薄膜晶体管的漏极与光电传感器之间的连接结构示意图，如图6所示，第一薄膜晶体管的漏极与光电传感器03的第一电极层31电连接，在一些实施方式中，第一薄膜晶体管的漏极复用为第一电极层31，换言之，第一薄膜晶体管的漏极与第一电极层31一体形成。
示例性的，第一薄膜晶体管的漏极的为钛(Ti)-铝(Al)-钛(Ti)金属合成层，也即第一电极层31为钛(Ti)-铝(Al)-钛(Ti)金属合成层。当然，本公开实施例对第一薄膜晶体管的漏极的材料不进行限定，除了为钛(Ti)-铝(Al)-钛(Ti)金属合成层之外，还可以是其他可行性的材料，具体可以根据经验和实际场景限定，对此本公开实施例不进行一一列举。
这里，由于第一薄膜晶体管的漏极可以直接复用为光电传感器03的第一电极层31，因此，在工艺制备阶段，可以直接制备一层金属电极层，能够提高制备效率。
需要说明的是，光电传感器03与第一薄膜晶体管的漏极可以同层设置，如图6所示，光电传感器03设置在第三绝缘层24中的第一平坦层PLN1背离衬底基板01的一侧，也即位于第三绝缘层24中的第二平坦层PLN2中。当然，光电传感器03也可以与除第二平坦层PLN2以外的其他层同层，即设置在该层中，例如第一绝缘层22、第二绝缘层23中的第二栅绝缘层GI2、第二绝缘层23中的层间绝缘层ILD、第三绝缘层24中的钝化层PVN和第一平坦层PLN1中的任 意一层同层，而其他同层设置的方式本公开实施例不再一一列举。又或者，光电传感器03也可以位于第一绝缘层22、第二绝缘层23中的第二栅绝缘层GI2、第二绝缘层23中的层间绝缘层ILD、第三绝缘层24中的钝化层PVX、第三绝缘层24中的第一平坦层PLN1和第三绝缘层24中的第二平坦层PLN2中的任意相邻两层之间，在此本公开实施例也不再一一列举。在光电传感器03与第一薄膜晶体管的漏极不同层时，如图4所示，第一薄膜晶体管T1的漏极T14可以通过连接过孔与光电传感器03的第一电极层31电连接。
在一些示例中，驱动电路包括用于驱动光电传感器03的第一薄膜晶体管，图7为本公开实施例提供的另一种光电传感器的驱动电路示意图，如图7所示，其中，第一薄膜晶体管T1的源极T13和漏极T14分别与外部信号源电连接(未在图7中示出，该外部信号源可以是能够提供固定电压的信号源)，第一薄膜晶体管T1的栅极T12与光电传感器03的第一电极层31电连接，光电传感器03的光电结构层32包括光电二极管PIN和电容C，光电二极管PIN和电容C并联，且并联第一端N1与第一电极层31连接，并联第二端N2与第二电极层33连接。示例性的，第一电极层31为光电传感器03的阳极，第二电极层33为光电传感器03的阴极，接入低电源电压VSS。
图8为本公开实施例提供的光电传感器位于岛区时，第一薄膜晶体管的栅极与光电传感器之间的连接结构示意图，如图8所示，第一薄膜晶体管T1的栅极T12与光电传感器03的第一电极层31电连接，，在一些实施方式中，第一薄膜晶体管的栅极复用为第一电极层31，图8为第一薄膜晶体管T1的栅极T12与光电传感器03之间连接关系示意图，图8未示出第一薄膜晶体管T1的栅极T12与第一电极层31的具体连接结构。
示例性的，第一薄膜晶体管的栅极的材料可以为钼(Mo)，或者其他可行性的材料，对此本公开实施例不进行具体限定。
这里，由于第一薄膜晶体管T1的栅极T12可以直接复用为光电传感器03的第一电极层31，因此，在工艺制备阶段，可以直接制备一层栅极层，能够提高制备效率。
需要说明的是，光电传感器03与第一薄膜晶体管T1的栅极T12可以同层 设置，如图8所示，光电传感器03设置在第一绝缘层22背离衬底基板01的一侧，也即设置在第二绝缘层23中的第二栅绝缘层GI2中。当然，光电传感器03也可以与除第二绝缘层23中的第二栅绝缘层GI2以外的其他层同层，例如第一绝缘层22、第二绝缘层23中的层间绝缘层ILD、第三绝缘层24中的钝化层PVX、第三绝缘层24中的第一平坦层PLN1和第三绝缘层24中的第二平坦层PLN2中的任意一层同层，即，将光电传感器设置在该层中，而其他同层设置的方式本公开实施例不再一一列举。又或者，光电传感器03也可以位于第一绝缘层22、第二绝缘层23中的第二栅绝缘层GI2、第二绝缘层23中的层间绝缘层ILD、第三绝缘层24中的钝化层PVX、第三绝缘层24中的第一平坦层PLN1和第三绝缘层24中的第二平坦层PLN2中的任意相邻两层之间，在此本公开实施例也不再一一列举。在光电传感器03与第一薄膜晶体管T1的栅极T12不同层时，第一薄膜晶体管T1的栅极T12可以通过连接过孔与光电传感器03的第一电极层31电连接。
在一些示例中，图9为本公开实施例提供的光电传感器位于岛区时，发光器件与光电传感器之间的连接结构示意图。如图9所示，电路层02背离衬底基板01一侧设置有发光器件04；发光器件04包括第三电极层41、第四电极层43，以及设置在第三电极层41和第四电极层43之间的发光层42；第三电极层41复用为第一电极层31，第四电极层43复用为第二电极层33。
第三电极层41为发光器件04的阳极AND、第四电极层43为发光器件04的阴极。第三电极层41的为氧化铟锡(ITO)-银(Ag)-氧化铟锡(ITO)合成层，也即第一电极层31为氧化铟锡ITO-银Ag-氧化铟锡ITO合成层。第四电极层43的材料为镁(Mg)或银(Ag)，也即第二电极层33的材料为镁(Mg)或银(Ag)。
发光层42包括第一空穴传输层HTL1和第一激子阻挡层ETL1。
在电路层02背离衬底基板01上设置像素界定层PDL(Pixel Definition Layer)，在像素界定层PDL背离衬底基板01一侧依次设置发光层42和第四电极层43。
驱动电路还包括用于驱动发光器件的第二薄膜晶体管T2，第二薄膜晶体管T2的源极T23与第三电极层41电连接，第二薄膜晶体管T2的有源层T21设置 在缓冲层21背离衬底基板01的一侧，第二薄膜晶体管T2的栅极T22设置在第一绝缘层22背离衬底基板01的一侧，且第二薄膜晶体管T2的栅极T22与第二薄膜晶体管T2的有源层T1在衬底基板01上正投影至少部分交叠；第二薄膜晶体管T2的源极T23和第二薄膜晶体管T2的漏极T24设置在第二绝缘层23背离衬底基板01的一侧，第二薄膜晶体管T2的源极T23的第一端通过第四连接过孔Via4与第二薄膜晶体T2的有源层T21的源区T21a电连接，第二薄膜晶体管T2的漏极T24通过第五连接过孔Via5与第二薄膜晶体管T2的有源层T21的漏区T21b电连接；第二薄膜晶体管T2的源极T23的第二端通过第六连接过孔Via6与第三电极层41电连接。
这里，由于第三电极层41可以直接复用为光电传感器03的第一电极层31，第四电极层43可以直接复用为光电传感器03的第二电极层33，因此，在工艺制备阶段，相互复用的电极层可以直接制备为一层，能够提高制备效率。当然，第一电极层31和第二电极层33也可以单独制备，不复用发光器件的第三电极层41和第四电极层43。
需要说明的是，如图9所示，光电传感器03与像素界定层PDL可以同层设置，也即光电传感器03设置在第三绝缘层24背离衬底基板01的一侧，相比分层设置，需要开设连接过孔的情况，同层设置能够提高制备效率，节省材料成本。当然，光电传感器03也可以与不同的绝缘层同层，本公开实施例不进行具体限定。
需要说明的是，第二薄膜晶体管有源层、源极、漏极和栅极的材料可以参照上述第一薄膜晶体管各结构具体材料的说明，重复部分不再赘述。
在一些实例中，第一电极层31设置为长方形结构，能够增强信号，防止信号光线上下分散，增大信噪比。
在一些示例中，由于桥区布线多为源极和漏极的驱动线，栅级驱动线较少，且OPD走线的噪声小，OPD材料可柔性，可耐桥区形变，因此，可以将光电传感器03设置在位于桥区的电路层02。以图5所示的驱动电路为例，图10为本公开实施例提供的光电传感器位于桥区时，显示基板各膜层的结构示意图，如图10所示，光电传感器03位于桥区；电路层02包括位于桥区且依次设置在 衬底基板01上的缓冲层21、第一绝缘层22和第三绝缘层24。
光电传感器03与第一绝缘层22或第三绝缘层24同层；或者，光电传感器03位于第一绝缘层22与第三绝缘层24之间，即，位于第一绝缘层22背离衬底基板01的表面上。图10示出了光电传感器03与第一绝缘层22同层的示意图。
这里，缓冲层21与上述图4示例中的缓冲层21的材料相同，功能相同；第一绝缘层22与上述图4示例中的第一绝缘层22的材料相同，功能相同；第三绝缘层24与上述图4示例中的第三绝缘层24的材料相同，功能相同，重复部分在此不再赘述。
在一些示例中，在位于桥区的第一绝缘层22中设置有至少一个第三连接过孔Via3，如图10所示，若在第三连接过孔Via3处设置有第一薄膜晶体管T1的漏极T14，此时，第一薄膜晶体管T1的漏极T14与位于桥区的第一绝缘层22同层，光电传感器03的第一电极层31与第一薄膜晶体管T1的漏极T14电连接，在一些实施方式中，第一薄膜晶体管T1的漏极T14复用为光电传感器03的第一电极层31。
若在第三连接过孔处设置有第一薄膜晶体管的栅极，此时，第一薄膜晶体管的栅极与位于桥区的第一绝缘层22同层，光电传感器03的第一电极层31可以与第一薄膜晶体管T1的栅极T12电连接，在一些实施方式中，第一薄膜晶体管T1的栅极T12复用为光电传感器03的第一电极层31。
在一些示例中，图11为本公开实施例提供的一种第一电极层的具体结构示意图，如图11所示，以光电传感器03与第三绝缘层24同层为优选设置方式，且设置在第一平坦层PLN1和第二平坦层PLN2之间为例，这里的第三绝缘层24即可以是位于岛区的第三绝缘层24，也可以是位于桥区的第三绝缘层24。第一电极层31包括第一子结构311、第二子结构312以及连接第一子结构311和第二子结构312的第三子结构313；第一子结构311、第三子结构313和第二子结构312沿衬底基板01指向电路层02的方向依次设置。
其中，第一子结构311和第二子结构312为梯形结构，其中，第一子结构311为正直角梯形，第二子结构312为倒的直接梯形；第三子结构313为长方形 结构，如此设置能够增强信号，防止信号光线上下分散，增大信噪比。具体地，可以通过曝光刻蚀第一平坦层PLN1和第二平坦层PLN2为梯形结构后，沉积形成图11所示的梯形的第一子结构311和第二子结构312。如图11所示，第一子结构311、第二子结构312的直角边和第三子结构313长边设置在同一侧，形成一个平面，从而第一子结构311、第二子结构312的斜边和第三子结构313另一长边设置在同一侧，因此形成的第一电极层31的一侧为凹面。
示例1、第二子结构312和第三子结构313，与第一薄膜晶体管T1的漏极T14电连接，第一薄膜晶体管T1的漏极T14复用为第二子结构312和第三子结构313。第一子结构311与第三电极层41电连接，且第三电极层41复用为第一子结构311。示例2、第一子结构311、第二子结构312和第三子结构313，均与第三电极层41电连接，第三电极层41同时复用为第一子结构311、第二子结构312和第三子结构313。示例3、第一薄膜晶体管T1的漏极T14同时复用为第一子结构311、第二子结构312和第三子结构313。
在本公开的实施例中，除了上述利用溶液法制备光电传感器03所得到的显示基板100的各个结构，下面以利用蒸镀法制备得到的光电传感器03为例对本公开实施例提供的显示基板100的各个结构进行详细说明。
在一些示例中，图12为本公开实施例提供的一种光电传感器位于岛区和桥区之间的各膜层的侧壁的结构示意图，如图12所示，孔区的过孔Via0位于岛区和桥区之间；光电传感器03位于岛区和桥区之间的各膜层的侧壁上；侧壁与衬底基板01呈预设倾角。
这里，预设倾角可以根据经验设定，本公开实施例不进行具体限定。
需要说明的是，岛区和桥区之间的各膜层的侧壁包括位于岛区的各膜层的侧壁和位于桥区的各膜层的侧壁。
在位于岛区的各膜层的侧壁上沿岛区指向桥区，依次层叠设置第一电极层31、光电结构层32和第二电极层33，和/或，在位于桥区的各膜层的侧壁上沿桥区指向岛区，依次层叠设置第一电极层31、光电结构层32和第二电极层33。
在本公开的实施例中，可以利用第一薄膜晶体管T1的漏极T14复用为第一 电极层31；或者，第一薄膜晶体管T1的栅极T12复用为第一电极层31；或者，第三电极层41复用为第一电极层31。具体结构连接实例可以参见上述利用溶液法制作光电传感器对应的显示基板100的各个结构，重复部分再次不在赘述。
如图12所示，以图5所示的驱动电路为例，第一薄膜晶体管T1的漏极T14与第一电极层31电连接，且第一薄膜晶体管T1的漏极T14复用为第一电极层31。
在一些示例中，图13为本公开实施例提供的另一种光电传感器位于岛区和桥区之间的各膜层的侧壁的结构示意图，如图13所示，孔区的过孔位于岛区和桥区之间；光电传感器03包括多级光电结构；多级光电结构位于岛区和桥区之间的各膜层的侧壁上；第i级光电结构的第一子光电结构与第i-1级光电结构的第二子光电结构连接；第i级光电结构的第二子光电结构与第i+1级光电结构的第一子光电结构连接；0＜i≤N，N为大于或等于2的正整数。例如，如图13所示，位于岛区侧壁上的光电传感器03包括4级光电结构I-IV，其中，第I级光电结构包括第一子光电结构I1和第二光电结构I2，第II级光电结构包括第一子光电结构II1和第二光电结构II2,第III级光电结构包括第一子光电结构III1和第二光电结构III2,第IV级光电结构包括第一子光电结构IV1。第II级光电结构的第一子光电结构II1与第I级光电结构的第二子光电结构I2连接，第II级光电结构的第二子光电结构II2与第III级光电结构的第一子光电结构III1连接。第i级光电结构的第一子光电结构与第i-1级光电结构的第二子光电结构之间的夹角位于85°～105°之间；第i级光电结构的第二子光电结构与第i+1级光电结构的第一子光电结构之间的夹角范围位于85°～105°之间；第i级光电结构的第一子光电结构与第i级光电结构的第二子光电结构之间的夹角位于85°～105°之间。
示例性的，为了便于制备，任意相连的第一子光电结构与第二子光电结构之间的夹角可以设置为90°。当然，本领域人员应该知道任意相连的第一子光电结构与第二子光电结构之间所呈拐角可以位于90°拐角所在误差允许的范围内。
多级光电结构组成阶梯状的光电结构，此时位于岛区和桥区之间的各膜层 的侧壁同样设置为阶梯状结构，以适配阶梯状的多级光电结构。
在本公开的实施例中，在位于岛区和桥区之间的各膜层的侧壁上具有较大的斜坡或者阶梯状，能够增大光电传感器03的表面积，增大信号强度，且不占用电路层02的面积，进而提高显示分辨率和开口率。
在一些示例中，电路层02背离衬底基板01一侧设置有发光层；发光层包括第一空穴传输层HTL1和第一激子阻挡层ETL1；光电结构层32包括沿第一电极层31指向第二电极层33，依次叠层设置的第二空穴传输层HTL2、第二激子阻挡层ETL2和光电材料层(也即OPD材料层)；第一空穴传输层HTL1与第二空穴传输层HTL2连接，且第一空穴传输层HTL1复用为第二空穴传输层HTL2；第一激子阻挡层ETL1与第二激子阻挡层ETL2连接，且第一激子阻挡层ETL1复用为第二激子阻挡层ETL2。
发光层中的第一空穴传输层HTL1和第一激子阻挡层ETL1，沿第三电极层指向第四电极层方向上依次叠置。
如图12所示，光电结构层32中的第二空穴传输层HTL2、第二激子阻挡层ETL2和光电材料层，共同组成了光电二极管PIN和电容C。
这里，第一空穴传输层HTL1复用为第二空穴传输层HTL2、第一激子阻挡层ETL1复用为第二激子阻挡层ETL2，能够节省设备和材料等成本。
在一些示例中，显示基板100的外侧，也即各个位于岛区和桥区各个膜层的外壁，设置封装膜层05。封装膜层05例如四氟乙烯TFE材料的膜层。图14o中仅示出了设置在岛区外侧的封装膜层05。
基于同一发明构思，本公开实施例中还提供了一种显示基板100的制备方法，由于本公开实施例中显示基板100的制备方法所解决问题的原理与本公开实施例上述显示基板100相似，因此显示基板100的制备方法中显示基板100的各个结构可以参见上述实施例提供的显示基板100，重复之处不再赘述。
在本公开的实施例中，提供了一种显示基板100的制备方法，其中，显示基板100具有岛区、孔区和桥区，显示基板100的制备方法包括：在衬底基板01上形成电路层02；在电路层02上形成位于岛区的驱动电路、以及位于孔区 的过孔；在电路层02上还形成与驱动电路电连接的至少一个光电传感器03；光电传感器03包括叠层设置的第一电极层31、光电结构层32和第二电极层33；光电传感器03位于岛区，且光电传感器03的第一电极层31、光电结构层32和第二电极层33沿岛区指向桥区的方向上依次设置；和/或，光电传感器03位于桥区，且光电传感器03的第一电极层31、光电结构层32和第二电极层33沿桥区指向岛区的方向上依次设置。
在本公开的实施例中，将光电传感器03集成到位于可拉伸岛区和/或桥区的显示基板100内，拉伸显示基板100，光电传感器03能够利用孔区内过孔Via0经拉伸变化后的光照变化，实现拉伸状态监测，可用于可拉伸显示，电子皮肤等显示。另外，光电传感器03中第一电极层31、光电结构层32和第二电极层33，沿岛区和桥区之间的指向层叠设置，也即光电传感器03各结构横向排布，能够降低占用面积，进而提高显示分辨率，提高开口率。
在一些示例中，以溶液法制备光电传感器03，为了进一步清楚的描述每一膜层的制备，以图5的驱动电路为例，下面以步骤S1～S15进行详细阐述，图14a～图14o为本公开实施例提供的显示基板的制备流程示意图：
S1、在衬底基板01上形成缓冲层21，并刻蚀位于孔区的缓冲层21，形成贯穿缓冲层21的过孔Via0，如图14a所示。
在一些示例中，衬底基板01包括玻璃子基底11和柔性子基底12，孔区在衬底基板01上的正投影所在区域，形成贯穿柔性子基底12的过孔，并在贯穿柔性子基底的过孔内填充低模量材料13。
可以采用化学气相沉积(Chemical Vapor Deposition，CVD)或原子层沉积(Atomic Layer Deposition，ALD)的方式，沉积缓冲层21。
需要说明的是，在衬底基板01上，同时制备位于岛区和桥区的缓冲层21。
S2、在缓冲层21背离衬底基板01的一侧形成第一薄膜晶体管T1的有源层T11和第二薄膜晶体管T2的有源层T21，如图14b所示。
具体地，首先，在衬底基板01上沉积一层半导体层；之后，在该半导体层背离衬底基板01的一侧涂覆光刻胶并进行曝光、显影、刻蚀、剥离等工艺制备， 得到第一薄膜晶体管T1的有源层T11和第二薄膜晶体管T2的有源层T21。半导体层可以采用CVD或ALD的方式，在衬底基板01上进行沉积。
S3、在第一薄膜晶体管T1的有源层T11背离衬底基板01一侧形成第一绝缘层22(也即第一栅绝缘层)，并在第一薄膜晶体管T1的有源层T11的源区T11a和漏区T11b正投影所在区域，形成贯穿第一绝缘层22的第一连接过孔Via1和第二连接过孔Via2；在第二薄膜晶体管T2的有源层T21的源区T21a和漏区T21b正投影所在区域，形成贯穿第一绝缘层22的第四连接过孔Via4和第五连接过孔Via5，如图14c所示。
第一绝缘层22可以为第一栅绝缘层GI1，用于保护第一薄膜晶体管T1的有源层T11。
由于最终形成的显示基板具有多层绝缘层，且该多层绝缘层具有较深的深度，一次贯穿多层绝缘层进行打孔工艺较难，因此，本公开实施例采取同一连接过孔分批次打通的方式。一种情况，为了降低打孔工艺难度，在每沉积一层绝缘层的情况下，贯穿该绝缘层形成连接过孔的子连接过孔，例如，在沉积一层第一栅绝缘层GI1后，在第一薄膜晶体管T1的有源层T11的源区T11a和漏区T11b正投影所在区域，形成贯穿第一绝缘层22的第一连接过孔Via1和第二连接过孔Via2，依次类推，在沉积另一层绝缘栅后，在第一薄膜晶体管T1的有源层T11的源区T11a和漏区T11b正投影所在区域，形成贯穿该绝缘层的第一连接过孔Via1和第二连接过孔Via2。另一种情况，针对贯穿多层绝缘层的连接过孔，为了降低打孔工艺难度，同时，也为了减少打孔次数，提高显示基板100的制备效率。在沉积两层或两层以上绝缘层之后，再执行打孔制备过程。具体打孔制备过程可以参照上述每沉积一层绝缘层执行的打孔过程。
需要说明的是，在衬底基板01上，同时制备位于岛区和桥区的第一绝缘层22。
S4、在岛区，在第一绝缘层22背离衬底基板01的一侧形成第一薄膜晶体管T1的栅极T12和第二薄膜晶体管T2的栅极T22，且第一薄膜晶体管T1的栅极T12与第一薄膜晶体管T1的有源层T11在衬底基板01上的正投影交叠；第二薄膜晶体管T2的栅极T22与第二薄膜晶体管T2的有源层T21在衬底基板01 上的正投影交叠，如图14d。
本步骤中的沉积第一薄膜晶体管T1的栅极的实施，参见S2沉积第一薄膜晶体管T1的有源层T11的实施，具体制备原理不再赘述。
S5、在第一薄膜晶体管T1的栅极T12背离衬底基板01的一侧形成第二栅绝缘层GI2，并在第一薄膜晶体管T1的有源层T11的源区T11a和漏区T11b正投影所在区域，形成贯穿第二栅绝缘层GI2的第一连接过孔Via1和第二连接过孔Via2；在第二薄膜晶体管T2的有源层T21的源区T21a和漏区T21b正投影所在区域，形成贯穿第二栅绝缘层GI2的第四连接过孔Via4和第五连接过孔Via5，如图14e所示。
第二栅绝缘层GI2用于保护第一薄膜晶体管T1的栅极T12和第二薄膜晶体管T2的栅极T22。
S6、在第二栅绝缘层GI2背离衬底基板01的一侧形成层间绝缘层ILD，并在第一薄膜晶体管T1的有源层T11的源区T11a和漏区T11b正投影所在区域，形成贯穿层间绝缘层ILD的第一连接过孔Via1和第二连接过孔Via2；在第二薄膜晶体管T2的有源层T21的源区T21a和漏区T21b正投影所在区域，形成贯穿层间绝缘层ILD的第四连接过孔Via4和第五连接过孔Via5，如图14f所示。
S7、在层间绝缘层ILD背离衬底基板01的一侧形成第一薄膜晶体管T1的源极T13和漏极T14，以及形成第二薄膜晶体管T2的源极T23和漏极T24，其中，第一薄膜晶体管T1的源极T13通过第一连接过孔Via1与第一薄膜晶体管T1的源区T11a电连接，第一薄膜晶体管T1的漏极T14通过第二连接过孔Via2与第一薄膜晶体管T1的漏区T11b电连接；第二薄膜晶体管T2的源极T23通过第四连接过孔Via4与第二薄膜晶体管T2的源区T21a电连接，第二薄膜晶体管T2的漏极T24通过第五连接过孔Via5与第二薄膜晶体管T2的漏区T21b电连接，如图14g所示。
本步骤的沉积第一薄膜晶体管T1的源极T13和漏极T14的实施，参见S2沉积第一薄膜晶体管T1的有源层T11的实施，具体制备原理不再赘述。
S8、在层间绝缘层ILD、第一薄膜晶体管T1的源极T13和漏极T14、第二 薄膜晶体管T2的源极T23和漏极T24背离衬底基板01一侧形成钝化层PVX，如图14h所示。
钝化层PVX覆盖第一薄膜晶体管T1的源极T13和漏极T14以及第二薄膜晶体管T2的源极T23和漏极T24，用于保护第一薄膜晶体管T1的源极T13和漏极T14以及第二薄膜晶体管T2的源极T23和漏极T24。
S9、在钝化层PVX背离衬底基板01一侧形成第一平坦层PLN1，并在第一薄膜晶体管T1的源极T13和漏极T14的正投影所在区域，形成贯穿第一平坦层PLN1的第一连接过孔Via1和第二连接过孔Via2，在第二薄膜晶体管T2的源极T23和漏极T24的正投影所在区域，形成贯穿第一平坦层PLN1的第四连接过孔Via4和第五连接过孔Via5，如图14i所示。
需要说明的是，在衬底基板01上，同时制备位于岛区和桥区的第一平坦层PLN1，其中，在桥区，在第一栅绝缘层GI1背离衬底基板01的一侧形成第一平坦层PLN1。
S10、在第一平坦层PLN1背离衬底基板01的一侧形成第一薄膜晶体管T1的源极T13和漏极T14以及第二薄膜晶体管T2的源极T23和漏极T24，其中，第一薄膜晶体管T1的源极T13通过第一连接过孔Via1与位于钝化层PVX处的第一薄膜晶体管T1的源极T13电连接，第一薄膜晶体管T1的漏极T14通过第二连接过孔Via2与位于钝化层PVX处的第一薄膜晶体管T1的漏极T14电连接；第二薄膜晶体管T2的源极T23通过第四连接过孔Via4与位于钝化层PVX处的第二薄膜晶体管T2的源极T23电连接，第二薄膜晶体管T2的漏极T24通过第五连接过孔Via5与位于钝化层PVX处的第二薄膜晶体管T2的漏极T24电连接。另外，第一薄膜晶体管T1的漏极T14复用为光电传感器03的第一电极层31。
此时，光电传感器03位于第一平坦层PLN1背离衬底基板01的一侧，也即与下述第二平坦层PLN2同层，如图14j所示。
S11、在S10中制备的第一薄膜晶体管T1的源极T13和漏极T14背离衬底基板01的一侧形成第二平坦层PLN2，并在第二平坦层PLN2上曝光刻蚀图形化排版后，留出光电传感器03待涂布的光电结构层32的过孔321以及第二电 极层33的过孔331,如图14k所示。
在S14制备发光器件的同时，在预留的过孔内涂布光电传感器03的光电结构层32，光电结构层32包括第二空穴传输层HTL2、光电材料层(OPD材料)和第二激子阻挡层ETL2，其中，第二激子阻挡层也可以为油墨材料，可以直接利用油墨进行打印，之后，进行涂光刻胶布，利用氧气进行刻蚀以形成图案，最后沉积ITO或Mg或Ag材料作为第二电极层33。
需要说明的是，在衬底基板01上，同时制备位于岛区和桥区的第二平坦层PLN2；而且可以同时在岛区和桥区分别制备光电传感器03。
S12、在S10中制备的第二薄膜晶体管T2的源极T23正投影所在区域形成贯穿第二平坦层PLN2的第六连接过孔Via6，并在第二平坦层PLN2背离衬底基板01一侧形成发光器件的第三电极层41，该第三电极层41通过第六连接过孔Via6与第二薄膜晶体管T2的源极T23电连接，如图14l所示。
S13、在第二平坦层PLN2背离衬底基板01的一侧形成像素界定层PDL，并在设定位置形成开槽，例如，在像素界定层PDL的对应第三电极层41的位置处形成过孔，以露出所述第三电极层41，如图14m所示。
需要说明的是，仅在位于岛区的第二平坦层PLN2背离衬底基板01一侧形成像素界定层PDL。
S14、在像素界定层PDL背离衬底基板01的一侧依次形成发光器件的发光层42和第四电极层43，如图14n所示。
发光器件04包括第三电极层41、第四电极层43和发光层42。第三电极层41为阳极，第四电极层43为阴极，发光层42包括第一空穴传输层HTL1和第一激子阻挡层ETL1，其中，在像素界定层PDL背离衬底基板01的一侧依次沉积第一空穴传输层HTL1、第一激子阻挡层ETL1和第四电极层43，第一空穴传输层HTL1复用为光电传感器03的第二空穴传输层HTL2，第一激子阻挡层ETL1复用为光电传感器03的第二激子阻挡层ETL2，而具体被复用的连接结构，图14n并未示出。
需要说明的是，在制备第一空穴传输层HTL1、第一激子阻挡层ETL1和第 四电极层43时，同时涂布光电传感器03的光电结构层32和第二电极层33，具体制备过程如S11所述。
S15、在位于岛区和桥区各个膜层的外壁形成封装膜层05，如图14o所示，该图中仅示出了岛区的封装膜层05。
在一些示例中，如图12所示，以蒸镀法制备光电传感器03，为了进一步清楚的描述每一膜层的制备，以图5的驱动电路为例，在按照步骤S1～S14的制备过程制备了第一薄膜晶体管T1、第二薄膜晶体管T2和发光器件04后，在位于岛区和桥区之间的各膜层的侧壁蒸镀光电传感器03。位于岛区的光电传感器03包括沿岛区指向桥区依次叠置的第一电极层31、第二空穴传输层HTL2(例如HTL材料)、光电材料层(例如OPD发光材料)、第二激子阻挡层ETL2(例如ETL材料)和第二电极层33。位于桥区的光电传感器03包括沿桥区指向岛区依次叠置第一电极层31、第二空穴传输层HTL2、光电材料层、第二激子阻挡层ETL2和第二电极层33。
其中，第一薄膜晶体管T1的漏极T14复用为光电传感器03的第一电极层31(阳极)，发光器件04的第一空穴传输层HTL1复用为光电传感器03的第一空穴传输层HTL1，在第一空穴传输层HTL1靠近孔区过孔一侧沉积光电材料层，发光器件04的第一激子阻挡层ETL1复用为光电传感器03的第二激子阻挡层ETL2，发光器件04的第四电极层43复用为光电传感器03的第二电极层33。
若位于岛区和桥区之间的各膜层的侧壁与衬底基板01之间呈预设倾角，则蒸镀形成的光电传感器03为大斜坡状；若位于岛区和桥区之间的各膜层的侧壁为阶梯状，则蒸镀形成的光电传感器03为阶梯状，具体可以参见上述实施例中光电传感器03为阶梯状结构的实施例，具体如图13所示。
基于同一发明构思，本公开实施例中还提供了一种显示装置，包括上述实施例中的显示基板100。由于本公开实施例中显示装置所解决问题的原理与本公开实施例上述显示基板100相似，因此显示装置中包含的显示基板100的各个结构可以参见上述实施例提供的显示基板100，重复之处不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例 性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种显示基板，包括衬底基板和设置在衬底基板上的电路层，并且具有岛区、孔区和桥区；
    所述电路层包括位于所述岛区的驱动电路、位于所述孔区的过孔；所述电路层还包括与所述驱动电路电连接的至少一个光电传感器；所述光电传感器包括叠层设置的第一电极层、光电结构层和第二电极层；
    所述光电传感器位于所述岛区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述岛区指向所述桥区的方向上依次设置；和/或，所述光电传感器位于所述桥区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述桥区指向所述岛区的方向上依次设置。
  2. 根据权利要求1所述的显示基板，其中，所述驱动电路包括用于驱动所述光电传感器的第一薄膜晶体管，所述第一薄膜晶体管的漏极与所述光电传感器的第一电极层电连接。
  3. 根据权利要求2所述的显示基板，其中，所述第一薄膜晶体管的漏极复用为所述第一电极层。
  4. 根据权利要求1所述的显示基板，其中，所述驱动电路包括用于驱动所述光电传感器的第一薄膜晶体管，所述第一薄膜晶体管的栅极与所述光电传感器的第一电极层电连接.
  5. 根据权利要求4所述的显示基板，其中，所述第一薄膜晶体管的栅极复用为所述第一电极层。
  6. 根据权利要求1所述的显示基板，其中，所述电路层背离所述衬底基板的一侧设置有发光器件；所述发光器件包括第三电极层、第四电极层，以及设 置在所述第三电极层和所述第四电极层之间的发光层；
    所述第三电极层复用为所述光电传感器的第一电极层，所述第四电极层复用为所述光电传感器的第二电极层。
  7. 根据权利要求1-6中任一项所述的显示基板，其中，所述光电传感器位于所述岛区；所述电路层包括位于岛区的第一薄膜晶体管，和位于所述岛区且依次设置在所述衬底基板上的缓冲层、第一绝缘层、第二绝缘层和第三绝缘层；
    所述第一薄膜晶体管包括有源层、栅极、源极和漏极；所述有源层设置在所述缓冲层背离所述衬底基板的一侧；所述第一绝缘层设置在所述缓冲层背离所述衬底基板的一侧且覆盖所述第一薄膜晶体管的有源层；所述第一薄膜晶体管的栅极设置在所述第一绝缘层背离所述衬底基板的一侧，且所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的有源层在所述衬底基板上正投影至少部分交叠；所述第一薄膜晶体管的源极和漏极设置在所述第二绝缘层背离所述衬底基板的一侧，所述源极通过贯穿所述第一绝缘层和所述第二绝缘层的第一连接过孔与所述有源层的源区电连接，所述漏极通过贯穿所述第一绝缘层和所述第二绝缘层的第二连接过孔与所述有源层的漏区电连接；
    所述光电传感器与所述第一绝缘层、所述第二绝缘层或所述第三绝缘层中的任意一层同层；或者，所述光电传感器位于所述第一绝缘层、所述第二绝缘层和所述第三绝缘层中的任意相邻两层之间。
  8. 根据权利要求7所述的显示基板，其中，所述第一电极层包括第一子结构、第二子结构以及连接所述第一子结构和第二子结构的第三子结构；
    所述第一子结构、所述第三子结构和所述第二子结构沿所述衬底基板指向所述电路层的方向依次设置。
  9. 根据权利要求8所述的显示基板，其中，所述第一子结构为正梯形结构， 所述第二子结构为倒梯形结构，以及第三子结构为长方形结构。
  10. 根据权利要求8所述的显示基板，其中，所述第二子结构和所述第三子结构，与所述第一薄膜晶体管的漏极电连接，且所述第一薄膜晶体管的漏极复用为所述第二子结构和所述第三子结构；所述第一子结构与第三电极层电连接，且所述第三电极层复用为所述第一子结构。
  11. 根据权利要求7所述的显示基板，其中，所述第一电极层设置为长方形结构。
  12. 根据权利要求1-5中任一项所述的显示基板，其中，所述光电传感器位于所述桥区；所述电路层包括位于所述桥区且依次设置在所述衬底基板上的缓冲层、第一绝缘层和第三绝缘层；
    所述光电传感器与所述第一绝缘层或所述第三绝缘层同层；或者，所述光电传感器位于所述第一绝缘层与所述第三绝缘层之间。
  13. 根据权利要求12所述的显示基板，其中，所述驱动电路包括用于驱动所述光电传感器的第一薄膜晶体管，所述第一绝缘层中设置有第三连接过孔；并且其中
    所述第一薄膜晶体管的漏极通过所述第三连接过孔与所述第一电极层电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第一薄膜晶体管的漏极复用为所述第一电极层。
  15. 根据权利要求12所述的显示基板，其中，所述驱动电路包括用于驱动 所述光电传感器的第一薄膜晶体管，所述第一绝缘层中设置有第三连接过孔；并且其中
    所述第一薄膜晶体管的栅极通过第三连接过孔与所述第一电极层电连接。
  16. 根据权利要求15所述的显示基板，其中，所述第一薄膜晶体管的栅极复用为所述第一电极层。
  17. 根据权利要求1-6中任一项所述的显示基板，其中，所述孔区的过孔位于所述岛区和所述桥区之间；所述光电传感器位于所述岛区和所述桥区之间的各膜层的侧壁上；所述侧壁与所述衬底基板呈预设倾角。
  18. 根据权利要求1-6中任一项所述的显示基板，其中，所述孔区的过孔位于所述岛区和所述桥区之间；所述光电传感器包括多级光电结构；所述多级光电结构位于所述岛区和所述桥区之间的各膜层的侧壁上；
    第i级光电结构的第一子光电结构与第i-1级光电结构的第二子光电结构连接；所述第i级光电结构的第二子光电结构与第i+1级光电结构的第一子光电结构连接；0＜i≤N，N为大于或等于2的正整数；
    所述第i级光电结构的第一子光电结构与所述第i-1级光电结构的第二子光电结构之间的夹角范围位于85°～105°之间；所述第i级光电结构的第二子光电结构与所述第i+1级光电结构的第一子光电结构之间的夹角范围位于85°～105°之间；所述第i级光电结构的第一子光电结构与所述第i级光电结构的第二子光电结构之间的夹角范围位于85°～105°之间。
  19. 一种显示基板的制备方法，其中，所述显示基板具有岛区、孔区和桥区，所述显示基板的制备方法包括：
    在衬底基板上形成电路层；在所述电路层上形成位于所述岛区的驱动电路、 以及位于所述孔区的过孔；
    在所述电路层上还形成与所述驱动电路电连接的至少一个光电传感器；所述光电传感器包括叠层设置的第一电极层、光电结构层和第二电极层；
    所述光电传感器位于所述岛区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述岛区指向所述桥区的方向上依次设置；和/或，所述光电传感器位于所述桥区，且所述光电传感器的所述第一电极层、所述光电结构层和所述第二电极层沿所述桥区指向所述岛区的方向上依次设置。
  20. 一种显示装置，其中，包括如权利要求1～18中任一项所述的显示基板。
PCT/CN2023/097074 2022-06-21 2023-05-30 显示基板及其制备方法、显示装置 WO2023246437A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210704395.8 2022-06-21
CN202210704395.8A CN115241239A (zh) 2022-06-21 2022-06-21 显示基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2023246437A1 true WO2023246437A1 (zh) 2023-12-28

Family

ID=83669492

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/097074 WO2023246437A1 (zh) 2022-06-21 2023-05-30 显示基板及其制备方法、显示装置

Country Status (2)

Country Link
CN (1) CN115241239A (zh)
WO (1) WO2023246437A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115241239A (zh) * 2022-06-21 2022-10-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
WO2024103316A1 (zh) * 2022-11-16 2024-05-23 京东方科技集团股份有限公司 显示面板及终端设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049602A1 (en) * 2014-08-12 2016-02-18 Samsung Display Co., Ltd. Stretchable substrate and organic light emitting display apparatus comprising the same
CN110854166A (zh) * 2019-10-28 2020-02-28 武汉华星光电半导体显示技术有限公司 可拉伸有机发光二极管显示面板
CN112230799A (zh) * 2020-10-15 2021-01-15 京东方科技集团股份有限公司 可拉伸显示面板及显示设备
CN112563308A (zh) * 2020-11-06 2021-03-26 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115241239A (zh) * 2022-06-21 2022-10-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049602A1 (en) * 2014-08-12 2016-02-18 Samsung Display Co., Ltd. Stretchable substrate and organic light emitting display apparatus comprising the same
CN110854166A (zh) * 2019-10-28 2020-02-28 武汉华星光电半导体显示技术有限公司 可拉伸有机发光二极管显示面板
CN112230799A (zh) * 2020-10-15 2021-01-15 京东方科技集团股份有限公司 可拉伸显示面板及显示设备
CN112563308A (zh) * 2020-11-06 2021-03-26 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115241239A (zh) * 2022-06-21 2022-10-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN115241239A (zh) 2022-10-25

Similar Documents

Publication Publication Date Title
WO2023246437A1 (zh) 显示基板及其制备方法、显示装置
US11217642B2 (en) Display panel, manufacturing method thereof, and display device
US11171304B2 (en) Flexible substrate, preparation method thereof, and display device
JP7203763B2 (ja) 表示基板及びその製造方法、表示装置
TWI581420B (zh) 有機發光顯示設備及其製造方法
US11903234B2 (en) Display substrate, preparation method thereof and display device
US9825106B2 (en) OLED display substrate and method for manufacturing the same, and display apparatus
CN112186023B (zh) 一种显示基板及其制备方法、显示装置
WO2021164617A1 (zh) 显示面板和显示装置
WO2022057515A1 (zh) 显示基板及其制备方法、显示装置
US20200027940A1 (en) Display panel, method for manufacturing the same and display device
US20220336525A1 (en) Flexible micro-led display panel and manufacturing method thereof
US10529790B2 (en) Organic light-emitting diode display and method of manufacturing the same with no cladding process
JP2023503668A (ja) ディスプレイパネル、フレキシブルディスプレイ、電子デバイスおよびディスプレイパネルの製造方法
WO2021213510A1 (zh) 显示面板、显示装置以及显示面板的制造方法
WO2021164645A1 (zh) 显示基板及显示装置
JP7343614B2 (ja) 表示基板及びその製造方法、表示装置
WO2021077334A1 (zh) 显示基板及其制备方法、显示装置
WO2021238975A1 (zh) 发光器件、显示面板以及显示装置
WO2021077332A1 (zh) 显示基板及其制备方法、显示装置
WO2020062410A1 (zh) 有机发光二极管显示器及其制作方法
WO2020239071A1 (zh) 显示基板及其制作方法、显示面板和显示装置
WO2021226879A1 (zh) 显示基板及其制备方法、显示装置
CN113346031B (zh) 显示装置
WO2022227154A1 (zh) 显示面板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23826086

Country of ref document: EP

Kind code of ref document: A1