WO2023246269A1 - Digital-analog hybrid low dropout regulator capable of realizing output voltage regulation - Google Patents

Digital-analog hybrid low dropout regulator capable of realizing output voltage regulation Download PDF

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WO2023246269A1
WO2023246269A1 PCT/CN2023/089622 CN2023089622W WO2023246269A1 WO 2023246269 A1 WO2023246269 A1 WO 2023246269A1 CN 2023089622 W CN2023089622 W CN 2023089622W WO 2023246269 A1 WO2023246269 A1 WO 2023246269A1
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voltage
digital
resistor
code
conversion module
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PCT/CN2023/089622
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French (fr)
Chinese (zh)
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齐伟
王乃龙
高玮
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北京芯格诺微电子有限公司
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Publication of WO2023246269A1 publication Critical patent/WO2023246269A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the invention relates to the technical field of integrated circuits, and in particular to a digital-analog hybrid low-voltage linear voltage regulator that can realize output voltage adjustment.
  • low dropout linear regulator LDO, Low Dropout Regulator
  • LDO Low Dropout Regulator
  • the existing sink-type LDO circuits have a structure that generates a fixed output voltage. In DC motor driving applications, they cannot meet the demand for high-end gate drive voltage.
  • FIG. 1 is a schematic diagram of the circuit structure of a sink type low dropout linear regulator in the prior art.
  • the existing sink-type LDO is a typical application of operational amplifiers and closed-loop negative feedback systems, which can stabilize the output voltage under different output currents.
  • LDO mainly includes startup circuit, voltage reference circuit, error amplifier, power device and feedback resistor.
  • the core modules are the error amplifier and power device, which form a closed-loop feedback system through the resistor feedback network.
  • V op which reduces the current through the P-type power transistor, thereby reducing the output voltage of the LDO. vice versa.
  • the structure is simple and easy to implement. Since the load is connected to the power supply voltage, the P-type power tube generates sink current. However, this LDO can only generate a fixed output voltage and cannot provide a voltage that changes with the power supply voltage, which has certain application limitations.
  • the technical purpose to be achieved by the present invention is to provide a digital-analog hybrid low voltage dropout linear regulator that can realize output voltage adjustment.
  • This new LDO structure can be used for high-end gate driving.
  • voltage sampling is performed through an ADC module.
  • the digital logic unit a digital code of the reference voltage difference that can follow the change of the power supply voltage is generated, and then the output voltage that follows the change of the power supply voltage is realized through the DAC module and the reference circuit to realize the driving of the high-end gate.
  • the sampling circuit and the output voltage calibration circuit together form a negative feedback loop to achieve accurate and stable output voltage of the LDO.
  • the present invention provides a digital-analog hybrid low-voltage linear regulator that can realize output voltage adjustment.
  • the low-voltage linear regulator includes an output voltage calibration circuit, a power transistor, a voltage sampling circuit, a first external Power interface and second external power interface;
  • the output voltage calibration circuit includes an error amplifier, a DAC digital-to-analog conversion module, a digital logic unit, a filter network, a startup circuit and a reference circuit; the voltage sampling circuit includes a first resistor negative feedback network, a second resistor negative feedback network and an ADC Analog-to-digital conversion module;
  • the output terminal of the error amplifier is connected to the gate of the power transistor, the source of the power transistor is grounded, and the drain of the power transistor is the voltage output terminal of the low voltage dropout linear regulator;
  • the first resistor negative feedback network is connected to the second external power interface.
  • the first resistor negative feedback network divides the high voltage domain external voltage V M and generates a first divided voltage V 1 .
  • the voltage V 1 is input to the ADC analog-to-digital conversion module;
  • the digital logic unit 12 stores a third digital code Code_V CC that represents the low-voltage domain external voltage V CC ; at the same time, the digital logic unit 12 stores the first digital code Code_V M and the second digital code Code_V CC .
  • the digital logic operation performed by the code Code_V OUT and the third digital code Code_V CC has obtained the fourth digital code Code_V FB that represents the feedback voltage V FB ; the digital logic operation is:
  • the output voltage V OUT is adjusted between VM and (V M -V CC ) by adjusting the third digital code Code_V CC inside the digital logic unit.
  • the full-scale value of the DAC digital-to-analog conversion module is set to 2V REF , and when the DAC digital-to-analog conversion module 1 outputs half of the full-scale value for the fourth digital code Code_V FB that is zero; that is, When the fourth digital code Code_V FB is zero, the feedback voltage V FB output by the DAC digital-to-analog conversion module 11 is equal to the reference voltage VREF .
  • the first resistor negative feedback network includes a first resistor R 1 and a second resistor R 2 .
  • the first end of the first resistor R 1 is connected to the second external power interface.
  • the first resistor R 1 The second end of the resistor R 1 and the first end of the second resistor R 2 are connected to the node X, and the second end of the second resistor R 2 is connected to ground; the second end of the first resistor R 1 is connected to the ADC module
  • the conversion module is to input the first divided voltage V 1 of the X node to the ADC analog-to-digital conversion module.
  • the load of the low dropout linear regulator is connected between the second external power interface and the drain of the power transistor.
  • sampling circuit and the output voltage calibration circuit together form a negative feedback loop to achieve accurate and stable LDO output voltage
  • Coupled refers to any direct or indirect communication or connection between two or more elements regardless of whether those elements are in physical contact with each other.
  • transmission refers to direct and indirect communications.
  • communication covers direct and indirect communications.
  • include and “include” and their derivatives mean including, but not limited to.
  • the term “or” is inclusive and means and/or.
  • the low voltage dropout linear regulator of the present invention that can realize voltage domain output includes an output voltage calibration circuit 1, a power transistor 2, a voltage sampling circuit 3, a first external power interface 4 and a second external power interface 5 .
  • the output voltage calibration circuit 1 includes an error amplifier 10, a DAC digital-to-analog conversion module 11, a digital Logic unit 12 and filter network 13. At the same time, the output voltage calibration circuit 1 also includes a starting circuit 14 and a reference circuit 15.
  • the voltage sampling circuit 3 includes a first resistor negative feedback network 30 , a second resistor negative feedback network 31 and an ADC analog-to-digital conversion module 32 .
  • the first external power interface 4 is connected to a low-voltage domain external power supply V CC .
  • the low-voltage external power supply V CC generates a reference voltage V REF through the startup circuit 14 and the reference circuit 15.
  • the reference voltage V REF is input to The non-inverting input terminal of error amplifier 10.
  • the output terminal of the error amplifier 10 is connected to the gate of the power transistor 2 , and the source of the power transistor 2 is grounded.
  • the second external power interface 5 is connected to a high-voltage domain external power supply VM .
  • the load of the low-voltage linear regulator in this embodiment is connected between the second external power interface 5 and the drain of the power transistor 2 .
  • the drain of the power transistor 2 serves as the voltage output terminal of the low voltage dropout linear regulator of this embodiment.
  • the first resistor negative feedback network 30 is connected to the second external power interface 5.
  • the first resistor negative feedback network 30 divides the high voltage domain external power supply V M and generates the first divided voltage V 1 .
  • the first divided voltage V 1 is input to the ADC analog-to-digital conversion module 32 .
  • the first resistor negative feedback network 30 includes a first resistor R 1 and a second resistor R 2 .
  • the first end of the first resistor R 1 is connected to the second external power interface 5 .
  • the second terminal of a resistor R 1 and the first terminal of the second resistor R 2 are connected to the node X, and the second terminal of the second resistor R 2 is connected to the ground.
  • the second end of the first resistor R 1 is connected to the ADC analog-to-digital conversion module 32 , that is, the first divided voltage V 1 of the X node is input to the ADC analog-to-digital conversion module 32 .
  • the second resistor negative feedback network 31 is connected to the voltage output end of the low voltage dropout linear regulator, and the second resistor negative feedback network 31 divides the output voltage V OUT and generates a second divided voltage V 2 , so The second divided voltage V 2 is input to the ADC analog-to-digital conversion module 32 .
  • the second resistor negative feedback network 31 includes a third resistor R 3 and a fourth resistor R 4 .
  • the first end of the third resistor R 3 is connected to the voltage output end of the low-voltage linear regulator.
  • the second end of the third resistor R 3 and the first end of the fourth resistor R 4 are connected to the node Y
  • the second end of the fourth resistor R 4 is connected to the ground.
  • the second end of the third resistor R 3 is connected to the ADC analog-to-digital conversion module 32 , that is, the second divided voltage V 2 of the Y node is input to the ADC analog-to-digital conversion module 32 .
  • the first divided voltage V 1 can be expressed as:
  • the second divided voltage V 2 can be expressed as:
  • the ADC analog-to-digital conversion module 32 converts the first divided voltage V 1 into a first digital code Code_VM
  • the ADC analog-to-digital conversion module 32 converts the second divided voltage V 2 into a second digital Code_V OUT
  • the purpose of using the first resistor negative feedback network 30 and the second resistor negative feedback network 31 to divide the high voltage domain external power supply VM and the output voltage V OUT is that the external power supply VM of the high voltage domain is
  • the power supply V M and the output voltage V OUT are both power supplies in the high voltage domain, and the withstand voltage of the MOS devices in the ADC analog-to-digital conversion module 32 is limited.
  • the ADC analog-to-digital conversion module 32 in the voltage sampling circuit 3 is connected to the digital logic unit 12 in the output voltage calibration circuit 1.
  • the digital logic unit 12 receives the first digital code Code_V M and the second digital code. After Code_V OUT , it performs digital logic operations in combination with the third digital code Code_V CC that has been stored inside and represents the low-voltage domain external power supply V CC . Thus, a fourth digital code Code_V FB characterizing the feedback voltage V FB is obtained.
  • the digital logic unit 12 is connected to the DAC digital-to-analog conversion module 11 , and the digital logic unit 12 inputs the fourth digital code Code_V FB obtained by the operation to the DAC digital-to-analog conversion module 11 .
  • the DAC digital-to-analog conversion module 11 converts the fourth digital code Code_V FB input into an analog feedback voltage V FB .
  • the feedback voltage V FB is input to the inverting input terminal of the error amplifier 10 after passing through the filter network 13 .
  • the digital logic operation performed by the digital logic unit 12 on the first digital code Code_VM , the second digital code Code_V OUT and the third digital code Code_V CC is:
  • the fourth digital code Code_V FB the first digital code Code_V M - the second digital code Code_V OUT - the third digital code Code_V CC .
  • the fourth digital code Code_V FB is the sum of the expression (the first digital code Code_V M - the third digital code Code_V CC ) and the second digital code Code_V OUT . difference between. Furthermore, the feedback voltage V FB expresses the difference between (high voltage domain external power supply VM - low voltage domain external power supply V CC ) and the output voltage V OUT .
  • the feedback voltage V FB output by the DAC digital-to-analog conversion module 11 is set to be equal to the reference voltage V REF .
  • the full-scale value of the DAC digital-to-analog conversion module 11 is set to 2V REF , and when the DAC digital-to-analog conversion module 11 outputs half of the full-scale value for the fourth digital code Code_V FB that is zero. Then when the fourth digital code Code_V FB is zero, the feedback voltage V FB output by the DAC digital-to-analog conversion module 11 is equal to the reference voltage VREF .
  • V OUT VM - V CC
  • the low-dropout linear regulator of this embodiment outputs an output voltage V OUT that can follow the change of the high-voltage domain external power supply VM , and by adjusting the internal digital logic
  • the output voltage V OUT can be adjusted between VM and ( VM - V CC ).

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Abstract

A digital-analog hybrid low dropout regulator capable of realizing output voltage regulation. The low dropout regulator comprises an output voltage calibration circuit (1), a power transistor (2), a voltage sampling circuit (3), a first external power source interface (4), and a second external power source interface (5), wherein the output voltage calibration circuit (1) comprises an error amplifier (10), a digital-to-analog conversion (DAC) module (11), a digital logic unit (12), a filtering network (13), a start circuit (14), and a reference circuit (15); the voltage sampling circuit (3) comprises a first resistor negative feedback network (30), a second resistor negative feedback network (31), and an analog-to-digital conversion (ADC) module (32); the first external power source interface (4) is connected to an external voltage VCC in a low-voltage domain; the second external power source interface (5) is connected to an external voltage VM in a high-voltage domain; and a reference voltage VREF is generated from the external voltage VCC in the low-voltage domain by means of the start circuit (14) and the reference circuit (15), and the reference voltage VREF is input into a non-inverting input end of the error amplifier (10).

Description

可实现输出电压调节的数模混合低压差线性稳压器Digital-to-Analog Hybrid Low Dropout Linear Regulator for Output Voltage Regulation 技术领域Technical field
本发明涉及集成电路技术领域，尤其涉及一种可实现输出电压调节的数模混合低压差线性稳压器。The invention relates to the technical field of integrated circuits, and in particular to a digital-analog hybrid low-voltage linear voltage regulator that can realize output voltage adjustment.
背景技术Background technique
现有技术中，高集成度、高可靠性及低功耗等成为了电源管理芯片、功率控制芯片和固态照明芯片的发展方向。其中，低压差线性稳压器(LDO，Low Dropout Regulator)由于其片外器件少，结构简单便于集成，静态功耗小且噪声低，使得其十分符合高性能模拟电路对电源的需求。然而现有的Sink型LDO电路多为产生固定输出电压的结构，在直流电机驱动的应用中，无法满足高端栅极驱动电压的需求。In the existing technology, high integration, high reliability and low power consumption have become the development direction of power management chips, power control chips and solid-state lighting chips. Among them, low dropout linear regulator (LDO, Low Dropout Regulator) has few external components, simple structure and easy integration, small static power consumption and low noise, making it very suitable for the power supply needs of high-performance analog circuits. However, most of the existing sink-type LDO circuits have a structure that generates a fixed output voltage. In DC motor driving applications, they cannot meet the demand for high-end gate drive voltage.
如图1所示的现有技术中的Sink型低压差线性稳压器电路结构示意图。现有的Sink型LDO是运算放大器和闭环负反馈***的一个典型应用，可以在不同的输出电流下实现稳定输出电压的作用。LDO主要包括启动电路、电压基准电路、误差放大器、功率器件及反馈电阻。其中，核心模块为误差放大器和功率器件，它们通过电阻反馈网络构成了一个闭环反馈***。当LDO的输出电压Vout上升时，反馈网络产生的反馈电压同时上升，即误差放大器的正向输入端的输入电压上升，通过和反向输入端的基准电压VREF进行比较，调整误差放大器的输出电压Vop，使得通过P型功率管的电流减少，进而降低LDO的输出电压。反之亦然。该结构简单易行，由于负载连接电源电压，因此P型功率管产生Sink电流。然而该LDO只能产生固定的输出电压，无法提供跟随电源电压变化的电压，存在一定的应用限制。Figure 1 is a schematic diagram of the circuit structure of a sink type low dropout linear regulator in the prior art. The existing sink-type LDO is a typical application of operational amplifiers and closed-loop negative feedback systems, which can stabilize the output voltage under different output currents. LDO mainly includes startup circuit, voltage reference circuit, error amplifier, power device and feedback resistor. Among them, the core modules are the error amplifier and power device, which form a closed-loop feedback system through the resistor feedback network. When the output voltage V out of the LDO rises, the feedback voltage generated by the feedback network rises at the same time, that is, the input voltage of the forward input terminal of the error amplifier rises. By comparing it with the reference voltage V REF at the reverse input terminal, the output voltage of the error amplifier is adjusted. V op , which reduces the current through the P-type power transistor, thereby reducing the output voltage of the LDO. vice versa. The structure is simple and easy to implement. Since the load is connected to the power supply voltage, the P-type power tube generates sink current. However, this LDO can only generate a fixed output voltage and cannot provide a voltage that changes with the power supply voltage, which has certain application limitations.
由此可见现有技术中提供需要一种，可以用于高端栅极驱动的新型LDO结构，同时能够跟随电源电压变化实现可调电压范围的电压域输出。 It can be seen that there is a need in the existing technology for a new LDO structure that can be used for high-end gate driving, and at the same time can follow changes in the power supply voltage to achieve voltage domain output in an adjustable voltage range.
发明内容Contents of the invention
本发明所要实现的技术目的在于提供一种可实现输出电压调节的数模混合低压差线性稳压器，该可以用于高端栅极驱动的新型LDO结构，本发明中通过ADC模块进行电压采样，在数字逻辑单元中产生了可跟随电源电压变化的基准电压差的数字编码，进而通过DAC模块和基准电路实现了跟随电源电压变化的输出电压，实现高端栅极的驱动。并且采样电路和输出电压校准电路共同构成负反馈回路，实现了LDO的输出电压精确且稳定。The technical purpose to be achieved by the present invention is to provide a digital-analog hybrid low voltage dropout linear regulator that can realize output voltage adjustment. This new LDO structure can be used for high-end gate driving. In the present invention, voltage sampling is performed through an ADC module. In the digital logic unit, a digital code of the reference voltage difference that can follow the change of the power supply voltage is generated, and then the output voltage that follows the change of the power supply voltage is realized through the DAC module and the reference circuit to realize the driving of the high-end gate. And the sampling circuit and the output voltage calibration circuit together form a negative feedback loop to achieve accurate and stable output voltage of the LDO.
基于上述技术目的，本发明提供一种可实现输出电压调节的数模混合低压差线性稳压器，所述低压差线性稳压器包括输出电压校准电路、功率晶体管、电压采样电路、第一外部电源接口和第二外部电源接口；Based on the above technical objectives, the present invention provides a digital-analog hybrid low-voltage linear regulator that can realize output voltage adjustment. The low-voltage linear regulator includes an output voltage calibration circuit, a power transistor, a voltage sampling circuit, a first external Power interface and second external power interface;
所述输出电压校准电路包括误差放大器、DAC数模转换模块、数字逻辑单元、滤波网络、启动电路和基准电路；所述电压采样电路包括第一电阻负反馈网络、第二电阻负反馈网络和ADC模数转换模块；The output voltage calibration circuit includes an error amplifier, a DAC digital-to-analog conversion module, a digital logic unit, a filter network, a startup circuit and a reference circuit; the voltage sampling circuit includes a first resistor negative feedback network, a second resistor negative feedback network and an ADC Analog-to-digital conversion module;
所述第一外部电源接口连接低电压域外部电压VCC，所述第二外部电源接口连接高电压域外部电压VM，所述低电压外部电压VCC经过启动电路和基准电路生成参考电压VREF，所述参考电压VREF输入到误差放大器的同相输入端；The first external power interface is connected to the low-voltage domain external voltage V CC , the second external power interface is connected to the high-voltage domain external voltage VM , and the low-voltage external voltage V CC generates the reference voltage V through the startup circuit and the reference circuit. REF , the reference voltage V REF is input to the non-inverting input terminal of the error amplifier;
所述误差放大器的输出端连接于功率晶体管的栅极，所述功率晶体管的源极接地，所述功率晶体管的漏极为所述低压差线性稳压器的电压输出端；The output terminal of the error amplifier is connected to the gate of the power transistor, the source of the power transistor is grounded, and the drain of the power transistor is the voltage output terminal of the low voltage dropout linear regulator;
所述第一电阻负反馈网络连接于第二外部电源接口，所述第一电阻负反馈网络对高电压域外部电压VM进行分压并生成第一分压电压V1，所述第一分压电压V1被输入至ADC模数转换模块；The first resistor negative feedback network is connected to the second external power interface. The first resistor negative feedback network divides the high voltage domain external voltage V M and generates a first divided voltage V 1 . The voltage V 1 is input to the ADC analog-to-digital conversion module;
所述第二电阻负反馈网络连接于低压差线性稳压器的电压输出端，所述第二电阻负反馈网络对所述电压输出端的输出电压VOUT进行分压并生成第二分压电压V2，所述第二分压电压V2输入至ADC模数转换模块；The second resistor negative feedback network is connected to the voltage output end of the low voltage dropout linear regulator, and the second resistor negative feedback network divides the output voltage V OUT of the voltage output end and generates a second divided voltage V 2. The second divided voltage V 2 is input to the ADC analog-to-digital conversion module;
所述ADC模数转换模块将第一分压电压V1转换为第一数字编码Code_VM，将第二分压电压V2转换为第二数字编码Code_VOUT；并将第一数字编码Code_VM和第二数字编码Code_VOUT输入至数字逻辑单元；The ADC analog-to-digital conversion module converts the first divided voltage V 1 into a first digital code Code_VM , and converts the second divided voltage V 2 into a second digital code Code_V OUT ; and converts the first digital code Code_VM and The second digital code Code_V OUT is input to the digital logic unit;
所述数字逻辑单元12存储有表征低电压域外部电压VCC的第三数字编码Code_VCC；同时所述所述数字逻辑单元12对第一数字编码Code_VM、第二数字 编码Code_VOUT和第三数字编码Code_VCC进行的数字逻辑运算已获得表征反馈电压VFB的第四数字编码Code_VFB；所述数字逻辑运算为：The digital logic unit 12 stores a third digital code Code_V CC that represents the low-voltage domain external voltage V CC ; at the same time, the digital logic unit 12 stores the first digital code Code_V M and the second digital code Code_V CC . The digital logic operation performed by the code Code_V OUT and the third digital code Code_V CC has obtained the fourth digital code Code_V FB that represents the feedback voltage V FB ; the digital logic operation is:
第四数字编码Code_VFB＝第一数字编码Code_VM－第二数字编码Code_VOUT－第三数字编码Code_VCC；The fourth digital code Code_V FB = the first digital code Code_V M - the second digital code Code_V OUT - the third digital code Code_V CC ;
所述第四数字编码Code_VFB输入至DAC数模转换模块；所述DAC数模转换模块将所述第四数字编码Code_VFB转换为反馈电压VFB；且所述DAC数模转换模块对数值为零的第四数字编码Code_VFB输出的反馈电压VFB等于参考电压VREF；所述反馈电压VFB经过滤波网络后被输入至误差放大器的反相输入端；The fourth digital code Code_V FB is input to the DAC digital-to-analog conversion module; the DAC digital-to-analog conversion module converts the fourth digital code Code_V FB into the feedback voltage V FB ; and the log value of the DAC digital-to-analog conversion module is The feedback voltage V FB output by the fourth digital code Code_V FB of zero is equal to the reference voltage V REF ; the feedback voltage V FB is input to the inverting input terminal of the error amplifier after passing through the filter network;
通过调节数字逻辑单元内部的第三数字编码Code_VCC使输出电压VOUT在VM至(VM-VCC)之间调节。The output voltage V OUT is adjusted between VM and (V M -V CC ) by adjusting the third digital code Code_V CC inside the digital logic unit.
在一个实施例中，所述DAC数模转换模块的满幅值设定为2VREF，且当DAC数模转换模块1针对为零的第四数字编码Code_VFB输出为满幅值的一半；即当第四数字编码Code_VFB为零时，所述DAC数模转换模块11输出的反馈电压VFB等于参考电压VREF。In one embodiment, the full-scale value of the DAC digital-to-analog conversion module is set to 2V REF , and when the DAC digital-to-analog conversion module 1 outputs half of the full-scale value for the fourth digital code Code_V FB that is zero; that is, When the fourth digital code Code_V FB is zero, the feedback voltage V FB output by the DAC digital-to-analog conversion module 11 is equal to the reference voltage VREF .
在一个实施例中，所述第一电阻负反馈网络包括第一电阻R1和第二电阻R2，所述第一电阻R1的第一端连接于第二外部电源接口，所述第一电阻R1的第二端与第二电阻R2的第一端连接于节点X，且第二电阻R2的第二端接地；所述第一电阻R1的第二端连接至ADC模数转换模块，即将X节点的第一分压电压V1输入至ADC模数转换模块。In one embodiment, the first resistor negative feedback network includes a first resistor R 1 and a second resistor R 2 . The first end of the first resistor R 1 is connected to the second external power interface. The first resistor R 1 The second end of the resistor R 1 and the first end of the second resistor R 2 are connected to the node X, and the second end of the second resistor R 2 is connected to ground; the second end of the first resistor R 1 is connected to the ADC module The conversion module is to input the first divided voltage V 1 of the X node to the ADC analog-to-digital conversion module.
在一个实施例中，所述第二电阻负反馈网络包括第三电阻R3和第四电阻R4，所述第三电阻R3的第一端连接于低压差线性稳压器的电压输出端，所述第三电阻R3的第二端与第四电阻R4的第一端连接于节点Y，且第四电阻R4的第二端接地。所述第三电阻R3的第二端连接至ADC模数转换模块，即将Y节点的第二分压电压V2输入至ADC模数转换模块。In one embodiment, the second resistor negative feedback network includes a third resistor R 3 and a fourth resistor R 4 . The first end of the third resistor R 3 is connected to the voltage output end of the low-voltage linear regulator. , the second end of the third resistor R 3 and the first end of the fourth resistor R 4 are connected to the node Y, and the second end of the fourth resistor R 4 is connected to the ground. The second end of the third resistor R 3 is connected to the ADC analog-to-digital conversion module, that is, the second divided voltage V 2 of the Y node is input to the ADC analog-to-digital conversion module.
在一个实施例中，所述第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的阻值满足于：
In one embodiment, the resistance values of the first resistor R 1 , the second resistor R 2 , the third resistor R 3 and the fourth resistor R 4 satisfy:
在一个实施例中，所述ADC模数转换模块和所述DAC数模转换模块被复用。 In one embodiment, the ADC analog-to-digital conversion module and the DAC digital-to-analog conversion module are multiplexed.
在一个实施例中，所述低压差线性稳压器的负载连接于第二外部电源接口与功率晶体管漏极之间。In one embodiment, the load of the low dropout linear regulator is connected between the second external power interface and the drain of the power transistor.
与现有技术相比，本发明的一个或多个实施例可以具有如下发明点及优势：Compared with the prior art, one or more embodiments of the present invention may have the following inventive points and advantages:
1.本发明中采用了数模混合的电路结构，通过ADC实现电压采样，在数字逻辑单元中产生了可跟随电源电压变化的基准电压差的数字编码。1. The present invention adopts a digital-analog mixed circuit structure, realizes voltage sampling through ADC, and generates a digital code of the reference voltage difference that can follow the change of the power supply voltage in the digital logic unit.
2.通过DAC和基准电路实现了可跟随电源电压变化的输出电压，用于高端栅极的驱动。2. Through the DAC and reference circuit, an output voltage that can follow the change of the power supply voltage is realized, which is used to drive the high-end gate.
3.采样电路和输出电压校准电路共同构成负反馈回路，实现了LDO输出电压的精确且稳定；3. The sampling circuit and the output voltage calibration circuit together form a negative feedback loop to achieve accurate and stable LDO output voltage;
4.通过调节数字逻辑内部基准数字编码的大小，可以产生跟随电源电压变化的电压域。4. By adjusting the size of the internal reference digital code of the digital logic, a voltage domain that follows the change of the power supply voltage can be generated.
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description, claims and appended drawings.
附图说明Description of the drawings
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation of the present invention. In the attached picture:
图1是现有技术中的Sink型低压差线性稳压器电路结构示意图；Figure 1 is a schematic diagram of the circuit structure of a sink-type low-voltage linear regulator in the prior art;
图2是本发明的低压差线性稳压器电路结构示意图；Figure 2 is a schematic diagram of the circuit structure of the low voltage dropout linear regulator of the present invention;
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.
在进行下面的详细描述之前，阐述贯穿本发明使用的某些单词和短语的定义可能是必要的。术语“耦接”“连接”及其派生词指两个或多个元件之间的任何直接或间接通信或者连接，而无论那些元件是否彼此物理接触。术语“传输”、“接收”和“通信”及其派生词涵盖直接和间接通信。术语“包括”和“包含”及其派生词是指包括但不限于。术语“或”是包含性的，意思是和/或。短语“与……相关联”及其派 生词是指包括、包括在……内、互连、包含、包含在……内、连接或与……连接、耦接或与……耦接、与……通信、配合、交织、并列、接近、绑定或与……绑定、具有、具有属性、具有关系或与……有关系等。术语“控制器”是指控制至少一个操作的任何设备、***或其一部分。这种控制器可以用硬件、或者硬件和软件和/或固件的组合来实施。与任何特定控制器相关联的功能可以是集中式的或分布式的，无论是本地的还是远程的。短语“至少一个”，当与项目列表一起使用时，意指可以使用所列项目中的一个或多个的不同组合，并且可能只需要列表中的一个项目。例如，“A、B、C中的至少一个”包括以下组合中的任意一个：A、B、C、A和B、A和C、B和C、A和B和C。Before proceeding to the detailed description below, it may be necessary to set forth definitions of certain words and phrases used throughout this disclosure. The terms "coupled,""connected," and their derivatives refer to any direct or indirect communication or connection between two or more elements regardless of whether those elements are in physical contact with each other. The terms "transmission", "reception" and "communication" and their derivatives cover direct and indirect communications. The terms "include" and "include" and their derivatives mean including, but not limited to. The term "or" is inclusive and means and/or. The phrase "associated with" and its origin New words include, include within, interconnect, contain, contain within, connect or be connected with, couple or be coupled with, communicate with, cooperate, interweave, juxtapose, and be close to , bound or bound to, having, having attributes, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one," when used in connection with a list of items, means that different combinations of one or more of the listed items may be used, and that only one of the items in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.
本发明中对于电阻、电容或电感的第一端和第二端的描述仅为了区分该器件的两个连接端，以便于描述该器件与其他器件的连接关系，其并不特定地指定电阻、电容或电感在实际情况下的某一端。本领域技术人员应当知晓在实际电路构建时，电阻、电容或电感在实际器件中的任何一端均可定义为第一端，同时当第一端被定义时，器件的另一端自动被定为第二端。The description of the first end and the second end of the resistor, capacitor or inductor in the present invention is only to distinguish the two connection ends of the device so as to facilitate the description of the connection relationship between the device and other devices. It does not specifically specify the resistor or capacitor. Or one end of the inductor in practical situations. Those skilled in the art should know that when constructing the actual circuit, any end of the resistor, capacitor or inductor in the actual device can be defined as the first end. At the same time, when the first end is defined, the other end of the device is automatically determined as the third end. Two ends.
本发明中对各种部件或元素进行描述时，所使用的“第一”、“第二”、“第三”……的描述方式仅为了区分各个部件，仅为了表达各个部件之间互不相同的关系。上述所使用的描述方式本身不包含任何对部件之间关联的隐含意义。例如，当仅出现“第一”和“第三”的描述时，不意味着二者之间还存在“第二”，这里对“第一”和“第三”的描述仅意味着存在两个不同的独立部件。When describing various components or elements in the present invention, the description methods of "first", "second", "third"... used are only to distinguish the various components and to express the mutual differences between the various components. Same relationship. The description method used above does not contain any implicit meaning of the relationship between components. For example, when only the description of "first" and "third" appears, it does not mean that there is a "second" between them. The description of "first" and "third" here only means that there are two different independent components.
贯穿本发明中提供的其他特定单词和短语的定义。本领域普通技术人员应该理解，在许多情况下，即使不是大多数情况下，这种定义也适用于这样定义的单词和短语的先前和将来使用。Definitions of other specific words and phrases are provided throughout this disclosure. It will be understood by those of ordinary skill in the art that in many, if not most, cases this definition will apply to prior and future uses of the words and phrases so defined.
在本发明中，模块的应用组合以及子模块的划分层级仅用于说明，在不脱离本公开的范围内，模块的应用组合以及子模块的划分层级可以具有不同的方式。In the present invention, the application combination of modules and the hierarchical division of sub-modules are only for illustration. The application combination of modules and the hierarchical division of sub-modules may be implemented in different ways without departing from the scope of the present disclosure.
实施例Example
如图2所示，本发明的可实现电压域输出的低压差线性稳压器包括输出电压校准电路1、功率晶体管2、电压采样电路3、第一外部电源接口4和第二外部电源接口5。As shown in Figure 2, the low voltage dropout linear regulator of the present invention that can realize voltage domain output includes an output voltage calibration circuit 1, a power transistor 2, a voltage sampling circuit 3, a first external power interface 4 and a second external power interface 5 .
所述输出电压校准电路1包括误差放大器10、DAC数模转换模块11、数字 逻辑单元12和滤波网络13。同时所述输出电压校准电路1中还包括有启动电路14和基准电路15。The output voltage calibration circuit 1 includes an error amplifier 10, a DAC digital-to-analog conversion module 11, a digital Logic unit 12 and filter network 13. At the same time, the output voltage calibration circuit 1 also includes a starting circuit 14 and a reference circuit 15.
所述电压采样电路3包括第一电阻负反馈网络30、第二电阻负反馈网络31和ADC模数转换模块32。The voltage sampling circuit 3 includes a first resistor negative feedback network 30 , a second resistor negative feedback network 31 and an ADC analog-to-digital conversion module 32 .
本实施例中，所述第一外部电源接口4连接低电压域外部电源VCC，低电压外部电源VCC经过启动电路14和基准电路15生成参考电压VREF，所述参考电压VREF输入到误差放大器10的同相输入端。In this embodiment, the first external power interface 4 is connected to a low-voltage domain external power supply V CC . The low-voltage external power supply V CC generates a reference voltage V REF through the startup circuit 14 and the reference circuit 15. The reference voltage V REF is input to The non-inverting input terminal of error amplifier 10.
本实施例中，所述误差放大器10的输出端连接于功率晶体管2的栅极，所述功率晶体管2的源极接地。In this embodiment, the output terminal of the error amplifier 10 is connected to the gate of the power transistor 2 , and the source of the power transistor 2 is grounded.
所述第二外部电源接口5连接高电压域外部电源VM，本实施例的低压差线性稳压器的负载被连接于第二外部电源接口5与功率晶体管2漏极之间。同时功率晶体管2的漏极作为本实施例的低压差线性稳压器的电压输出端。The second external power interface 5 is connected to a high-voltage domain external power supply VM . The load of the low-voltage linear regulator in this embodiment is connected between the second external power interface 5 and the drain of the power transistor 2 . At the same time, the drain of the power transistor 2 serves as the voltage output terminal of the low voltage dropout linear regulator of this embodiment.
所述第一电阻负反馈网络30连接于第二外部电源接口5，所述第一电阻负反馈网络30对高电压域外部电源VM进行分压并生成第一分压电压V1，所述第一分压电压V1被输入至ADC模数转换模块32。The first resistor negative feedback network 30 is connected to the second external power interface 5. The first resistor negative feedback network 30 divides the high voltage domain external power supply V M and generates the first divided voltage V 1 . The first divided voltage V 1 is input to the ADC analog-to-digital conversion module 32 .
本实施例中，所述第一电阻负反馈网络30包括第一电阻R1和第二电阻R2，所述第一电阻R1的第一端连接于第二外部电源接口5，所述第一电阻R1的第二端与第二电阻R2的第一端连接于节点X，且第二电阻R2的第二端接地。所述第一电阻R1的第二端连接至ADC模数转换模块32，即将X节点的第一分压电压V1输入至ADC模数转换模块32。In this embodiment, the first resistor negative feedback network 30 includes a first resistor R 1 and a second resistor R 2 . The first end of the first resistor R 1 is connected to the second external power interface 5 . The second terminal of a resistor R 1 and the first terminal of the second resistor R 2 are connected to the node X, and the second terminal of the second resistor R 2 is connected to the ground. The second end of the first resistor R 1 is connected to the ADC analog-to-digital conversion module 32 , that is, the first divided voltage V 1 of the X node is input to the ADC analog-to-digital conversion module 32 .
所述第二电阻负反馈网络31连接于低压差线性稳压器的电压输出端，所述第二电阻负反馈网络31对输出电压VOUT进行分压并生成第二分压电压V2，所述第二分压电压V2输入至ADC模数转换模块32。The second resistor negative feedback network 31 is connected to the voltage output end of the low voltage dropout linear regulator, and the second resistor negative feedback network 31 divides the output voltage V OUT and generates a second divided voltage V 2 , so The second divided voltage V 2 is input to the ADC analog-to-digital conversion module 32 .
本实施例中，所述第二电阻负反馈网络31包括第三电阻R3和第四电阻R4，所述第三电阻R3的第一端连接于低压差线性稳压器的电压输出端，所述第三电阻R3的第二端与第四电阻R4的第一端连接于节点Y，且第四电阻R4的第二端接地。所述第三电阻R3的第二端连接至ADC模数转换模块32，即将Y节点的第二分压电压V2输入至ADC模数转换模块32。In this embodiment, the second resistor negative feedback network 31 includes a third resistor R 3 and a fourth resistor R 4 . The first end of the third resistor R 3 is connected to the voltage output end of the low-voltage linear regulator. , the second end of the third resistor R 3 and the first end of the fourth resistor R 4 are connected to the node Y, and the second end of the fourth resistor R 4 is connected to the ground. The second end of the third resistor R 3 is connected to the ADC analog-to-digital conversion module 32 , that is, the second divided voltage V 2 of the Y node is input to the ADC analog-to-digital conversion module 32 .
所述第一分压电压V1可以表示为：
The first divided voltage V 1 can be expressed as:
所述第二分压电压V2可以表示为：
The second divided voltage V 2 can be expressed as:
本实例中，所述ADC模数转换模块32将第一分压电压V1转换为第一数字编码Code_VM，所述ADC模数转换模块32将第二分压电压V2转换为第二数字编码Code_VOUT，本实施例中使用第一电阻负反馈网络30和第二电阻负反馈网络31对高电压域外部电源VM和输出电压VOUT进行分压的目的在于，所述高电压域外部电源VM和输出电压VOUT均为处于高电压域的电源，而所述ADC模数转换模块32内的MOS器件的耐压是有限的，因此为了能够满足ADC模数转换模块32输出电压限制，从而对所述高电压域外部电源VM和输出电压VOUT进行分压处理。且分压电压值仍然能够满足与所述高电压域外部电源VM和输出电压VOUT间的线性关系。In this example, the ADC analog-to-digital conversion module 32 converts the first divided voltage V 1 into a first digital code Code_VM , and the ADC analog-to-digital conversion module 32 converts the second divided voltage V 2 into a second digital Code_V OUT , in this embodiment, the purpose of using the first resistor negative feedback network 30 and the second resistor negative feedback network 31 to divide the high voltage domain external power supply VM and the output voltage V OUT is that the external power supply VM of the high voltage domain is The power supply V M and the output voltage V OUT are both power supplies in the high voltage domain, and the withstand voltage of the MOS devices in the ADC analog-to-digital conversion module 32 is limited. Therefore, in order to meet the output voltage limit of the ADC analog-to-digital conversion module 32 , thereby performing voltage division processing on the high-voltage domain external power supply VM and the output voltage V OUT . And the divided voltage value can still satisfy the linear relationship with the high-voltage domain external power supply VM and the output voltage V OUT .
所述电压采样电路3中的ADC模数转换模块32连接于所述输出电压校准电路1中的数字逻辑单元12，所述数字逻辑单元12在接收到第一数字编码Code_VM和第二数字编码Code_VOUT后，结合其内部已经存储的表征低电压域外部电源VCC的第三数字编码Code_VCC进行数字逻辑运算。从而获得表征反馈电压VFB的第四数字编码Code_VFB。The ADC analog-to-digital conversion module 32 in the voltage sampling circuit 3 is connected to the digital logic unit 12 in the output voltage calibration circuit 1. The digital logic unit 12 receives the first digital code Code_V M and the second digital code. After Code_V OUT , it performs digital logic operations in combination with the third digital code Code_V CC that has been stored inside and represents the low-voltage domain external power supply V CC . Thus, a fourth digital code Code_V FB characterizing the feedback voltage V FB is obtained.
所述数字逻辑单元12连接于DAC数模转换模块11，且数字逻辑单元12将运算获得的所述第四数字编码Code_VFB输入至DAC数模转换模块11。所述DAC数模转换模块11将所述第四数字编码Code_VFB输入转换为模拟量的反馈电压VFB。所述反馈电压VFB经过滤波网络13后被输入至误差放大器10的反相输入端。The digital logic unit 12 is connected to the DAC digital-to-analog conversion module 11 , and the digital logic unit 12 inputs the fourth digital code Code_V FB obtained by the operation to the DAC digital-to-analog conversion module 11 . The DAC digital-to-analog conversion module 11 converts the fourth digital code Code_V FB input into an analog feedback voltage V FB . The feedback voltage V FB is input to the inverting input terminal of the error amplifier 10 after passing through the filter network 13 .
本实施例中，所述数字逻辑单元12对第一数字编码Code_VM、第二数字编码Code_VOUT和第三数字编码Code_VCC进行的数字逻辑运算为：In this embodiment, the digital logic operation performed by the digital logic unit 12 on the first digital code Code_VM , the second digital code Code_V OUT and the third digital code Code_V CC is:
第四数字编码Code_VFB＝第一数字编码Code_VM－第二数字编码Code_VOUT－第三数字编码Code_VCC。The fourth digital code Code_V FB = the first digital code Code_V M - the second digital code Code_V OUT - the third digital code Code_V CC .
即经过数字逻辑单元12的运算，所述第四数字编码Code_VFB即为表达(第一数字编码Code_VM－第三数字编码Code_VCC)与第二数字编码Code_VOUT之 间的差。更进一步的，征反馈电压VFB所表达的即为(高电压域外部电源VM－低电压域外部电源VCC)与输出电压VOUT之间的差。That is, after the operation of the digital logic unit 12, the fourth digital code Code_V FB is the sum of the expression (the first digital code Code_V M - the third digital code Code_V CC ) and the second digital code Code_V OUT . difference between. Furthermore, the feedback voltage V FB expresses the difference between (high voltage domain external power supply VM - low voltage domain external power supply V CC ) and the output voltage V OUT .
同时，本实施例中为了便于数字逻辑单元12的计算，在使用第一电阻负反馈网络30和第二电阻负反馈网络31对高电压域外部电源VM和输出电压VOUT进行分压时，对所述第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的阻值进行限定，具体为：
At the same time, in this embodiment, in order to facilitate the calculation of the digital logic unit 12, when using the first resistor negative feedback network 30 and the second resistor negative feedback network 31 to divide the high voltage domain external power supply V M and the output voltage V OUT , The resistance values of the first resistor R 1 , the second resistor R 2 , the third resistor R 3 and the fourth resistor R 4 are limited, specifically as follows:
这样，所述数字逻辑单元12对第一数字编码Code_VM、第二数字编码Code_VOUT无需再进行数值转换既可以保证第一数字编码Code_VM、第二数字编码Code_VOUT是等比例表达高电压域外部电源VM和输出电压VOUT的。In this way, the digital logic unit 12 does not need to perform numerical conversion on the first digital code Code_VM and the second digital code Code_V OUT , and can ensure that the first digital code Code_VM and the second digital code Code_V OUT are equal proportions expressing the high voltage domain. external power supply V M and output voltage V OUT .
例如，ADC模数转换模块32为9bits，则去的一个LSB代表100mV，那么当高电压域外部电源VM＝40V，所对应的第一数字编码Code_VM为400，输出电压VOUT为25V，所对应的第二数字编码Code_VOUT为250。当数字逻辑单元12中设定低电压域外部电源VCC为15V，所对应的第三数字编码Code_VCC为150。进而有第一数字编码Code_VM－第二数字编码Code_VOUT－第三数字编码Code_VCC＝0。For example, the ADC analog-to-digital conversion module 32 is 9 bits, and one LSB represents 100mV. Then when the high voltage domain external power supply V M =40V, the corresponding first digital code Code_V M is 400, and the output voltage V OUT is 25V. The corresponding second digital code Code_V OUT is 250. When the low-voltage domain external power supply V CC is set to 15V in the digital logic unit 12, the corresponding third digital code Code_V CC is 150. Furthermore, the first digital code Code_V M - the second digital code Code_V OUT - the third digital code Code_V CC =0.
在实际工作时，事先设定第三数字编码Code_VCC为某个值，然后设定高电压域外部电源VM和输出电压VOUT的电阻分压比，使得LSB代表的电压值符合设定，再由数字逻辑单元12进行逻辑运算。In actual work, set the third digital code Code_V CC to a certain value in advance, and then set the resistor voltage dividing ratio of the high-voltage domain external power supply V M and the output voltage V OUT so that the voltage value represented by LSB meets the setting. Then the digital logic unit 12 performs logical operations.
本实施例中将第四数字编码Code_VFB为零时，设定DAC数模转换模块11输出的反馈电压VFB等于参考电压VREF。例如，将DAC数模转换模块11的满幅值设定为2VREF，且当DAC数模转换模块11针对为零的第四数字编码Code_VFB输出为满幅值的一半。则当第四数字编码Code_VFB为零时，所述DAC数模转换模块11输出的反馈电压VFB即等于参考电压VREF。In this embodiment, when the fourth digital code Code_V FB is zero, the feedback voltage V FB output by the DAC digital-to-analog conversion module 11 is set to be equal to the reference voltage V REF . For example, the full-scale value of the DAC digital-to-analog conversion module 11 is set to 2V REF , and when the DAC digital-to-analog conversion module 11 outputs half of the full-scale value for the fourth digital code Code_V FB that is zero. Then when the fourth digital code Code_V FB is zero, the feedback voltage V FB output by the DAC digital-to-analog conversion module 11 is equal to the reference voltage VREF .
当误差放大器10的反相输入端输入的电压为VREF时，误差放大器10的输出端保持稳定。此时由于，VOUT＝VM-VCC，即本实施例的低压差线性稳压器输出了一个可以跟随高电压域外部电源VM变化的输出电压VOUT，并且通过调节数字逻辑内部的第三数字编码Code_VCC便可产生不同的跟随高电压域外部电源VM变 化的输出电压域。即VOUT＝m*(VM-VCC)，m为任意的正数。所述输出电压VOUT可以在VM至(VM-VCC)之间调节。When the voltage input to the inverting input terminal of the error amplifier 10 is V REF , the output terminal of the error amplifier 10 remains stable. At this time, since V OUT = VM - V CC , that is, the low-dropout linear regulator of this embodiment outputs an output voltage V OUT that can follow the change of the high-voltage domain external power supply VM , and by adjusting the internal digital logic The third digital code Code_V CC can generate different changes following the external power supply V M in the high voltage domain. ized output voltage domain. That is, V OUT =m*(V M -V CC ), m is any positive number. The output voltage V OUT can be adjusted between VM and ( VM - V CC ).
本实施例中的输出电压校准电路1和电压采样电路3共同构成了一个负反馈回路，用于保证输出电压VOUT稳定且精确。功率晶体管2选用NMOS管，便于在低压域中产生栅端的控制信号。当输出电压VOUT上升时，ADC模数转换模块32产生的第二数字编码Code_VOUT随之变大，同时第一数字编码Code_VM保持不变，则有Code_VFB＝Code_VM－Code_VOUT－Code_VCC<0，数字逻辑单元12输出Code_VFB小于DAC满幅值的一半。进而DAC数模转换模块11输出的电压VFB<VREF，使得误差放大器10的反相输入端电压降低，通过和正向输入端的基准电压VREF进行比较，使误差放大器10的输出电压Vop增加，从而使功率晶体管2产生的Sink电流升高，进而降低低压差线性稳压器的输出电压。反之亦然。The output voltage calibration circuit 1 and the voltage sampling circuit 3 in this embodiment together form a negative feedback loop to ensure that the output voltage V OUT is stable and accurate. The power transistor 2 uses an NMOS transistor to facilitate the generation of gate-end control signals in the low-voltage domain. When the output voltage V OUT rises, the second digital code Code_V OUT generated by the ADC analog-to-digital conversion module 32 becomes larger, while the first digital code Code_V M remains unchanged, then Code_V FB =Code_V M -Code_V OUT -Code_V CC <0, the output Code_V FB of the digital logic unit 12 is less than half of the full scale value of the DAC. Furthermore, the voltage V FB <V REF output by the DAC digital-to-analog conversion module 11 causes the voltage at the inverting input terminal of the error amplifier 10 to decrease. By comparing it with the reference voltage V REF at the forward input terminal, the output voltage V op of the error amplifier 10 increases. , thereby causing the Sink current generated by the power transistor 2 to increase, thereby reducing the output voltage of the low-dropout linear regulator. vice versa.
相比于现有技术，本实施例中的低压差线性稳压器所使用的ADC模块及DAC模块均可复用于低压差线性稳压器所处电路***中的已有的模块。通过ADC和数字逻辑单元实现了与电源电压相关的基准电压差，并通过LDO负反馈环路，产生精确稳定且可跟随电压源变化的输出电压。通过调节数字逻辑内部的code_VCC的大小，可以产生跟随电源电压VM变化的电压域，用于驱动高端栅极，具有更广阔的应用前景。Compared with the existing technology, the ADC module and the DAC module used in the low dropout linear regulator in this embodiment can be reused with existing modules in the circuit system where the low dropout linear regulator is located. The reference voltage difference related to the power supply voltage is realized through the ADC and digital logic unit, and through the LDO negative feedback loop, an output voltage that is accurate and stable and can follow the changes of the voltage source is generated. By adjusting the size of code_V CC inside the digital logic, a voltage domain that follows the change of the power supply voltage V M can be generated to drive the high-end gate, which has broader application prospects.
以上所述，仅为本发明的具体实施案例，本发明的保护范围并不局限于此，任何熟悉本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的保护范围之内。 The above are only specific implementation examples of the present invention, and the protection scope of the present invention is not limited thereto. Any modification or replacement of the present invention within the technical specifications described in the present invention by any skilled person familiar with the technology should be made. within the protection scope of the present invention.

Claims (8)

  1. 一种可实现输出电压调节的数模混合低压差线性稳压器，其特征在于，所述低压差线性稳压器包括输出电压校准电路、功率晶体管、电压采样电路、第一外部电源接口和第二外部电源接口；A digital-analog hybrid low-voltage dropout linear regulator that can realize output voltage adjustment, characterized in that the low-dropout linear regulator includes an output voltage calibration circuit, a power transistor, a voltage sampling circuit, a first external power interface and a third Two external power interfaces;
    所述输出电压校准电路包括误差放大器、DAC数模转换模块、数字逻辑单元、滤波网络、启动电路和基准电路；所述电压采样电路包括第一电阻负反馈网络、第二电阻负反馈网络和ADC模数转换模块；The output voltage calibration circuit includes an error amplifier, a DAC digital-to-analog conversion module, a digital logic unit, a filter network, a startup circuit and a reference circuit; the voltage sampling circuit includes a first resistor negative feedback network, a second resistor negative feedback network and an ADC Analog-to-digital conversion module;
    所述第一外部电源接口连接低电压域外部电压VCC，所述第二外部电源接口连接高电压域外部电压VM，所述低电压外部电压VCC经过启动电路和基准电路生成参考电压VREF，所述参考电压VREF输入到误差放大器的同相输入端；The first external power interface is connected to the low-voltage domain external voltage V CC , the second external power interface is connected to the high-voltage domain external voltage VM , and the low-voltage external voltage V CC generates the reference voltage V through the startup circuit and the reference circuit. REF , the reference voltage V REF is input to the non-inverting input terminal of the error amplifier;
    所述误差放大器的输出端连接于功率晶体管的栅极，所述功率晶体管的源极接地，所述功率晶体管的漏极为所述低压差线性稳压器的电压输出端；The output terminal of the error amplifier is connected to the gate of the power transistor, the source of the power transistor is grounded, and the drain of the power transistor is the voltage output terminal of the low voltage dropout linear regulator;
    所述第一电阻负反馈网络连接于第二外部电源接口，所述第一电阻负反馈网络对高电压域外部电压VM进行分压并生成第一分压电压V1，所述第一分压电压V1被输入至ADC模数转换模块；The first resistor negative feedback network is connected to the second external power interface. The first resistor negative feedback network divides the high voltage domain external voltage V M and generates a first divided voltage V 1 . The voltage V 1 is input to the ADC analog-to-digital conversion module;
    所述第二电阻负反馈网络连接于低压差线性稳压器的电压输出端，所述第二电阻负反馈网络对所述电压输出端的输出电压VOUT进行分压并生成第二分压电压V2，所述第二分压电压V2输入至ADC模数转换模块；The second resistor negative feedback network is connected to the voltage output end of the low voltage dropout linear regulator, and the second resistor negative feedback network divides the output voltage V OUT of the voltage output end and generates a second divided voltage V 2. The second divided voltage V 2 is input to the ADC analog-to-digital conversion module;
    所述ADC模数转换模块将第一分压电压V1转换为第一数字编码Code_VM，将第二分压电压V2转换为第二数字编码Code_VOUT；并将第一数字编码Code_VM和第二数字编码Code_VOUT输入至数字逻辑单元；The ADC analog-to-digital conversion module converts the first divided voltage V 1 into a first digital code Code_VM , and converts the second divided voltage V 2 into a second digital code Code_V OUT ; and converts the first digital code Code_VM and The second digital code Code_V OUT is input to the digital logic unit;
    所述数字逻辑单元存储有表征低电压域外部电压VCC的第三数字编码Code_VCC；同时所述所述数字逻辑单元对第一数字编码Code_VM、第二数字编码Code_VOUT和第三数字编码Code_VCC进行的数字逻辑运算已获得表征反馈电压VFB的第四数字编码Code_VFB；所述数字逻辑运算为：The digital logic unit stores a third digital code Code_V CC that represents the low-voltage domain external voltage V CC ; at the same time, the digital logic unit stores the first digital code Code_V M , the second digital code Code_V OUT and the third digital code The digital logic operation performed by Code_V CC has obtained the fourth digital code Code_V FB that represents the feedback voltage V FB ; the digital logic operation is:
    第四数字编码Code_VFB＝第一数字编码Code_VM－第二数字编码Code_VOUT－第三数字编码Code_VCC； The fourth digital code Code_V FB = the first digital code Code_V M - the second digital code Code_V OUT - the third digital code Code_V CC ;
    所述第四数字编码Code_VFB输入至DAC数模转换模块；所述DAC数模转换模块将所述第四数字编码Code_VFB转换为反馈电压VFB；且所述DAC数模转换模块对数值为零的第四数字编码Code_VFB输出的反馈电压VFB等于参考电压VREF；所述反馈电压VFB经过滤波网络后被输入至误差放大器的反相输入端；The fourth digital code Code_V FB is input to the DAC digital-to-analog conversion module; the DAC digital-to-analog conversion module converts the fourth digital code Code_V FB into the feedback voltage V FB ; and the log value of the DAC digital-to-analog conversion module is The feedback voltage V FB output by the fourth digital code Code_V FB of zero is equal to the reference voltage V REF ; the feedback voltage V FB is input to the inverting input terminal of the error amplifier after passing through the filter network;
    通过调节数字逻辑单元内部的第三数字编码Code_VCC使输出电压VOUT在VM至(VM-VCC)之间调节。The output voltage V OUT is adjusted between VM and (V M -V CC ) by adjusting the third digital code Code_V CC inside the digital logic unit.
  2. 根据权利要求1所述的低压差线性稳压器，其特征在于，所述DAC数模转换模块的满幅值设定为2倍反馈电压VREF，且当DAC数模转换模块针对为零的第四数字编码Code_VFB输出为满幅值的一半；即当第四数字编码Code_VFB为零时，所述DAC数模转换模块输出的反馈电压VFB等于参考电压VREF。The low dropout linear voltage regulator according to claim 1, characterized in that the full amplitude value of the DAC digital-to-analog conversion module is set to 2 times the feedback voltage VREF , and when the DAC digital-to-analog conversion module is zero The output of the fourth digital code Code_V FB is half of the full amplitude value; that is, when the fourth digital code Code_V FB is zero, the feedback voltage V FB output by the DAC digital-to-analog conversion module is equal to the reference voltage V REF .
  3. 根据权利要求1所述的低压差线性稳压器，其特征在于，所述第一电阻负反馈网络包括第一电阻R1和第二电阻R2，所述第一电阻R1的第一端连接于第二外部电源接口，所述第一电阻R1的第二端与第二电阻R2的第一端连接于节点X，且第二电阻R2的第二端接地；所述第一电阻R1的第二端连接至ADC模数转换模块，即将X节点的第一分压电压V1输入至ADC模数转换模块。The low dropout linear voltage regulator according to claim 1, wherein the first resistor negative feedback network includes a first resistor R1 and a second resistor R2 , and the first terminal of the first resistor R1 Connected to the second external power interface, the second end of the first resistor R 1 and the first end of the second resistor R 2 are connected to the node X, and the second end of the second resistor R 2 is grounded; the first The second end of the resistor R 1 is connected to the ADC analog-to-digital conversion module, that is, the first divided voltage V 1 of the X node is input to the ADC analog-to-digital conversion module.
  4. 根据权利要求3所述的低压差线性稳压器，其特征在于，所述第二电阻负反馈网络包括第三电阻R3和第四电阻R4，所述第三电阻R3的第一端连接于低压差线性稳压器的电压输出端，所述第三电阻R3的第二端与第四电阻R4的第一端连接于节点Y，且第四电阻R4的第二端接地。所述第三电阻R3的第二端连接至ADC模数转换模块，即将Y节点的第二分压电压V2输入至ADC模数转换模块。The low dropout linear regulator according to claim 3, wherein the second resistor negative feedback network includes a third resistor R3 and a fourth resistor R4 , and the first end of the third resistor R3 Connected to the voltage output end of the low-dropout linear regulator, the second end of the third resistor R 3 and the first end of the fourth resistor R 4 are connected to the node Y, and the second end of the fourth resistor R 4 is grounded. . The second end of the third resistor R 3 is connected to the ADC analog-to-digital conversion module, that is, the second divided voltage V 2 of the Y node is input to the ADC analog-to-digital conversion module.
  5. 根据权利要求4所述的低压差线性稳压器，其特征在于，所述第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的阻值满足于：
    The low dropout linear regulator according to claim 4, wherein the resistance values of the first resistor R 1 , the second resistor R 2 , the third resistor R 3 and the fourth resistor R 4 satisfy:
  6. 根据权利要求1所述的低压差线性稳压器，其特征在于，所述ADC模数转换模块和所述DAC数模转换模块被复用。The low dropout linear voltage regulator according to claim 1, wherein the ADC analog-to-digital conversion module and the DAC digital-to-analog conversion module are multiplexed.
  7. 根据权利要求1所述的低压差线性稳压器，其特征在于，所述低压差线性稳压器的负载连接于第二外部电源接口与功率晶体管漏极之间。The low-dropout linear regulator according to claim 1, wherein the load of the low-dropout linear regulator is connected between the second external power interface and the drain of the power transistor.
  8. 一种集成电路结构，所述集成电路结构中包含权利要求1-7之一所述的低 压差线性稳压器。 An integrated circuit structure, the integrated circuit structure includes the low-voltage device according to one of claims 1-7 Dropout Linear Regulator.
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