WO2023245719A1 - 时序逻辑元件性能检查方法及设备 - Google Patents

时序逻辑元件性能检查方法及设备 Download PDF

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WO2023245719A1
WO2023245719A1 PCT/CN2022/103203 CN2022103203W WO2023245719A1 WO 2023245719 A1 WO2023245719 A1 WO 2023245719A1 CN 2022103203 W CN2022103203 W CN 2022103203W WO 2023245719 A1 WO2023245719 A1 WO 2023245719A1
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sequential logic
target
logic element
circuit
simulation
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PCT/CN2022/103203
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English (en)
French (fr)
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吴增泉
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长鑫存储技术有限公司
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Priority to US18/094,100 priority Critical patent/US20230419008A1/en
Publication of WO2023245719A1 publication Critical patent/WO2023245719A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a sequential logic element performance inspection method and device.
  • STA Static Timing Analysis
  • Embodiments of the present disclosure provide a sequential logic element performance inspection method and device, which can quickly complete the inspection of the characteristic parameters of the sequential logic element and improve the design efficiency of integrated circuits.
  • embodiments of the present disclosure provide a method for checking the performance of sequential logic components, which is applied to a circuit to be simulated, where the circuit to be simulated includes a plurality of sequential logic components.
  • the method includes:
  • multiple simulation waveforms are used to simulate the circuit to be simulated to obtain simulation results; wherein, the performance check files are used to check each of the timings during the simulation process. Whether the target characteristic parameter of the logic element meets the preset condition, and output identification information of the target sequential logic element whose target characteristic parameter does not meet the preset condition in the simulation result.
  • the method before obtaining the performance check file corresponding to each of the sequential logic elements, the method further includes:
  • the method further includes:
  • the target simulation waveform it is determined whether there is a timing error in the target sequential logic elements belonging to the same path.
  • the method further includes:
  • the input signal of the target sequential logic element belonging to the same path is adjusted.
  • the sequential logic element includes a flip-flop and/or a latch;
  • the target characteristic parameter includes a setup time and/or a hold time.
  • adjusting the input signals of the target sequential logic elements belonging to the same path includes:
  • embodiments of the present disclosure provide a sequential logic element performance inspection device, which is applied to a circuit to be simulated.
  • the circuit to be simulated includes a plurality of sequential logic elements.
  • the device includes:
  • An acquisition module used to acquire performance check files corresponding to each of the sequential logic elements
  • a simulation module is used to simulate the circuit to be simulated using a variety of simulation waveforms based on the performance check files corresponding to each of the sequential logic elements to obtain simulation results; wherein the performance check files are used to perform simulation during the simulation process. Check whether the target characteristic parameters of each of the sequential logic elements meet the preset conditions, and output identification information of the target sequential logic elements whose target characteristic parameters do not meet the preset conditions in the simulation results.
  • it also includes a configuration module for:
  • it also includes a processing module for:
  • the target simulation waveform it is determined whether there is a timing error in the target sequential logic elements belonging to the same path.
  • it also includes an adjustment module for:
  • the input signal of the target sequential logic element belonging to the same path is adjusted.
  • the sequential logic element includes a flip-flop and/or a latch;
  • the target characteristic parameter includes a setup time and/or a hold time.
  • the adjustment module is specifically used to:
  • embodiments of the present disclosure provide an electronic device, including: at least one processor and a memory;
  • the memory stores computer execution instructions
  • the at least one processor executes the computer execution instructions stored in the memory, so that the at least one processor executes the sequential logic element performance inspection method provided in the first aspect.
  • embodiments of the present disclosure provide a computer-readable storage medium.
  • Computer-executable instructions are stored in the computer-readable storage medium.
  • the processor executes the computer-executable instructions, the timing sequence provided in the first aspect is implemented.
  • Logic component performance checking methods are implemented.
  • embodiments of the present disclosure provide a computer program product, including a computer program.
  • the computer program When the computer program is executed by a processor, the method for checking the performance of sequential logic elements as provided in the first aspect is implemented.
  • the sequential logic element performance inspection method and device when inspecting the circuit to be simulated, obtain the performance inspection file corresponding to each sequential logic element in the circuit to be simulated, and then based on the performance inspection file corresponding to each sequential logic element, Use a variety of simulation waveforms to simulate the circuit to be simulated to obtain simulation results; among them, the above performance check file can check whether the target characteristic parameters of each sequential logic element meet the preset conditions during the simulation process, and output the target characteristics in the simulation results Compared with manual inspection, the identification information of target sequential logic components whose parameters do not meet the preset conditions not only saves time and effort, but also has higher accuracy, which can effectively improve the design efficiency of integrated circuits.
  • Figure 1 is a schematic diagram of the setup time and hold time of sequential logic elements in an embodiment of the present disclosure
  • Figure 2 is a schematic flowchart of the steps of a method for checking the performance of sequential logic components provided in an embodiment of the present disclosure
  • Figure 3 is a schematic step flow diagram of another method for checking the performance of sequential logic components provided in an embodiment of the present disclosure
  • Figure 4 is a schematic step flow diagram of yet another method for checking the performance of sequential logic components provided in an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of a program module of a sequential logic element performance inspection device provided in an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present disclosure.
  • module refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic or combination of hardware or/and software code capable of performing the functions associated with that element .
  • PKI process design kits
  • the above-mentioned sequential logic elements can be latch (Latch), flip-flop (Flip Flop, referred to as FF), etc.
  • latches are memory cell circuits that are sensitive to pulse levels. They can change state under the action of a specific input pulse level. Latching is to temporarily store signals to maintain a certain level state. In digital circuits, binary digital signals "0" and "1" can be recorded.
  • a flip-flop also called a bistable gate, is a storage component with two stable states that can record binary digital signals "1" and "0". Its output is determined by the data input at the time specified by the input clock. .
  • the setup time (Setup Time) of the sequential logic element refers to the shortest time that the data input signal must remain stable before the valid edge of the clock; the hold time (Hold time) refers to the data input signal must remain stable after the valid edge of the clock. the shortest time.
  • the sequential logic element can correctly collect the data; and after the valid edge of the clock (or at the same time) At the same time), even if the data changes, it will not affect the output of the sequential logic element.
  • FIG. 1 is a schematic diagram of the setup time and hold time of the sequential logic elements in the embodiment of the present disclosure.
  • embodiments of the present disclosure provide a sequential logic element performance inspection method.
  • the performance inspection file corresponding to each sequential logic element in the circuit to be simulated is obtained, and then based on each sequential logic element
  • the corresponding performance check file uses a variety of simulation waveforms to simulate the circuit to be simulated to obtain simulation results; among them, the above performance check file can check whether the target characteristic parameters of each sequential logic element meet the preset conditions during the simulation process, and The simulation results output the identification information of the target sequential logic components whose target characteristic parameters do not meet the preset conditions.
  • it not only saves time and effort, but also has higher accuracy, which can effectively improve the design efficiency of integrated circuits.
  • FIG. 2 is a schematic flowchart of steps of a sequential logic element performance inspection method provided in an embodiment of the present disclosure.
  • the above sequential logic element performance inspection method can be applied to a circuit to be simulated, which includes multiple sequential logic elements.
  • the above sequential logic element performance inspection method includes:
  • a test platform can be established in advance, and software can be used in the test platform to simulate a circuit to be simulated, where the circuit to be simulated includes at least one sequential logic element.
  • the above-mentioned sequential logic element can sample the input data signal according to the clock signal.
  • the above-mentioned sequential logic elements may be latches, flip-flops, etc., which are not limited by the embodiments of this disclosure.
  • a performance check file corresponding to each sequential logic element can be configured in advance.
  • the performance check file can monitor the output signal of each sequential logic element during the simulation process and determine whether the output signal of each sequential logic element meets the output expectations. .
  • the above simulation waveform includes a clock signal and an input data signal.
  • a variety of different clock signals and input data signals can be selected in advance, and specific simulation tools can be used to simulate the circuit to be simulated multiple times based on the performance check files corresponding to each of the above sequential logic components.
  • Different simulation waveforms correspond to different clock signals and/or input data signals.
  • each sequential logic element can sample the input data signal according to the clock signal.
  • the target characteristic parameter of each sequential logic element is the setup time (Setup Time).
  • the setup time is between the target edge of the clock signal and the target edge of the target sample value in the input data signal. time difference.
  • the sequential logic element may output the inverse value of the target sample value because it cannot collect the target sample value, or may output the reverse value of the target sample value with a higher delay. Output the above target sample value.
  • the output data of the sequential logic element or the output delay of the sequential logic element can be monitored, and then compared with the output data or output delay threshold set in the performance check file corresponding to the sequential logic element, If the output data of the sequential logic element is inconsistent with the output data set in the performance check file corresponding to the sequential logic element, or the output delay of the sequential logic element is greater than the output delay threshold set in the performance check file corresponding to the sequential logic element, Then it can be considered that the establishment time of the sequential logic element does not meet the above preset conditions.
  • the identification information of its corresponding sequential logic element will be Output to simulation results for review by design engineers or for one-step screening.
  • the sequential logic element performance inspection method when inspecting the circuit to be simulated, obtains the performance inspection file corresponding to each sequential logic element in the circuit to be simulated, and then uses multiple performance inspection files based on the performance inspection file corresponding to each sequential logic element.
  • Each simulation waveform simulates the circuit to be simulated separately to obtain simulation results; among them, the above-mentioned performance check file can check whether the target characteristic parameters of each sequential logic element meet the preset conditions during the simulation process, and output whether the target characteristic parameters are satisfied in the simulation results.
  • the identification information of target sequential logic components that meet the preset conditions not only saves time and effort, but also has higher accuracy, which can effectively improve the design efficiency of integrated circuits.
  • FIG. 3 is a schematic flowchart of steps of another sequential logic element performance inspection method provided in an embodiment of the present disclosure.
  • the above sequential logic element performance inspection method includes:
  • Step S301 Generate a netlist corresponding to the circuit to be simulated according to the design database of the circuit to be simulated.
  • the chip design stage will clarify the purpose, specifications, and performance of the chip.
  • the chip design can be divided into processes such as function definition, system-level design, front-end design, and back-end design.
  • System design refers to clarifying the system-level design such as chip architecture, business modules, and power supply based on the early functional definition.
  • designers carry out specific circuit design for each module based on the plan determined by the system design, and use a specialized hardware description language to describe the specific circuit implementation at the register transfer level (RTL) level.
  • RTL register transfer level
  • logic synthesis tools are used to convert RTL-level codes written in hardware description languages into gate-level netlists to ensure that the circuit meets target parameters such as area and timing.
  • the entire design process is an iterative process. If any step fails to meet the requirements, the previous steps need to be repeated or even the RTL code redesigned.
  • the back-end design is based on the netlist first, laying out and routing the circuit within a given size of silicon chip area, and then conducting various functional and timing verifications on the physical layout of the wiring. The back-end design is also an iteration If the verification does not meet the requirements, you need to repeat the previous steps and finally generate a Graphic Data Stream (GDS) file for chip production.
  • GDS Graphic Data Stream
  • a netlist corresponding to the circuit to be simulated can be generated based on the design database of the circuit to be simulated.
  • the netlist includes circuit description statements of the circuit to be simulated, such as the connection method of the circuit, the components constituting the circuit, Properties, parameters, identification information, etc. of devices, power nodes, etc.
  • Step S302 Find each sequential logic element in the netlist corresponding to the circuit to be simulated according to the preset keywords.
  • the keywords of the identification information corresponding to each sequential logic element in the circuit to be simulated can be determined in advance.
  • the identification information corresponding to all latches in the circuit to be simulated usually contains the keyword "Latch”, Then all latches can be found in the netlist corresponding to the circuit to be simulated through the keyword "Latch”; similarly, the identification information corresponding to all flip-flops in the circuit to be simulated usually contains the keyword "FF", then through The keyword "FF" can find all flip-flops in the netlist corresponding to the circuit to be simulated.
  • Step S303 Configure performance check files corresponding to each sequential logic element.
  • the performance check file corresponding to each sequential logic element can be configured based on the chktiming statement.
  • the ideal output data, output delay, etc. of the sequential logic components can be set in the above performance check file.
  • the above performance check file can be recognized by the simulation tool used in the embodiment of the present disclosure.
  • the above simulation tool can be the finesim simulator.
  • Step S304 Based on the performance check files corresponding to each sequential logic element, use multiple simulation waveforms to simulate the circuit to be simulated to obtain simulation results.
  • the above performance check file is used to check whether the target characteristic parameters of each sequential logic element meet the preset conditions during the simulation process, and to output the identification information of the target sequential logic element whose target characteristic parameters do not meet the preset conditions in the simulation results.
  • reasonable clock signals and input data signals can be selected in advance, and then the circuit to be simulated can be simulated based on the performance check files corresponding to each of the above sequential logic components.
  • each sequential logic element can sample the input data signal according to the clock signal.
  • the target characteristic parameter as setup time (Setup Time) as an example.
  • the above performance check file can monitor the output data of the sequential logic element, or the output data of the sequential logic element. The output delay is then compared with its set output data or output delay threshold. If the output data of the sequential logic element is inconsistent with the output data set in the performance check file corresponding to the sequential logic element, or the output delay of the sequential logic element time is greater than the output delay threshold set in the performance check file corresponding to the sequential logic element, it can be determined that the establishment time of the sequential logic element does not meet the above preset conditions.
  • the identification information of its corresponding sequential logic element is output to the simulation result for the design engineer to view.
  • the target sequential logic element output in the simulation result can be determined to be a sequential logic element with potential timing errors, such as a sequential logic element with insufficient setup time or hold time.
  • the setup time of the sequential logic element when the setup time of the sequential logic element is sufficient, the data signal is relatively stable when the effective edge of the clock signal arrives, so the clock-to-output delay of the sequential logic element will be smaller and the size is relatively stable; when the timing When the setup time of the logic element is insufficient, the data signal may not be in a stable state when the valid edge of the clock signal arrives. Therefore, the clock-to-output delay of the sequential logic element will also increase, and the less sufficient the setup time, the lower the timing. The greater the clock-to-output delay of the logic element; when the setup time of the sequential logic element is reduced to the point where it cannot collect the target sample value when the valid edge of the clock signal arrives, the sequential logic element will fail to output the target sample value. At this time, Sequential logic elements have zero clock-to-output delay.
  • Step S305 Determine the minimum target characteristic parameter corresponding to the target sequential logic element belonging to the same path in the simulation result, and the target simulation waveform corresponding to the minimum target characteristic parameter.
  • the same path refers to a hierarchy of instantiated flip-flops or latches.
  • Step S306 Determine whether the target sequential logic elements belonging to the same path have timing errors according to the target simulation waveform. If yes, adjust the input signal of the target sequential logic element belonging to the same path in the design database of the circuit to be simulated; if not, end the process.
  • the target characteristic parameter as the setup time
  • the simulation waveform corresponding to the minimum target characteristic parameters when multiple simulation waveforms are used to simulate the circuit to be simulated, there will be differences in the setup time corresponding to the target sequential logic elements output in the simulation results, because the setup time is longer.
  • the clock signals and/or corresponding to the above-mentioned target sequential logic elements belonging to the same path can be adjusted in the design database of the circuit to be simulated. Data input signal.
  • the above-mentioned input data signal can be advanced and/or the clock signal can be delayed.
  • the sequential logic element performance inspection method determines, after obtaining the simulation results, the minimum target characteristic parameters corresponding to the target sequential logic elements belonging to the same path in the simulation results, and the simulation waveform corresponding to the minimum target characteristic parameters, According to the simulation waveform, it is determined whether the above-mentioned target sequential logic elements belonging to the same path have timing errors, which can effectively improve the inspection efficiency of the sequential logic elements.
  • FIG. 4 is a schematic flowchart of steps of yet another sequential logic element performance inspection method provided in an embodiment of the present disclosure.
  • the above sequential logic element performance inspection method includes:
  • each sequential logic element can be found in the above netlist according to preset keywords, and a performance check file corresponding to each sequential logic element can be configured.
  • multiple simulation waveforms can be used to simulate the circuit to be simulated respectively, and the simulation results can be obtained.
  • the above-mentioned performance check file can check whether the target characteristic parameters of each sequential logic element meet the preset conditions during the simulation process, and output target identification information in the simulation results that the target characteristic parameters do not meet the above-mentioned preset conditions.
  • the minimum target characteristic parameter corresponding to the target sequential logic element belonging to the same path in the simulation result is determined, and the simulation waveform corresponding to the minimum target characteristic parameter is determined.
  • the sequential logic element performance inspection method provided by the embodiments of the present disclosure can quickly find the sequential logic elements with timing errors in the circuit to be simulated. Compared with the manual inspection method, it not only saves time and effort, but also has higher accuracy, so that it can Effectively improve the design efficiency of integrated circuits.
  • embodiments of the present disclosure also provide a sequential logic element performance inspection device, which is applied to a circuit to be simulated, and the circuit to be simulated includes a plurality of sequential logic elements.
  • Figure 5 is a schematic diagram of a program module of a sequential logic element performance inspection device provided in an embodiment of the present disclosure.
  • the sequential logic element performance inspection device includes:
  • the acquisition module 501 is used to acquire performance check files corresponding to each sequential logic element.
  • the simulation module 502 is used to simulate the circuit to be simulated using a variety of simulation waveforms based on the performance check files corresponding to each of the sequential logic elements to obtain simulation results; wherein the performance check files are used in the simulation process Check whether the target characteristic parameters of each of the sequential logic elements meet the preset conditions, and output identification information of the target sequential logic elements whose target characteristic parameters do not meet the preset conditions in the simulation results.
  • the above device further includes a configuration module for:
  • the above device further includes a processing module for:
  • the target simulation waveform it is determined whether there is a timing error in the target sequential logic elements belonging to the same path.
  • the above device further includes an adjustment module for:
  • the input signal of the target sequential logic element belonging to the same path is adjusted.
  • the above adjustment module is specifically used to:
  • the sequential logic element performance inspection device when inspecting the circuit to be simulated, obtains the performance inspection file corresponding to each sequential logic element in the circuit to be simulated, and then uses multiple performance inspection files based on the performance inspection file corresponding to each sequential logic element.
  • Each simulation waveform simulates the circuit to be simulated separately to obtain simulation results; among them, the above-mentioned performance check file can check whether the target characteristic parameters of each sequential logic element meet the preset conditions during the simulation process, and output whether the target characteristic parameters are satisfied in the simulation results.
  • the identification information of target sequential logic components that meet the preset conditions not only saves time and effort, but also has higher accuracy, which can effectively improve the design efficiency of integrated circuits.
  • embodiments of the present disclosure also provide an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor The computer execution instructions stored in the memory are executed to implement each step in the sequential logic element performance inspection method as described in the above embodiment, which will not be described again in this embodiment.
  • FIG. 6 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • the electronic device 60 of this embodiment includes: a processor 601 and a memory 602; wherein:
  • Memory 602 used to store computer execution instructions
  • the processor 601 is configured to execute computer execution instructions stored in the memory to implement various steps in the sequential logic element performance inspection method described in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.
  • the memory 602 can be independent or integrated with the processor 601 .
  • the device When the memory 502 is provided independently, the device also includes a bus 603 for connecting the memory 602 and the processor 601 .
  • embodiments of the present disclosure also provide a computer-readable storage medium, which stores computer-executable instructions.
  • the processor executes the computer-executed instructions, , to implement each step in the sequential logic element performance inspection method as described in the above embodiment, which will not be described again in this embodiment.
  • the embodiments of the present disclosure also provide a computer program product.
  • the computer program product stores computer execution instructions.
  • the processor executes the computer execution instructions, to implement the following: Each step in the sequential logic element performance inspection method described in the above embodiment will not be described again in this embodiment.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the above modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules may be combined or integrated into Another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms.
  • the modules described above as separate components may or may not be physically separated.
  • the components shown as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in various embodiments of the present disclosure can be integrated into a processing unit, or each module can exist physically alone, or two or more modules can be integrated into one unit.
  • the above-mentioned module integrated units can be implemented in the form of hardware or in the form of hardware plus software functional units.

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Abstract

本公开实施例提供一种时序逻辑元件性能检查方法及设备，涉及半导体技术领域，在对待仿真电路进行检查时，获取待仿真电路中各个时序逻辑元件对应的性能检查文件，然后基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果；其中，上述性能检查文件可以在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信息，相较于人工检查的方式，不仅省时省力，而且准确性更高，从而能够有效提升集成电路的设计效率。

Description

时序逻辑元件性能检查方法及设备
本公开要求于2022年06月22日提交中国专利局、申请号为202210711774.X、申请名称为“时序逻辑元件性能检查方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种时序逻辑元件性能检查方法及设备。
背景技术
目前，在进行基于标准单元库的专用集成电路(Application Specific Integrated Circuit，简称ASIC)设计时，通常采用静态时序分析(Static Timing Analysis，简称STA)方式来分析诸如触发器、锁存器等时序逻辑元件的特性参数(如建立时间或保持时间等)。
然而，在全定制集成电路设计过程中，时序逻辑元件的特性参数的检查却比较困难，需要依靠人工检查，费时费力，影响集成电路的设计效率。
发明内容
本公开实施例提供了一种时序逻辑元件性能检查方法及设备，可以快速完成对时序逻辑元件的特性参数的检查，提升集成电路的设计效率。
第一方面，本公开实施例提供一种时序逻辑元件性能检查方法，应用于待仿真电路，所述待仿真电路中包括多个时序逻辑元件，所述方法包括：
获取各个所述时序逻辑元件对应的性能检查文件；
基于各个所述时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对所述待仿真电路进行仿真，得到仿真结果；其中，所述性能检查文件用于在仿真过程中检查各个所述时序逻辑元件的目标特性参数是否满足预设条件，并在所述仿真结果中输出目标特性参数不满足所述预设条件的目标时序逻辑元件的标识信息。
在一种可行的实施方式中，所述获取各个所述时序逻辑元件对应的性 能检查文件之前，还包括：
根据所述待仿真电路的设计数据库，生成所述待仿真电路对应的网表；
根据预设关键词，在所述待仿真电路对应的网表中查找出各个所述时序逻辑元件；
配置各个所述时序逻辑元件对应的性能检查文件。
在一种可行的实施方式中，所述得到仿真结果之后，还包括：
确定所述仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及所述最小目标特性参数对应的目标仿真波形；
根据所述目标仿真波形，确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误。
在一种可行的实施方式中，所述确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误之后，还包括：
当确定所述属于同一路径下的目标时序逻辑元件存在时序错误时，调整所述属于同一路径下的目标时序逻辑元件的输入信号。
在一种可行的实施方式中，所述时序逻辑元件包括触发器和/或锁存器；所述目标特性参数包括建立时间和/或保持时间。
在一种可行的实施方式中，所述调整所述属于同一路径下的目标时序逻辑元件的输入信号，包括：
调整所述属于同一路径下的目标时序逻辑元件对应的时钟信号和/或数据输入信号。
第二方面，本公开实施例提供一种时序逻辑元件性能检查装置，应用于待仿真电路，所述待仿真电路中包括多个时序逻辑元件，所述装置包括：
获取模块，用于获取各个所述时序逻辑元件对应的性能检查文件；
仿真模块，用于基于各个所述时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对所述待仿真电路进行仿真，得到仿真结果；其中，所述性能检查文件用于在仿真过程中检查各个所述时序逻辑元件的目标特性参数是否满足预设条件，并在所述仿真结果中输出目标特性参数不满足所述预设条件的目标时序逻辑元件的标识信息。
在一种可行的实施方式中，还包括配置模块，用于：
根据所述待仿真电路的设计数据库，生成所述待仿真电路对应的网表；
根据预设关键词，在所述待仿真电路对应的网表中查找出各个所述时序逻辑元件；
配置各个所述时序逻辑元件对应的性能检查文件。
在一种可行的实施方式中，还包括处理模块，用于：
确定所述仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及所述最小目标特性参数对应的目标仿真波形；
根据所述目标仿真波形，确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误。
在一种可行的实施方式中，还包括调整模块，用于：
当确定所述属于同一路径下的目标时序逻辑元件存在时序错误时，调整所述属于同一路径下的目标时序逻辑元件的输入信号。
在一种可行的实施方式中，所述时序逻辑元件包括触发器和/或锁存器；所述目标特性参数包括建立时间和/或保持时间。
在一种可行的实施方式中，所述调整模块具体用于：
调整所述属于同一路径下的目标时序逻辑元件对应的时钟信号和/或数据输入信号。
第三方面，本公开实施例提供一种电子设备，包括：至少一个处理器和存储器；
所述存储器存储计算机执行指令；
所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如第一方面提供的时序逻辑元件性能检查方法。
第四方面，本公开实施例提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如第一方面提供的时序逻辑元件性能检查方法。
第五方面，本公开实施例提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时，实现如第一方面提供的时序逻辑元件性能检查方法。
本公开实施例提供的时序逻辑元件性能检查方法及设备，在对待仿真电路进行检查时，获取待仿真电路中各个时序逻辑元件对应的性能检查文件，然后基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形 分别对待仿真电路进行仿真，得到仿真结果；其中，上述性能检查文件可以在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信息，相较于人工检查的方式，不仅省时省力，而且准确性更高，从而能够有效提升集成电路的设计效率。
附图说明
图1为本公开实施例中时序逻辑元件的建立时间与保持时间示意图；
图2为本公开实施例中提供的一种时序逻辑元件性能检查方法的步骤流程示意图；
图3为本公开实施例中提供的另一种时序逻辑元件性能检查方法的步骤流程示意图；
图4为本公开实施例中提供的又一种时序逻辑元件性能检查方法的步骤流程示意图；
图5为本公开实施例中提供的一种时序逻辑元件性能检查装置的程序模块示意图；
图6为本公开实施例中提供的一种电子设备的硬件结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。此外，虽然本公开中公开内容按照示范性一个或几个实例来介绍，但应理解，可以就这些公开内容的各个方面也可以单独构成一个完整实施方式。
需要说明的是，本公开中对于术语的简要说明，仅是为了方便理解接下来描述的实施方式，而不是意图限定本公开的实施方式。除非另有说明，这些术语应当按照其普通和通常的含义理解。
本公开中说明书和权利要求书及上述附图中的术语“第一”、“第二”等 是用于区别类似或同类的对象或实体，而不必然意味着限定特定的顺序或先后次序，除非另外注明。应该理解这样使用的用语在适当情况下可以互换，例如能够根据本公开实施例图示或描述中给出那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖但不排他的包含，例如，包含了一系列组件的产品或设备不必限于清楚地列出的那些组件，而是可包括没有清楚地列出的或对于这些产品或设备固有的其它组件。
本公开实施例中使用的术语“模块”，是指任何已知或后来开发的硬件、软件、固件、人工智能、模糊逻辑或硬件或/和软件代码的组合，能够执行与该元件相关的功能。
在半导体技术领域中，在进行基于标准单元库的ASIC设计流程中，芯片设计者采用硬件描述语言设计芯片，即对芯片功能进行建模，然后运用自动化设计软件将设计代码综合成标准单元电路，进而通过物理后端设计将标准单元电路转换成对应制程工艺下可制造的图形数据流文件(Graphic Data Stream，简称GDS)版图，最后由代工厂生产芯片。
其中，在进行基于标准单元库的ASIC设计时，代工厂通常会预先提供工艺设计工具包(Process Design Kit，简称PDK)，其会包含一些时序逻辑元件的设计和特性参数(如建立时间或保持时间等)。
可选的，上述时序逻辑元件可以为锁存器(Latch)、触发器(Flip Flop，简称FF)等。
其中，锁存器是一种对脉冲电平敏感的存储单元电路，它们可以在特定输入脉冲电平作用下改变状态。锁存，就是把信号暂存以维持某种电平状态，在数字电路中则可以记录二进制数字信号“0”和“1”。
触发器也叫双稳态门，是一种具有两种稳态的用于储存的组件，可记录二进制数字信号“1”和“0”，其输出由输入时钟所规定的时刻的数据输入确定。
时序逻辑元件的建立时间(Setup Time)是指在时钟有效沿之前，数据输入端信号必须保持稳定的最短时间；保持时间(Hold time)是指在时钟有效沿之后，数据输入端信号必须保持稳定的最短时间。
可以理解的是，在理想情况下，只要在时钟有效沿来临时，有效数据 也来临(时钟有效沿之前或同时)，则时序逻辑元件便能够正确采集到数据；而在时钟有效沿之后(或同时)，即使数据发生变化，也不会影响时序逻辑元件的输出了。
然而，在实际情况中，时钟沿打开开关需要时间，逻辑门的状态改变(电容充放电等)也都需要时间，因此数据的采集是需要一定时间的，在这个时间内数据不能发生变化，即在时钟有效沿来临之前，数据必须提前一个最小时间量“预先准备好”，这个最小时间量就是上述建立时间。另外，时钟沿关闭开关也需要时间，如果在这个时间段内数据有变化的话，那么新数据就有可能被传递到下一级，进而发生错误，所以数据必须保持一定时间不变，即在时钟有效沿来临之后，数据必须保持一个最小时间量“不能变化”，这个最小时间量就是上述保持时间。
为了更好的理解本公开实施例，参照图1，图1为本公开实施例中时序逻辑元件的建立时间与保持时间示意图。
在图1中，在时钟信号CK的上升沿来之前，数据信号D须提前一个最小时间量“预先准备好”，且不能变化，这个最小时间量就是建立时间；另外，在时钟信号CK的上升沿来之后，数据D仍旧须保持一个最小时间量不能变化，这个最小时间量就是保持时间。
目前，在全定制集成电路设计过程中，时序逻辑元件的特性参数的检查却比较困难，需要依靠人工检查，费时费力，影响集成电路的设计效率。
面对上述技术问题，本公开实施例提供了一种时序逻辑元件性能检查方法，在对待仿真电路进行检查时，获取待仿真电路中各个时序逻辑元件对应的性能检查文件，然后基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果；其中，上述性能检查文件可以在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信息，相较于人工检查的方式，不仅省时省力，而且准确性更高，从而能够有效提升集成电路的设计效率。具体实施方式请参见以下实施例中的内容。
参照图2，图2为本公开实施例中提供的一种时序逻辑元件性能检查方法的步骤流程示意图。在本公开一些实施例中，上述时序逻辑元件性能 检查方法可以应用于待仿真电路，该待仿真电路中包括多个时序逻辑元件，上述时序逻辑元件性能检查方法包括：
S201、获取各个时序逻辑元件对应的性能检查文件。
在一些实施方式中，可以预先建立测试平台，并在该测试平台中采用软件模拟出待仿真电路，该待仿真电路中包括至少一个时序逻辑元件。
其中，上述时序逻辑元件可以根据时钟信号对输入数据信号进行采样。
可选的，上述时序逻辑元件可以为锁存器、触发器等，本公开实施例不做限制。
在一些实施方式中，可以预先配置各个时序逻辑元件对应的性能检查文件，该性能检查文件可以在仿真过程中监控各个时序逻辑元件的输出信号，并判断各个时序逻辑元件的输出信号是否符合输出预期。
S202、基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果；其中，性能检查文件用于在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信息。
其中，上述仿真波形包括时钟信号与输入数据信号。
在一些实施方式中，可以预先选取多种不同的时钟信号与输入数据信号，并采用特定的仿真工具，基于上述各个时序逻辑元件对应的性能检查文件，对待仿真电路进行多次仿真。
其中，不同的仿真波形对应的时钟信号和/或输入数据信号不同。
其中，上述待仿真电路在仿真过程中，各个时序逻辑元件可以根据时钟信号对输入数据信号进行采样。
为了更好的理解本公开实施例，假设各个时序逻辑元件的目标特性参数为建立时间(Setup Time)，该建立时间为时钟信号的目标沿与上述输入数据信号中目标采样值的目标沿之间的时间差。
可以理解的是，当时序逻辑元件的建立时间小于其对应的通用建立时间时，时序逻辑元件可能会因为无法采集到目标采样值而输出上述目标采样值的反向值，或者以较高的延迟输出上述目标采样值。
在本公开一些实施例中，可以监测时序逻辑元件的输出数据，或者时 序逻辑元件的输出延时，然后与时序逻辑元件对应的性能检查文件中设定的输出数据或输出延时阈值进行比较，如果时序逻辑元件的输出数据与时序逻辑元件对应的性能检查文件中设定的输出数据不一致，或者时序逻辑元件的输出延时大于时序逻辑元件对应的性能检查文件中设定的输出延时阈值，则可以认为时序逻辑元件的建立时间不满足上述预设条件。
在一些实施方式中，上述待仿真电路在仿真过程中，任意时序逻辑元件在检查出其对应的时序逻辑元件的目标特性参数不满足预设条件时，则将其对应的时序逻辑元件的标识信息输出至仿真结果中，以供设计工程师查看，或进行一步筛查。
本公开实施例提供的时序逻辑元件性能检查方法，在对待仿真电路进行检查时，获取待仿真电路中各个时序逻辑元件对应的性能检查文件，然后基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果；其中，上述性能检查文件可以在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信息，相较于人工检查的方式，不仅省时省力，而且准确性更高，从而能够有效提升集成电路的设计效率。
基于上述实施例中描述的内容，参照图3，图3为本公开实施例中提供的另一种时序逻辑元件性能检查方法的步骤流程示意图。在本公开一些实施例中，上述时序逻辑元件性能检查方法包括：
步骤S301、根据待仿真电路的设计数据库，生成待仿真电路对应的网表。
在本公开一些实施例中，以芯片设计流程为例，芯片设计阶段会明确芯片的用途、规格和性能表现，芯片设计可分为功能定义、***级设计、前端设计和后端设计等过程。
其中，功能定义描述了对芯片功能和性能参数的要求。***设计是指基于前期的功能定义，明确芯片架构、业务模块、供电等***级设计。前端设计时，设计人员根据***设计确定的方案，针对各模块开展具体的电路设计，使用专门的硬件描述语言，对具体的电路实现进行寄存器传输级(register transfer level，RTL)级别的代码描述，生成电脑能理解的代码。代 码生成后，就需要严格按照已制定的规格标准，通过仿真验证来反复检验代码设计的正确性。之后，用逻辑综合工具，把用硬件描述语言写成的RTL级的代码转成门级网表，以确保电路在面积、时序等目标参数上达到标准。逻辑综合完成后需要进行静态时序分析，套用特定的时序模型，针对特定电路分析其是否违反设计者给定的时序限制。整个设计流程是一个迭代的流程，任何一步不能满足要求都需要重复之前的步骤，甚至重新设计RTL代码。后端设计则是先基于网表，在给定大小的硅片面积内，对电路进行布局和绕线，再对布线的物理版图进行功能和时序上的各种验证，后端设计也是一个迭代的流程，验证不满足要求则需要重复之前的步骤，最终生成用于芯片生产的图形数据流(Graphic Data Stream，GDS)文件。
在本公开一些实施例中，可以基于待仿真电路的设计数据库，生成待仿真电路对应的网表，该网表中包括待仿真电路的电路描述语句，如电路的连接方式、构成电路的元件、器件、电源节点等的属性、参数、标识信息等。
步骤S302、根据预设关键词，在待仿真电路对应的网表中查找出各个时序逻辑元件。
在本公开一些实施例中，可以预先确定待仿真电路中各个时序逻辑元件对应的标识信息的关键词，例如，待仿真电路中所有锁存器对应的标识信息中通常含有关键词“Latch”，则通过关键词“Latch”可以在待仿真电路对应的网表中查找出所有的锁存器；同理，待仿真电路中所有触发器对应的标识信息中通常含有关键词“FF”，则通过关键词“FF”可以在待仿真电路对应的网表中查找出所有的触发器。
步骤S303、配置各个时序逻辑元件对应的性能检查文件。
在一些实施方式中，可以基于chktiming语句，配置各个时序逻辑元件对应的性能检查文件。
可选的，上述性能检查文件中可以设定时序逻辑元件理想的输出数据、输出延时等。
其中，上述性能检查文件可以被本公开实施例中采用的仿真工具识别。可选的，上述仿真工具可以为finesim仿真器。
本公开实施例中，通过配置各个时序逻辑元件对应的性能检查文件， 可以实现时序逻辑元件性能参数的自动检查，相较于人工检查的方式，不仅省时省力，而且准确性更高。
步骤S304、基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果。
其中，上述性能检查文件用于在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信息。
在一些实施方式中，可以预先选取合理的时钟信号与输入数据信号，然后基于上述各个时序逻辑元件对应的性能检查文件，对待仿真电路进行仿真。
其中，上述待仿真电路在仿真过程中，各个时序逻辑元件可以根据时钟信号对输入数据信号进行采样。
为了更好的理解本公开实施例，以目标特性参数为建立时间(Setup Time)为例，在本公开一些实施例中，上述性能检查文件可以监测时序逻辑元件的输出数据，或者时序逻辑元件的输出延时，然后与其设定的输出数据或输出延时阈值进行比较，如果时序逻辑元件的输出数据与时序逻辑元件对应的性能检查文件中设定的输出数据不一致，或者时序逻辑元件的输出延时大于时序逻辑元件对应的性能检查文件中设定的输出延时阈值，则可以确定时序逻辑元件的建立时间不满足上述预设条件。
其中，任意时序逻辑元件在检查出其对应的时序逻辑元件的目标特性参数不满足预设条件时，则将其对应的时序逻辑元件的标识信息输出至仿真结果中，以供设计工程师查看。
在一些实施例中，可以将仿真结果中输出的目标时序逻辑元件确定为是潜在的会存在时序错误的时序逻辑元件，如建立时间或保持时间不足的时序逻辑元件。
例如，当时序逻辑元件的建立时间较充足时，在时钟信号的有效沿到达时，数据信号也比较稳定，因此时序逻辑元件的时钟到输出延时也会比较小，且大小比较稳定；当时序逻辑元件的建立时间不够充足时，在时钟信号的有效沿到达时，数据信号可能并不处于稳定状态，因此时序逻辑元件的时钟到输出延时也会增大，且建立时间越不充足，时序逻辑元件的时 钟到输出延时越大；当时序逻辑元件的建立时间减小到无法在时钟信号的有效沿到达时采集到目标采样值，则时序逻辑元件会输出目标采样值失败，此时，时序逻辑元件的时钟到输出延时为零。
步骤S305、确定仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及最小目标特性参数对应的目标仿真波形。
在一些实施例中，同一路径是指例化的一个触发器或锁存器的层次。
步骤S306、根据上述目标仿真波形，确定上述属于同一路径下的目标时序逻辑元件是否存在时序错误。若是，则在待仿真电路的设计数据库中调整上述属于同一路径下的目标时序逻辑元件的输入信号；若否，则结束流程。
示例性的，以目标特性参数为建立时间为例，当采用多种仿真波形分别对待仿真电路进行仿真后，仿真结果中输出的目标时序逻辑元件对应建立时间的大小会存在差异，由于建立时间越小，时序逻辑元件出现时序错误的概率就越大，因此，为了提升检查效率，可以选取仿真结果中同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及最小目标特性参数对应的仿真波形，来分析上述同一路径下的目标时序逻辑元件是否存在时序错误。
在一些实施方式中，当确定上述属于同一路径下的目标时序逻辑元件存在时序错误时，可以在待仿真电路的设计数据库中调整上述属于同一路径下的目标时序逻辑元件对应的时钟信号和/或数据输入信号。
在一种可行的实施方式中，可以提前上述输入数据信号，和/或者延迟时钟信号。
本公开实施例提供的时序逻辑元件性能检查方法，在得到仿真结果后，确定仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及该最小目标特性参数对应的仿真波形，根据仿真波形，确定上述属于同一路径下的目标时序逻辑元件是否存在时序错误，由此可以有效提升时序逻辑元件的检查效率。
基于上述实施例中描述的内容，参照图4，图4为本公开实施例中提供的又一种时序逻辑元件性能检查方法的步骤流程示意图。在本公开一些实施例中，上述时序逻辑元件性能检查方法包括：
一、获取待仿真电路的设计数据库。
二、根据上述设计数据库，生成网表。
三、根据上述网表生成时序逻辑元件对应的性能检查文件。
在一些实施方式中，可以根据预设关键词，在上述网表中查找出各个时序逻辑元件，并配置各个时序逻辑元件对应的性能检查文件。
四、对待仿真电路进行仿真。
在一些实施方式中，可以基于上述网表，以及各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果。
其中，上述性能检查文件可以在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足上述预设条件的目标标识信息。
五、处理仿真结果。
在一些实施方式中，确定仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及最小目标特性参数对应的仿真波形。
六、检查仿真结果。
在一些实施方式中，根据上述目标仿真波形，确定上述属于同一路径下的目标时序逻辑元件是否存在时序错误。
当确定上述属于同一路径下的目标时序逻辑元件存在时序错误时，调整设计数据库中上述属于同一路径下的目标时序逻辑元件的输入信号；当确定上述属于同一路径下的目标时序逻辑元件不存在时序错误时，结束检查流程。
本公开实施例提供的时序逻辑元件性能检查方法，可以快速查找出待仿真电路中存在时序错误的时序逻辑元件，相较于人工检查的方式，不仅省时省力，而且准确性更高，从而能够有效提升集成电路的设计效率。
基于上述实施例中所描述的内容，本公开实施例中还提供一种时序逻辑元件性能检查装置，应用于待仿真电路，该待仿真电路中包括多个时序逻辑元件。
参照图5，图5为本公开实施例中提供的一种时序逻辑元件性能检查装置的程序模块示意图，该时序逻辑元件性能检查装置包括：
获取模块501，用于获取各个时序逻辑元件对应的性能检查文件。
仿真模块502，用于基于各个所述时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对所述待仿真电路进行仿真，得到仿真结果；其中，所述性能检查文件用于在仿真过程中检查各个所述时序逻辑元件的目标特性参数是否满足预设条件，并在所述仿真结果中输出目标特性参数不满足所述预设条件的目标时序逻辑元件的标识信息。
在一些实施例中，上述装置还包括配置模块，用于：
根据所述待仿真电路的设计数据库，生成所述待仿真电路对应的网表；
根据预设关键词，在所述待仿真电路对应的网表中查找出各个所述时序逻辑元件；
配置各个所述时序逻辑元件对应的性能检查文件。
在一些实施例中，上述装置还包括处理模块，用于：
确定所述仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及所述最小目标特性参数对应的目标仿真波形；
根据所述目标仿真波形，确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误。
在一些实施例中，上述装置还包括调整模块，用于：
当确定所述属于同一路径下的目标时序逻辑元件存在时序错误时，调整所述属于同一路径下的目标时序逻辑元件的输入信号。
在一些实施例中，上述调整模块具体用于：
调整所述属于同一路径下的目标时序逻辑元件对应的时钟信号和/或数据输入信号。
需要说明的是，本公开实施例中的获取模块501及仿真模块502具体执行的内容可以参阅图2至图4所示实施例中相关内容，此处不做赘述。
本公开实施例提供的时序逻辑元件性能检查装置，在对待仿真电路进行检查时，获取待仿真电路中各个时序逻辑元件对应的性能检查文件，然后基于各个时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对待仿真电路进行仿真，得到仿真结果；其中，上述性能检查文件可以在仿真过程中检查各个时序逻辑元件的目标特性参数是否满足预设条件，并在仿真结果中输出目标特性参数不满足预设条件的目标时序逻辑元件的标识信 息，相较于人工检查的方式，不仅省时省力，而且准确性更高，从而能够有效提升集成电路的设计效率。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种电子设备，该电子设备包括至少一个处理器和存储器；其中，存储器存储计算机执行指令；上述至少一个处理器执行存储器存储的计算机执行指令，以实现如上述实施例中描述的时序逻辑元件性能检查方法中的各个步骤，本实施例此处不再赘述。
为了更好的理解本公开实施例，参照图6，图6为本公开实施例提供的一种电子设备的硬件结构示意图。
如图6所示，本实施例的电子设备60包括：处理器601以及存储器602；其中：
存储器602，用于存储计算机执行指令；
处理器601，用于执行存储器存储的计算机执行指令，以实现上述实施例中描述的时序逻辑元件性能检查方法中的各个步骤，具体可以参见前述方法实施例中的相关描述。
可选地，存储器602既可以是独立的，也可以跟处理器601集成在一起。
当存储器502独立设置时，该设备还包括总线603，用于连接存储器602和处理器601。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行计算机执行指令时，以实现如上述实施例中描述的时序逻辑元件性能检查方法中的各个步骤，本实施例此处不再赘述。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种计算机程序产品，该计算机程序产品中存储有计算机执行指令，当处理器执行计算机执行指令时，以实现如上述实施例中描述的时序逻辑元件性能检查方法中的各个步骤，本实施例此处不再赘述。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，上述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以 有另外的划分方式，例如多个模块可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
上述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述模块集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种时序逻辑元件性能检查方法，应用于待仿真电路，所述待仿真电路中包括多个时序逻辑元件，所述方法包括：
    获取各个所述时序逻辑元件对应的性能检查文件；
    基于各个所述时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对所述待仿真电路进行仿真，得到仿真结果；其中，所述性能检查文件用于在仿真过程中检查各个所述时序逻辑元件的目标特性参数是否满足预设条件，并在所述仿真结果中输出目标特性参数不满足所述预设条件的目标时序逻辑元件的标识信息。
  2. 根据权利要求1所述的方法，其中，所述获取各个所述时序逻辑元件对应的性能检查文件之前，还包括：
    根据所述待仿真电路的设计数据库，生成所述待仿真电路对应的网表；
    根据预设关键词，在所述待仿真电路对应的网表中查找出各个所述时序逻辑元件；
    配置各个所述时序逻辑元件对应的性能检查文件。
  3. 根据权利要求1所述的方法，其中，所述得到仿真结果之后，还包括：
    确定所述仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及所述最小目标特性参数对应的目标仿真波形；
    根据所述目标仿真波形，确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误。
  4. 根据权利要求3所述的方法，其中，所述确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误之后，还包括：
    当确定所述属于同一路径下的目标时序逻辑元件存在时序错误时，调整所述属于同一路径下的目标时序逻辑元件的输入信号。
  5. 根据权利要求1至4任一项所述的方法，其中，
    所述时序逻辑元件包括触发器和/或锁存器；
    所述目标特性参数包括建立时间和/或保持时间。
  6. 根据权利要求5所述的方法，其中，所述调整所述属于同一路径下的目标时序逻辑元件的输入信号，包括：
    调整所述属于同一路径下的目标时序逻辑元件对应的时钟信号和/或数据输入信号。
  7. 一种时序逻辑元件性能检查装置，应用于待仿真电路，所述待仿真电路中包括多个时序逻辑元件，所述装置包括：
    获取模块，用于获取各个所述时序逻辑元件对应的性能检查文件；
    仿真模块，用于基于各个所述时序逻辑元件对应的性能检查文件，采用多种仿真波形分别对所述待仿真电路进行仿真，得到仿真结果；其中，所述性能检查文件用于在仿真过程中检查各个所述时序逻辑元件的目标特性参数是否满足预设条件，并在所述仿真结果中输出目标特性参数不满足所述预设条件的目标时序逻辑元件的标识信息。
  8. 根据权利要求7所述的装置，其中，还包括配置模块，用于：
    根据所述待仿真电路的设计数据库，生成所述待仿真电路对应的网表；
    根据预设关键词，在所述待仿真电路对应的网表中查找出各个所述时序逻辑元件；
    配置各个所述时序逻辑元件对应的性能检查文件。
  9. 根据权利要求7所述的装置，其中，还包括处理模块，用于：
    确定所述仿真结果中属于同一路径下的目标时序逻辑元件对应的最小目标特性参数，以及所述最小目标特性参数对应的目标仿真波形；
    根据所述目标仿真波形，确定所述属于同一路径下的目标时序逻辑元件是否存在时序错误。
  10. 根据权利要求9所述的装置，其中，还包括调整模块，用于：
    当确定所述属于同一路径下的目标时序逻辑元件存在时序错误时，调整所述属于同一路径下的目标时序逻辑元件的输入信号。
  11. 根据权利要求7至10任一项所述的装置，其中，
    所述时序逻辑元件包括触发器和/或锁存器；
    所述目标特性参数包括建立时间和/或保持时间。
  12. 根据权利要求11所述的装置，其中，所述调整模块具体用于：
    调整所述属于同一路径下的目标时序逻辑元件对应的时钟信号和/或数据输入信号。
  13. 一种电子设备，包括：至少一个处理器和存储器；
    所述存储器存储计算机执行指令；
    所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如权利要求1至6任一项所述的时序逻辑元件性能检查方法。
  14. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如权利要求1至6任一项所述的时序逻辑元件性能检查方法。
  15. 一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时，实现权利要求1至6任一项所述的时序逻辑元件性能检查方法。
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