WO2023245509A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2023245509A1
WO2023245509A1 PCT/CN2022/100511 CN2022100511W WO2023245509A1 WO 2023245509 A1 WO2023245509 A1 WO 2023245509A1 CN 2022100511 W CN2022100511 W CN 2022100511W WO 2023245509 A1 WO2023245509 A1 WO 2023245509A1
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WIPO (PCT)
Prior art keywords
substrate
via hole
display
layer
light
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PCT/CN2022/100511
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English (en)
French (fr)
Inventor
王利忠
宁策
王东方
郭晖
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/100511 priority Critical patent/WO2023245509A1/zh
Priority to CN202280001850.6A priority patent/CN117730276A/zh
Publication of WO2023245509A1 publication Critical patent/WO2023245509A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • Liquid crystal display (Liquid Crystal Display, LCD) has the advantages of light weight, low power consumption, high image quality, low radiation and easy portability. It has gradually replaced the traditional cathode ray tube display (CRT). It is widely used in modern information equipment, such as virtual reality (VR) head-mounted display devices, laptops, TVs, mobile phones and digital products.
  • VR virtual reality
  • embodiments of the present disclosure provide a display substrate, including:
  • a plurality of gate lines and a plurality of data lines are provided on one side of the first substrate, the plurality of gate lines and the plurality of data lines are arranged to cross each other and are insulated from each other;
  • a flat layer disposed on the side of the gate line and the data line away from the first base substrate, and including a first via hole;
  • a support structure is provided on a side of the flat layer away from the first base substrate and filled into the first via hole. In a direction perpendicular to the first base substrate, the support structure The height is greater than the depth of the first via hole.
  • the surface of the support structure on the side away from the first substrate substrate is a first surface
  • the first surface is a curved surface structure
  • the The vertical height difference range between the maximum distance and the minimum distance between the first surface and the first substrate is a, 0 ⁇
  • the orthographic projection of the plurality of gate lines on the first substrate is the same as the orthographic projection of the plurality of data lines on the first substrate.
  • the orthographic projection on the substrate has a plurality of overlapping areas, and at least a part of the overlapping areas are located within the orthographic projection of the first via hole on the first substrate substrate.
  • the above display substrate provided by the embodiment of the present disclosure further includes a first light-shielding structure located between the layer where the gate line is located and the first substrate substrate, and the first light-shielding structure is between The orthographic projection on the first substrate substrate at least covers the orthographic projection of the first via hole outside the overlapping area on the first substrate substrate.
  • the above display substrate provided by the embodiment of the present disclosure also includes a first electrode located between the flat layer and the layer where the support structure is located, and is located between the flat layer and the data line. Transfer electrodes between layers, and a filling structure provided on the same layer as the support structure;
  • the flat layer further includes a second via hole, the first electrode is connected to the transfer electrode through the second via hole, and the filling structure fills the second via hole.
  • the maximum radial size of the support structure in a cross section perpendicular to the first substrate substrate, is equal to the maximum radial size of the filling structure.
  • the difference is greater than or equal to 0 ⁇ m and less than or equal to 5 ⁇ m.
  • the maximum radial size of the first via hole in a cross-section perpendicular to the first substrate substrate, is equal to the maximum radial size of the second via hole.
  • the difference in maximum radial dimensions is greater than or equal to 2 ⁇ m and less than or equal to 9 ⁇ m.
  • the depth of the first via hole is greater than the depth of the second via hole in a direction perpendicular to the first substrate substrate.
  • the shortest distance S between the first via hole and the second via hole in a cross section perpendicular to the first substrate substrate 1 is greater than or equal to 2 ⁇ m and less than or equal to 5 ⁇ m, and the longest distance between the first via hole and the second via hole is equal to (S 1 +h 1 *cot ⁇ +h 2 *cot ⁇ ), where h 1 is the The depth of the first via hole in the direction perpendicular to the first substrate substrate, ⁇ is the slope angle of the flat layer at the first via hole, h 2 is the vertical angle of the second via hole The depth in the direction of the first base substrate, ⁇ , is the slope angle of the flat layer at the second via hole.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a transistor located between the layer where the transfer electrode is located and the first substrate substrate, the transistor includes a gate, and the An orthographic projection of at least part of the second via hole on the first substrate is located within an orthographic projection of the gate on the first substrate.
  • the above display substrate provided by the embodiment of the present disclosure further includes a second light-shielding structure located between the layer where the gate electrode is located and the first substrate substrate;
  • the transistor includes an active layer located between the layer where the gate electrode is located and the layer where the second light-shielding structure is located.
  • the active layer includes a channel region, and the channel region is located on the first substrate.
  • the orthographic projection on the second light-shielding structure is located within the orthographic projection of the second light-shielding structure on the first base substrate.
  • the first light-shielding structure and the second light-shielding structure are arranged on the same layer, and the first light-shielding structure and the second light-shielding structure are mutually exclusive. Independent, or one first light-shielding structure and an adjacent second light-shielding structure are integrated structures.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a connection structure provided on the same layer as the support structure and the filling structure, and the connection structure is located between the support structure and the filling structure. between structures and integrated with the support structure and the filling structure;
  • the distance from the surface of the connection structure away from the first base substrate to the first base substrate is greater than the distance from the surface of the support structure or the filling structure away from the first base substrate. distance between the first substrate and the substrate.
  • the above display substrate provided by the embodiment of the present disclosure further includes a second electrode located on a side of the layer where the first electrode is located away from the flat layer.
  • an embodiment of the present disclosure provides a display panel, including: an opposite display substrate and a counter substrate, wherein the display substrate is the above-mentioned display substrate provided by the embodiment of the present disclosure, and the counter substrate It includes a second base substrate and a spacer located on the side of the second base substrate facing the display substrate. The end of the spacer facing the display substrate is provided on the support structure. inside the depression.
  • an embodiment of the present disclosure provides a display device, including the above display panel provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • Figure 3 is an electron microscope view of the support structure provided by an embodiment of the present disclosure.
  • Figure 4 is another electron microscope view of the support structure provided by an embodiment of the present disclosure.
  • Figure 5 is an electron microscope image of the flat layer provided by an embodiment of the present disclosure.
  • Figure 6 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 7 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 8 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 9 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 10 is an electron microscope image of a spacer provided by an embodiment of the present disclosure.
  • the related liquid crystal display panel includes an opposite display substrate and a counter substrate, wherein the side of the counter substrate facing the display substrate is provided with a spacer, and the side of the display substrate facing the counter substrate is provided with a spacer for supporting the spacer. supporting structure. Since the spacer occupies part of the space used for disposing the liquid crystal layer between the display substrate and the counter substrate, there is no liquid crystal layer at the location of the spacer. Therefore, the location of the spacer will not be driven by the electric field to achieve the light transmission effect. or shading effect. In order to prevent the spacers from affecting the display, it is usually necessary to use a black matrix to block the spacers, thus reducing the pixel aperture ratio.
  • the impact of spacers on the pixel aperture ratio is gradually increasing.
  • the size of the spacers is gradually reduced, and the corresponding support structure is also gradually reduced.
  • the contact surface between the support structure and the spacer is flat, so the smaller spacer can easily slide out of the support structure and scratch the orientation layer (PI) near the support structure, causing light leakage.
  • a display substrate as shown in Figures 1 to 6, including:
  • a plurality of gate lines 101 and a plurality of data lines 102 are provided on one side of the first substrate 100.
  • the plurality of gate lines 101 and the plurality of data lines 102 are arranged to cross each other and are insulated from each other;
  • the flat layer 103 is provided on the side of the gate line 101 and the data line 102 away from the first base substrate 100, and includes the first via V 1 ;
  • the support structure 104 is provided on the side of the flat layer 103 away from the first base substrate 100 and filled into the first via hole V 1 , so that the surface of the support structure 104 away from the first base substrate 100 has a recessed portion C, And in the direction Z perpendicular to the first substrate 100, the height H of the support structure 104 is greater than the depth h 1 of the first via V 1 , and the recessed portion C can limit the sliding of the spacer 201; optionally, to ensure The support structure 104 has good stability and is not easy to fall or fall off, so that it can better support the spacer 201.
  • the support structure 104 can have a structure that is narrow at the top and wide at the bottom.
  • the slope angle ⁇ of the support structure 104 is It can be an acute angle greater than or equal to 40°, or, as shown in Figure 4, the support structure 104 is a structure with the same width up and down, and the slope angle ⁇ of the support structure 104 is 90°, which is equivalent to the support structure 104 being perpendicular to the first substrate.
  • the height H of the support structure 104 may be greater than or equal to 0.5 ⁇ m and less than or equal to 3 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, etc.
  • the surface of the support structure 104 away from the first base substrate 100 has a recessed portion C. , thereby limiting the sliding of the spacer 201 through the recessed portion C, ensuring that the end of the spacer 201 facing the display substrate 001 is limited in the recessed portion C, and solving the light leakage problem caused by the spacer 201 sliding out of the support structure 104 .
  • the flat layer 103 itself has a second via V 2 for connecting the first electrode 105 and the transfer electrode 106 , and the first via V 1 of the present disclosure can be It is formed using the same patterning process as the second via hole V 2 , so the process flow can be simplified and the production cost can be reduced.
  • the surface of the support structure 104 away from the first base substrate 100 can also be separately processed to form the recessed portion C, which is not limited here.
  • the thickness of the flat layer 103 is greater than or equal to 1 ⁇ m and less than or equal to 2 ⁇ m (such as 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, etc.), and the flat layer 103 has a slope angle ⁇ of the first via hole V 1 and a slope angle ⁇ of the second via hole V 2
  • the angle ⁇ may be greater than or equal to 60° and less than or equal to 80°, such as 60°, 65°, 70°, 75°, 80°, etc.
  • the surface of the support structure 104 away from the first substrate substrate 100 is the first surface, and the first surface is a curved surface structure
  • the vertical height difference range between the maximum distance and the minimum distance between the first surface and the first base substrate 100 is a, 0 ⁇
  • the first surface of the support structure 104 is set into a curved structure and the value of a is controlled to be within 1 ⁇ m, which can not only achieve a small occupied area of the first via V1 , but also ensure that the sliding of the spacer 201 can be restricted.
  • the curved surface structure may be an indented structure formed by the recess C shown in FIG. 2 , so that the end of the spacer 201 facing the display substrate 001 is limited in the recess C.
  • the curved surface structure is a convex structure arched away from the first substrate 100 .
  • the end of the spacer 201 facing the display substrate 001 can be a concave structure adapted to the convex structure, so as to The convex structure of the support structure 104 is limited in the recessed structure of the spacer 201 to effectively support and limit the spacer 201.
  • the orthographic projection of the plurality of gate lines 101 on the first substrate substrate 100 and the plurality of data lines 102 are on
  • the orthographic projection on the first substrate substrate 100 has a plurality of overlapping areas O, and at least a part of the overlapping areas O are located within the orthographic projection of the first via hole V 1 on the first substrate substrate 100; exemplarily, FIG. 6 only shows one gate line 101 and one data line 102, as well as an overlapping area O of the two orthographic projections.
  • the first via V 1 is provided at the overlapping area O, so that through the gate line 101 and the data line 102 at the overlapping area O, the first via V 1 can be simultaneously connected in the extending direction of the gate line 101 and the extending direction of the data line 102 .
  • One via V 1 has a light-shielding effect, reducing light leakage and improving product quality.
  • the support structure 104 is embedded in the first via hole V 1 , and the support structure 104 is used to support the spacers 201 . Therefore, the arrangement of the first via holes V 1 can be equivalent to the arrangement of the spacers 201 . cloth method.
  • the first via holes V 1 should be uniformly distributed (equivalent to the uniform distribution of the spacers 201 ), and the number does not need to be specifically limited. For example, the total number of the first via holes V 1 Can be less than the total number of overlapping areas O.
  • the spacers 201 in the related art are arranged in the pixel opening area, resulting in a decrease in the pixel aperture ratio. In the present disclosure, the spacers 201 are arranged in the overlapping area O, which prevents the spacers 201 from occupying the pixel opening area, which can improve Pixel aperture ratio.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may also include a layer located between the gate line 101 (arranged in the same layer as the gate electrode 91 ) and the first substrate.
  • the first light shielding structure 107 between the substrates 100, the orthographic projection of the first light shielding structure 107 on the first substrate substrate 100 at least covers the first via hole V 1 outside the overlapping area O on the first substrate substrate 100 orthographic projection to use the first light-shielding structure 107 to block at least the first via V 1 outside the overlapping area O, so that the first light-shielding structure 107 , the gate line 101 and the data line 102 jointly block the backlight and avoid the first via hole Light leakage at V1 .
  • the orthographic projection of the first light-shielding structure 107 on the first base substrate 100 can be set to cover the orthographic projection of the first via V1 on the first base substrate 100, That is, the orthographic projection area of the first light-shielding structure 107 on the first base substrate 100 is greater than or equal to the orthographic projection area of the first via hole V 1 on the first base substrate 100 .
  • the first via hole V 1 is on the first base substrate 100 .
  • the orthographic projection on the base substrate 100 is located within the orthographic projection of the first light shielding structure 107 on the first base substrate 100 , or the orthographic projection of the first via hole V 1 on the first base substrate 100 is within the same angle as the first light shielding structure 107 .
  • the orthographic projection of the structure 107 on the first base substrate 100 coincides.
  • the orthogonal projection boundary of the first via hole V 1 on the first base substrate 100 is aligned with the first The distance between orthographic projection boundaries of the light-shielding structure 107 on the first base substrate 100 may be greater than or equal to 0 and less than or equal to 5 ⁇ m, such as 0 ⁇ m, 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m. , 4.5 ⁇ m, 5 ⁇ m, etc.
  • the second via hole V 2 in the flat layer 103 for connecting the first electrode 105 and the transfer electrode 106 may be provided.
  • the filling structure 108 and the support structure 104 can be arranged on the same layer, so that the same film layer can be used to form the filling structure 108 and the support structure 104 in one patterning process.
  • the maximum radial dimension d 3 of the support structure 104 may be greater than or equal to the filling structure.
  • the maximum radial dimension d 4 of 108 is to improve the alignment tolerance (margin) of the mask used to make the support structure 104 and the filling structure 108 and the display substrate. It is easy to understand that the larger the support structure 104 is and the larger the first via hole V 1 that accommodates the support structure 104 is, the larger the first light-shielding structure 107 needs to be to block the backlight and avoid the first via hole V 1 from leaking light.
  • the size of the supporting structure 104 can be reasonably increased.
  • the difference between the maximum radial dimension d3 of the supporting structure 104 and the maximum radial dimension d4 of the filling structure 108 can be greater than Equal to 0 ⁇ m and less than or equal to 5 ⁇ m, such as 0 ⁇ m, 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, etc.
  • the maximum radial dimension d 1 of the first via V 1 is equal to
  • the difference between the maximum radial dimensions d 2 of the second via hole V 2 may be greater than or equal to 2 ⁇ m and less than or equal to 9 ⁇ m, for example, it may be 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, or 9 ⁇ m. wait.
  • the depth h 1 of the first via hole V 1 is greater than the depth h 1 of the first via hole V 1 .
  • the depth h 2 of the second via hole V 2 optionally, the difference between the depth h 1 of the first via hole V 1 and the depth h 2 of the second via hole V 2 ( i.e. h 1 -h 2 ) can be equal to the transfer electrode 106 is a thickness in the direction Z perpendicular to the first base substrate 100 .
  • the first via hole V 1 and the second via hole V 2 on a cross-section perpendicular to the first substrate substrate 100 , between the first via hole V 1 and the second via hole V 2
  • the shortest distance S 1 between them is greater than or equal to 1.5 ⁇ m and less than or equal to 5 ⁇ m, such as 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, etc., the first via V 1 and the second via V 2
  • the longest distance S 2 between them is equal to (S 1 +h 1 *cot ⁇ +h 2 *cot ⁇ ), where h 1 is the depth of the first via V 1 in the direction Z perpendicular to the first substrate substrate 101, ⁇ is the slope angle of the flat layer 103 at the first via hole V 1 , h 2 is the depth of the second via hole V 2 in the direction Z perpendicular to the first base substrate 101 ,
  • a first via V 1 and a second via V 2 can be set simultaneously within a sub-pixel size (Pitch) range, and in a high-resolution product structure, in order to fully utilize the space of the sub-pixel , the maximum radial dimension d 1 of the first via hole V 1 , the maximum radial dimension d 2 of the second via hole V 2 , and the shortest distance between the first via hole V 1 and the second via hole V 2 can be set.
  • the sum of S 1 (that is, d 1 +d 2 +S 1 ) is equal to the size of the sub-pixel on the line connecting the center of the first via hole V 1 and the center of the second via hole V 2 .
  • the maximum radial size d 1 of the first via hole V 1 and the The sum of the maximum radial dimension d 2 of the two via holes V 2 and the shortest distance S 1 between the first via hole V 1 and the second via hole V 2 may be less than The size of the pixel on the line connecting the center of the first via hole V 1 and the center of the second via hole V 2 .
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may also include a transistor 109 located between the layer where the transfer electrode 106 is located and the first substrate substrate 100,
  • the transistor 109 includes a gate electrode 91, and the orthographic projection of the second via hole V 2 on the first substrate substrate 100 is located within the orthographic projection of the gate electrode 91 on the first substrate substrate 100, so as to block the backlight through the gate electrode 91 to avoid The second via hole V2 leaks light.
  • the orthographic projection of the second via hole V 2 on the first substrate 100 may also intersect with the orthographic projection of the gate 91 on the first substrate 100 .
  • Stack no limitation is made here.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may also include a second light-shielding structure located between the layer where the gate electrode 91 is located and the first base substrate 100 110.
  • the transistor 109 includes an active layer 92 located between the layer where the gate electrode 91 is located and the second light-shielding structure 110.
  • the active layer 92 includes a channel region N, and the orthographic projection of the channel region N on the first substrate 100 It is located within the orthographic projection of the second light-shielding structure 110 on the first base substrate 100 to block the backlight through the second light-shielding structure 110 to prevent the backlight from irradiating the channel region N and affecting the stability of the transistor 109 .
  • the distance between orthographic projection boundaries of N on the first base substrate 100 may be greater than or equal to 0.5 ⁇ m and less than or equal to 5 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m. , 5 ⁇ m, etc.
  • the channel region N can be arranged directly opposite to the gate electrode 91 , that is, the orthogonal projected area of the channel region N on the first substrate substrate 100 is equal to the area of the gate electrode 91 on the first substrate substrate 100 .
  • the orthographic projection area is the same. Therefore, in the extension direction of the data line 102, the orthographic projection boundary of the second light-shielding structure 110 on the first base substrate 100 is between the orthographic projection boundary of the gate 91 on the first base substrate 100.
  • the distance between them can also be greater than or equal to 0.5 ⁇ m and less than or equal to 5 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, etc.
  • the upper and lower portions of the gate line 101 and the channel region N are used as gate electrodes 91 .
  • the second light shielding structure 110 and the first light shielding structure 107 can be in the same layer.
  • the second light-shielding structure 110 and the first light-shielding structure 107 can be independent of each other, or a second light-shielding structure 110 and an adjacent first light-shielding structure 107 can be an integrated structure.
  • an adjacent second light-shielding structure 110 and a first light-shielding structure 107 are located in the same pixel area.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may also include a connection structure 111 provided on the same layer as the support structure 104 and the filling structure 108 .
  • the connection structure 111 is located on the support structure 104 and the filling structure 108, and the connection structure 111 is integrally arranged with the support structure 104 and the filling structure 108, so that the support structure 101, the connection structure 111 and the filling structure 108 form a strip structure.
  • the extension of the strip structure The direction is the same as the extending direction of the gate line 101 .
  • first via V 1 below the support structure 104 and a second via V 1 below the filling structure 108
  • the surfaces of the support structure 104 and the filling structure 108 away from the first base substrate 100 will be affected by the existence of the via holes. And is slightly recessed, so that the distance from the surface of the connection structure 111 away from the first base substrate 100 to the first base substrate 100 is greater than the distance from the surface of the support structure 104 or the filling structure 108 away from the first base substrate 100 . distance of the first base substrate 100 .
  • the surface of the support structure 104 or the filling structure 108 on the side far away from the first base substrate 100 is lower by 0.1 ⁇ m to 0.5 ⁇ m, for example, 0.1 ⁇ m. ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, etc.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may also include a second electrode 112 located on the side of the layer where the first electrode 105 is located away from the flat layer 103.
  • the second electrode 112 The orthographic projection on the first base substrate 100 at least partially overlaps the orthographic projection of the first electrode 105 on the first base substrate 100 .
  • the first electrode 105 is a pixel electrode
  • the second electrode 112 is a common electrode
  • the common electrode may be a slit-shaped electrode.
  • the transfer electrode 106 is electrically connected to the active layer 92 of the transistor 109 .
  • the material of the active layer 92 can be It is a metal oxide, such as indium gallium zinc oxide (IGZO), amorphous or polycrystalline zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), tin zinc oxide (IZTO), Any one or more of gallium zinc tin oxide (IGZTO) and indium gallium oxide (IGO), and in order to improve the transmittance, the material of the transfer electrode 106 can be indium tin oxide (ITO), indium tin oxide (IZO) ) and other transparent conductive oxides.
  • IGZO indium gallium zinc oxide
  • IZO zinc oxide
  • IGO indium gallium oxide
  • IGO indium gallium oxide
  • the material of the transfer electrode 106 can be indium tin oxide (ITO), indium tin oxide (IZO) ) and other transparent conductive oxides.
  • the present disclosure may also include a polysilicon transistor with a top-gate structure, and the first light-shielding structure 107 and the second light-shielding structure 110 may be provided in the same layer as the gate electrode of the polysilicon transistor.
  • the above display substrate provided by the embodiment of the present disclosure may also include a first gate insulating layer 114, a first interlayer dielectric layer 115, a second gate insulating layer 116, The second interlayer dielectric layer 117, the first insulating layer 118, the second insulating layer 119, and so on.
  • Other essential components of the display substrate are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • an embodiment of the present disclosure also provides a display panel, as shown in Figure 1 , including: a display substrate 001 and a counter substrate 002 that are opposite to each other, wherein the display substrate 001 is a display panel provided by an embodiment of the present disclosure.
  • the above-mentioned display substrate 001 and the counter substrate 002 include a second base substrate 200 and a spacer 201 located on the side of the second base substrate 200 facing the display substrate 001.
  • the end of the spacer 201 faces the display substrate 001. Being disposed in the recess C makes it difficult for the spacer 201 to slide out of the support structure 104 due to the restriction of the recess C.
  • the slope angle ⁇ of the spacer 201 is greater than or equal to 40° and less than or equal to 90°, such as 40°, 45°, 50°, 55°, 60°, 65°, 70°. °, 75°, 80°, 85°, 90°, etc.
  • the height of the spacer 201 is greater than or equal to 0.5 ⁇ m and less than or equal to 2 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, etc.
  • the above-mentioned display panel provided by the embodiment of the present disclosure may be a liquid crystal display panel.
  • the liquid crystal display panel may further include a liquid crystal layer between the display substrate 001 and the counter substrate 002 .
  • the first electrode 105 and the second electrode 112 are both disposed on the display substrate 001 as an example.
  • the second electrode 112 may also be disposed on the opposite substrate 002 .
  • an embodiment of the present disclosure also provides a display device, including the above display panel provided by an embodiment of the present disclosure. Since the principle of the display device to solve the problem is similar to the principle of the above-mentioned display panel to solve the problem, the implementation of the display device provided by the embodiment of the present disclosure can be referred to the implementation of the above-mentioned display panel, and the repeated details will not be repeated.
  • the above-mentioned display device provided by the embodiments of the present disclosure may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or a virtual reality device.
  • VR Any product or component with a display function such as a head-mounted display device.
  • the display device includes but is not limited to: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply and other components.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above display device provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.

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Abstract

一种显示基板、显示面板及显示装置，包括第一衬底基板（100）；多条栅线（101）和多条数据线（102），设置在第一衬底基板（100）的一侧，多条栅线（101）和多条数据线（102）相互交叉设置且相互绝缘；平坦层（103），设置在栅线（101）和数据线（102）远离第一衬底基板（100）的一侧，且包括第一过孔（V1）；支撑结构（104），设置在平坦层（103）远离第一衬底基板（100）的一侧且填充至第一过孔（V1）中，在垂直于第一衬底基板（100）的方向上，支撑结构（104）的高度大于第一过孔（V1）的深度。

Description

显示基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有重量轻、耗电少、画质高、辐射低和携带方便等优点，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，而被广泛应用于现代化信息设备，如虚拟现实(VR)头戴式显示设备、笔记本电脑、电视、移动电话和数字产品等。
发明内容
本公开实施例提供的显示基板、显示面板及显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
第一衬底基板；
多条栅线和多条数据线，设置在所述第一衬底基板的一侧，所述多条栅线和所述多条数据线相互交叉设置且相互绝缘；
平坦层，设置在所述栅线和所述数据线远离所述第一衬底基板的一侧，且包括第一过孔；
支撑结构，设置在所述平坦层远离所述第一衬底基板的一侧且填充至所述第一过孔中，在垂直于所述第一衬底基板的方向上，所述支撑结构的高度大于所述第一过孔的深度。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述支撑结构远离所述第一衬底基板一侧的表面为第一表面，所述第一表面为曲面结构，所述第一表面到所述第一衬底基板之间的最大距离与最小距离之间的垂直高 度差值范围为a，0＜|a|≤1μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多条栅线在所述第一衬底基板上的正投影与所述多条数据线在所述第一衬底基板上的正投影具有多个交叠区，至少部分数量的所述交叠区位于所述第一过孔在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述栅线所在层与所述第一衬底基板之间的第一遮光结构，所述第一遮光结构在所述第一衬底基板上的正投影至少覆盖所述交叠区之外的所述第一过孔在所述第一衬底基板上的正投影。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述平坦层与所述支撑结构所在层之间的第一电极，位于所述平坦层与所述数据线所在层之间的转接电极，以及与所述支撑结构同层设置的填充结构；
所述平坦层还包括第二过孔，所述第一电极通过所述第二过孔与所述转接电极连接，所述填充结构填充所述第二过孔。
在一些实施例中，在本公开实施例提供的上述显示基板中，在垂直所述第一衬底基板的截面上，所述支撑结构的最大径向尺寸与所述填充结构的最大径向尺寸之差大于等于0μm且小于等于5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，在垂直所述第一衬底基板的截面上，所述第一过孔的最大径向尺寸与所述第二过孔的最大径向尺寸之差大于等于2μm且小于等于9μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，在垂直于所述第一衬底基板的方向上，所述第一过孔的深度大于所述第二过孔的深度。
在一些实施例中，在本公开实施例提供的上述显示基板中，在垂直所述第一衬底基板的截面上，所述第一过孔与所述第二过孔之间的最短距离S 1大于等于2μm且小于等于5μm，所述第一过孔与所述第二过孔之间的最长距离等于(S 1+h 1*cotβ+h 2*cotγ)，其中，h 1为所述第一过孔在垂直于所述第一衬底基板的方向上的深度，β为所述平坦层在所述第一过孔处的坡度角，h 2为 所述第二过孔在垂直于所述第一衬底基板的方向上的深度，γ为所述平坦层在所述第二过孔处的坡度角。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述转接电极所在层与所述第一衬底基板之间的晶体管，所述晶体管包括栅极，所述第二过孔的至少部分在所述第一衬底基板上的正投影位于所述栅极在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述栅极所在层与所述第一衬底基板之间的第二遮光结构；
所述晶体管包括位于所述栅极所在层与所述第二遮光结构所在层之间的有源层，所述有源层包括沟道区，所述沟道区在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一遮光结构与所述第二遮光结构同层设置，且所述第一遮光结构与所述第二遮光结构相互独立，或者，一个所述第一遮光结构与相邻的一个所述第二遮光结构为一体结构。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括与所述支撑结构、所述填充结构同层设置的连接结构，所述连接结构位于所述支撑结构与所述填充结构之间，并与所述支撑结构、所述填充结构一体设置；
所述连接结构远离所述第一衬底基板一侧的表面到所述第一衬底基板的距离，大于所述支撑结构或所述填充结构远离所述第一衬底基板一侧的表面到所述第一衬底基板的距离。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一电极所在层远离所述平坦层一侧的第二电极。
另一方面，本公开实施例提供了一种显示面板，包括：相对而置的显示基板和对向基板，其中，所述显示基板为本公开实施例提供的上述显示基板，所述对向基板包括第二衬底基板、以及位于所述第二衬底基板面向所述显示基板一侧的隔垫物，所述隔垫物朝向所述显示基板一侧的端部设置在所述支 撑结构的凹陷部内。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。
附图说明
图1为本公开实施例提供的显示面板的结构示意图；
图2为本公开实施例提供的显示基板的一种结构示意图；
图3为本公开实施例提供的支撑结构的一种电镜图；
图4为本公开实施例提供的支撑结构的又一种电镜图；
图5为本公开实施例提供的平坦层的电镜图；
图6为本公开实施例提供的显示基板的又一种结构示意图；
图7为本公开实施例提供的显示基板的又一种结构示意图；
图8为本公开实施例提供的显示基板的又一种结构示意图；
图9为本公开实施例提供的显示基板的又一种结构示意图；
图10为本公开实施例提供的隔垫物的电镜图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意 指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
相关液晶显示面板包括相对而置的显示基板和对向基板，其中，对向基板面向显示基板的一侧设置有隔垫物，显示基板面向对向基板的一侧设置有用于支撑隔垫物的支撑结构。由于隔垫物占用了显示基板与对向基板之间用于设置液晶层的部分空间，相当于隔垫物所在位置没有液晶层，因此隔垫物所在位置不会受电场驱动而实现透光效果或遮光效果。为避免隔垫物影响显示，通常需要采用黑矩阵遮挡隔垫物，由此降低了像素开口率。随着产品分辨率(PPI)的不断提升，隔垫物对像素开口率的影响逐渐提升。为了满足像素开口率的需求，隔垫物的尺寸逐渐减小，对应的支撑结构也逐渐减小。然而支撑结构与隔垫物的接触面为平面，导致较小的隔垫物很容易滑出支撑结构而划伤支撑结构附近的取向层(PI)，造成漏光现象。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图1至图6所示，包括：
第一衬底基板100；
多条栅线101和多条数据线102，设置在第一衬底基板100的一侧，多条栅线101和多条数据线102相互交叉设置且相互绝缘；
平坦层103，设置在栅线101和数据线102远离第一衬底基板100的一侧，且包括第一过孔V 1；
支撑结构104，设置在平坦层103远离第一衬底基板100的一侧且填充至第一过孔V 1中，使得支撑结构104远离第一衬底基板100一侧的表面具有凹陷部C，且在垂直于第一衬底基板100的方向Z上，支撑结构104的高度H大于第一过孔V 1的深度h 1，凹陷部C可限制隔垫物201滑动；可选地，为保证支撑结构104的稳定性较好，不易倾倒或脱落，从而可以更好地支撑隔垫物201，支撑结构104可以具有上窄下宽的结构，如图3所示，支撑结构104 的坡度角α可以为大于等于40°的锐角，或者，如图4所示，支撑结构104为上下宽度一致的结构，支撑结构104的坡度角α为90°，相当于支撑结构104垂直于第一衬底基板100设置；可选地，支撑结构104的高度H可以大于等于0.5μm且小于等于3μm，例如0.5μm、1μm、1.5μm、2μm、2.5μm、3μm等。
在本公开实施例提供的上述显示面板中，通过将支撑结构104填充至平坦层103的第一过孔V 1中，使得支撑结构104远离第一衬底基板100一侧的表面具有凹陷部C，从而可通过凹陷部C限制隔垫物201滑动，保证隔垫物201朝向显示基板001的端部被限定在凹陷部C内，解决隔垫物201滑出支撑结构104而导致的漏光问题。
在一些实施例中，如图2和图5所示，平坦层103本身具有用于连接第一电极105和转接电极106的第二过孔V 2，本公开的第一过孔V 1可与第二过孔V 2采用一道构图工艺形成，因此可简化工艺流程，降低生产成本。当然，在一些实施例中，也可以单独对支撑结构104远离第一衬底基板100一侧的表面进行处理来形成凹陷部C，在此不做限定。可选地，平坦层103厚度大于等于1μm且小于等于2μm(例如1μm、1.5μm、2μm等)，平坦层103在第一过孔V 1的坡度角β、第二过孔V 2处的坡度角γ可以大于等于60°且小于等于80°，例如60°、65°、70°、75°、80°等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，支撑结构104远离第一衬底基板100一侧的表面为第一表面，第一表面为曲面结构，第一表面到第一衬底基板100之间的最大距离与最小距离之间的垂直高度差值范围为a，0＜|a|≤1μm。由于支撑结构104越大，容纳支撑结构104的第一过孔V 1越大，对高分辨率的产品结构的像素开口率造成的牺牲越大，所以第一过孔V 1的尺寸不能太大。本公开中将支撑结构104的第一表面设置成曲面结构且控制a的数值在1μm以内，既可实现第一过孔V 1占用面积小，又可保证能限制住隔垫物201滑动。
可选地，曲面结构可以为图2所示凹陷部C构成的内凹结构，以将隔垫物201朝向显示基板001的端部被限定在凹陷部C内。或者，曲面结构为朝 向远离第一衬底基板100的方向拱起的外凸结构，相应地，隔垫物201朝向显示基板001的端部可以为与外凸结构适配的凹陷结构，以将支撑结构104的外凸结构限定在隔垫物201的凹陷结构内，实现对隔垫物201的有效支撑和限位。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图6所示，多条栅线101在第一衬底基板100上的正投影与多条数据线102在第一衬底基板100上的正投影具有多个交叠区O，至少部分数量的交叠区O位于第一过孔V 1在第一衬底基板100上的正投影内；示例性地，图6仅示出了一条栅线101和一条数据线102，以及二者正投影的一个交叠区O。将第一过孔V 1设置在交叠区O处，使得可以通过交叠区O处的栅线101和数据线102，在栅线101延伸方向上、以及数据线102延伸方向上同时对第一过孔V 1起到遮光效果，减少漏光，提升产品的品质。
需要说明的是，第一过孔V 1内嵌有支撑结构104，而支撑结构104用于支撑隔垫物201，因此第一过孔V 1的排布方式可以相当于隔垫物201的排布方式。为利于维持液晶显示面板的盒厚均一性，第一过孔V 1宜保持均匀分布(相当于隔垫物201均匀分布)，数量可以不做具体限定，例如，第一过孔V 1的总数可以小于交叠区O的总数。此外，相关技术中的隔垫物201设置在像素开口区，造成像素开口率的下降，本公开将隔垫物201设置在交叠区O，避免了隔垫物201占用像素开口区，可提高像素开口率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图7所示，还可以包括位于栅线101(与栅极91同层设置)所在层与第一衬底基板100之间的第一遮光结构107，第一遮光结构107在第一衬底基板100上的正投影至少覆盖交叠区O之外的第一过孔V 1在第一衬底基板100上的正投影，以采用第一遮光结构107至少遮挡交叠区O之外的第一过孔V 1，使得第一遮光结构107、栅线101和数据线102共同遮挡背光，避免第一过孔V 1处漏光。
可选地，为便于制作第一遮光结构107，可设置第一遮光结构107在第一衬底基板100上的正投影覆盖第一过孔V 1在第一衬底基板100上的正投影， 即第一遮光结构107在第一衬底基板100上的正投影面积大于等于第一过孔V 1在第一衬底基板100上的正投影面积，换言之，第一过孔V 1在第一衬底基板100上的正投影位于第一遮光结构107在第一衬底基板100上的正投影内，或者，第一过孔V 1在第一衬底基板100上的正投影与第一遮光结构107在第一衬底基板100上的正投影重合。在一些实施例中，为避免第一遮光结构107过大而对像素开口率造成较大牺牲，可选地，第一过孔V 1在第一衬底基板100上的正投影边界与第一遮光结构107在第一衬底基板100上的正投影边界之间的距离可以大于等于0且小于等于5μm，例如0μm、0.5μm、1μm、1.5μm、2μm、2.5μm、3μm、3.5μm、4μm、4.5μm、5μm等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，平坦层103中用于连接第一电极105与转接电极106的第二过孔V 2处可设置有填充结构108，以提高第二过孔V 2处的平坦度。可选地，填充结构108可以与支撑结构104同层设置，从而可采用同一膜层，结合一次构图工艺形成填充结构108和支撑结构104。
在一些实施例中，在本公开实施例提供的显示基板中，如图2所示，在垂直第一衬底基板100的截面上，支撑结构104的最大径向尺寸d 3可以大于等于填充结构108的最大径向尺寸d 4，以提升用于制作支撑结构104和填充结构108的掩膜板(mask)与显示基板的对位容差(margin)。易于理解的是，支撑结构104越大，容纳支撑结构104的第一过孔V 1越大，就需要设置较大的第一遮光结构107来遮挡背光，避免第一过孔V 1漏光，这对像素开口率的提升是不利的。因此，可在填充结构108的基础上，合理增大设置支撑结构104的尺寸，可选地，支撑结构104的最大径向尺寸d 3与填充结构108的最大径向尺寸d 4之差可以大于等于0μm且小于等于5μm，例如0μm、0.5μm、1μm、1.5μm、2μm、2.5μm、3μm、3.5μm、4μm、4.5μm、5μm等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，在垂直第一衬底基板100的截面上，第一过孔V 1的最大径向尺寸d 1与第二过孔V 2的最大径向尺寸d 2之差(即d 1-d 2)可以大于等于2μm且小于等于9μm， 例如可以为2μm、3μm、4μm、5μm、6μm、7μm、8μm、9μm等。通过以第二过孔V 2为基准，合理增大第一过孔V 1，不仅使得可在较大的第一过孔V 1内设置较大的支撑结构104，以对隔垫物201进行有效支撑和限制滑动，还可保证对像素开口率的影响较小。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，在垂直于第一衬底基板100的方向Z上，第一过孔V 1的深度h 1大于第二过孔V 2的深度h 2，可选地，第一过孔V 1的深度h 1与第二过孔V 2的深度h 2之差(即h 1-h 2)可以等于转接电极106在垂直于第一衬底基板100的方向Z上的厚度。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，在垂直第一衬底基板100的截面上，第一过孔V 1与第二过孔V 2之间的最短距离S 1大于等于1.5μm且小于等于5μm，例如1.5μm、2μm、2.5μm、3μm、3.5μm、4μm、4.5μm、5μm等，第一过孔V 1与第二过孔V 2之间的最长距离S 2等于(S 1+h 1*cotβ+h 2*cotγ)，其中，h 1为第一过孔V 1在垂直于第一衬底基板101方向Z上的深度，β为平坦层103在第一过孔V 1处的坡度角，h 2为第二过孔V 2在垂直于第一衬底基板101方向Z上的深度，γ为平坦层103在第二过孔V 2处的坡度角。
可选地，在一个子像素尺寸(Pitch)范围内可同时设置一个第一过孔V 1和一个第二过孔V 2，且在高分辨率的产品结构中，为了充分利用子像素的空间，可以设置第一过孔V 1的最大径向尺寸d 1、第二过孔V 2的最大径向尺寸d 2、以及第一过孔V 1与第二过孔V 2之间的最短距离S 1之和(即d 1+d 2+S 1)等于子像素在第一过孔V 1的中心与第二过孔V 2的中心连线上的尺寸。应当理解的是，在低分辨率的产品中，由于具有足够的空间设置第一过孔V 1和第二过孔V 2，因此，第一过孔V 1的最大径向尺寸d 1、第二过孔V 2的最大径向尺寸d 2、以及第一过孔V 1与第二过孔V 2之间的最短距离S 1之和(即d 1+d 2+S 1)可以小于子像素在第一过孔V 1的中心与第二过孔V 2的中心连线上的尺寸。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图7所示，还可以包括位于转接电极106所在层与第一衬底基板100之间的晶体 管109，晶体管109包括栅极91，第二过孔V 2在第一衬底基板100上的正投影位于栅极91在第一衬底基板100上的正投影内，以通过栅极91遮挡背光，避免第二过孔V 2漏光。当然，在一些实施例中，如图6所示，第二过孔V 2在第一衬底基板100上的正投影也可以与栅极91在第一衬底基板100上的正投影部分交叠，在此不做限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图7所示，还可以包括位于栅极91所在层与第一衬底基板100之间的第二遮光结构110，晶体管109包括位于栅极91所在层与第二遮光结构110之间的有源层92，有源层92包括沟道区N，沟道区N在第一衬底基板100上的正投影位于第二遮光结构110在第一衬底基板100上的正投影内，以通过第二遮光结构110遮挡背光，避免背光照射沟道区N而影响晶体管109的稳定性。
可选地，为在第二遮光结构110有效避免背光照射沟道区N的同时，兼顾像素开口率较大，第二遮光结构110在第一衬底基板100上的正投影边界与沟道区N在第一衬底基板100上的正投影边界之间的距离可以大于等于0.5μm且小于等于5μm，例如0.5μm、1μm、1.5μm、2μm、2.5μm、3μm、3.5μm、4μm、4.5μm、5μm等。
在一些实施例中，沟道区N可与栅极91上下正对设置，即沟道区N在第一衬底基板100上的正投影面积与栅极91在第一衬底基板100上的正投影面积相同，因此，在数据线102的延伸方向上，第二遮光结构110在第一衬底基板100上的正投影边界与栅极91在第一衬底基板100上的正投影边界之间的距离也可以大于等于0.5μm且小于等于5μm，例如0.5μm、1μm、1.5μm、2μm、2.5μm、3μm、3.5μm、4μm、4.5μm、5μm等。可选地，栅线101与沟道区N上下正对的部分作为栅极91使用。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图7和图8所示，为减少构图工艺和膜层数量，第二遮光结构110与第一遮光结构107可以同层设置，且第二遮光结构110与第一遮光结构107之间可以相互独立，或者一个第二遮光结构110与相邻的一个第一遮光结构107为一体结构。在 一些实施例中，相邻的一个第二遮光结构110与一个第一遮光结构107位于同一像素区。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图9所示，还可以包括与支撑结构104、填充结构108同层设置的连接结构111，连接结构111位于支撑结构104与填充结构108之间，且连接结构111与支撑结构104、填充结构108一体设置，使得撑结构101、连接结构111、填充结构108三者形成条状结构，可选地，条状结构的延伸方向与栅线101的延伸方向相同。由于支撑结构104下方有第一过孔V 1、填充结构108下方有第二过孔V 1，因此支撑结构104、填充结构108远离第一衬底基板100一侧的表面会因过孔的存在而略有凹陷，使得连接结构111远离第一衬底基板100一侧的表面到第一衬底基板100的距离，大于支撑结构104或填充结构108远离第一衬底基板100一侧的表面到第一衬底基板100的距离。可选地，相较于连接结构111远离第一衬底基板100一侧的表面，支撑结构104或填充结构108远离第一衬底基板100一侧的表面偏低0.1μm～0.5μm，例如0.1μm、0.2μm、0.3μm、0.3μm、0.5μm等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，还可以包括位于第一电极105所在层远离平坦层103一侧的第二电极112，第二电极112在第一衬底基板100上的正投影与第一电极105在第一衬底基板100上的正投影至少部分交叠。可选地，第一电极105为像素电极，第二电极112为公共电极，公共电极可为狭缝状电极。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，转接电极106与晶体管109的有源层92电连接，可选地，有源层92的材料可以为金属氧化物，例如，氧化铟镓锌(IGZO)、非晶态或多晶态的氧化锌(ZnO)、氧化铟锌(IZO)、氧化锌锡(ZTO)、氧化锡锌(IZTO)、氧化镓锌锡(IGZTO)、氧化铟镓(IGO)中的任意一种或多种，且为了提高透过率，转接电极106的材料可以为氧化铟锡(ITO)、氧化铟锡(IZO)等透明导电氧化物。另外，如图2所示，在本公开中还可以包括顶栅结构的多晶硅晶体管， 第一遮光结构107和第二遮光结构110可以与多晶硅晶体管的栅极同层设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，还可以包括第一栅绝缘层114、第一层间介电层115、第二栅绝缘层116、第二层间介电层117、第一绝缘层118和第二绝缘层119等。对于显示基板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例还提供了一种显示面板，如图1所示，包括：相对而置的显示基板001和对向基板002，其中，显示基板001为本公开实施例提供的上述显示基板001，对向基板002包括第二衬底基板200、以及位于第二衬底基板200面向显示基板001一侧的隔垫物201，隔垫物201朝向显示基板001一侧的端部设置在凹陷部C内，使得隔垫物201因凹陷部C的限制作用而较难滑出支撑结构104。
在一些实施例中，如图10所示，隔垫物201的坡度角θ大于等于40°且小于等于90°，例如40°、45°、50°、55°、60°、65°、70°、75°、80°、85°、90°等。隔垫物201的高度大于等于0.5μm且小于等于2μm，例如0.5μm、1μm、1.5μm、2μm等。
在一些实施例中，本公开实施例提供的上述显示面板可为液晶显示面板。液晶显示面板还可以包括位于显示基板001和对向基板002之间的液晶层。可选地，本公开中以第一电极105和第二电极112均设置在显示基板001上为例进行说明，在一些实施例中，第二电极112也可以设置在对向基板002上。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健 身腕带、个人数字助理、虚拟现实(VR)头戴式显示设备等任何具有显示功能的产品或部件。该显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示基板，其中，包括：
    第一衬底基板；
    多条栅线和多条数据线，设置在所述第一衬底基板的一侧，所述多条栅线和所述多条数据线相互交叉设置且相互绝缘；
    平坦层，设置在所述栅线和所述数据线远离所述第一衬底基板的一侧，且包括第一过孔；
    支撑结构，设置在所述平坦层远离所述第一衬底基板的一侧且填充至所述第一过孔中，在垂直于所述第一衬底基板的方向上，所述支撑结构的高度大于所述第一过孔的深度。
  2. 如权利要求1所述的显示基板，其中，所述支撑结构远离所述第一衬底基板一侧的表面为第一表面，所述第一表面为曲面结构，所述第一表面到所述第一衬底基板之间的最大距离与最小距离之间的垂直高度差值范围为a，0＜|a|≤1μm。
  3. 如权利要求2所述的显示基板，其中，所述多条栅线在所述第一衬底基板上的正投影与所述多条数据线在所述第一衬底基板上的正投影具有多个交叠区，至少部分数量的所述交叠区位于所述第一过孔在所述第一衬底基板上的正投影内。
  4. 如权利要求3所述的显示基板，其中，还包括位于所述栅线所在层与所述第一衬底基板之间的第一遮光结构，所述第一遮光结构在所述第一衬底基板上的正投影至少覆盖所述交叠区之外的所述第一过孔在所述第一衬底基板上的正投影。
  5. 如权利要求4所述的显示基板，其中，还包括位于所述平坦层与所述支撑结构所在层之间的第一电极，位于所述平坦层与所述数据线所在层之间的转接电极，以及与所述支撑结构同层设置的填充结构；
    所述平坦层还包括第二过孔，所述第一电极通过所述第二过孔与所述转 接电极连接，所述填充结构填充所述第二过孔。
  6. 如权利要求5所述的显示基板，其中，在垂直所述第一衬底基板的截面上，所述支撑结构的最大径向尺寸与所述填充结构的最大径向尺寸之差大于等于0μm且小于等于5μm。
  7. 如权利要求5或6所述的显示基板，其中，在垂直所述第一衬底基板的截面上，所述第一过孔的最大径向尺寸与所述第二过孔的最大径向尺寸之差大于等于2μm且小于等于9μm。
  8. 如权利要求5～7任一项所述的显示基板，其中，在垂直于所述第一衬底基板的方向上，所述第一过孔的深度大于所述第二过孔的深度。
  9. 如权利要求5～8任一项所述的显示基板，其中，在垂直所述第一衬底基板的截面上，所述第一过孔与所述第二过孔之间的最短距离S 1大于等于2μm且小于等于5μm，所述第一过孔与所述第二过孔之间的最长距离等于(S 1+h 1*cotβ+h 2*cotγ)，其中，h 1为所述第一过孔在垂直于所述第一衬底基板的方向上的深度，β为所述平坦层在所述第一过孔处的坡度角，h 2为所述第二过孔在垂直于所述第一衬底基板的方向上的深度，γ为所述平坦层在所述第二过孔处的坡度角。
  10. 如权利要求5～9任一项所述的显示基板，其中，还包括位于所述转接电极所在层与所述第一衬底基板之间的晶体管，所述晶体管包括栅极，所述第二过孔的至少部分在所述第一衬底基板上的正投影位于所述栅极在所述第一衬底基板上的正投影内。
  11. 如权利要求10所述的显示基板，其中，还包括位于所述栅极所在层与所述第一衬底基板之间的第二遮光结构；
    所述晶体管包括位于所述栅极所在层与所述第二遮光结构所在层之间的有源层，所述有源层包括沟道区，所述沟道区在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
  12. 如权利要求11所述的显示基板，其中，所述第一遮光结构与所述第二遮光结构同层设置，且所述第一遮光结构与所述第二遮光结构相互独立， 或者，一个所述第一遮光结构与相邻的一个所述第二遮光结构为一体结构。
  13. 如权利要求5～12任一项所述的显示基板，其中，还包括与所述支撑结构、所述填充结构同层设置的连接结构，所述连接结构位于所述支撑结构与所述填充结构之间，并与所述支撑结构、所述填充结构一体设置；
    所述连接结构远离所述第一衬底基板一侧的表面到所述第一衬底基板的距离，大于所述支撑结构或所述填充结构远离所述第一衬底基板一侧的表面到所述第一衬底基板的距离。
  14. 如权利要求5～13任一项所述的显示基板，其中，还包括位于所述第一电极所在层远离所述平坦层一侧的第二电极。
  15. 一种显示面板，其中，包括：相对而置的显示基板和对向基板，其中，所述显示基板为如权利要求1～14任一项所述的显示基板，所述对向基板包括第二衬底基板、以及位于所述第二衬底基板面向所述显示基板一侧的隔垫物，所述隔垫物朝向所述显示基板一侧的端部设置在所述支撑结构的凹陷部内。
  16. 一种显示装置，其中，包括如权利要求15所述的显示面板。
PCT/CN2022/100511 2022-06-22 2022-06-22 显示基板、显示面板及显示装置 WO2023245509A1 (zh)

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EP1918765A2 (en) * 2006-10-31 2008-05-07 Samsung Electronics Co., Ltd. Display apparatus and method of fabricating the same
CN105929607A (zh) * 2016-07-04 2016-09-07 京东方科技集团股份有限公司 一种液晶显示面板及其制造方法、显示装置
CN205750219U (zh) * 2016-06-21 2016-11-30 厦门天马微电子有限公司 一种液晶显示装置
CN107703683A (zh) * 2017-09-26 2018-02-16 武汉华星光电技术有限公司 显示面板及其制作方法
CN109856841A (zh) * 2019-03-29 2019-06-07 厦门天马微电子有限公司 一种液晶显示面板及显示装置
JP2020042104A (ja) * 2018-09-07 2020-03-19 株式会社ジャパンディスプレイ 液晶表示装置
CN114068590A (zh) * 2022-01-14 2022-02-18 京东方科技集团股份有限公司 阵列基板以及显示面板

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1918765A2 (en) * 2006-10-31 2008-05-07 Samsung Electronics Co., Ltd. Display apparatus and method of fabricating the same
CN205750219U (zh) * 2016-06-21 2016-11-30 厦门天马微电子有限公司 一种液晶显示装置
CN105929607A (zh) * 2016-07-04 2016-09-07 京东方科技集团股份有限公司 一种液晶显示面板及其制造方法、显示装置
CN107703683A (zh) * 2017-09-26 2018-02-16 武汉华星光电技术有限公司 显示面板及其制作方法
JP2020042104A (ja) * 2018-09-07 2020-03-19 株式会社ジャパンディスプレイ 液晶表示装置
CN109856841A (zh) * 2019-03-29 2019-06-07 厦门天马微电子有限公司 一种液晶显示面板及显示装置
CN114068590A (zh) * 2022-01-14 2022-02-18 京东方科技集团股份有限公司 阵列基板以及显示面板

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