WO2023234963A1 - Dispositif et procédés de mesure de bruit de phase - Google Patents

Dispositif et procédés de mesure de bruit de phase Download PDF

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Publication number
WO2023234963A1
WO2023234963A1 PCT/US2022/051211 US2022051211W WO2023234963A1 WO 2023234963 A1 WO2023234963 A1 WO 2023234963A1 US 2022051211 W US2022051211 W US 2022051211W WO 2023234963 A1 WO2023234963 A1 WO 2023234963A1
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WO
WIPO (PCT)
Prior art keywords
signal
output
noise
receive
communication channel
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Application number
PCT/US2022/051211
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English (en)
Inventor
Gary Qu Jin
Chris DU QUESNAY
Ehsan RAHIMI
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Microchip Technology Incorporated
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Filing date
Publication date
Priority claimed from US17/952,535 external-priority patent/US20230393184A1/en
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Publication of WO2023234963A1 publication Critical patent/WO2023234963A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31709—Jitter measurements; Jitter generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks

Definitions

  • the present disclosure relates to a device and method for measuring phase noise through a communication channel.
  • a clock signal in a digital communication channel, includes a noise component which is generally referred to herein as phase noise.
  • phase noise will be propagated through the communication channel
  • the communication channel may modify the frequency content of the phase noise.
  • This communication channel could be known or unknown.
  • the phase noise at the receiver end (after the communication channel) may be modified by the communication channel and have a different frequency spectrum than the original phase noise.
  • Different communication protocols may impose different requirements on clock phase noise. In order to ensure compliance with communications standards, it is important to accurately measure phase noise at the receiver end.
  • a clock signal may be sampled to obtain digital samples of the clock signal.
  • the phase noise may be contained in the digital samples of the clock signal.
  • the sampling may be performed in the time domain and a time to frequency transformer may transform the time domain sample into frequency domain.
  • the frequency domain signal may be passed through a communication channel, either a physical channel or a model, to produce an output that includes the impact of the channel on the phase noise of the clock signal.
  • the output of this channel will also include frequency spurs introduced by the sampling of the clock signal.
  • phase noise of the clock signal at the receiver end is that the bandwidth of the channel may exceed the clock signal sampling rate.
  • a simple noise integration may be performed to calculate the phase noise.
  • existing solutions may use a spectrum extension method or other method of estimating the high frequency content.
  • Spectrum extension may be performed using a technique including but not limited to spectral replication or folding, harmonic replication, neural- network training model, pitch adaptive modulation or Hidden Markov Model (HMM). These estimates may be impacted by spur frequencies introduced by the sampling operation.
  • spectrum extension will be of limited accuracy because spectrum extension may include assumptions of how to estimate the higher frequency content, which assumptions may not be 100% accurate.
  • the out-of-band noise may be unpredictable and any spectrum extension will introduce error.
  • a device for measuring phase noise including a sampler to sample an input signal, an input filter to receive an input from the sampler, a noise generator to generate a noise signal, a combiner to receive input from, respectively, the input filter and the noise generator, the combiner to output an integrated noise output measurement.
  • An aspect provides a device for measuring phase noise including a time-to-frequency domain transformer to receive the sampled input signal and to generate a first and a second output signal at least partly as a result of the received sampled input signal, a first communication channel to receive the first output signal from the time-to-frequency domain transformer, a low-pass filter to receive an output signal from the first channel communication channel, a spur suppression filter to receive an output signal from the low-pass filter, the spur suppression filter to output a signal to the combiner.
  • An aspect provides a device for measuring phase noise including a noise spectrum generator to receive the second output signal from the time-to-frequency domain transformer, a second communication channel to receive an output from the noise spectrum generator, a high-pass filter to receive an output from the second communication channel, the high-pass filter to output a signal to the combiner.
  • a method for measuring phase noise including sampling an input signal to generate a sampled input signal, filtering the sampled input signal to generate a filtered input signal, generating a noise signal, and combining the filtered input signal and the noise signal to generate an integrated noise output.
  • An aspect provides a method for measuring phase noise including transforming the sampled input signal from the time domain to the frequency domain thereby generating a frequency domain representation of the sampled input signal, passing the frequency domain representation of the sampled input signal through a first communication channel, filtering the output of the first communication channel with a low-pass filter to generate a low-frequency filtered signal, and suppressing spurs in the low-frequency filtered signal with a spur suppression filter;
  • An aspect provides a method for measuring phase noise including generating a noise signal, based at least partly on the frequency domain representation of the sampled input signal, passing the frequency domain representation of the sampled input signal through a second communication channel, and filtering the output of the second communication channel with a high-pass filter to generate a high-frequency filtered signal;
  • the figures illustrate example circuits and systems for measurement of phase noise.
  • FIGURE 1 illustrates a device for measuring phase noise of an input clock.
  • FIGURE 2 illustrates a device for measuring phase noise of an input clock in the frequency domain.
  • FIGURE 3 illustrates a circuit for a spur suppression filter.
  • FIGURE 4 illustrates a technique for estimating a noise level in the frequency domain.
  • FIGURE 5 illustrates an alternative device for measuring phase noise of an input clock signal in the frequency domain.
  • FIGURE 6 illustrates a method for estimating a noise level in the time domain.
  • FIGURE 7 illustrates a device for measuring phase noise of an input clock in the time domain.
  • FIGURE 8 illustrates an alternative device for measuring phase noise of an input clock in the time domain.
  • FIGURE 1 illustrates one of various examples of a device for measurement of phase noise.
  • Device 100 may be a digital signal processor (DSP) where individual components of FIGURE 1 may represent specific functions implemented on the DSP.
  • DSP digital signal processor
  • Device 100 may be a microcontroller where individual components of FIGURE 1 may represent specific functions implemented on the microcontroller.
  • DSP digital signal processor
  • Device 100 may be a field-programmable gate array (FPGA) where individual components of FIGURE 1 may represent specific functions implemented on the FPGA.
  • Device 100 may be a combination of multiple individual computational elements which in combination form the device illustrated in FIGURE 1.
  • Device 100 may include a clock input 110.
  • Clock input 110 may receive a clock signal from a phase- locked loop (PLL), delay-locked loop (DLL), or other clock source.
  • PLL phase-locked loop
  • DLL delay-locked loop
  • Clock input 110 may be sampled by sampler 130.
  • sampler 130 may be sampled clock signal 135.
  • Sampled clock signal 135 may be input to input filter 150.
  • Input filter 150 may include multiple computational blocks to filter sampled clock signal 135. Computational blocks may include but are not limited to low-pass filters, communication channels, band-pass filters, high-pass filters, spur suppression filters, noise generators, equalizers and transforms.
  • Input filter 150 may provide a filtered output 155 to combiner 190. Input filter 150 may optionally provide an output 160 to noise generator 170.
  • Noise generator 170 may include one or more computational blocks to compute a noise signal. Noise generator 170 may include other computational blocks, including but not limited to low-pass filters, communication channels, band-pass filters, high-pass filters, spur suppression filters, equalizers and transforms. Noise generator 170 may provide noise output 175 to combiner 190.
  • Combiner 190 may combine filtered output 155 and noise output 175 using one of various methods.
  • Combiner 190 may include adders, integrators, multipliers and other computational blocks to combine filtered output 155 and noise output 175. Combiner 190 may output an integrated phase noise measurement 199.
  • FIGURE 2 illustrates one of various examples of a device for measurement of phase noise.
  • Device 200 may be a digital signal processor (DSP) where individual components of FIGURE 2 may represent specific functions implemented on the DSP.
  • DSP digital signal processor
  • Device 200 may be a microcontroller where individual components of FIGURE 2 may represent specific functions implemented on the microcontroller.
  • DSP digital signal processor
  • Device 200 may be a field-programmable gate array (FPGA) where individual components of FIGURE 2 may represent specific functions implemented on the FPGA.
  • Device 200 may be a combination of multiple individual computational elements which in combination form the device illustrated in FIGURE 2.
  • Device 200 may include a clock input 110.
  • Clock input 110 may receive a clock signal from a phase- locked loop (PLL), delay-locked loop (DLL), or other clock source.
  • PLL phase-locked loop
  • Clock input 110 may be sampled by sampler 130.
  • the output of sampler 130 may be sampled clock signal 135.
  • Sampled clock signal 135 may be input to time to frequency transformer 250.
  • Time to frequency transformer 250 may convert the time domain sampled clock signal 135 into frequency domain representation 255.
  • Frequency domain representation 255 may be input to first communication channel 260.
  • First communication channel 260 may be a physical channel, or may be a model of a channel defined by frequency domain response H(s).
  • First communication channel 260 may modify the frequency content of the frequency domain representation 255 consistent with the frequency domain representation H(s).
  • First communication channel 260 may be a model defined by a frequency domain model H(f).
  • First communication channel 260 may modify the frequency content of the frequency domain representation 255 consistent with the frequency domain representation H(f).
  • first communication channel 260 may be input to a low-pass filter 265, defined by an s-domain response Hi(s).
  • Low-pass filter 265 may be defined by a frequency domain response Hi(f).
  • the output of low-pass filter 265 may be input to spur suppression filter 280.
  • Spur suppression filter 280 may filter the input low-pass filtered signal to remove frequency spurs introduced by sampler 130, first communication channel 260, low-pass filter 265, or any spurious content from other sources.
  • Components time to frequency transformer 250, first communication channel 260, low-pass filter 265 and spur suppression filter 280 may comprise input filter 150 as illustrated in FIGURE 1.
  • Frequency domain representation 255 may be input to noise spectrum generator 270.
  • Noise spectrum generator 270 may produce an output noise spectrum 271 with noise magnitude controlled at least partly by the frequency domain representation 255, as detailed in later portions of this specification.
  • the output noise spectrum 271 of the noise spectrum generator 270 may be input to second communication channel 272.
  • Second communication channel 272 may be a physical channel, or may be a model of a channel defined by frequency domain response H(s).
  • Second communication channel 272 may be defined by a frequency domain model H(f).
  • Second communication channel 272 and first communication channel 260 may have identical responses H(s).
  • Second communication channel 272 and first communication channel 260 may have identical responses H(f).
  • the output of second communication channel 272 may be input to high-pass filter 275, defined by a frequency domain response l-Hi(s).
  • High-pass filter 275 may be defined by a frequency domain response l-Hi(f).
  • Components noise spectrum generator 270, second communication channel 272, and high-pass filter 275 may comprise noise generator 170 as illustrated in FIGURE 1.
  • the output of spur suppression filter 280 and the output of high-pass filter 275 respectively may be inputs to adder 285.
  • the output of adder 285 may be input to integrator 290.
  • Integrator 290 may integrate the output of adder 285 over a predetermined frequency bandwidth to determine an integrated phase noise measurement 299. Integrator 290 and adder 285 may comprise combiner 190 of FIGURE 1.
  • FIGURE 3 illustrates one of various examples of spur suppression filter 280.
  • Input signal 310 may be input to spur frequency search block 320.
  • Input signal 310 may be the output of low-pass filter 265 of FIGURE 2.
  • Spur frequency search block 320 may calculate the location of a spur frequency according to the following method. The spur frequency may be determined based on finding a peak in the frequency spectrum of input signal 310 between a first frequency fspur in- BWspur and a second frequency fspur in + BWspur, where fspur in represents the frequency of the sampler 130 of FIGURE 1, and BWspur represents a predetermined bandwidth of the spur.
  • the spur frequency also referred to as fspur
  • Linear interpolation block 330 may suppress harmonics of spur frequency fspur Up tO a predetermined maximum frequency fmax according to the following method.
  • a spur start frequency fstan may be defined as k*f sp ur - BWspur
  • a spur stop frequency may be defined as k*f sp ur + BWspur., where k may be an integer from 1 to N, where N may be defined as fmax/ fspur.
  • the frequency content of input signal 310 between the spur start frequency and the spur stop frequency may be suppressed according to the following interpolation equation, where 1(f) represents the interpolated frequency content at each of the N spur locations, between the spur start frequency and the spur stop frequency:
  • FIGURE 3 is one of various examples of spur suppression and is not intended to limit other methods of spur suppression.
  • noise spectrum generator 270 of FIGURE 2 may generate a noise signal based on one of various methods.
  • Frequency domain representation 255 may be represented as S(f).
  • S(f) may contain N spectral bins, numbered from bin 0 to bin N-l, and the spectral magnitude of S(f) may be defined as
  • the last M spectral bins (bins N-M to N-l) may be analyzed. Of the last M spectral bins, the K bins with the smallest spectral magnitude are selected.
  • the values of N, M, and K may be predetermined values where N>M and M>K.
  • Array Smin may contain the K bins of smallest spectral magnitude, defined as Smin(l) to Smin(K).
  • the magnitude of output noise spectrum 271 is termed NL, and may be defined as the average of these K bins of smallest spectral magnitude as follows:
  • Frequency domain representation 255 is illustrated as spectral magnitude 410, with magnitude on the y-axis and spectral bin on the x-axis.
  • N the total number of spectral bins, may be 128. This number is not intended to be limiting but is merely for illustration purposes.
  • the shape and magnitude of spectral magnitude 410 is not intended to be limiting and is merely for purposes of illustration.
  • M may be set to 16.
  • K may be set to 4.
  • the 4 bins of smallest magnitude are selected from the final 16 bins.
  • FIGURE 5 illustrates an alternative device for measuring phase noise.
  • Device 500 may be a digital signal processor (DSP) where individual components of FIGURE 5 may represent specific functions implemented on the DSP.
  • DSP digital signal processor
  • Device 500 may be a microcontroller where individual components of FIGURE 5 may represent specific functions implemented on the microcontroller.
  • DSP digital signal processor
  • Device 500 may be a field-programmable gate array (FPGA) where individual components of FIGURE 5 may represent specific functions implemented on the FPGA.
  • Device 500 may be a combination of multiple individual computational elements which in combination form the device illustrated in FIGURE 5.
  • Device 500 may have a clock input 110.
  • Clock input 110 may receive a clock signal from a phase-locked loop (PLL), delay-locked loop (DLL), or other clock source.
  • PLL phase-locked loop
  • DLL delay-locked loop
  • Clock input 110 may be sampled by a sampler 130.
  • the output of sampler 130 may be a sampled clock signal 135.
  • Sampled clock signal 135 may be input to time to frequency transformer 550.
  • Time to frequency transformer 550 may convert sampled clock signal 135 into a frequency domain representation 555.
  • Frequency domain representation 555 may be input to a communication channel 560.
  • Communication channel 560 may be a physical channel, or may be a model of a channel defined by frequency response H(s).
  • Communication channel 560 may modify the frequency content of the frequency domain representation 555 consistent with frequency domain representation H(s).
  • Communication channel 560 may be defined by a frequency domain model H(f).
  • Communication channel 560 may modify the frequency content of the frequency domain representation 555 consistent with frequency domain representation H(f).
  • the output of communication channel 560 may be input to a low- pass filter 565, defined by a frequency domain response Hi(s).
  • Low-pass filter 565 may be defined by a frequency domain response Hi(f).
  • the output of low-pass filter 565 may be input to a spur suppression filter 580.
  • Spur suppression filter 580 may filter the input signal to remove spurs in the signal introduced by sampler 130, by communication channel 560, by low-pass filter 565, or any spurious content from other sources.
  • Integrator 590 may integrate the output of spur suppression filter 580.
  • Time to frequency transformer 550, communication channel 560, low-pass filter 565 and spur suppression filter 580 may comprise input filter 150 of FIGURE 1.
  • An output of integrator 590 may be one input to an adder 585.
  • Noise estimate 595 may be a second input to adder 585.
  • Output of adder 585 may be integrated phase noise measurement 599.
  • Integrator 590 and adder 585 may comprise combiner 190 of FIGURE 1.
  • the magnitude of the noise estimate 595 may be determined in the frequency domain according to the method illustrated in FIGURE 4.
  • the magnitude of the noise estimate 595 may be determined in the time domain according to the method illustrated in FIGURE 6.
  • FIGURE 6 illustrates a method for determining a noise level NL in the time domain, where NL represents the magnitude of a generated noise signal.
  • a noise level NL may be initialized to zero and index n may be initialized to zero.
  • Input x(n) may be sampled input signal 135.
  • a comparison may be performed between the current sample of input x(n) and the current value of the noise level, NL. If the magnitude of the input signal sample exceeds the magnitude of the noise level, or
  • the parameter si may be a predetermined value between 0 and 1, which may control the rate of change of the noise level NL.
  • the noise level NL will quickly change to approach the value of
  • , where for a value of si 0.1 the noise level NL will slowly change to approach the value of
  • NL NL + S2 * (
  • Parameter S2 may be a predetermined value between 0 and 1, which may control the rate of change of the updated noise level, NL.
  • the updated noise level may quickly change to near the value of
  • , where for a value of S2 0.1 the updated noise level may very slowly change to approach the value of
  • S2 may be set to a value much larger than si, and the noise level may decrease much faster than it will increase.
  • the values of si and S2 may be set to enable a particular rate of increase and decrease in the noise level, NL, as the input magnitude
  • the method returns to operation 620 and the next sample of x(n) is analyzed. If there is no more data to process, the method ends and the noise level may not update further.
  • FIGURE 7 illustrates one of various examples of a device for measurement of phase noise in the time domain.
  • Device 700 may be a digital signal processor (DSP) where individual components of FIGURE 7 may represent specific functions implemented on the DSP.
  • DSP digital signal processor
  • Device 700 may be a microcontroller where individual components of FIGURE 7 may represent specific functions implemented on the microcontroller.
  • DSP digital signal processor
  • Device 700 may be a field- programmable gate array (FPGA) where individual components of FIGURE 7 may represent specific functions implemented on the FPGA.
  • Device 700 may be a combination of multiple individual computational elements which in combination form the device illustrated in FIGURE 7.
  • Device 700 may include a clock input 110.
  • Clock input 110 may receive a clock signal from a phase-locked loop (PLL), delay-locked loop (DLL), or other clock source.
  • PLL phase-locked loop
  • DLL delay-locked loop
  • Clock input 110 may be sampled by sampler 130.
  • the output of sampler 130 may be sampled clock signal 135.
  • Sampled clock signal 135 may be input to first communication channel 760.
  • First communication channel 760 may be a physical channel, or may be a model of a channel defined by time domain response h(t).
  • First communication channel 760 may modify the content of sampled clock signal 135 consistent with the time domain representation h(t).
  • the output of first communication channel 760 may be input to a low-pass filter 765, defined by a time domain response hi(t).
  • the output of low-pass filter 765 may be input to spur suppression filter 780.
  • Spur suppression filter 780 may filter the input low-pass filtered signal to remove frequency spurs introduced by sampler 130, first communication channel 760, low-pass filter 765, or any spurious content from other sources.
  • Components first communication channel 760, low-pass filter 765 and spur suppression filter 780 may comprise input filter 150 as illustrated in FIGURE 1.
  • Sampled clock signal 135 may be input to noise signal generator 770.
  • Noise signal generator 770 may produce an output noise signal 771 with noise magnitude controlled at least partly by sampled clock signal 135.
  • the output noise signal 771 of the noise signal generator 770 may be input to second communication channel 772.
  • Second communication channel 772 may be a physical channel, or may be a model of a channel defined by time domain response h(t).
  • Second communication channel 772 and first communication channel 760 may have identical responses h(t).
  • the output of second communication channel 772 may be input to high-pass filter 775, defined by a time domain response l-hi(t).
  • Components noise signal generator 770, second communication channel 772, and high-pass filter 775 may comprise noise generator 170 as illustrated in FIGURE 1.
  • Spur suppression filter 780 may suppress spurs in the low-pass filter output as described in previous portions of this disclosure.
  • Spur suppression filter 780 may suppress spurs in the low-pass filter output by another method.
  • Noise signal generator 770 may generate a noise signal as described in previous portions of this disclosure. Noise signal generator 770 may generate a noise signal by another method.
  • the output of spur suppression filter 780 and the output of high-pass filter 775 respectively may be inputs to adder 785.
  • the output of adder 785 may be input to integrator 790.
  • Integrator 790 may integrate the output of adder 785 over a predetermined period to determine an integrated phase noise measurement 799.
  • FIGURE 8 illustrates an alternative device for measuring phase noise in the time domain.
  • Device 800 may be a digital signal processor (DSP) where individual components of FIGURE 8 may represent specific functions implemented on the DSP.
  • DSP digital signal processor
  • Device 800 may be a microcontroller where individual components of FIGURE 8 may represent specific functions implemented on the microcontroller.
  • Device 800 may be a field-programmable gate array (FPGA) where individual components of FIGURE 8 may represent specific functions implemented on the FPGA.
  • Device 800 may be a combination of multiple individual computational elements which in combination form the device illustrated in FIGURE 8.
  • Device 800 may have a clock input 110.
  • Clock input 110 may receive a clock signal from a phase- locked loop (PLL), delay-locked loop (DLL), or other clock source.
  • PLL phase-locked loop
  • DLL delay-locked loop
  • Clock input 110 may be sampled by a sampler 130.
  • the output of sampler 130 may be a sampled clock signal 135.
  • Sampled clock signal 135 may be input to communication channel 860.
  • Communication channel 860 may be a physical channel, or may be a model of a channel defined by time domain response h(t).
  • Communication channel 860 may modify the content of the sampled clock signal 135 consistent with time domain representation h(t).
  • the output of communication channel 860 may be input to a low-pass filter 865, defined by a time domain response hi(t).
  • the output of low-pass filter 865 may be input to a spur suppression filter 880.
  • Spur suppression filter 880 may filter the input signal to remove spurs in the signal introduced by sampler 130, by communication channel 860, by low-pass filter 865, or any spurious content from other sources.
  • Integrator 890 may integrate the output of spur suppression filter 880.
  • An output of integrator 890 may be one input to an adder 885.
  • Noise estimate 895 may be a second input to adder 885.
  • Output of adder 885 may be integrated phase noise measurement 599.
  • the magnitude of the noise estimate 895 may be determined in the frequency domain according to the method illustrated in FIGURE 4.
  • the magnitude of the noise estimate 895 may be determined in the time domain according to the method illustrated in FIGURE 6.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Noise Elimination (AREA)

Abstract

L'invention concerne un dispositif pour mesurer un bruit de phase, comprenant un échantillonneur pour échantillonner un signal d'entrée, un filtre d'entrée pour recevoir une entrée provenant de l'échantillonneur, un générateur de bruit pour générer un signal de bruit, un combinateur pour recevoir une entrée à partir, respectivement, du filtre d'entrée et du générateur de bruit, le combinateur étant destiné à délivrer en sortie une mesure de sortie de bruit intégrée. Le filtre d'entrée peut fonctionner soit dans le domaine temporel, soit dans le domaine fréquentiel. Le générateur de bruit peut générer un signal de bruit sur la base de la sortie d'échantillonneur ou peut générer une valeur d'estimation de bruit sur la base de la sortie d'échantillonneur.
PCT/US2022/051211 2022-06-02 2022-11-29 Dispositif et procédés de mesure de bruit de phase WO2023234963A1 (fr)

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US17/952,535 2022-09-26
US17/952,535 US20230393184A1 (en) 2022-06-02 2022-09-26 Device and methods for phase noise measurement

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US7239969B2 (en) * 2004-11-09 2007-07-03 Guide Technology, Inc. System and method of generating test signals with injected data-dependent jitter (DDJ)
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US20170236526A1 (en) * 2014-08-15 2017-08-17 Samsung Electronics Co., Ltd. Sound quality improving method and device, sound decoding method and device, and multimedia device employing same

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US7239969B2 (en) * 2004-11-09 2007-07-03 Guide Technology, Inc. System and method of generating test signals with injected data-dependent jitter (DDJ)
US8965727B2 (en) * 2005-05-20 2015-02-24 Omniphase Research Laboratories, Inc. Intelligent low noise design
US20170236526A1 (en) * 2014-08-15 2017-08-17 Samsung Electronics Co., Ltd. Sound quality improving method and device, sound decoding method and device, and multimedia device employing same

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Title
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RUBIOLA ENRICO ET AL: "Correlation-based phase noise measurements", REVIEW OF SCIENTIFIC INSTRUMENTS, AMERICAN INSTITUTE OF PHYSICS, 2 HUNTINGTON QUADRANGLE, MELVILLE, NY 11747, vol. 71, no. 8, 1 August 2000 (2000-08-01), pages 3085 - 3091, XP012038446, ISSN: 0034-6748, DOI: 10.1063/1.1304871 *

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