WO2023231081A1 - 封装结构及其制作方法、半导体器件 - Google Patents
封装结构及其制作方法、半导体器件 Download PDFInfo
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- WO2023231081A1 WO2023231081A1 PCT/CN2022/098442 CN2022098442W WO2023231081A1 WO 2023231081 A1 WO2023231081 A1 WO 2023231081A1 CN 2022098442 W CN2022098442 W CN 2022098442W WO 2023231081 A1 WO2023231081 A1 WO 2023231081A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 65
- 230000003993 interaction Effects 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 24
- 239000010410 layer Substances 0.000 description 156
- 239000000523 sample Substances 0.000 description 30
- 238000002955 isolation Methods 0.000 description 21
- 238000005192 partition Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 12
- 239000002346 layers by function Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 230000006870 function Effects 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
Definitions
- the present disclosure relates to the field of semiconductor technology, including but not limited to packaging structures and manufacturing methods thereof, and semiconductor devices.
- ports for testing and performing functional interactions need to be prepared on the packaging structure.
- embodiments of the present disclosure provide a packaging structure, a manufacturing method thereof, and a semiconductor device.
- a packaging structure including:
- a rewiring layer which is electrically connected to the interconnection layer of the semiconductor functional structure
- the exposed part of the redistribution layer includes at least one first pad; wherein the first pad includes a first area and a second area arranged continuously; the first area is used for testing; The second area is used to perform functional interaction corresponding to the content of the test.
- the packaging structure further includes: a plurality of second pads, composed of the exposed portions of the rewiring layer of the insulating layer, used for testing or performing tasks corresponding to the content of the test. functional interaction;
- the second pads among the plurality of second pads are arranged side by side with the at least one first pad along a first direction, and the first direction is perpendicular to the first area and points toward the The direction of the second area; the area of each first pad is greater than the area of each second pad.
- the first liner and the second liner are both in the shape of strips; the width of the first liner along the first direction is the same as the width of the second liner along the first direction.
- the widths in the directions are the same; the spacing between two adjacent pads is equal; and one end of all pads arranged side by side along the first direction is flush.
- the number of the first pads includes multiple, and at least part of the first pads are arranged side by side in the first direction close to the first edge of the semiconductor functional structure; at least part of the second pads Pads are arranged juxtaposed on both sides of the plurality of first pads along the first direction.
- At least two second pads are included on each side of the plurality of first pads.
- a part of the second pads are arranged side by side on both sides of the plurality of first pads along the first direction, and another part of the second pads are arranged side by side in the second direction close to the semiconductor function.
- the second direction is perpendicular to the first direction; the first edge and the second edge are two opposite edges of the semiconductor functional structure.
- the number of the first pads includes multiple, a part of the first pads are arranged side by side along the first direction close to the first edge of the semiconductor functional structure, and the other part of the first pads
- the pads are arranged side by side along the first direction close to the second edge of the semiconductor functional structure; a part of the second pads are arranged side by side on both sides of a part of the first pad along the first direction, and the other part
- the second pads are arranged side by side on both sides of the other part of the first pads along the first direction; the first edge and the second edge are two opposite edges of the semiconductor functional structure.
- the arrangement of the first pad and the second pad located close to the first edge of the semiconductor functional structure is consistent with the arrangement of all the first pads located close to the second edge of the semiconductor functional structure.
- the first pad and the second pad are arranged symmetrically.
- one end of all pads arranged side by side along the first direction and close to the edge of the semiconductor functional structure is flush;
- the first region is located at an end of the first pad close to the edge of the semiconductor functional structure, and the second region is located at an end of the first pad away from the edge of the semiconductor functional structure.
- a semiconductor device including: a semiconductor functional structure and a packaging structure as described in any one of the above embodiments of the disclosure.
- a method for manufacturing a packaging structure includes:
- a rewiring layer on the semiconductor functional structure, the rewiring layer being electrically connected to the interconnection layer on the semiconductor functional structure;
- each of the first pads is composed of a portion of the redistribution layer exposed by the insulating layer;
- the first pad includes a first area and a second area arranged continuously; the first area is used for testing, and the second area is used for performing functional interaction corresponding to the content of the test.
- each first pad includes a first area for performing a test, and a first area for performing a test corresponding to the content of the test.
- the second area for functional interaction; the first area and the second area are set up continuously, in other words, there is no partition wall between the first area and the second area.
- Figure 1 is a schematic cross-sectional structural diagram of a packaging structure provided in an embodiment of the present disclosure
- Figure 2a is a schematic cross-sectional structural diagram of another packaging structure provided in an embodiment of the present disclosure.
- Figure 2b is a schematic cross-sectional structural diagram of yet another packaging structure provided in an embodiment of the present disclosure.
- Figures 3a-3e are schematic diagrams of the relative positional relationship between several first pads and second pads provided by embodiments of the present disclosure
- Figure 4 is a schematic flowchart of a manufacturing method of a packaging structure provided in an embodiment of the present disclosure
- 5a-5c are schematic cross-sectional views of a manufacturing process of a packaging structure provided in an embodiment of the present disclosure.
- the term "A and B are connected" includes the situation where A and B are in direct contact, or the situation where A and B are in indirect contact through an intermediate conductive structure.
- the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
- the term "layer” refers to a portion of material that includes a region having a thickness.
- a layer may extend on the lower or upper surface of the structure and may have an area less than or equal to the extended surface.
- the semiconductor functional structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
- the final device may include memory.
- a pad also called a pad, expressed in English as PAD
- RDL Redistribution Layer
- the rewiring layer opening refers to forming a rewiring layer on the top metal layer of the semiconductor functional structure, forming a passivation layer or an insulating layer on the rewiring layer, and then forming an opening on the passivation layer or insulating layer. window area to expose part of the rewiring layer, forming two types of pads placed side by side.
- the rewiring layer can play the role of adjusting the pad position in the semiconductor device, and can also play the role of enhancing the power supply network of the power ground.
- first type of pad In the windowing method of the redistribution layer, two types of pads are usually provided, namely the first type of pad and the second type of pad; among them, the first type of pad is used for probe stuck pin testing, and the second type of pad is used for probe stuck test.
- Type II pads are used to lead out bonding wires on the pads. Due to physical isolation requirements and considering that the machine has a limited identification area for the first type of liner and the second type of liner, a partition is generally set up between the first type of liner and the second type of liner that are arranged side by side. wall, as shown in Figure 1.
- the semiconductor functional structure 101 is sequentially stacked with an isolation layer 102 , a redistribution layer 103 covering the isolation layer 102 , and an insulation layer 104 covering the redistribution layer 103 ; wherein, after part of the insulation layer 104 is removed , a portion of the redistribution layer 103 is exposed, and the exposed portion of the redistribution layer 103 includes a first type of pad 105 and a second type of pad 106; wherein, one of the first type of pad 105 and the second type of pad 106 There is a partition wall 107 between them.
- the probe card needle may directly hit the side wall.
- the high height of the side wall will increase the probability of damage to the probe card; at the same time, the side wall can also easily contaminate the needle with impurities (such as dielectric materials), thereby affecting the test results; in addition, after the probe card destroys the partition wall, The performance of the second type of pad 106 may also be affected, thereby affecting the operation of the semiconductor functional structure.
- embodiments of the present disclosure provide a packaging structure, a manufacturing method thereof, and a semiconductor device, wherein the packaging structure includes: a rewiring layer, and the rewiring layer Electrically connected to the interconnection layer of the semiconductor functional structure; an insulating layer covers and exposes part of the redistribution layer; the exposed part of the redistribution layer includes at least one first pad; wherein, the first The pad includes a first area and a second area that are continuously arranged; the first area is used for testing; and the second area is used for performing functional interaction corresponding to the content of the test.
- the packaging structure includes:
- a substrate (not shown in Figure 2a).
- the constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (SOI) or germanium on insulator (SOI). Germanium on Insulator, GOI).
- a semiconductor functional structure 200 is located above the substrate.
- the semiconductor functional structure 200 includes a semiconductor functional layer 201 and an interconnection layer 202 located on the semiconductor functional layer 201.
- the interconnection layer 202 is used to extract electrical signals from the functional structures in the semiconductor functional layer 201 to run the functional structures.
- the interconnect layer 202 includes a top metal layer, which is used not only to extract electrical signals from the functional structure, but also to support the semiconductor functional structure 200 .
- the isolation layer 203 covers the surface of the interconnection layer 202 and is used to isolate the interconnection layer 202 and the subsequently formed rewiring layer 205 in some areas.
- a via hole 204 is provided in the isolation layer 203, and the via hole 204 exposes a portion of the interconnection layer 202.
- the shape of the via hole 204 may be cylindrical, inverted trapezoidal, or any suitable shape; the composition material of the isolation layer 203 includes but is not limited to tetraethylorthosilicate (TEOS).
- Redistribution layer 205 covers the surface of the isolation layer 203 and the sidewalls and bottom of the via hole 204, and part of the redistribution layer 205 is connected to the exposed part of the interconnection layer 202, It is used to lead out the electrical signals of the interconnection layer 202.
- the constituent material of the redistribution layer 205 includes but is not limited to metal; preferably, the material of the redistribution layer is aluminum (Al).
- the thickness of the redistribution layer 205 on the exposed portion of the interconnection layer 202 and the thickness of the redistribution layer 205 on the surface of the isolation layer 203 may be the same.
- the diameter width of the via hole 204 is greater than twice the thickness of the redistribution layer 205 .
- the redistribution layer 205 covers the sidewalls and bottom of the via hole 204 , and the redistribution layer 205 is surrounded by a groove 206 .
- the insulating layer 207 covers the surface of the redistribution layer 205. On the one hand, it can be used to isolate the electrical connection between the redistribution layer 205 and other conductive materials. On the other hand, it can be used to protect the redistribution layer 205 from being destroy.
- the material of the insulating layer 207 includes but is not limited to polyimide (PI).
- the insulating layer 207 is also filled into the groove 206 .
- the hardness of the material of the insulating layer 207 is less than the hardness of the material of the redistribution layer 205 . In this way, the stress of the packaging structure can be reduced and the reliability of the packaging structure can be increased.
- part of the insulating layer 207 is removed, and the exposed part of the redistribution layer 205 includes a first pad 208; wherein the first pad 208 includes a continuously arranged first region 2081 and a first pad 208.
- the first area 2081 is used for probe testing; the second area 2082 is used for drawing out bonding wires.
- the first area 2081 and the second area 2082 are continuously arranged, that is, there is no partition wall between the first area 2081 and the second area 2082.
- a partition wall 107 is provided between the first type of liner 105 and the second type of liner 106.
- This embodiment of the present disclosure can ensure an area for testing and for execution. On the premise that the functional interaction areas corresponding to the test content are physically separated, it can avoid damage to the probe card caused by the partition wall when the probe is not aimed when performing the test, thus prolonging the life of the probe card. service life; at the same time, it reduces the generation of impurities, which is beneficial to improving test accuracy; in addition, it reduces damage to partition walls by probe cards, thereby improving the overall reliability of the packaging structure.
- the first type of gasket 105 in the related art corresponds to the first region 2081 in the embodiment of the present disclosure, and the functions and areas of the two may be the same; the second type of gasket 106 corresponds to the first region 2081 in the embodiment of the present disclosure.
- the second area 2082 corresponds to the second area 2082, and the functions and areas of the two areas can be the same.
- the area of the first area 2081 and the area of the second area 2082 may be the same or different.
- the area of the first area 2081 is the same as the area of the second area 2082.
- the exposed portion of the redistribution layer may only include the second pad.
- the second pad can be used for probe testing and for drawing out bonding wires.
- the package structure further includes: a plurality of second pads 209, composed of the exposed portions of the rewiring layer 205 of the insulation layer, used for testing or for performing the related work. Functional interaction corresponding to the content of the test; wherein at least some of the second pads 209 among the plurality of second pads 209 are arranged side by side with the at least one first pad 208 along a first direction, and the first direction A direction perpendicular to the first area and pointing to the second area; the area of each first pad is larger than the area of each second pad.
- the first direction may be the X-axis direction or the Y-axis direction; the second direction may be the Y-axis direction or the X-axis direction; it should be noted that when the first direction is the X-axis direction, the second direction is the Y-axis direction Axis direction; when the first direction is the Y-axis direction, the second direction is the X-axis direction.
- the first direction is the X-axis direction and the second direction is the Y-axis direction as an example for explanation.
- a plurality of second pads 209 and at least one first pad 208 may be formed in the same process.
- the partition wall between the first type liner and the second type liner in the related art is removed, so that the area of the first liner 208 is greater than or equal to the first type liner.
- the area of the first type of pad and the second type of pad is the maximum area that the machine can locate by identifying its edges. This leads to the possibility that the machine does not The method is to accurately locate the first pad 208 by identifying its edges.
- both testing and wiring require high-precision positioning.
- the identification range of the test machine is: from the center point to 50um around. It is necessary to find the surrounding edges of the window within the scope, that is, the edge of the liner; and the first liner in the embodiment of the present disclosure can be in a strip shape, and at least one side length is due to the superposition of two liner in the related art ( The lengths of the first type of liner and the second type of liner are likely to exceed the above identification range, making it impossible for the test machine to find the edge of the first liner within the existing identification accuracy range, thus causing the first liner to Positioning failed.
- the packaging structure includes at least one first pad and a plurality of second pads.
- the first pad and the plurality of second pads are positioned such that both areas of the first pad can be successfully positioned.
- the first liner and the second liner are both elongated; the width of the first liner along the first direction is different from the width of the second liner along the first direction.
- the width in the first direction is the same; the spacing between two adjacent pads is equal; and one end of all pads arranged side by side along the first direction is flush.
- the strip shape includes general rectangle (length and width are different) and square (length and width are the same).
- the shape of each first pad 208 and each second pad 209 is generally rectangular; in other embodiments, the shape of each second pad 209 is is a square, and the shape of each first pad 208 is generally a rectangle.
- each first pad 208 along the first direction is the same as the width of each second pad 209 along the first direction; the length of each first pad 208 along the second direction is greater than The length of each second pad 209 along the second direction.
- the equal spacing between two adjacent pads can be understood as: the spacing between two adjacent first pads, the spacing between adjacent first pads and the second pads. , and the spacing between two adjacent second pads is equal.
- the fact that one end of all the pads arranged side by side along the first direction are flush can be understood to mean that one end of all the first pads and all the second pads arranged side by side along the first direction are flush. For example, one end of all first pads and all second pads arranged side by side along the first direction are flush close to the edge of the semiconductor functional structure.
- the number of the first pads includes a plurality of first pads, and at least some of the first pads among the plurality of first pads are arranged side by side in a first direction close to the first semiconductor functional structure. At the position of the edge; at least some of the second pads among the plurality of second pads are arranged side by side along the first direction on both sides of the plurality of first pads.
- the number of the first pads 208 may include multiple, and the plurality of first substrates are disposed near the middle position of the first edge of the semiconductor functional structure; the second pads The number 209 may include multiple, and the plurality of second pads 209 are respectively disposed on both sides of the plurality of first pads 208 .
- the identification of the two areas in the first pad 208 can be assisted by the second pads 209 located on both sides. specifically:
- the area of the second pad 209 is similar to the area of the first type pad or the second type pad in the related art.
- the second pad 209 is within the identification range of the testing machine, and the testing machine can The position (four edges) of each second pad 209 is accurately identified.
- the first liner 208 and the second liner 209 are both elongated in shape, have the same width, have one end flush, and the spacing between two adjacent pads is equal, by Using the positions of the second pads 209 on both sides as a reference, the predicted position of the area (first area or second area) close to the alignment end of each first pad 208 can be obtained.
- the width direction of the first pad 208 (i.e., the first direction) is within the identification range of the testing machine, and combined with the identification in the width direction, the area close to the alignment end of each first pad 208 can be accurately identified. After accurately identifying an area of the first pad 208, the center point of the first area can be obtained. Considering that the two areas of the first pad are continuously arranged, share a long side, and the length of the first pad is The length of the side is constant.
- the center point of the first area is moved a fixed distance to the second direction perpendicular to the first direction, it can be considered as the center point of another area in the first pad 208 away from the aligned end, thus also Another area of the first pad 208 remote from the aligned end is further identified.
- one end of all the pads arranged side by side in the first direction and close to the edge of the semiconductor function structure is flush; the first region is located at both ends of the first pad close to the semiconductor function structure. One end of the structure edge, the second region is located at one end of the two ends of the first pad away from the edge of the semiconductor functional structure. That is to say, the first area 2081 of the first pad can be identified first by relying on the second pads 209 located on both sides, and then the second area 2082 can be identified using the first area 2081.
- the edge of a semiconductor functional structure when used to describe the positional relationship between different areas in the first pad or the positional relationship between the first pad and the second pad, the edge refers to a plurality of semiconductor functional structures.
- the edge to which the first liner is close is, more specifically, the edge to which the first liner is close to among the two edges opposite in the second direction; correspondingly, later in the description of the second pad using semiconductor functional structure edges
- the edge refers to the edge where the second pad is close to among the multiple edges of the semiconductor functional structure.
- one end of all pads arranged side by side along the first direction away from the edge of the semiconductor functional structure is flush, and the second region is located in the first pad close to the edge of the semiconductor functional structure. At one end of the first pad, the first region is located at an end of the first pad away from the edge of the semiconductor functional structure.
- arranging the second region 2082 at one end of the two ends of the first pad 208 close to the edge of the semiconductor functional structure is beneficial to shortening the length of the bonding wire welded to the second region 2082 and increasing the bonding efficiency. Craft window.
- At least two of said second liners are included on each side of said plurality of first liners.
- the plurality of first pads 208 has a first side and a second side; wherein the first side of the first pad 208 and the second side of the first pad 208 are opposite sides. .
- the direction in which the first side points to the second side is parallel to the X-axis direction.
- the number of the first pads 208 includes 6, and the number of the second pads 209 includes 10; 6 first pads 208 and 10 second pads 208.
- the pads 209 are arranged side by side along the side and second side.
- the number of second pads 209 located on both sides of the first pad 208 may include one or more.
- the identification of the first area and the second area in the first pad 208 can be assisted.
- the second liner 209 located at the edge on both sides away from the first liner 208 is easily damaged, such as being cut, worn, etc. Therefore, two or more second pads 209 are provided on both sides of the first pad 208; in this way, even if one second pad 209 at the edge is damaged, the remaining one can be ensured to be utilized.
- the undamaged second pad 209 enables precise positioning of the first pad.
- first pads there is a first number of second pads on a first side of the plurality of first pads 208 and a second number of second pads on a second side of the plurality of first pads, so
- the first quantity and the second quantity may be the same or different.
- Figure 3a shows the case where the first quantity is the same as the second quantity
- Figure 3b shows the case where the first quantity and the second quantity are different.
- the first pads may also be located in the middle area in the first direction, that is, the leftmost side of the plurality of first pads and the left side of the semiconductor functional structure
- the spacing between edges is equal to the spacing between the rightmost edge of the plurality of first pads and the right edge of the semiconductor functional structure.
- a part of the second pads are arranged side by side on both sides of the plurality of first pads along the first direction, and another part of the second pads in the plurality of second pads Arranged side by side along the second direction close to the second edge of the semiconductor functional structure; the second direction is perpendicular to the first direction; the first edge and the second edge are the semiconductor functional structure Opposite edges.
- first pads 208 and 12 second pads 209 are provided on the semiconductor functional structure 200; wherein, near the first edge 20a of the semiconductor functional structure, 8 first pads 208, and 4 second pads 209 are respectively provided on both sides of the 8 first pads 208 (a total of 8 second pads).
- Four second pads are provided near the second edge 20b of the semiconductor functional structure; and the four second pads are arranged side by side along the Y-axis direction.
- Figure 3c is based on Figure 3a and adds a plurality of semiconductor functional structures arranged along the second direction (along the Y-axis direction) near the second edge 20b of the semiconductor functional structure. a plurality of second pads 209.
- the area of the plurality of second pads 209 arranged side by side along the Y-axis direction is within the identification range of the testing machine, and the testing machine can accurately identify the position of each second pad 209 (fourth). edge), based on this, a plurality of second pads 209 arranged side by side along the Y-axis direction can be used to obtain an accurate second direction, so that the identified first area is moved a fixed distance to the second direction to identify In the second area, more accurate movement in the second direction is achieved, thereby achieving more accurate positioning of the second area.
- the plurality of second pads 209 arranged along the second direction shown in FIG. 3c are rotated 90 degrees clockwise compared to the plurality of second pads 209 arranged along the first direction.
- the placement direction of the plurality of second pads 209 arranged along the second direction can also be completely consistent with the placement direction of the plurality of second pads 209 arranged along the first direction, without making a 90-degree angle. It can be understood that a 90-degree rotation is more conducive to saving the area for placing pads.
- the number of the first pads includes multiple, a part of the first pads are arranged side by side along the first direction close to the first edge of the semiconductor functional structure, and the other part of the first pads are arranged side by side along the first direction.
- a pad is juxtaposed along the first direction close to the second edge of the semiconductor functional structure; a part of the second pad is juxtaposed on both sides of a part of the first pad along the first direction, Another part of the second pad is arranged side by side on both sides of the other part of the first pad along the first direction; the first edge and the second edge are two opposite sides of the semiconductor functional structure. edge.
- 20 first pads 208 and 12 second pads 209 are provided on the semiconductor functional structure 200; wherein, near the first edge 20a of the semiconductor functional structure, There are 10 first pads 208, and 3 second pads 209 are respectively provided on both sides of the 10 first pads 208 (a total of 6 second pads). Ten first pads 208 are also provided near the second edge 20b of the semiconductor functional structure, and three second pads 209 are respectively provided on both sides of the ten first pads 208 (a total of 6 second pads).
- the arrangement of the first liner and the second liner located near the first edge of the semiconductor functional structure is consistent with the arrangement of the first liner located near the second edge of the semiconductor functional structure.
- the pad and the second pad are arranged symmetrically.
- the symmetry may be understood to mean that the pad located at the first edge position is mirrored in the first direction relative to the pad located at the second edge position.
- 10 first pads 208 and 6 second pads 209 located close to the first edge 20a of the semiconductor functional structure are arranged side by side along the X-axis direction;
- the 10 first pads 208 and 6 second pads 209 at the second edge 20b of the structure are arranged side by side along the X-axis direction; here, all the pads at the first edge 20a and the second edge 20b are All pads are set to a symmetrical structure, which can save process flow and improve production efficiency.
- the first area and the second area of the corresponding first pad 208 can be identified from the first edge and the second edge respectively, if The two first pads corresponding to the first edge and the second edge are identified, and the connecting direction of the two corresponding first areas is parallel to the second direction, which further illustrates that the identification of both sides is accurate.
- the arrangement of the first pad and the second pad located close to the first edge of the semiconductor functional structure is consistent with the arrangement of the first pad located close to the second edge of the semiconductor functional structure.
- the arrangement of the pad and the second pad is asymmetric.
- the asymmetry may be understood to mean that the pad located at the first edge position is not arranged as a mirror image in the first direction relative to the pad located at the second edge position.
- all pads at the first edge 20a position and all pads at the second edge 20b position are set into an asymmetric structure; specifically, near the semiconductor functional structure At the position of the first edge 20a, 10 first pads are provided, and 3 second pads 209 are provided on each of the first and second sides of the 10 first pads; close to the semiconductor functional structure At the position of the second edge 20b, 10 first pads are set, and 4 second pads 209 are set on the first side of the 10 first pads, and 2 second pads are set on the second side. MAT 209. In this way, all the pads located at the first edge 20a and all the pads located at the second edge 20b are arranged in an asymmetric structure.
- the pad at the first edge position is asymmetrically arranged with the pad at the second edge position
- the first area 2081 and the second area 2082 of the corresponding first pad 208 are respectively identified from the first edge and the second edge.
- situation can determine whether errors may occur in the recognition results. For example, the situations in which the first area 2081 and the second area 2082 of the corresponding first pad 208 are respectively identified from the first edge and the second edge should be different. If the conditions of the first pads on both sides are detected at this time, are the same, it can be judged that at least one side of the two edge recognition situations is wrong.
- first pads and second pads in Figures 3a, 3b, 3c, 3d, and 3e for example, 4, 6, 8, 10, 20, etc.
- description of the number of first pads and second pads in Figures 3a, 3b, 3c, 3d, and 3e is only used to schematically illustrate the present disclosure and is not intended to limit the scope of the present disclosure.
- a semiconductor device including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the disclosure.
- an embodiment of the present disclosure provides a method for manufacturing a packaging structure, which is used to form the packaging structure in the above embodiment;
- FIG. 4 is a schematic flow chart of the manufacturing method of the packaging structure provided by an embodiment of the present disclosure. .
- the manufacturing method of the packaging structure provided by the embodiment of the present disclosure includes the following steps:
- Step S401 Form a redistribution layer on the semiconductor functional structure, and the redistribution layer is electrically connected to the interconnection layer on the semiconductor functional structure;
- Step S402 Form an insulating layer on the surface of the redistribution layer
- Step S403 Remove part of the insulating layer to expose part of the redistribution layer and form at least one first pad; each first pad is a part of the rewiring exposed by the insulating layer. layer composition;
- the first pad includes a first area and a second area arranged continuously; the first area is used for testing, and the second area is used for performing functional interaction corresponding to the content of the test.
- 5a to 5c are schematic cross-sectional views of a manufacturing process of a packaging structure provided by an embodiment of the present disclosure. The manufacturing method of the packaging structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 4 and FIG. 5a to FIG. 5c.
- step S401 a rewiring layer is formed.
- forming the redistribution layer includes: providing a substrate (not marked in Figure 5a); forming a semiconductor functional structure 500 on the substrate; forming a redistribution layer 505 on the semiconductor functional structure 500.
- forming a semiconductor functional structure on the substrate includes: forming a semiconductor functional layer 501 on the substrate; and forming an interconnect layer 502 on the semiconductor functional layer 501.
- the interconnect can be formed on the semiconductor functional layer 501 by physical vapor deposition (PVD, Physical Vapor Deposition), chemical vapor deposition (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition), etc. Connected layer 502.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- ALD Atomic Layer Deposition
- an isolation layer 503 is formed on the interconnection layer; the isolation layer 503 is used to protect the interconnection layer 502 from damage.
- the composition material of the isolation layer 503 includes but is not limited to tetraethylorthosilicate (TEOS).
- TEOS tetraethylorthosilicate
- the method of forming the isolation layer 503 includes but is not limited to PVD, CVD, ALD and other processes.
- part of the isolation layer 503 is removed, so that there are a plurality of vias 504 in the isolation layer 503, and the vias 504 expose part of the interconnection layer 502; the exposed part of the interconnection Layer 502 serves as a region where the rewiring layer 505 and the interconnection layer 502 are electrically connected.
- the shape of the via hole 504 may be cylindrical, inverted trapezoidal, or any suitable shape.
- a redistribution layer 505 is formed on the surface of the isolation layer 503 and in the via hole 504 , wherein the redistribution layer 505 is electrically connected to the interconnection layer 502 .
- the specific method of forming the rewiring layer 505 on the isolation layer 503 includes: forming a new conductor pattern on the isolation layer 503 by exposure and development, and then using electroplating technology according to The new conductor patterns form a redistribution layer 505 that includes new conductor paths that are electrically connected to the interconnection layer 502 .
- the constituent material of the redistribution layer 505 includes but is not limited to metal; preferably, the material of the redistribution layer is aluminum (Al).
- the thickness of the redistribution layer on the exposed portion of the interconnection layer 502 and the thickness of the redistribution layer on the surface of the isolation layer 503 may be the same.
- the diameter width of the via hole 504 is greater than twice the thickness of the redistribution layer.
- the redistribution layer 505 covers the sidewalls and bottom of the via hole 504 , and the redistribution layer 505 is surrounded by a groove 506 .
- step 402 referring to FIG. 5b, an insulating layer 507 is formed on the surface of the redistribution layer 505.
- the insulating layer 507 covers the surface of the redistribution layer 505. On the one hand, it can be used to isolate the electrical connection between the redistribution layer 505 and other conductive materials. On the other hand, it can be used to protect the redistribution layer 505 from being damaged.
- the material of the insulating layer 507 includes but is not limited to polyimide (PI).
- the method of forming the first insulating layer 507 includes but is not limited to PVD, CVD, ALD and other processes.
- the insulating layer 507 is also filled in the groove 506 surrounded by the redistribution layer 505 .
- the hardness of the material of the insulating layer 507 is less than the hardness of the material of the rewiring layer 505 , which can reduce the stress of the packaging structure and increase reliability.
- step 403 referring to Figure 5c, at least one first liner 508 is formed.
- each first pad 508 includes a first area 5081 and a second area 5082 arranged continuously; the first area 5081 is used for testing, and the second area 5082 is used for performing the test. Functional interaction corresponding to the content.
- At least one first pad is provided on the semiconductor functional structure, wherein each first pad includes a first area for performing testing, and a first area for performing the test.
- the second area for functional interaction corresponding to the content; the first area and the second area are set up continuously, in other words, there is no partition wall between the first area and the second area.
- the disclosed devices and methods can be implemented in a non-target manner.
- the device embodiments described above are only illustrative.
- the division of the units is only a logical function division.
- the components shown or discussed are coupled to each other, or directly coupled.
- the units described above as separate components may or may not be physically separated.
- the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
- each first pad includes a first area for performing a test, and a first area for performing a test corresponding to the content of the test.
- the second area for functional interaction; the first area and the second area are set up continuously, in other words, there is no partition wall between the first area and the second area.
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Abstract
本公开实施例提出了一种封装结构及其制作方法、半导体器件,所述封装结构包括:重布线层,所述重布线层与半导体功能结构的互连层电性连接;绝缘层,覆盖且暴露出部分所述重布线层;被暴露出的部分所述重布线层包括至少一个第一衬垫;其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试;所述第二区域用于执行与所述测试的内容对应的功能交互。
Description
相关的交叉引用
本公开基于申请号为202210621334.5、申请日为2022年06月01日、发明名称为“封装结构及其制作方法、半导体器件”的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本公开作为参考。
本公开涉及半导体技术领域,涉及但不限于封装结构及其制作方法、半导体器件。
随着电子设备普及率快速提升、电子设备市场的蓬勃发展,越来越要求电子产品在具有高性能、多功能、高可靠性以及便捷性的同时要向着小型化、薄型化的方向演进。这样的需求对半导体器件的封装提出了更好、更轻、更薄、封装密度更高、更好的电性能和热性能、更高的可靠性以及更高的性价比要求。
为保证半导体器件的性能满足对应要求,需要在封装结构上制备用于测试和执行功能交互的端口。
发明内容
鉴于此,为解决相关技术问题中的一个或多个,本公开实施例提出了封装结构及其制作方法、半导体器件。
根据本公开实施例,提供了一种封装结构,包括:
重布线层,所述重布线层与半导体功能结构的互连层电性连接;
绝缘层,覆盖且暴露出部分所述重布线层;
被暴露出的部分所述重布线层包括至少一个第一衬垫;其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试;所述第二区域用于执行与所述测试的内容对应的功能交互。
上述方案中,所述封装结构还包括:多个第二衬垫,由所述绝缘层暴露出的部分所述重布线层构成,用于进行测试或者用于执行与所述测试的内容对应的功能交互;
其中,多个所述第二衬垫中至少部分第二衬垫与所述至少一个所述第一衬垫沿第一方向并列设置,所述第一方向垂直于所述第一区域指向所述第二区域的方向;每一所述第一衬垫的面积大于每一所述第二衬垫的面积。
上述方案中,所述第一衬垫与所述第二衬垫均为长条状;所述第一衬垫沿所述第一方向上的宽度与所述第二衬垫沿所述第一方向上的宽度相同;相邻的两个衬垫间的间距相等;沿第一方向并列设置的所有衬垫的一端平齐。
上述方案中,所述第一衬垫的数量包括多个,至少部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处;至少部分所述第二衬垫沿所述第一方向并列设置在所述多个第一衬垫的两侧。
上述方案中,在所述多个第一衬垫每一侧至少包括两个所述第二衬垫。
上述方案中,在所述多个第一衬垫的第一侧具有第一数量的所述第二衬垫,在所述多个第一衬垫的第二侧具有第二数量的所述第二衬垫,所述第一数量与所述第二数量不同。
上述方案中,一部分所述第二衬垫沿第一方向并列设置在所述多个第一衬垫的两侧,另一部分所述第二衬垫沿第二方向并列设置在靠近所述半导体功能结构第二边缘的位置处;所述第二方向和所述第一方向垂直;所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘。
上述方案中,所述第一衬垫的数量包括多个,一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处,另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处;一部分所述第二衬垫沿所述第一方向并列设置在一部分所述第一衬垫的两侧,另一部分所述第二衬垫沿所述第一方向并列设置在另一部分所述第一衬垫的两侧;所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘。
上述方案中,位于靠近所述半导体功能结构第一边缘的位置处的所述第一衬垫和所述第二衬垫的排布与位于靠近所述半导体功能结构第二边缘的位置处的所述第一衬垫和所述第二衬垫的排布为对称设置。
上述方案中,沿第一方向并列设置的所有衬垫靠近所述半导体功能结构边缘的一端平齐;
所述第一区域位于所述第一衬垫中靠近所述半导体功能结构边缘的一端,所述第二区域位于所述第一衬垫中远离所述半导体功能结构边缘的一端。
根据本公开实施例,又提供了一种半导体器件,包括:半导体功能结构及如本公开上述多个实施例中任一项所述的封装结构。
根据本公开实施例,还提供了一种封装结构的制作方法,所述方法包括:
在半导体功能结构上形成重布线层,所述重布线层与所述半导体功能结构上的互连层电性连接;
在所述重布线层的表面形成绝缘层;
去除部分所述绝缘层,以暴露出部分所述重布线层,形成至少一个第 一衬垫;每一所述第一衬垫均由所述绝缘层暴露出的部分所述重布线层构成;
其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试,所述第二区域用于执行与所述测试的内容对应的功能交互。
本公开各实施例中,通过在半导体功能结构上设置至少一个第一衬垫,其中,每个第一衬垫包括用于执行测试的第一区域,以及用于执行与所述测试的内容对应的功能交互的第二区域;第一区域与第二区域之间连续设置,换言之,第一区域和第二区域之间未设置隔墙。如此,在保证用于测试的区域和用于执行与测试内容对应的功能交互的区域在物理上存在区分的前提下,能够在执行测试时,避免探针出现未瞄准的情况下,隔墙对探针卡造成的损伤,从而延长了探针卡的使用寿命;同时,减少杂质的产生,从而提高了测试效率;另外,减少探针卡对隔墙的破坏,进而从整体上提高了封装结构的可靠性。
图1为本公开实施例中提供的一种封装结构的剖面结构示意图;
图2a为本公开实施例中提供的另一种封装结构的剖面结构示意图;
图2b为本公开实施例中提供的又一种封装结构的剖面结构示意图;
图3a-图3e为本公开实施例提供的几种第一衬垫与第二衬垫的相对位置关系示意图;
图4为本公开实施例中提供的封装结构的制造方法的流程示意图;
图5a-图5c为本公开实施例中提供的一种封装结构的制造过程的剖面示意图。
附图标记说明
101-半导体功能结构;102-隔离层;103-重布线层;104-绝缘层;105-第一类衬垫;106-第二类衬垫;107-隔墙;200-半导体功能结构;201-半导体功能层;202-互连层;203-隔离层;204-过孔;205-重布线层;206-凹槽;207-绝缘层;208-第一衬垫;2081-第一衬垫的第一区域;2082-第一衬垫的第二区域;209-第二衬垫;500-半导体功能结构;501-半导体功能层;502-互连层;503-隔离层504-过孔;505-重布线层;506-凹槽;507-绝缘层;508-第一衬垫;5081-第一衬垫的第一区域;5082-第一衬垫的第二区域;509-第二衬垫。
在上述附图(其不一定是按比例绘制的)中,相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻的理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开各实施例。根据下面说明和权利要求书,本公开的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是,本公开的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读,以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义,而且还包括在某物“上”且其间有居间特征或层的含义。
在本公开实施例中,术语“A与B相连”包含A、B两者直接接触的情形,或者A和B通过中间导电结构间接接触的情形。
在本公开实施例中,术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。
在本公开实施例中,术语“层”是指包括具有厚度的区域的材料部分。层可以在结构的下方表面或上方表面延伸,其面积可以小于等于所在的延伸表面。
需要说明的是,本公开实施例所记载的技术方案之间,在不冲突的情况下,可以任意组合。
本公开实施例涉及的半导体功能结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里,所述最终的器件可以包括存储器。
在半导体器件如,动态随机存取存储器(DRAM,Dynamic Random Access Memory)的封装结构的设计中,一种衬垫(还可以被称为焊盘,英文表达为PAD)的设计方式是重布线层(RDL,Redistribution Layer)开窗的方式。
所述重布线层开窗是指在半导体功能结构的顶层金属层上形成重布线层,在重布线层上形成钝化层或绝缘层,然后,在所述钝化层或绝缘层上形成开窗区域,以暴露部分重布线层,形成并列设置的两个类型的衬垫。这里,重布线层在半导体器件中可以起到调整衬垫位置的作用,还能起到增强电源地的供电网络的作用。
在重布线层的开窗方式中,通常设置有两个类型的衬垫,即第一类衬垫和第二类衬垫;其中,第一类衬垫用于进行探针卡扎针测试,第二类衬垫用于在该衬垫上进行键合线(Bonding wire)的引出。出于物理隔离需求, 同时考虑到机台对第一类衬垫与第二类衬垫的识别区域有限,一般会在并列排布的第一类衬垫与第二类衬垫之间设置隔墙,如图1所示。
示例性的,参考图1,半导体功能结构101上依次堆叠设置有隔离层102、覆盖隔离层102的重布线层103、覆盖重布线层103的绝缘层104;其中,部分绝缘层104被去除后,暴露出部分重布线层103,被暴露的部分所述重布线层103包括第一类衬垫105和第二类衬垫106;其中,第一类衬垫105和第二类衬垫106之间设置有隔墙107。
然而,在探针卡与第一类衬垫的对准过程中,当探针卡与第一类衬垫的中心点出现偏移时,探针卡扎针可能会直接打在侧墙上。侧墙高度较高,会增加探针卡的损坏机率;同时,侧墙也容易使扎针上沾染杂质(例如介质材料),从而影响测试的结果;另外,在探针卡破坏了隔墙后,第二类衬垫106的性能也可能会受到影响,进而对半导体功能结构的运行产生影响。
鉴于此,为解决上述问题中的一个或多个,本公开实施例提供了一种封装结构及其制作方法、半导体器件,其中,所述封装结构,包括:重布线层,所述重布线层与半导体功能结构的互连层电性连接;绝缘层,覆盖且暴露出部分所述重布线层;被暴露出的部分所述重布线层包括至少一个第一衬垫;其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试;所述第二区域用于执行与所述测试的内容对应的功能交互。
具体地,参考图2a,所述封装结构包括:
基底(图2a中未示出),所述基底的组成材料可以包括硅(Si)、锗(Ge)、锗化硅(SiGe)、绝缘体上硅(Silicon on Insulator,SOI)或者绝缘体上锗(Germanium on Insulator,GOI)。
半导体功能结构200,所述半导体功能结构200位于基底上方。具体地,所述半导体功能结构200包括半导体功能层201和位于所述半导体功能层201上的互连层202,根据实际需求,在所述半导体功能层201中可以设置多种功能结构;相应地,所述互连层202用于将半导体功能层201中功能结构的电信号引出,以运行所述功能结构。在一些实施例中,互连层202包括顶层金属层,顶层金属层不仅用于将功能结构的电信号引出,还用于支撑半导体功能结构200。
隔离层203,覆盖互连层202表面,用于在部分区域隔离互连层202和后续形成的重布线层205。隔离层203中设置有过孔204,过孔204暴露部分互连层202。其中,过孔204的形状可以是圆柱形,也可以是倒梯形,或者是任何合适的形状;隔离层203的组成材料包括但不限于正硅酸乙酯(TEOS)。
重布线层205,所述重布线层205覆盖所述隔离层203的表面上和所述过孔204的侧壁和底部,部分重布线层205与被暴露的部分所述互连层202 连接,用于将互连层202的电信号引出。其中,所述重布线层205的组成材料包括但不限于金属;优选地,所述重布线层的材料为铝(Al)。
需要说明的是,被暴露的部分所述互连层202上的重布线层205的厚度与隔离层203表面上的重布线层205的厚度可以相同。在一些实施例中,过孔204的径宽大于两倍重布线层205的厚度,此时,重布线层205覆盖过孔204的侧壁和底部,重布线层205围成有凹槽206。绝缘层207,所述绝缘层207覆盖重布线层205的表面,一方面可以用于隔离重布线层205与其他导电材料之间的电连接,另一方面可以用于保护重布线层205不被破坏。所述绝缘层207的材料包括但不限于聚酰亚胺(PI)。
这里,所述绝缘层207还填充至凹槽206内。
在一些实施例中,所述绝缘层207的材料的硬度小于所述重布线层205的材料的硬度,如此,可以减小封装结构的应力,增加封装结构的可靠性。
这里,所述绝缘层207的部分区域被去除,被暴露出的部分所述重布线层205包括第一衬垫208;其中,所述第一衬垫208包括连续设置的第一区域2081和第二区域2082;所述第一区域2081用于进行测试;所述第二区域2082用于执行与所述测试的内容对应的功能交互。在一些具体实施例中,所述第一区域2081用于探针测试;所述第二区域2082用于引出键合线。
参考图2a,第一区域2081和第二区域2082之间是连续设置的,即第一区域2081和第二区域2082之间并未设置隔墙。这样,相较于相关技术中,参考图1,在第一类衬垫105和第二类衬垫106之间设置隔墙107,本公开实施例可以在保证用于测试的区域和用于执行与测试内容对应的功能交互的区域在物理上存在区分的前提下,能够在执行测试时,避免探针出现未瞄准的情况下,隔墙对探针卡造成的损伤,从而延长探针卡的使用寿命;同时,减少杂质的产生,有利于提升测试准确性;另外,减少探针卡对隔墙的破坏,进而从整体上提高了封装结构的可靠性。
需要说明的是,相关技术中的第一类衬垫105与本公开实施例中的第一区域2081对应,二者的功能和面积可以相同;第二类衬垫106与本公开实施例中的第二区域2082对应,二者的功能和面积可以相同。这里,所述第一区域2081的面积与第二区域2082的面积可以相同也可以不同。优选地,所述第一区域2081的面积与第二区域2082的面积相同。
需要说明的是,在另一些实施例中,还可能存在能够支持在同一片开窗区域上,先经过探针卡扎针测试,再到封装厂进行键合线封装,而不影响封装打线的成品率的问题。换言之,被暴露出的部分所述重布线层还可以仅包括第二衬垫。其中,第二衬垫既可以用于探针测试,也可以用于引出键合线。
在一些具体实施例中,参考图2b,所述封装结构还包括:多个第二衬垫209,由绝缘层暴露的部分所述重布线层205构成,用于进行测试或者用 于执行与所述测试的内容对应的功能交互;其中,多个所述第二衬垫209中至少部分第二衬垫209与所述至少一个第一衬垫208沿第一方向并列设置,所述第一方向垂直于所述第一区域指向所述第二区域的方向;每一所述第一衬垫的面积大于每一所述第二衬垫的面积。
这里,所述第一方向可以为X轴方向或者Y轴方向;第二方向可以为Y轴方向或者X轴方向;需要说明的是,在第一方向为X轴方向时,第二方向为Y轴方向;在第一方向为Y轴方向时,第二方向为X轴方向。为了便于清楚理解,在本公开实施例中,以第一方向为X轴方向,第二方向为Y轴方向为例进行解释说明。
实际应用中,多个第二衬垫209与至少一个第一衬垫208可以在同一制程中形成。
本实施例中,为了保证测试和打线的质量,去除了相关技术中第一类衬垫和第二类衬垫之间的隔墙,使得第一衬垫208的面积大于等于第一类衬垫和第二类衬垫的面积之和,而相关技术中第一类衬垫和第二类衬垫的面积为机台能够通过识别其边缘进行定位的最大面积,这就导致机台可能没有办法通过识别第一衬垫208的边缘对其进行准确的定位。
示例性的,相关技术中,测试和打线均需要高精度的定位,探针在识别衬垫时,对识别图形的范围有限制,测试机台的识别范围为:由中心点向四周50um的范围内需要找到开窗的四周边缘,即衬垫的边缘;而本公开实施例中的第一衬垫可以为长条状,且至少一边的边长由于叠加了相关技术中两个衬垫(第一类衬垫和第二类衬垫)的长度,较容易超出上述识别范围,使得测试机台在现有的识别精度范围内无法找到第一衬垫的边缘,进而造成第一衬垫的定位失败。
为了能够在现有的识别精度范围内精确地定位第一衬垫208的具***置,本公开的一些实施例中,封装结构包括至少一个第一衬垫和多个第二衬垫,通过合理安排第一衬垫和所述多个第二衬垫的位置,使得第一衬垫的两个区均可以成功定位。
在一些实施例中,所述第一衬垫与所述第二衬垫均为长条状;所述第一衬垫沿所述第一方向上的宽度与所述第二衬垫沿所述第一方向上的宽度相同;相邻的两个衬垫间的间距相等;沿第一方向并列设置的所有衬垫的一端平齐。
这里,所述长条状包括一般长方形(长和宽不同)和正方形(长和宽相同)。在一些实施例中,每一所述第一衬垫208及每一所述第二衬垫209的形状均为一般长方形;在另一些实施例中,每一所述第二衬垫209的形状为正方形,每一所述第一衬垫208的形状为一般长方形。
这里,每一第一衬垫208沿第一方向上的宽度与每一第二衬垫209沿第一方向上的宽度相同;每一所述第一衬垫208沿第二方向上的长度大于每一所述第二衬垫209沿第二方向上的长度。
上述实施例中,相邻的两个衬垫间的间距相等可以理解为:相邻的两个第一衬垫之间的间距、相邻的第一衬垫与第二衬垫之间的间距、以及相邻的两个第二衬垫之间的间距均相等。而沿第一方向并列设置的所有衬垫的一端平齐可以理解为,沿第一方向并列设置的所有第一衬垫及所有第二衬垫的一端平齐。示例性的,沿第一方向并列设置的所有第一衬垫及所有第二衬垫靠近所述半导体功能结构边缘的一端平齐。
在一些实施例中,所述第一衬垫的数量包括多个,多个所述第一衬垫中至少部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处;多个所述第二衬垫中至少部分所述第二衬垫沿所述第一方向并列设置在所述多个第一衬垫的两侧。
这里,参考图3a,所述第一衬垫208的数量可以包括多个,多个所述第一衬底设置在靠近所述半导体功能结构第一边缘的中部位置处;所述第二衬垫209的数量可以包括多个,多个所述第二衬垫209分别设置在所述多个第一衬垫208的两侧。
这里,所述第一衬垫208中两个区域的识别可以依靠位于两侧的第二衬垫209来辅助实现。具体地:
前已述及,第二衬垫209的面积与相关技术中第一类衬垫或第二类衬垫的面积类似,第二衬垫209在测试机台的识别范围之内,测试机台可以精准的识别到每个第二衬垫209的位置(四个边缘)。在前述的所述第一衬垫208与所述第二衬垫209形状均为长条状、宽度均相同、一端平齐,且相邻的两个衬垫间的间距相等的前提下,通过两侧的第二衬垫209的位置作为参考,可以得到每个第一衬垫208中靠近所述对齐端的区域(第一区域或第二区域)的预测位置,由于第一衬垫208宽度方向(即第一方向)在测试机台的识别范围之内,结合宽度方向的识别可以准确的识别出每个第一衬垫208中靠近所述对齐端的区域。在准确的识别出第一衬垫208的一个区域后,可以获取到第一区域的中心点,考虑到所述第一衬垫的两个区域连续设置、共用长边且第一衬垫的长边的长度一定,将第一区域的中心点向垂直于第一方向的第二方向移动固定距离,即可认为是第一衬垫208中远离所述对齐端的另一区域的中心点,从而也就进一步识别出第一衬垫208中远离所述对齐端的另一区域。
在一些实施例中,沿第一方向并列设置的所有衬垫的靠近所述半导体功能结构边缘的一端平齐;所述第一区域位于所述第一衬垫的两端中靠近所述半导体功能结构边缘的一端,所述第二区域位于所述第一衬垫的两端中远离所述半导体功能结构边缘的一端。也就是说,这里可以依靠位于两侧的第二衬垫209先识别出第一衬垫的第一区域2081,再利用第一区域2081识别出第二区域2082。
需要说明的是,在利用半导体功能结构边缘描述第一衬垫中不同区域的位置关系或者描述第一衬垫和第二衬垫的位置关系时,其中的边缘指的 是半导体功能结构的多个边缘中第一衬垫靠近的边缘,更具体地,是在第二方向上相对的两个边缘中第一衬垫靠近的边缘;相应地,后续在利用半导体功能结构边缘描述第二衬垫中不同区域的位置关系或第一衬垫和第二衬垫的位置关系时,其中的边缘指的是半导体功能结构的多个边缘中第二衬垫靠近的边缘。
可以理解的是,在第一衬垫208上引出键合线的工艺可控性或可调节性较为灵活,而将第一衬垫208与探针卡对准的工艺难度相对较大,因此,将第一区域2081设置在所述第一衬垫208的两端中靠近半导体功能结构边缘的一侧,有利于降低第一区域2081与探针卡的对准难度,为探针卡在执行测试过程中预留出较高的容错率。
在另一些实施例中,沿第一方向并列设置的所有衬垫的远离所述半导体功能结构边缘的一端平齐,所述第二区域位于所述第一衬垫中靠近所述半导体功能结构边缘的一端,所述第一区域位于所述第一衬垫中远离所述半导体功能结构边缘的一端。此时,同样可以依靠位于两侧的第二衬垫209先识别出第一衬垫的第一区域2081,再利用第一区域2081识别出第二区域2082。
这里,将第二区域2082设置在所述第一衬垫208的两端中靠近半导体功能结构边缘的一端,有利于缩短焊接在第二区域2082上的键合线的长度,增大键合的工艺窗口。
在一些实施例中,在所述多个第一衬垫每一侧至少包括两个所述第二衬垫。
这里,所述多个第一衬垫208具有第一侧和第二侧;其中,所述第一衬垫208的第一侧与所述第一衬垫208的第二侧为相对的两侧。所述第一侧指向所述第二侧的方向与X轴方向平行。
示例性的,参考图3a,所述第一衬垫208的数量包括6个,所述第二衬垫209的数量包括10个;6个所述第一衬垫208与10个所述第二衬垫209沿X轴方向并列设置在靠近所述半导体功能结构200第一边缘20a位置处;并且,10个所述第二衬垫209分别设置在6个所述第一衬垫208的第一侧和第二侧。
需要说明的是,位于第一衬垫208的两侧的第二衬垫209的数量分别可以包括一个或多个。当位于第一衬垫208的两侧分别设置一个第二衬垫209的即可辅助实现第一衬垫208中第一区域和第二区域的识别。然而,在实际的工艺操作中,位于两侧中,远离第一衬垫208一侧的边缘处的第二衬垫209易于被损坏,例如被切割、被磨损等。因此,在第一衬垫208的两侧均设置两个或两个以上第二衬垫209;如此,能够在边缘处的一个第二衬垫209被损坏的情况下,还能保证利用剩余的未被损坏的第二衬垫209实现对第一衬垫的精确定位。
这里,在所述多个第一衬垫208的第一侧具有第一数量的第二衬垫, 在所述多个第一衬垫的第二侧具有第二数量的第二衬垫,所述第一数量与所述第二数量可以相同,也可以不同。图3a中示出的是第一数量与所述第二数量相同的情况,图3b中示出的是第一数量与所述第二数量不相同的情况。此外,需要说明的是,当第一数量与第二数量不同时,第一衬垫也可以位于第一方向的中间区域,即多个第一衬垫的最左侧与半导体功能结构的左侧边缘之间的间距等于多个第一衬垫的最右侧与半导体功能结构的右侧边缘之间的间距。
在另一些实施例中,一部分所述第二衬垫沿第一方向并列设置在所述多个第一衬垫的两侧,所述多个第二衬垫中另一部分所述第二衬垫沿第二方向并列设置在靠近所述半导体功能结构第二边缘的位置处;所述第二方向和所述第一方向垂直;所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘。
示例性的,参考图3c,所述半导体功能结构200上设置有8个第一衬垫208和12个第二衬垫209;其中,在靠近所述半导体功能结构第一边缘20a位置处,设置8个第一衬垫208,以及在所述8个第一衬垫208的两侧分别设置有4个第二衬垫209(共计8个第二衬垫)。在靠近所述半导体功能结构第二边缘20b位置处,设置有4个第二衬垫;且该4个第二衬垫沿Y轴方向并列排布。
可以看出,相较于前一个实施例,图3c在图3a的基础上增加设置了靠近所述半导体功能结构第二边缘20b位置处的多个沿第二方向(沿Y轴方向)排布的多个第二衬垫209。
可以理解的是,沿Y轴方向并列设置的多个第二衬垫209的面积在测试机台的识别范围之内,测试机台可以精准的识别到每个第二衬垫209的位置(四个边缘),基于此,可以利用沿Y轴方向并列设置的多个第二衬垫209得到精确的第二方向,从而在利用已识别出的第一区域向第二方向移动固定距离从而识别出第二区域时,实现更精确的第二方向的移动,从而实现更精准的第二区域的定位。
需要说明的是,图3c中示出的沿第二方向排布的多个第二衬垫209相较于沿第一方向排布的多个第二衬垫209顺时针旋转了90度。但在另一些实施例中,沿第二方向排布的多个第二衬垫209也可以与沿第一方向排布的多个第二衬垫209的摆放方向完全一致,不进行90度的旋转,可以理解的是,进行90度的旋转更利于节省摆放衬垫的面积。
在一些实施例中,所述第一衬垫的数量包括多个,一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处,另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处;一部分所述第二衬垫沿所述第一方向并列设置在一部分所述第一衬垫的两侧,另一部分所述第二衬垫沿所述第一方向并列设置在另一部分所述第一衬垫的两侧;所述第一边缘与所述第二边缘为所述半导体 功能结构相对的两个边缘。
示例性的,参考图3d,所述半导体功能结构200上设置有20个第一衬垫208和12个第二衬垫209;其中,在靠近所述半导体功能结构第一边缘20a位置处,设置10个第一衬垫208,以及在所述10个第一衬垫208的两侧分别设置有3个第二衬垫209(共计6个第二衬垫)。在靠近所述半导体功能结构第二边缘20b位置处,同样设置10个第一衬垫208,以及在所述10个第一衬垫208的两侧分别设置有3个第二衬垫209(共计6个第二衬垫)。
在一些实施例中,位于靠近所述半导体功能结构第一边缘的位置处的第一衬垫和第二衬垫的排布与位于靠近所述半导体功能结构第二边缘的位置处的第一衬垫和第二衬垫的排布为对称设置。这里,所述对称可以理解为位于第一边缘位置处的衬垫相对于位于第二边缘位置处的衬垫沿第一方向镜像设置。
示例性的,参考图3d,在靠近所述半导体功能结构第一边缘20a位置处的10个第一衬垫208和6个第二衬垫209沿X轴方向并列设置;在靠近所述半导体功能结构第二边缘20b位置处的10个第一衬垫208和6个第二衬垫209沿X轴方向并列设置;这里,将第一边缘20a位置处的所有衬垫和第二边缘20b位置处的所有衬垫设置为对称结构,可以节省工艺流程,提高生产效率。
当第一边缘位置处的衬垫与第二边缘位置处的衬垫对称设置时,可以从第一边缘和第二边缘分别识别出相应第一衬垫208的第一区域和第二区域,若第一边缘和第二边缘对应的两个第一衬垫被识别出的对应的两个第一区域的连线方向与第二方向平行则进一步说明了两边的识别均是精确的。
在另一些实施例中,位于靠近所述半导体功能结构第一边缘的位置处的第一衬垫和第二衬垫的排布与位于靠近所述半导体功能结构第二边缘的位置处的第一衬垫和第二衬垫的排布为非对称设置。这里,所述非对称可以理解为位于第一边缘位置处的衬垫相对于位于第二边缘位置处的衬垫沿第一方向不是镜像设置的。
示例性的,参考图3e,将所述第一边缘20a位置处的所有衬垫和所述第二边缘20b位置处的所有衬垫设置为非对称结构;具体地,在靠近所述半导体功能结构第一边缘20a位置处,设置10个第一衬垫,以及在所述10个第一衬垫的第一侧和第二侧各设置3个第二衬垫209;在靠近所述半导体功能结构第二边缘20b位置处,设置10个第一衬垫,以及在所述10个第一衬垫的第一侧设置4个第二衬垫209,在所述第二侧设置2个第二衬垫209。如此,位于所述第一边缘20a位置处的所有衬垫和位于所述第二边缘20b位置处的所有衬垫设置为非对称结构。
当第一边缘位置处的衬垫与第二边缘位置处的衬垫非对称设置时,从 第一边缘和第二边缘分别识别出相应第一衬垫208的第一区域2081和第二区域2082的情况可以判断识别结果中是否可能出现错误。例如,从第一边缘和第二边缘分别识别出相应第一衬垫208的第一区域2081和第二区域2082的情况应该是不相同的,如果此时检测到的两边第一衬垫的情况是相同的,则可以判断两个边缘的识别情况中至少有一侧是错误的。
需要说明的是,图3a、图3b、图3c、图3d、图3e中关于第一衬垫、第二衬垫的数量的描述(例如4个、6个、8个10、20个等),仅用于示意性的说明本公开,并不用来限制本公开的范围。
根据本公开的另一方面,又提供了一种半导体器件,包括:半导体功能结构及如本公开上述多个实施例中所述的封装结构。
根据本公开的又一方面,本公开实施例提供了一种封装结构的制作方法,用于形成上述实施例中的封装结构;图4为本公开实施例提供的封装结构的制造方法的流程示意图。如图4所示,本公开实施例提供的封装结构的制造方法包括以下步骤:
步骤S401:在半导体功能结构上形成重布线层,所述重布线层与所述半导体功能结构上的互连层电性连接;
步骤S402:在所述重布线层的表面形成绝缘层;
步骤S403:去除部分所述绝缘层,以暴露出部分所述重布线层,形成至少一个第一衬垫;每一所述第一衬垫均由所述绝缘层暴露出的部分所述重布线层构成;
其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试,所述第二区域用于执行与所述测试的内容对应的功能交互。
应当理解,图4中所示的步骤并非排他的,也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤;图4中所示的各步骤可以根据实际需求进行顺序调整。图5a至图5c为本公开实施例提供的一种封装结构的制作过程的剖面示意图。下面结合图4、图5a至图5c,对本公开实施例提供的封装结构的制作方法进行详细地说明。
在步骤S401中,形成重布线层。
参考图5a,形成重布线层包括:提供基底(图5a中未标出);在所述基底上形成半导体功能结构500;在所述半导体功能结构500上形成重布线层505。其中,在所述基底上形成半导体功能结构包括:在所述基底上形成半导体功能层501;在所述半导体功能层501上形成互连层502。
这里,可以通过物理气相沉积(PVD,Physical Vapor Deposition)、化学气相沉积(CVD,Chemical Vapor Deposition)、原子层沉积(ALD,Atomic Layer Deposition)等方式在所述半导体功能层501上形成所述互连层502。
接下来,在所述互连层上形成隔离层503;所述隔离层503用于保护互连层502不被破坏。所述隔离层503的组成材料包括但不限于正硅酸乙酯 (TEOS)。形成所述隔离层503的方法包括但不限于PVD、CVD、ALD等工艺。
这里,所述隔离层503的部分区域被去除,使得所述隔离层503中具有多个过孔504,所述过孔504暴露部分所述互连层502;该被暴露的部分所述互连层502作为重布线层505与所述互连层502实现电连接的区域。所述过孔504的形状可以是圆柱形,也可以是倒梯形,或者是任何合适的形状。
接下来,在所述隔离层503表面上和过孔504中形成重布线层505,其中,所述重布线层505与所述互连层502电性连接。
在一些具体实施例中,在所述隔离层503上形成所述重布线层505的具体方式包括:以曝光显影的方式在所述隔离层503上形成新的导线图案,然后,利用电镀技术按照所述新的导线图案形成重布线层505,所述重布线层505包括新的导线路径,该新的导线路径连接与所述互连层502导电连接。其中,所述重布线层505的组成材料包括但不限于金属;优选地,所述重布线层的材料为铝(Al)。
需要说明的是,被暴露的部分所述互连层502上的重布线层的厚度与隔离层503表面上的重布线层的厚度可以相同。在一些实施例中,过孔504的径宽大于两倍重布线层的厚度,此时,重布线层505覆盖过孔504的侧壁和底部,重布线层505围成有凹槽506。
在步骤402中,参考图5b,在所述重布线层505的表面上形成绝缘层507。
所述绝缘层507覆盖重布线层505的表面,一方面可以用于隔离重布线层505与其他导电材料之间的电连接,另一方面可以用于保护重布线层505不被破坏。其中,所述绝缘层507的材料包括但不限于聚酰亚胺(PI)。形成所述第一绝缘层507的方式包括但不限于PVD、CVD、ALD等工艺。
这里,在所述重布线层505围成的凹槽506内也填充绝缘层507。
在一些实施例中,所述绝缘层507的材料的硬度小于所述重布线层505的材料的硬度,可以减小封装结构的应力,增加可靠性。在步骤403中,参考图5c,形成至少一个第一衬垫508。
具体地,去除部分所述绝缘层507,暴露出部分重布线层505;该被暴露出的部分所述重布线层505包括第一衬垫508。其中,每一所述第一衬垫508包括连续设置的第一区域5081和第二区域5082;所述第一区域5081用于进行测试,所述第二区域5082用于执行与所述测试的内容对应的功能交互。
基于此,本公开各实施例中,通过在半导体功能结构上设置至少一个第一衬垫,其中,每个第一衬垫包括用于执行测试的第一区域,以及用于执行与所述测试的内容对应的功能交互的第二区域;第一区域与第二区域之间连续设置,换言之,第一区域和第二区域之间未设置隔墙。如此,在 保证用于测试的区域和用于执行与测试内容对应的功能交互的区域在物理上存在区分的前提下,能够在执行测试时,避免探针出现未瞄准的情况下,隔墙对探针卡造成的损伤,从而延长探针卡的使用寿命;同时,减少杂质的产生,有利于提升测试准确性;另外,减少探针卡对隔墙的破坏,进而从整体上提高了封装结构的可靠性。
在本公开所提供的几个实施例中,应该理解到,所揭露的设备和方法,可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,如:多个单元或组件可以结合,或可以集成到另一个***,或一些特征可以忽略,或不执行。另外,所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的,作为单元显示的部件可以是、或也可以不是物理单元,即可以位于一个地方,也可以分布到多个网络单元上;可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或设备实施例中所揭露的特征,在不冲突的情况下可以任意组合,得到新的方法实施例或设备实施例。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
本公开各实施例中,通过在半导体功能结构上设置至少一个第一衬垫,其中,每个第一衬垫包括用于执行测试的第一区域,以及用于执行与所述测试的内容对应的功能交互的第二区域;第一区域与第二区域之间连续设置,换言之,第一区域和第二区域之间未设置隔墙。如此,在保证用于测试的区域和用于执行与测试内容对应的功能交互的区域在物理上存在区分的前提下,能够在执行测试时,避免探针出现未瞄准的情况下,隔墙对探针卡造成的损伤,从而延长了探针卡的使用寿命;同时,减少杂质的产生,从而提高了测试效率;另外,减少探针卡对隔墙的破坏,进而从整体上提高了封装结构的可靠性。
Claims (12)
- 一种封装结构,包括:重布线层,所述重布线层与半导体功能结构的互连层电性连接;绝缘层,覆盖且暴露出部分所述重布线层;被暴露出的部分所述重布线层包括至少一个第一衬垫;其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试;所述第二区域用于执行与所述测试的内容对应的功能交互。
- 根据权利要求1所述的封装结构,其中,所述封装结构还包括:多个第二衬垫,由所述绝缘层暴露出的部分所述重布线层构成,用于进行测试或者用于执行与所述测试的内容对应的功能交互;其中,多个所述第二衬垫中至少部分第二衬垫与所述至少一个所述第一衬垫沿第一方向并列设置,所述第一方向垂直于所述第一区域指向所述第二区域的方向;每一所述第一衬垫的面积大于每一所述第二衬垫的面积。
- 根据权利要求2所述的封装结构,其中,所述第一衬垫与所述第二衬垫均为长条状;所述第一衬垫沿所述第一方向上的宽度与所述第二衬垫沿所述第一方向上的宽度相同;相邻的两个衬垫间的间距相等;沿第一方向并列设置的所有衬垫的一端平齐。
- 根据权利要求3所述的封装结构,其中,所述第一衬垫的数量包括多个,至少部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处;至少部分所述第二衬垫沿所述第一方向并列设置在所述多个第一衬垫的两侧。
- 根据权利要求4所述的封装结构,其中,在至少部分所述第一衬垫每一侧至少包括两个所述第二衬垫。
- 根据权利要求4所述的封装结构,其中,在所述多个第一衬垫的第一侧具有第一数量的所述第二衬垫,在所述多个第一衬垫的第二侧具有第二数量的所述第二衬垫,所述第一数量与所述第二数量不同。
- 根据权利要求4所述的封装结构,其中,一部分所述第二衬垫沿第一方向并列设置在所述多个第一衬垫的两侧,另一部分所述第二衬垫沿第二方向并列设置在靠近所述半导体功能结构第二边缘的位置处;所述第二方向和所述第一方向垂直;所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘。
- 根据权利要求3所述的封装结构,其中,所述第一衬垫的数量包括多个,一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处,另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处;一部分所述第二衬垫沿所述第一方向并列设置在一部分所述第一衬垫的两侧,另一部分所述第二衬垫沿所述 第一方向并列设置在另一部分所述第一衬垫的两侧;所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘。
- 根据权利要求8所述的封装结构,其中,位于靠近所述半导体功能结构第一边缘的位置处的所述第一衬垫和所述第二衬垫的排布与位于靠近所述半导体功能结构第二边缘的位置处的所述第一衬垫和所述第二衬垫的排布为对称设置。
- 根据权利要求3-9中任一项所述的封装结构,其中,沿第一方向并列设置的所有衬垫靠近所述半导体功能结构边缘的一端平齐;所述第一区域位于所述第一衬垫中靠近所述半导体功能结构边缘的一端,所述第二区域位于所述第一衬垫中远离所述半导体功能结构边缘的一端。
- 一种半导体器件,包括:半导体功能结构及如权利要求1至10中任一项所述的封装结构。
- 一种封装结构的制作方法,所述方法包括:在半导体功能结构上形成重布线层,所述重布线层与所述半导体功能结构上的互连层电性连接;在所述重布线层的表面形成绝缘层;去除部分所述绝缘层,以暴露出部分所述重布线层,形成至少一个第一衬垫;每一所述第一衬垫均由所述绝缘层暴露出的部分所述重布线层构成;其中,所述第一衬垫包括连续设置的第一区域和第二区域;所述第一区域用于进行测试,所述第二区域用于执行与所述测试的内容对应的功能交互。
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CN1819168A (zh) * | 2005-02-08 | 2006-08-16 | 恩益禧电子股份有限公司 | 半导体装置及其制造方法 |
US20060279001A1 (en) * | 2005-06-13 | 2006-12-14 | Nec Electronics Corporation | Semiconductor device and manufacturing method therefor |
US20090134523A1 (en) * | 2007-11-26 | 2009-05-28 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20170062367A1 (en) * | 2015-08-26 | 2017-03-02 | Samsung Electronics Co., Ltd. | Semiconductor chip, semiconductor package including the same, and method of fabricating the same |
CN106684063A (zh) * | 2015-11-10 | 2017-05-17 | 三星电子株式会社 | 半导体器件和包括半导体器件的半导体封装件 |
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CN1819168A (zh) * | 2005-02-08 | 2006-08-16 | 恩益禧电子股份有限公司 | 半导体装置及其制造方法 |
US20060279001A1 (en) * | 2005-06-13 | 2006-12-14 | Nec Electronics Corporation | Semiconductor device and manufacturing method therefor |
US20090134523A1 (en) * | 2007-11-26 | 2009-05-28 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20170062367A1 (en) * | 2015-08-26 | 2017-03-02 | Samsung Electronics Co., Ltd. | Semiconductor chip, semiconductor package including the same, and method of fabricating the same |
CN106684063A (zh) * | 2015-11-10 | 2017-05-17 | 三星电子株式会社 | 半导体器件和包括半导体器件的半导体封装件 |
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