WO2023223745A1 - Semiconductor display device and spatial phase modulation device - Google Patents

Semiconductor display device and spatial phase modulation device Download PDF

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Publication number
WO2023223745A1
WO2023223745A1 PCT/JP2023/015455 JP2023015455W WO2023223745A1 WO 2023223745 A1 WO2023223745 A1 WO 2023223745A1 JP 2023015455 W JP2023015455 W JP 2023015455W WO 2023223745 A1 WO2023223745 A1 WO 2023223745A1
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WIPO (PCT)
Prior art keywords
transistor
circuit
display device
pixel
substrate
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PCT/JP2023/015455
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French (fr)
Japanese (ja)
Inventor
幹生 岡
泰弘 渡邉
Original Assignee
ソニーグループ株式会社
ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2023223745A1 publication Critical patent/WO2023223745A1/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to a semiconductor display device and a spatial phase modulation device.
  • a phase modulation device has a panel structure in which a liquid crystal layer is sandwiched between electrodes, and controls the phase of incident light in an analog manner by controlling the voltage applied to the liquid crystal layer.
  • the phase modulation device is desired to have analog drive and high speed pixel circuits.
  • switching elements within pixels such as transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), are required to have high withstand voltage and low leakage performance.
  • MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
  • oxide semiconductors have high breakdown voltage and low leakage characteristics, they have a problem of extremely low electron mobility.
  • this configuration poses a problem in that the response performance of the pixel circuit using an oxide semiconductor is insufficient with respect to the input frequency of image signals.
  • a current sink circuit is used to reduce the parasitic resistance during the write operation as a means to reduce the influence of the source follower effect, which simultaneously activates multiple row scan lines and supplies image signals for multiple pixels at the same time.
  • a method has been proposed to reduce this.
  • multiple row scanning lines are simultaneously activated and image signals are supplied to multiple pixels at the same time, multiple digital-to-analog conversion circuits and analog buffers are required, which increases the scale of the signal line drive circuit. There are issues such as slow shrinkage of picture frames and chip sizes.
  • the present disclosure provides a display device in which a pixel circuit can output an appropriate output.
  • a semiconductor display device includes a pixel circuit, a pixel array, a first drive circuit, a first signal line, a second drive circuit, and a second signal line.
  • the pixel circuit includes a display element.
  • the pixel array includes the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction.
  • the first drive circuit controls driving of the pixel circuits in the first direction in the pixel array.
  • the first signal line transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction.
  • the second drive circuit transmits a reference signal to the pixel circuits belonging to the second direction in the pixel array.
  • the second signal line transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction.
  • the pixel circuit includes a memory circuit and a comparison circuit.
  • the memory circuit stores digital grayscale values indicating the display intensity of the pixel circuit.
  • the comparison circuit is connected to the memory circuit and compares the digital grad
  • a first transistor whose output end is connected to the drive terminal of the display element; and a second transistor whose one end is connected to the comparison circuit and the other end is connected to the gate of the first transistor. Good too.
  • a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate.
  • the semiconductor device may include two transistors, the second substrate may include the memory circuit and the comparison circuit, and the first transistor and second transistor may include an oxide semiconductor.
  • the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
  • the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
  • the device may further include a resistor connected between the gate of the first transistor and the power supply voltage.
  • a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate.
  • the semiconductor device may include two transistors, the second substrate may include the memory circuit and the comparison circuit, and the first transistor and second transistor may include an oxide semiconductor.
  • the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
  • the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
  • the resistor may be a pull-up resistor or a pull-down resistor.
  • the display device may include a first transistor whose gate is connected to the comparison circuit and whose output terminal is connected to the drive terminal of the display element.
  • a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element and the first transistor.
  • the second substrate may include the memory circuit and the comparison circuit, and the first transistor may include an oxide semiconductor.
  • the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
  • the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
  • the pixel circuit may further include a level shift circuit that is connected to the comparison circuit and controls the voltage of the input signal.
  • a first transistor whose output end is connected to the drive terminal of the display element; and a second transistor whose one end is connected to the level shift circuit and the other end is connected to the gate of the first transistor. It's okay.
  • a first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate.
  • the second substrate may include the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor may include an oxide semiconductor. good.
  • the second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage.
  • the reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
  • a spatial phase modulation device includes any of the semiconductor display devices described above, the pixel circuit is a circuit that constitutes a reflective pixel, and the display element is a liquid crystal.
  • the pitch of the pixel circuit may be 3.6 um or less.
  • FIG. 1 is a diagram schematically showing a semiconductor display device according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment.
  • FIG. 1 is a diagram schematically showing a laser processing device according to an embodiment.
  • FIG. 1 is a diagram schematically illustrating an optical computing device according to an embodiment.
  • FIG. 1 is a schematic diagram of a stacked structure of a semiconductor device according to an embodiment.
  • FIG. 1 is a block diagram schematically showing a semiconductor display device according to an embodiment.
  • the semiconductor display device 1 includes a pixel array 10 , a control circuit 12 , a vertical drive circuit 14 , a horizontal drive circuit 16 , a first signal line 140 , and a second signal line 160 .
  • the pixel array 10 includes a plurality of pixel circuits 100 arranged in an array in a first direction and a second direction intersecting the first direction.
  • Each pixel circuit 100 includes a display element.
  • Each pixel circuit 100 included in this pixel array 10 allows the semiconductor display device 1 to display an image or display for phase modulation.
  • the first direction and the second direction represent, by way of non-limiting example, a line direction and a column direction, respectively.
  • the control circuit 12 is a circuit that controls the display of the image displayed on the pixel array 10 or the display for phase modulation.
  • the control circuit 12 controls each of the pixel circuits 100 in the pixel array 10 by sending appropriate control signals to the vertical drive circuit 14 and the horizontal drive circuit 16 .
  • the vertical drive circuit 14 (first drive circuit) transmits a signal that controls which line of the pixel circuit 100 in the pixel array 10 is to be driven. Pixel circuits 100 belonging to the same line are connected to the same first signal line 140. The vertical drive circuit 14 outputs a signal (drive signal) for controlling the drive of the pixel circuit 100 belonging to each line via the first signal line 140 .
  • the horizontal drive circuit 16 (second drive circuit) transmits a signal indicating the display intensity or phase modulation degree for each column to the pixel circuit 100 whose drive is controlled by the vertical drive circuit 14 . Pixel circuits 100 belonging to the same column are connected to the same second signal line 160. The horizontal drive circuit 16 outputs a signal (reference signal) for controlling the intensity, etc. of the pixel circuit 100 belonging to each column via the second signal line 160 .
  • the horizontal drive circuit 16 starts outputting a ramp signal at a timing controlled by the control circuit 12 for each column.
  • the pixel circuit 100 reads the signal value of the lamp signal transmitted from the horizontal drive circuit 16 via the second signal line 160 at an appropriate timing to drive the light emitting element or phase modulation element with appropriate intensity or phase modulation degree. Drive.
  • the semiconductor display device 1 can display an appropriate image or set an appropriate degree of phase modulation in the pixel array 10.
  • FIG. 2 is a diagram schematically showing an example of the pixel circuit 100.
  • the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a phase modulation element Pm as a display element, and a first transistor Tr1 that controls the drive of the phase modulation element Pm based on signals transmitted from respective signal lines. , a second transistor Tr2, and a capacitor C.
  • the memory circuit 102 stores digital gradation values indicating the phase modulation degree (display intensity of the display element) of the phase modulation element Pm.
  • the memory circuit 102 is, by way of non-limiting example, SRAM (Static Random Access Memory).
  • the stored digital gradation values may be input from the horizontal drive circuit 16 via the second signal line 160, for example, before display.
  • the comparison circuit 104 is connected to the memory circuit 102 and compares the digital gradation value stored in the memory circuit 102 with the count value output from the counter 200 provided outside the pixel circuit 100 and outputs the result. .
  • the first transistor Tr1 operates as a switch that writes a signal that determines the modulation intensity of the phase modulation element Pm into the capacitor C.
  • the first transistor Tr1 is, for example, an n-type transistor including an oxide semiconductor, and has a drain connected to the signal line DT, and a source connected to one end of the capacitor C and the phase modulation element Pm.
  • the second transistor Tr2 operates as a switch that controls the timing of driving the first transistor Tr1.
  • the second transistor Tr2 is, for example, an n-type transistor including an oxide semiconductor, and has a drain connected to the comparator circuit 104, a source connected to the gate of the first transistor Tr1, and a gate connected to the signal line GT. .
  • the oxide semiconductor included in the first transistor Tr1 and the second transistor Tr2 may be formed of, for example, IGZO, or other oxides such as oxides containing oxides of zinc, tin, and indium. It may be a transistor comprising:
  • One end of the capacitor C is connected to the source of the first transistor Tr1, and the other end is connected to the reference voltage line VCOM.
  • the phase modulation element Pm is, for example, an element including a liquid crystal, and one end is connected to one end of the capacitor C, and the other end is connected to the reference voltage line VCOM.
  • Comparison circuit 104 compares the gradation value stored in memory circuit 102 and the count value output from counter 200 .
  • This count value is, for example, a value that is counted up from a minimum value to a maximum value.
  • the comparison circuit 104 outputs a voltage for driving the first transistor Tr1 to the drain of the second transistor Tr2 at the timing when the count value exceeds the gradation value.
  • the second transistor Tr2 When the second transistor Tr2 is turned on by the signal line GT, it outputs a voltage to drive the gate of the first transistor Tr1 at a timing corresponding to the output from the comparator circuit 104.
  • the signal line GT is connected to the first signal line 140 in FIG. 1, for example. That is, at the timing when the line to which the pixel circuit 100 belongs is selected and the counter value exceeds the gradation value, the second transistor Tr2 outputs a signal that drives the first transistor Tr1.
  • the first transistor Tr1 outputs a signal to the capacitor C according to the voltage value applied to the signal line DT at the timing when the drive signal is input to the gate. A signal value corresponding to the voltage of the signal line DT output from the first transistor Tr1 is written into the capacitor C.
  • the signal line DT is connected to the second signal line 160 in FIG. 1, for example.
  • a ramp signal from the horizontal drive circuit 16 is input to the second signal line 160 as a reference signal.
  • This ramp signal is a signal that transitions from the minimum value (predetermined minimum value) to the maximum value (predetermined maximum value) of the display value or modulation value.
  • the start timing of the ramp signal output by the horizontal drive circuit 16 and the count of the counter 200 may be synchronized.
  • capacitor C is charged with the voltage of the ramp signal ( signal value of the reference signal) is stored. As a result, a voltage corresponding to the gradation value stored in the memory circuit 102 is stored in the capacitor C.
  • the phase modulation element Pm performs display according to the voltage written in the capacitor C.
  • the angle of the liquid crystal molecules in the phase modulation element Pm is set according to the voltage written to the capacitor C, and the degree of phase modulation is set for each pixel circuit 100 based on the difference in this angle. .
  • the signal for controlling the phase modulation degree is written into the capacitor C from the ramp-shaped reference signal at an appropriate timing, so that the electron mobility is lower than that of the MOSFET. Even in the case of using an oxide semiconductor with a low sensitivity, it is possible to read and display appropriate pixel values without insufficient response speed. Therefore, appropriate phase modulation processing can be achieved using a transistor including an oxide semiconductor having high breakdown voltage and low leakage characteristics.
  • the semiconductor display device 1 can output an analog display signal based on the digital gradation value to the display element without going through a digital-to-analog conversion circuit. Therefore, according to the semiconductor display device 1 of the present disclosure, it is also possible to drive all pixels at the same timing.
  • the first transistor Tr1 and the second transistor Tr2 are N-type transistors, but they are not limited to this, and P-type transistors can also be implemented by adjusting the control voltage. Is possible. Although embodiments other than the first embodiment will be described as n-type transistors, they may be p-type transistors as well.
  • the oxide semiconductor is p-type, the oxide semiconductor may be formed of a substance containing an oxide of copper, silver, tin, or the like.
  • the count value output by the counter 200 is assumed to count up, the present invention is not limited to this.
  • the count value output by the counter 200 may be a value that counts down from the maximum value to the minimum value.
  • the voltage applied to the signal line DT may also be a downward ramp signal whose voltage value decreases from a predetermined maximum value to a predetermined minimum value. The same applies to the following embodiments.
  • FIG. 3 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the second embodiment.
  • the pixel circuit 100 includes a resistor R connected to the gate of the first transistor Tr1.
  • the resistor R is a resistor that pulls down the gate voltage of the first transistor Tr1, and stabilizes the potential of the gate of the first transistor Tr1.
  • the semiconductor display device 1 can perform display (phase modulation) based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to do so.
  • FIG. 4 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the third embodiment.
  • the pixel circuit 100 has a resistor that is used as a pull-up resistor instead of the pull-down resistor in the configuration of the second embodiment described above.
  • One end of the resistor R is connected to the gate of the first transistor Tr1, and the other end is connected to the positive power supply voltage.
  • This is a resistor that pulls up the gate voltage of the first transistor Tr1 of the resistor R, and stabilizes the potential of the gate of the first transistor Tr1.
  • the semiconductor display device 1 can perform display (phase modulation) based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to do so. Compared to the second embodiment described above, there is no need for a grounding path for each display pixel (pixel circuit 100), so the wiring layout area can be reduced and resources can be secured for the area of this wiring. You can also do it.
  • the resistor R is a pull-down or pull-up resistor, but this can also be determined depending on, for example, the conductivity type of the first transistor Tr1. For example, if the first transistor Tr1 is an N-type, a pull-down resistor may be provided, and if the first transistor Tr1 is a P-type, a pull-up resistor may be provided.
  • the pixel circuit includes two oxide semiconductors, but in this embodiment, the structure of the transistor is changed.
  • FIG. 5 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the fourth embodiment.
  • the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a first transistor Tr1, a capacitor C, and a phase modulation element Pm as a display element.
  • the memory circuit 102, capacitor C, and phase modulation element Pm operate in the same manner as in each of the above embodiments.
  • Comparison circuit 104 compares the digital gradation value stored in memory circuit 102 and the counter value output from counter 200 provided outside pixel circuit 100, as in each of the above-described embodiments. Output the result to the gate of the first transistor Tr1.
  • the first transistor Tr1 is, for example, an n-type oxide semiconductor, and has a drain connected to the signal line DT, a source connected to one end of the capacitor C and one end of the phase modulation element Pm, and a gate connected to the comparator circuit 104. be done.
  • the configuration may be such that the second transistor in each of the above-described embodiments is not provided.
  • a signal based on the comparison result output from the comparison circuit 104 is directly applied to the gate of the first transistor Tr1. Then, similar to the embodiment described above, a ramp-shaped signal is transferred from the signal line DT to the capacitor C at the timing when the result of comparing the gradation value and the counter value is obtained.
  • the semiconductor display device 1 can perform display based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. (phase modulation). By not providing the second transistor Tr2, it is possible to reduce the region in which the transistor is formed.
  • FIG. 6 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the fifth embodiment.
  • the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a first transistor Tr1, a second transistor Tr2, and a phase modulation element Pm.
  • phase modulation element Pm The operations of the memory circuit 102, comparator circuit 104, second transistor Tr2, first transistor Tr1, and phase modulation element Pm are approximately the same as in the above embodiment.
  • the first transistor Tr1 transfers the signal value from the signal line DT to one end of the phase modulation element Pm at a timing corresponding to the gradation value stored in the memory circuit 102.
  • the degree of phase modulation of the phase modulation element Pm is controlled based on the signal value transferred from the first transistor Tr1.
  • the semiconductor display device 1 can generate appropriate display signals using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to display (phase modulation) based on
  • the first transistor Tr1 which is an oxide semiconductor, is used as a transistor to transfer signals based on pixel values, and an appropriate voltage is applied to transfer signals for an appropriate period of time. It becomes possible to control the display on the screen.
  • the phase modulation element Pm includes a liquid crystal, it is possible to hold the voltage by the capacitance related to the liquid crystal.
  • FIG. 7 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the sixth embodiment.
  • the pixel circuit 100 may further include a level shift circuit 106 in addition to the configuration of the first embodiment. That is, the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a level shift circuit 106, a first transistor Tr1, a second transistor Tr2, a capacitor C, and a phase modulation element Pm.
  • the level shift circuit 106 is connected between the comparison circuit 104 and the second transistor Tr2.
  • the level shift circuit 106 converts the signal output from the comparison circuit 104 to a predetermined voltage level and outputs the same.
  • the output of this level shift circuit 106 is applied to the gate of the first transistor Tr1 via the second transistor Tr2, thereby converting the output of the comparator circuit 104 to an appropriate voltage level for driving the first transistor Tr1. can be applied.
  • the semiconductor display device 1 can perform display based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. (phase modulation).
  • phase modulation By providing the level shift circuit 106, it becomes possible to control the first transistor Tr1, which is an oxide semiconductor, with more precision.
  • phase modulation element including, for example, a liquid crystal is used as a display element, but a light emitting element can also be used as a display element. That is, the configuration of the semiconductor display device 1 including an oxide semiconductor can also be applied to a display device of a light emitting device that realizes a general display such as a display.
  • FIG. 8 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the seventh embodiment.
  • the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a third transistor Tr3, a fourth transistor Tr4, a capacitor C, and a light emitting element L as a display element.
  • the memory circuit 102 stores digital gradation values that define the intensity at which the light emitting element L emits light.
  • the comparison circuit 104 compares the gradation value stored in the memory circuit 102 and the count value output from the counter 200 provided outside the pixel circuit 100, and outputs the comparison result and a drive signal.
  • the third transistor Tr3 is, for example, a transistor including an n-type oxide semiconductor, and its drain is connected to the power supply voltage line VCC.
  • the fourth transistor Tr4 is, for example, a transistor including an n-type oxide semiconductor, and has a drain connected to the signal line VSIG, a source connected to the gate of the third transistor Tr3, and a gate connected to the output of the comparison circuit 104. be done.
  • One end of the capacitor C is connected to the gate of the third transistor Tr3 and the source of the fourth transistor Tr4, and the other end is connected to the source of the third transistor Tr3.
  • the light-emitting element L is, for example, a light-emitting element such as an LED (Light Emitting Diode), an organic EL (Electroluminescence) including an organic LED, or an inorganic EL.
  • the light emitting element is not limited to these, and may be other types of elements whose emission intensity (brightness) is determined by the voltage applied to one end.
  • One end of the light emitting element L to which a voltage corresponding to the light emission intensity is applied is connected to the source of the third transistor Tr3 and the other end of the capacitor C, and the other end is grounded.
  • Digital gradation values that determine the light emission intensity of the light emitting element L are stored in the memory circuit 102 .
  • the comparison circuit 104 compares the gradation value stored in the memory circuit 102 with the count value input from the external counter 200, and when the counter value exceeds the gradation value, outputs a signal to the gate of the fourth transistor Tr4. Outputs a signal to drive the fourth transistor Tr4.
  • the fourth transistor Tr4 transfers the voltage applied to the signal line VSIG to the capacitor C at the timing when the driving signal is input.
  • a ramp-like reference signal synchronized with the counter 200 is applied to the signal line VSIG. For example, a ramp signal that transitions from a predetermined minimum value to a predetermined maximum value for applying a voltage corresponding to the minimum to maximum brightness of the light emitting element L is applied to the signal line VSIG.
  • a voltage Vcc which is the power supply voltage of the oxide semiconductor, is applied to the drain of the third transistor Tr3 from the power supply voltage line VCC.
  • Vcc the power supply voltage of the oxide semiconductor
  • a voltage corresponding to the emission intensity is applied to the anode of the light emitting element L, and a current flows appropriately, so that the light emitting element L emits light at an intensity based on the gradation stored in the memory circuit 102.
  • the semiconductor display device 1 is capable of controlling the light emission intensity of not only a phase modulation element but also a light emitting element in a display device such as a general display. Also in this form, the response speed is insufficient for emitting light based on a signal converted from a digital signal into an analog intensity voltage in a pixel circuit using an oxide semiconductor having high breakdown voltage and low leakage characteristics as in each of the above embodiments. It becomes possible to control without
  • the pixel circuits 100 according to the fourth to seventh embodiments may include the pull-down resistor according to the second embodiment or the pull-up resistor according to the third embodiment. Furthermore, the pixel circuit 100 according to the fourth embodiment, fifth embodiment, or seventh embodiment may include the level shift circuit according to the sixth embodiment.
  • Semiconductor display device 1 can, for example, form a suitable reflective film on the side opposite to the display surface of the phase modulation element Pm as shown in Figure 2 to reflect the light that has passed through the liquid crystal element and output it from the display surface. It can operate as a modulator.
  • the degree of phase modulation by the liquid crystal can be controlled by taking into account the double pass caused by reflection.
  • FIG. 9 is an example in which the pixel circuit 100 is used as a reflective pixel in this way, and is a diagram showing an example in which the semiconductor display device 1 is applied to a laser processing device.
  • the laser processing device 3 includes a light source 300 , a mirror 302 , a phase modulation device including a semiconductor display device 1 , a mirror 304 , an optical system 306 , a condensing section 308 , and a support section 310 .
  • the light source 300 may be, for example, a solid laser, a liquid laser, a gas laser, or a semiconductor laser such as a LD (Laser Diode).
  • the light source 300 emits laser light using a pulse transmission method, for example.
  • the laser light may be linearly polarized.
  • Mirrors 302 and 304 are mirrors that reflect the laser light output from the light source 300.
  • the phase modulation device includes, for example, a semiconductor display device 1 that includes a liquid crystal as a phase modulation element.
  • the pixel circuit of the semiconductor display device 1 is a circuit that constitutes a reflective pixel, and the display element included in the pixel circuit is a liquid crystal.
  • the pixel circuits of this semiconductor display device 1 may have a pixel pitch that allows appropriate phase modulation in the laser processing device 3 , for example, a pixel pitch of 3.6 ⁇ m or less.
  • the phase modulator appropriately modulates the phase of the laser beam reflected by the mirror 302 and outputs it to the mirror 304 .
  • the optical system 306 may be an imaging optical system, for example, a double-sided telecentric optical system in which the reflecting surface of the phase modulation device and the entrance pupil plane of the condenser 308 are in an imaging relationship.
  • the condensing unit 308 condenses the laser beam and irradiates it onto the surface of the target Ob.
  • the support part 310 supports the object so that the upper surface of the object is parallel to the horizontal plane, for example, by adsorbing the object Ob.
  • the support portion 310 may be configured to be able to translate and rotate within a horizontal plane, for example.
  • the laser beam emitted from the light source 300 is reflected by the mirror 302 and enters the phase modulation device.
  • the phase modulation device light that has been appropriately phase modulated in a phase modulation element in a pixel circuit provided as a reflective pixel in the semiconductor display device 1 is emitted to the mirror 304 as reflected light.
  • the laser light is phase modulated and emitted without modifying the polarization plane of the phase modulation device.
  • the phase modulated laser beam output from the phase modulation device is reflected by the mirror 304 to the optical system 306 .
  • the optical system 306 forms a telecentric optical system in which the reflecting surface of the phase modulator and the entrance pupil plane of the condenser 308 are in an imaging relationship, so the laser output from the phase modulator The light is imaged at the entrance pupil plane of the condenser 308 .
  • the condensing unit 308 focuses and irradiates the laser beam on the object Ob-shaped plane, which is placed at an appropriate position by the support unit 310, and the image formed on the incident plane is focused on the object Ob at a predetermined magnification. to be projected onto the surface of As a result, a modified region of the pattern of the projected image is formed on the surface of the object Ob.
  • an image forming a pattern to be formed in the modified region is formed by a spatial phase modulation device (semiconductor display device 1 ).
  • a spatial phase modulation device semiconductor display device 1 .
  • such a spatial phase modulation device exhibits highly accurate reforming performance due to its high response speed, and also has low leakage characteristics, making it possible to reduce power consumption. becomes.
  • FIG. 10 is a diagram schematically showing an optical computing device 4 including a semiconductor display device 1 as a spatial phase modulation device.
  • the optical computing device 4 includes a light source 400, a light valve 402, a display section of a plurality of semiconductor display devices 1, and a detection section 404.
  • a transmissive phase modulation device can be used as a display part of semiconductor display device 1. It can be formed using The display section is formed including, for example, the oxide semiconductor shown in FIG. 2 and the like, a phase modulation element, and wiring.
  • the display portions of the semiconductor display device 1 are overlapped with each other with a predetermined interval.
  • the display section of this semiconductor display device 1 will be referred to as a spatial phase modulator.
  • the light source 400 irradiates the light valve 402 with laser light.
  • the light valve 402 is, for example, a light transmission type optical modulator, and modulates the light intensity of the laser light incident from the light source 400 based on a control signal (image data) input from the outside. As a result, the light valve 402 generates a pattern of image light according to the control signal input from the outside.
  • the light valve 402 irradiates the first spatial phase modulator with the generated image light.
  • the image light is phase modulated by the first spatial phase modulator, and the light acquired thereby is irradiated to the second spatial phase modulator.
  • the light irradiated to the second spatial phase modulator is phase modulated by the second spatial phase modulator, and the light acquired thereby is irradiated to the third spatial phase modulator.
  • the image light is phase modulated by each spatial phase modulator, and the light output from the last spatial phase modulator is detected by the detection unit 404.
  • the detection unit 404 estimates image data input to the light valve 402 based on the input light.
  • the light source 400 and the light valve 402 may be omitted.
  • the first spatial phase modulator may be irradiated with image light input from the outside.
  • the light-transmitting paper surface on which characters or pictures are written is used as the light input source for the first spatial phase modulator.
  • the first spatial phase modulator may be placed on the surface of the paper and detect external light transmitted through the surface of the paper.
  • the phase distribution that determines the processing content in the optical computing device 4 is formed by the semiconductor display device 1 that operates as a spatial phase modulation device. This makes it possible to realize optical computing with low power consumption and the ability to change calculation content.
  • the semiconductor display device 1 may be formed from a plurality of stacked semiconductor substrates.
  • FIG. 11 is a schematic diagram showing a non-limiting example of the stacked structure of the semiconductor display device 1.
  • the structure corresponding to the semiconductor display device 1 particularly the pixel circuit 100 of the semiconductor display device 1 , may be formed by forming two semiconductor layers and stacking them so as to overlap each other.
  • the semiconductor display device 1 may include, for example, a first substrate 50 and a second substrate 52, and may be formed by appropriately laminating these two substrates. Conductive layers such as electrodes and wiring are appropriately formed on the contact surfaces of the first substrate 50 and the second substrate 52 to electrically connect them at appropriate locations.
  • the first substrate 50 has, for example, a display element, and the display element is arranged on the first substrate 50 so that a display is performed on the display element toward the top of the figure.
  • the semiconductor display device 1 may include an appropriate optical system for the display element. Further, in the semiconductor display device 1 , an appropriate coating may be applied on the upper surface of the first substrate 50 to protect the display element. In such a definition, the second substrate 52 is placed farther from the display surface of the semiconductor display device 1 than the first substrate 50 .
  • the pixel circuit 100 of the semiconductor display device 1 includes a first transistor Tr1, a second transistor Tr2, a memory circuit 102, and a comparison circuit 104.
  • elements may be formed on each substrate as follows.
  • the first substrate 50 includes at least a display element, a first transistor Tr1 and a second transistor Tr2 including an oxide semiconductor, and the second substrate 52 may include a memory circuit 102 and a comparison circuit 104. .
  • the second transistor Tr2 if the second transistor Tr2 is not provided, at least the first transistor Tr1 including an oxide semiconductor may be provided on the first substrate 50.
  • this level shift circuit 106 may be provided on the second substrate 52.
  • the semiconductor display device 1 includes the light emitting element L, in which the transistor in the pixel circuit 100 is provided on the first substrate 50, and the memory circuit 102 etc. is provided on the second substrate 52. You can also use it as
  • the first substrate 50 and the second substrate 52 in this way, it is possible to form a layer that forms a transistor including an oxide semiconductor and a layer that forms other transistors, such as a MOSFET, separately. Therefore, the complexity and complexity of the process can be reduced.
  • first substrate 50 and second substrate 52 may be formed, for example, in a CoC (Chip on Chip) format in which chips are stacked together, or in a CoW (Chip on Wafer) format in which chips and wafers are stacked. Alternatively, it may be formed in a WoW (Wafer on Wafer) format in which wafers are stacked.
  • CoC Chip on Chip
  • CoW Chip on Wafer
  • WoW WoW
  • electrical connections such as wiring on the first substrate 50 and the second substrate 52 can be formed by any method such as micro bumps, hybrid junctions, via holes, etc.
  • the above stacked structure is given as a non-limiting example, and the semiconductor display device 1 according to the present disclosure does not have semiconductors formed on separate chips or the like and then bonded together, as described above. It may be formed in a separate layer in the process.
  • circuits such as the memory circuit 102 and the comparison circuit 104, particularly a circuit having a MOSFET as a structure, are formed on the substrate as a second semiconductor layer.
  • a first semiconductor layer including a pixel circuit 100 including an oxide semiconductor is laminated on the formed second semiconductor layer. It can be formed in the form of
  • the semiconductor display device displays analog intensity information when a digital signal is input using an oxide semiconductor as a transistor that controls switches in a pixel circuit. It becomes possible to form pixels. As a result, these semiconductor display devices are able to improve the light focusing area due to high phase stability, expand the viewing angle due to strong image pitch, reduce chip size due to the layered structure, and improve image quality due to high refresh rate. It can be realized.
  • a pixel circuit including a display element; a pixel array including the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction; a first drive circuit that controls driving of the pixel circuits belonging to the first direction in the pixel array; a first signal line that transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction; a second drive circuit that transmits a reference signal to the pixel circuits in the second direction in the pixel array; a second signal line that transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction; Equipped with The pixel circuit is a memory circuit that stores digital gradation values indicating display intensity of the pixel circuit; a comparison circuit that is connected to the memory circuit and compares the digital gradation value stored in the memory circuit with a counter signal; Equipped with Semiconductor display device.
  • the semiconductor display device comprising:
  • the semiconductor display device formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
  • the first substrate includes the display element, the first transistor, and the second transistor,
  • the second substrate includes the memory circuit and the comparison circuit, the first transistor and the second transistor include an oxide semiconductor;
  • the semiconductor display device according to (2).
  • the semiconductor display device (Four) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
  • the semiconductor display device according to (2) or (3).
  • the semiconductor display device formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
  • the first substrate includes the display element, the first transistor, and the second transistor,
  • the second substrate includes the memory circuit and the comparison circuit, the first transistor and the second transistor include an oxide semiconductor;
  • the semiconductor display device according to (5).
  • the semiconductor display device (7) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
  • the semiconductor display device according to (5) or (6).
  • the resistor is a pull-up resistor or a pull-down resistor;
  • the semiconductor display device according to any one of (5) to (7).
  • the semiconductor display device (Ten) formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
  • the first substrate includes the display element and the first transistor,
  • the second substrate includes the memory circuit and the comparison circuit,
  • the first transistor includes an oxide semiconductor.
  • the semiconductor display device (11) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
  • the semiconductor display device according to (9) or (10).
  • the pixel circuit is a level shift circuit connected to the comparison circuit and controlling the voltage of the input signal;
  • the semiconductor display device formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
  • the first substrate includes the display element, the first transistor, and the second transistor,
  • the second substrate includes the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor include an oxide semiconductor.
  • the semiconductor display device according to (13).
  • the semiconductor display device (15) a capacitor connected between a drive terminal of the display element and a predetermined voltage; Furthermore, The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
  • the semiconductor display device according to (13) or (14).
  • the pixel circuit is a circuit that constitutes a reflective pixel, the display element is a liquid crystal; Spatial phase modulator.
  • the pitch of the pixel circuit is 3.6 um or less, The spatial phase modulation device according to (16).
  • 1 Semiconductor display device, 10: Pixel array, 100: Pixel circuit, 102: Memory circuit, 104: Comparison circuit, 106: Level shift circuit, Tr1, Tr2, Tr3, Tr4: transistor, C: Capacitor, R: Resistance Pm: Phase modulation element, L: light emitting element, 12: Control circuit, 14: Vertical drive circuit, 140: 1st signal line, 16: Horizontal drive circuit, 160: 2nd signal line, 200: counter, 3: Laser processing equipment, 300: Light source, 302, 304: mirror, 306: Optical system, 308: Light collecting section, 310: Support part, 4: Optical computing equipment, 400: light source, 402: Light valve, 404: Detection unit, 50: 1st board, 52: 2nd board

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Abstract

[Problem] To perform suitable output in a pixel circuit. [Solution] A semiconductor display device comprises pixel circuits, a pixel array, a first drive circuit, a first signal line, a second drive circuit, and a second signal line. The pixel circuits are provided with a display element, a memory circuit, and a comparison circuit. In the pixel array, the pixel circuits are provided in a two-dimensional array along a first direction and a second direction that intersects the first direction. The first drive circuit controls driving of the pixel circuits belonging to the first direction of the pixel array. The first signal line transmits a drive signal from the first drive circuit to the pixel circuits belonging to the first direction. The second drive circuit transmits a reference signal to the pixel circuits belonging to the second direction in the pixel array. The second signal line transmits the reference signal from the second drive circuit to the pixel circuits belonging to the second direction. The memory circuit stores a digital gradation value indicating the display intensity of the pixel circuits The comparison circuit is connected to the memory circuit and compares a counter signal and the digital gradation value which is stored in the memory circuit.

Description

半導体表示装置及び空間位相変調装置Semiconductor display device and spatial phase modulation device
　本開示は、半導体表示装置及び空間位相変調装置に関する。 The present disclosure relates to a semiconductor display device and a spatial phase modulation device.
　光の位相を変調して所望の像を生成する位相変調装置としての表示装置は、立体ディスプレイ、レーザー加工装置等において、幅広い応用が期待されている。位相変調装置は、電極間に液晶層を挟んだパネル構造を有し、液晶層に印加する電圧を制御することによって入射光の位相をアナログ的に制御する。高い位相安定性を担保するために、位相変調装置は、画素回路のアナログ駆動と高速化が望まれる。さらに、画素内のスイッチング素子、例えば、 MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) といったトランジスタには、高耐圧かつ低リーク性能が要求される。高耐圧な MOSFET は、素子サイズが非常に大きく、また、プロセス世代を進化させても印加する電圧の高さに起因する信頼性において課題があるため、素子を微細化することができない。 Display devices, which function as phase modulators that modulate the phase of light to generate a desired image, are expected to have a wide range of applications in stereoscopic displays, laser processing devices, and the like. A phase modulation device has a panel structure in which a liquid crystal layer is sandwiched between electrodes, and controls the phase of incident light in an analog manner by controlling the voltage applied to the liquid crystal layer. In order to ensure high phase stability, the phase modulation device is desired to have analog drive and high speed pixel circuits. Furthermore, switching elements within pixels, such as transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), are required to have high withstand voltage and low leakage performance. High-voltage MOSFETs have extremely large element sizes, and even with the evolution of process generations, there are issues with reliability due to the high applied voltage, making it impossible to miniaturize the elements.
　この課題の解決策として、素子サイズの微細化が可能な酸化物半導体を用いる方法が提案されている。酸化物半導体は、高耐圧かつ低リーク特性を有する反面、電子移動度が非常に低い問題がある。フィールドシーケンシャル方式表示やサブフレーム数増加による画品位向上を目指す場合等に、この構成は、画像信号の入力頻度に対して酸化物半導体を用いた画素回路の応答性能が不足するという問題が生じる。 As a solution to this problem, a method using an oxide semiconductor that allows miniaturization of the element size has been proposed. Although oxide semiconductors have high breakdown voltage and low leakage characteristics, they have a problem of extremely low electron mobility. When aiming to improve image quality by field sequential display or by increasing the number of subframes, this configuration poses a problem in that the response performance of the pixel circuit using an oxide semiconductor is insufficient with respect to the input frequency of image signals.
　これに対応するべく、複数の行走査線を同時に活性化させて複数の画素について同時に画像信号を供給するソースフォロワ効果の影響を軽減させる手段として、電流シンク回路を用いて書き込み動作中の寄生抵抗を低減する方法が提案されている。しかしながら、複数の行走査線を同時に活性化させて複数の画素に同時に画像信号を供給することからデジタル－アナログ変換回路やアナログバッファが複数必要となるため、信号線駆動回路の規模が増大し、額縁やチップサイズのシュリンクが進まないといった課題がある。 To cope with this, a current sink circuit is used to reduce the parasitic resistance during the write operation as a means to reduce the influence of the source follower effect, which simultaneously activates multiple row scan lines and supplies image signals for multiple pixels at the same time. A method has been proposed to reduce this. However, since multiple row scanning lines are simultaneously activated and image signals are supplied to multiple pixels at the same time, multiple digital-to-analog conversion circuits and analog buffers are required, which increases the scale of the signal line drive circuit. There are issues such as slow shrinkage of picture frames and chip sizes.
特開2013-008054号公報Japanese Patent Application Publication No. 2013-008054
　そこで、本開示では、画素回路において適切な出力が可能な表示装置を提供する。 Therefore, the present disclosure provides a display device in which a pixel circuit can output an appropriate output.
　一実施形態によれば、半導体表示装置は、画素回路と、画素アレイと、第 1 駆動回路と、第 1 信号線と、第 2 駆動回路と、第 2 信号線と、を備える。画素回路は、表示素子を備える。画素アレイは、第 1 方向と、前記第 1 方向に交わる第 2 方向において、 2 次元のアレイ状に前記画素回路が備えられる。第 1 駆動回路は、前記画素アレイにおける前記第 1 方向に属する前記画素回路の駆動を制御する。第 1 信号線は、前記第 1 駆動回路から前記第 1 方向に属する前記画素回路に駆動信号を送信する。第 2 駆動回路は、前記画素アレイにおける前記第 2 方向に属する前記画素回路に参照信号を送信する。第 2 信号線は、前記第 2 駆動回路から前記第 2 方向に属する前記画素回路に前記参照信号を送信する。前記画素回路は、メモリ回路と、比較回路と、を備える。メモリ回路は、前記画素回路の表示強度を示すデジタル階調値を格納する。比較回路は、前記メモリ回路と接続され、前記メモリ回路に格納されている前記デジタル階調値と、カウンタ信号とを比較する。 According to one embodiment, a semiconductor display device includes a pixel circuit, a pixel array, a first drive circuit, a first signal line, a second drive circuit, and a second signal line. The pixel circuit includes a display element. The pixel array includes the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction. The first drive circuit controls driving of the pixel circuits in the first direction in the pixel array. The first signal line transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction. The second drive circuit transmits a reference signal to the pixel circuits belonging to the second direction in the pixel array. The second signal line transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction. The pixel circuit includes a memory circuit and a comparison circuit. The memory circuit stores digital grayscale values indicating the display intensity of the pixel circuit. The comparison circuit is connected to the memory circuit and compares the digital gradation value stored in the memory circuit with a counter signal.
　出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタと、一端が前記比較回路と接続され、他端が前記第 1 トランジスタのゲートと接続される、第 2 トランジスタと、を備えてもよい。 a first transistor whose output end is connected to the drive terminal of the display element; and a second transistor whose one end is connected to the comparison circuit and the other end is connected to the gate of the first transistor. Good too.
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成されてもよく、前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備えてもよく、前記第 2 基板は、前記メモリ回路及び前記比較回路を備えてもよく、前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備えてもよい。 A first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate. The semiconductor device may include two transistors, the second substrate may include the memory circuit and the comparison circuit, and the first transistor and second transistor may include an oxide semiconductor.
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、をさらに備えてもよく、前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込んでもよい。 The second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage. The reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
　前記第 1 トランジスタのゲートと、電源電圧と、の間に接続される、抵抗、をさらに備えてもよい。 The device may further include a resistor connected between the gate of the first transistor and the power supply voltage.
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成されてもよく、前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備えてもよく、前記第 2 基板は、前記メモリ回路及び前記比較回路を備えてもよく、前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備えてもよい。 A first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate. The semiconductor device may include two transistors, the second substrate may include the memory circuit and the comparison circuit, and the first transistor and second transistor may include an oxide semiconductor.
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、をさらに備えてもよく、前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込んでもよい。 The second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage. The reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
　前記抵抗は、プルアップ抵抗又はプルダウン抵抗であってもよい。 The resistor may be a pull-up resistor or a pull-down resistor.
　ゲートが前記比較回路と接続され、出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタ、を備えてもよい。 The display device may include a first transistor whose gate is connected to the comparison circuit and whose output terminal is connected to the drive terminal of the display element.
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成されてもよく、前記第 1 基板は、前記表示素子及び前記第 1 トランジスタを備えてもよく、　前記第 2 基板は、前記メモリ回路及び前記比較回路を備えてもよく、前記第 1 トランジスタは、酸化物半導体を備えてもよい。 A first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element and the first transistor. The second substrate may include the memory circuit and the comparison circuit, and the first transistor may include an oxide semiconductor.
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、をさらに備えてもよく、前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込んでもよい。 The second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage. The reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
　前記画素回路は、前記比較回路と接続され、入力された信号の電圧を制御する、レベルシフト回路、をさらに備えてもよい。 The pixel circuit may further include a level shift circuit that is connected to the comparison circuit and controls the voltage of the input signal.
　出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタと、一端が前記レベルシフト回路と接続され、他端が前記第 1 トランジスタのゲートと接続される、第 2 トランジスタと、を備えてもよい。 a first transistor whose output end is connected to the drive terminal of the display element; and a second transistor whose one end is connected to the level shift circuit and the other end is connected to the gate of the first transistor. It's okay.
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成されてもよく、前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備えてもよく、前記第 2 基板は、前記メモリ回路、前記比較回路及び前記レベルシフト回路を備えてもよく、前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備えてもよい。 A first substrate and a second substrate disposed farther from the display surface than the first substrate may be stacked, and the first substrate may include the display element, the first transistor, and the second substrate. The second substrate may include the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor may include an oxide semiconductor. good.
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、をさらに備えてもよく、前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込んでもよい。 The second drive circuit may further include a capacitor connected between a drive terminal of the display element and a predetermined voltage, and the second drive circuit generates a ramp signal that changes from a predetermined minimum voltage to a predetermined maximum voltage. The reference signal may be output as a signal and written into the capacitor at the timing when the first transistor is driven.
　一実施形態によれば、空間位相変調装置は、上記のいずれかに記載の半導体表示装置を備え、前記画素回路は、反射画素を構成する回路であり、前記表示素子は、液晶である。 According to one embodiment, a spatial phase modulation device includes any of the semiconductor display devices described above, the pixel circuit is a circuit that constitutes a reflective pixel, and the display element is a liquid crystal.
　前記画素回路のピッチは、 3.6 um 以下であってもよい。 The pitch of the pixel circuit may be 3.6 um or less.
一実施形態に係る半導体表示装置を模式的に示す図。FIG. 1 is a diagram schematically showing a semiconductor display device according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係る画素回路を模式的に示す図。FIG. 1 is a diagram schematically showing a pixel circuit according to an embodiment. 一実施形態に係るレーザー加工装置を模式的に示す図。FIG. 1 is a diagram schematically showing a laser processing device according to an embodiment. 一実施形態に係る光コンピューティング装置を模式的に示す図。FIG. 1 is a diagram schematically illustrating an optical computing device according to an embodiment. 一実施形態に係る半導体装置の積層構造の概略図。FIG. 1 is a schematic diagram of a stacked structure of a semiconductor device according to an embodiment.
　以下、図面を参照して本開示における実施形態の説明をする。図面は、説明のために用いるものであり、実際の装置における各部の構成の形状、サイズ、又は、他の構成とのサイズの比等が図に示されている通りである必要はない。また、図面は、簡略化して書かれているため、図に書かれている以外にも実装上必要な構成は、適切に備えるものとする。また、本開示における説明においては、表示素子又はキャパシタの放電については特に記載されていないが、表示素子又はキャパシタの少なくとも一方を放電する構造が適宜備えられていてもよい。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation, and the shapes and sizes of the components of the actual device, or the size ratios with respect to other components, etc., do not need to be as shown in the drawings. Furthermore, since the drawings are drawn in a simplified manner, configurations necessary for implementation other than those shown in the drawings shall be appropriately provided. Further, although the description in the present disclosure does not specifically describe discharging the display element or the capacitor, a structure for discharging at least one of the display element or the capacitor may be provided as appropriate.
　図1は、一実施形態に係る半導体表示装置を模式的に示すブロック図である。半導体表示装置 1 は、画素アレイ 10 と、制御回路 12 と、垂直駆動回路 14 と、水平駆動回路 16 と、第 1 信号線 140 と、第 2 信号線 160 と、を備える。 FIG. 1 is a block diagram schematically showing a semiconductor display device according to an embodiment. The semiconductor display device 1 includes a pixel array 10 , a control circuit 12 , a vertical drive circuit 14 , a horizontal drive circuit 16 , a first signal line 140 , and a second signal line 160 .
　画素アレイ 10 は、第 1 方向及び第 1 方向に交わる第 2 方向にアレイ状に配置される複数の画素回路 100 を備える。画素回路 100 は、それぞれが表示素子を備える。この画素アレイ 10 に備えられるそれぞれの画素回路 100 により、半導体表示装置 1 は、画像を表示したり、位相を変調するための表示をしたりする。第 1 方向及び第 2 方向は、限定されない一例として、ライン方向及びカラム方向をそれぞれ表す。 The pixel array 10 includes a plurality of pixel circuits 100 arranged in an array in a first direction and a second direction intersecting the first direction. Each pixel circuit 100 includes a display element. Each pixel circuit 100 included in this pixel array 10 allows the semiconductor display device 1 to display an image or display for phase modulation. The first direction and the second direction represent, by way of non-limiting example, a line direction and a column direction, respectively.
　制御回路 12 は、画素アレイ 10 に表示する画像の表示、又は、位相変調のための表示を制御する回路である。制御回路 12 は、垂直駆動回路 14 及び水平駆動回路 16 に適切な制御信号を送信することで、画素アレイ 10 における画素回路 100 をそれぞれに制御する。 The control circuit 12 is a circuit that controls the display of the image displayed on the pixel array 10 or the display for phase modulation. The control circuit 12 controls each of the pixel circuits 100 in the pixel array 10 by sending appropriate control signals to the vertical drive circuit 14 and the horizontal drive circuit 16 .
　垂直駆動回路 14 (第 1 駆動回路) は、画素アレイ 10 において、どのラインに属する画素回路 100 を駆動させるかを制御する信号を送信する。同一のラインに属する画素回路 100 は、同一の第 1 信号線 140 に接続される。垂直駆動回路 14 は、第 1 信号線 140 を介して、それぞれのラインに属する画素回路 100 の駆動を制御する信号 (駆動信号) を出力する。 The vertical drive circuit 14 (first drive circuit) transmits a signal that controls which line of the pixel circuit 100 in the pixel array 10 is to be driven. Pixel circuits 100 belonging to the same line are connected to the same first signal line 140. The vertical drive circuit 14 outputs a signal (drive signal) for controlling the drive of the pixel circuit 100 belonging to each line via the first signal line 140 .
　水平駆動回路 16 (第 2 駆動回路) は、垂直駆動回路 14 により駆動制御された画素回路 100 に対して、カラムごとに表示の強度又は位相変調度を示す信号を送信する。同一のカラムに属する画素回路 100 は、同一の第 2 信号線 160 に接続される。水平駆動回路 16 は、第 2 信号線 160 を介して、それぞれのカラムに属する画素回路 100 の強度等を制御する信号 (参照信号) を出力する。 The horizontal drive circuit 16 (second drive circuit) transmits a signal indicating the display intensity or phase modulation degree for each column to the pixel circuit 100 whose drive is controlled by the vertical drive circuit 14 . Pixel circuits 100 belonging to the same column are connected to the same second signal line 160. The horizontal drive circuit 16 outputs a signal (reference signal) for controlling the intensity, etc. of the pixel circuit 100 belonging to each column via the second signal line 160 .
　水平駆動回路 16 は、一例として、カラムごとに制御回路 12 により制御されたタイミングでランプ信号の出力を開始する。画素回路 100 は、適切なタイミングで水平駆動回路 16 から第 2 信号線 160 を介して送信されたランプ信号の信号値を読み取ることで、適切な強度又は位相変調度で発光素子又は位相変調素子を駆動する。 For example, the horizontal drive circuit 16 starts outputting a ramp signal at a timing controlled by the control circuit 12 for each column. The pixel circuit 100 reads the signal value of the lamp signal transmitted from the horizontal drive circuit 16 via the second signal line 160 at an appropriate timing to drive the light emitting element or phase modulation element with appropriate intensity or phase modulation degree. Drive.
　このように、それぞれの画素回路 100 が適切な駆動をすることで、半導体表示装置 1 は、画素アレイ 10 において適切な画像を表示、又は、適切な位相変調度を設定することができる。 In this way, by appropriately driving each pixel circuit 100, the semiconductor display device 1 can display an appropriate image or set an appropriate degree of phase modulation in the pixel array 10.
　以下、図1のブロック図において、画素回路 100 の限定されないいくつかの例を挙げ、その動作について説明する。 Hereinafter, some non-limiting examples of the pixel circuit 100 will be given in the block diagram of FIG. 1, and their operations will be explained.
　(第 1 実施形態)
　図2は、画素回路 100 の一例を模式的に示す図である。画素回路 100 は、メモリ回路 102 と比較回路 104 と、表示素子としての位相変調素子 Pm と、それぞれの信号線から送信された信号に基づいて位相変調素子 Pm の駆動制御をする第 1 トランジスタ Tr1と、第 2 トランジスタ Tr2 と、キャパシタ C と、を備える。 (First embodiment)
FIG. 2 is a diagram schematically showing an example of the pixel circuit 100. The pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a phase modulation element Pm as a display element, and a first transistor Tr1 that controls the drive of the phase modulation element Pm based on signals transmitted from respective signal lines. , a second transistor Tr2, and a capacitor C.
　メモリ回路 102 は、位相変調素子 Pm の位相変調度 (表示素子の表示強度) を示すデジタルの階調値を格納する。メモリ回路 102 は、限定されない一例として SRAM (Static Random Access Memory) である。格納されているデジタルの階調値は、表示の事前に、例えば、第 2 信号線 160 を介して水平駆動回路 16 から入力されていてもよい。 The memory circuit 102 stores digital gradation values indicating the phase modulation degree (display intensity of the display element) of the phase modulation element Pm. The memory circuit 102 is, by way of non-limiting example, SRAM (Static Random Access Memory). The stored digital gradation values may be input from the horizontal drive circuit 16 via the second signal line 160, for example, before display.
　比較回路 104 は、メモリ回路 102 と接続され、メモリ回路 102 に格納されているデジタルの階調値と、画素回路 100 の外部に備えられるカウンタ 200 から出力されるカウント値とを比較して出力する。 The comparison circuit 104 is connected to the memory circuit 102 and compares the digital gradation value stored in the memory circuit 102 with the count value output from the counter 200 provided outside the pixel circuit 100 and outputs the result. .
　第 1 トランジスタ Tr1 は、位相変調素子 Pm の変調強度を決定する信号をキャパシタ C に書き込むスイッチとして動作する。第 1 トランジスタ Tr1 は、例えば、酸化物半導体を有する n 型のトランジスタであり、ドレインが信号線 DT に接続され、ソースがキャパシタ C の一端及び位相変調素子 Pm と接続される。 The first transistor Tr1 operates as a switch that writes a signal that determines the modulation intensity of the phase modulation element Pm into the capacitor C. The first transistor Tr1 is, for example, an n-type transistor including an oxide semiconductor, and has a drain connected to the signal line DT, and a source connected to one end of the capacitor C and the phase modulation element Pm.
　第 2 トランジスタ Tr2 は、第 1 トランジスタ Tr1 を駆動するタイミングを制御するスイッチとして動作する。第 2 トランジスタ Tr2 は、例えば、酸化物半導体を有する n 型のトランジスタであり、ドレインが比較回路 104 に接続され、ソースが第 1 トランジスタ Tr1 のゲートと接続され、ゲートが信号線 GT と接続される。 The second transistor Tr2 operates as a switch that controls the timing of driving the first transistor Tr1. The second transistor Tr2 is, for example, an n-type transistor including an oxide semiconductor, and has a drain connected to the comparator circuit 104, a source connected to the gate of the first transistor Tr1, and a gate connected to the signal line GT. .
　第 1 トランジスタ Tr1 及び第 2 トランジスタ Tr2 に備えられる酸化物半導体は、例えば、 IGZO により形成されていてもよいし、亜鉛、スズ、インジウムの酸化物を含有する酸化物に代表される他の酸化物を備えるトランジスタであってもよい。 The oxide semiconductor included in the first transistor Tr1 and the second transistor Tr2 may be formed of, for example, IGZO, or other oxides such as oxides containing oxides of zinc, tin, and indium. It may be a transistor comprising:
　キャパシタ C は、一端が第 1 トランジスタ Tr1 のソースと接続され、他端が基準電圧線 VCOM と接続される。 One end of the capacitor C is connected to the source of the first transistor Tr1, and the other end is connected to the reference voltage line VCOM.
　位相変調素子 Pm は、例えば、液晶を備える素子であり、一端がキャパシタ C の一端と接続され、他端が基準電圧線 VCOM と接続される。 The phase modulation element Pm is, for example, an element including a liquid crystal, and one end is connected to one end of the capacitor C, and the other end is connected to the reference voltage line VCOM.
　この構成における表示 (位相変調) の動作について説明する。 The operation of display (phase modulation) in this configuration will be explained.
　比較回路 104 は、メモリ回路 102 に格納されている階調値と、カウンタ 200 から出力されるカウント値とを比較する。このカウント値は、例えば、最小値から最大値へとカウントアップされる値である。比較回路 104 は、例えば、カウント値が階調値を超えたタイミングで第 2 トランジスタ Tr2 のドレインに、第 1 トランジスタ Tr1 を駆動するための電圧を出力する。 Comparison circuit 104 compares the gradation value stored in memory circuit 102 and the count value output from counter 200 . This count value is, for example, a value that is counted up from a minimum value to a maximum value. For example, the comparison circuit 104 outputs a voltage for driving the first transistor Tr1 to the drain of the second transistor Tr2 at the timing when the count value exceeds the gradation value.
　第 2 トランジスタ Tr2 は、信号線 GT によりオンしている場合、比較回路 104 からの出力に応じたタイミングで第 1 トランジスタ Tr1 のゲートに駆動するための電圧を出力する。信号線 GT は、例えば、図1の第 1 信号線 140 と接続される。すなわち、画素回路 100 が属するラインが選択され、かつ、カウンタ値が階調値を上回ったタイミングで第 2 トランジスタ Tr2 は、第 1 トランジスタ Tr1 を駆動する信号を出力する。 When the second transistor Tr2 is turned on by the signal line GT, it outputs a voltage to drive the gate of the first transistor Tr1 at a timing corresponding to the output from the comparator circuit 104. The signal line GT is connected to the first signal line 140 in FIG. 1, for example. That is, at the timing when the line to which the pixel circuit 100 belongs is selected and the counter value exceeds the gradation value, the second transistor Tr2 outputs a signal that drives the first transistor Tr1.
　第 1 トランジスタ Tr1 は、ゲートに駆動信号が入力されるタイミングで信号線 DT に印加されている電圧値にしたがう信号をキャパシタ C に出力する。キャパシタ C は、第 1 トランジスタ Tr1 から出力される信号線 DT の電圧に対応する信号値が書き込まれる。 The first transistor Tr1 outputs a signal to the capacitor C according to the voltage value applied to the signal line DT at the timing when the drive signal is input to the gate. A signal value corresponding to the voltage of the signal line DT output from the first transistor Tr1 is written into the capacitor C.
　信号線 DT は、例えば、図1の第 2 信号線 160 と接続される。第 2 信号線 160 には、例えば、水平駆動回路 16 からランプ信号が参照信号として入力される。このランプ信号は、表示値又は変調値の最小値 (所定最小値) から最大値 (所定最大値) まで遷移する信号である。水平駆動回路 16 が出力するランプ信号と、カウンタ 200 のカウントとの開始のタイミングは同期されていてもよい。 The signal line DT is connected to the second signal line 160 in FIG. 1, for example. For example, a ramp signal from the horizontal drive circuit 16 is input to the second signal line 160 as a reference signal. This ramp signal is a signal that transitions from the minimum value (predetermined minimum value) to the maximum value (predetermined maximum value) of the display value or modulation value. The start timing of the ramp signal output by the horizontal drive circuit 16 and the count of the counter 200 may be synchronized.
　カウンタ値と同期するランプ信号を参照信号とすることで、キャパシタ C には、カウンタ 200 が出力するカウンタ値がメモリ回路 102 に格納される階調値を超えたタイミングに対応するランプ信号の電圧 (参照信号の信号値) が蓄電される。この結果、キャパシタ C には、メモリ回路 102 に格納されている階調値に応じた電圧が蓄電される。 By using a ramp signal that is synchronized with the counter value as a reference signal, capacitor C is charged with the voltage of the ramp signal ( signal value of the reference signal) is stored. As a result, a voltage corresponding to the gradation value stored in the memory circuit 102 is stored in the capacitor C.
　位相変調素子 Pm は、キャパシタ C に書き込まれている電圧に応じて表示を行う。液晶素子を備える場合、位相変調素子 Pm は、キャパシタ C に書き込まれている電圧に応じて液晶分子の角度が設定され、この角度の違いにより、位相の変調度合いが画素回路 100 ごとに設定される。 The phase modulation element Pm performs display according to the voltage written in the capacitor C. When equipped with a liquid crystal element, the angle of the liquid crystal molecules in the phase modulation element Pm is set according to the voltage written to the capacitor C, and the degree of phase modulation is set for each pixel circuit 100 based on the difference in this angle. .
　以上のように、本実施形態に係る半導体表示装置によれば、適切なタイミングでランプ状の参照信号からキャパシタ C に位相変調度を制御する信号が書き込みされるため、電子移動度が MOSFET と比較して低い酸化物半導体を用いる場合においても、適切な画素値の読み込み及び表示を応答速度の不足なしに実現することが可能となる。このため、高耐圧かつ低リーク特性を有する酸化物半導体を備えるトランジスタを用いて、適切な位相変調処理を実現することができる。 As described above, according to the semiconductor display device according to the present embodiment, the signal for controlling the phase modulation degree is written into the capacitor C from the ramp-shaped reference signal at an appropriate timing, so that the electron mobility is lower than that of the MOSFET. Even in the case of using an oxide semiconductor with a low sensitivity, it is possible to read and display appropriate pixel values without insufficient response speed. Therefore, appropriate phase modulation processing can be achieved using a transistor including an oxide semiconductor having high breakdown voltage and low leakage characteristics.
　また、このような構造を有することで、半導体表示装置 1 は、デジタル－アナログ変換回路を介することなく、デジタル階調値に基づいたアナログの表示信号を表示素子に出力することができる。このため、本開示における半導体表示装置 1 によれば、全画素を同じタイミングで駆動させることも可能となる。 Furthermore, by having such a structure, the semiconductor display device 1 can output an analog display signal based on the digital gradation value to the display element without going through a digital-to-analog conversion circuit. Therefore, according to the semiconductor display device 1 of the present disclosure, it is also possible to drive all pixels at the same timing.
　なお、以上の例では、第 1 トランジスタ Tr1 及び第 2 トランジスタ Tr2 は、 n 型のトランジスタであるとしたが、これに限定されるものではなく、 p 型でも制御する電圧を調整することで実装することが可能である。第 1 実施形態以外の実施形態においても n 型のトランジスタとして説明するが、同様に p 型であってもよい。 p 型である場合、酸化物半導体は、例えば、銅、銀、スズ等の酸化物を含有する物質により形成されていてもよい。 In the above example, the first transistor Tr1 and the second transistor Tr2 are N-type transistors, but they are not limited to this, and P-type transistors can also be implemented by adjusting the control voltage. Is possible. Although embodiments other than the first embodiment will be described as n-type transistors, they may be p-type transistors as well. When the oxide semiconductor is p-type, the oxide semiconductor may be formed of a substance containing an oxide of copper, silver, tin, or the like.
　また、カウンタ 200 が出力するカウント値は、カウントアップするものとしたが、これに限定されるものではない。カウンタ 200 が出力するカウント値は、最大値から最小値へとカウントダウンする値であってもよい。この場合、信号線 DT に印加される電圧も、所定最大値から所定最小値へと向かって電圧値が下がる下り方向のランプ信号であってもよい。以下の実施形態においても同様である。 Furthermore, although the count value output by the counter 200 is assumed to count up, the present invention is not limited to this. The count value output by the counter 200 may be a value that counts down from the maximum value to the minimum value. In this case, the voltage applied to the signal line DT may also be a downward ramp signal whose voltage value decreases from a predetermined maximum value to a predetermined minimum value. The same applies to the following embodiments.
　(第 2 実施形態)
　図3は、第 2 実施形態に係る半導体表示装置 1 の画素回路の一例を模式的に示す図である。画素回路 100 は、前述の第 1 実施形態の構成に加え、第 1 トランジスタ Tr1 のゲートに接続される抵抗 R を備える。 (Second embodiment)
FIG. 3 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the second embodiment. In addition to the configuration of the first embodiment described above, the pixel circuit 100 includes a resistor R connected to the gate of the first transistor Tr1.
　抵抗 R は、一端が第 1 トランジスタ Tr1 のゲートに接続され、他端が接地される。すなわち、抵抗 R の他端は、負側の電源電圧に接続されてもよい。抵抗 R は、第 1 トランジスタ Tr1 のゲート電圧をプルダウンする抵抗であり、第 1 トランジスタ Tr1 のゲートの電位を安定化する。 One end of the resistor R is connected to the gate of the first transistor Tr1, and the other end is grounded. That is, the other end of the resistor R may be connected to the negative power supply voltage. The resistor R is a resistor that pulls down the gate voltage of the first transistor Tr1, and stabilizes the potential of the gate of the first transistor Tr1.
　本実施形態の構成によっても、半導体表示装置 1 は、デジタル－アナログ変換回路を配置することなく、画素回路 100 内において、酸化物半導体を用いた適切な表示信号に基づいた表示 (位相変調) をすることが可能となる。 Also with the configuration of this embodiment, the semiconductor display device 1 can perform display (phase modulation) based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to do so.
　(第 3 実施形態)
　図4は、第 3 実施形態に係る半導体表示装置 1 の画素回路の一例を模式的に示す図である。画素回路 100 は、前述の第 2 実施形態の構成におけるプルダウン抵抗に代わりにプルアップ抵抗にする抵抗を有する。 (Third embodiment)
FIG. 4 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the third embodiment. The pixel circuit 100 has a resistor that is used as a pull-up resistor instead of the pull-down resistor in the configuration of the second embodiment described above.
　抵抗 R は、一端が第 1 トランジスタ Tr1 のゲートに接続され、他端が正側の電源電圧に接続される。抵抗 R の第 1 トランジスタ Tr1 のゲート電圧をプルアップする抵抗であり、第 1 トランジスタ Tr1 のゲートの電位を安定化する。 One end of the resistor R is connected to the gate of the first transistor Tr1, and the other end is connected to the positive power supply voltage. This is a resistor that pulls up the gate voltage of the first transistor Tr1 of the resistor R, and stabilizes the potential of the gate of the first transistor Tr1.
　本実施形態の構成によっても、半導体表示装置 1 は、デジタル－アナログ変換回路を配置することなく、画素回路 100 内において、酸化物半導体を用いた適切な表示信号に基づいた表示 (位相変調) をすることが可能となる。前述の第 2 実施形態と比較して、表示画素 (画素回路 100 ) ごとに接地するための経路が不要であるため、配線の配置面積を削減し、この配線の面積分のリソースを確保することもできる。 Also with the configuration of this embodiment, the semiconductor display device 1 can perform display (phase modulation) based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to do so. Compared to the second embodiment described above, there is no need for a grounding path for each display pixel (pixel circuit 100), so the wiring layout area can be reduced and resources can be secured for the area of this wiring. You can also do it.
　第 2 実施形態及び第 3 実施形態において、抵抗 R は、プルダウン又はプルアップする抵抗であるが、これは、例えば、第 1 トランジスタ Tr1 の導電型に依存して決定することもできる。例えば、第 1 トランジスタ Tr1 が n 型の場合には、プルダウン抵抗を配置してもよいし、第 1 トランジスタ Tr1 が p 型の場合には、プルアップ抵抗を配置してもよい。 In the second and third embodiments, the resistor R is a pull-down or pull-up resistor, but this can also be determined depending on, for example, the conductivity type of the first transistor Tr1. For example, if the first transistor Tr1 is an N-type, a pull-down resistor may be provided, and if the first transistor Tr1 is a P-type, a pull-up resistor may be provided.
　(第 4 実施形態)
　前述の各実施形態においては、画素回路内に 2 つの酸化物半導体を備える形態について説明したが、本実施形態は、このトランジスタの構成が変更された構造について説明する。 (Fourth embodiment)
In each of the embodiments described above, the pixel circuit includes two oxide semiconductors, but in this embodiment, the structure of the transistor is changed.
　図5は、第 4 実施形態に係る半導体表示装置 1 の画素回路の一例を模式的に示す図である。画素回路 100 は、メモリ回路 102 と、比較回路 104 と、第 1 トランジスタ Tr1 と、キャパシタ C と、表示素子としての位相変調素子 Pm と、を備える。 FIG. 5 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the fourth embodiment. The pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a first transistor Tr1, a capacitor C, and a phase modulation element Pm as a display element.
　メモリ回路 102 、キャパシタ C 及び位相変調素子 Pm について前述の各実施形態と同様の動作をする。 The memory circuit 102, capacitor C, and phase modulation element Pm operate in the same manner as in each of the above embodiments.
　比較回路 104 は、前述の各実施形態と同様にメモリ回路 102 に格納されているデジタルの階調値と、画素回路 100 外部に備えられるカウンタ 200 から出力されるカウンタ値とを比較して、比較結果を第 1 トランジスタ Tr1 のゲートに出力する。 Comparison circuit 104 compares the digital gradation value stored in memory circuit 102 and the counter value output from counter 200 provided outside pixel circuit 100, as in each of the above-described embodiments. Output the result to the gate of the first transistor Tr1.
　第 1 トランジスタ Tr1 は、例えば、 n 型の酸化物半導体であり、ドレインが信号線 DT に接続され、ソースがキャパシタ C の一端及び位相変調素子 Pm の一端と接続され、ゲートが比較回路 104 に接続される。 The first transistor Tr1 is, for example, an n-type oxide semiconductor, and has a drain connected to the signal line DT, a source connected to one end of the capacitor C and one end of the phase modulation element Pm, and a gate connected to the comparator circuit 104. be done.
　このように、前述の各実施形態における第 2 トランジスタを設けない構成としてもよい。この場合、比較回路 104 から出力される比較結果に基づいた信号が第 1 トランジスタ Tr1 のゲートに直接的に印加される。そして、前述の実施形態と同様に、階調値とカウンタ値とを比較した結果を取得するタイミングでランプ状の信号を信号線 DT からキャパシタ C へと転送する。 In this way, the configuration may be such that the second transistor in each of the above-described embodiments is not provided. In this case, a signal based on the comparison result output from the comparison circuit 104 is directly applied to the gate of the first transistor Tr1. Then, similar to the embodiment described above, a ramp-shaped signal is transferred from the signal line DT to the capacitor C at the timing when the result of comparing the gradation value and the counter value is obtained.
　以上のように、本実施形態の構成によっても、半導体表示装置 1 は、デジタル－アナログ変換回路を配置することなく、画素回路 100 内において、酸化物半導体を用いた適切な表示信号に基づいた表示 (位相変調) をすることが可能となる。第 2 トランジスタ Tr2 を備えないことで、トランジスタの形成領域を削減することが可能となる。 As described above, even with the configuration of this embodiment, the semiconductor display device 1 can perform display based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. (phase modulation). By not providing the second transistor Tr2, it is possible to reduce the region in which the transistor is formed.
　なお、本実施形態において、キャパシタ C を省略することも可能である。 Note that in this embodiment, it is also possible to omit the capacitor C.
　(第 5 実施形態)
　前述の第 4 実施形態では、第 2 トランジスタ Tr2 が備えられない構成について説明したが、キャパシタ C が備えられない構成であってもよい。 (Fifth embodiment)
In the fourth embodiment described above, a configuration in which the second transistor Tr2 is not provided has been described, but a configuration in which the capacitor C is not provided may also be used.
　図6は、第 5 実施形態に係る半導体表示装置 1 の画素回路の一例を模式的に示す図である。画素回路 100 は、メモリ回路 102 と、比較回路 104 と、第 1 トランジスタ Tr1 と、第 2 トランジスタ Tr2 と、位相変調素子 Pm と、を備える。 FIG. 6 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the fifth embodiment. The pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a first transistor Tr1, a second transistor Tr2, and a phase modulation element Pm.
　メモリ回路 102 、比較回路 104 、第 2 トランジスタ Tr2 、第 1 トランジスタ Tr1 、位相変調素子 Pm についての動作は、上記の実施形態と略同等である。 The operations of the memory circuit 102, comparator circuit 104, second transistor Tr2, first transistor Tr1, and phase modulation element Pm are approximately the same as in the above embodiment.
　第 1 トランジスタ Tr1 は、メモリ回路 102 に格納されている階調値に応じたタイミングで信号線 DT から信号値を位相変調素子 Pm の一端に転送する。位相変調素子 Pm は、第 1 トランジスタ Tr1 から転送された信号値に基づいて、位相変調度が制御される。 The first transistor Tr1 transfers the signal value from the signal line DT to one end of the phase modulation element Pm at a timing corresponding to the gradation value stored in the memory circuit 102. The degree of phase modulation of the phase modulation element Pm is controlled based on the signal value transferred from the first transistor Tr1.
　以上のように、キャパシタを備えない本実施形態の構成によっても、半導体表示装置 1 は、デジタル－アナログ変換回路を配置することなく、画素回路 100 内において、酸化物半導体を用いた適切な表示信号に基づいた表示 (位相変調) をすることが可能となる。 As described above, even with the configuration of this embodiment that does not include a capacitor, the semiconductor display device 1 can generate appropriate display signals using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. It becomes possible to display (phase modulation) based on
　酸化物半導体の低リーク特性から、キャパシタが無い状態においても、酸化物半導体である第 1 トランジスタ Tr1 を画素値に基づいた信号を転送するトランジスタとして用いて適切な電圧を印加して、適切な期間における表示を制御することが可能となる。例えば、位相変調素子 Pm が液晶を備える場合には、この液晶に係る容量により電圧を保持することが可能である。 Due to the low leakage characteristics of oxide semiconductors, even in the absence of a capacitor, the first transistor Tr1, which is an oxide semiconductor, is used as a transistor to transfer signals based on pixel values, and an appropriate voltage is applied to transfer signals for an appropriate period of time. It becomes possible to control the display on the screen. For example, when the phase modulation element Pm includes a liquid crystal, it is possible to hold the voltage by the capacitance related to the liquid crystal.
　(第 6 実施形態)
　図7は、第 6 実施形態に係る半導体表示装置 1 の画素回路の一例を模式的に示す図である。画素回路 100 は、第 1 実施形態の構成に、さらに、レベルシフト回路 106 を備えてもよい。すなわち、画素回路 100 は、メモリ回路 102 と、比較回路 104 と、レベルシフト回路 106 と、第 1 トランジスタ Tr1 と、第 2 トランジスタ Tr2 と、キャパシタ C と、位相変調素子 Pm と、を備える。 (Sixth embodiment)
FIG. 7 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the sixth embodiment. The pixel circuit 100 may further include a level shift circuit 106 in addition to the configuration of the first embodiment. That is, the pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a level shift circuit 106, a first transistor Tr1, a second transistor Tr2, a capacitor C, and a phase modulation element Pm.
　レベルシフト回路 106 は、比較回路 104 と、第 2 トランジスタ Tr2 との間に接続される。レベルシフト回路 106 は、比較回路 104 から出力された信号を、所定の電圧レベルへと変換して出力する。このレベルシフト回路 106 の出力が第 2 トランジスタ Tr2 を介して第 1 トランジスタ Tr1 のゲートに印加されることにより、比較回路 104 の出力を第 1 トランジスタ Tr1 を駆動するための適切な電圧レベルに変換して印加することができる。 The level shift circuit 106 is connected between the comparison circuit 104 and the second transistor Tr2. The level shift circuit 106 converts the signal output from the comparison circuit 104 to a predetermined voltage level and outputs the same. The output of this level shift circuit 106 is applied to the gate of the first transistor Tr1 via the second transistor Tr2, thereby converting the output of the comparator circuit 104 to an appropriate voltage level for driving the first transistor Tr1. can be applied.
　以上のように、本実施形態の構成によっても、半導体表示装置 1 は、デジタル－アナログ変換回路を配置することなく、画素回路 100 内において、酸化物半導体を用いた適切な表示信号に基づいた表示 (位相変調) をすることが可能となる。レベルシフト回路 106 を備えることで、酸化物半導体である第 1 トランジスタ Tr1 をより精度よく制御することが可能となる。 As described above, even with the configuration of this embodiment, the semiconductor display device 1 can perform display based on an appropriate display signal using an oxide semiconductor in the pixel circuit 100 without disposing a digital-to-analog conversion circuit. (phase modulation). By providing the level shift circuit 106, it becomes possible to control the first transistor Tr1, which is an oxide semiconductor, with more precision.
　(第 7 実施形態)
　前述の各実施形態においては、表示素子として、例えば、液晶を備える位相変調素子を用いる例について説明したが、表示素子として発光素子を用いることもできる。すなわち、酸化物半導体を有する半導体表示装置 1 の構成は、ディスプレイ等の一般的な表示を実現する発光デバイスの表示装置についても適用することができる。 (Seventh embodiment)
In each of the above-described embodiments, an example has been described in which a phase modulation element including, for example, a liquid crystal is used as a display element, but a light emitting element can also be used as a display element. That is, the configuration of the semiconductor display device 1 including an oxide semiconductor can also be applied to a display device of a light emitting device that realizes a general display such as a display.
　図8は、第 7 実施形態に係る半導体表示装置 1 の画素回路の一例を模式的に示す図である。画素回路 100 は、メモリ回路 102 と、比較回路 104 と、第 3 トランジスタ Tr3 と、第 4 トランジスタ Tr4 と、キャパシタ C と、表示素子としての発光素子 L と、を備える。 FIG. 8 is a diagram schematically showing an example of a pixel circuit of the semiconductor display device 1 according to the seventh embodiment. The pixel circuit 100 includes a memory circuit 102, a comparison circuit 104, a third transistor Tr3, a fourth transistor Tr4, a capacitor C, and a light emitting element L as a display element.
　メモリ回路 102 は、発光素子 L を発光させる強度を定義するデジタルの階調値を格納する。 The memory circuit 102 stores digital gradation values that define the intensity at which the light emitting element L emits light.
　比較回路 104 は、メモリ回路 102 に格納されている階調値と、画素回路 100 の外部に備えられるカウンタ 200 から出力されるカウント値とを比較して、比較結果を、駆動信号を出力する。 The comparison circuit 104 compares the gradation value stored in the memory circuit 102 and the count value output from the counter 200 provided outside the pixel circuit 100, and outputs the comparison result and a drive signal.
　第 3 トランジスタ Tr3 は、例えば、 n 型の酸化物半導体を備えるトランジスタであり、ドレインが電源電圧線 VCC と接続される。 The third transistor Tr3 is, for example, a transistor including an n-type oxide semiconductor, and its drain is connected to the power supply voltage line VCC.
　第 4 トランジスタ Tr4 は、例えば、 n 型の酸化物半導体を備えるトランジスタであり、ドレインが信号線 VSIG と接続され、ソースが第 3 トランジスタ Tr3 のゲートと接続され、ゲートが比較回路 104 の出力と接続される。 The fourth transistor Tr4 is, for example, a transistor including an n-type oxide semiconductor, and has a drain connected to the signal line VSIG, a source connected to the gate of the third transistor Tr3, and a gate connected to the output of the comparison circuit 104. be done.
　キャパシタ C は、一端が第 3 トランジスタ Tr3 のゲート及び第 4 トランジスタ Tr4 のソースに接続され、他端が第 3 トランジスタ Tr3 のソースと接続される。 One end of the capacitor C is connected to the gate of the third transistor Tr3 and the source of the fourth transistor Tr4, and the other end is connected to the source of the third transistor Tr3.
　発光素子 L は、例えば、 LED (Light Emitting Diode) 、有機 LED を含む、有機 EL (Electroluminescence) 又は無機 EL といった発光素子である。発光素子は、これらに限定されるものではなく、一端に印加される電圧により発光強度 (輝度) が決定される他の種類の素子であってもよい。発光素子 L は、発光強度に対応する電圧が印加される一端が第 3 トランジスタ Tr3 のソース及びキャパシタ C の他端と接続され、他端が接地される。 The light-emitting element L is, for example, a light-emitting element such as an LED (Light Emitting Diode), an organic EL (Electroluminescence) including an organic LED, or an inorganic EL. The light emitting element is not limited to these, and may be other types of elements whose emission intensity (brightness) is determined by the voltage applied to one end. One end of the light emitting element L to which a voltage corresponding to the light emission intensity is applied is connected to the source of the third transistor Tr3 and the other end of the capacitor C, and the other end is grounded.
　この画素回路 100 の動作について説明する。 The operation of this pixel circuit 100 will be explained.
　メモリ回路 102 に発光素子 L の発光強度を決定するデジタルの階調値が格納される。比較回路 104 は、メモリ回路 102 に格納されている階調値と、外部のカウンタ 200 から入力されるカウント値を比較し、カウンタ値が階調値を上回ったタイミングで第 4 トランジスタ Tr4 のゲートに第 4 トランジスタ Tr4 を駆動する信号を出力する。 Digital gradation values that determine the light emission intensity of the light emitting element L are stored in the memory circuit 102 . The comparison circuit 104 compares the gradation value stored in the memory circuit 102 with the count value input from the external counter 200, and when the counter value exceeds the gradation value, outputs a signal to the gate of the fourth transistor Tr4. Outputs a signal to drive the fourth transistor Tr4.
　第 4 トランジスタ Tr4 は、駆動する信号が入力されたタイミングで、信号線 VSIG に印加されている電圧をキャパシタ C へと転送する。信号線 VSIG には、カウンタ 200 と同期したランプ状の参照信号が印加されている。信号線 VSIG には、例えば、発光素子 L の最小輝度から最大輝度に対応する電圧を印加するための所定最小値から所定最大値までを遷移するランプ信号が印加されている。 The fourth transistor Tr4 transfers the voltage applied to the signal line VSIG to the capacitor C at the timing when the driving signal is input. A ramp-like reference signal synchronized with the counter 200 is applied to the signal line VSIG. For example, a ramp signal that transitions from a predetermined minimum value to a predetermined maximum value for applying a voltage corresponding to the minimum to maximum brightness of the light emitting element L is applied to the signal line VSIG.
　このため、比較回路 104 が第 4 トランジスタ Tr4 を駆動するタイミングで、メモリ回路 102 に格納されている階調値に対応した電圧がキャパシタ C の一端及び第 3 トランジスタ Tr3 のゲートに印加される。 Therefore, at the timing when the comparison circuit 104 drives the fourth transistor Tr4, a voltage corresponding to the gradation value stored in the memory circuit 102 is applied to one end of the capacitor C and the gate of the third transistor Tr3.
　第 3 トランジスタ Tr3 のドレインには、酸化物半導体の電源電圧となる電圧 Vcc が電源電圧線 VCC から印加される。ゲートに第 4 トランジスタ Tr4 から電圧が印加されると第 3 トランジスタ Tr3 がオンし、キャパシタ C に第 4 トランジスタ Tr4 により転送された階調値に対応する電圧が印加される。 A voltage Vcc, which is the power supply voltage of the oxide semiconductor, is applied to the drain of the third transistor Tr3 from the power supply voltage line VCC. When a voltage is applied to the gate from the fourth transistor Tr4, the third transistor Tr3 is turned on, and a voltage corresponding to the gradation value transferred by the fourth transistor Tr4 is applied to the capacitor C.
　この結果、発光素子 L のアノードに発光強度に応じた電圧が印加され、適切に電流が流れることにより、メモリ回路 102 に格納されている階調に基づいた強度で発光素子 L が発光する。 As a result, a voltage corresponding to the emission intensity is applied to the anode of the light emitting element L, and a current flows appropriately, so that the light emitting element L emits light at an intensity based on the gradation stored in the memory circuit 102.
　以上のように、本実施形態によれば、半導体表示装置 1 は、位相変調素子のみならず、一般的なディスプレイ等の表示装置における発光素子の発光強度を制御することが可能である。この形態においても、前述の各実施形態と同様に高耐圧、低リーク特性を有する酸化物半導体を用いてデジタル信号から画素回路においてアナログの強度電圧に変換した信号に基づいた発光を応答速度が不足することなく制御することが可能となる。 As described above, according to the present embodiment, the semiconductor display device 1 is capable of controlling the light emission intensity of not only a phase modulation element but also a light emitting element in a display device such as a general display. Also in this form, the response speed is insufficient for emitting light based on a signal converted from a digital signal into an analog intensity voltage in a pixel circuit using an oxide semiconductor having high breakdown voltage and low leakage characteristics as in each of the above embodiments. It becomes possible to control without
　なお、第 4 実施形態から第 7 実施形態に係る画素回路 100 において、第 2 実施形態に係るプルダウン抵抗又は第 3 実施形態に係るプルアップ抵抗を備えてもよい。また、第 4 実施形態、第 5 実施形態又は第 7 実施形態に係る画素回路 100 において、第 6 実施形態に係るレベルシフト回路を備えてもよい。 Note that the pixel circuits 100 according to the fourth to seventh embodiments may include the pull-down resistor according to the second embodiment or the pull-up resistor according to the third embodiment. Furthermore, the pixel circuit 100 according to the fourth embodiment, fifth embodiment, or seventh embodiment may include the level shift circuit according to the sixth embodiment.
　(第 1 適用例)
　以下、前述の各実施形態で説明した半導体表示装置 1 の応用例について説明する。半導体表示装置 1 は、バンドギャップが広い酸化物半導体を用いることで可視光領域において表示素子以外を透過する層を形成することも可能である。 (1st application example)
Application examples of the semiconductor display device 1 described in each of the above embodiments will be described below. In the semiconductor display device 1, by using an oxide semiconductor with a wide band gap, it is also possible to form a layer that transmits light other than the display element in the visible light region.
　半導体表示装置 1 は、例えば、図2等の位相変調素子 Pm の表示面とは逆側に適切な反射膜を形成することで、液晶素子を透過した光を反射して表示面から出力する位相変調装置として動作することができる。もちろん、半導体表示装置 1 は、液晶による位相の変調度合いは、反射によるダブルパスを考慮に入れて制御することができる。 Semiconductor display device 1 can, for example, form a suitable reflective film on the side opposite to the display surface of the phase modulation element Pm as shown in Figure 2 to reflect the light that has passed through the liquid crystal element and output it from the display surface. It can operate as a modulator. Of course, in the semiconductor display device 1, the degree of phase modulation by the liquid crystal can be controlled by taking into account the double pass caused by reflection.
　図9は、このように画素回路 100 を反射画素として用いる例であり、半導体表示装置 1 をレーザー加工装置に適用する例を示す図である。レーザー加工装置 3 は、光源 300 と、ミラー 302 と、半導体表示装置 1 を備える位相変調装置と、ミラー 304 と、光学系 306 と、集光部 308 と、支持部 310 と、を備える。 FIG. 9 is an example in which the pixel circuit 100 is used as a reflective pixel in this way, and is a diagram showing an example in which the semiconductor display device 1 is applied to a laser processing device. The laser processing device 3 includes a light source 300 , a mirror 302 , a phase modulation device including a semiconductor display device 1 , a mirror 304 , an optical system 306 , a condensing section 308 , and a support section 310 .
　光源 300 は、例えば、固体レーザー、液体レーザー又は気体レーザーであってもよいし、 LD (Laser Diode) といった半導体レーザーであってもよい。光源 300 は、例えば、パルス発信方式によりレーザー光を射出する。レーザー光は、直線偏光であってもよい。 The light source 300 may be, for example, a solid laser, a liquid laser, a gas laser, or a semiconductor laser such as a LD (Laser Diode). The light source 300 emits laser light using a pulse transmission method, for example. The laser light may be linearly polarized.
　ミラー 302 、 304 は、光源 300 から出力されるレーザー光を反射するミラーである。 Mirrors 302 and 304 are mirrors that reflect the laser light output from the light source 300.
　位相変調装置は、例えば、液晶を位相変調素子として備える半導体表示装置 1 を備える。上述のように、一例として、半導体表示装置 1 の画素回路は、反射画素を構成する回路であり、画素回路に備えられる表示素子は、液晶である。また、この半導体表示装置 1 の画素回路同士は、レーザー加工装置 3 において適切な位相変調が可能である画素ピッチ、例えば、 3.6 um 以下といった画素ピッチであってもよい。位相変調装置は、ミラー 302 により反射されたレーザー光を適切に位相変調してミラー 304 へと出力する。 The phase modulation device includes, for example, a semiconductor display device 1 that includes a liquid crystal as a phase modulation element. As described above, as an example, the pixel circuit of the semiconductor display device 1 is a circuit that constitutes a reflective pixel, and the display element included in the pixel circuit is a liquid crystal. Further, the pixel circuits of this semiconductor display device 1 may have a pixel pitch that allows appropriate phase modulation in the laser processing device 3 , for example, a pixel pitch of 3.6 μm or less. The phase modulator appropriately modulates the phase of the laser beam reflected by the mirror 302 and outputs it to the mirror 304 .
　光学系 306 は、結像光学系絵あり、例えば、位相変調装置の反射面と集光部 308 の入射瞳面とが結像関係にある両側テレセントリック光学系であってもよい。 The optical system 306 may be an imaging optical system, for example, a double-sided telecentric optical system in which the reflecting surface of the phase modulation device and the entrance pupil plane of the condenser 308 are in an imaging relationship.
　集光部 308 は、レーザー光を集光して対象 Ob の表面に照射する。 The condensing unit 308 condenses the laser beam and irradiates it onto the surface of the target Ob.
　支持部 310 は、例えば、対象 Ob を吸着することで、対象の上表面が水平面と平行になるように対象物を支持する。支持部 310 は、例えば、水平面内において並進移動、及び、回転が可能に構成されていてもよい。 The support part 310 supports the object so that the upper surface of the object is parallel to the horizontal plane, for example, by adsorbing the object Ob. The support portion 310 may be configured to be able to translate and rotate within a horizontal plane, for example.
　レーザー加工装置 3 の動作について説明する。 The operation of laser processing equipment 3 will be explained.
　光源 300 から射出されたレーザー光は、ミラー 302 で反射し、位相変調装置に入射する。位相変調装置においては、半導体表示装置 1 に反射画素として備えられる画素回路における位相変調素子において適切に位相変調がされた光が反射光としてミラー 304 へと射出される。この際、レーザー光は、位相変調装置の偏光面を改質させることなく位相変調され、射出される。 The laser beam emitted from the light source 300 is reflected by the mirror 302 and enters the phase modulation device. In the phase modulation device, light that has been appropriately phase modulated in a phase modulation element in a pixel circuit provided as a reflective pixel in the semiconductor display device 1 is emitted to the mirror 304 as reflected light. At this time, the laser light is phase modulated and emitted without modifying the polarization plane of the phase modulation device.
　位相変調装置から出力される位相変調されたレーザー光は、ミラー 304 において光学系 306 へと反射する。光学系 306 は、上述したように、位相変調装置の反射面と集光部 308 の入射瞳面とが結像関係にあるテレセントリック光学系を形成しているので、位相変調装置から出力されるレーザー光は、集光部 308 の入射瞳面において結像する。 The phase modulated laser beam output from the phase modulation device is reflected by the mirror 304 to the optical system 306 . As mentioned above, the optical system 306 forms a telecentric optical system in which the reflecting surface of the phase modulator and the entrance pupil plane of the condenser 308 are in an imaging relationship, so the laser output from the phase modulator The light is imaged at the entrance pupil plane of the condenser 308 .
　集光部 308 は、支持部 310 により適切な位置に配置されている対象 Ob の状平面において、レーザー光を集光して照射し、入射面に結像された像を所定の倍率で対象 Ob の表面に投影する。この結果、対象 Ob の表面には、投影された像のパターンの改質領域が形成される。 The condensing unit 308 focuses and irradiates the laser beam on the object Ob-shaped plane, which is placed at an appropriate position by the support unit 310, and the image formed on the incident plane is focused on the object Ob at a predetermined magnification. to be projected onto the surface of As a result, a modified region of the pattern of the projected image is formed on the surface of the object Ob.
　本適用例では、改質領域に形成するパターンを形成する像が空間位相変調装置 (半導体表示装置 1 ) によって形成される。このような空間位相変調装置は、前述した各実施形態において記載したように、高速な応答速度により精度のよい改質性能を発揮するとともに、低リーク特性を有するため消費電力を削減することも可能となる。 In this application example, an image forming a pattern to be formed in the modified region is formed by a spatial phase modulation device (semiconductor display device 1 ). As described in each of the above-mentioned embodiments, such a spatial phase modulation device exhibits highly accurate reforming performance due to its high response speed, and also has low leakage characteristics, making it possible to reduce power consumption. becomes.
　(第 2 適用例)
　図10は、半導体表示装置 1 を空間位相変調装置として備える光コンピューティング装置 4 を模式的に示す図である。光コンピューティング装置 4 は、光源 400 と、ライトバルブ 402 と、複数の半導体表示装置 1 の表示部と、検出部 404 と、を備える。 (Second application example)
FIG. 10 is a diagram schematically showing an optical computing device 4 including a semiconductor display device 1 as a spatial phase modulation device. The optical computing device 4 includes a light source 400, a light valve 402, a display section of a plurality of semiconductor display devices 1, and a detection section 404.
　本適用例においては、半導体表示装置 1 の画素回路として可視光を透過する酸化物半導体によるトランジスタと、表示素子として液晶素子を備えることで、透過型の位相変調装置を半導体表示装置 1 の表示部を用いて形成することができる。表示部は、例えば、図2等における酸化物半導体と、位相変調素子と、配線と、を備えて形成される。光コンピューティング装置 4 において、半導体表示装置 1 の表示部は、所定の間隔を有して重ね合わされる。以下、この半導体表示装置 1 の表示部を空間位相変調器と記載する。 In this application example, by providing a transistor made of an oxide semiconductor that transmits visible light as a pixel circuit of semiconductor display device 1 and a liquid crystal element as a display element, a transmissive phase modulation device can be used as a display part of semiconductor display device 1. It can be formed using The display section is formed including, for example, the oxide semiconductor shown in FIG. 2 and the like, a phase modulation element, and wiring. In the optical computing device 4 , the display portions of the semiconductor display device 1 are overlapped with each other with a predetermined interval. Hereinafter, the display section of this semiconductor display device 1 will be referred to as a spatial phase modulator.
　光源 400 は、ライトバルブ 402 に対してレーザー光を照射する。ライトバルブ 402 は、例えば、光透過型の光変調器であり、外部から入力された制御信号 (画像データ) に基づいて、光源 400 から入射したレーザー光を光強度変調する。この結果、ライトバルブ 402 は、外部から入力された制御信号に応じたパターンの画像光を生成する。 The light source 400 irradiates the light valve 402 with laser light. The light valve 402 is, for example, a light transmission type optical modulator, and modulates the light intensity of the laser light incident from the light source 400 based on a control signal (image data) input from the outside. As a result, the light valve 402 generates a pattern of image light according to the control signal input from the outside.
　ライトバルブ 402 は、例えば、生成した画像光を 1 つ目の空間位相変調器に照射する。画像光は、 1 つ目の空間位相変調器により位相変調され、これにより取得された光が 2 つ目の空間位相変調器に照射される。 2 つ目の空間位相変調器に照射された光は、 2 つ目の空間位相変調器により位相変調され、これにより取得された光が 3 つ目の空間位相変調器に照射される。 For example, the light valve 402 irradiates the first spatial phase modulator with the generated image light. The image light is phase modulated by the first spatial phase modulator, and the light acquired thereby is irradiated to the second spatial phase modulator. The light irradiated to the second spatial phase modulator is phase modulated by the second spatial phase modulator, and the light acquired thereby is irradiated to the third spatial phase modulator.
　このようにして、画像光は、それぞれの空間位相変調器によって位相変調され、最後の空間位相変調器から出力された光が検出部 404 において検出される。検出部 404 は、入力された光に基づいて、ライトバルブ 402 に入力された画像データを推定する。 In this way, the image light is phase modulated by each spatial phase modulator, and the light output from the last spatial phase modulator is detected by the detection unit 404. The detection unit 404 estimates image data input to the light valve 402 based on the input light.
　なお、本適用例において、光源 400 及びライトバルブ 402 が省略されてもよい。この場合、外部から入力された画像光が 1 つ目の空間位相変調器に照射されてもよい。また、本適用例において、光源 400 及びライトバルブ 402 が省略される場合、文字が書かれ、又は、絵が描かれた光透過性を有する紙面を、 1 つ目の空間位相変調器の光入射面上に配置し、紙面を透過した外光を 1 つ目の空間位相変調器で検出させる形態であってもよい。 Note that in this application example, the light source 400 and the light valve 402 may be omitted. In this case, the first spatial phase modulator may be irradiated with image light input from the outside. In addition, in this application example, when the light source 400 and the light valve 402 are omitted, the light-transmitting paper surface on which characters or pictures are written is used as the light input source for the first spatial phase modulator. The first spatial phase modulator may be placed on the surface of the paper and detect external light transmitted through the surface of the paper.
　本適用例では、光コンピューティング装置 4 における処理内容を決定づける位相分布が空間位相変調装置として動作する半導体表示装置 1 によって形成される。これにより、低消費電力かつ計算内容を変更可能な光コンピューティングを実現することも可能である。 In this application example, the phase distribution that determines the processing content in the optical computing device 4 is formed by the semiconductor display device 1 that operates as a spatial phase modulation device. This makes it possible to realize optical computing with low power consumption and the ability to change calculation content.
　(実装例)
　次に、前述した各実施形態に係る半導体表示装置 1 の実装例について説明する。半導体表示装置 1 は、積層された複数の半導体基板により形成されてもよい。 (Implementation example)
Next, implementation examples of the semiconductor display device 1 according to each of the embodiments described above will be described. The semiconductor display device 1 may be formed from a plurality of stacked semiconductor substrates.
　図11は、半導体表示装置 1 の積層構造の限定されない一例を示す模式図である。半導体表示装置 1 、特に、半導体表示装置 1 の画素回路 100 に該当する構成は、 2 つの半導体層おいてそれぞれ形成され、重ね合わされるように積層されて形成されてもよい。 FIG. 11 is a schematic diagram showing a non-limiting example of the stacked structure of the semiconductor display device 1. The structure corresponding to the semiconductor display device 1 , particularly the pixel circuit 100 of the semiconductor display device 1 , may be formed by forming two semiconductor layers and stacking them so as to overlap each other.
　半導体表示装置 1 は、例えば、第 1 基板 50 と、第 2 基板 52 と、を備え、これらの 2 つの基板が適切に積層されて形成されていてもよい。第 1 基板 50 と第 2 基板 52 においては、その接触面において適切に電極、配線といった導電層が形成されて適切な箇所において電気的に接続される。 The semiconductor display device 1 may include, for example, a first substrate 50 and a second substrate 52, and may be formed by appropriately laminating these two substrates. Conductive layers such as electrodes and wiring are appropriately formed on the contact surfaces of the first substrate 50 and the second substrate 52 to electrically connect them at appropriate locations.
　第 1 基板 50 は、例えば、表示素子を有し、表示素子は、第 1 基板 50 において、図の上面方向に表示素子における表示をするように配置される。半導体表示装置 1 は、表示素子に対して、適切な光学系を備えてもよい。また、半導体表示装置 1 は、表示素子を保護するべく適切なコーティングが第 1 基板 50 の上面において施されていてもよい。このような定義の場合、第 2 基板 52 は、第 1 基板 50 よりも半導体表示装置 1 の表示面から遠い位置に配置される。 The first substrate 50 has, for example, a display element, and the display element is arranged on the first substrate 50 so that a display is performed on the display element toward the top of the figure. The semiconductor display device 1 may include an appropriate optical system for the display element. Further, in the semiconductor display device 1 , an appropriate coating may be applied on the upper surface of the first substrate 50 to protect the display element. In such a definition, the second substrate 52 is placed farther from the display surface of the semiconductor display device 1 than the first substrate 50 .
　図2、図3、図4又は図6に示すように、半導体表示装置 1 の画素回路 100 が第 1 トランジスタ Tr1 と、第 2 トランジスタ Tr2 と、メモリ回路 102 と、比較回路 104 と、を備える場合、次のようにそれぞれの基板上に素子を形成してもよい。 As shown in FIG. 2, FIG. 3, FIG. 4, or FIG. 6, the pixel circuit 100 of the semiconductor display device 1 includes a first transistor Tr1, a second transistor Tr2, a memory circuit 102, and a comparison circuit 104. , elements may be formed on each substrate as follows.
　すなわち、第 1 基板 50 は、表示素子と、酸化物半導体を備える第 1 トランジスタ Tr1 及び第 2 トランジスタ Tr2 と、を少なくとも備え、第 2 基板 52 は、メモリ回路 102 及び比較回路 104 を備えてもよい。 That is, the first substrate 50 includes at least a display element, a first transistor Tr1 and a second transistor Tr2 including an oxide semiconductor, and the second substrate 52 may include a memory circuit 102 and a comparison circuit 104. .
　また、図5に示すように、第 2 トランジスタ Tr2 が備えられない場合には、少なくとも、酸化物半導体を備える第 1 トランジスタ Tr1 が第 1 基板 50 に備えられてもよい。 Furthermore, as shown in FIG. 5, if the second transistor Tr2 is not provided, at least the first transistor Tr1 including an oxide semiconductor may be provided on the first substrate 50.
　また、図7に示すように、レベルシフト回路 106 が備えられる場合には、このレベルシフト回路 106 が第 2 基板 52 に備えられてもよい。 Further, as shown in FIG. 7, when a level shift circuit 106 is provided, this level shift circuit 106 may be provided on the second substrate 52.
　また、図8に示すように、半導体表示装置 1 が発光素子 L を備える場合も同様であり、画素回路 100 におけるトランジスタを第 1 基板 50 に備え、メモリ回路 102 等を第 2 基板 52 に備える構成としてもよい。 Furthermore, as shown in FIG. 8, the same applies to the case where the semiconductor display device 1 includes the light emitting element L, in which the transistor in the pixel circuit 100 is provided on the first substrate 50, and the memory circuit 102 etc. is provided on the second substrate 52. You can also use it as
　このように第 1 基板 50 及び第 2 基板 52 を形成することで、酸化物半導体を備えるトランジスタを形成する層と、それ以外のトランジスタ、例えば、 MOSFET を備える層とを別々に形成することが可能であり、プロセスの煩雑さ、複雑さを低減することができる。 By forming the first substrate 50 and the second substrate 52 in this way, it is possible to form a layer that forms a transistor including an oxide semiconductor and a layer that forms other transistors, such as a MOSFET, separately. Therefore, the complexity and complexity of the process can be reduced.
　これらの第 1 基板 50 及び第 2 基板 52 は、例えば、チップ同士が積層される CoC (Chip on Chip) 形式で形成されてもよいし、チップとウエハを積層する CoW (Chip on Wafer) 形式で形成されてもよいし、また、ウエハとウエハを積層する WoW (Wafer on Wafer) 形式で形成されてもよい。 These first substrate 50 and second substrate 52 may be formed, for example, in a CoC (Chip on Chip) format in which chips are stacked together, or in a CoW (Chip on Wafer) format in which chips and wafers are stacked. Alternatively, it may be formed in a WoW (Wafer on Wafer) format in which wafers are stacked.
　また、これらの第 1 基板 50 及び第 2 基板 52 における配線等の電気的な接続は、マイクロバンプ、ハイブリッド接合、ビアホール等の任意の手法において形成することができる。 Further, electrical connections such as wiring on the first substrate 50 and the second substrate 52 can be formed by any method such as micro bumps, hybrid junctions, via holes, etc.
　上記の積層構造は、限定されない一例として上げたものであり、本開示に係る半導体表示装置 1 は、上記のように、別々のチップ等にそれぞれの半導体が形成されて貼り合わされるのではなく、プロセスにおいて別の層に形成されるものであってもよい。 The above stacked structure is given as a non-limiting example, and the semiconductor display device 1 according to the present disclosure does not have semiconductors formed on separate chips or the like and then bonded together, as described above. It may be formed in a separate layer in the process.
　半導体表示装置 1 のプロセスとしては、例えば、まず、メモリ回路 102 、比較回路 104 等の回路、特に、 MOSFET を構成として有する回路を第 2 半導体層として基板上に形成する。 In the process of the semiconductor display device 1, for example, first, circuits such as the memory circuit 102 and the comparison circuit 104, particularly a circuit having a MOSFET as a structure, are formed on the substrate as a second semiconductor layer.
　続いて、適切に蒸着、研磨等をして画素回路 100 と接続される配線を形成した後に、酸化物半導体を有する画素回路 100 を含む第 1 半導体層を当該形成された第 2 半導体層に積層する形で形成することができる。 Subsequently, after forming wiring to be connected to the pixel circuit 100 by appropriately performing vapor deposition, polishing, etc., a first semiconductor layer including a pixel circuit 100 including an oxide semiconductor is laminated on the formed second semiconductor layer. It can be formed in the form of
　このようなプロセスによれば、 MOSFET を備える層と、酸化物半導体を備える層とを別々の前工程で形成することなく連続で行うことが可能となるとともに、異なる層に形成される MOSFET と酸化物半導体とを適切にプロセス数を過大に増加させることなく形成することができる。 According to such a process, it is possible to form a layer containing a MOSFET and a layer containing an oxide semiconductor in succession without forming them in separate pre-processes, and it is also possible to form a layer containing a MOSFET and a layer containing an oxide semiconductor in different layers. A physical semiconductor can be appropriately formed without excessively increasing the number of processes.
　以上のように、本開示における種々の実施形態で示したように、半導体表示装置は、酸化物半導体を画素回路のスイッチ制御をするトランジスタとして用いてデジタル信号を入力するとアナログの強度情報を表示する画素を形成することが可能となる。この結果、これらの半導体表示装置によれば、高い位相安定性による集光殿向上、強画像ピッチによる視域角の拡大、積層構造によるチップサイズの縮小、また、高リフレッシュレートによる画質の向上を実現することができる。 As described above, as shown in the various embodiments of the present disclosure, the semiconductor display device displays analog intensity information when a digital signal is input using an oxide semiconductor as a transistor that controls switches in a pixel circuit. It becomes possible to form pixels. As a result, these semiconductor display devices are able to improve the light focusing area due to high phase stability, expand the viewing angle due to strong image pitch, reduce chip size due to the layered structure, and improve image quality due to high refresh rate. It can be realized.
　前述した実施形態は、以下のような形態としてもよい。 The embodiment described above may be modified as follows.
(1)
　表示素子を備える、画素回路と、
　第 1 方向と、前記第 1 方向に交わる第 2 方向において、 2 次元のアレイ状に前記画素回路が備えられる、画素アレイと、
　前記画素アレイにおける前記第 1 方向に属する前記画素回路の駆動を制御する、第 1 駆動回路と、
　前記第 1 駆動回路から前記第 1 方向に属する前記画素回路に駆動信号を送信する、第 1 信号線と、
　前記画素アレイにおける前記第 2 方向に属する前記画素回路に参照信号を送信する、第 2 駆動回路と、
　前記第 2 駆動回路から前記第 2 方向に属する前記画素回路に前記参照信号を送信する、第 2 信号線と、
　を備え、
　前記画素回路は、
　　前記画素回路の表示強度を示すデジタル階調値を格納する、メモリ回路と、
　　前記メモリ回路と接続され、前記メモリ回路に格納されている前記デジタル階調値と、カウンタ信号とを比較する、比較回路と、
　を備える、
　半導体表示装置。 (1)
a pixel circuit including a display element;
a pixel array including the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction;
a first drive circuit that controls driving of the pixel circuits belonging to the first direction in the pixel array;
a first signal line that transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction;
a second drive circuit that transmits a reference signal to the pixel circuits in the second direction in the pixel array;
a second signal line that transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction;
Equipped with
The pixel circuit is
a memory circuit that stores digital gradation values indicating display intensity of the pixel circuit;
a comparison circuit that is connected to the memory circuit and compares the digital gradation value stored in the memory circuit with a counter signal;
Equipped with
Semiconductor display device.
(2)
　出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタと、
　一端が前記比較回路と接続され、他端が前記第 1 トランジスタのゲートと接続される、第 2 トランジスタと、
　を備える、(1)に記載の半導体表示装置。 (2)
a first transistor whose output terminal is connected to a drive terminal of the display element;
a second transistor, one end of which is connected to the comparison circuit, and the other end of which is connected to the gate of the first transistor;
The semiconductor display device according to (1), comprising:
(3)
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
　　前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備え、
　　前記第 2 基板は、前記メモリ回路及び前記比較回路を備え、
　前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備える、
　(2)に記載の半導体表示装置。 (3)
formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
The first substrate includes the display element, the first transistor, and the second transistor,
The second substrate includes the memory circuit and the comparison circuit,
the first transistor and the second transistor include an oxide semiconductor;
The semiconductor display device according to (2).
(4)
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
　をさらに備え、
　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
　(2)又は(3)に記載の半導体表示装置。 (Four)
a capacitor connected between a drive terminal of the display element and a predetermined voltage;
Furthermore,
The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
The semiconductor display device according to (2) or (3).
(5)
　前記第 1 トランジスタのゲートと、電源電圧と、の間に接続される、抵抗、
　をさらに備える、(2)に記載の半導体表示装置。 (Five)
a resistor connected between the gate of the first transistor and a power supply voltage;
The semiconductor display device according to (2), further comprising:
(6)
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
　　前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備え、
　　前記第 2 基板は、前記メモリ回路及び前記比較回路を備え、
　前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備える、
　(5)に記載の半導体表示装置。 (6)
formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
The first substrate includes the display element, the first transistor, and the second transistor,
The second substrate includes the memory circuit and the comparison circuit,
the first transistor and the second transistor include an oxide semiconductor;
The semiconductor display device according to (5).
(7)
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
　をさらに備え、
　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
　(5)又は(6)に記載の半導体表示装置。 (7)
a capacitor connected between a drive terminal of the display element and a predetermined voltage;
Furthermore,
The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
The semiconductor display device according to (5) or (6).
(8)
　前記抵抗は、プルアップ抵抗又はプルダウン抵抗である、
　(5)から(7)のいずれかに記載の半導体表示装置。 (8)
the resistor is a pull-up resistor or a pull-down resistor;
The semiconductor display device according to any one of (5) to (7).
(9)
　ゲートが前記比較回路と接続され、出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタ、
　を備える、(1)に記載の半導体表示装置。 (9)
a first transistor whose gate is connected to the comparison circuit and whose output terminal is connected to the drive terminal of the display element;
The semiconductor display device according to (1), comprising:
(10)
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
　　前記第 1 基板は、前記表示素子及び前記第 1 トランジスタを備え、
　　前記第 2 基板は、前記メモリ回路及び前記比較回路を備え、
　前記第 1 トランジスタは、酸化物半導体を備える、
　(9)に記載の半導体表示装置。 (Ten)
formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
The first substrate includes the display element and the first transistor,
The second substrate includes the memory circuit and the comparison circuit,
The first transistor includes an oxide semiconductor.
The semiconductor display device according to (9).
(11)
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
　をさらに備え、
　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
　(9)又は(10)に記載の半導体表示装置。 (11)
a capacitor connected between a drive terminal of the display element and a predetermined voltage;
Furthermore,
The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
The semiconductor display device according to (9) or (10).
(12)
　前記画素回路は、
　　前記比較回路と接続され、入力された信号の電圧を制御する、レベルシフト回路、
　をさらに備える、(1)に記載の半導体表示装置。 (12)
The pixel circuit is
a level shift circuit connected to the comparison circuit and controlling the voltage of the input signal;
The semiconductor display device according to (1), further comprising:
(13)
　出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタと、
　一端が前記レベルシフト回路と接続され、他端が前記第 1 トランジスタのゲートと接続される、第 2 トランジスタと、
　を備える、(12)に記載の半導体表示装置。 (13)
a first transistor whose output terminal is connected to a drive terminal of the display element;
a second transistor, one end of which is connected to the level shift circuit, and the other end of which is connected to the gate of the first transistor;
The semiconductor display device according to (12), comprising:
(14)
　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
　　前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備え、
　　前記第 2 基板は、前記メモリ回路、前記比較回路及び前記レベルシフト回路を備え
　前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備える、
　(13)に記載の半導体表示装置。 (14)
formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
The first substrate includes the display element, the first transistor, and the second transistor,
The second substrate includes the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor include an oxide semiconductor.
The semiconductor display device according to (13).
(15)
　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
　をさらに備え、
　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
　(13)又は(14)に記載の半導体表示装置。 (15)
a capacitor connected between a drive terminal of the display element and a predetermined voltage;
Furthermore,
The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
The semiconductor display device according to (13) or (14).
(16)
　(1)から(15)のいずれかに記載の半導体表示装置を備え、
　前記画素回路は、反射画素を構成する回路であり、
　前記表示素子は、液晶である、
　空間位相変調装置。 (16)
Equipped with a semiconductor display device according to any one of (1) to (15),
The pixel circuit is a circuit that constitutes a reflective pixel,
the display element is a liquid crystal;
Spatial phase modulator.
(17)
　前記画素回路のピッチは、 3.6 um 以下である、
　(16)に記載の空間位相変調装置。 (17)
The pitch of the pixel circuit is 3.6 um or less,
The spatial phase modulation device according to (16).
　本開示の態様は、前述した実施形態に限定されるものではなく、想到しうる種々の変形も含むものであり、本開示の効果も前述の内容に限定されるものではない。各実施形態における構成要素は、適切に組み合わされて適用されてもよい。すなわち、特許請求の範囲に規定された内容及びその均等物から導き出される本開示の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更及び部分的削除が可能である。 The aspects of the present disclosure are not limited to the above-described embodiments, and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be applied in appropriate combinations. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.
　1: 半導体表示装置、
　 10: 画素アレイ、
　  100: 画素回路、
　  102: メモリ回路、
　  104: 比較回路、
　  106: レベルシフト回路、
　  Tr1、 Tr2、 Tr3、 Tr4: トランジスタ、
　  C: キャパシタ、
　  R: 抵抗
　  Pm: 位相変調素子、
　  L: 発光素子、
　 12: 制御回路、
　 14: 垂直駆動回路、
　  140: 第 1 信号線、
　 16: 水平駆動回路、
　  160: 第 2 信号線、
　200: カウンタ、
　3: レーザー加工装置、
　 300: 光源、
　 302、 304: ミラー、
　 306: 光学系、
　 308: 集光部、
　 310: 支持部、
　4: 光コンピューティング装置、
　 400: 光源、
　 402: ライトバルブ、
　 404: 検出部、
　50: 第 1 基板、
　52: 第 2 基板 1: Semiconductor display device,
10: Pixel array,
100: Pixel circuit,
102: Memory circuit,
104: Comparison circuit,
106: Level shift circuit,
Tr1, Tr2, Tr3, Tr4: transistor,
C: Capacitor,
R: Resistance Pm: Phase modulation element,
L: light emitting element,
12: Control circuit,
14: Vertical drive circuit,
140: 1st signal line,
16: Horizontal drive circuit,
160: 2nd signal line,
200: counter,
3: Laser processing equipment,
300: Light source,
302, 304: mirror,
306: Optical system,
308: Light collecting section,
310: Support part,
4: Optical computing equipment,
400: light source,
402: Light valve,
404: Detection unit,
50: 1st board,
52: 2nd board

Claims (17)

  1. 　表示素子を備える、画素回路と、
    　第 1 方向と、前記第 1 方向に交わる第 2 方向において、 2 次元のアレイ状に前記画素回路が備えられる、画素アレイと、
    　前記画素アレイにおける前記第 1 方向に属する前記画素回路の駆動を制御する、第 1 駆動回路と、
    　前記第 1 駆動回路から前記第 1 方向に属する前記画素回路に駆動信号を送信する、第 1 信号線と、
    　前記画素アレイにおける前記第 2 方向に属する前記画素回路に参照信号を送信する、第 2 駆動回路と、
    　前記第 2 駆動回路から前記第 2 方向に属する前記画素回路に前記参照信号を送信する、第 2 信号線と、
    　を備え、
    　前記画素回路は、
    　　前記画素回路の表示強度を示すデジタル階調値を格納する、メモリ回路と、
    　　前記メモリ回路と接続され、前記メモリ回路に格納されている前記デジタル階調値と、カウンタ信号とを比較する、比較回路と、
    　を備える、
    　半導体表示装置。     a pixel circuit including a display element;
    a pixel array including the pixel circuits in a two-dimensional array in a first direction and a second direction intersecting the first direction;
    a first drive circuit that controls driving of the pixel circuits belonging to the first direction in the pixel array;
    a first signal line that transmits a drive signal from the first drive circuit to the pixel circuit belonging to the first direction;
    a second drive circuit that transmits a reference signal to the pixel circuits in the second direction in the pixel array;
    a second signal line that transmits the reference signal from the second drive circuit to the pixel circuit belonging to the second direction;
    Equipped with
    The pixel circuit is
    a memory circuit that stores digital gradation values indicating display intensity of the pixel circuit;
    a comparison circuit that is connected to the memory circuit and compares the digital gradation value stored in the memory circuit with a counter signal;
    Equipped with
    Semiconductor display device.
  2. 　出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタと、
    　一端が前記比較回路と接続され、他端が前記第 1 トランジスタのゲートと接続される、第 2 トランジスタと、
    　を備える、請求項1に記載の半導体表示装置。     a first transistor whose output terminal is connected to a drive terminal of the display element;
    a second transistor, one end of which is connected to the comparison circuit, and the other end of which is connected to the gate of the first transistor;
    2. The semiconductor display device according to claim 1, comprising:
  3. 　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
    　　前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備え、
    　　前記第 2 基板は、前記メモリ回路及び前記比較回路を備え、
    　前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備える、
    　請求項2に記載の半導体表示装置。     formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
    The first substrate includes the display element, the first transistor, and the second transistor,
    The second substrate includes the memory circuit and the comparison circuit,
    the first transistor and the second transistor include an oxide semiconductor;
    3. The semiconductor display device according to claim 2.
  4. 　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
    　をさらに備え、
    　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
    　請求項2に記載の半導体表示装置。     a capacitor connected between a drive terminal of the display element and a predetermined voltage;
    Furthermore,
    The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
    3. The semiconductor display device according to claim 2.
  5. 　前記第 1 トランジスタのゲートと、電源電圧と、の間に接続される、抵抗、
    　をさらに備える、請求項2に記載の半導体表示装置。     a resistor connected between the gate of the first transistor and a power supply voltage;
    3. The semiconductor display device according to claim 2, further comprising:
  6. 　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
    　　前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備え、
    　　前記第 2 基板は、前記メモリ回路及び前記比較回路を備え、
    　前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備える、
    　請求項5に記載の半導体表示装置。     formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
    The first substrate includes the display element, the first transistor, and the second transistor,
    The second substrate includes the memory circuit and the comparison circuit,
    the first transistor and the second transistor include an oxide semiconductor;
    6. The semiconductor display device according to claim 5.
  7. 　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
    　をさらに備え、
    　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
    　請求項5に記載の半導体表示装置。     a capacitor connected between a drive terminal of the display element and a predetermined voltage;
    Furthermore,
    The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
    6. The semiconductor display device according to claim 5.
  8. 　前記抵抗は、プルアップ抵抗又はプルダウン抵抗である、
    　請求項5に記載の半導体表示装置。     the resistor is a pull-up resistor or a pull-down resistor;
    6. The semiconductor display device according to claim 5.
  9. 　ゲートが前記比較回路と接続され、出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタ、
    　を備える、請求項1に記載の半導体表示装置。     a first transistor whose gate is connected to the comparison circuit and whose output terminal is connected to the drive terminal of the display element;
    2. The semiconductor display device according to claim 1, comprising:
  10. 　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
    　　前記第 1 基板は、前記表示素子及び前記第 1 トランジスタを備え、
    　　前記第 2 基板は、前記メモリ回路及び前記比較回路を備え、
    　前記第 1 トランジスタは、酸化物半導体を備える、
    　請求項9に記載の半導体表示装置。     formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
    The first substrate includes the display element and the first transistor,
    The second substrate includes the memory circuit and the comparison circuit,
    The first transistor includes an oxide semiconductor.
    10. The semiconductor display device according to claim 9.
  11. 　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
    　をさらに備え、
    　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
    　請求項9に記載の半導体表示装置。     a capacitor connected between a drive terminal of the display element and a predetermined voltage;
    Furthermore,
    The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
    10. The semiconductor display device according to claim 9.
  12. 　前記画素回路は、
    　　前記比較回路と接続され、入力された信号の電圧を制御する、レベルシフト回路、
    　をさらに備える、請求項1に記載の半導体表示装置。     The pixel circuit is
    a level shift circuit connected to the comparison circuit and controlling the voltage of the input signal;
    2. The semiconductor display device according to claim 1, further comprising:
  13. 　出力端が前記表示素子の駆動端子と接続される、第 1 トランジスタと、
    　一端が前記レベルシフト回路と接続され、他端が前記第 1 トランジスタのゲートと接続される、第 2 トランジスタと、
    　を備える、請求項12に記載の半導体表示装置。     a first transistor whose output terminal is connected to a drive terminal of the display element;
    a second transistor, one end of which is connected to the level shift circuit, and the other end of which is connected to the gate of the first transistor;
    13. The semiconductor display device according to claim 12, comprising:
  14. 　第 1 基板と、前記第 1 基板よりも表示面から遠く配置される第 2 基板と、が積層されて形成され、
    　　前記第 1 基板は、前記表示素子、前記第 1 トランジスタ及び前記第 2 トランジスタを備え、
    　　前記第 2 基板は、前記メモリ回路、前記比較回路及び前記レベルシフト回路を備え
    　前記第 1 トランジスタ及び前記第 2 トランジスタは、酸化物半導体を備える、
    　請求項13に記載の半導体表示装置。     formed by laminating a first substrate and a second substrate disposed farther from the display surface than the first substrate,
    The first substrate includes the display element, the first transistor, and the second transistor,
    The second substrate includes the memory circuit, the comparison circuit, and the level shift circuit, and the first transistor and the second transistor include an oxide semiconductor.
    14. The semiconductor display device according to claim 13.
  15. 　前記表示素子の駆動端子と、所定電圧と、の間に接続される、キャパシタ、
    　をさらに備え、
    　前記第 2 駆動回路は、所定最小電圧から所定最大電圧まで変化するランプ信号を前記参照信号として出力し、前記第 1 トランジスタが駆動するタイミングで、前記キャパシタに前記参照信号を書き込む、
    　請求項13に記載の半導体表示装置。     a capacitor connected between a drive terminal of the display element and a predetermined voltage;
    Furthermore,
    The second drive circuit outputs a ramp signal that varies from a predetermined minimum voltage to a predetermined maximum voltage as the reference signal, and writes the reference signal into the capacitor at a timing when the first transistor is driven.
    14. The semiconductor display device according to claim 13.
  16. 　請求項1に記載の半導体表示装置を備え、
    　前記画素回路は、反射画素を構成する回路であり、
    　前記表示素子は、液晶である、
    　空間位相変調装置。     comprising the semiconductor display device according to claim 1,
    The pixel circuit is a circuit that constitutes a reflective pixel,
    the display element is a liquid crystal;
    Spatial phase modulator.
  17. 　前記画素回路のピッチは、 3.6 um 以下である、
    　請求項16に記載の空間位相変調装置。     The pitch of the pixel circuit is 3.6 um or less,
    17. The spatial phase modulation device according to claim 16.
PCT/JP2023/015455 2022-05-20 2023-04-18 Semiconductor display device and spatial phase modulation device WO2023223745A1 (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524844A (en) * 2003-04-24 2006-11-02 ディスプレイテック，インコーポレイテッド Microdisplay and interface on a single chip
JP2009110006A (en) * 2000-03-30 2009-05-21 Seiko Epson Corp Display device
US20100026613A1 (en) * 2006-05-30 2010-02-04 Thomson Licensing Methods for Sequential Color Display by Modulation of Pulses
US20100220085A1 (en) * 2009-03-02 2010-09-02 Cheng-Chi Yen Display controlling system and method thereof
JP2011013517A (en) * 2009-07-03 2011-01-20 Victor Co Of Japan Ltd Liquid crystal display device and method for driving the same
US20120075320A1 (en) * 2007-01-04 2012-03-29 Micron Technology, Inc. Defect mapping for a digital display
JP2020508485A (en) * 2017-02-14 2020-03-19 ナンヤン テクノロジカル ユニヴァーシティー Sub-pixel circuit, and display system and electronic device having the same
JP2020109450A (en) * 2019-01-07 2020-07-16 ソニー株式会社 Spatial optical modulation system, spatial optical modulation device, and display unit
JP2021105705A (en) * 2019-12-26 2021-07-26 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 Pixel circuit controlling light-emitting element

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009110006A (en) * 2000-03-30 2009-05-21 Seiko Epson Corp Display device
JP2006524844A (en) * 2003-04-24 2006-11-02 ディスプレイテック，インコーポレイテッド Microdisplay and interface on a single chip
US20100026613A1 (en) * 2006-05-30 2010-02-04 Thomson Licensing Methods for Sequential Color Display by Modulation of Pulses
US20120075320A1 (en) * 2007-01-04 2012-03-29 Micron Technology, Inc. Defect mapping for a digital display
US20100220085A1 (en) * 2009-03-02 2010-09-02 Cheng-Chi Yen Display controlling system and method thereof
JP2011013517A (en) * 2009-07-03 2011-01-20 Victor Co Of Japan Ltd Liquid crystal display device and method for driving the same
JP2020508485A (en) * 2017-02-14 2020-03-19 ナンヤン テクノロジカル ユニヴァーシティー Sub-pixel circuit, and display system and electronic device having the same
JP2020109450A (en) * 2019-01-07 2020-07-16 ソニー株式会社 Spatial optical modulation system, spatial optical modulation device, and display unit
JP2021105705A (en) * 2019-12-26 2021-07-26 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 Pixel circuit controlling light-emitting element

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