WO2023221227A1 - 内存条热插拔方法及装置、内存条 - Google Patents

内存条热插拔方法及装置、内存条 Download PDF

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Publication number
WO2023221227A1
WO2023221227A1 PCT/CN2022/099681 CN2022099681W WO2023221227A1 WO 2023221227 A1 WO2023221227 A1 WO 2023221227A1 CN 2022099681 W CN2022099681 W CN 2022099681W WO 2023221227 A1 WO2023221227 A1 WO 2023221227A1
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Prior art keywords
power
memory
memory module
abnormal
button
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PCT/CN2022/099681
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English (en)
French (fr)
Inventor
黄国维
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020227039437A priority Critical patent/KR20230161864A/ko
Priority to JP2022562319A priority patent/JP2024523768A/ja
Priority to EP22760642.3A priority patent/EP4300319A4/en
Priority to US17/821,760 priority patent/US12008245B2/en
Publication of WO2023221227A1 publication Critical patent/WO2023221227A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/186—Securing of expansion boards in correspondence to slots provided at the computer enclosure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and specifically to a memory stick hot-swapping method, a memory stick hot-swapping device, and a memory stick.
  • DIMM Dual-Inline-Memory-Modules
  • a method for hot-swapping a memory stick including: when the system is in a power-on state, in response to a triggering operation of a replacement button of an abnormal memory stick, copying data on the abnormal memory stick to the idle memory stick; after the data is copied, the abnormal memory stick is powered off and the abnormal memory stick is replaced with a new memory stick; in response to the triggering operation of the power-on button of the new memory stick, the abnormal memory stick is The new memory module is powered on.
  • powering off the abnormal memory bar includes: pulling down the power management chip enable signal corresponding to the abnormal memory bar to power off the abnormal memory bar. .
  • the method further includes: removing the abnormal memory bar from the memory mapping table of the system.
  • the method further includes: adding the new memory bar to the memory mapping table of the system.
  • the method further includes: determining the physical address of the abnormal memory stick according to the logical address of the abnormal data.
  • copying the data on the abnormal memory bar to a free memory bar includes: stopping writing operations on the abnormal memory bar, and copying the abnormal memory bar through a read operation.
  • the data in the abnormal memory bar is stored in the cache; the data in the cache is written into the free memory bar.
  • powering on the new memory bar includes: pulling up a power management chip enable signal corresponding to the new memory bar to power on the new memory bar.
  • a memory module hot-swap device including: a data copy module configured to, when the system is in a power-on state, respond to a triggering operation of a replacement button on an abnormal memory module.
  • the data on the abnormal memory stick is copied to the free memory stick;
  • the power-off module is used to power off the abnormal memory stick after the data is copied, and replace the abnormal memory stick with a new memory stick;
  • the power-on module used to power on the new memory module in response to the triggering operation of the power-on button on the new memory module.
  • a memory stick including: a memory stick body and a replacement button and a power-on button provided on the memory stick body; wherein the replacement button and the power-on button are respectively
  • the input and output interface is connected to a repeater, and the repeater is used to send the system management bus signal to the CPU when a level conversion occurs in the input and output interface; the CPU is used to send the system management bus signal to the CPU after receiving the system management bus signal. Power on or off the memory module.
  • a first power supply and a first resistor are further included; wherein the input and output interface is grounded through the replacement button, and the first power supply is provided between the input and output interface and the On the connection line of the replacement button, the first resistor is set on the connection line of the first power supply.
  • a second power supply and a second resistor are further included; wherein the input and output interface is grounded through the power-on button, and the second power supply is provided between the input and output interface and the power button.
  • the second resistor is set on the connection line of the second power supply.
  • a third power supply is further included; wherein the input and output interface is grounded, and the replacement button is provided between the third power supply and the input and output interface.
  • a fourth power supply is further included; wherein the input and output interface is grounded, and the power-on button is provided between the fourth power supply and the input and output interface.
  • both the power-on button and the replacement button are switches.
  • the CPU is connected to the power management chip of the memory stick, and the CPU controls the power-off of the memory stick by pulling the power management chip enable signal low;
  • the CPU controls the power-on of the memory module by pulling the enable signal of the power management chip high.
  • Figure 1 schematically shows a flow chart of a memory module hot-swapping method according to an exemplary embodiment of the present disclosure
  • Figure 2 schematically illustrates a flow chart for determining an abnormal memory stick from abnormal data according to an exemplary embodiment of the present disclosure
  • Figure 3 schematically shows a flow chart of data copying on an abnormal memory stick according to an exemplary embodiment of the present disclosure
  • Figure 4 schematically shows a step flow chart of a memory module hot-swapping method according to an exemplary embodiment of the present disclosure
  • Figure 5 schematically shows a block diagram of a memory stick hot-swap device according to an exemplary embodiment of the present disclosure
  • Figure 6 schematically shows a schematic structural diagram of a memory stick according to an exemplary embodiment of the present disclosure
  • Figure 7 schematically shows a schematic diagram 2 of a memory stick structure according to an exemplary embodiment of the present disclosure
  • Figure 8 schematically shows a memory stick structure schematic diagram three according to an exemplary embodiment of the present disclosure
  • FIG. 9 schematically shows a structural diagram of a motherboard in which the above-mentioned memory module is inserted according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • DDR4 is the abbreviation of the fourth generation DDR SDRAM
  • DDR5 is the abbreviation of the fifth generation DDR SDRAM
  • DDR SDRAM is the abbreviation of Double Data Rate SDRAM in English
  • the Chinese translation is double rate SDRAM
  • SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory , translated as synchronous dynamic random access memory, the synchronization object is the system clock frequency. Therefore, combined, DDR4 is the fourth generation of double-rate synchronous dynamic random access memory, and DDR5 is the fifth generation of double-rate synchronous dynamic random access memory. From DDR4 to DDR5, the power supply unit of the DIMM memory module has been moved from the motherboard to the DIMM memory module. The power supply on each DIMM memory module is independent. Therefore, each DIMM memory module can be powered on and off independently.
  • embodiments of the present disclosure provide a memory stick hot-swapping method, which is applied to memories such as DDR5 that can independently power the memory sticks, so that abnormal memory sticks can be replaced without shutting down the system.
  • implement a hot-swappable memory module method implement a hot-swappable memory module method.
  • the memory module hot-swap method may include the following steps:
  • Step S110 When the system is powered on, in response to the triggering operation of the replacement button of the abnormal memory module, copy the data on the abnormal memory module to the free memory module;
  • Step S120 after the data is copied, power off the abnormal memory module and replace the abnormal memory module with a new memory module;
  • Step S130 In response to the triggering operation of the power-on button of the new memory module, power on the new memory module.
  • the memory stick hot-swapping method can first copy the data on the abnormal memory stick to a free memory stick in response to the triggering operation of the replacement button of the abnormal memory stick when the system is in a working state. After the data is copied, only the abnormal memory module is powered off, and then the abnormal memory module can be replaced with a new memory module; and then in response to the triggering operation of the power-on button of the new memory module, the new memory module can be powered on. electricity.
  • the above whole process can realize an abnormal memory module replacement process when the system is in working state, which is a hot-swapping method of the memory module.
  • step S110 when the system is in the power-on state, in response to the triggering operation of the replacement button of the abnormal memory bar, the data on the abnormal memory bar is copied to the free memory bar.
  • the system may include a computer system or a server system, which is a machine system that receives and stores information according to human requirements, automatically performs data processing and calculation, and outputs result information.
  • the system usually needs to store data, so the system also contains a memory stick. During the working process, the system can read data from the memory stick or store data into the memory stick.
  • the system is in a power-on state, which may mean that the system is in a boot state, or the system is in a working state, for example, the system is performing data access operations, etc.
  • the system being powered on here can also be understood to mean that the system is not shut down, and there is no need to shut down the system during the entire hot-swap process of the memory module.
  • the abnormal memory stick may be a memory stick where a data reading error occurs, that is, abnormal data is found in the abnormal memory stick. After abnormal data is discovered, the physical address of the abnormal memory module can be determined based on the logical address of the abnormal data.
  • FIG. 2 a flow chart for determining an abnormal memory stick from abnormal data is shown.
  • the memory controller when the memory controller discovers that there is abnormal data in the memory data, the memory controller can obtain the logical address of the abnormal data from the logical address mapping area. The memory controller then based on the conversion relationship between the logical address and the physical address, Convert the logical address of the abnormal data into the physical address of the abnormal memory module, so that the corresponding memory module DIMM can be found based on the physical address.
  • the physical address mapping area in the memory controller corresponds to the physical address of the memory stick in the memory mapping table. The specific abnormal memory bank can be determined from the physical address in the physical address mapping area.
  • the replacement button may be a physical button provided on the abnormal memory module, or it may be a virtual button added on the BMC (Baseboard Management Controller) interface.
  • the replacement button is connected to the system's CPU (Central Processing Unit, central processing unit) through a repeater, and notifies the CPU or MC (Memory Controller) through Smbus (System management bus, system management bus) or I3C (Improved Inter Integrated Circuit) signal. Memory controller) needs to power off the corresponding memory module and replace it.
  • CPU Central Processing Unit, central processing unit
  • MC Memory Controller
  • Smbus System management bus, system management bus
  • I3C Improved Inter Integrated Circuit
  • the memory module hot-swapping method can respond to the triggering operation of the replacement button and first copy the data in the abnormal memory module to the free memory module. in the memory stick to save the data in the abnormal memory stick.
  • the trigger operation for changing the key may be a single click operation, a double click operation, a long press operation, or other trigger operations.
  • the exemplary embodiments of the present disclosure do not specifically limit the specific form of the trigger operation.
  • FIG. 3 a flow chart of data copying on an abnormal memory bar is shown.
  • the free memory bar here may be a normal memory bar that stores some data, or it may be a normal memory bar that does not store data.
  • step S120 after the data is copied, the abnormal memory module is powered off and the abnormal memory module is replaced with a new memory module.
  • the abnormal memory bar after the data in the abnormal memory bar is copied to the free memory bar, the abnormal memory bar can be powered off.
  • the specific power-off operation can be that after the CPU or MC receives the Smbus or I3C signal, the abnormal memory module can be powered off by pulling down the power management chip enable signal corresponding to the abnormal memory module.
  • the power management chip enable signal is the enable signal when the power management chip (Power Management IC, PMIC) is working.
  • the indicator light can also be used to indicate whether the abnormal memory module has been powered off. For example, set the replacement key to one with a two-color indicator light. After pressing the replacement button, the indicator light changes color, indicating that the abnormal memory module has been powered off.
  • the abnormal memory module After the abnormal memory module is powered off, the abnormal memory module can be replaced with a new one. This process can be done manually.
  • the abnormal memory module needs to be removed from the memory mapping table of the system so that the abnormal memory module is no longer recorded in the system.
  • the memory mapping table is a record table that stores the physical address of the memory stick.
  • Abnormal memory sticks usually need to be removed from the memory mapping table so that the system can obtain the physical address of the normal memory stick from the memory mapping table.
  • step S130 in response to the triggering operation of the power-on button of the new memory module, the new memory module is powered on.
  • a trigger operation is required for the newly inserted new memory stick.
  • the trigger operation can be a single click operation, a double click operation, a long press operation, or
  • the exemplary embodiments of the present disclosure do not specifically limit the specific form of the triggering operations.
  • the power-on button can notify the CPU or the memory controller to perform power-on initialization of the new memory module.
  • the power-on button may be a physical button provided on the new memory module, or it may be a virtual button added on the BMC interface.
  • the power-on button is connected to the system's CPU or memory controller through a repeater, and notifies the CPU or memory controller through Smbus or I3C signals that the corresponding memory module needs to be powered on.
  • the specific power-on operation can be that after the CPU or memory controller receives the Smbus or I3C signal, the new memory module can be powered on by raising the power management chip enable signal corresponding to the new memory module.
  • the power management chip enable signal is the enable signal when the power management chip (Power Management IC, PMIC) is working.
  • the indicator light can also be used to indicate whether the memory module has been powered on.
  • set the power-on button to be a button with a two-color indicator light. After pressing the power-on button, the indicator light changes color, indicating that the new memory module has been powered on.
  • the system In actual applications, after the new memory stick is powered on, the system also needs to initialize and adjust the new memory stick to make the new memory stick in the best working condition. After that, the system can add the new memory stick to the system's memory map. table for normal use of the system. Among them, initializing and adjusting new memory modules are conventional technical means and will not be described again here.
  • the memory module hot-swapping method provided by the exemplary embodiments of the present disclosure can respond to the triggering operation of the abnormal memory module replacement button when the system is powered on, and after copying the data of the abnormal memory module to the free memory module, Powering off the abnormal memory module and replacing it with a new one is equivalent to replacing the abnormal memory module without shutting down the system. There is no need to shut down the system during the replacement process, thus reducing the time required to replace the abnormal memory module. Time-consuming, when the system is powered on or working, an abnormal memory module hot-swapping method is implemented, which provides convenience to users.
  • step S401 is entered.
  • the replacement button of the abnormal memory module is triggered.
  • Step S402 in response to the trigger operation of the replacement button of the abnormal memory module, the data on the abnormal memory module is Copy to the free memory stick, referred to as copying data; Step S403, after the data is copied, pull down the power management chip enable signal to power off the abnormal memory stick; Step S404, after the abnormal memory stick is powered off, replace the abnormal memory
  • the strip is a new memory strip; step S405, trigger the power-on button of the new memory strip; step S406, in response to the triggering operation of the power-on button of the new memory strip, power on and initialize the new memory strip; step S407, after initialization, Add the new memory stick to the system's memory mapping table so that the new memory stick can work properly.
  • the memory module hot-swap device 500 includes: a data copy module 510, a power-off module 520, a power-on module 530, a removal module 540, an addition module 550 and an address determination module 560; wherein,
  • the data copy module 510 can be used to copy the data on the abnormal memory stick to a free memory stick in response to the trigger operation of the replacement button on the abnormal memory stick when the system is powered on;
  • the power-off module 520 can be used to power off the abnormal memory module after the data is copied, and replace the abnormal memory module with a new memory module;
  • the power-on module 530 may be configured to power on the new memory module in response to the triggering operation of the power-on button on the new memory module.
  • the power-off module 520 may be used to pull down the power management chip enable signal corresponding to the abnormal memory bar, so as to power off the abnormal memory bar.
  • the removal module 540 may be used to remove the abnormal memory strip from the memory mapping table of the system.
  • the adding module 550 may be used to add the new memory stick to the memory mapping table of the system.
  • the address determination module 560 may be configured to determine the physical address of the abnormal memory stick according to the logical address of the abnormal data.
  • the data copy module 510 can be used to stop the writing operation on the abnormal memory bar, and store the data in the abnormal memory bar in the cache through the read operation; The data in the cache is written into the free memory bank.
  • the power-on module 530 may be used to pull up the power management chip enable signal corresponding to the new memory bar to power on the new memory bar.
  • the memory stick includes: a memory stick body 610. and the replacement button 620 and the power-on button 630 provided on the memory module body 610; wherein,
  • the replacement button 620 and the power-on button 630 are respectively connected to the repeater HUB640 through the input and output interface IO.
  • the repeater 640 can be used to send the system management bus signal to the CPU when a level conversion occurs in the input and output interface IO, that is to say,
  • the relay 640 needs to be connected to the CPU, and the CPU can be a component in the system that exists independently of the memory module.
  • the memory module needs to be connected to the CPU through a repeater 640 so that the memory module can be powered on or off through the CPU. In other words, after the CPU receives the system management bus signal, it can power on or off the memory module.
  • the input and output interface IO connected to the replacement button 620 and the power-on button 630 can be different PIN pins of the same IO chip, one of which is connected to the replacement button 620 and the other PIN is connected to the power-on button 630 connected.
  • the above-mentioned system management bus signal may include the Smbus or I3C signal described in the previous embodiment.
  • the level conversion of the input and output interface IO may be when the replacement button 620 is triggered, and the level at the input and output interface IO is converted from a high level to a low level; or when the replacement button is triggered.
  • the level at the input and output interface IO changes from low level to high level.
  • the level conversion of the input and output interface IO can also occur when the power-on button 630 is triggered, and the level of the input-output interface IO changes from high level to low level; or when the power-on button 630 is triggered, the input The level at the output interface IO is converted from low level to high level.
  • the memory stick may also include a first power supply 710 and a first resistor 720, wherein the input and output interface IO is grounded through the replacement button 620, and the first power supply 710 is set at the input
  • the connection between the output interface IO and the replacement button 620 provides a high level for the input and output interface IO.
  • a first resistor 720 is also provided on the connection line of the first power supply 710, and the first resistor 710 can play a voltage stabilizing role.
  • the resistance of the first resistor 720 can be set according to the actual situation, and the exemplary embodiment of the present disclosure does not impose any special limitation on this.
  • the input and output interface IO after pressing the replacement button 620, the input and output interface IO will be connected to the ground terminal, so that the level at the input and output interface IO is converted from high level to low level.
  • the input and output interface IO here can be the first PIN pin 1 of an IO chip.
  • the replacement button 620 can be a switch. When the replacement button 620 is pressed, the input and output interface IO and the ground terminal can be connected.
  • the memory module may further include a second power supply 730 and a second resistor 740 , wherein the input and output interface IO is grounded through the power button 630 , and the second power supply 730 is set on the input
  • the connection between the output interface IO and the power-on button 630 provides a high level for the input and output interface IO.
  • a second resistor 740 is also provided on the connection line of the second power supply 730, and the second resistor 740 can play a voltage stabilizing role.
  • the resistance value of the second resistor 740 can be set according to the actual situation, and the exemplary embodiment of the present disclosure does not impose special limitations on this.
  • the input-output interface IO after pressing the power-on button 630, the input-output interface IO will be connected to the ground terminal, so that the level at the input-output interface IO is converted from high level to low level.
  • the input and output interface IO here can be the second PIN pin 2 of an IO chip.
  • the power-on button 630 may be a switch. When the power-on button 630 is pressed, the input-output interface IO and the ground terminal can be connected.
  • the memory stick may also include a third power supply 810.
  • the input-output interface IO Directly connected to ground, it can provide a low level for the input and output interface IO.
  • the replacement button 620 is disposed between the third power supply 810 and the input-output interface IO. When the replacement button 620 is pressed or triggered, the third power supply 810 will be connected to the input-output interface IO, thereby causing the input-output interface IO to The level changes from low level to high level.
  • the input and output interface IO here can be the first PIN 1 of an IO chip.
  • a resistor may or may not be provided next to the third power supply 810, which is not specifically limited in the exemplary embodiments of the present disclosure.
  • the resistance value of the resistor can also be set according to the actual situation, and is not limited here.
  • the replacement button 620 may be a switch. After the replacement button 620 is pressed, the third power supply 810 and the input and output interface IO may be turned on.
  • the memory stick may also include a fourth power supply 820.
  • the level at the input-output interface IO is initially low. level.
  • the fourth power supply 820 will be connected to the input-output interface IO, thereby causing the input and output The level at interface IO is converted from low level to high level.
  • the input and output interface IO here can be the second PIN pin 2 of an IO chip.
  • the above-mentioned power-on button 630 may also be a switch. After pressing the power-on button 630, the fourth power supply 820 and the input and output interface IO can be turned on.
  • the CPU in order to power on or off the memory stick through the CPU, as shown in Figure 6, the CPU also needs to be connected to the power management chip PMIC650 of the memory stick.
  • the CPU pulls the power management chip enable signal If it is low, the memory module can be controlled to power off; the CPU can control the memory module to power on by pulling the power management chip enable signal high.
  • the input and output interface IO is connected to the gold finger of the memory stick through the repeater HUB.
  • the gold finger connects the repeater HUB to the CPU through the wiring on the motherboard, thereby realizing signal transmission.
  • the memory module provided by the embodiment of the present disclosure can switch between the power supply and the ground terminal by connecting the input and output interfaces to the power supply or ground terminal, thereby realizing level conversion at the input and output interface; level conversion occurs at the input and output interface
  • the repeater can send the system management bus signal to the CPU, and the memory module can be powered on or off through the CPU, so that the abnormal memory module can be powered off and replaced and the newly replaced memory module can be powered on, that is, It can be used in the hot-swapping process of the memory module described in the above embodiment.
  • each DIMM has an independent PMIC, so that each DIMM can be processed independently. Power on and off.
  • the sub-memory controller (SMC) of each channel of the CPU is also independent, and one SMC controls one DIMM.
  • SMC0 on the CPU controls DIMM0
  • SMC1 controls DIMM1.
  • SMC0 When replacing DIMM0, only SMC0 is required to control it; when replacing DIMM1, only SMC1 is required to control it.
  • the computer program product includes one or more computer commands.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer commands may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or include one or more data storage devices such as servers and data centers that can be integrated with the medium.
  • the available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, solid state disk (SSD)), etc.
  • the computer may include the aforementioned device.

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Abstract

一种内存条热插拔方法、内存条热插拔装置、内存条，涉及集成电路技术领域。该内存条热插拔方法包括：在***处于上电状态下，响应于异常内存条的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；响应于所述新内存条的上电按键的触发操作，对所述新内存条上电。提供了一种在***不下电的情况下对内存条进行热插拔的方式。 (图1)

Description

内存条热插拔方法及装置、内存条
相关申请的交叉引用
本申请要求于2022年05月18日提交的申请号为202210550689.X、名称为“内存条热插拔方法及装置、内存条”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种内存条热插拔方法、内存条热插拔装置、内存条。
背景技术
DIMM(Dual-Inline-Memory-Modules，双列直插式存储模块)内存条提供了64位的数据通道，得到了广泛应用。
一般情况下，在内存条的实际应用中，是无法进行热插拔的。一旦内存条出现异常，对内存条的更换必须在***下电的情况下进行。
然而，通常***的下电过程耗时较长，导致内存条的更换极不便利。
发明内容
根据本公开的第一方面，提供一种内存条热插拔方法，包括：在***处于上电状态下，响应于异常内存条的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；响应于所述新内存条的上电按键的触发操作，对所述新内存条上电。
在本公开的一种示例性实施方式中，所述对所述异常内存条下电，包括：拉低所述异常内存条对应的电源管理芯片使能信号，以使所述异常内存条下电。
在本公开的一种示例性实施方式中，在所述异常内存条下电后，所述方法还包括：将所述异常内存条从***的内存映射表中移除。
在本公开的一种示例性实施方式中，在所述新内存条上电后，所述方法还包括：将所述新内存条添加到***的内存映射表中。
在本公开的一种示例性实施方式中，所述方法还包括：根据异常数据的逻辑地址，确定所述异常内存条的物理地址。
在本公开的一种示例性实施方式中，所述将所述异常内存条上的数据复制到空闲内存条中，包括：停止对所述异常内存条的写入操作，通过读操作将所述异常内存条中的数据存入缓存中；将所述缓存中的数据写入所述空闲内存条中。
在本公开的一种示例性实施方式中，对所述新内存条上电，包括：拉高所述新内存条对应的电源管理芯片使能信号，以使所述新内存条上电。
根据本公开的第二方面，提供一种内存条热插拔装置，包括：数据复制模块，用于在***处于上电状态下，响应于异常内存条上的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；下电模块，用于在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；上电模块，用于响应于所述新内存条上的上电按键的触发操作，对所述新内存条上电。
根据本公开的第三方面，提供一种内存条，包括：内存条本体和设置在所述内存条本体上的更换按键和上电按键；其中，所述更换按键和所述上电按键分别通过输入输出接口与中转器连接，所述中转器用于在所述输入输出接口发生电平转换时，将***管理总线信号发送给CPU；所述CPU用于在接收到所述***管理总线信号后，对所述内存条上电或下电。
在本公开的一种示例性实施方式中，还包括第一电源和第一电阻；其中，所述输入输出接口通过所述更换按键接地，所述第一电源设置在所述输入输出接口和所述更换按键的连线上，所述第一电阻设置在所述第一电源的连接线上。
在本公开的一种示例性实施方式中，还包括第二电源和第二电阻；其中，所述输入输出接口通过所述上电按键接地，所述第二电源设置在所述输入输出接口和所述上电按键的连线上，所述第二电阻设置在所述第二电源的连接线上。
在本公开的一种示例性实施方式中，还包括第三电源；其中，所述输入输出接口接地，所述更换按键设置在所述第三电源和所述输入输出接口之间。
在本公开的一种示例性实施方式中，还包括第四电源；其中，所述输入输出接口接地，所述上电按键设置在所述第四电源和所述输入输出接口之间。
在本公开的一种示例性实施方式中，所述上电按键和所述更换按键均为开关。
在本公开的一种示例性实施方式中，所述CPU与所述内存条的电源管理芯片相连，所述CPU通过将电源管理芯片使能信号拉低，以控制所述内存条下电；所述CPU通过将所述电源管理芯片使能信号拉高，以控制所述内存条上电。
附图说明
图1示意性示出了根据本公开的示例性实施方式的一种内存条热插拔方法的流程图；
图2示意性示出了根据本公开的示例性实施方式的一种由异常数据确定异常内存条的流程图；
图3示意性示出了根据本公开的示例性实施方式的一种异常内存条上的数据复制流程图；
图4示意性示出了根据本公开的示例性实施方式的一种内存条热插拔方法的步骤流程图；
图5示意性示出了根据本公开的示例性实施方式的一种内存条热插拔装置的框图；
图6示意性示出了根据本公开的示例性实施方式的一种内存条结构示意图一；
图7示意性示出了根据本公开的示例性实施方式的一种内存条结构示意图二；
图8示意性示出了根据本公开的示例性实施方式的一种内存条结构示意图三；
图9示意性示出了根据本公开的示例性实施方式的一种插设上述内存条的主板的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还 可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。另外，下面所有的术语“第一”、“第二”、“第三”仅是为了区分的目的，不应作为本公开内容的限制。
DDR4是***DDR SDRAM的简称，DDR5是第五代DDR SDRAM的简称，DDR SDRAM是英文Double Data Rate SDRAM的缩写，中文译为双倍速率SDRAM，而SDRAM又是Synchronous Dynamic Random Access Memory的缩写，译为同步动态随机存取存储器，同步对象是***时钟频率。因此，组合起来而言，DDR4就是***双倍速率同步动态随机存取存储器，DDR5就是第五代双倍速率同步动态随机存取存储器。从DDR4到DDR5，DIMM内存条的供电单元已经由主板上移动到了DIMM内存条上，每根DIMM内存条上的供电都是独立的。因此，可以对每个DIMM内存条进行单独上下电。
基于此，本公开实施例提供了一种内存条热插拔方法，应用于如DDR5这种可以对内存条进行独立供电的存储器，可以实现在不关闭***的情况下，对异常内存条进行更换，实现一种内存条的热插拔方式。参照图1，该内存条热插拔方法可以包括以下步骤：
步骤S110，在***处于上电状态下，响应于异常内存条的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；
步骤S120，在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；
步骤S130，响应于所述新内存条的上电按键的触发操作，对所述新内存条上电。
本公开示例性实施方式提供的内存条热插拔方法，可以在***处于工作状态下，响应于异常内存条的更换按键的触发操作，先将异常内存条上的数据复制到空闲内存条中，并在数据复制完后，仅仅对异常内存条下电，接着，可以将异常内存条更换为新内存条；再响应于新内存条的上电按键的触发操作，可以完成对新内存条的上电。上述整个过程可以实现一种在***处于工作状态下的异常内存条更换过程，也就是内存条的一种热插拔方法。
下面，结合具体的操作过程对上述内存条热插拔方法进行具体说明：
在步骤S110中，在***处于上电状态下，响应于异常内存条的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中。
本公开示例性实施方式中，***可以包括计算机***或者服务器***，是一种按人的要求接收和存储信息，自动进行数据处理和计算，并输出结果信息的机器***。
***通常需要存储数据，因此，***也包含有内存条，***在工作过程中，可以从内存条中读取数据，也可以将数据存储到内存条中。
本公开示例性实施方式中，***处于上电状态可以是***处于开机状态，也可以是***正处于工作状态，例如，***正在进行数据存取运算等状态。此处的***处于上电状态还可以理解为***不处于关闭状态，并且在整个的内存条热插拔过程中，无需关闭***。
在实际应用中，异常内存条可以是发生数据读取错误的内存条，即在异常内存条中发现异常数据。在发现异常数据后，可以根据异常数据的逻辑地址，确定出异常内存条的物理地址。
参照图2，示出了由异常数据确定异常内存条的流程图。如图2所示，当内存控制器发现内存数据中有异常数据时，内存控制器可以从逻辑地址映射区获取到异常数据的逻辑地址，内存控制器再根据逻辑地址和物理地址的转换关系，将异常数据的逻辑地址转换为异常内存条的物理地址，从而可以根据物理地址找到对应的内存条DIMM。图2中，内存控制器中物理地址映射区与内存映射表中的内存条物理地址相对应。可以从物理地址映射区中的物理地址确定出具体的异常内存条。
本公开示例性实施方式中，更换按键可以是设置在异常内存条上的一个实体按键，也可以是增加在BMC(Baseboard Management Controller)界面上的一个虚拟按键。该更换按键通过中转器与***的CPU(Central Processing Unit，中央处理器)相连，并通过Smbus (System management bus，***管理总线)或者I3C(Improved Inter Integrated Circuit)信号通知CPU或者MC(Memeory Controller，内存控制器)需要对相应的内存条进行下电更换。
在用户想要换下异常内存条，并在按下更换按键后，本公开实施例提供的内存条热插拔方法可以响应于更换按键的触发操作，先将异常内存条中的数据复制到空闲内存条中，以对异常内存条中的数据进行保存。其中，对更换按键的触发操作可以是单击操作、双击操作、长按操作或者其他的触发操作，本公开示例性实施方式对于触发操作的具体形式不作特殊限定。
在本公开的示例性实施方式中，参照图3，示出了一种异常内存条上的数据复制流程图，在异常内存条上的数据复制过程中，首先，需要停止对异常内存条的写入操作，不再将新的数据写入到异常内存条中，以防止数据丢失；其次，通过读操作(read)可以将异常内存条中的数据读取出来，并将读取出来的数据存入到可以对数据进行暂时性存储的缓存中；最后，可以将缓存中的数据通过写操作(write)写入到异常内存条之外的空闲内存条中。其中，此处的空闲内存条可以是存储有部分数据的正常内存条，也可以是没有存储数据的正常内存条。
需要说明的是，上述异常内存条的数据复制过程可以由内存控制器来执行。
在步骤S120中，在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条。
本公开示例性实施方式中，在将异常内存条中的数据复制到空闲内存条中后，就可以对异常内存条进行下电操作。具体的下电操作可以是在CPU或者MC接收到Smbus或者I3C信号后，可以通过拉低异常内存条对应的电源管理芯片使能信号，来使异常内存条下电。其中，电源管理芯片使能信号是电源管理芯片(Power Management IC，PMIC)进行工作时的使能Enable信号。
在实际应用中，还可以通过指示灯指示异常内存条是否已经下电。例如，将更换按键设置为具有双色指示灯的按键。在更换按键按下后，指示灯变颜色，则说明异常内存条已经下电。
在异常内存条下电后，就可以对异常内存条进行更换，换上新内存条，此过程可以人为手动操作。
本公开示例性实施方式中，在异常内存条下电后，还需要将异常内存条从***的内存映射表Memory Mapping中移除，使***中不再记录有该异常内存条。其中，内存映射表是存储有内存条物理地址的记录表，异常内存条通常需要从内存映射表中移除，以便于***可以从内存映射表中获取正常内存条的物理地址。
在步骤S130中，响应于所述新内存条的上电按键的触发操作，对所述新内存条上电。
本公开示例性实施方式中，在将异常内存条更换为新内存条之后，需要对新插上的新内存条有一个触发操作，该触发操作可以是单击操作、双击操作、长按操作或者其他的触发操作，本公开示例性实施方式对于触发操作的具体形式不作特殊限定。
响应于对新内存条上电按键的触发操作，该上电按键可以通知CPU或者内存控制器对新内存条进行上电初始化。
本公开示例性实施方式中，上电按键可以是设置在新内存条上的一个实体按键，也可以是增加在BMC界面上的一个虚拟按键。该上电按键通过中转器与***的CPU或者内存控制器相连，并通过Smbus或者I3C信号通知CPU或者内存控制器需要对相应的内存条进行上电操作。
具体的上电操作可以是在CPU或者内存控制器接收到Smbus或者I3C信号后，可以通过拉高新内存条对应的电源管理芯片使能信号，来使新内存条上电。其中，电源管理芯片使能信号是电源管理芯片(Power Management IC，PMIC)进行工作时的使能Enable信 号。
在实际应用中，还可以通过指示灯指示心内存条是否已经上电。例如，将上电按键设置为具有双色指示灯的按键。在上电按键按下后，指示灯变颜色，则说明新内存条已经上电。
在实际应用中，在新内存条上电之后，***还需要对新内存条进行初始化和调整，以使新内存条处于最佳工作状态，之后，***可以将新内存条添加到***的内存映射表中以供***正常使用。其中，对新内存条进行初始化和调整属于常规技术手段，此处不再赘述。
本公开示例性实施方式提供的内存条热插拔方法，可以在***处于上电状态下，响应于异常内存条更换按键的触发操作，在将异常内存条的数据复制到空闲内存条后，可以对异常内存条进行下电，并更换为新内存条，相当于对异常内存条的更换过程无需关闭***，也就不存在更换过程中关闭***所耗费的时间，从而可以减少异常内存条更换的耗时，在***处于上电或工作状态时，实现一种异常内存条热插拔方式，为用户提供了便利。
参照图4，示出了本公开示例性实施方式提供的内存条热插拔方法的步骤流程图。如图4所示，首先，进入步骤S401，在***处于上电状态下，触发异常内存条的更换按键；步骤S402，响应于异常内存条的更换按键的触发操作，将异常内存条上的数据复制到空闲内存条中，简称为复制数据；步骤S403，在数据复制完后，拉低电源管理芯片使能信号使异常内存条下电；步骤S404，在异常内存条下电后，更换异常内存条为新内存条；步骤S405，触发新内存条的上电按键；步骤S406，响应于新内存条的上电按键的触发操作，对新内存条进行上电和初始化；步骤S407，初始化后，将新内存条添加到***的内存映射表中，以使新内存条可以正常工作。
另外，本公开示例性实施方式还提供了一种内存条热插拔装置。参照图5，该内存条热插拔装置500包括：数据复制模块510、下电模块520、上电模块530、移除模块540、添加模块550和地址确定模块560；其中，
数据复制模块510，可以用于在***处于上电状态下，响应于异常内存条上的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；
下电模块520，可以用于在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；
上电模块530，可以用于响应于所述新内存条上的上电按键的触发操作，对所述新内存条上电。
在本公开的一种示例性实施方式中，下电模块520可以用于拉低所述异常内存条对应的电源管理芯片使能信号，以使所述异常内存条下电。
在本公开的一种示例性实施方式中，移除模块540可以用于将所述异常内存条从***的内存映射表中移除。
在本公开的一种示例性实施方式中，添加模块550可以用于将所述新内存条添加到***的内存映射表中。
在本公开的一种示例性实施方式中，地址确定模块560可以用于根据异常数据的逻辑地址，确定所述异常内存条的物理地址。
在本公开的一种示例性实施方式中，数据复制模块510，可以用于停止对所述异常内存条的写入操作，通过读操作将所述异常内存条中的数据存入缓存中；将所述缓存中的数据写入所述空闲内存条中。
在本公开的一种示例性实施方式中，上电模块530，可以用于拉高所述新内存条对应的电源管理芯片使能信号，以使所述新内存条上电。
上述内存条热插拔装置中各个模块的具体细节已经在对应的内存条热插拔方法中进行了详细的描述，因此此处不再赘述。
进一步，为了实现上述的内存条热插拔方法，本公开示例性实施方式还提供了一种能 够应用该内存条热插拔方法的内存条，参照图6，该内存条包括：内存条本体610和设置在内存条本体610上的更换按键620和上电按键630；其中，
更换按键620和上电按键630分别通过输入输出接口IO与中转器HUB640相连，中转器640可以用于在输入输出接口IO发生电平转换时，将***管理总线信号发送给CPU，也就是说，该中转器640需要与CPU相连，而CPU可以为***中独立于内存条存在的元件。
该内存条需要通过中转器640与CPU连接，以通过CPU对内存条进行上电或下电。也就是说，CPU在接收到***管理总线信号后，就可以对内存条进行上电或下电操作。
在实际应用中，与更换按键620和上电按键630连接的输入输出接口IO可以是同一个IO芯片的不同PIN脚，其中一个PIN脚与更换按键620相连，另一个PIN脚与上电按键630相连。
在本公开示例性实施方式中，上述***管理总线信号可以包括前述实施例所述的Smbus或I3C信号。
在本公开示例性实施方式中，输入输出接口IO发生电平转换可以是在触发更换按键620时，输入输出接口IO处的电平由高电平转换为低电平；或者是在触发更换按键620时，输入输出接口IO处的电平由低电平转换为高电平。
另外，输入输出接口IO发生电平转换还可以是在触发上电按键630时，输入输出接口IO处的电平由高电平转换为低电平；或者是在触发上电按键630时，输入输出接口IO处的电平由低电平转换为高电平。
为了实现输入输出接口IO处的电平转换，参照图7，内存条还可以包括第一电源710和第一电阻720，其中，输入输出接口IO通过更换按键620接地，第一电源710设置在输入输出接口IO和更换按键620的连线上，以为输入输出接口IO提供高电平。在第一电源710的连接线上还设置有第一电阻720，第一电阻710可以起到稳压作用。其中，第一电阻720的阻值大小可以根据实际情况设置，本公开示例性实施方式对此不作特殊限定。
本公开示例性实施方式中，在按下更换按键620后，输入输出接口IO会与接地端连通，使得输入输出接口IO处的电平由高电平转换为低电平。如图7所示，此处的输入输出接口IO可以为一个IO芯片的第一PIN脚1。
在实际应用中，更换按键620可以是一个开关，按下更换按键620时可以导通输入输出接口IO和接地端。
本公开示例性实施方式中，继续如图7所示，内存条还可以包括第二电源730和第二电阻740，其中，输入输出接口IO通过上电按键630接地，第二电源730设置在输入输出接口IO和上电按键630的连线上，以为输入输出接口IO提供高电平。在第二电源730的连接线上还设置有第二电阻740，第二电阻740可以起到稳压作用。其中，第二电阻740的阻值大小可以根据实际情况设置，本公开示例性实施方式对此不作特殊限定。
本公开示例性实施方式中，在按下上电按键630后，输入输出接口IO会与接地端连通，使得输入输出接口IO处的电平由高电平转换为低电平。如图7所示，此处的输入输出接口IO可以为一个IO芯片的第二PIN脚2。
在实际应用中，上电按键630可以是一个开关，按下上电按键630时可以导通输入输出接口IO和接地端。
本公开示例性实施方式还提供了另一种实现输入输出接口IO处的电平转换的方法，参照图8，该内存条还可以包括第三电源810，在该内存条中，输入输出接口IO直接接地，可以为输入输出接口IO提供低电平。另外，更换按键620设置在第三电源810和输入输出接口IO之间，当按下或者触发更换按键620时，第三电源810会与输入输出接口IO导通，从而使得输入输出接口IO处的电平由低电平转换为高电平。如图8所示，此处的输入输出接口IO可以为一个IO芯片的第一PIN脚1。
在实际应用中，第三电源810旁边可以设置电阻，也可以不设置电阻，本公开示例性实施方式对此不作特殊限定。其中，电阻的阻值大小也可以根据实际情况设置，此处不作限定。
本公开示例性实施方式中，更换按键620可以为一个开关，在按下更换按键620后，可以导通第三电源810和输入输出接口IO。
本公开示例性实施方式中，继续如图8所示，内存条还可以包括第四电源820，在此内存条中，由于输入输出接口IO直接接地，输入输出接口IO处的电平起初为低电平。另外，通过将上电按键630设置在第四电源820和输入输出接口IO之间，在按下或者触发上电按键630时，第四电源820会与输入输出接口IO导通，从而使得输入输出接口IO处的电平由低电平转换为高电平。如图8所示，此处的输入输出接口IO可以为一个IO芯片的第二PIN脚2。
本公开示例性实施方式中，上述的上电按键630也可以是一个开关，在按下上电按键630后，可以导通第四电源820和输入输出接口IO。
本公开示例性实施方式中，为了通过CPU对内存条进行上电或下电，如图6所示，CPU还需要与内存条的电源管理芯片PMIC650相连，CPU通过将电源管理芯片使能信号拉低，就可以控制内存条下电；CPU通过将电源管理芯片使能信号拉高，就可以控制内存条上电。
本公开示例性实施方式中，如图7和图8所示，输入输出接口IO通过中转器HUB连接在内存条的金手指上。金手指通过主板上的走线，从而使得中转器HUB与CPU连接，进而实现信号的传输。
本公开实施例提供的内存条，通过将输入输出接口与电源或接地端连接，可以在电源和接地端切换，从而实现了输入输出接口处的电平转换；在输入输出接口处发生电平转换时，中转器可以将***管理总线信号发送给CPU，通过CPU就可以对内存条进行上电或下电，从而可以实现异常内存条的下电更换以及新换上的内存条的上电，即可以用于上述实施例所述的内存条热插拔过程中。
参照图9，提供了一种插设上述内存条的主板。在图9所示的主板上，每个内存条的供电电源PMIC已经由主板移到内存条上，如DDR5DIMM条所示，每个DIMM上都有独立的PMIC，从而可以对每个DIMM独立进行上下电。
另外，CPU的每个通道(channel)的子内存控制器(Sub Memory Controller，SMC)也是独立的，一个SMC控制一个DIMM。例如，如图9所示，CPU上的SMC0控制DIMM0，SMC1控制DIMM1。更换DIMM0时，只要SMC0来控制即可，更换DIMM1时，只要SMC1来控制即可。
因此，在其中一个内存条发生异常需要更换时，只要对该内存条进行下电操作即可，不会影响到其他内存条的正常使用，并且CPU也能正常工作；同样的，对于新换上的内存条也可以直接进行上电，而不会对其他内存条及CPU带来影响，进而为内存条的热插拔提供了基础。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机命令。在计算机上加载和执行计算机程序命令时，全部或部分地产生按照本公开实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机命令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。本 公开实施例中，计算机可以包括前面所述的装置。
尽管在此结合各实施例对本公开进行了描述，然而，在实施所要求保护的本公开过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其他单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本公开进行了描述，显而易见的，在不脱离本公开的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本公开的示例性说明，且视为已覆盖本公开范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种内存条热插拔方法，包括：
    在***处于上电状态下，响应于异常内存条的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；
    在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；
    响应于所述新内存条的上电按键的触发操作，对所述新内存条上电。
  2. 根据权利要求1所述的方法，其中，所述对所述异常内存条下电，包括：
    拉低所述异常内存条对应的电源管理芯片使能信号，以使所述异常内存条下电。
  3. 根据权利要求1或2所述的方法，其中，在所述异常内存条下电后，所述方法还包括：
    将所述异常内存条从***的内存映射表中移除。
  4. 根据权利要求1所述的方法，其中，在所述新内存条上电后，所述方法还包括：
    将所述新内存条添加到***的内存映射表中。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    根据异常数据的逻辑地址，确定所述异常内存条的物理地址。
  6. 根据权利要求1所述的方法，其中，所述将所述异常内存条上的数据复制到空闲内存条中，包括：
    停止对所述异常内存条的写入操作，通过读操作将所述异常内存条中的数据存入缓存中；
    将所述缓存中的数据写入所述空闲内存条中。
  7. 根据权利要求1所述的方法，其中，对所述新内存条上电，包括：
    拉高所述新内存条对应的电源管理芯片使能信号，以使所述新内存条上电。
  8. 一种内存条热插拔装置，包括：
    数据复制模块，用于在***处于上电状态下，响应于异常内存条上的更换按键的触发操作，将所述异常内存条上的数据复制到空闲内存条中；
    下电模块，用于在所述数据复制完后，对所述异常内存条下电，更换所述异常内存条为新内存条；
    上电模块，用于响应于所述新内存条上的上电按键的触发操作，对所述新内存条上电。
  9. 一种内存条，包括：内存条本体和设置在所述内存条本体上的更换按键和上电按键；其中，
    所述更换按键和所述上电按键分别通过输入输出接口与中转器连接，所述中转器用于在所述输入输出接口发生电平转换时，将***管理总线信号发送给CPU；
    所述CPU用于在接收到所述***管理总线信号后，对所述内存条上电或下电。
  10. 根据权利要求9所述的内存条，其中，还包括第一电源和第一电阻；其中，
    所述输入输出接口通过所述更换按键接地，所述第一电源设置在所述输入输出接口和所述更换按键的连线上，所述第一电阻设置在所述第一电源的连接线上。
  11. 根据权利要求9所述的内存条，其中，还包括第二电源和第二电阻；其中，
    所述输入输出接口通过所述上电按键接地，所述第二电源设置在所述输入输出接口和所述上电按键的连线上，所述第二电阻设置在所述第二电源的连接线上。
  12. 根据权利要求9所述的内存条，其中，还包括第三电源；其中，
    所述输入输出接口接地，所述更换按键设置在所述第三电源和所述输入输出接口之间。
  13. 根据权利要求9所述的内存条，其中，还包括第四电源；其中，
    所述输入输出接口接地，所述上电按键设置在所述第四电源和所述输入输出接口之间。
  14. 根据权利要求9-13中任一项所述的内存条，其中，所述上电按键和所述更换按 键均为开关。
  15. 根据权利要求9所述的内存条，其中，所述CPU与所述内存条的电源管理芯片相连，所述CPU通过将电源管理芯片使能信号拉低，以控制所述内存条下电；
    所述CPU通过将所述电源管理芯片使能信号拉高，以控制所述内存条上电。
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CN109302188A (zh) * 2017-07-25 2019-02-01 厦门雅迅网络股份有限公司 一种电阻分压式的线控按键的检测方法和电路

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CN118035140B (zh) * 2024-04-11 2024-06-11 中诚华隆计算机技术有限公司 一种服务器内存通道的切换***

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