WO2023207399A1 - Dielectric layer filling method for straight-hole through silicon via - Google Patents
Dielectric layer filling method for straight-hole through silicon via Download PDFInfo
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- WO2023207399A1 WO2023207399A1 PCT/CN2023/081818 CN2023081818W WO2023207399A1 WO 2023207399 A1 WO2023207399 A1 WO 2023207399A1 CN 2023081818 W CN2023081818 W CN 2023081818W WO 2023207399 A1 WO2023207399 A1 WO 2023207399A1
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- silicon
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 107
- 239000010703 silicon Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000003475 lamination Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 73
- 239000000463 material Substances 0.000 claims description 20
- 238000001465 metallisation Methods 0.000 claims description 10
- 238000001771 vacuum deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 229910010272 inorganic material Inorganic materials 0.000 claims description 4
- 239000011147 inorganic material Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 238000004026 adhesive bonding Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Definitions
- the present invention relates to the technical field of semiconductor packaging, and in particular to a dielectric layer filling method for straight through silicon holes.
- Image sensors, MEMS, fingerprint chips and other related products are widely used in consumer electronics products. As the performance of consumer electronic products improves, such electronic products are required to become smaller and thinner, which drives the chip packaging size to become smaller and thinner, making traditional single-chip wiring The form of packaging is largely restricted. Packaging based on wafer-level silicon via technology has the advantages of low cost, small packaging size, low packaging height, and high reliability.
- TSV Thine-Silicon-Via
- Via-last TSV technology Making TSV (Through-Silicon-Via) on the back side of the active wafer and leading out the circuit.
- the obvious advantage of this solution is that it does not change the existing integrated circuit design. Compared with the Via-middle TSV process in the wafer factory, its cost can be reduced by about 10%.
- FIG. 3 shows a cross-sectional view of a straight hole through silicon via according to the prior art.
- the dielectric layer is made using conventional spin coating methods. Due to the presence of air in the through silicon via hole, the dielectric layer cannot completely enter the through silicon via hole. After baking, the air in the through silicon via will break through the surface dielectric layer, causing direct contact between the metal in the through silicon via and the external air, which may cause corrosion and other problems.
- the task of the present invention is to provide a method for filling the dielectric layer of a straight hole through silicon hole.
- the metal layer on the inner wall of the straight hole through silicon hole can be effectively protected and the reliability of the chip is enhanced.
- the wafer surface is relatively flat, making it easy to implement a multi-layer rewiring structure without the problem of line discontinuity.
- the present invention provides a dielectric layer filling method for straight through silicon holes, including:
- the dielectric layer is formed in the through silicon hole and on the wafer through a vacuum lamination or vacuum coating process.
- the method also includes: photolithography dielectric layer to form circuit pattern; and
- Metal is electroplated on the circuit pattern to form an under-bump metallization layer, and solder balls are arranged on the under-bump metallization layer.
- a vacuum lamination machine is used to fix the wafer on the machine table of the vacuum lamination machine, and then the vacuum is evacuated to heat the dielectric layer material on the surface of the wafer to make the dielectric layer
- the fluidity of the layer material increases and pressure is applied to the air bag.
- the dielectric layer material remains on the surface of the wafer while the dielectric layer material is filled into the through silicon via.
- the wafer is fixed on the machine table, vacuumed, and then the dielectric layer material is spin-coated.
- the dielectric layer material remains on the surface of the wafer, and at the same time, the dielectric layer material is filled into within through silicon vias.
- an inorganic material is deposited on the back side of the wafer and in the through silicon hole by plasma enhanced chemical vapor deposition to form an insulating layer, and then the insulating layer at the bottom of the through silicon hole is removed by etching to expose the pins. .
- a metal layer is first electroplated on the inner wall and bottom of the through silicon hole and the insulating layer located on the back of the wafer, and then the metal layer is etched to form the metal wiring.
- the metal wiring is electrically connected to the pin.
- the through silicon hole is a straight hole.
- the present invention has at least the following beneficial effects: a straight-hole through-silicon via media disclosed in the present invention
- the material layer filling method uses a vacuum lamination process or a vacuum coating process to fill the dielectric layer in the straight-hole through-silicon hole, which can effectively solve the protection problem of the metal layer on the inner wall of the straight-hole through-silicon hole and enhance the reliability of the chip.
- due to The through silicon holes are filled with dielectric layers, and the wafer surface is relatively flat without huge holes. It is easy to realize a multi-layer rewiring structure without the problem of line discontinuity.
- Figure 1 shows a cross-sectional view of a tilted through silicon via in a filter according to the prior art
- FIG. 2 shows a cross-sectional view of a tilted through silicon via in a fingerprint recognition chip according to the prior art
- FIG. 3 shows a cross-sectional view of a straight hole through silicon via according to the prior art
- Figure 4 shows a flow chart of a dielectric layer filling method for a straight hole through silicon hole according to an embodiment of the present invention
- 5A to 5F show a schematic diagram of the formation process of a straight hole through silicon hole filled with a dielectric layer according to an embodiment of the present invention
- Figure 6 shows a cross-sectional view of the through silicon hole after filling using the dielectric layer filling method of the straight hole through silicon hole according to one embodiment of the present invention.
- FIG. 7 shows a top view of a wafer with through-silicon vias filled by a dielectric layer filling method of straight-hole through-silicon vias according to one embodiment of the present invention.
- the quantifiers "a” and “ ⁇ " do not exclude the scenario of multiple elements.
- the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and does not limit the order of each step. In different embodiments of the present invention, it can be determined according to the adjustment of the process. Adjust the order of steps.
- FIG. 4 shows a flow chart of a dielectric layer filling method for straight-hole through silicon holes according to an embodiment of the present invention
- FIGS. 5A to 5F show a dielectric layer filling method according to an embodiment of the present invention. Schematic diagram of the formation process of straight hole through silicon vias.
- a dielectric layer filling method for straight through silicon holes includes:
- the carrier 102 is bonded to the front surface of the wafer 101.
- the carrier is generally a single crystal silicon wafer, and other materials can be selected for the carrier, such as glass slides, organic substrates, metal substrates, ceramic substrates, substrates composed of organic substrates and metal substrates, or other similar materials. Those skilled in the art will understand that any flat surface with specific strength can be used as a slide of the present invention.
- step S2 the backside of the wafer 101 is thinned and the through silicon via 103 is formed.
- through-silicon vias 103 are formed on the backside of the wafer 101 by etching to expose the pins 104 .
- the through silicon via 103 is a straight hole.
- the diameter of the through silicon via 103 ranges from 5 microns to 1 millimeter.
- an insulating layer 105 is formed on the back side of the wafer 101 and in the through silicon hole 103, and the insulating layer at the bottom of the through silicon hole 103 is removed.
- an inorganic material is deposited on the back side of the wafer 101 and in the through silicon hole 103 by a plasma enhanced chemical vapor deposition method to form an insulating layer 105, and then the insulating layer at the bottom of the through silicon hole 103 is removed by etching to expose Pin 104.
- the insulating layer 105 may be an inorganic material such as silicon dioxide, or an organic material.
- metal wiring 106 is formed within the through silicon via 103 and on the insulating layer 105.
- the metal wiring layer 106 is electrically connected to the pins 104 .
- a metal layer of a certain thickness is first electroplated on the inner wall and bottom of the through silicon hole 103 and the insulating layer 105 on the back side of the wafer 101, and then the metal layer is etched to form the metal wiring 106.
- a dielectric layer 107 is formed in the through silicon via 103 and on the wafer 101, and the dielectric layer 107 is photolithographed to form a circuit pattern 108.
- the dielectric layer 107 fills the through silicon hole 103 .
- the dielectric layer 107 is formed in the through silicon hole 103 and on the wafer 101 through a vacuum lamination or vacuum coating process, and the dielectric layer located on part of the metal wiring 106 is removed through photolithography to expose part of the metal wiring 106 to form Line graphics108.
- a vacuum lamination machine is used to fix the wafer 101 on the table of the vacuum lamination machine, and then vacuum is applied to heat the dielectric material on the surface of the wafer 101 to improve the fluidity of the dielectric material. Increase. Pressure is applied to the air bag, and the dielectric material remains on the surface of the wafer 101 while the dielectric material is filled into the through silicon via 103 .
- the wafer 101 When forming the dielectric layer 107 using a vacuum coating process, the wafer 101 is fixed on the machine table, vacuumed, and then the dielectric layer material is spin-coated. The dielectric layer material remains on the surface of the wafer 101, and at the same time, the dielectric layer material is filled into the through silicon hole. Within 103.
- step S6 metal is electroplated on the circuit pattern 108 to form an under-bump metallization layer 109, and solder balls 110 are arranged on the under-bump metallization layer 109.
- BGA balls 110 are arranged on the under-bump metallization layer 109 through a ball placement process.
- Under-bump metallization layer 109 is electrically connected to metal wiring 106 .
- Figure 6 shows a cross-sectional view of the through silicon hole filled with a dielectric layer filling method using a straight hole through silicon hole according to an embodiment of the present invention
- Figure 7 shows a through silicon hole with a straight hole hole according to an embodiment of the present invention.
- the present invention has at least the following beneficial effects:
- the present invention discloses a dielectric layer filling method for straight-hole through-silicon holes.
- the dielectric layer is filled in the straight-hole through-silicon holes through a vacuum lamination process or a vacuum gluing process, which can effectively solve the problem of direct hole through-silicon holes.
- the protection of the metal layer on the inner wall of the through-silicon via enhances the reliability of the chip.
- the through-silicon via is filled with a dielectric layer, the wafer surface is relatively flat and there are no huge holes, making it easy to realize a multi-layer rewiring structure. There will be no problem of line discontinuity.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a dielectric layer filling method for a straight-hole through silicon via, comprising: thinning the back surface of a wafer, and manufacturing a through silicon via; forming an insulating layer on the back surface of the wafer and in the through silicon via, and removing the insulating layer at the bottom of the through silicon via; forming metal wires in the through silicon via and on the insulating layer; and forming a dielectric layer in the through silicon via and on the wafer by means of a vacuum lamination or vacuum gluing process. By means the method, a metal layer on the inner wall of a straight-hole through silicon via can be effectively protected, and the reliability of a chip is enhanced; moreover, because the through silicon via is filled with a dielectric layer, the surface of a wafer is relatively flat, and a multi-layer re-wiring structure can be easily achieved without the problem of line discontinuity.
Description
本发明涉及半导体封装技术领域，尤其涉及一种直孔硅通孔的介质层填充方法。The present invention relates to the technical field of semiconductor packaging, and in particular to a dielectric layer filling method for straight through silicon holes.
图像传感器、MEMS和指纹类芯片等多类相关产品广泛应用于消费类电子产品上。随着消费类电子产品性能的提升，要求这类电子产品越来越小，厚度越来越薄，这就驱动芯片封装尺寸越来越小，厚度越来越薄，使传统的单芯片打线封装形式在很大程度上受到了制约。基于晶圆级硅通孔技术的封装，具有成本低、封装尺寸小、封装高度低、可靠性高等优势。Image sensors, MEMS, fingerprint chips and other related products are widely used in consumer electronics products. As the performance of consumer electronic products improves, such electronic products are required to become smaller and thinner, which drives the chip packaging size to become smaller and thinner, making traditional single-chip wiring The form of packaging is largely restricted. Packaging based on wafer-level silicon via technology has the advantages of low cost, small packaging size, low packaging height, and high reliability.
在有源晶圆的背面制作TSV(Through-Silicon-Via，硅通孔)，并引出线路，被称为后通孔(Via-last TSV)技术。该方案的明显优势是可以不改变现有的集成电路设计，相比晶圆厂的中通孔(Via-middle TSV)工艺，其成本可以下降约10％。Making TSV (Through-Silicon-Via) on the back side of the active wafer and leading out the circuit is called Via-last TSV technology. The obvious advantage of this solution is that it does not change the existing integrated circuit design. Compared with the Via-middle TSV process in the wafer factory, its cost can be reduced by about 10%.
目前常用的Via-last TSV技术，一般刻蚀倾斜的硅通孔，倾斜角度从60°到85°之间，然后通过TSV引出线路互连。图1示出了根据现有技术的滤波器中的倾斜硅通孔的截面图。图2示出了根据现有技术的指纹识别芯片中的倾斜硅通孔的截面图。The currently commonly used Via-last TSV technology generally etches inclined through silicon holes with an angle of between 60° and 85°, and then leads to line interconnections through TSV. Figure 1 shows a cross-sectional view of a tilted through silicon via in a filter according to the prior art. 2 shows a cross-sectional view of a tilted through silicon via in a fingerprint recognition chip according to the related art.
但是这种常用的Via-last TSV方案有一个显著的缺点，倾斜孔占用一定的空间，如果电极之间间距不足，无法实现线路引出。However, this commonly used Via-last TSV solution has a significant shortcoming. The inclined hole takes up a certain amount of space. If the spacing between electrodes is insufficient, line extraction cannot be achieved.
使用直孔硅通孔进行封装，可以提高封装密度，但是在硅通孔内部金属填充后，由于硅通孔角度过大，金属表面很难使用介质层进行保护。图3示出了根据现有技术的直孔硅通孔的截面图。介质层采用常规的旋涂方法制作，由于硅通孔孔内存在空气，介质层无法彻底进入硅通孔孔内。经过烘烤后，硅通孔孔内的空气会冲破表面的介质层，导致硅通孔内金属和外部空气直接接触，从而可能发生腐蚀等问题。
Using straight-hole through-silicon vias for packaging can increase the packaging density. However, after the metal is filled inside the through-silicon vias, it is difficult to protect the metal surface with a dielectric layer because the angle of the through-silicon vias is too large. 3 shows a cross-sectional view of a straight hole through silicon via according to the prior art. The dielectric layer is made using conventional spin coating methods. Due to the presence of air in the through silicon via hole, the dielectric layer cannot completely enter the through silicon via hole. After baking, the air in the through silicon via will break through the surface dielectric layer, causing direct contact between the metal in the through silicon via and the external air, which may cause corrosion and other problems.
发明内容Contents of the invention
本发明的任务是提供一种直孔硅通孔的介质层填充方法，通过该方法，可以有效保护直孔硅通孔内壁的金属层，增强芯片的可靠性，同时由于硅通孔内有介质层填充，晶圆表面相对平整，容易实现多层再布线结构，而不会出现线路不连续的问题。The task of the present invention is to provide a method for filling the dielectric layer of a straight hole through silicon hole. Through this method, the metal layer on the inner wall of the straight hole through silicon hole can be effectively protected and the reliability of the chip is enhanced. At the same time, because there is a dielectric in the through silicon hole, With layer filling, the wafer surface is relatively flat, making it easy to implement a multi-layer rewiring structure without the problem of line discontinuity.
针对现有技术中存在的问题，本发明提供一种直孔硅通孔的介质层填充方法来解决，包括：In order to solve the problems existing in the prior art, the present invention provides a dielectric layer filling method for straight through silicon holes, including:
将晶圆的背面减薄，并制作硅通孔；Thin the backside of the wafer and create through silicon vias;
在晶圆的背面以及硅通孔内形成绝缘层，并去除位于硅通孔的底部的绝缘层；Form an insulating layer on the back side of the wafer and in the through-silicon hole, and remove the insulating layer at the bottom of the through-silicon hole;
在硅通孔内和绝缘层上形成金属布线；以及Forming metal wiring within the through silicon via and on the insulating layer; and
通过真空压膜或真空涂胶工艺在硅通孔内和晶圆上形成介质层。The dielectric layer is formed in the through silicon hole and on the wafer through a vacuum lamination or vacuum coating process.
进一步地，还包括：光刻介质层形成线路图形；以及Further, the method also includes: photolithography dielectric layer to form circuit pattern; and
在线路图形电镀金属形成凸点下金属化层，并在凸点下金属化层上布置焊球。Metal is electroplated on the circuit pattern to form an under-bump metallization layer, and solder balls are arranged on the under-bump metallization layer.
进一步地，通过真空压膜工艺形成所述介质层时，使用真空压膜机，将晶圆固定在真空压膜机的机台上，然后抽真空，加热晶圆表面的介质层材料，使介质层材料的流动性增加，并对气囊施加压力，介质层材料保留在晶圆的表面，同时介质层材料填充入硅通孔内。Further, when forming the dielectric layer through a vacuum lamination process, a vacuum lamination machine is used to fix the wafer on the machine table of the vacuum lamination machine, and then the vacuum is evacuated to heat the dielectric layer material on the surface of the wafer to make the dielectric layer The fluidity of the layer material increases and pressure is applied to the air bag. The dielectric layer material remains on the surface of the wafer while the dielectric layer material is filled into the through silicon via.
进一步地，通过真空涂胶工艺形成所述介质层时，将晶圆固定在机台上，抽真空，然后旋涂介质层材料，介质层材料保留在晶圆的表面，同时介质层材料填充入硅通孔内。Further, when forming the dielectric layer through a vacuum coating process, the wafer is fixed on the machine table, vacuumed, and then the dielectric layer material is spin-coated. The dielectric layer material remains on the surface of the wafer, and at the same time, the dielectric layer material is filled into within through silicon vias.
进一步地，通过等离子体增强化学气相沉积在所述晶圆的背面以及所述硅通孔内沉积无机材料以形成绝缘层，然后通过刻蚀去除位于硅通孔的底部的绝缘层，露出管脚。Further, an inorganic material is deposited on the back side of the wafer and in the through silicon hole by plasma enhanced chemical vapor deposition to form an insulating layer, and then the insulating layer at the bottom of the through silicon hole is removed by etching to expose the pins. .
进一步地，形成所述金属布线时，先在所述硅通孔的内壁和底部以及位于所述晶圆的背面的绝缘层上电镀金属层，然后刻蚀金属层形成所述金属布线。Further, when forming the metal wiring, a metal layer is first electroplated on the inner wall and bottom of the through silicon hole and the insulating layer located on the back of the wafer, and then the metal layer is etched to form the metal wiring.
进一步地，所述金属布线与所述管脚电连接。Further, the metal wiring is electrically connected to the pin.
进一步地，所述凸点下金属化层与所述金属布线电连接。Further, the under-bump metallization layer is electrically connected to the metal wiring.
进一步地，所述硅通孔为直孔。Further, the through silicon hole is a straight hole.
本发明至少具有下列有益效果：本发明公开的一种直孔硅通孔的介
质层填充方法，通过真空压膜工艺或真空涂胶工艺在直孔硅通孔内填充介质层，可以有效解决直孔硅通孔内壁的金属层的保护问题，增强芯片的可靠性，同时由于硅通孔内有介质层填充，晶圆表面相对平整，不存在巨大的孔洞，容易实现多层再布线结构，而不会出现线路不连续的问题。The present invention has at least the following beneficial effects: a straight-hole through-silicon via media disclosed in the present invention The material layer filling method uses a vacuum lamination process or a vacuum coating process to fill the dielectric layer in the straight-hole through-silicon hole, which can effectively solve the protection problem of the metal layer on the inner wall of the straight-hole through-silicon hole and enhance the reliability of the chip. At the same time, due to The through silicon holes are filled with dielectric layers, and the wafer surface is relatively flat without huge holes. It is easy to realize a multi-layer rewiring structure without the problem of line discontinuity.
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。In order to further elucidate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that the drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be labeled with the same or similar reference numerals, for purposes of clarity and clarity.
图1示出了根据现有技术的滤波器中的倾斜硅通孔的截面图；Figure 1 shows a cross-sectional view of a tilted through silicon via in a filter according to the prior art;
图2示出了根据现有技术的指纹识别芯片中的倾斜硅通孔的截面图；2 shows a cross-sectional view of a tilted through silicon via in a fingerprint recognition chip according to the prior art;
图3示出了根据现有技术的直孔硅通孔的截面图；3 shows a cross-sectional view of a straight hole through silicon via according to the prior art;
图4示出了根据本发明的一个实施例的一种直孔硅通孔的介质层填充方法的流程图；Figure 4 shows a flow chart of a dielectric layer filling method for a straight hole through silicon hole according to an embodiment of the present invention;
图5A至图5F示出了根据本发明一个实施例的一种介质层填充的直孔硅通孔的形成过程示意图；5A to 5F show a schematic diagram of the formation process of a straight hole through silicon hole filled with a dielectric layer according to an embodiment of the present invention;
图6示出了根据本发明一个实施例的采用直孔硅通孔的介质层填充方法填充后的硅通孔的截面图；以及Figure 6 shows a cross-sectional view of the through silicon hole after filling using the dielectric layer filling method of the straight hole through silicon hole according to one embodiment of the present invention; and
图7示出了根据本发明一个实施例的具有直孔硅通孔的介质层填充方法填充的硅通孔的晶圆的俯视图。FIG. 7 shows a top view of a wafer with through-silicon vias filled by a dielectric layer filling method of straight-hole through-silicon vias according to one embodiment of the present invention.
应当指出，各附图中的各组件可能为了图解说明而被夸大地示出，而不一定是比例正确的。It should be noted that components in the various figures may be exaggerated for illustration and are not necessarily proportionally correct.
在本发明中，各实施例仅仅旨在说明本发明的方案，而不应被理解为限制性的。In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be construed as limiting.
在本发明中，除非特别指出，量词“一个”、“一”并未排除多个元素的场景。In the present invention, unless otherwise specified, the quantifiers "a" and "一" do not exclude the scenario of multiple elements.
在此还应当指出，在本发明的实施例中，为清楚、简单起见，可能
示出了仅仅一部分部件或组件，但是本领域的普通技术人员能够理解，在本发明的教导下，可根据具体场景需要添加所需的部件或组件。It should also be noted here that in the embodiments of the present invention, for the sake of clarity and simplicity, it may be Only some parts or components are shown, but those of ordinary skill in the art can understand that, under the teachings of the present invention, required parts or components can be added according to specific scene requirements.
在此还应当指出，在本发明的范围内，“相同”、“相等”、“等于”等措辞并不意味着二者数值绝对相等，而是允许一定的合理误差，也就是说，所述措辞也涵盖了“基本上相同”、“基本上相等”、“基本上等于”。It should also be noted here that within the scope of the present invention, terms such as "the same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error. That is to say, the The wording also covers "substantially the same", "substantially equal", and "substantially equal to".
在此还应当指出，在本发明的描述中，术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是明示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为明示或暗示相对重要性。It should also be noted here that in the description of the present invention, the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", The orientations or positional relationships indicated by "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention. and simplified description, rather than expressly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention. Furthermore, the terms “first” and “second” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
另外，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。In addition, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and does not limit the order of each step. In different embodiments of the present invention, it can be determined according to the adjustment of the process. Adjust the order of steps.
图4示出了根据本发明的一个实施例的一种直孔硅通孔的介质层填充方法的流程图；图5A至图5F示出了根据本发明一个实施例的一种介质层填充的直孔硅通孔的形成过程示意图。FIG. 4 shows a flow chart of a dielectric layer filling method for straight-hole through silicon holes according to an embodiment of the present invention; FIGS. 5A to 5F show a dielectric layer filling method according to an embodiment of the present invention. Schematic diagram of the formation process of straight hole through silicon vias.
如图4所示，一种直孔硅通孔的介质层填充方法包括：As shown in Figure 4, a dielectric layer filling method for straight through silicon holes includes:
在步骤S1，如图5A所示，在晶圆101的正面键合载片102。载片一般为单晶硅片，载片还可选择其他材料，如玻璃载片、有机基板、金属基板、陶瓷基板、有机基板与金属基板复合的基板，或者其他类似材料也可以。本领域的技术人员应该理解，只要具有特定强度的平整表面，即可作为本发明的载片。In step S1, as shown in FIG. 5A, the carrier 102 is bonded to the front surface of the wafer 101. The carrier is generally a single crystal silicon wafer, and other materials can be selected for the carrier, such as glass slides, organic substrates, metal substrates, ceramic substrates, substrates composed of organic substrates and metal substrates, or other similar materials. Those skilled in the art will understand that any flat surface with specific strength can be used as a slide of the present invention.
在步骤S2，如图5B所示，将晶圆101的背面减薄，并制作硅通孔103。在本发明的一个实施例中，通过刻蚀在晶圆101的背面制作硅通孔103，露出管脚104。在此，硅通孔103为直孔。硅通孔103的直径在5微米到1毫米的范围内。In step S2, as shown in FIG. 5B, the backside of the wafer 101 is thinned and the through silicon via 103 is formed. In one embodiment of the present invention, through-silicon vias 103 are formed on the backside of the wafer 101 by etching to expose the pins 104 . Here, the through silicon via 103 is a straight hole. The diameter of the through silicon via 103 ranges from 5 microns to 1 millimeter.
在步骤S3，如图5C所示，在晶圆101的背面以及硅通孔103内形成绝缘层105，并去除位于硅通孔103的底部的绝缘层。在本发明的一
个实施例中，通过等离子体增强化学气相沉积方法在晶圆101的背面以及硅通孔103内沉积无机材料形成绝缘层105，然后通过刻蚀去除位于硅通孔103的底部的绝缘层，露出管脚104。绝缘层105可以是二氧化硅等无机材料，还可以是有机材料。In step S3, as shown in FIG. 5C, an insulating layer 105 is formed on the back side of the wafer 101 and in the through silicon hole 103, and the insulating layer at the bottom of the through silicon hole 103 is removed. In one of the present invention In this embodiment, an inorganic material is deposited on the back side of the wafer 101 and in the through silicon hole 103 by a plasma enhanced chemical vapor deposition method to form an insulating layer 105, and then the insulating layer at the bottom of the through silicon hole 103 is removed by etching to expose Pin 104. The insulating layer 105 may be an inorganic material such as silicon dioxide, or an organic material.
在步骤S4，如图5D所示，在硅通孔103内和绝缘层105上形成金属布线106。金属布线层106与管脚104电连接。形成金属布线106时，先在硅通孔103的内壁和底部以及位于晶圆101的背面的绝缘层105上电镀一定厚度的金属层，然后刻蚀金属层形成金属布线106。In step S4, as shown in FIG. 5D, metal wiring 106 is formed within the through silicon via 103 and on the insulating layer 105. The metal wiring layer 106 is electrically connected to the pins 104 . When forming the metal wiring 106, a metal layer of a certain thickness is first electroplated on the inner wall and bottom of the through silicon hole 103 and the insulating layer 105 on the back side of the wafer 101, and then the metal layer is etched to form the metal wiring 106.
在步骤S5，如图5E所示，在硅通孔103内和晶圆101上形成介质层107，并光刻介质层107形成线路图形108。介质层107将硅通孔103填满。具体的，通过真空压膜或真空涂胶工艺在硅通孔103内和晶圆101上形成介质层107，并通过光刻去除位于部分金属布线106上的介质层，露出部分金属布线106，形成线路图形108。In step S5, as shown in FIG. 5E, a dielectric layer 107 is formed in the through silicon via 103 and on the wafer 101, and the dielectric layer 107 is photolithographed to form a circuit pattern 108. The dielectric layer 107 fills the through silicon hole 103 . Specifically, the dielectric layer 107 is formed in the through silicon hole 103 and on the wafer 101 through a vacuum lamination or vacuum coating process, and the dielectric layer located on part of the metal wiring 106 is removed through photolithography to expose part of the metal wiring 106 to form Line graphics108.
采用真空压膜工艺形成介质层107时，使用真空压膜机，把晶圆101固定在真空压膜机的机台上，然后抽真空，加热晶圆101表面的介质材料，介质材料的流动性增加。对气囊施加压力，介质材料保留在晶圆101表面，同时介质材料填充入硅通孔103内。When using a vacuum lamination process to form the dielectric layer 107, a vacuum lamination machine is used to fix the wafer 101 on the table of the vacuum lamination machine, and then vacuum is applied to heat the dielectric material on the surface of the wafer 101 to improve the fluidity of the dielectric material. Increase. Pressure is applied to the air bag, and the dielectric material remains on the surface of the wafer 101 while the dielectric material is filled into the through silicon via 103 .
采用真空涂胶工艺形成介质层107时，把晶圆101固定在机台上，抽真空，然后旋涂介质层材料，介质层材料保留在晶圆101表面，同时介质层材料填充入硅通孔103内。When forming the dielectric layer 107 using a vacuum coating process, the wafer 101 is fixed on the machine table, vacuumed, and then the dielectric layer material is spin-coated. The dielectric layer material remains on the surface of the wafer 101, and at the same time, the dielectric layer material is filled into the through silicon hole. Within 103.
可选的，在步骤S6，如图5F所示，在线路图形108电镀金属形成凸点下金属化层109，并在凸点下金属化层109上布置焊球110。通过植球工艺在凸点下金属化层109上布置BGA球110。凸点下金属化层109与金属布线106电连接。Optionally, in step S6, as shown in FIG. 5F, metal is electroplated on the circuit pattern 108 to form an under-bump metallization layer 109, and solder balls 110 are arranged on the under-bump metallization layer 109. BGA balls 110 are arranged on the under-bump metallization layer 109 through a ball placement process. Under-bump metallization layer 109 is electrically connected to metal wiring 106 .
图6示出了根据本发明一个实施例的采用直孔硅通孔的介质层填充方法填充后的硅通孔的截面图；图7示出了根据本发明一个实施例的具有直孔硅通孔的介质层填充方法填充的硅通孔的晶圆的俯视图。Figure 6 shows a cross-sectional view of the through silicon hole filled with a dielectric layer filling method using a straight hole through silicon hole according to an embodiment of the present invention; Figure 7 shows a through silicon hole with a straight hole hole according to an embodiment of the present invention. Top view of a wafer filled with through-silicon vias using the hole dielectric layer filling method.
如图6所示，采用该直孔硅通孔的介质层填充方法填充硅通孔后，硅通孔内不存在空气，介质层能够充满硅通孔，保护了硅通孔内的金属，防止硅通孔内的金属与外界空气接触。As shown in Figure 6, after filling the through silicon hole using the dielectric layer filling method of the straight hole through silicon hole, there is no air in the through silicon hole, and the dielectric layer can fill the through silicon hole, protecting the metal in the through silicon hole and preventing The metal in the through silicon via is in contact with the outside air.
如图7所示，采用该直孔硅通孔的介质层填充方法填充硅通孔后，由于硅通孔内有介质层填充，晶圆200的表面相对平整，没有巨大的孔
洞，能够在晶圆表面布置多层金属再布线结构201，而且金属再布线结构201的线路连续，不会出现线路断裂的问题。As shown in Figure 7, after the through silicon hole is filled using the dielectric layer filling method of the straight hole through silicon hole, the surface of the wafer 200 is relatively smooth without huge holes due to the dielectric layer filling in the through silicon hole. Holes enable the multi-layer metal rewiring structure 201 to be arranged on the wafer surface, and the circuits of the metal rewiring structure 201 are continuous, and there will be no problem of circuit breakage.
本发明至少具有下列有益效果：本发明公开的一种直孔硅通孔的介质层填充方法，通过真空压膜工艺或真空涂胶工艺在直孔硅通孔内填充介质层，可以有效解决直孔硅通孔内壁的金属层的保护问题，增强芯片的可靠性，同时由于硅通孔孔内有介质层填充，晶圆表面相对平整，不存在巨大的孔洞，容易实现多层再布线结构，而不会出现线路不连续的问题。The present invention has at least the following beneficial effects: The present invention discloses a dielectric layer filling method for straight-hole through-silicon holes. The dielectric layer is filled in the straight-hole through-silicon holes through a vacuum lamination process or a vacuum gluing process, which can effectively solve the problem of direct hole through-silicon holes. The protection of the metal layer on the inner wall of the through-silicon via enhances the reliability of the chip. At the same time, because the through-silicon via is filled with a dielectric layer, the wafer surface is relatively flat and there are no huge holes, making it easy to realize a multi-layer rewiring structure. There will be no problem of line discontinuity.
虽然本发明的一些实施方式已经在本申请文件中予以了描述，但是本领域技术人员能够理解，这些实施方式仅仅是作为示例示出的。本领域技术人员在本发明的教导下可以想到众多的变型方案、替代方案和改进方案而不超出本发明的范围。所附权利要求书旨在限定本发明的范围，并藉此涵盖这些权利要求本身及其等同变换的范围内的方法和结构。
Although some embodiments of the present invention have been described in this application document, those skilled in the art will understand that these embodiments are shown as examples only. Those skilled in the art can think of numerous variations, substitutions and improvements based on the teachings of the present invention without departing from the scope of the present invention. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims themselves and their equivalents be covered thereby.
Claims (9)
- 一种直孔硅通孔的介质层填充方法，包括：A dielectric layer filling method for straight silicon through silicon holes, including:将晶圆的背面减薄，并制作硅通孔；Thin the backside of the wafer and create through silicon vias;在晶圆的背面以及硅通孔内形成绝缘层，并去除位于硅通孔的底部的绝缘层；Form an insulating layer on the back side of the wafer and in the through-silicon hole, and remove the insulating layer at the bottom of the through-silicon hole;在硅通孔内和绝缘层上形成金属布线；以及Forming metal wiring within the through silicon via and on the insulating layer; and通过真空压膜或真空涂胶工艺在硅通孔内和晶圆上形成介质层。The dielectric layer is formed in the through silicon hole and on the wafer through a vacuum lamination or vacuum coating process.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，还包括：光刻介质层形成线路图形；以及The dielectric layer filling method for straight through silicon holes according to claim 1, further comprising: photolithography of the dielectric layer to form a circuit pattern; and在线路图形电镀金属形成凸点下金属化层，并在凸点下金属化层上布置焊球。Metal is electroplated on the circuit pattern to form an under-bump metallization layer, and solder balls are arranged on the under-bump metallization layer.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，通过真空压膜工艺形成所述介质层时，使用真空压膜机，将晶圆固定在真空压膜机的机台上，然后抽真空，加热晶圆表面的介质层材料，使介质层材料的流动性增加，并对气囊施加压力，使得介质层材料保留在晶圆的表面，同时介质层材料填充入硅通孔内。The dielectric layer filling method of straight-hole through-silicon vias according to claim 1, characterized in that when forming the dielectric layer through a vacuum lamination process, a vacuum lamination machine is used to fix the wafer on the vacuum lamination machine. The machine is then evacuated, heating the dielectric layer material on the surface of the wafer to increase the fluidity of the dielectric layer material, and applying pressure to the air bag so that the dielectric layer material remains on the surface of the wafer, while the dielectric layer material is filled with silicon inside the through hole.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，通过真空涂胶工艺形成所述介质层时，将晶圆固定在机台上，抽真空，然后旋涂介质层材料，使得介质层材料保留在晶圆的表面，同时介质层材料填充入硅通孔内。The dielectric layer filling method of straight-hole through-silicon holes according to claim 1, characterized in that when forming the dielectric layer through a vacuum coating process, the wafer is fixed on the machine table, vacuumed, and then the dielectric is spin-coated layer material, so that the dielectric layer material remains on the surface of the wafer, and the dielectric layer material is filled into the through silicon hole.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，通过等离子体增强化学气相沉积在所述晶圆的背面以及所述硅通孔内沉积无机材料以形成绝缘层，然后通过刻蚀去除位于硅通孔的底部的绝缘层，露出管脚。The dielectric layer filling method of straight-hole through-silicon vias according to claim 1, characterized in that inorganic materials are deposited on the back side of the wafer and in the through-silicon vias through plasma-enhanced chemical vapor deposition to form an insulating layer. , and then remove the insulating layer at the bottom of the through silicon via by etching to expose the pins.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，形成所述金属布线时，先在所述硅通孔的内壁和底部以及位于所述晶圆的背面的绝缘层上电镀金属层，然后刻蚀金属层形成所述金属布线。The dielectric layer filling method of straight-hole through-silicon holes according to claim 1, characterized in that when forming the metal wiring, first insulating the inner wall and bottom of the through-silicon hole and the back surface of the wafer. A metal layer is electroplated on the layer, and then the metal layer is etched to form the metal wiring.
- 根据权利要求5所述的直孔硅通孔的介质层填充方法，其特征在于，所述金属布线与所述管脚电连接。The dielectric layer filling method for straight through silicon vias according to claim 5, wherein the metal wiring is electrically connected to the pins.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，所述凸点下金属化层与所述金属布线电连接。 The dielectric layer filling method for straight through silicon vias according to claim 1, wherein the under-bump metallization layer is electrically connected to the metal wiring.
- 根据权利要求1所述的直孔硅通孔的介质层填充方法，其特征在于，所述硅通孔为直孔。 The dielectric layer filling method of straight through silicon holes according to claim 1, wherein the through silicon holes are straight holes.
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| CN114883251A (en) * | 2022-04-29 | 2022-08-09 | 华进半导体封装先导技术研发中心有限公司 | Method for filling dielectric layer of straight-hole silicon through hole |
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