WO2023206148A1 - 阵列基板、显示面板 - Google Patents

阵列基板、显示面板 Download PDF

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Publication number
WO2023206148A1
WO2023206148A1 PCT/CN2022/089589 CN2022089589W WO2023206148A1 WO 2023206148 A1 WO2023206148 A1 WO 2023206148A1 CN 2022089589 W CN2022089589 W CN 2022089589W WO 2023206148 A1 WO2023206148 A1 WO 2023206148A1
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Prior art keywords
substrate
orthographic projection
sub
gate
line
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PCT/CN2022/089589
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English (en)
French (fr)
Inventor
肖锋
刘良军
朱伟
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京东方科技集团股份有限公司
成都京东方显示科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方显示科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000922.5A priority Critical patent/CN117546084A/zh
Priority to PCT/CN2022/089589 priority patent/WO2023206148A1/zh
Publication of WO2023206148A1 publication Critical patent/WO2023206148A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • an array substrate including:
  • the gate electrode of the thin film transistor extends along the first direction
  • the first electrode of the thin film transistor includes a connected first body and a first end;
  • the second electrode of the thin film transistor includes a connected second body and a second end;
  • the orthographic projections of the first body and the second body on the substrate of the array substrate are respectively located within the orthographic projection of the gate on the substrate, and at least part of the first end is The orthographic projection of at least part of the second end portion on the substrate does not overlap with the orthographic projection of the gate on the substrate, and the first end portion is on the substrate.
  • the orthographic projection on the substrate and the orthographic projection of the second end on the substrate are both located on the same side of the orthographic projection of the gate on the substrate;
  • the average distance between the first end and the second end is greater than the average distance between the first body and the second body.
  • the first pole further includes a third end, and the first body connects the first end and the third end;
  • the second pole further includes a fourth end. End portion, the second body connects the second end portion and the fourth end portion;
  • Orthographic projections of at least a partial region of the third end portion and at least a partial region of the fourth end portion on the substrate do not overlap with an orthographic projection of the gate electrode on the substrate;
  • the average distance between the third end and the fourth end is greater than the average distance between the first body and the second body.
  • the array substrate further includes gate lines, data lines, pixel electrodes, first wiring lines, and second wiring lines.
  • the data lines intersect and are insulated from the gate lines.
  • the pole is electrically connected to the gate line, the pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines, and the third end of the first pole passes through the
  • the first wiring is electrically connected to the data line, and the second end of the second pole is electrically connected to the pixel electrode through the second wiring;
  • the part along the third end connected to the first body points in the direction of the part connected to the third end and the first trace, and the third end to the data line The minimum distance between gradually decreases
  • the portion along the first end connected to the first body points in the direction of the portion of the first end away from the first body, and the first end The minimum distance to the second end gradually increases, and the minimum distance between the first end and the data line gradually decreases;
  • the part along the fourth end connected to the second body points in the direction of the part of the fourth end away from the second body, between the fourth end and the third end.
  • the minimum distance gradually increases, and the minimum distance between the fourth end and the data line gradually increases.
  • orthographic projections of the first end, the second end, the third end and the fourth end on the substrate are respectively aligned with the gate.
  • the orthographic projections of the poles on the substrate do not overlap with each other.
  • orthographic projections of the first end, the second end, the third end and the fourth end on the substrate are respectively aligned with the gate.
  • the orthographic projections of the poles on the substrate partially overlap.
  • the first end portion includes a first adjustment sub-portion and a first protection sub-portion, and the first adjustment sub-portion is located between the first body and the first protection sub-portion. between;
  • the minimum distance between the first adjustment sub-section and the data line gradually decreases, and the minimum distance between the first protection sub-section and the data line The minimum distance between them remains unchanged.
  • the fourth end portion includes a fourth adjustment sub-portion and a second protection sub-portion, and the fourth adjustment sub-portion is located between the second body and the second protection sub-portion. between;
  • the minimum distance between the fourth adjustment sub-section and the data line gradually increases, and the minimum distance between the second protection sub-section and the data line The minimum distance between them remains unchanged.
  • the first end portion includes a first adjustment sub-portion and a first protection sub-portion, and the first adjustment sub-portion is located between the first body and the first protection sub-portion. between; the second end includes a second adjustment sub-section; the third end includes a third adjustment sub-section; the fourth end includes a fourth adjustment sub-section and a second protection sub-section, and the Four adjustment sub-parts are located between the second body and the second protection sub-part;
  • the geometric center of the first adjustment sub-section, the geometric center of the second adjustment sub-section, the geometric center of the third adjustment sub-section and the geometric center of the fourth adjustment sub-section are on the substrate.
  • the minimum distance between the orthographic projection of the first protection sub-portion on the substrate and the orthographic projection of the gate on the substrate, the second protection sub-portion The minimum distance between the orthographic projection of the sub-portion on the substrate and the orthographic projection of the gate on the substrate, the orthographic projection of the first trace on the substrate to the gate
  • the minimum distance between the orthographic projection of the electrode on the substrate, and the minimum distance between the orthographic projection of the second trace on the substrate and the orthographic projection of the gate on the substrate The distances are all greater than or equal to 2 ⁇ m.
  • the shapes of orthographic projections of the first end, the second end, the third end and the fourth end on the substrate each include an arc. At least one of a shape, a polygon, and a shape formed by a combination of an arc and a polygon.
  • the orthographic projection shapes of the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section on the substrate Both are parallelograms, and the orthographic projection shapes of the first protective sub-portion and the second protective sub-portion on the substrate are both rectangular.
  • the size of the orthographic projection of the first adjustment sub-portion on the substrate along the first direction is the same as the orthogonal projection of the first protection sub-portion on the substrate.
  • the size of the projection along the first direction is equal, and the size of the orthogonal projection of the fourth adjustment sub-portion on the substrate along the first direction is the same as the size of the second protection sub-portion on the substrate.
  • Orthographic projections on the base have equal dimensions along the first direction.
  • the gate line includes a first line segment and a second line segment, the first line segment intersects and is insulated from the data line, and a partial area of the second line segment serves as the gate line segment. pole;
  • the dimension of the orthographic projection of the second line segment on the substrate along the direction perpendicular to the first direction is larger than the orthographic projection of the first line segment on the substrate along the dimension perpendicular to the first direction. Dimensions in direction.
  • the gate line includes a first line segment, a second line segment and a third line segment, the first line segment intersects and is insulated from the data line, and the second line segment serves as the Gate, the third line segment is located at an end of the second line segment away from the first line segment;
  • the dimension of the orthographic projection of the second line segment on the substrate along the direction perpendicular to the first direction is larger than the dimension of the orthographic projection of the third line segment on the substrate along the direction perpendicular to the first direction.
  • the upward dimension, and the dimension of the orthographic projection of the third line segment on the substrate along the direction perpendicular to the first direction is larger than the orthographic projection of the first line segment on the substrate along the dimension perpendicular to the first direction. the size in the first direction.
  • the array substrate further includes an active layer, the active layer is located on a side of the gate away from the substrate, and the active layer is on the substrate.
  • the outer contour of the orthographic projection is located within the outer contour of the orthographic projection of the gate on the substrate, and a partial region of the first pole and a partial region of the second pole are in direct contact with the active layer respectively.
  • the dimension of the orthographic projection of the active layer on the substrate along the direction perpendicular to the first direction is smaller than the dimension of the orthographic projection of the first body on the substrate along the direction perpendicular to the first direction.
  • the upward dimension, and the orthographic projection of the active layer on the substrate along the dimension perpendicular to the first direction is smaller than the orthographic projection of the second body on the substrate along the dimension perpendicular to the The size in the first direction.
  • the array substrate includes a first storage capacitor line, a second storage capacitor line, a third storage capacitor line and a fourth storage capacitor line arranged in the same layer as the gate electrode;
  • the first storage capacitor line, the second storage capacitor line and the third storage capacitor line are all located between two adjacent data lines, and all extend in the same direction as the data lines;
  • the fourth storage capacitor line intersects and is connected to the first storage capacitor line, the second storage capacitor line and the third storage capacitor line respectively, and the first storage capacitor line, the second storage capacitor line Orthographic projections of the capacitance line, the third storage capacitance line and the fourth storage capacitance line on the substrate respectively overlap with the orthographic projection of the pixel electrode on the substrate.
  • the second storage capacitor line is located between the first storage capacitor line and the third storage capacitor line
  • the array substrate further includes a a conductive island
  • the orthographic projection of the intersection of the second storage capacitor line and the fourth storage capacitor line on the substrate overlaps with the orthographic projection of the conductive island on the substrate, and the The conductive island is electrically connected to the pixel electrode.
  • embodiments of the present application provide a display panel, including the array substrate as described above.
  • Figures 1 and 2 are schematic structural diagrams of array substrates in two related technologies provided by embodiments of the present application.
  • Figures 3-13 are schematic structural diagrams of eleven array substrates provided by embodiments of the present application.
  • Figure 14 is a cross-sectional view along the B1B1 direction of Figure 13;
  • FIG. 15 is a cross-sectional view along the C1C2 direction of FIG. 13 .
  • the source and drain of the transistor are symmetrical, the source and drain can be interchanged.
  • one of the source electrode and the drain electrode of the transistor is called a first electrode, and the other of the source electrode and the drain electrode is called a second electrode.
  • the term "electrical connection” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.
  • An embodiment of the present application provides an array substrate, as shown in Figures 3 to 8, including:
  • the gate electrode of the thin film transistor extends along the first direction OA;
  • the first pole 4 of the thin film transistor includes a connected first body 41 and a first end 42;
  • the second pole 5 of the thin film transistor includes a connected second body 51 and a second end 52;
  • the orthographic projections of the first body 41 and the second body 42 on the substrate of the array substrate are respectively located within the orthographic projection of the gate on the substrate. At least part of the first end 42 and at least part of the second end 52
  • the orthographic projection of the region on the substrate does not overlap with the orthographic projection of the gate on the substrate respectively; and the orthographic projection of the first end 42 on the substrate and the orthographic projection of the second end 52 on the substrate Both are located on the same side of the orthographic projection of the gate on the substrate;
  • the average distance between the first end 42 and the second end 52 is greater than the average distance between the first body 41 and the second body 51 .
  • the average distance between the first end 42 and the second end 52 refers to: the maximum distance between the first end 42 and the second end 52 in the first direction OA. distance and the average of the minimum distance between the first end 42 and the second end 52 .
  • the average distance between the first body 41 and the second body 51 refers to the maximum distance between the first body 41 and the second body 51 and the distance between the first body 41 and the second body 51 . the average of the minimum distances between them.
  • the maximum distance, the minimum distance and the average distance between the first body 41 and the second body 51 are all equal to d1.
  • the minimum distance between the first end 42 and the second end 52 is equal to the average distance d1 between the first body 41 and the second body 51 .
  • the distance between the area where the first end 42 does not overlap with the gate and the area where the second end 43 does not overlap with the gate is greater than the distance between the first body 41 and the second body.
  • the distance between the first end 42 and the second end 52 in the first direction OA is represented by d2, where d2 >d1.
  • the type of the above-mentioned thin film transistor is not limited here.
  • the thin film transistor may be an N-type transistor, or the thin film transistor may be a P-type transistor.
  • a part of the gate line 2 in the array substrate can be used as the gate electrode of the thin film transistor; or, the gate line and the gate electrode of the thin film transistor can be set independently, so that the two who are connected.
  • a part of the gate line 2 is used as the gate electrode of the thin film transistor as an example.
  • the gate line and the gate electrode of the thin film transistor are made of the same material.
  • the material may include any one of copper, aluminum, nickel, molybdenum, and titanium, or a combination of at least two metals that are stacked.
  • the above-mentioned first direction OA is the horizontal direction.
  • the first direction OA can also be other directions, which can be specifically determined according to the design of the array substrate.
  • the first direction OA is used.
  • the direction OA is the horizontal direction as an example for explanation.
  • the first electrode 4 of the thin film transistor may be a source electrode, and the second electrode 5 of the thin film transistor may be a drain electrode; or, the first electrode 4 of the thin film transistor may be a drain electrode, and the thin film transistor may be a drain electrode.
  • the second pole 5 can be the source.
  • the first electrode 4 of the thin film transistor is the source electrode, and the second electrode 5 of the thin film transistor is the drain electrode.
  • the first electrode 4 and the second electrode 5 of the thin film transistor are both located in the same conductive layer, such as the source-drain metal layer SD.
  • the material of the source and drain metal layers may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of at least two metals arranged in a stack.
  • the orthographic projections of the first body 41 and the second body 42 on the substrate of the array substrate are respectively located within the orthographic projection of the gate on the substrate, including the following situations:
  • the outer contour of the orthographic projection of the first body 41 on the substrate of the array substrate and the outer contour of the orthographic projection of the second body 42 on the substrate of the array substrate are respectively located at the gate. Within the outer contour of the orthographic projection on the substrate.
  • the orthographic projection of at least a partial region of the first end 42 and at least a partial region of the second end 52 on the substrate does not overlap with the orthographic projection of the gate on the substrate, including the following situations:
  • the orthographic projection of a partial region of the first end 42 on the substrate and the orthographic projection of a partial region of the second end 52 on the substrate are respectively the same as the orthographic projection of the gate on the substrate. Orthographic projections do not overlap each other.
  • the orthographic projection of the first end 42 on the substrate and the orthographic projection of the second end 52 on the substrate are respectively the same as the orthographic projection of the gate on the substrate. Orthographic projections do not overlap each other.
  • the shape of the orthographic projection of the first end 42 on the substrate and the shape of the orthographic projection of the second end 52 on the substrate are not limited here, and can be determined based on the actual design.
  • the shape of the orthographic projection of the first end 42 on the substrate and the shape of the orthographic projection of the second end 52 on the substrate may be the same, or the shape of the orthographic projection of the first end 42 on the substrate may be the same.
  • the shape of the orthographic projection of the second end portion 52 on the substrate may be different.
  • the orthographic projection of the first end 42 on the substrate is a rectangle
  • the orthographic projection of the second end 52 on the substrate is a parallelogram
  • the shape of the orthographic projection of the first end 42 on the substrate is a figure composed of a rectangle and a parallelogram
  • the shape of the orthographic projection of the second end 52 on the substrate is a rectangle.
  • the first electrode and the second electrode of the thin film transistor located in the source and drain metal layer are different from the first electrode and the second electrode located in the gate layer.
  • the overlapping area between the gates shifts or the area of the overlapping area changes, causing the capacitance value of the parasitic capacitance generated in the two conductive layers to change, resulting in different parasitic capacitance values in different sub-pixels of the array substrate.
  • the influence of different parasitic capacitances on the charging rate of each sub-pixel is inconsistent, so that the charging rates of different sub-pixels are different.
  • the first electrode 4 of the thin film transistor is set.
  • the length of the second electrode 5 in the direction parallel to the data line 6 is greater than the width of the gate electrode in the direction parallel to the data line 6, so that even in the case of fluctuations in the manufacturing process, the first electrode 4 of the thin film transistor in different sub-pixels , the area of the overlapping region between the second electrode 5 and the gate electrode located in the gate layer tends to be consistent.
  • parts of the first electrode 4 and the second electrode 5 The area is at the climbing position shown by the dotted circle in Figure 2.
  • conductive material residues (such as metal material residues) are easily generated at the climbing position, so that in the dotted circle shown in Figure 1 A short circuit between the first pole 4 and the second pole 5 may easily occur at this location, causing abnormal use of the array substrate.
  • the first pole 4 by arranging the first pole 4 to include a first body 41 and a first end 42, the second pole 5 to include a second body 51 and a second end 52, the first end 42 and the second The end 52 is located on the same side of the gate, and both the projection of the first end 42 and the projection of the second end 52 have non-overlapping areas with the projection of the gate.
  • the first end The average distance between the end portion 42 and the second end portion 52 is greater than the average distance between the first body 41 and the second body 51. In this way, the distance between the first body 41 and the second body 51 can be ensured without changing the distance between the first body 41 and the second body 51.
  • the average distance between the first end 42 and the second end 52 is increased as much as possible, which greatly reduces the creep of the first pole 4 and the second pole 5.
  • the probability of short circuit occurring at the slope position improves the production yield and quality of the array substrate.
  • the first pole 4 also includes a third end 43, and the first body 41 connects the first end 42 and the third end 43;
  • the second pole 5 also includes a fourth end 53, and the second body 51 connects the second end 52 and the fourth end 53;
  • the orthographic projection of at least a partial region of the third end portion 43 and at least a partial region of the fourth end portion 53 on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate;
  • the average distance between the third end 43 and the fourth end 53 is greater than the average distance between the first body 41 and the second body 42 .
  • the average distance between the third end 43 and the fourth end 53 refers to: the maximum distance between the third end 43 and the fourth end 53 in the first direction OA. The average value of the distance and the minimum distance between the third end 43 and the fourth end 53 .
  • the average distance between the first body 41 and the second body 51 refers to the maximum distance between the first body 41 and the second body 51 and the distance between the first body 41 and the second body 51 . the average of the minimum distances between them.
  • the maximum distance, the minimum distance and the average distance between the first body 41 and the second body 51 are all equal to d1.
  • the minimum distance between the third end 43 and the fourth end 53 is equal to the average distance d1 between the first body 41 and the second body 51 .
  • the distance between the area where the third end 43 does not overlap with the gate and the area where the fourth end 53 does not overlap with the gate is larger than the distance between the first body 41 and the second body 51 The average distance d1 between them.
  • the distance between the third end 43 and the fourth end 53 in the first direction OA is represented by d3, where d3 >d1.
  • the relationship between the average distance between the third end 43 and the fourth end 53 and the average distance between the first end 42 and the second end 52 is not limited here. The details may be determined according to the actual product. Design confirmed.
  • the shape of the orthographic projection of the third end portion 43 on the substrate and the shape of the orthographic projection of the fourth end portion 53 on the substrate are not limited here, and can be determined based on the actual design.
  • the shape of the orthographic projection of the third end portion 43 on the substrate and the shape of the orthographic projection of the fourth end portion 53 on the substrate may be the same, or the shape of the orthographic projection of the third end portion 43 on the substrate may be the same.
  • the shape of the orthographic projection of the fourth end portion 53 on the substrate may be different.
  • the orthographic projection of at least a partial region of the third end 43 and at least a partial region of the fourth end 53 on the substrate does not overlap with the orthographic projection of the gate on the substrate, including the following situations:
  • the orthographic projection of the partial area of the third end 43 on the substrate and the orthographic projection of the partial area of the fourth end 53 on the substrate are respectively the same as the orthographic projection of the gate on the substrate. Orthographic projections do not overlap each other.
  • the orthographic projection of the third end 43 on the substrate and the orthographic projection of the fourth end 53 on the substrate are mutually exclusive with the orthographic projection of the gate on the substrate. No overlap.
  • the present application also includes a third end 43, and the first body 41 connects the first end 42 and the third end 43; the second pole 5 also includes a fourth end 53, and the second body 51 connects The second end portion 52 and the fourth end portion 53; the orthographic projection of at least a partial area of the third end portion 43 and at least a partial area of the fourth end portion 53 on the substrate are respectively mutually exclusive with the orthographic projection of the gate on the substrate. No overlap; in the first direction OA, the average distance between the third end 43 and the fourth end 53 is greater than the average distance between the first body 41 and the second body 42, so that the first body can be formed without changing the first body 41.
  • the average distance between the third end 43 and the fourth end 53 is as wide as possible, further reducing the distance between the first pole 4 and the second pole 5.
  • the probability of short circuit occurring at the climbing position improves the production yield and quality of the array substrate.
  • the array substrate also includes gate lines 2, data lines 6, pixel electrodes 15, first wiring lines 9 and second wiring lines 10.
  • the data lines 6 and The gate lines 2 intersect and are insulated.
  • the gate electrode and the gate line 2 are electrically connected.
  • the pixel electrode 15 is located at a position defined by two adjacent data lines 6 and two adjacent gate lines 2 .
  • the third end 43 of the first pole 4 The first wiring 9 is electrically connected to the data line 6.
  • the second end 52 of the second pole 5 is electrically connected to the pixel electrode 15 through the second wiring 10.
  • the second wiring 10 is electrically connected to the pixel electrode 15 through the via VIA1. connect;
  • the portion along the third end 43 connected to the first body 41 points in the direction of the portion connected between the third end 43 and the first trace 9 , and between the third end 43 and the data line 6 The minimum distance between them gradually decreases;
  • the minimum distance between the second end 52 and the data line 6 gradually increases.
  • the third end 43 of the first pole 4 may be arranged to be inclined in a direction away from the fourth end 53 of the second pole 5 , and the third end 43 of the second pole 5
  • the two ends 52 are inclined away from the first end 42 of the first pole 4, and a third end 43 is electrically connected to the data line through the first trace 9, and the second end 52 is connected to the second trace 9.
  • the wires 10 are electrically connected, so that in the first direction OA, the average distance between the third end 43 and the fourth end 53 is greater than the average distance between the first body 41 and the second body 42, and the first end
  • the average distance between the end portion 42 and the second end portion 52 is greater than the average distance between the first body 41 and the second body 51, so that the distance between the first body 41 and the second body 51 can be adjusted without changing the distance between the first body 41 and the second body 51.
  • the average distance between the first end 42 and the second end 52 is widened, and the average distance between the third end 43 and the fourth end 53 is widened as much as possible, which greatly reduces the first pole
  • the probability of short circuit between 4 and the second pole 5 at the climbing position improves the production yield and quality of the array substrate.
  • the part along the first end 42 connected to the first body 41 points in the direction of the part of the first end 42 away from the first body 41 , and the first end
  • the minimum distance between 42 and the second end 52 gradually increases, and the minimum distance between the first end 42 and the data line 6 gradually decreases;
  • the minimum distance between the fourth end 53 and the third end 43 gradually increases in the direction where the fourth end 53 is connected to the second body 51 in the direction of the part of the fourth end 53 away from the second body 51 . , and the minimum distance between the fourth end 43 and the data line 6 gradually increases.
  • the first end 42 of the first pole 4 is inclined away from the second end 52 of the second pole 5
  • the fourth end 53 of the second pole 5 is inclined away from the second end 52 of the second pole 5 .
  • the direction of the third end 43 in the first pole 4 is inclined, further increasing the average distance between the third end 43 and the fourth end 53 and the average distance between the first end 42 and the second end 52 distance, thereby further reducing the probability of short circuit between the first pole 4 and the second pole 5 at the climbing position, and improving the production yield and quality of the array substrate.
  • the orthographic projections of the first end 42 , the second end 52 , the third end 43 and the fourth end 53 on the substrate are respectively aligned with the gate electrode. Orthographic projections on the substrate do not overlap.
  • the orthographic projections of the first end, the second end, the third end and the fourth end on the substrate are respectively the same as the orthographic projections of the gate on the substrate. Orthographic projections partially overlap.
  • the first end portion 42 includes a first adjustment sub-portion 421 and a first protection sub-portion 422 .
  • the first adjustment sub-portion 421 is located between the first body 41 and the first protective sub-portion 422 . between the first protection sub-parts 422; in the direction in which the first body 41 points to the first end 42, the minimum distance between the first adjustment sub-part 421 and the data line 6 gradually decreases, and the first protection sub-part 422 reaches The minimum distance between data lines 6 remains unchanged.
  • the first adjusting sub-section 421 can adjust the distance between the first end 42 of the first pole 4 and the second end 52 of the second pole 5, thereby reducing the distance between the first pole 4 and the second pole 5.
  • the probability of short-circuiting diode 5 improves the production yield of the array substrate.
  • the first protection sub-section 422 on the one hand, it is possible to avoid sharp conductive patterns similar to the first adjustment sub-section 421 with a parallelogram projection shape as shown in FIG. 5 in the array substrate.
  • the minimum distance between the first adjustment sub-section 421 and the data line 6 is gradually reduced, and the minimum distance between the first protection sub-section 422 and the data line 6 remains unchanged, reducing the distance between the first pole 4 and the second pole. While reducing the probability of short circuit of pole 5, it avoids the occurrence of other abnormal problems caused by too small a distance between the first end 42 of the first pole and the data line 6, and also saves design space.
  • the fourth end portion 53 includes a fourth adjustment sub-portion 531 and a second protection sub-portion 532 .
  • the fourth adjustment sub-portion 531 is located between the second body 51 and the second protection sub-portion 532 . between the second protection sub-section 532; in the direction in which the second body 51 points to the fourth end 53, the minimum distance between the fourth adjustment sub-section 531 and the data line 6 gradually increases, and the second protection sub-section 532 reaches The minimum distance between data lines 6 remains unchanged.
  • the fourth adjustment sub-section 531 can adjust the distance between the fourth end 53 and the third end 43 to reduce the probability of a short circuit between the two.
  • the second protection sub-section 532 and the third end 43 After the four adjustment sub-sections 531 are connected, sharp conductive patterns can be avoided in the array substrate, thereby reducing the probability of electrostatic breakdown between the fourth end section 53 and the gate.
  • the fourth adjustment sub-section 531 is set to the data line The minimum distance between the first pole 4 and the second pole 5 gradually increases, and the minimum distance between the second protection sub-section 532 and the data line 6 remains unchanged, which reduces the probability of short circuit between the first pole 4 and the second pole 5 and saves design space.
  • the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section may be arranged in a direction parallel to the data line 6
  • the dimensions on are all greater than or equal to 2 ⁇ m.
  • the first end 42 includes a first adjustment sub-portion 421 and a first protection sub-portion 422 .
  • the first adjustment sub-portion 421 is located between the first body 41 and the first protection sub-portion 422 .
  • the second end part 52 includes a second adjusting sub-part;
  • the third end part 43 includes a third adjusting sub-part;
  • the fourth end part 53 includes a fourth adjusting sub-part 531 and a second protecting sub-part 532,
  • the fourth adjustment sub-part 531 is located between the second body 51 and the second protection sub-part 532;
  • the geometric center of the first adjusting sub-section 421 , the geometric center of the second adjusting sub-section of the second end 52 , the geometric center of the third adjusting sub-section of the third end 43 and the geometric center of the fourth adjusting sub-section 531 The orthographic projection of the center on the substrate respectively falls on the contour of the orthographic projection of the gate on the substrate.
  • the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section are all located at the climbing position on the side of the gate.
  • the conductive pattern is easily prone to cracks due to local stress concentration.
  • by setting the geometric center of the first adjusting sub-section 421, the geometric center of the second adjusting sub-section of the second end 52, the third end The orthographic projections of the geometric center of the third adjustment sub-section of the portion 43 and the geometric center of the fourth adjustment sub-section 531 on the substrate respectively fall on the outline of the orthographic projection of the gate on the substrate, so that the stress is more evenly dispersed. on the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section, thereby reducing the probability of cracks or fractures and improving the production yield and quality of the array substrate.
  • the first adjustment sub-section in order to make the stress more uniformly distributed on the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section, the first adjustment sub-section is provided.
  • the dimensions of the sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section along the direction OB parallel to the data line 6 are all greater than or equal to 4 ⁇ m.
  • the dimensions of the first protection sub-portion 422 and the second protection sub-portion 532 along the direction OB parallel to the data line 6 are both greater than or equal to 2 ⁇ m.
  • the orthographic projection of the first protection sub-section 422 on the substrate is the orthographic projection of the gate electrode (for example, a part of the gate line 2 ) on the substrate.
  • the minimum distance h3 between the orthographic projection of the gate on the substrate, and the minimum distance h2 between the orthographic projection of the second trace 10 on the substrate and the orthographic projection of the gate on the substrate are both greater than or equal to 2 ⁇ m. .
  • the sizes of the portions of the first adjustment sub-section, the second adjustment sub-section, the third adjustment sub-section and the fourth adjustment sub-section that do not overlap with the gate electrode along the direction OB parallel to the data line 6 are all greater than or equal to 2 ⁇ m. .
  • the shapes of the orthographic projections of the first end 42 , the second end 52 , the third end 43 and the fourth end 53 on the substrate each include an arc, a polygon, and an arc. At least one of the shapes formed by a combination of shapes and polygons.
  • the orthographic projection shape of the first end portion 42 on the substrate and the orthographic projection shape of the fourth end portion 53 on the substrate are both rectangular, and the second end portion 52 is on the substrate.
  • the orthographic projection shape on the substrate and the orthographic projection shape of the third end portion 43 on the substrate are both parallelograms.
  • the orthographic projection shape of the second end portion 52 on the substrate and the orthographic projection shape of the third end portion 43 on the substrate are both rectangular, and the first end portion 42 is on the substrate.
  • the orthographic projection shape and the orthographic projection shape of the fourth end portion 53 on the substrate are both shapes formed by a combination of a rectangle and a parallelogram.
  • the orthographic projection shape of the second end portion 52 on the substrate and the orthographic projection shape of the third end portion 43 on the substrate are both parallelograms, and the first end portion 42
  • the orthographic projection shape on the substrate and the orthographic projection shape of the fourth end portion 53 on the substrate are both shapes formed by a combination of a rectangle and a parallelogram.
  • the orthographic projection shape of the second end portion 52 on the substrate and the orthographic projection shape of the third end portion 43 on the substrate are both arc-shaped, and the first end portion 42
  • the orthographic projection shape on the substrate and the orthographic projection shape of the fourth end portion 53 on the substrate are both shapes formed by a combination of a rectangular shape and an arc shape.
  • the orthographic projections of the first adjustment sub-section 421 , the second adjustment sub-section 421 , the third adjustment sub-section 531 on the substrate are shown in FIG. 9 and FIG. 10 .
  • the shapes are all parallelograms, and the orthographic projection shapes of the first protection sub-portion 422 and the second protection sub-portion 532 on the substrate are both rectangular.
  • the size of the orthographic projection of the first adjustment sub-portion 421 on the substrate along the first direction OA is the same as the orthographic projection of the first protection sub-portion 422 on the substrate along the first direction OA. are equal in size, and the size of the orthographic projection of the fourth adjustment sub-portion 531 on the substrate along the first direction OA is equal to the size of the orthographic projection of the second protection sub-portion 532 on the substrate along the first direction OA.
  • the third adjustment sub-section is avoided.
  • the first regulating sub-portion 421 and the fourth regulating sub-portion 531 leak out sharp conductive patterns, thereby further reducing electrostatic breakdown (ESD) between the first end portion 42 and the gate electrode and between the fourth end portion 53 and the gate electrode. probability, further improving the production yield and quality of the array substrate.
  • ESD electrostatic breakdown
  • the gate line 2 includes a first line segment 21 and a second line segment 22 .
  • the first line segment 21 intersects and is insulated from the data line 6 , and a partial area of the second line segment 22 As a gate electrode; a gate insulation layer is provided between the gate line 2 and the data line 6;
  • the dimension of the orthographic projection of the second line segment 22 on the substrate along the direction perpendicular to the first direction OA is larger than the dimension of the orthographic projection of the first line segment 21 on the substrate along the direction perpendicular to the first direction OA.
  • the size of the parasitic capacitance generated between the data line 6 and the first line segment 21 can be reduced as much as possible. Reduce the negative impact of parasitic capacitance on the electrical signals in the array substrate.
  • Position misalignment can ensure that the area of the overlapping area of the gate electrode and the first electrode 4 in different transistors is consistent as much as possible, and the area of the area of the overlapping area of the gate electrode and the second electrode 5 is consistent, thereby reducing process fluctuations or alignment. Performance differences between thin film transistors that are not prepared on time improve the quality of array substrates.
  • the gate line 2 includes a first line segment 21 , a second line segment 22 and a third line segment 23 .
  • the first line segment 21 intersects and is insulated from the data line 6
  • the second line segment 21 intersects and is insulated from the data line 6 .
  • the line segment 22 serves as a gate
  • the third line segment 23 is located at an end of the second line segment 22 away from the first line segment 21;
  • the size of the orthographic projection of the second line segment 22 on the substrate along the direction perpendicular to the first direction OA is greater than the size of the orthographic projection of the third line segment 23 on the substrate along the direction perpendicular to the first direction OA, and the third line segment
  • the size of the orthographic projection of 23 on the substrate along the direction perpendicular to the first direction OA is larger than the size of the orthographic projection of the first line segment 21 on the substrate along the direction perpendicular to the first direction OA.
  • the size of the parasitic capacitance generated at the intersection of the data line 6 and the gate line 2 can be reduced, and the charging rate of the array substrate by the parasitic capacitance can be avoided.
  • the width of the second line segment 22 set as the gate electrode is the largest, which can tolerate the fluctuation of the preparation process and the position of the first electrode (second electrode) and the gate electrode offset, the first electrode ( The area of the area where the second electrode) overlaps with the gate electrode is stable, so that the electrical properties of the thin film transistor remain stable;
  • the width of the third line segment is set to be smaller than the width of the second line segment and greater than the width of the first line segment, while ensuring stable transmission of electrical signals, the design space is saved and the aperture ratio of the array substrate is increased, thereby improving the light transmittance of the display panel prepared from the array substrate.
  • the array substrate also includes an active layer 7 .
  • the active layer 7 is located on the side of the gate away from the substrate 1 .
  • the active layer 7 is on the side of the substrate 1 .
  • the outer contour of the orthographic projection on the gate is located within the outer contour of the orthographic projection of the gate on the substrate 1, and a partial area of the first pole 4 and a partial area of the second pole 5 are in direct contact with the active layer 7 respectively;
  • the size of the orthographic projection of the active layer 7 on the substrate 1 along the direction perpendicular to the first direction OA is smaller than the size of the orthographic projection of the first body 41 on the substrate 1 along the direction perpendicular to the first direction OA, and there is The size of the orthographic projection of the source layer 7 on the substrate 1 along the direction perpendicular to the first direction OA is smaller than the size of the orthographic projection of the second body 51 on the substrate 1 along the direction perpendicular to the first direction OA.
  • the material of the active layer 7 may include crystalline silicon or metal oxide.
  • crystalline silicon may include monocrystalline silicon, polycrystalline silicon, and amorphous silicon
  • metal oxide may include indium gallium zinc oxide (IGZO).
  • FIG. 14 is a cross-sectional view of the thin film transistor T in FIG. 13 along the B1B2 direction.
  • the width of the active layer 7 is smaller than the length of the first body 41 and smaller than the length of the second body 51 , since the distance between the first body 41 and the second body 51 is fixed, , in the case of fluctuations in the preparation process, the impact of process fluctuations on the width-to-length ratio of the thin-film transistor channel can be avoided as much as possible, and the negative impact of changes in the width-to-length ratio on the electrical properties of the thin-film transistor can be avoided, thereby avoiding the formation of thin films in different sub-pixels.
  • the transistors are electrically inconsistent.
  • the dimension of the orthographic projection of the active layer 7 on the substrate 1 along the first direction OA perpendicular to the first direction OA is the channel width of the thin film transistor, and the first body 41 extends along the first direction OA to the second direction OA.
  • the size between the bodies 51 is the channel width of the thin film transistor.
  • the minimum distance between the first body 41 and the second body 51 is equal to the maximum distance between the first body 41 and the second body 51 .
  • the dimension of the orthographic projection of the active layer 7 on the substrate 1 along the direction perpendicular to the first direction OA is greater than or equal to 5 ⁇ m.
  • the dimension of the orthographic projection of the first body 41 on the substrate 1 along the direction perpendicular to the first direction OA is the same as the orthographic projection of the second body 51 on the substrate 1 along the dimension perpendicular to the first direction OA.
  • the dimensions are equal.
  • the dimension of the orthographic projection of the first body 41 on the substrate 1 along the direction perpendicular to the first direction OA is greater than or equal to 8 ⁇ m.
  • the size of the orthographic projection of the gate on the substrate 1 along the direction perpendicular to the first direction OA is equal to the size of the orthographic projection of the first body 41 on the substrate 1 along the direction perpendicular to the first direction OA.
  • the size of the orthographic projection of the gate electrode on the substrate 1 along the direction perpendicular to the first direction OA is larger than the size of the orthographic projection of the first body 41 on the substrate 1 along the direction perpendicular to the first direction OA.
  • the distance between the dimension of the orthographic projection of the gate electrode on the substrate 1 along the direction perpendicular to the first direction OA and the dimension of the orthographic projection of the first body 41 on the substrate 1 along the dimension perpendicular to the first direction OA is The difference is greater than or equal to 4 ⁇ m.
  • the distance between the dimension of the orthographic projection of the gate electrode on the substrate 1 along the direction perpendicular to the first direction OA and the dimension of the orthographic projection of the active layer 7 on the substrate 1 along the dimension perpendicular to the first direction OA is The difference is greater than or equal to 5 ⁇ m.
  • the array substrate includes a first storage capacitor line 11 , a second storage capacitor line 12 , a third storage capacitor line 13 and a fourth storage capacitor arranged in the same layer as the gate electrode. line 14;
  • the first storage capacitor line 11, the second storage capacitor line 12 and the third storage capacitor line 13 are all located between two adjacent data lines 6, and all extend in the same direction as the data lines 6;
  • the fourth storage capacitor line 14 intersects and is connected to the first storage capacitor line 11 , the second storage capacitor line 12 and the third storage capacitor line 13 respectively, and the first storage capacitor line 11 , the second storage capacitor line 12 and the third storage capacitor line 13 are respectively connected to each other.
  • the orthographic projections of the capacitance line 13 and the fourth storage capacitance line 14 on the substrate respectively overlap with the orthographic projections of the pixel electrode 15 on the substrate.
  • a storage capacitor is formed between each storage capacitor line and the pixel electrode to store the power obtained by the sub-pixel during the charging process.
  • the second storage capacitor line 12 is located between the first storage capacitor line 11 and the third storage capacitor line 13 , and the array substrate also includes the data line 6 .
  • the conductive island 17 is arranged in layers, the orthographic projection of the intersection of the second storage capacitor line 12 and the fourth storage capacitor line 14 on the substrate 1 overlaps with the orthographic projection of the conductive island 17 on the substrate 1, and the conductive island 17 It is electrically connected to the pixel electrode 15 through the via hole VIA2.
  • FIG. 15 is a cross-sectional view along the C1C2 direction of FIG. 13 .
  • the gate electrode and the gate line are located in the same conductive layer, such as the gate layer Gate, and the first electrode of the thin film transistor, the second electrode of the thin film transistor, the data line and the conductive island are located in the same conductive layer, such as the source In the drain metal layer SD, in addition, in Figure 13, the film layer marked Active represents the active layer, and the film layer marked Pixel ITO represents the pixel electrode.
  • a gate insulating layer 3 is provided between the gate layer Gate and the source-drain metal layer SD, and an interlayer dielectric layer 16 is provided between the source-drain metal layer SD and the pixel electrode Pixel ITO.
  • the position of the conductive island 17 can be broken down by laser, so that the pixel electrode 15 is connected to the memory.
  • the electrode lines 12/14 are turned on, thereby short-circuiting the circuit in the abnormally displayed sub-pixel, causing no display, thus avoiding the negative impact of the abnormal sub-pixel on the overall display effect of the display panel prepared on the array substrate, and improving display effect.
  • An embodiment of the present application provides a display panel, including the array substrate as described above.
  • the display panel may further include a color filter substrate, and the color filter substrate is arranged opposite to the array substrate.
  • the display panel provided by the embodiment of the present application is a liquid crystal display panel (LCD, Liquid Crystal Display).
  • the display panel can be a display device such as an LCD monitor, as well as any TV, digital camera, mobile phone, tablet computer, etc. including these display devices. Products or components with display functions.
  • the above display panel is a liquid crystal display panel in the ADS (Advanced Super Dimension Switch) display mode, where ADS is the collective name for core technologies represented by wide viewing angle technology.
  • ADS Advanced Super Dimension Switch
  • the first pole 4 includes a first body 41 and a first end 42
  • the second pole 5 includes a second body 51 and a second end 52
  • the first end 42 and the second end 52 are located on the same side of the gate, and both the projection of the first end 42 and the projection of the second end 52 have non-overlapping areas with the projection of the gate, by being arranged in the first direction OA , the average distance between the first end 42 and the second end 52 is greater than the average distance between the first body 41 and the second body 51. In this way, the distance between the first body 41 and the second body 51 can be changed without changing the distance between the first body 41 and the second body 51.
  • the spacing ensures that the distance between the first end 42 and the second end 52 is as wide as possible while the width-to-length ratio of the thin film transistor remains unchanged, which greatly reduces the distance between the first pole 4 and the second pole. 5.
  • the probability of short circuit occurring at the climbing position improves the production yield and quality of the display panel, and improves the display effect of the display panel.

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Abstract

本申请提供了一种阵列基板、显示面板，该阵列基板包括薄膜晶体管的栅极，沿第一方向延伸；薄膜晶体管的第一极，包括相连的第一本体和第一端部；薄膜晶体管的第二极，包括相连的第二本体和第二端部；第一本体和第二本体在阵列基板的衬底上的正投影分别位于栅极在衬底上的正投影以内，第一端部的至少部分区域和第二端部的至少部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠，且第一端部在衬底上的正投影和第二端部在衬底上的正投影均位于栅极在衬底上的正投影的同一侧；其中，在第一方向上，第一端部到第二端部之间的平均距离大于第一本体到第二本体之间的平均距离。该阵列基板的制备良率高，品质好。

Description

阵列基板、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板。
背景技术
随着显示技术的快速发展，业内对显示产品中阵列基板的性能和品质要求越来越高，然而，在相关技术中，在制备工艺不稳定或制备精度有限的情况下，膜层间极易产生电容值大小不同的寄生电容或出现其它不良问题，导致阵列基板的制备良率和品质降低。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种阵列基板，包括：
薄膜晶体管的栅极，沿第一方向延伸；
所述薄膜晶体管的第一极，包括相连的第一本体和第一端部；
所述薄膜晶体管的第二极，包括相连的第二本体和第二端部；
所述第一本体和所述第二本体在所述阵列基板的衬底上的正投影分别位于所述栅极在所述衬底上的正投影以内，所述第一端部的至少部分区域和所述第二端部的至少部分区域在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影互不交叠，且所述第一端部在所述衬底上的正投影和所述第二端部在所述衬底上的正投影均位于所述栅极在所述衬底上的正投影的同一侧；
其中，在所述第一方向上，所述第一端部到所述第二端部之间的平均距离大于所述第一本体到所述第二本体之间的平均距离。
在本申请的一些实施例中，所述第一极还包括第三端部，所述第一本体连接所述第一端部和所述第三端部；所述第二极还包括第四端部，所述第二本体连接所述第二端部和所述第四端部；
所述第三端部的至少部分区域和所述第四端部的至少部分区域在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影互不交叠；
在所述第一方向上，所述第三端部到所述第四端部之间的平均距离大于所述第一本体到所述第二本体之间的平均距离。
在本申请的一些实施例中，所述阵列基板还包括栅线、数据线、像 素电极、第一走线和第二走线，所述数据线和所述栅线相交且绝缘，所述栅极和所述栅线电连接，所述像素电极位于相邻两条所述数据线和相邻两条所述栅线限定的位置处，所述第一极的所述第三端部通过所述第一走线与所述数据线电连接，所述第二极的所述第二端部通过所述第二走线与所述像素电极电连接；
其中，沿所述第三端部与所述第一本体连接的部分指向所述第三端部与所述第一走线连接的部分的方向上，所述第三端部到所述数据线之间的最小距离逐渐减小；
沿所述第二端部与所述第二本体连接的部分指向所述第二端部与所述第二走线连接的部分的方向上，所述第二端部到所述数据线之间的最小距离逐渐增大。
在本申请的一些实施例中，沿所述第一端部与所述第一本体连接的部分指向所述第一端部远离所述第一本体的部分的方向上，所述第一端部到所述第二端部之间的最小距离逐渐增大，且所述第一端部到所述数据线之间的最小距离逐渐减小；
沿所述第四端部与所述第二本体连接的部分指向所述第四端部远离所述第二本体的部分的方向上，所述第四端部到所述第三端部之间的最小距离逐渐增大，且所述第四端部到所述数据线之间的最小距离逐渐增大。
在本申请的一些实施例中，所述第一端部、所述第二端部、所述第三端部和所述第四端部在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影互不交叠。
在本申请的一些实施例中，所述第一端部、所述第二端部、所述第三端部和所述第四端部在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影部分交叠。
在本申请的一些实施例中，所述第一端部包括第一调节子部和第一保护子部，所述第一调节子部位于所述第一本体与所述第一保护子部之间；
沿所述第一本体指向所述第一端部的方向上，所述第一调节子部到所述数据线之间的最小距离逐渐减小，所述第一保护子部到所述数据线之间的最小距离保持不变。
在本申请的一些实施例中，所述第四端部包括第四调节子部和第二 保护子部，所述第四调节子部位于所述第二本体与所述第二保护子部之间；
沿所述第二本体指向所述第四端部的方向上，所述第四调节子部到所述数据线之间的最小距离逐渐增大，所述第二保护子部到所述数据线之间的最小距离保持不变。
在本申请的一些实施例中，所述第一端部包括第一调节子部和第一保护子部，所述第一调节子部位于所述第一本体与所述第一保护子部之间；所述第二端部包括第二调节子部；所述第三端部包括第三调节子部；所述第四端部包括第四调节子部和第二保护子部，所述第四调节子部位于所述第二本体与所述第二保护子部之间；
其中，所述第一调节子部的几何中心、所述第二调节子部的几何中心、所述第三调节子部的几何中心和所述第四调节子部的几何中心在所述衬底上的正投影分别落入所述栅极在所述衬底上的正投影的轮廓上。
在本申请的一些实施例中，所述第一保护子部在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离、所述第二保护子部在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离、所述第一走线在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离、以及所述第二走线在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离均大于或等于2μm。
在本申请的一些实施例中，所述第一端部、所述第二端部、所述第三端部和所述第四端部在所述衬底上的正投影的形状均包括弧形、多边形、以及弧形和多边形组合形成的形状中的至少一种。
在本申请的一些实施例中，所述第一调节子部、所述第二调节子部、所述第三调节子部和所述第四调节子部在所述衬底上的正投影形状均为平行四边形，且所述第一保护子部和所述第二保护子部在所述衬底上的正投影形状均矩形。
在本申请的一些实施例中，所述第一调节子部在所述衬底上的正投影沿所述第一方向上的尺寸与所述第一保护子部在所述衬底上的正投影沿所述第一方向上的尺寸相等，且所述第四调节子部在所述衬底上的正投影沿所述第一方向上的尺寸与所述第二保护子部在所述衬底上的正投影沿所述第一方向上的尺寸相等。
在本申请的一些实施例中，所述栅线包括第一线段和第二线段，所 述第一线段与所述数据线相交且绝缘，所述第二线段的部分区域作为所述栅极；
其中，所述第二线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸大于所述第一线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸。
在本申请的一些实施例中，所述栅线包括第一线段、第二线段和第三线段，所述第一线段与所述数据线相交且绝缘，所述第二线段作为所述栅极，所述第三线段位于所述第二线段远离所述第一线段的一端；
其中，所述第二线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸大于所述第三线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸，且所述第三线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸大于所述第一线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸。
在本申请的一些实施例中，所述阵列基板还包括有源层，所述有源层位于所述栅极远离所述衬底的一侧，所述有源层在所述衬底上的正投影的外轮廓位于所述栅极在所述衬底上的正投影的外轮廓以内，所述第一极的部分区域和所述第二极的部分区域分别与所述有源层直接接触；
其中，所述有源层在所述衬底上的正投影沿垂直于所述第一方向上的尺寸小于所述第一本体在所述衬底上的正投影沿垂直于所述第一方向上的尺寸，且所述有源层在所述衬底上的正投影沿垂直于所述第一方向上的尺寸小于所述第二本体在所述衬底上的正投影沿垂直于所述第一方向上的尺寸。
在本申请的一些实施例中，所述阵列基板包括与所述栅极同层设置的第一存储电容线、第二存储电容线、第三存储电容线和第四存储电容线；
所述第一存储电容线、所述第二存储电容线和所述第三存储电容线均位于相邻的两条所述数据线之间，且均与所述数据线的延伸方向相同；
所述第四存储电容线分别与所述第一存储电容线、所述第二存储电容线和所述第三存储电容线相交且连接，且所述第一存储电容线、所述第二存储电容线、所述第三存储电容线和所述第四存储电容线在所述衬底上的正投影分别与所述像素电极在所述衬底上的正投影交叠。
在本申请的一些实施例中，所述第二存储电容线位于所述第一存储 电容线和所述第三存储电容线之间，所述阵列基板还包括与所述数据线同层设置的导电岛，所述第二存储电容线与所述第四存储电容线的相交处在所述衬底上的正投影与所述导电岛在所述衬底上的正投影交叠，且所述导电岛与所述像素电极电连接。
第二方面，本申请的实施例提供了一种显示面板，包括如前文所述的阵列基板。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1和图2为本申请实施例提供的两种相关技术中的阵列基板的结构示意图。
图3-图13为本申请实施例提供的十一种阵列基板的结构示意图；
图14为图13沿B1B1方向的截面图；
图15为图13沿C1C2方向的截面图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。
在本申请的实施例中，除非另有说明，“多个”的含义是两个或两个 以上；术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的实施例中，由于晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本申请的实施例中，将晶体管的源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。
在本发明的实施例中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其他组件电连接。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
本申请的实施例提供了一种阵列基板，参考图3-图8所示，包括：
薄膜晶体管的栅极，沿第一方向OA延伸；
薄膜晶体管的第一极4，包括相连的第一本体41和第一端部42；
薄膜晶体管的第二极5，包括相连的第二本体51和第二端部52；
第一本体41和第二本体42在阵列基板的衬底上的正投影分别位于栅极在衬底上的正投影以内，第一端部42的至少部分区域和第二端部52的至少部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠；且第一端部42在衬底上的正投影和第二端部52在衬底上的正投影均位于栅极在衬底上的正投影的同一侧；
其中，在第一方向OA上，第一端部42到第二端部52之间的平均距离大于第一本体41到第二本体51之间的平均距离。
在示例性的实施例中，第一端部42到第二端部52之间的平均距离指的是：在第一方向OA上，第一端部42到第二端部52之间的最大距离与第一端部42到第二端部52之间的最小距离的平均值。
在示例性的实施例中，第一本体41到第二本体51之间的平均距离指的是第一本体41到第二本体51之间的最大距离与第一本体41到第二本体51之间的最小距离的平均值。示例性的，第一本体41到第二本体51之间的最大距离、最小距离和平均距离均等于d1。
示例性的，参考图3所示，在第一方向OA上，第一端部42到第二端部52之间的最小距离等于第一本体41到第二本体51之间的平均距离d1。在第一方向OA上，第一端部42与栅极不不交叠的区域到第二端部43与栅极不不交叠的区域之间的距离均大于第一本体41到第二本体51之间的平均距离d1。
除第一端部42到第二端部52之间的最小距离之外，在第一方向OA上，第一端部42到第二端部52之间的距离均用d2表示，其中，d2＞d1。
这里对于上述薄膜晶体管的类型不进行限定。示例性的，薄膜晶体管可以为N型晶体管，或者，薄膜晶体管可以为P型晶体管。
在示例性的实施例中，参考图3所示，阵列基板中的栅线2的一部分可以作为薄膜晶体管的栅极；或者，可以将栅线和薄膜晶体管的栅极各自独立设置，并使得两者相连。在本申请的实施例提供的附图中，均以栅线2的一部分作为薄膜晶体管的栅极为例进行绘制。
示例性的，栅线和薄膜晶体管的栅极的材料相同，例如，其材料可以包括铜、铝、镍、钼和钛中的任意一种或者层叠设置的至少两种金属的组合。
示例性的，在图3中，上述第一方向OA为水平方向，实际上，第一方向OA还可以是其它方向，具体可以根据阵列基板的设计确定，本申请的实施例中均以第一方向OA为水平方向为例进行说明。
在示例性的实施例中，上述薄膜晶体管的第一极4可以为源极，薄膜晶体管的第二极5可以为漏极；或者，上述薄膜晶体管的第一极4可以为漏极，薄膜晶体管的第二极5可以为源极。在本申请的实施例中，以上述薄膜晶体管的第一极4为源极，薄膜晶体管的第二极5为漏极为例进行说明。
在示例性的实施例中，薄膜晶体管的第一极4和第二极5均位于同一层导电层中，例如源漏金属层SD。示例性的，源漏金属层的材料可以包括铜、铝、镍、钼和钛中的任意一种或者层叠设置的至少两种金属的组合。
其中，第一本体41和第二本体42在阵列基板的衬底上的正投影分别位于栅极在衬底上的正投影以内包括以下情况：
第一种，参考图3、图4或图5所示，第一本体41在阵列基板的衬底上的正投影的外轮廓和第二本体42在阵列基板的衬底上的正投影的外轮廓分别与栅极在衬底上的正投影的外轮廓部分重叠。
第二种，参考图6所示，第一本体41在阵列基板的衬底上的正投影的外轮廓和第二本体42在阵列基板的衬底上的正投影的外轮廓分别位于栅极在衬底上的正投影的外轮廓以内。
其中，第一端部42的至少部分区域和第二端部52的至少部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠包括以下情况：
第一种，参考图6所示，第一端部42的部分区域在衬底上的正投影和第二端部52的部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠。
第二种，参考图3、图4或图5所示，第一端部42在衬底上的正投影和第二端部52在衬底上的正投影分别与栅极在衬底上的正投影互不交叠。
这里对于第一端部42在衬底上的正投影的形状和第二端部52在衬底上的正投影的形状不进行限定，具体可以根据实际设计确定。
另外，第一端部42在衬底上的正投影的形状和第二端部52在衬底上的正投影的形状可以相同，或者，第一端部42在衬底上的正投影的形状和第二端部52在衬底上的正投影的形状可以不同。
例如，参考图3所示，第一端部42在衬底上的正投影的形状为矩形，第二端部52在衬底上的正投影的形状为平行四边形。
又例如，参考图4所示，第一端部42在衬底上的正投影的形状为矩形和平行四边形构成的图形，第二端部52在衬底上的正投影的形状为矩形。
在相关技术中，在制备阵列基板的过程中，在制备工艺波动或者对 位精度有限的情况下，位于源漏金属层中的薄膜晶体管的第一极、第二极与位于栅极层中的栅极之间的交叠区域发生移位或者交叠区域的面积发生变化，使得两层导电层中产生的寄生电容的电容值发生变化，从而使得阵列基板的不同子像素中的寄生电容值不同，这样，不同寄生电容对各子像素的充电率的影响程度不一致，以致不同子像素的充电率不同，为了改善这个问题，参考图1所示，相关技术中设置薄膜晶体管的第一极4、第二极5沿平行于数据线6方向上的长度大于栅极沿平行于数据线6方向上的宽度，以使得即使在制备工艺波动的情况下，不同子像素中薄膜晶体管的第一极4、第二极5与位于栅极层中的栅极之间的交叠区域的面积趋于一致，然而，由于位于底层的栅极的厚度的影响，第一极4和第二极5的部分区域处于如图2中虚线圈所示的爬坡位置处，在阵列基板制备过程中，爬坡位置处极易产生导电材料残留(例如金属材料残留)，以致在图1所示的虚线圈的位置处容易发生第一极4和第二极5的短路，造成阵列基板的使用异常。
在本申请的实施例中，通过设置第一极4包括第一本体41和第一端部42，第二极5包括第二本体51和第二端部52，第一端部42和第二端部52位于栅极的同一侧，且第一端部42的投影和第二端部52的投影均与栅极的投影存在不交叠区，通过设置在第一方向OA上，第一端部42到第二端部52之间的平均距离大于第一本体41到第二本体51之间的平均距离，这样，可以在不改变第一本体41到第二本体51之间的间距，确保薄膜晶体管的宽长比不变的情况下，尽可能拉开第一端部42到第二端部52之间的平均距离，很大程度上降低了第一极4和第二极5在爬坡位置处发生短路的概率，提升了阵列基板的制备良率和品质。
在本申请的一些实施例中，参考图3-图8所示，第一极4还包括第三端部43，第一本体41连接第一端部42和第三端部43；第二极5还包括第四端部53，第二本体51连接第二端部52和第四端部53；
第三端部43的至少部分区域和第四端部53的至少部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠；
在第一方向OA上，第三端部43到第四端部53之间的平均距离大于第一本体41到第二本体42之间的平均距离。
在示例性的实施例中，第三端部43到第四端部53之间的平均距离 指的是：在第一方向OA上，第三端部43到第四端部53之间的最大距离与第三端部43到第四端部53之间的最小距离的平均值。
在示例性的实施例中，第一本体41到第二本体51之间的平均距离指的是第一本体41到第二本体51之间的最大距离与第一本体41到第二本体51之间的最小距离的平均值。示例性的，第一本体41到第二本体51之间的最大距离、最小距离和平均距离均等于d1。
示例性的，参考图3所示，在第一方向OA上，第三端部43到第四端部53之间的最小距离等于第一本体41到第二本体51之间的平均距离d1。在第一方向OA上，第三端部43与栅极不不交叠的区域到第四端部53与栅极不不交叠的区域之间距离均大于第一本体41到第二本体51之间的平均距离d1。
除第三端部43到第四端部53之间的最小距离之外，在第一方向OA上，第三端部43到第四端部53之间的距离均用d3表示，其中，d3＞d1。
这里对于第三端部43到第四端部53之间的平均距离与第一端部42到第二端部52之间的平均距离之间的大小关系不进行限定，具体可以根据实际产品的设计确定。
这里对于第三端部43在衬底上的正投影的形状和第四端部53在衬底上的正投影的形状不进行限定，具体可以根据实际设计确定。
另外，第三端部43在衬底上的正投影的形状和第四端部53在衬底上的正投影的形状可以相同，或者，第三端部43在衬底上的正投影的形状和第四端部53在衬底上的正投影的形状可以不同。
其中，第三端部43的至少部分区域和第四端部53的至少部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠包括以下情况：
第一种，参考图6所示，第三端部43的部分区域在衬底上的正投影和第四端部53的部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠。
第二种，参考图3-图5所示，第三端部43在衬底上的正投影和第四端部53在衬底上的正投影分别与栅极在衬底上的正投影互不交叠。
在本申请的实施例中，还包括第三端部43，第一本体41连接第一端部42和第三端部43；第二极5还包括第四端部53，第二本体51连 接第二端部52和第四端部53；第三端部43的至少部分区域和第四端部53的至少部分区域在衬底上的正投影分别与栅极在衬底上的正投影互不交叠；在第一方向OA上，第三端部43到第四端部53之间的平均距离大于第一本体41到第二本体42之间的平均距离，这样，可以在不改变第一本体41到第二本体51之间的间距的情况下，尽可能拉开第三端部43到第四端部53之间的平均距离，进一步降低了第一极4和第二极5在爬坡位置处发生短路的概率，提升了阵列基板的制备良率和品质。
在本申请的一些实施例中，结合图3和图13所示，阵列基板还包括栅线2、数据线6、像素电极15、第一走线9和第二走线10，数据线6和栅线2相交且绝缘，栅极和栅线2电连接，像素电极15位于相邻两条数据线6和相邻两条栅线2限定的位置处，第一极4的第三端部43通过第一走线9与数据线6电连接，第二极5的第二端部52通过第二走线10与像素电极15电连接；第二走线10通过过孔VIA1与像素电极15电连接；
其中，在图3中，沿第三端部43与第一本体41连接的部分指向第三端部43与第一走线9连接的部分的方向上，第三端部43到数据线6之间的最小距离逐渐减小；
沿第二端部52与第二本体51连接的部分指向第二端部52与第二走线10连接的部分的方向上，第二端部52到数据线6之间的最小距离逐渐增大。
在本申请的实施例中，参考图3所示，可以设置第一极4中的第三端部43向远离第二极5中第四端部53的方向倾斜，第二极5中的第二端部52向远离第一极4中的第一端部42的方向倾斜，再设置第三端部43通过第一走线9与数据线电连接，设置第二端部52与第二走线10电连接，这样，在第一方向OA上，第三端部43到第四端部53之间的平均距离大于第一本体41到第二本体42之间的平均距离，且第一端部42到第二端部52之间的平均距离大于第一本体41到第二本体51之间的平均距离，从而可以在不改变第一本体41到第二本体51之间的间距的情况下，尽可能拉开第一端部42到第二端部52之间的平均距离，拉开第三端部43到第四端部53之间的平均距离，很大程度上降低了第一极4和第二极5在爬坡位置处发生短路的概率，提升了阵列基板的制备 良率和品质。
在本申请的一些实施例中，参考图5所示，沿第一端部42与第一本体41连接的部分指向第一端部42远离第一本体41的部分的方向上，第一端部42到第二端部52之间的最小距离逐渐增大，且第一端部42到数据线6之间的最小距离逐渐减小；
沿第四端部53与第二本体51连接的部分指向第四端部53远离第二本体51的部分的方向上，第四端部53到第三端部43之间的最小距离逐渐增大，且第四端部43到数据线6之间的最小距离逐渐增大。
在本申请的实施例中，可以设置第一极4中的第一端部42向远离第二极5中第二端部52的方向倾斜，第二极5中的第四端部53向远离第一极4中的第三端部43的方向倾斜，进一步增大第三端部43到第四端部53之间的平均距离以及第一端部42到第二端部52之间的平均距离，从而进一步降低了第一极4和第二极5在爬坡位置处发生短路的概率，提升了阵列基板的制备良率和品质。
在本申请的一些实施例中，参考图5所示，第一端部42、第二端部52、第三端部43和第四端部53在衬底上的正投影分别与栅极在衬底上的正投影互不交叠。
在本申请的一些实施例中，参考图6所示，第一端部、第二端部、第三端部和第四端部在衬底上的正投影分别与栅极在衬底上的正投影部分交叠。
在本申请的一些实施例中，参考图5-图8所示，第一端部42包括第一调节子部421和第一保护子部422，第一调节子部421位于第一本体41与第一保护子部422之间；沿第一本体41指向第一端部42的方向上，第一调节子部421到数据线6之间的最小距离逐渐减小，第一保护子部422到数据线6之间的最小距离保持不变。
在本申请的实施例中，第一调节子部421能够调整第一极4的第一端部42到第二极5的第二端部52之间的距离，从而降低第一极4与第二极5短路的概率，提高阵列基板的制备良率。另外，通过设置第一保护子部422，一方面，能够避免阵列基板中出现类似于如图5中所示的投影形状为平行四边形的第一调节子部421的尖锐的导电图形，另一方面，能够增加第一端部42的尖端位置到栅极之间的距离，避免第一端部42与栅极之间发生静电击穿，从而进一步提高阵列基板的制备良率， 提高阵列基板的品质。进一步的，设置第一调节子部421到数据线6之间的最小距离逐渐减小，第一保护子部422到数据线6之间的最小距离保持不变，降低第一极4与第二极5短路的概率的同时，避免了第一极的第一端部42距离数据线6之间的距离太小造成其它异常问题的发生，也节省了设计空间。
在本申请的一些实施例中，参考图5-图8所示，第四端部53包括第四调节子部531和第二保护子部532，第四调节子部531位于第二本体51与第二保护子部532之间；沿第二本体51指向第四端部53的方向上，第四调节子部531到数据线6之间的最小距离逐渐增大，第二保护子部532到数据线6之间的最小距离保持不变。
在本申请的实施例中，第四调节子部531能够调节第四端部53到第三端部43之间的距离，降低两者之间发生短路的概率，第二保护子部532与第四调节子部531连接之后，能够避免阵列基板中出现尖锐的导电图形，从而降低第四端部53与栅极之间发生静电击穿的概率，另外，设置第四调节子部531到数据线6之间的最小距离逐渐增大，第二保护子部532到数据线6之间的最小距离保持不变，降低第一极4与第二极5短路的概率的同时，节省了设计空间。
在示例性的实施例中，在如图5所示的结构中，可以设置第一调节子部、第二调节子部、第三调节子部和第四调节子部沿平行于数据线6方向上的尺寸均大于或等于2μm。
在本申请的一些实施例中，参考图6所示，第一端部42包括第一调节子部421和第一保护子部422，第一调节子部421位于第一本体41与第一保护子部422之间；第二端部52包括第二调节子部；第三端部43包括第三调节子部；第四端部53包括第四调节子部531和第二保护子部532，第四调节子部531位于第二本体51与第二保护子部532之间；
其中，第一调节子部421的几何中心、第二端部52的第二调节子部的几何中心、第三端部43的第三调节子部的几何中心和第四调节子部531的几何中心在衬底上的正投影分别落入栅极在衬底上的正投影的轮廓上。
在实际应用中，由于栅极具有一定厚度，第一调节子部、第二调节子部、第三调节子部和第四调节子部均位于栅极侧面的爬坡位置处，爬 坡位置处的导电图案极易由于局部应力集中产生裂纹，在本申请的实施例中，通过设置第一调节子部421的几何中心、第二端部52的第二调节子部的几何中心、第三端部43的第三调节子部的几何中心和第四调节子部531的几何中心在衬底上的正投影分别落入栅极在衬底上的正投影的轮廓上，使得应力更均匀的分散在第一调节子部、第二调节子部、第三调节子部和第四调节子部上，从而降低其发生裂纹或断裂的概率，提高阵列基板的制备良率和品质。
另外，在图6中，在制备工艺波动的情况下，当第一极(第二极)与栅极之间的位置发生偏移时，仍然能够使得第一极的第一调节子部(第二极的第四调节子部)在栅极的爬坡位置处，从而使得爬坡位置处第一端部到第二端部之间的距离较大，第三端部到第四端部之间的距离较大，避免第一极和第二极之间发生短路，降低了制备工艺难度。
在示例性的实施例中，在图6中，为了使得应力更均匀的分散在第一调节子部、第二调节子部、第三调节子部和第四调节子部上，设置第一调节子部、第二调节子部、第三调节子部和第四调节子部沿平行于数据线6方向OB上的尺寸均大于或等于4μm。
在示例性的实施例中，第一保护子部422和第二保护子部532沿平行于数据线6方向OB上的尺寸均大于或等于2μm。
在本申请的一些实施例中，参考图9或图10所示，第一保护子部422在衬底上的正投影到栅极(例如栅线2的一部分区域)在衬底上的正投影之间的最小距离h1、第二保护子部532在衬底上的正投影到栅极在衬底上的正投影之间的最小距离h4、第一走线9在衬底上的正投影到栅极在衬底上的正投影之间的最小距离h3、以及第二走线10在衬底上的正投影到栅极在衬底上的正投影之间的最小距离h2均大于或等于2μm。
此时，第一调节子部、第二调节子部、第三调节子部和第四调节子部与栅极不交叠的部分沿平行于数据线6方向OB上的尺寸均大于或等于2μm。
在本申请的一些实施例中，第一端部42、第二端部52、第三端部43和第四端部53在衬底上的正投影的形状均包括弧形、多边形、以及弧形和多边形组合形成的形状中的至少一种。
示例性的，参考图3所示，第一端部42在衬底上的正投影形状和 第四端部53在衬底上的正投影的形状均为矩形，第二端部52在衬底上的正投影形状和第三端部43在衬底上的正投影形状均为平行四边形。
示例性的，参考图4所示，第二端部52在衬底上的正投影形状和第三端部43在衬底上的正投影形状均为矩形，第一端部42在衬底上的正投影形状和第四端部53在衬底上的正投影的形状均矩形和平行四边形组合形成的形状。
示例性的，参考图5和图6所示，第二端部52在衬底上的正投影形状和第三端部43在衬底上的正投影形状均为平行四边形，第一端部42在衬底上的正投影形状和第四端部53在衬底上的正投影的形状均矩形和平行四边形组合形成的形状。
示例性的，参考图7和图8所示，第二端部52在衬底上的正投影形状和第三端部43在衬底上的正投影形状均为弧形，第一端部42在衬底上的正投影形状和第四端部53在衬底上的正投影的形状均矩形和弧形组合形成的形状。
在本申请的一些实施例中，参考图9和图10所示，第一调节子部421、第二调节子部、第三调节子部和第四调节子部531在衬底上的正投影形状均为平行四边形，且第一保护子部422和第二保护子部532在衬底上的正投影形状均矩形。
在本申请的一些实施例中，第一调节子部421在衬底上的正投影沿第一方向OA上的尺寸与第一保护子部422在衬底上的正投影沿第一方向OA上的尺寸相等，且第四调节子部531在衬底上的正投影沿第一方向OA上的尺寸与第二保护子部532在衬底上的正投影沿第一方向OA尺寸相等。
在本申请的实施例中，通过设置第一调节子部421的宽度与第一保护子部422的宽度相等，第四调节子部531的宽度与第二保护子部532的宽度，避免了第一调节子部421和第四调节子部531漏出尖锐的导电图案，从而进一步降低了第一端部42与栅极之间、第四端部53与栅极之间发生静电击穿(ESD)的概率，进一步提高了阵列基板的制备良率和品质。
在本申请的一些实施例中，参考图11所示，栅线2包括第一线段21和第二线段22，第一线段21与数据线6相交且绝缘，第二线段22的部分区域作为栅极；栅线2与数据线6之间设置有栅绝缘层；
其中，第二线段22在衬底上的正投影沿垂直于第一方向OA上的尺寸大于第一线段21在衬底上的正投影沿垂直于第一方向OA上的尺寸。
在本申请的实施例中，一方面，通过减小与数据线6相交的第一线段21的宽度，可以降低数据线6与第一线段21之间产生的寄生电容的大小，尽可能降低寄生电容对阵列基板***号的负面影响，另一方面，通过加宽第二线段22的宽度，在薄膜晶体管的第一极4和第二极5制作过程中，即使发生工艺波动或对位不准，可以尽可能的确保不同晶体管中栅极与第一极4交叠的区域的面积一致，栅极与第二极5交叠的区域的面积一致，从而减小工艺波动或者对位不准时制备的薄膜晶体管间的性能差异，提高了阵列基板的质量。
在本申请的一些实施例中，参考图2所示，栅线2包括第一线段21、第二线段22和第三线段23，第一线段21与数据线6相交且绝缘，第二线段22作为栅极，第三线段23位于第二线段22远离第一线段21的一端；
其中，第二线段22在衬底上的正投影沿垂直于第一方向OA上的尺寸大于第三线段23在衬底上的正投影沿垂直于第一方向OA上的尺寸，且第三线段23在衬底上的正投影沿垂直于第一方向OA上的尺寸大于第一线段21在衬底上的正投影沿垂直于第一方向OA上的尺寸。
在本申请的实施例中，通过设置栅线包括宽度不同的三个线段，一方面，能够降低数据线6与栅线2相交处产生的寄生电容的大小，避免寄生电容对阵列基板的充电率的负面影响；另一方面，设置作为栅极的第二线段22的宽度最大，能够容许在制备工艺波动，第一极(第二极)与栅极的位置发生偏移时，第一极(第二极)与栅极交叠的区域的面积区域稳定，从而使得薄膜晶体管的电性仍保持稳定；又一方面，设置第三线段宽度小于第二线段宽度、且大于第一线段宽度，在保证电信号稳定传输的情况下，节省设计空间，增大阵列基板的开口率，从而提高由阵列基板制备的显示面板的透光率。
在本申请的一些实施例中，结合图12和图14所示，阵列基板还包括有源层7，有源层7位于栅极远离衬底1的一侧，有源层7在衬底1上的正投影的外轮廓位于栅极在衬底1上的正投影的外轮廓以内，第一极4的部分区域和第二极5的部分区域分别与有源层7直接接触；
其中，有源层7在衬底1上的正投影沿垂直于第一方向OA上的尺寸小于第一本体41在衬底1上的正投影沿垂直于第一方向OA上的尺寸，且有源层7在衬底1上的正投影沿垂直于第一方向OA上的尺寸小于第二本体51在衬底1上的正投影沿垂直于第一方向OA上的尺寸。
在示例性的实施例中，有源层7的材料可以包括晶体硅或金属氧化物。例如，晶体硅可以包括单晶硅、多晶硅和非晶硅，金属氧化物可以包括铟镓锌氧化物(IGZO)。
其中，图14是图13中的薄膜晶体管T沿B1B2方向的截面图。
在本申请的实施例中，通过设置有源层7的宽度小于第一本体41的长度、且小于第二本体51的长度，由于第一本体41到第二本体51之间的间距固定不变，在制备工艺发生波动的情况下，能够尽可能避免工艺波动对薄膜晶体管沟道的宽长比的影响，避免宽长比变化对薄膜晶体管电性的负面影响，从而避免造成不同子像素中薄膜晶体管的电性不一致。
其中，以图6为例，有源层7在衬底1上的正投影沿垂直于第一方向OA上的尺寸为薄膜晶体管的沟道宽度，第一本体41沿第一方向OA到第二本体51之间的尺寸为薄膜晶体管的沟道宽度。
需要说明的是，在本申请的实施例中，在第一方向OA上，第一本体41和第二本体51之间的最小距离与第一本体41和第二本体51之间的最大距离相等。
在示例性的实施例中，有源层7在衬底1上的正投影沿垂直于第一方向OA上的尺寸大于或等于5μm。
在示例性的实施例中，第一本体41在衬底1上的正投影沿垂直于第一方向OA上的尺寸与第二本体51在衬底1上的正投影沿垂直于第一方向OA上的尺寸相等。
示例性的，第一本体41在衬底1上的正投影沿垂直于第一方向OA上的尺寸大于或等于8μm。
在一些实施例中，栅极在衬底1上的正投影沿垂直于第一方向OA上的尺寸与第一本体41在衬底1上的正投影沿垂直于第一方向OA上的尺寸相等。
在一些实施例中，栅极在衬底1上的正投影沿垂直于第一方向OA上的尺寸大于第一本体41在衬底1上的正投影沿垂直于第一方向OA 上的尺寸。
示例性的，栅极在衬底1上的正投影沿垂直于第一方向OA上的尺寸与第一本体41在衬底1上的正投影沿垂直于第一方向OA上的尺寸之间的差值大于或等于4μm。
示例性的，栅极在衬底1上的正投影沿垂直于第一方向OA上的尺寸与有源层7在衬底1上的正投影沿垂直于第一方向OA上的尺寸之间的差值大于或等于5μm。
在本申请的一些实施例中，参考图13所示，阵列基板包括与栅极同层设置的第一存储电容线11、第二存储电容线12、第三存储电容线13和第四存储电容线14；
第一存储电容线11、第二存储电容线12和第三存储电容线13均位于相邻的两条数据线6之间，且均与数据线6的延伸方向相同；
第四存储电容线14分别与第一存储电容线11、第二存储电容线12和第三存储电容线13相交且连接，且第一存储电容线11、第二存储电容线12、第三存储电容线13和第四存储电容线14在衬底上的正投影分别与像素电极15在衬底上的正投影交叠。
在本申请的实施例中，各存储电容线与像素电极之间形成存储电容，以存储子像素在充电过程中获取的电量。
在本申请的一些实施例中，结合图13和图15所示，第二存储电容线12位于第一存储电容线11和第三存储电容线13之间，阵列基板还包括与数据线6同层设置的导电岛17，第二存储电容线12与第四存储电容线14的相交处在衬底1上的正投影与导电岛17在衬底1上的正投影交叠，且导电岛17与像素电极15通过过孔VIA2电连接。图15是图13沿C1C2方向的截面图。
需要说明的是，栅极和栅线位于同一导电层中，例如栅极层Gate中，薄膜晶体管的第一极、薄膜晶体管的第二极、数据线和导电岛位于同一导电层中，例如源漏金属层SD中，另外，在图13中，标记Active的膜层代表有源层，标记Pixel ITO的膜层代表像素电极。
其中，栅极层Gate和源漏金属层SD之间设置有栅绝缘层3，源漏金属层SD与像素电极Pixel ITO之间设置有层间介质层16。
在本申请的实施例中，通过设置导电岛17，在阵列基板中的某个子像素显示异常时，例如闪烁，可以通过激光镭射的方式将导电岛17 所在位置击穿，使得像素电极15与存储电极线12/14导通，从而使得该显示异常的子像素中的电路短路，使得不显示，从而避免了该异常的子像素对阵列基板制备的显示面板的整体显示效果的负面影响，提高了显示效果。
本申请的实施例提供了一种显示面板，包括如前文所述的阵列基板。
本申请的实施例中的显示面板包括的阵列基板的具体结构可以参考前文描述，这里不再说明。
在示例性的实施例中，该显示面板还可以包括彩膜基板，彩膜基板与阵列基板相对设置。
本申请的实施例提供的显示面板为液晶显示面板(LCD，Liquid Crystal Display)，另外，该显示面板可以是LCD显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
示例性的，上述显示面板是ADS(Advanced Super Dimension Switch，高级超维场转换技术)显示模式的液晶显示面板，其中，ADS是以宽视角技术为代表的核心技术统称。
在本申请的实施例提供的显示面板中，通过设置第一极4包括第一本体41和第一端部42，第二极5包括第二本体51和第二端部52，第一端部42和第二端部52位于栅极的同一侧，且第一端部42的投影和第二端部52的投影均与栅极的投影存在不交叠区，通过设置在第一方向OA上，第一端部42到第二端部52之间的平均距离大于第一本体41到第二本体51之间的平均距离，这样，可以在不改变第一本体41到第二本体51之间的间距，确保薄膜晶体管的宽长比不变的情况下，尽可能拉开第一端部42到第二端部52之间的距离，很大程度上降低了第一极4和第二极5在爬坡位置处发生短路的概率，提升了显示面板的制备良率和品质，提升了显示面板的显示效果。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种阵列基板，其中，包括：
    薄膜晶体管的栅极，沿第一方向延伸；
    所述薄膜晶体管的第一极，包括相连的第一本体和第一端部；
    所述薄膜晶体管的第二极，包括相连的第二本体和第二端部；
    所述第一本体和所述第二本体在所述阵列基板的衬底上的正投影分别位于所述栅极在所述衬底上的正投影以内，所述第一端部的至少部分区域和所述第二端部的至少部分区域在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影互不交叠，且所述第一端部在所述衬底上的正投影和所述第二端部在所述衬底上的正投影均位于所述栅极在所述衬底上的正投影的同一侧；
    其中，在所述第一方向上，所述第一端部到所述第二端部之间的平均距离大于所述第一本体到所述第二本体之间的平均距离。
  2. 根据权利要求1所述的阵列基板，其中，所述第一极还包括第三端部，所述第一本体连接所述第一端部和所述第三端部；所述第二极还包括第四端部，所述第二本体连接所述第二端部和所述第四端部；
    所述第三端部的至少部分区域和所述第四端部的至少部分区域在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影互不交叠；
    在所述第一方向上，所述第三端部到所述第四端部之间的平均距离大于所述第一本体到所述第二本体之间的平均距离。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括栅线、数据线、像素电极、第一走线和第二走线，所述数据线和所述栅线相交且绝缘，所述栅极和所述栅线电连接，所述像素电极位于相邻两条所述数据线和相邻两条所述栅线限定的位置处，所述第一极的所述第三端部通过所述第一走线与所述数据线电连接，所述第二极的所述第二端部通过所述第二走线与所述像素电极电连接；
    其中，沿所述第三端部与所述第一本体连接的部分指向所述第三端部与所述第一走线连接的部分的方向上，所述第三端部到所述数据线之间的最小距离逐渐减小；
    沿所述第二端部与所述第二本体连接的部分指向所述第二端部与所述第二走线连接的部分的方向上，所述第二端部到所述数据线之间的最小距离逐渐增大。
  4. 根据权利要求3所述的阵列基板，其中，沿所述第一端部与所述第一本体连接的部分指向所述第一端部远离所述第一本体的部分的方向上，所述第一端部到所述第二端部之间的最小距离逐渐增大，且所述第一端部到所述数据线之间的最小距离逐渐减小；
    沿所述第四端部与所述第二本体连接的部分指向所述第四端部远离所述第二本体的部分的方向上，所述第四端部到所述第三端部之间的最小距离逐渐增大，且所述第四端部到所述数据线之间的最小距离逐渐增大。
  5. 根据权利要求4所述的阵列基板，其中，所述第一端部、所述第二端部、所述第三端部和所述第四端部在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影互不交叠。
  6. 根据权利要求4所述的阵列基板，其中，所述第一端部、所述第二端部、所述第三端部和所述第四端部在所述衬底上的正投影分别与所述栅极在所述衬底上的正投影部分交叠。
  7. 根据权利要求5或6所述的阵列基板，其中，所述第一端部包括第一调节子部和第一保护子部，所述第一调节子部位于所述第一本体与所述第一保护子部之间；
    沿所述第一本体指向所述第一端部的方向上，所述第一调节子部到所述数据线之间的最小距离逐渐减小，所述第一保护子部到所述数据线之间的最小距离保持不变。
  8. 根据权利要求5或6所述的阵列基板，其中，所述第四端部包括第四调节子部和第二保护子部，所述第四调节子部位于所述第二本体与所述第二保护子部之间；
    沿所述第二本体指向所述第四端部的方向上，所述第四调节子部到所述数据线之间的最小距离逐渐增大，所述第二保护子部到所述数据线之间的最小距离保持不变。
  9. 根据权利要求6所述的阵列基板，其中，所述第一端部包括第一调节子部和第一保护子部，所述第一调节子部位于所述第一本体与所述第一保护子部之间；所述第二端部包括第二调节子部；所述第三端部包括第三调节子部；所述第四端部包括第四调节子部和第二保护子部，所述第四调节子部位于所述第二本体与所述第二保护子部之间；
    其中，所述第一调节子部的几何中心、所述第二调节子部的几何中 心、所述第三调节子部的几何中心和所述第四调节子部的几何中心在所述衬底上的正投影分别落入所述栅极在所述衬底上的正投影的轮廓上。
  10. 根据权利要求9所述的阵列基板，其中，所述第一保护子部在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离、所述第二保护子部在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离、所述第一走线在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离、以及所述第二走线在所述衬底上的正投影到所述栅极在所述衬底上的正投影之间的最小距离均大于或等于2μm。
  11. 根据权利要求9所述的阵列基板，其中，所述第一端部、所述第二端部、所述第三端部和所述第四端部在所述衬底上的正投影的形状均包括弧形、多边形、以及弧形和多边形组合形成的形状中的至少一种。
  12. 根据权利要求11所述的阵列基板，其中，所述第一调节子部、所述第二调节子部、所述第三调节子部和所述第四调节子部在所述衬底上的正投影形状均为平行四边形，且所述第一保护子部和所述第二保护子部在所述衬底上的正投影形状均矩形。
  13. 根据权利要求11所述的阵列基板，其中，所述第一调节子部在所述衬底上的正投影沿所述第一方向上的尺寸与所述第一保护子部在所述衬底上的正投影沿所述第一方向上的尺寸相等，且所述第四调节子部在所述衬底上的正投影沿所述第一方向上的尺寸与所述第二保护子部在所述衬底上的正投影沿所述第一方向上的尺寸相等。
  14. 根据权利要求3所述的阵列基板，其中，所述栅线包括第一线段和第二线段，所述第一线段与所述数据线相交且绝缘，所述第二线段的部分区域作为所述栅极；
    其中，所述第二线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸大于所述第一线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸。
  15. 根据权利要求3所述的阵列基板，其中，所述栅线包括第一线段、第二线段和第三线段，所述第一线段与所述数据线相交且绝缘，所述第二线段作为所述栅极，所述第三线段位于所述第二线段远离所述第一线段的一端；
    其中，所述第二线段在所述衬底上的正投影沿垂直于所述第一方向 上的尺寸大于所述第三线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸，且所述第三线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸大于所述第一线段在所述衬底上的正投影沿垂直于所述第一方向上的尺寸。
  16. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括有源层，所述有源层位于所述栅极远离所述衬底的一侧，所述有源层在所述衬底上的正投影的外轮廓位于所述栅极在所述衬底上的正投影的外轮廓以内，所述第一极的部分区域和所述第二极的部分区域分别与所述有源层直接接触；
    其中，所述有源层在所述衬底上的正投影沿垂直于所述第一方向上的尺寸小于所述第一本体在所述衬底上的正投影沿垂直于所述第一方向上的尺寸，且所述有源层在所述衬底上的正投影沿垂直于所述第一方向上的尺寸小于所述第二本体在所述衬底上的正投影沿垂直于所述第一方向上的尺寸。
  17. 根据权利要求3所述的阵列基板，其中，所述阵列基板包括与所述栅极同层设置的第一存储电容线、第二存储电容线、第三存储电容线和第四存储电容线；
    所述第一存储电容线、所述第二存储电容线和所述第三存储电容线均位于相邻的两条所述数据线之间，且均与所述数据线的延伸方向相同；
    所述第四存储电容线分别与所述第一存储电容线、所述第二存储电容线和所述第三存储电容线相交且连接，且所述第一存储电容线、所述第二存储电容线、所述第三存储电容线和所述第四存储电容线在所述衬底上的正投影分别与所述像素电极在所述衬底上的正投影交叠。
  18. 根据权利要求17所述的阵列基板，其中，所述第二存储电容线位于所述第一存储电容线和所述第三存储电容线之间，所述阵列基板还包括与所述数据线同层设置的导电岛，所述第二存储电容线与所述第四存储电容线的相交处在所述衬底上的正投影与所述导电岛在所述衬底上的正投影交叠，且所述导电岛与所述像素电极电连接。
  19. 一种显示面板，其中，包括如权利要求1-18中任一项所述的阵列基板。
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