WO2023185311A1 - 一种基于fpga芯片的电缆绝缘状态检测***及方法 - Google Patents

一种基于fpga芯片的电缆绝缘状态检测***及方法 Download PDF

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WO2023185311A1
WO2023185311A1 PCT/CN2023/077061 CN2023077061W WO2023185311A1 WO 2023185311 A1 WO2023185311 A1 WO 2023185311A1 CN 2023077061 W CN2023077061 W CN 2023077061W WO 2023185311 A1 WO2023185311 A1 WO 2023185311A1
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module
signal
cable
synchronization
data
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PCT/CN2023/077061
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English (en)
French (fr)
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张大兴
黄泽荣
尹星光
李贤靓
蔡冰子
袁昊宇
田明明
李泽基
王掬涵
袁英平
温振兴
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广东电网有限责任公司惠州供电局
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Publication of WO2023185311A1 publication Critical patent/WO2023185311A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
    • G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
    • G01R31/1272—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of cable, line or wire insulation, e.g. using partial discharge measurements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • G01R31/14—Circuits therefor, e.g. for generating test voltages, sensing circuits

Definitions

  • This application relates to the technical field of power secondary equipment, for example, to a cable insulation status detection system and method based on an FPGA chip.
  • cable fault detection methods mainly include offline ranging, live detection and online monitoring.
  • the offline distance measurement method involves a power outage after a fault occurs and the power cable is untied, and the fault distance is tested through relevant equipment. This method has a long power outage and affects social and economic production.
  • the offline detection method is to use manpower and material resources to find the cause and locate the fault point after the fault occurs, which is very inefficient.
  • Live detection includes DC component method, dielectric constant method, distributed optical fiber temperature measurement, partial discharge live detection, etc. These methods are only feasible in the ideal environment of the laboratory, but they are difficult to provide ideal results when used in the field.
  • This application proposes a cable insulation status detection system and method based on a Field-Programmable Gate Array (FPGA) chip.
  • FPGA Field-Programmable Gate Array
  • This application proposes a cable insulation status detection system based on an FPGA chip, which includes: a detection board and a coupler; the detection board includes an FPGA chip, and a first circuit and a second circuit connected to the FPGA chip;
  • the FPGA chip includes a logic control module and a detection signal generation module connected in series with the first circuit; and a synchronization module, a noise reduction module, a signal processing module and a state evaluation module connected in series with the second circuit.
  • the first circuit sends the detection signal generated by the detection signal generation module to the coupler; the coupler injects the detection signal into the cable under test connected to the coupler, and the cable under test
  • the reflected signal is extracted and sent to the status evaluation module through the second circuit for evaluation of the status of the cable to be tested.
  • This application also provides a cable insulation status detection method based on FPGA chip, which includes the following steps:
  • the FPGA chip generates a first detection signal in the digital domain and transmits it to the first circuit
  • a digital to analog converter converts the first detection signal into a first analog signal, which is amplified by the sending circuit and sent to the coupler, and the coupler injects the first detection signal into the In the cable under test connected to the coupler;
  • the coupler extracts the reflected signal from the cable under test and transmits it to the second circuit
  • an Analog to Digital Converter converts the first analog signal into a second detection signal in the digital domain and sends it to the FPGA chip;
  • the FPGA chip evaluates the status of the cable under test based on the reflected signal
  • the status evaluation results of the cable to be tested are displayed on the LCD screen, and the control switch is set to 0 to end the cable insulation status monitoring program.
  • Figure 1 is a schematic diagram of a cable insulation status detection system based on FPGA chip.
  • Figure 2 is the workflow of the cable insulation status detection system described in this application.
  • FIG. 3 is a structural diagram of the internal logic circuit of the FPGA described in this application.
  • Figure 4 is a diagram of the internal logical structure of the synchronization module described in this application.
  • Figure 5 is a diagram of the internal logic structure of the noise reduction module described in this application.
  • Figure 6 is a diagram of the internal logic structure of the signal processing module described in this application.
  • Figure 7 is a workflow diagram of the status assessment module described in this application.
  • Figure 8 is a work flow chart of the detection signal generation module described in this application.
  • this application proposes a cable insulation status detection system based on FPGA chips, including: detection board and coupler; wherein, the detection board mainly includes: control switch, FPGA chip, first circuit , the second circuit and LCD screen.
  • both the first circuit and the second circuit are connected to the FPGA chip.
  • the FPGA chip includes a logic control module and a detection signal generation module connected in series with the first circuit; and a synchronization module, a noise reduction module, a signal processing module and a state evaluation module, and a ROM module connected in series with the second circuit.
  • the first circuit sends the detection signal generated by the detection signal generation module to the coupler; the coupler injects the detection signal into the cable to be tested connected to it, and injects the reflected signal in the cable to be tested.
  • the extracted information is sent to the status evaluation module through the second circuit for evaluation of the status of the cable to be tested.
  • the first circuit at least includes a DAC digital-to-analog converter and a sending circuit; the DAC digital-to-analog converter converts the digital domain signal from the detection signal generation module into an analog domain signal, which is amplified by the sending circuit sent to the coupler.
  • the second circuit at least includes a receiving circuit and an ADC digital-to-analog converter; after the receiving circuit amplifies the acquired reflected signal, the ADC digital-to-analog converter converts the analog domain signal into a digital domain signal and sends it to the synchronization module .
  • the workflow of the cable insulation status detection system based on FPGA chips described in this application mainly includes the following steps:
  • Step 1 Turn on the control switch and start the cable insulation status detection process
  • Step 2 The FPGA chip generates a detection signal in the digital domain
  • Step 3 The DAC digital-to-analog converter converts the digital domain detection signal into an analog signal
  • Step 4 The amplifier circuit amplifies the analog signal
  • Step 5 The coupler injects the amplified analog signal into the cable under test
  • Step 6 The coupler extracts the analog signal in the cable under test
  • Step 7 The receiving circuit filters and amplifies the extracted analog signal
  • Step 8 The ADC digital-to-analog converter converts the analog signal into a digital signal
  • Step 9 The FPGA chip performs data processing on the collected reflection signals, determines the cable insulation status based on the processing results, and transmits the judgment results to the LCD screen;
  • Step 10 The LCD screen displays the test results
  • Step 11 The detection is completed.
  • Figure 3 the structure diagram of the internal logic circuit of FPGA is shown in Figure 3, which mainly includes logic control module, detection signal generation module, ROM module, synchronization module, noise reduction module, signal processing module and status evaluation module.
  • Logic control module responsible for the timing control, external interface and other functions of the entire FPGA internal logic.
  • the logic control module is connected to the external control switch and monitors the control switch status. Once the control switch is detected to be open, the cable insulation status detection process is started, a pulse signal is generated, and the detection signal generation module is notified to start working.
  • the logic control module is also connected to an external LCD screen to output the cable insulation status detection results output by the status evaluation module to the LCD screen for display.
  • the training sequence is read from the ROM module, and the number of readings is M.
  • the read training sequence is used as a detection signal of the cable insulation status and is injected into the cable to be tested connected to it through the first circuit.
  • the ROM module stores a training sequence with a length of N and a bit width of B, where N ⁇ 128 and B ⁇ 10 bits.
  • the ROM module provides training sequences for the detection signal generation module, synchronization module, and signal processing module.
  • the synchronization module performs synchronization data processing after receiving the reflected signal from the second circuit.
  • the internal logic structure of the synchronization module is shown in Figure 4. It is mainly divided into a coarse synchronization related calculation module, a fine synchronization related calculation module, and a first comparison module. It consists of a second comparator, a third comparator, a selector, a data delay and a data interception module.
  • the coarse synchronization correlation calculation module calculates the reflected signal energy and autocorrelation value
  • the fine synchronization correlation calculation module calculates the cross-correlation value between the reflected signal and the training sequence in the ROM module.
  • the first comparator compares the two output signals of the coarse synchronization correlation calculation module. If the correlation value is greater than the input signal energy, it indicates coarse synchronization locking and generates an indication signal 1;
  • the second comparator compares the cross-correlation value calculated by the fine synchronization correlation calculation module with the preset threshold value. If it is greater than the preset threshold value, it indicates that the fine synchronization is locked, and an indication signal 2 is generated at the same time.
  • the third comparator determines the positivity of the output of the selector module. If it is negative, it indicates timing synchronization locking and generates an indication signal 3; if it is positive, no signal is output.
  • the data delay module delays the input signal data.
  • the delay time is the data processing time of the synchronization module.
  • the delayed data is the input signal of the data interception module.
  • the data interception module After detecting the indication signal 3, the data interception module starts to output a signal.
  • the signal length is N*M, where N is the length of the training sequence stored in the ROM, and M is the number of times the detection signal generation module reads the ROM data.
  • the main purpose of the noise reduction module is to increase the useful signal energy in the collected signal and improve the signal-to-noise ratio.
  • Its internal logic structure is shown in Figure 5. It mainly includes an adder and a RAM. The adder completes the addition operation and the RAM storage depth is N. The width is B.
  • the internal logic structure of the signal processing module is shown in Figure 6, including two FFT modules, a divider, an amplitude calculation module, a peak search module and a data output module.
  • the signal processing module there are two inputs to the signal processing module, one of which is the output signal sequence of the noise reduction module, length N, which is sent to the FFT1 module to convert the time domain signal into a frequency domain signal; the other is the output signal sequence of the ROM module, length Also N, it is sent to the FFT2 module to convert the time domain signal into a frequency domain signal.
  • the length of the output sequence is N.
  • the element with the second largest peak value is searched and its serial number idx is recorded. Based on this serial number, the data output module outputs data e 3 (idx) to the status evaluation module for cable insulation status judgment.
  • the status evaluation module determines the insulation status of the cable to be tested based on the output of the signal processing module. As shown in Figure 7, the status evaluation module determines whether there is insulation aging based on the output data e 3 (idx). If there is insulation aging in the cable, then Determine the type of insulation aging and the degree of insulation aging. Otherwise, if there is no insulation aging in the cable, end the status assessment.
  • the status evaluation module is connected to a liquid crystal screen to present the status evaluation results of the cable under test.
  • This application also provides a cable insulation status detection method based on FPGA chip, which includes the following steps:
  • the DAC digital-to-analog converter converts the digital domain detection signal into an analog signal, which is amplified by the sending circuit Then it is sent to the coupler, and the coupler injects the detection signal into the cable to be tested connected to it;
  • the ADC digital-to-analog converter converts the analog signal into a digital domain detection signal and sends it to the FPGA chip;
  • the FPGA chip evaluates the status of the cable under test based on the reflected signal
  • the FPGA chip generates a detection signal, including the following steps:
  • the detection signal generation module starts to read the training sequence from the ROM module
  • the FPGA chip evaluates the status of the cable under test based on the reflected signal, including the following steps:
  • the synchronization module performs logical operations on the reflected signal, and after processing by the noise reduction module, sends it to the FFT1 module for signal processing; at the same time, the FFT2 module obtains the output signal sequence of the ROM module and performs signal processing;
  • e 3 (i) is the i-th element in the divider output sequence
  • e 1 (i) is the i-th element in the FFT1 module output sequence
  • e 2 (i) is the i-th element in the FFT 2 module output sequence.
  • Element; N is the length of the output sequence;
  • the output of the divider is a complex signal with real and imaginary parts, it cannot be directly compared, so the amplitude needs to be calculated first.
  • S163 Calculate the amplitude, search for the element with the second largest peak value and record its serial number idx, and output the data e 3 (idx) to the status evaluation module; among them, the element with the largest amplitude corresponds to the reflection at the injection cable of the detection board signal; the element with the second largest amplitude corresponds to the reflected signal of the injected detection signal at the insulation aging point. So search for the element with the second largest amplitude.
  • the state assessment module determines whether there is insulation aging based on the output data e 3 (idx). The formula is:
  • H 1 represents the cable insulation status
  • T represents the threshold value
  • represents the amplitude of x
  • H 2 represents the cable insulation aging type; when e 3 (idx) is greater than 0, it is high resistance insulation aging; if it is less than 0, it means low resistance insulation aging; H 3 is the quantized insulation aging degree, expressed in Q bits; THR is the quantization reference; floor(x) represents the largest integer less than x.
  • the synchronization module performs logical operations on the reflected signal, including:
  • the coarse synchronization related calculation module and the fine synchronization related calculation module perform data processing after receiving the reflected signal sent by the ADC digital-to-analog converter.
  • the data delay module delays the input signal data.
  • the delay length is the coarse synchronization related calculation module and the fine synchronization related calculation module. Calculate the data processing time of the module; the delayed data is used as the input signal of the data interception module;
  • the coarse synchronization correlation calculation module calculates the reflected signal energy and autocorrelation value, and determines whether the autocorrelation value is greater than the reflected signal energy through the first comparator. If it is greater, the coarse synchronization is locked, and an indication signal 1 is generated at the same time; if Less than, coarse synchronization is not locked.
  • the fine synchronization correlation calculation module calculates the cross-correlation value of the reflected signal and the training sequence in the ROM module, and determines whether the cross-correlation value is greater than the preset threshold value through the second comparator. If it is greater, the fine synchronization is locked, and at the same time Generate an indication signal 2; if it is less than 2, the fine synchronization is not locked.
  • the selector module After the selector module obtains the indication signal 2, it selects the autocorrelation value of the coarse synchronization correlation calculation module as the input value of the third comparator, and determines the positivity or negativity of the input value through the third comparator. If it is negative, Then the timing is synchronized and locked, and an indication signal 3 is generated at the same time; if it is positive, no signal is output.
  • the data interception module After detecting the indication signal 3, the data interception module begins to output signals to the noise reduction module; wherein, the input data sequence of the noise reduction module is assumed to be:
  • A ⁇ a 11 , a 12 ,..., a 1N , a 21 , a 22 ,..., a 2N ,..., a M1 , a M2 ,...a MN ⁇ ;
  • the formula is:
  • c i is the i-th element in the output data sequence C
  • a ij is the (i-1)*N+j-th element in the input data sequence A
  • the coarse synchronization correlation calculation module is used to calculate the input signal energy and autocorrelation value, and is connected to the first comparator; the fine synchronization correlation calculation module is used to calculate the cross-correlation value of the input signal and the training sequence in the ROM module, and Connected to the second comparator; both the first comparator and the second comparator are connected to a selector, and the selector is connected to the third comparator; the data delay module delays the input signal data, and the delay time is The data processing duration of the synchronization module and the delayed data are used as input signals of the data interception module; the data interception module begins to output signals to the noise reduction module in response to the instruction signal sent by the third comparator.
  • the cable insulation status detection system and method proposed in this application can not only determine whether there is insulation status aging phenomenon in substation cables, but also provide the type and degree of aging points, which is conducive to a comprehensive and comprehensive assessment of the cable insulation status. Provide a more reliable and accurate basis for the monitoring and maintenance of station cables.
  • the cable insulation status detection system and method proposed in this application are based on FPGA chips, which can realize the rapid upgrade of the acquisition signal processing algorithm and cable status identification algorithm. It has the characteristics of simple principle, economical and practical, and convenient application.
  • the main core of the cable insulation status detection system proposed in this application is based on the FPGA chip. Based on the FPGA chip, a comprehensive azimuthal assessment of the cable insulation status can be completed, and it is convenient for subsequent algorithm iterative upgrades, and can be aligned without adding additional hardware equipment. Online monitoring of cables in low-voltage distribution networks has the characteristics of simple principle, economical and practical, and convenient application.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Testing Relating To Insulation (AREA)

Abstract

一种基于FPGA芯片的电缆绝缘状态检测***及方法，通过控制开关，开启电缆绝缘状态监测程序，由FPGA芯片产生数字域的检测信号传入第一电路，经发送电路放大后送至耦合器，由耦合器将检测信号注入与其相连接的待测电缆中，再通过耦合器将待测电缆中的反射信号提取出来，通过FPGA芯片根据反射信号进行待测电缆状态评估。

Description

一种基于FPGA芯片的电缆绝缘状态检测***及方法
本申请要求在2022年3月28日提交中国专利局、申请号为202210308342.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及电力二次设备技术领域，例如是涉及一种基于FPGA芯片的电缆绝缘状态检测***及方法。
背景技术
近年来，电网公司发生多起因变电站内电力电缆绝缘降低造成的短路故障，由于变电站内交直流电缆一起敷设电缆沟内，当一条电缆出现短路故障时，短路电流将整条沟内电缆均会烧毁，造成设备误动与拒动。由于变电站内电缆传输距离远、支线多、环境和气候条件恶劣、设备故障等原因，难以通过人工红外测温、外观检查等手段来发现缺陷。因此，实现变电站内电力电缆的绝缘在线监测，对维护电网的安全稳定，意义巨大。
常见的电缆绝缘缺陷和故障，包括接头处工艺或材料不良、电缆老化以及外力导致的电缆绝缘受损等情况。目前电缆故障检测方法主要有离线测距、带电检测及在线监测等。离线测距方式在故障发生后停电并解开电力电缆，通过相关设备测试故障距离，该方法停电时间较长，影响社会经济生产。此外，离线检测的方法是在故障发生之后，动用人力物力查找原因，定位故障点，效率非常低。带电检测包括直流分量法、介电常数法、分布式光纤测温以及局部放电带电检测等，这些方法仅在试验室的理想环境里可行，但在现场实际运用时难以提供理想效果。
发明内容
本申请提出了一种基于现场可编程门阵列(Field-Programmable Gate Array，FPGA)芯片的电缆绝缘状态检测***及方法，通过在待测电缆一端加装上一个检测板卡和一个耦合器即可进行实时检测，本申请主要通过检测板卡上的FPGA芯片产生、注入、采集、分析检测信号，利用信号处理算法结果识别待 测电缆绝缘老化状态，判断绝缘老化点类型以及老化程度，实现变电站站用电缆绝缘状态在线监测。
本申请提出了一种基于FPGA芯片的电缆绝缘状态检测***，包括：检测板卡和耦合器；所述检测板卡包括FPGA芯片，及与所述FPGA芯片连接的第一电路和第二电路；
所述FPGA芯片包括与所述第一电路串联的逻辑控制模块和检测信号生成模块；及与所述第二电路串联的同步模块，降噪模块，信号处理模块及状态评估模块。
所述第一电路将所述检测信号生成模块产生的检测信号发送至所述耦合器；由所述耦合器将检测信号注入与所述耦合器相连接的待测电缆中，并将待测电缆中的反射信号提取出来经所述第二电路送入所述状态评估模块进行待测电缆状态评估。
本申请还提供一种基于FPGA芯片的电缆绝缘状态检测方法，包括以下步骤：
控制开关置1，开启电缆绝缘状态监测程序；
FPGA芯片产生数字域的第一检测信号传入第一电路；
数模转换器(Digital to Analog Converter，DAC)将所述第一检测信号转换成第一模拟信号，经发送电路放大后送至耦合器，由所述耦合器将所述第一检测信号注入与所述耦合器相连接的待测电缆中；
耦合器将待测电缆中的反射信号提取出来传入第二电路；
接收电路将获取的反射信号进行滤波和放大处理后，由数模转换器(Analog to Digital Converter，ADC)将所述第一模拟信号转换成数字域的第二检测信号，并发送至FPGA芯片；
FPGA芯片根据所述反射信号进行待测电缆状态评估；
在液晶屏端呈现待测电缆状态评估结果，控制开关置0，结束电缆绝缘状态监测程序。
附图说明
图1为种基于FPGA芯片的电缆绝缘状态检测***示意图。
图2为本申请所述的电缆绝缘状态检测***工作流程。
图3为本申请所述的FPGA内部逻辑电路结构图。
图4为本申请所述同步模块内部逻辑结构图。
图5为本申请所述降噪模块内部逻辑结构图。
图6为本申请所述信号处理模块内部逻辑结构图。
图7为本申请所述状态评估模块工作流程图。
图8为本申请所述检测信号生成模块工作流程图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，本申请提出了一种基于FPGA芯片的电缆绝缘状态检测***，包括：检测板卡和耦合器；其中，所述检测板卡主要包括：控制开关，FPGA芯片，第一电路，第二电路及液晶屏。
例如，所述第一电路和第二电路均与FPGA芯片连接。
所述FPGA芯片包括与所述第一电路串联的逻辑控制模块和检测信号生成模块；及与所述第二电路串联的同步模块，降噪模块，信号处理模块及状态评估模块，以及ROM模块。
所述第一电路将所述检测信号生成模块产生的检测信号发送至所述耦合器；由所述耦合器将检测信号注入与其相连接的待测电缆中，并将待测电缆中的反射信号提取出来经所述第二电路送入所述状态评估模块进行待测电缆状态评估。
其中，所述第一电路至少包括DAC数模转换器和发送电路；所述DAC数模转换器将来自所述检测信号生成模块的数字域信号转换成模拟域信号，经所述发送电路放大后发送至所述耦合器。
所述第二电路至少包括接收电路和ADC数模转换器；所述接收电路将获取的反射信号放大后，由ADC数模转换器将模拟域信号转换成数字域信号并发送至所述同步模块。
如图2所示，本申请所述的基于FPGA芯片的电缆绝缘状态检测***，工作流程，主要包括以下几个步骤：
步骤1：控制开关打开，启动电缆绝缘状态检测流程；
步骤2：FPGA芯片产生数字域的检测信号；
步骤3：DAC数模转换器将数字域检测信号转换成模拟信号；
步骤4：放大电路放大模拟信号；
步骤5：耦合器将放大后的模拟信号注入到待测电缆中；
步骤6：耦合器提取待测电缆中的模拟信号；
步骤7：接收电路对提取的模拟信号进行滤波和放大处理；
步骤8：ADC数模转换器将模拟信号转换成数字信号；
步骤9：FPGA芯片对采集的反射信号进行数据处理，根据处理结果判断电缆绝缘状态，并将判断结果输送给液晶屏；
步骤10：液晶屏显示检测结果；
步骤11：检测结束。
其中，FPGA内部逻辑电路的结构图如图3所示，主要包括逻辑控制模块、检测信号生成模块、ROM模块、同步模块、降噪模块、信号处理模块及状态评估等模块。
逻辑控制模块：负责整个FPGA内部逻辑的时序控制、对外接口等功能。逻辑控制模块与外部的控制开关连接，监测控制开关状态，一旦监测到控制开关处于打开状态，则启动电缆绝缘状态检测流程，产生脉冲信号，通知检测信号生成模块开始工作。例如，逻辑控制模块还与外部的液晶屏连接，将状态评估模块输出的电缆绝缘状态检测结果输出给液晶屏进行展示。
所述检测信号生成模块启动后，从所述ROM模块中读取训练序列，读取次数为M。读取到的训练序列作为电缆绝缘状态的检测信号，经第一电路注入与其相连接的待测电缆中。
其中，ROM模块存储了长度为N，位宽为B的训练序列，其中N≥128，B≥10比特。ROM模块为检测信号生成模块、同步模块、信号处理模块提供训练序列。
同步模块在接收到来自第二电路的反射信号后进行同步数据处理，其中，同步模块的内部逻辑结构如图4所示，主要分为粗同步相关计算模块、细同步相关计算模块、第一比较器、第二比较器、第三比较器、选择器、数据延迟和数据截取模块组成。其中粗同步相关计算模块进行反射信号能量和自相关值计算，细同步相关计算模块进行反射信号与ROM模块中训练序列的互相关值计算。
第一比较器比较粗同步相关计算模块的两个输出信号，若相关值大于输入信号能量，则表示粗同步锁定，同时产生一个指示信号1；
第二比较器将细同步相关计算模块计算的互相关值与预设门限值进行比较，若大于，表示细同步锁定，同时产生一个指示信号2。
第三比较器判断选择器模块的输出的正负性，若为负，则表示定时同步锁定，同时产生一个指示信号3；若为正，则不输出信号。
数据延迟模块对输入信号数据延迟，延迟时长为同步模块的数据处理时长，延迟后的数据最为数据截取模块的输入信号。数据截取模块在检测到指示信号3后，开始输出信号，信号长度为N*M，其中N为ROM中存储的训练序列长度，M为检测信号生成模块读取ROM数据的次数。
降噪模块主要为了增加采集信号中有用信号能量，提高信噪比，其内部逻辑结构如图5所示，主要包括一个加法器和一个RAM，其中加法器完成加法运算，RAM存储深度为N，宽度为B。
信号处理模块内部逻辑结构如图6所示，包括两个FFT模块、除法器、幅值计算模块、峰值搜寻模块和数据输出模块。其中，信号处理模块的两个输入，其中一个为降噪模块的输出信号序列，长度N，送入FFT1模块，将时域信号转换成频域信号；另一个为ROM模块的输出信号序列，长度也为N，送入FFT2模块，将时域信号转换成频域信号。经除法器模块完成除法运算，输出序列长度为N，计算其幅值后，搜寻峰值第二大的元素，并记录其序号idx。数据输出模块根据这个序号，输出数据e3(idx)至状态评估模块，用于电缆绝缘状态判断。
状态评估模块根据信号处理模块的输出，判断待测电缆绝缘状态，如图7所示，状态评估模块根据所述输出数据e3(idx)，判断是否存在绝缘老化，若电缆存在绝缘老化，则判断绝缘老化类型，及判断绝缘老化程度，否则，若电缆不存在绝缘老化，结束状态评估。
例如，所述状态评估模块连接液晶屏用于呈现待测电缆状态评估结果。
本申请还提供一种基于FPGA芯片的电缆绝缘状态检测方法，包括以下步骤：
S11：控制开关置1，开启电缆绝缘状态监测程序；
S12：FPGA芯片产生数字域的检测信号传入第一电路；
S13：DAC数模转换器将数字域检测信号转换成模拟信号，经发送电路放 大后送至耦合器，由所述耦合器将检测信号注入与其相连接的待测电缆中；
S14：耦合器将待测电缆中的反射信号提取出来传入第二电路；
S15：接收电路将获取的反射信号进行滤波和放大处理后，由ADC数模转换器将模拟信号转换成数字域检测信号，并发送至FPGA芯片；
S16：FPGA芯片根据所述反射信号进行待测电缆状态评估；
S17：在液晶屏端呈现待测电缆状态评估结果，控制开关置0，结束电缆绝缘状态监测程序。
其中，如图8所示，所述S12，FPGA芯片生成检测信号，包括以下步骤：
S121：逻辑控制模块接收到来自控制开关的启动信号时，则开启电缆绝缘状态检测程序，并产生脉冲信号通知所述检测信号生成模块开始运行；所述检测信号生成模块检测到脉冲信号，转S122；否则，直到持续检测脉冲信号；
S122：初始化m＝1，m为读取次数；
S123：所述检测信号生成模块开始从ROM模块中读取训练序列；
S124：判断m＝M，若是，则结束；否则，m＝m+1，转S123；
其中，所述S16，FPGA芯片根据所述反射信号进行待测电缆状态评估，包括以下步骤：
S161：同步模块对所述反射信号进行逻辑运算，并经降噪模块处理后发送至FFT1模块进行信号处理；同时，FFT2模块获取ROM模块的输出信号序列并进行信号处理；
S162：除法器对所述FFT1模块和FFT2模块的输出结果进行处理，计算公式为：
其中，e3(i)是除法器输出序列中的第i个元素，e1(i)是FFT1模块输出序列的第i个元素，e2(i)是FFT2模块输出序列的第i个元素；N为输出序列长度；
由于除法器的输出是个复数信号，有实部和虚部，不能直接比较大小，所以需要首先计算器幅值。
S163：进行幅值计算，并搜寻峰值第二大的元素并记录其序号idx，输出数据e3(idx)至状态评估模块；其中，幅值最大的元素对应着检测板卡注入电缆处的反射信号；幅值第二大的元素对应着注入的检测信号在绝缘老化点的反射信号。所以要搜寻幅值第二大的元素。
S164：状态评估模块根据所述输出数据e3(idx)，判断是否存在绝缘老化，公式为：
若电缆存在绝缘老化，则判断绝缘老化类型，公式为：
判断绝缘老化程度，公式为：
否则，若电缆不存在绝缘老化，结束状态评估；
其中，H1表示电缆绝缘状态，T表示门限值，|x|表示x的幅值；H2表示电缆绝缘老化类型；当e3(idx)大于0，则为高阻绝缘老化；若小于0，则为低阻绝缘老化；H3是经过量化后的绝缘老化程度，用Q比特表示；THR是量化基准；floor(x)表示小于x的最大整数。
其中，所述同步模块对所述反射信号进行逻辑运算，包括：
粗同步相关计算模块和细同步相关计算模块接收到ADC数模转换器发送的反射信号后进行数据处理，同时，数据延迟模块对输入信号数据延迟，延迟时长为粗同步相关计算模块和细同步相关计算模块数据处理时长；延迟后的数据作为数据截取模块的输入信号；
其中：
所述粗同步相关计算模块：进行反射信号能量和自相关值计算，并通过第一比较器判断自相关值是否大于反射信号能量，若大于，则粗同步锁定，同时产生一个指示信号1；若小于，则粗同步未锁定。
所述细同步相关计算模块：进行反射信号与ROM模块中训练序列的互相关值计算，并通过第二比较器判断互相关值是否大于预设门限值，若大于，则细同步锁定，同时产生一个指示信号2；若小于，则细同步未锁定。
选择器模块获取到指示信号2后，选择将所述粗同步相关计算模块的自相关值作为第三比较器的输入值，经第三比较器判断该输入值的正负性，若为负，则定时同步锁定，同时产生一个指示信号3；若为正，则不输出信号。
所述数据截取模块在检测到指示信号3后，则开始输出信号至降噪模块；其中，设降噪模块的输入数据序列为：
A＝{a11，a12，...，a1N，a21，a22，...，a2N，...，aM1，aM2，...aMN}；
输出数据序列为C＝{c1，c2，...，cN}，则通过降噪模块处理，公式为：
其中ci是输出数据序列C中的第i个元素，aij为输入数据序列A中的第(i-1)*N+j个元素；
所述粗同步相关计算模块用于计算输入信号能量和自相关值，并与第一比较器连接；所述细同步相关计算模块用于计算输入信号与ROM模块中训练序列的互相关值，并与第二比较器连接；所述第一比较器与所述第二比较器均接入选择器，所述选择器连接第三比较器；所述数据延迟模块对输入信号数据延迟，延迟时长为所述同步模块的数据处理时长，延迟后的数据作为数据截取模块的输入信号；所述数据截取模块响应于所述第三比较器发送的指示信号开始输出信号至降噪模块。
本申请提出的电缆绝缘状态检测***及方法，不仅可以判断变电站站用电缆是否存在绝缘状态老化现象，还能给出老化点的类型及老化程度，有利于对电缆绝缘状态进行全面综合的评估，为站用电缆的监测和维护提供更加可靠、准确的依据。
此外，本申请提出的电缆绝缘状态检测***及方法基于FPGA芯片，可以实现采集信号处理算法、电缆状态识别算法的快速升级，具有原理简单、经济实用、应用方便的特点。
本申请所提出电缆绝缘状态检测***主要核心在于基于FPGA芯片，通过基于FPGA芯片即可完成对电缆绝缘状态的全面方位评估，且便于后续算法迭代升级，无需增加额外的硬件设备，即可对中低压配电网中的电缆进行在线监测，具有原理简单、经济实用、应用方便的特点。

Claims (10)

  1. 一种基于现场可编程门阵列FPGA芯片的电缆绝缘状态检测***，包括：检测板卡和耦合器；所述检测板卡包括FPGA芯片，及与所述FPGA芯片连接的第一电路和第二电路；
    所述FPGA芯片包括与所述第一电路串联的逻辑控制模块和检测信号生成模块；及与所述第二电路串联的同步模块，降噪模块，信号处理模块及状态评估模块；
    所述第一电路将所述检测信号生成模块产生的检测信号发送至所述耦合器；由所述耦合器将检测信号注入与所述耦合器相连接的待测电缆中，并将所述待测电缆中的反射信号提取出来经所述第二电路送入所述状态评估模块进行待测电缆状态评估。
  2. 根据权利要求1所述的***，其中，
    所述第一电路包括数模转换器DAC和发送电路；所述DAC将来自所述检测信号生成模块的数字域信号转换成模拟域信号，经所述发送电路放大后发送至所述耦合器；
    所述第二电路包括接收电路和数模转换器ADC；所述接收电路将获取的反射信号放大后，由所述ADC将模拟域信号转换成数字域信号并发送至所述同步模块。
  3. 根据权利要求2所述的***，其中，所述FPGA芯片还包括：只读内存ROM模块，设置为存储长度为N，位宽为B的训练序列，其中N≥128，B≥10比特；所述ROM模块设置为为所述检测信号生成模块，所述同步模块，和所述信号处理模块提供训练序列。
  4. 根据权利要求3所述的***，其中，所述逻辑控制模块通过对外接口连接控制开关，所述逻辑控制模块设置为响应于确定所述控制开关处于打开状态，启动电缆绝缘状态检测程序，产生脉冲信号通知所述检测信号生成模块开始运行；
    所述检测信号生成模块设置为从所述ROM模块中读取训练序列，读取次数为M。
  5. 根据权利要求4所述的***，其中，所述同步模块包括：与所述ADC并列连接的第一同步相关计算模块，第二同步相关计算模块和数据延迟模块；所述第一同步相关计算模块设置为进行反射信号能量和自相关值计算，并与第一比较器连接；所述第二同步相关计算模块设置为进行反射信号与所述ROM 模块中训练序列的互相关值计算，并与第二比较器连接；所述第一比较器与所述第二比较器分别接入选择器，所述选择器连接第三比较器；所述数据延迟模块设置为对输入信号数据延迟，并将延迟后的数据作为数据截取模块的输入信号，延迟时长为所述同步模块的数据处理时长；所述数据截取模块设置为响应于所述第三比较器发送的指示信号，输出信号至降噪模块。
  6. 根据权利要求5所述的***，其中，
    所述降噪模块包括一个加法器和一个随机存储器RAM；其中所述加法器设置为完成加法运算后输出至所述信号处理模块；
    所述信号处理模块包括：FFT1模块，FFT2模块，除法器，幅值计算模块，峰值搜寻模块和数据输出模块，所述FFT1模块设置为接收所述加法器信号并进行信号处理；所述FFT2模块设置为获取ROM模块的输出信号序列并进行信号处理；所述除法器设置为对所述FFT1模块和FFT2模块的输出结果进行处理后，转入所述幅值计算模块和所述峰值搜寻模块进行处理，处理结果由所述数据输出模块发送至所述状态评估模块；
    所述状态评估模块连接液晶屏，设置为呈现待测电缆状态评估结果。
  7. 一种基于现场可编程门阵列FPGA芯片的电缆绝缘状态检测方法，包括：
    控制开关置1，开启电缆绝缘状态监测程序；
    所述FPGA芯片产生数字域的第一检测信号传入第一电路；
    数模转换器DAC将所述第一检测信号转换成第一模拟信号，经发送电路放大后送至耦合器，由所述耦合器将所述第一检测信号注入与所述耦合器相连接的待测电缆中；
    所述耦合器将所述待测电缆中的反射信号提取出来传入第二电路；
    接收电路将获取的反射信号进行滤波和放大处理后，由数模转换器ADC将所述第一模拟信号转换成数字域的第二检测信号，并发送至FPGA芯片；
    所述FPGA芯片根据所述反射信号进行待测电缆状态评估；
    在液晶屏端呈现待测电缆状态评估结果，控制开关置0，结束电缆绝缘状态监测程序。
  8. 根据权利要求7所述的方法，其中，所述FPGA芯片产生数字域的第一检测信号传入第一电路，包括：
    响应于确定逻辑控制模块接收到来自控制开关的启动信号，开启电缆绝缘 状态检测程序，并产生脉冲信号通知所述检测信号生成模块开始运行；
    初始化m＝1，m为读取次数；
    所述检测信号生成模块开始从ROM模块中读取训练序列；
    判断m＝M是否成立，基于m＝M成立的判断结果，所述检测信号生成模块结束运行；基于m＝M不成立的判断结果，确定m＝m+1，所述检测信号生成模块开始从ROM模块中读取训练序列。
  9. 根据权利要求8所述的方法，其中，所述FPGA芯片根据所述反射信号进行待测电缆状态评估，包括：
    同步模块对所述反射信号进行逻辑运算，并经降噪模块处理后发送至FFT1模块进行信号处理；同时，FFT2模块获取ROM模块的输出信号序列并进行信号处理；
    除法器对所述FFT1模块和所述FFT2模块的输出结果进行处理，计算公式为：
    其中，e3(i)是除法器输出序列中的第i个元素，e1(i)是FFT1模块输出序列的第i个元素，e2(i)是FFT2模块输出序列的第i个元素；N为输出序列长度；
    进行幅值计算，并搜寻峰值第二大的元素，记录所述第二大元素的序号idx，输出数据e3(idx)至状态评估模块；
    所述状态评估模块根据所述输出数据e3(idx)，判断所述待测电缆是否存在绝缘老化，公式为：
    基于所述待测电缆存在绝缘老化的判断结果，判断绝缘老化类型和绝缘老化程度，公式分别为：

    基于所述待测电缆不存在绝缘老化的判断结果，结束状态评估；
    其中，H1表示电缆绝缘状态，T表示门限值，|x|表示x的幅值；H2表示电 缆绝缘老化类型；响应于确定e3(idx)大于0，确定所述待测电缆为高阻绝缘老化；响应于确定e3(idx)小于0，确定所述待测电缆为低阻绝缘老化；H3是经过量化后的绝缘老化程度，用Q比特表示；THR是量化基准；floor(x)表示小于x的最大整数。
  10. 根据权利要求9所述的方法，其中，所述同步模块对所述反射信号进行逻辑运算，包括：
    第一同步相关计算模块和第二同步相关计算模块接收到数模转换器ADC发送的反射信号后进行数据处理，同时，数据延迟模块对输入信号数据延迟，延迟时长为粗同步相关计算模块和细同步相关计算模块数据处理时长；延迟后的数据作为数据截取模块的输入信号；其中，
    所述第一同步相关计算模块进行反射信号能量和自相关值计算，并通过第一比较器判断自相关值是否大于反射信号能量，基于所述自相关值大于所述反射信号能量的判断结果，确定第一同步锁定，同时产生一个第一指示信号；基于所述自相关值小于所述反射信号能量的判断结果，确定所述第一同步未锁定；
    所述第二同步相关计算模块进行反射信号与ROM模块中训练序列的互相关值计算，并通过第二比较器判断所述互相关值是否大于预设门限值，基于所述互相关值大于所述预设门限值的判断结果，确定第二同步锁定，同时产生一个第二指示信号；基于所述互相关值小于所述预设门限值的判断结果，确定所述第二同步未锁定；
    选择器模块获取到所述第二指示信号后，选择将所述第一同步相关计算模块的自相关值作为第三比较器的输入值，经所述第三比较器判断所述输入值的正负性，基于所述输入值为负的判断结果，确定定时同步锁定，同时产生一个第三指示信号；基于所述输入值为正的判断结果，不输出信号；
    所述数据截取模块在检测到所述第三指示信号后，开始输出信号至降噪模块；其中，预设所述降噪模块的输入数据序列为A＝{a11，a12，...，a1N，a21，a22，...，a2N，...，aM1，aM2，...，aMN}，输出数据序列为C＝{c1，c2，...，cN}，所述降噪模块处理通过以下公式进行处理：
    其中ci是输出数据序列C中的第i个元素，aij为输入数据序列A中的第(i-1)*N+j个元素。
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