WO2023184567A1 - 阵列基板、液晶显示面板及显示装置 - Google Patents

阵列基板、液晶显示面板及显示装置 Download PDF

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Publication number
WO2023184567A1
WO2023184567A1 PCT/CN2022/086293 CN2022086293W WO2023184567A1 WO 2023184567 A1 WO2023184567 A1 WO 2023184567A1 CN 2022086293 W CN2022086293 W CN 2022086293W WO 2023184567 A1 WO2023184567 A1 WO 2023184567A1
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Prior art keywords
sub
pixel
pixel electrode
adjacent
pixel units
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PCT/CN2022/086293
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English (en)
French (fr)
Inventor
刘莹莹
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苏州华星光电技术有限公司
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Priority to US17/770,357 priority Critical patent/US11947230B2/en
Publication of WO2023184567A1 publication Critical patent/WO2023184567A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and specifically to an array substrate, a liquid crystal display panel and a display device.
  • LCD panels have been widely used in various fields.
  • LCD panels are used in a variety of electronic products due to their superior characteristics such as thinness, thinness, low power consumption, and no radiation.
  • DLS Data Line Sharing, data line sharing
  • the present application provides an array substrate, a liquid crystal display panel and a display device to solve the technical problem of shaking heads in the display screen of the array substrate with a DLS architecture.
  • This application provides an array substrate, which includes:
  • a plurality of scan lines, the plurality of scan lines are arranged along the first direction;
  • a plurality of data lines, the plurality of data lines are arranged along a second direction, and the second direction intersects the first direction;
  • a plurality of pixel units are arranged in an array, each of the pixel units includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode and the second sub-pixel The electrodes are electrically connected to the same data line;
  • one data line is provided between two adjacent columns of pixel units, and two scan lines are provided between two adjacent rows of pixel units; in each row of pixel units, the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged, and each of the first sub-pixel electrodes is connected to one of the scanning lines that is one level above and adjacent to the row of the pixel unit. Electrically connected, each second sub-pixel electrode is electrically connected to one of the scanning lines at the next level and adjacent to the row where the pixel unit is located.
  • connection types of the first sub-pixel electrode and the second sub-pixel electrode are reduced, thereby reducing the brightness difference between the sub-pixels and improving the problem of head wrinkles.
  • the first sub-pixel electrodes located in two adjacent rows of the pixel units are staggered along the first direction, and in the same column of the pixel units, the first sub-pixel electrodes are staggered.
  • Two adjacent pixel units are respectively connected to two adjacent data lines.
  • the polarity of the first sub-pixel electrode and the second sub-pixel electrode can be controlled, thereby achieving more voltage reactions in the first direction. transfer function.
  • the first sub-pixel electrode is closer to the electrode that simultaneously connects the first sub-pixel electrode and the second sub-pixel electrode. data cable.
  • the array substrate only includes two pixel connection types: B type and C type. Moreover, the C-type gate-source capacitance Cgs is small, and the B-type coupling capacitance Cpg is small, which has less impact on the first sub-pixel electrode and the second sub-pixel electrode, thereby further reducing the brightness difference between each sub-pixel. Improve the problem of shaking head wrinkles.
  • the second sub-pixel electrode is closer to the electrode that simultaneously connects the first sub-pixel electrode and the second sub-pixel electrode. data cable.
  • the array substrate only includes two pixel connection types, A-type and D-type, which can reduce the brightness difference between sub-pixels and improve the problem of head wrinkles.
  • two adjacent data lines are configured to transmit data voltages with opposite polarities.
  • the array substrate adopts a 2-point inversion driving method, which can further improve the quality of the display image.
  • each of the data lines in the same display frame, is configured to transmit data voltages with the same polarity.
  • the same data line The lines are configured to carry data voltages of opposite polarity.
  • the array substrate adopts a frame inversion driving method, which not only improves the display quality, but also reduces the complexity of data voltage changes and reduces the power consumption of the driver chip that provides the data voltage.
  • the first sub-pixel electrodes located in the pixel units in two adjacent rows are arranged in one-to-one correspondence, and the pixel units located in the same column are connected to the same piece of data. wired electrical connection;
  • the first sub-pixel electrode is located in the second column
  • the second sub-pixel electrode is located in the first column
  • the first sub-pixel electrode is located in the first column
  • the The second sub-pixel electrode is located in the second column.
  • the array substrate only includes two pixel connection types, and since the first sub-pixel electrode and the second sub-pixel electrode are at the same position in each pixel unit, the first sub-pixel electrode and the second sub-pixel electrode are The connections between electrodes, scan lines and data lines are more regular, simplifying the manufacturing process.
  • the polarities of the data voltages received by two adjacent pixel units sharing the same data line are opposite.
  • 2-point inversion can be achieved by changing the polarity of the data voltage to further improve the display screen.
  • This application also provides a liquid crystal display panel, which includes an array substrate and a color filter substrate arranged oppositely.
  • the array substrate includes:
  • a plurality of scan lines, the plurality of scan lines are arranged along the first direction;
  • a plurality of data lines, the plurality of data lines are arranged along a second direction, and the second direction intersects the first direction;
  • a plurality of pixel units are arranged in an array, each of the pixel units includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode and the second sub-pixel The electrodes are connected to the same data line;
  • one data line is provided between two adjacent columns of pixel units, and two scan lines are provided between two adjacent rows of pixel units; in each row of pixel units, the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged, and each of the first sub-pixel electrodes is connected to one of the scanning lines that is one level above and adjacent to the row of the pixel unit. Electrically connected, each second sub-pixel electrode is electrically connected to one of the scanning lines at the next level and adjacent to the row where the pixel unit is located.
  • the color filter substrate includes a plurality of color resistors, and the plurality of color resistors include a red color resistor, a green color resistor, and a blue color resistor;
  • each of the color resistors is provided corresponding to a first sub-pixel electrode or a second sub-pixel electrode, and the red color resistor, the green color resistor and the green color resistor are provided corresponding to a row of pixel units.
  • the blue color resistors are repeatedly arranged in any arrangement and combination, and the color resistors corresponding to the first sub-pixel electrode or the second sub-pixel electrode located in the same column have the same color.
  • the first sub-pixel electrodes located in two adjacent rows of the pixel units are staggered along the first direction, and in the same column of the pixel units, the first sub-pixel electrodes are staggered.
  • Two adjacent pixel units are respectively connected to two adjacent data lines.
  • the first sub-pixel electrode is closer to the electrode that simultaneously connects the first sub-pixel electrode and the second sub-pixel electrode. data cable.
  • the second sub-pixel electrode is closer to the electrode that simultaneously connects the first sub-pixel electrode and the second sub-pixel electrode. data cable.
  • the first sub-pixel electrodes located in the pixel units in two adjacent rows are arranged in one-to-one correspondence, and the pixel units located in the same column are connected to the same piece of data. wired electrical connection;
  • the first sub-pixel electrode is located in the second column
  • the second sub-pixel electrode is located in the first column
  • the first sub-pixel electrode is located in the first column
  • the The second sub-pixel electrode is located in the second column.
  • the application also provides a display device, which includes a liquid crystal display panel, a source driver chip and a gate driver circuit.
  • the source driver chip is used to provide data voltage to the liquid crystal display panel.
  • the gate driver circuit is used to provide data voltage to the liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, and the array substrate includes:
  • a plurality of scan lines, the plurality of scan lines are arranged along the first direction;
  • a plurality of data lines, the plurality of data lines are arranged along a second direction, and the second direction intersects the first direction;
  • a plurality of pixel units are arranged in an array, each of the pixel units includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode and the second sub-pixel The electrodes are connected to the same data line;
  • one data line is provided between two adjacent columns of pixel units, and two scan lines are provided between two adjacent rows of pixel units; in each row of pixel units, the first sub-pixel electrodes and the second sub-pixel electrodes are alternately arranged, and each of the first sub-pixel electrodes is connected to one of the scanning lines that is one level above and adjacent to the row of the pixel unit. Electrically connected, each second sub-pixel electrode is electrically connected to one of the scanning lines at the next level and adjacent to the row where the pixel unit is located.
  • the liquid crystal display panel includes a color filter substrate arranged opposite to the array substrate;
  • the color filter substrate includes a plurality of color resistors, and the plurality of color resistors include a red color resistor, a green color resistor and a blue color resistor;
  • each of the color resistors is provided corresponding to a first sub-pixel electrode or a second sub-pixel electrode, and the red color resistor, the green color resistor and the green color resistor are provided corresponding to a row of pixel units.
  • the blue color resistors are repeatedly arranged in any arrangement and combination, and the color resistors corresponding to the first sub-pixel electrode or the second sub-pixel electrode located in the same column have the same color.
  • the first sub-pixel electrodes located in two adjacent rows of the pixel units are staggered along the first direction, and in the same column of the pixel units, the first sub-pixel electrodes are staggered.
  • Two adjacent pixel units are respectively connected to two adjacent data lines.
  • the first sub-pixel electrode is closer to the electrode that simultaneously connects the first sub-pixel electrode and the second sub-pixel electrode. data cable.
  • the second sub-pixel electrode is closer to the electrode that simultaneously connects the first sub-pixel electrode and the second sub-pixel electrode. data cable.
  • the first sub-pixel electrodes located in the pixel units in two adjacent rows are arranged in one-to-one correspondence, and the pixel units located in the same column are connected to the same piece of data. wired electrical connection;
  • the first sub-pixel electrode is located in the second column
  • the second sub-pixel electrode is located in the first column
  • the first sub-pixel electrode is located in the first column
  • the The second sub-pixel electrode is located in the second column.
  • the array substrate includes multiple scan lines, multiple data lines and multiple pixel units.
  • Each pixel unit includes a first sub-pixel electrode and a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode are electrically connected to the same data line.
  • first sub-pixel electrodes and second sub-pixel electrodes are alternately arranged, and each first sub-pixel electrode is electrically connected to a scanning line at the upper level and adjacent to the row of the pixel unit.
  • the second sub-pixel electrodes are all electrically connected to a scan line next to and adjacent to the row where the pixel unit is located.
  • Figure 1 is a schematic structural diagram of an array substrate in the prior art provided by this application.
  • FIG 2 is an enlarged structural schematic diagram of position A in Figure 1 provided by this application;
  • FIG 3 is a schematic diagram of the circuit structure at A in Figure 1 provided by this application;
  • Figure 4 is a schematic diagram of the brightness distribution of green sub-pixels in adjacent columns in Figure 1 provided by this application;
  • FIG. 5 is a schematic diagram of the relationship between data voltage and feeder voltage provided by this application.
  • Figure 6 is a first structural schematic diagram of the array substrate provided by this application.
  • Figure 7 is a schematic diagram of the brightness distribution of green sub-pixels in adjacent columns in Figure 6 provided by this application;
  • Figure 8 is a second structural schematic diagram of the array substrate provided by this application.
  • Figure 9 is a schematic diagram of the brightness distribution of green sub-pixels in adjacent columns in Figure 8 provided by this application.
  • Figure 10 is a third structural schematic diagram of the array substrate provided by this application.
  • Figure 11 is a fourth structural schematic diagram of the array substrate provided by this application.
  • Figure 12 is a schematic structural diagram of the liquid crystal display panel provided by this application.
  • Figure 13 is a schematic structural diagram of a display device provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • This application provides an array substrate, a liquid crystal display panel and a display device, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • Figure 1 is a schematic structural diagram of an array substrate in the prior art provided by this application.
  • Figure 2 is an enlarged structural schematic diagram of position A in Figure 1 provided by this application.
  • Figure 3 is a schematic diagram of the circuit structure at A in Figure 1 provided by this application.
  • each sub-pixel 10 is electrically connected to the corresponding scan line 11 and data line 12 through a transistor (not labeled in the figure).
  • Each sub-pixel 10 includes a pixel electrode 13 .
  • the gate electrode of the transistor is electrically connected to the scan line 11 .
  • the source of the transistor is electrically connected to the data line 12 .
  • the drain of the transistor is electrically connected to the pixel electrode 13 .
  • the connection line between the pixel electrode 13 of the two sub-pixels 10 and the transistor The length is also different.
  • the length of the first connection line 210 in FIG. 2 is greater than the length of the second connection line 220 .
  • the different lengths of the connecting lines are respectively referred to as long-axis connection and short-axis connection.
  • the gate-source capacitance Cgs of the sub-pixels 10 connected along the long axis is larger, and the gate-source capacitance Cgs of the sub-pixels 10 connected along the short axis is smaller.
  • the scan lines 11 are turned on row by row, the first row of scan lines 11 located above the sub-pixels 10 will turn on the sub-pixels 10 connected to it first. Then the second row of scan lines 11 located below the sub-pixel 10 turns on the sub-pixel 10 connected thereto. At this time, the second row scan line 11 has a larger coupling capacitance Cpg to the pixel electrode 13 of the sub-pixel 10 opened through the first row scan line 11, while the third row scan line 11 has a larger coupling capacitance Cpg due to the longer distance.
  • the pixel electrode 13 with the row scanning line 11 turned on has only a small coupling capacitance Cpg, which is negligible.
  • Vft (Cgs+Cpg)/Ctotal
  • Cst is the storage capacitor and Clc is the liquid crystal capacitance.
  • Figure 4 is a schematic diagram of the relationship between the data voltage and the feeder voltage provided in this application.
  • the solid line in the figure represents the ideal voltage of the sub-pixel 10.
  • the dashed line represents the actual voltage of sub-pixel 10.
  • the positive polarity data voltage DA + and the negative polarity data voltage DA- of the same gray scale are symmetrical about the common voltage COM.
  • the difference in the feed circuit voltage Vft corresponds to the difference in display brightness of the sub-pixels 10 .
  • the greater the feed circuit voltage Vft the smaller the actual voltage, and the darker the pixel.
  • the larger the feed circuit voltage Vft is, the larger the actual voltage is and the brighter the pixel is.
  • connection methods of the sub-pixels 10 in the existing array substrate can be divided into four types according to the feed circuit voltage Vft.
  • the first type Type A connected from the bottom (connected to the scan line 11 located below the sub-pixel 10) from the short axis (the gate-source capacitance Cgs is small, the coupling capacitance Cpg is ignored, and the feed circuit voltage Vft is the smallest).
  • Type B connected from the lower long axis (the gate-source capacitance Cgs is large, the coupling capacitance Cpg is ignored, and the feed circuit voltage Vft is small).
  • the third type Type C connected from the top (connected to the scan line 11 located above the sub-pixel 10) on the short axis (the gate-source capacitance Cgs is small, the coupling current Cpg is large, and the feed circuit voltage Vft is large).
  • Figure 5 is a schematic diagram of the brightness distribution of adjacent columns of green sub-pixels in Figure 1 provided by this application.
  • each row of sub-pixels 10 is repeatedly arranged with RGB as a repeating unit, and two adjacent data lines 12 are configured to transmit data voltages with opposite polarities. Since human eyes are more sensitive to green among RGB three-color sub-pixels, this application uses the brightness distribution of green sub-pixels as an example to illustrate.
  • the array substrate 100 includes a plurality of scan lines 11 , a plurality of data lines 12 and a plurality of pixel units 20 .
  • each scan line 11 extends along the second direction X.
  • the plurality of scan lines 11 are arranged along the first direction Y.
  • Each data line 12 extends along the first direction Y.
  • the plurality of data lines 12 are arranged along the second direction X.
  • the plurality of pixel units 20 are arranged in an array.
  • Each pixel unit 20 includes a first sub-pixel electrode 21 and a second sub-pixel electrode 22. The first subpixel electrode 21 and the second subpixel electrode 22 are electrically connected to the same data line 12 .
  • Each data line 12 between two adjacent columns of pixel units 20 .
  • Two scanning lines 11 are provided between two adjacent rows of pixel units 20 .
  • the first sub-pixel electrodes 21 and the second sub-pixel electrodes 22 are alternately arranged.
  • Each first sub-pixel electrode 21 is electrically connected to a scanning line 11 that is one level above and adjacent to the row where the pixel unit 20 is located.
  • Each second sub-pixel electrode 22 is electrically connected to a scan line 11 below and adjacent to the next level of the row where the pixel unit 20 is located.
  • the upper level is the upper level.
  • the first direction Y and the second direction X may intersect perpendicularly, or may only intersect without perpendicularity.
  • the accompanying drawings are only examples and should not be construed as limiting the application.
  • the material of the scan line 11 and the data line 12 can be silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), tungsten (W) or titanium ( Ti) any one.
  • the above-mentioned metal has good conductivity and low cost, and can reduce production costs while ensuring the conductivity of the scan line 11 and the data line 12 .
  • the material of the scan line 11 and the data line 12 can also be a transparent material with a small resistivity such as carbon nanotubes or graphene, so as to reduce the impact of the scan line 11 and the data line 12 on the pixel aperture ratio.
  • the number of scan lines 11 and data lines 12 can be set according to the size of the array substrate 100 and the resolution specification of the array substrate 100, which is not specifically limited in this application.
  • the first sub-pixel electrode 21 and the second sub-pixel electrode 22 are electrically connected to the same data line 12, that is, the DLS driving method is used to reduce the number of data lines 12, thereby reducing the number of source driver chips and reducing the cost. production costs.
  • the sub-pixel electrode electrically connected to the scan line 11 that is opened first is the first sub-pixel electrode 21.
  • the subpixel electrode electrically connected to the scan line 11 that is opened later is the second subpixel electrode 22 .
  • first sub-pixel electrodes 21 and second sub-pixel electrodes 22 are arranged alternately. Moreover, each first sub-pixel electrode 21 is electrically connected to a scanning line 11 located above and adjacent to the pixel unit 20, and each second sub-pixel electrode 22 is electrically connected to a scanning line 11 located below and adjacent to the pixel unit 20.
  • the connection makes the connection method between the first sub-pixel electrode 21 and the second sub-pixel electrode 22 in each row of pixel unit 20 and the scanning line 11 and the data line 12 relatively simple. Therefore, the connection types of the first sub-pixel electrode 21 and the second sub-pixel electrode 22 can be reduced, and the interference difference between the sub-pixels can be reduced, thereby reducing the brightness difference between the sub-pixels, and improving the problem of shaking head wrinkles.
  • the first sub-pixel electrodes 21 located in two adjacent rows of pixel units 20 are staggered.
  • two adjacent pixel units 20 are respectively connected to two adjacent data lines 12.
  • each pixel unit 20 in a row of pixel units 20 is electrically connected to an adjacent data line 12 on the left.
  • Each pixel unit 20 in another row of pixel units 20 is electrically connected to an adjacent data line 12 on the right.
  • the first sub-pixel electrodes 21 located in two adjacent rows of pixel units 20 are staggered, and in the same column, adjacent pixel units 20 are connected to different data lines 12 . While reducing the pixel connection types of the first sub-pixel electrode 21 and the second sub-pixel electrode 22 in the array substrate 100, the first sub-pixel electrode 21 can be controlled by changing the polarity of the data voltage transmitted by the adjacent data line 12. and the polarity of the second subpixel electrode 22 . Therefore, in the first direction Y, more voltage reversal functions can be realized.
  • the first subpixel electrode 21 is closer to the data line 12 that simultaneously connects the first subpixel electrode 21 and the second subpixel electrode 22 .
  • the first sub-pixel electrode 21 is located in the first column, and the second sub-pixel electrode 22 is located in the second column.
  • the first sub-pixel electrode 21 is located in the second column, and the second sub-pixel electrode 22 is located in the first column.
  • the pixel connection type of the first sub-pixel electrode 21 is all C-type, that is, connected from the top short axis.
  • the pixel connection types of the second sub-pixel electrodes 22 are all B-type, that is, they are connected from the lower long axis.
  • the array substrate 100 provided by the embodiment of the present application only includes two pixel connection types. And from the above analysis, it can be seen that the gate-source capacitance Cgs of type C is small, and the coupling capacitance Cpg of type B is small. Therefore, the pixel connection type in the embodiment of the present application has less impact on the first sub-pixel electrode 21 and the second sub-pixel electrode 22, thereby further reducing the brightness difference between the sub-pixels and improving the problem of shake head wrinkles.
  • two adjacent data lines 12 are configured to transmit data voltages with opposite polarities.
  • the array substrate 100 adopts a 2-point inversion driving method along the second direction X, and also adopts a 2-point inversion driving method along the first direction Y, which can further improve the display screen. the quality of.
  • the sub-pixels corresponding to the plurality of first sub-pixel electrodes 21 and the plurality of second sub-pixel electrodes 22 are repeatedly arranged with RGB as a repeating unit, and
  • the sub-pixel colors corresponding to the first sub-pixel electrode 21 or the second sub-pixel electrode 22 located in the same column are all the same. This is explained as an example, but this should not be understood as a limitation of the present application.
  • FIG. 7 is a schematic diagram of the brightness distribution of green sub-pixels in adjacent columns in FIG. 6 provided by this application. It can be seen from the above analysis that in the embodiment of the present application, when two adjacent data lines 12 are configured to transmit data voltages with opposite polarities, in the first row of pixel units 20 , the first green sub-pixel has a positive polarity.
  • the second green sub-pixel is a positive polarity pixel, and is type C connected from the short axis from the top
  • the third green sub-pixel is a negative polarity pixel, and is connected from the bottom
  • the fourth green sub-pixel is a negative polarity pixel, and it is type C connected from the short axis from above.
  • the pixel connection types of the green sub-pixels in the second row of pixel units 20 , the third row of pixel units 20 and the fourth row of pixel units 20 can be obtained based on the above content, and will not be described again here.
  • the gate-source capacitance Cgs is relatively large, and the coupling capacitance Cpg is ignored.
  • the gate-source capacitance Cgs is small and the coupling capacitance Cpg is large. Therefore, taking into account the influence of the gate-source capacitance Cgs and the coupling capacitance Cpg on the brightness of the sub-pixel, the feed voltage Vft of type B and type C can be regarded as the same.
  • the first green sub-pixel and the second green sub-pixel are both positive polarity pixels. Therefore, the brightness of the first green subpixel and the second green subpixel are considered to be the same.
  • the brightness of the third green sub-pixel and the fourth green sub-pixel are considered to be the same. And because, under the same feed circuit voltage Vft, the brightness of the negative polarity pixel is greater than the brightness of the positive polarity pixel, therefore, the brightness of the first green sub-pixel and the second green sub-pixel is set to 2, and the brightness of the third green sub-pixel is set to 2. and the brightness of the fourth green subpixel is set to 3.
  • the brightness arrangement of the second row of pixel units 20 , the third row of pixel units 20 and the fourth row of pixel units 20 can be obtained based on the above analysis, and will not be described again here.
  • each data line 12 in the same display frame, can be configured to transmit data voltages with the same polarity. In two adjacent frames of display, the data line 12 is configured to transmit data voltages with opposite polarities.
  • the array substrate 100 adopts the frame inversion driving method, which not only improves the display quality, but also reduces the complexity of changes in the data voltage and reduces the power consumption of the driver chip that provides the data voltage. And at this time, if there is no difference in positive and negative polarity in the same frame, since the pixel connection type of the first sub-pixel electrode 21 and the second sub-pixel electrode 22 is fixed, the sum of the brightness of the green sub-pixels in adjacent columns is also the same. , will not cause the problem of shaking head wrinkles.
  • FIG. 8 is a second structural schematic diagram of the array substrate provided by the present application.
  • the difference from the array substrate 100 shown in FIG. 6 is that in the embodiment of the present application, in the same pixel unit 20, the second sub-pixel electrode 22 is closer to the first sub-pixel electrode 21 and the second sub-pixel electrode 22.
  • Data line 12 of pixel electrode 22 is closer to the first sub-pixel electrode 21 and the second sub-pixel electrode 22 .
  • the first sub-pixel electrode 21 is located in the second column, and the second sub-pixel electrode 22 is located in the first column.
  • the first sub-pixel electrode 21 is located in the first column, and the second sub-pixel electrode 22 is located in the second column.
  • the pixel connection type of the first sub-pixel electrode 21 is D-type, that is, connected from the upper long axis.
  • the pixel connection types of the second sub-pixel electrodes 22 are all A-type, that is, they are connected from the lower short axis.
  • the array substrate 100 provided by the embodiment of the present application only includes two pixel connection types, which can reduce the brightness difference between sub-pixels and improve the problem of head wrinkles.
  • two adjacent data lines 12 may also be configured to transmit data voltages with opposite polarities.
  • the first green sub-pixel is a positive polarity pixel and is a D-type connected from the upper long axis.
  • the second green sub-pixel is a positive polarity pixel and is connected from the lower short axis.
  • the third green sub-pixel is a negative-polarity pixel and is a D-type connected from the upper long axis.
  • the fourth green sub-pixel is a negative-polarity pixel and is an A-type connected from the lower short axis.
  • the pixel connection types of the green sub-pixels in the second row of pixel units 20 , the third row of pixel units 20 and the fourth row of pixel units 20 can be obtained based on the above content, and will not be described again here.
  • Figure 9 is a schematic diagram of the brightness distribution of green sub-pixels in adjacent columns in Figure 8 provided by this application. It can be seen from the figure that in the brightness distribution of the array substrate 100 in the embodiment of the present application, the sum of the brightness of the green sub-pixels in adjacent columns is 10. There is no column brightness difference, and the stripe-like shaking head phenomenon will not be formed.
  • FIG. 10 is a third structural schematic diagram of the array substrate provided by the present application.
  • the difference from the array substrate 100 shown in FIG. 6 is that in this embodiment, the first sub-pixel electrodes 21 located in two adjacent rows of pixel units 20 are arranged in one-to-one correspondence, and the pixel units 20 located in the same column are It is electrically connected to the same data line 12 .
  • the first sub-pixel electrode 21 is located in the first column, and the second sub-pixel electrode 22 is located in the second column.
  • the pixel connection type of the first sub-pixel electrode 21 is all C-type, that is, connected from the upper short axis.
  • the pixel connection types of the second sub-pixel electrodes 22 are all B-type, that is, they are connected from the lower long axis.
  • the pixel connection type of the first sub-pixel electrode 21 and the second sub-pixel electrode 22 is fixed, which reduces the pixel connection type in the array substrate 100 and reduces the interference difference between each sub-pixel.
  • the first sub-pixel electrode 21 and the second sub-pixel electrode 22 in each row of pixel units 20 are the same, the first sub-pixel electrode 21 and the second sub-pixel electrode 22 are connected to the scanning line 11 and the data line 12 .
  • the connections are more regular and the manufacturing process is simplified.
  • the polarity of the data voltage transmitted by each data line 12 when each row of scanning lines 11 is turned on can also be changed, so that two adjacent data lines sharing the same data line 12 along the first direction Y
  • the data voltages received by each pixel unit 20 have opposite polarities. While simplifying the manufacturing process, 2-point inversion is achieved by changing the polarity of the data voltage, further improving the display screen.
  • FIG. 11 is a fourth structural schematic diagram of the array substrate provided by the present application.
  • the difference from the array substrate 100 shown in FIG. 10 is that in this embodiment, in each pixel unit 20, the first sub-pixel electrode 21 is located in the second column, and the second sub-pixel electrode 22 is located in the first column. .
  • the pixel connection type of the first sub-pixel electrode 21 is type A, that is, connected from the upper long axis.
  • the pixel connection types of the second sub-pixel electrodes 22 are all D-type, that is, they are connected from the lower short axis.
  • the pixel connection types of the first sub-pixel electrode 21 and the second sub-pixel electrode 22 are fixed, which reduces the pixel connection types in the array substrate 100 and reduces the interference difference between each sub-pixel.
  • the first sub-pixel electrode 21 and the second sub-pixel electrode 22 are at the same position, so that the first sub-pixel electrode 21 and the second sub-pixel electrode 22 are in direct contact with the scanning line 11 and the data line 12.
  • the connections are more regular and the manufacturing process is simplified.
  • this application also provides a liquid crystal display panel.
  • FIG. 12 is a schematic structural diagram of the liquid crystal display panel provided by the present application.
  • the liquid crystal display panel 1000 includes an array substrate 100 and a color filter substrate 200 arranged oppositely.
  • the liquid crystal layer 30 is disposed between the array substrate 100 and the color filter substrate 200 .
  • the array substrate 100 includes a functional film layer 101 and a first sub-pixel electrode 21 and a second sub-pixel electrode 22 provided on the functional film layer 101 .
  • the color filter substrate 200 includes a substrate 201 and a color resistor 202 disposed on the substrate 201 . Each color resistor 202 is provided corresponding to a first sub-pixel electrode 21 or a second sub-pixel electrode 22 .
  • the sub-pixels presented in the display screen may be red sub-pixels, green sub-pixels, blue sub-pixels, white sub-pixels, yellow sub-pixels, etc., which are not specifically limited in this application.
  • the LCD panel 1000 provided by this application can adopt the standard RGB pixel arrangement architecture, RGB PenTile pixel arrangement architecture, RGB Delta pixel arrangement architecture, RGBW pixel arrangement architecture, etc. The specific settings can be based on the display requirements of the LCD panel 1000.
  • the plurality of color resistors 202 may include red color resistors, green color resistors, blue color resistors, etc., to form red sub-pixels, green sub-pixels and blue sub-pixels correspondingly.
  • the red color resistors, green color resistors and blue color resistors provided corresponding to one row of pixel units 20 are repeatedly arranged in any arrangement and combination.
  • the color resistors 202 corresponding to the first sub-pixel electrode 21 or the second sub-pixel electrode 22 located in the same column have the same color.
  • the RGB pixel arrangement structure is simple and the process is mature.
  • the process can be simplified and the production cost can be reduced.
  • this application also provides a display device, which includes an array substrate, a source driver chip and a gate driver circuit.
  • the source driver chip is used to provide data voltage to the array substrate.
  • the gate drive circuit is used to provide scanning signals to the array substrate.
  • the array substrate is the array substrate described in any of the above embodiments. For details, please refer to the above content and will not be described again here.
  • the display device may be a smartphone, a tablet computer, an e-book reader, a smart watch, a video camera, a game console, etc., which is not limited in this application.
  • FIG. 13 is a schematic structural diagram of a display device provided by the present application.
  • the display device 2000 includes a liquid crystal display panel 1000, a gate driving circuit 500, a source driving chip 300 and a timing controller 400.
  • the liquid crystal display panel 1000 includes an array substrate.
  • the array substrate includes a plurality of scan lines 11 and a plurality of data lines 12 .
  • the plurality of scan lines 11 are arranged along the first direction Y.
  • the plurality of data lines 12 are arranged along the second direction X.
  • the liquid crystal display panel 1000 includes a plurality of sub-pixels (not labeled in the figure), and each sub-pixel is electrically connected to a corresponding scan line 11 and a data line 12 .
  • the timing controller 400 may generate a scan control signal for controlling the gate driving circuit 500 and a data control signal for controlling the source driving chip 300 in response to an externally received control signal.
  • the control signals may include a dot clock, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal.
  • the timing controller 400 may supply the scan control signal to the gate driving circuit 500 and may supply the data control signal to the source driving chip 300 .
  • the gate driving circuit 500 transmits scanning signals to the liquid crystal display panel 1000 through the scanning lines 11 .
  • the gate driving circuit 500 may be an independently provided gate chip.
  • the gate driving circuit 500 may be a GOA (array substrate gate driving technology) disposed in the array substrate, which is not specifically limited in this application.
  • the source driver chip 300 transmits data signals to the liquid crystal display panel 1000 through the data lines 12 .
  • the source driver chip 300 can be bound to the array substrate through a COF (Chip On Film), which is not specifically limited in this application.
  • the display device 2000 includes a liquid crystal display panel 1000 .
  • first sub-pixel electrodes and second sub-pixel electrodes are arranged alternately, and in two adjacent rows of pixel units, the first sub-pixel electrodes are arranged alternately or in one-to-one correspondence.
  • each first sub-pixel electrode is electrically connected to a scan line located above and adjacent to the pixel unit
  • each second sub-pixel electrode is electrically connected to a scan line located below and adjacent to the pixel unit, so that each row of pixels
  • the connection method between the first sub-pixel electrode and the second sub-pixel electrode in the unit and the scanning line and the data line is relatively simple. This can reduce the connection types of the first sub-pixel electrode and the second sub-pixel electrode, reduce the interference difference between the sub-pixels, thereby reducing the brightness difference between the sub-pixels, and improve the problem of shake head wrinkles.

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Abstract

一种阵列基板(100)、液晶显示面板(1000)及显示装置(2000)。每一像素单元(20)均包括电连接至同一条数据线(12)的第一子像素电极(21)和第二子像素电极(22)。每一行像素单元(20)中，第一子像素电极(21)和第二子像素电极(22)交替排布，第一子像素电极(21)与像素单元(20)所在行的上一级且邻近的一条扫描线(11)连接，第二子像素电极(22)与像素单元(20)所在行下一级且邻近的一条扫描线(11)连接。

Description

阵列基板、液晶显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板、液晶显示面板及显示装置。
 背景技术
随着科技的进步，液晶显示面板已经广泛的被运用在各种领域，尤其是液晶显示面板，因具有体型轻薄、低功率消耗及无辐射等优越特性，而应用在多种电子产品中。而随着解析度及分辨率的提升，液晶显示面板中的数据线的数量会成比例增加，进而提供数据信号的源极驱动芯片的数量成倍增加，导致生产成本上升。对此，常采用DLS(Data Line Sharing，数据线共享)的驱动方式，以减少数据线的数量。
 技术问题
在静止情况下观察这种DLS架构的液晶显示面板时，由于正负帧不断切换，像素显示的亮度也不断亮暗变化，亮度在人眼叠加，人眼并不能分辨出任何亮度差异。但是当液晶显示面板显示动态画面或者人摇头观看屏幕的情况下，亮、亮或暗、暗相叠加，人眼就会捕捉到条纹或网格状的显示画面，即所谓的摇头纹现象。
 技术解决方案
本申请提供一种阵列基板、液晶显示面板及显示装置，以解决具有DLS架构的阵列基板的显示画面中出现摇头纹的技术问题。
本申请提供一种阵列基板，其包括：
多条扫描线，多条所述扫描线沿第一方向排布；
多条数据线，多条所述数据线沿第二方向排布，所述第二方向与所述第一方向交叉；
多个像素单元，多个所述像素单元呈阵列排布，每一所述像素单元均包括第一子像素电极和第二子像素电极，所述第一子像素电极和所述第二子像素电极电连接至同一条所述数据线；
其中，相邻的两列所述像素单元之间均设有一条所述数据线，相邻的两行所述像素单元之间均设有两条所述扫描线；在每一行所述像素单元中，所述第一子像素电极和所述第二子像素电极交替排布，每一所述第一子像素电极均与所述像素单元所在行的上一级且邻近的一条所述扫描线电连接，每一所述第二子像素电极均与所述像素单元所在行的下一级且邻近的一条所述扫描线电连接。
本申请实施例中，减少了第一子像素电极和第二子像素电极的连接类型，从而减小了各子像素之间的亮度差异，改善了摇头纹问题。
可选的，在本申请一些实施例中，沿所述第一方向，位于相邻两行所述像素单元中的所述第一子像素电极交错设置，在同一列所述像素单元中，相邻的两个所述像素单元分别连接至相邻的两条所述数据线。
本申请实施例中，通过改变相邻数据线传输的数据电压的极性，即可控制第一子像素电极和第二子像素电极的极性，从而在第一方向上，实现更多电压反转的功能。
可选的，在本申请一些实施例中，在同一个所述像素单元中，所述第一子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
本申请实施例中，阵列基板仅包括B型和C型两种像素连接类型。且C型的栅源电容Cgs较小，B型的耦合电容Cpg较小，对第一子像素电极和第二子像素电极的影响更小，从而进一步减小各子像素之间的亮度差异，改善摇头纹问题。
可选的，在本申请一些实施例中，在同一个所述像素单元中，所述第二子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
本申请实施例中，阵列基板仅包括A型和D型两种像素连接类型，可以减小各子像素之间的亮度差异，改善摇头纹问题。
可选的，在本申请一些实施例中，在同一帧显示画面中，相邻两条所述数据线被配置为传输极性相反的数据电压。
本申请实施例中，阵列基板采用2点反转的驱动方式，可以进一步改善显示画面的质量。
可选的，在本申请一些实施例中，在同一帧显示画面中，每条所述数据线均被配置为传输极性相同的数据电压，在相邻两帧显示画面中，同一所述数据线被配置为传输极性相反的数据电压。
本申请实施例中，阵列基板采用帧反转的驱动方式，在改善显示画面质量的同时，降低数据电压的变化复杂性，降低提供数据电压的驱动芯片的功耗。
可选的，在本申请一些实施例中，位于相邻两行所述像素单元中的所述第一子像素电极一一对应设置，且位于同一列的所述像素单元与同一条所述数据线电连接；
其中，在每一所述像素单元中，所述第一子像素电极位于第二列，所述第二子像素电极位于第一列，或者所述第一子像素电极位于第一列，所述第二子像素电极位于第二列。
本申请实施例中，阵列基板仅包括两种像素连接类型，且由于每一像素单元中，第一子像素电极和第二子像素电极的位置相同，使得第一子像素电极和第二子像素电极与扫描线以及数据线的连接更加规律，简化了制程工艺。
可选的，在本申请一些实施例中，沿所述第一方向，共用同一条所述数据线的相邻两个所述像素单元接收的数据电压的极性相反。
本申请实施例中，在简化制成工艺的同时，可以通过数据电压极性的改变，实现2点反转，进一步改善显示画面。
本申请还提供一种液晶显示面板，其包括相对设置的阵列基板和彩膜基板，所述阵列基板包括：
多条扫描线，多条所述扫描线沿第一方向排布；
多条数据线，多条所述数据线沿第二方向排布，所述第二方向与所述第一方向交叉；
多个像素单元，多个所述像素单元呈阵列排布，每一所述像素单元均包括第一子像素电极和第二子像素电极，所述第一子像素电极和所述第二子像素电极连接至同一条所述数据线；
其中，相邻的两列所述像素单元之间均设有一条所述数据线，相邻的两行所述像素单元之间均设有两条所述扫描线；在每一行所述像素单元中，所述第一子像素电极和所述第二子像素电极交替排布，每一所述第一子像素电极均与所述像素单元所在行的上一级且邻近的一条所述扫描线电连接，每一所述第二子像素电极均与所述像素单元所在行的下一级且邻近的一条所述扫描线电连接。
可选的，在本申请一些实施例中，所述彩膜基板包括多个色阻，所述多个色阻包括红色色阻、绿色色阻以及蓝色色阻；
其中，每一所述色阻对应一所述第一子像素电极或一所述第二子像素电极设置，对应一行所述像素单元设置的所述红色色阻、所述绿色色阻以及所述蓝色色阻以任一排列组合重复排列，位于同一列的所述第一子像素电极或所述第二子像素电极对应的所述色阻的颜色相同。
可选的，在本申请一些实施例中，沿所述第一方向，位于相邻两行所述像素单元中的所述第一子像素电极交错设置，在同一列所述像素单元中，相邻的两个所述像素单元分别连接至相邻的两条所述数据线。
可选的，在本申请一些实施例中，在同一个所述像素单元中，所述第一子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
可选的，在本申请一些实施例中，在同一个所述像素单元中，所述第二子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
可选的，在本申请一些实施例中，位于相邻两行所述像素单元中的所述第一子像素电极一一对应设置，且位于同一列的所述像素单元与同一条所述数据线电连接；
其中，在每一所述像素单元中，所述第一子像素电极位于第二列，所述第二子像素电极位于第一列，或者所述第一子像素电极位于第一列，所述第二子像素电极位于第二列。
本申请还提供一种显示装置，其包括液晶显示面板、源极驱动芯片和栅极驱动电路，所述源极驱动芯片用于提供数据电压至所述液晶显示面板，所述栅极驱动电路用于提供扫描信号至所述液晶显示面板，所述液晶显示面板包括阵列基板，所述阵列基板包括：
多条扫描线，多条所述扫描线沿第一方向排布；
多条数据线，多条所述数据线沿第二方向排布，所述第二方向与所述第一方向交叉；
多个像素单元，多个所述像素单元呈阵列排布，每一所述像素单元均包括第一子像素电极和第二子像素电极，所述第一子像素电极和所述第二子像素电极连接至同一条所述数据线；
其中，相邻的两列所述像素单元之间均设有一条所述数据线，相邻的两行所述像素单元之间均设有两条所述扫描线；在每一行所述像素单元中，所述第一子像素电极和所述第二子像素电极交替排布，每一所述第一子像素电极均与所述像素单元所在行的上一级且邻近的一条所述扫描线电连接，每一所述第二子像素电极均与所述像素单元所在行的下一级且邻近的一条所述扫描线电连接。
可选的，在本申请一些实施例中，所述液晶显示面板包括与所述阵列基板相对设置的彩膜基板；
所述彩膜基板包括多个色阻，所述多个色阻包括红色色阻、绿色色阻以及蓝色色阻；
其中，每一所述色阻对应一所述第一子像素电极或一所述第二子像素电极设置，对应一行所述像素单元设置的所述红色色阻、所述绿色色阻以及所述蓝色色阻以任一排列组合重复排列，位于同一列的所述第一子像素电极或所述第二子像素电极对应的所述色阻的颜色相同。
可选的，在本申请一些实施例中，沿所述第一方向，位于相邻两行所述像素单元中的所述第一子像素电极交错设置，在同一列所述像素单元中，相邻的两个所述像素单元分别连接至相邻的两条所述数据线。
可选的，在本申请一些实施例中，在同一个所述像素单元中，所述第一子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
可选的，在本申请一些实施例中，在同一个所述像素单元中，所述第二子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
可选的，在本申请一些实施例中，位于相邻两行所述像素单元中的所述第一子像素电极一一对应设置，且位于同一列的所述像素单元与同一条所述数据线电连接；
其中，在每一所述像素单元中，所述第一子像素电极位于第二列，所述第二子像素电极位于第一列，或者所述第一子像素电极位于第一列，所述第二子像素电极位于第二列。
 有益效果
本申请提供一种阵列基板、液晶显示面板及显示装置。阵列基板包括多条扫描线、多条数据线以及多个像素单元。每一像素单元均包括第一子像素电极和第二子像素电极，第一子像素电极和第二子像素电极电连接至同一条数据线。其中，相邻的两列像素单元之间均设有一条数据线，相邻的两行像素单元之间均设有两条扫描线。在每一行像素单元中，第一子像素电极和第二子像素电极交替排布，每一第一子像素电极均与像素单元所在行的上一级且邻近的一条扫描线电连接，每一第二子像素电极均与像素单元所在行的下一级且邻近的一条扫描线电连接。本申请通过上述设置能够减少阵列基板中子像素的连接种类，减小各子像素之间受到的干扰差异，进而减小各子像素之间的亮度差异，改善摇头纹问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的现有技术中阵列基板的结构示意图；
图2是本申请提供的图1中A处的放大结构示意图；
图3是本申请提供的图1中A处的电路结构示意图；
图4是本申请提供的图1中相邻列绿色子像素的亮度分布示意图；
图5是本申请提供的数据电压与馈路电压的关系示意图；
图6是本申请提供的阵列基板的第一结构示意图；
图7是本申请提供的图6中相邻列绿色子像素的亮度分布示意图；
图8是本申请提供的阵列基板的第二结构示意图；
图9是本申请提供的图8中相邻列绿色子像素的亮度分布示意图；
图10是本申请提供的阵列基板的第三结构示意图；
图11是本申请提供的阵列基板的第四结构示意图；
图12是本申请提供的液晶显示面板的一种结构示意图；
图13是本申请提供的显示装置的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。
本申请提供一种阵列基板、液晶显示面板及显示装置，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
具体的，请参阅图1-图3。图1是本申请提供的现有技术中阵列基板的结构示意图。图2是本申请提供的图1中A处的放大结构示意图。图3是本申请提供的图1中A处的电路结构示意图。
通常每一子像素10均通过一晶体管（图中未标识）与相应的扫描线11以及数据线12电连接。每一子像素10均包括像素电极13。晶体管的栅极与扫描线11电连接。晶体管的源极与数据线12电连接。晶体管的漏极与像素电极13电连接。
首先，对于与同一根数据线12连接的相邻两个子像素10，由于两个子像素10与同一条数据线12之间的距离不同，两个子像素10的像素电极13与晶体管之间的连接线长度也不同。比如，图2中的第一连接线210的长度大于第二连接线220的长度。本申请以下实施例均将连接线的长短不同分别称为长轴连接和短轴连接。长轴连接的子像素10的栅源电容Cgs较大，短轴连接的子像素10的栅源电容Cgs较小。
其次，由于扫描线11逐行打开，位于子像素10上方的第一行扫描线11将与其连接的子像素10先打开。随后位于子像素10下方的第二行扫描线11打开与其连接的子像素10。此时，第二行扫描线11对经第一行扫描线11打开的子像素10的像素电极13有较大的耦合电容Cpg，而第三行扫描线11由于距离较远，对经第二行扫描线11打开的像素电极13只有较小的耦合电容Cpg，可忽略不计。
因此，根据栅源Cgs以及耦合电容Cpg引起的Feedthrough（馈路）电压公式为：
Vft=（Cgs+Cpg）/Ctotal
可知栅源电容Cgs和耦合电容Cpg的大小差异会造成不同子像素10的馈路电压Vft大小差异。其中，Ctotal为所有像素相关电容，常见的公式为Ctotal=Cgs+Cst+Clc。其中，Cst为存储电容，Clc为液晶电容。
请同时参阅图1-图4，图4是本申请提供的数据电压与馈路电压的关系示意图。其中，图中实线代表子像素10的理想电压。虚线代表子像素10的实际电压。同一灰阶的正极性数据电压DA +和负极性数据电压DA -关于公共电压COM对称。可知，馈路电压Vft的差异对应的即是子像素10的显示亮度差异。其中，对于正极性像素，馈路电压Vft越大，实际电压越小，像素越暗。而对于负极性像素，馈路电压Vft越大，实际越大，像素越亮。
因此，结合图1可知，现有阵列基板中子像素10的连接方式可通过馈路电压Vft分为四种类型。第一种：从下（与位于子像素10下方的扫描线11连接）短轴连接的A型（栅源电容Cgs较小，耦合电容Cpg忽略，馈路电压Vft最小）。第二种：从下长轴连接的B型（栅源电容Cgs较大，耦合电容Cpg忽略，馈路电压Vft较小）。第三种：从上（与位于子像素10上方的扫描线11连接）短轴连接的C型（栅源电容Cgs较小，耦合电Cpg较大，馈路电压Vft较大）。第四种：从上长轴连接的D（栅源电容Cgs较大，耦合电Cpg较大，馈路电压Vft最大）。
进一步的，请同时参阅图1-图5，图5是本申请提供的图1中相邻列绿色子像素的亮度分布示意图。其中，现有阵列基板中，每行子像素10以RGB为重复单元重复排列，且相邻两条数据线12被配置为传输极性相反的数据电压。由于在RGB三色子像素中，人眼对绿色较为敏感，所以本申请以绿色子像素的亮度分布为例进行说明。
具体的，根据上述四种像素连接类型以及子像素10的正负极性，发现相邻列绿色子像素的亮度总和为8和12之间的切换，本身有列亮度差异，最终导致摇头纹现象的形成。
请参阅图6，图6是本申请提供的阵列基板的第一结构示意图。在本申请实施例中，阵列基板100包括多条扫描线11、多条数据线12以及多个像素单元20。
具体的，每条扫描线11均沿第二方向X延伸。多条扫描线11沿第一方向Y排布。每条数据线12沿第一方向Y延伸。多条数据线12沿第二方向X排布。多个像素单元20呈阵列排布。每一像素单元20均包括第一子像素电极21和第二子像素电极22。第一子像素电极21和第二子像素电极22电连接至同一条数据线12。
其中，相邻的两列像素单元20之间均设有一条数据线12。相邻的两行像素单元20之间均设有两条扫描线11。在每一行像素单元20中，第一子像素电极21和第二子像素电极22交替排布。每一第一子像素电极21均与像素单元20所在行的上一级且邻近的一条扫描线11电连接。每一第二子像素电极22均与像素单元20所在行的下一级下方且邻近的一条扫描线11电连接。
其中，在阵列基板100处于竖直平面时，上一级即为上方。第一方向Y和第二方向X可以垂直交叉，也可以只交叉不垂直。附图仅为示例，不能理解为对本申请的限定。
其中，扫描线11和数据线12的材料可以为银（Ag）、铝（Al）、镍（Ni）、铬（Cr）、钼（Mo）、铜（Cu）、钨（W）或钛（Ti）中的任一种。上述金属的导电性好，成本较低，在保证扫描线11和数据线12的导电性的同时可以降低生产成本。扫描线11和数据线12的材料也可以为碳纳米管或石墨烯等电阻率较小的透明材料，以降低扫描线11和数据线12对像素开口率的影响。
其中，扫描线11和数据线12的条数可根据阵列基板100的尺寸以及阵列基板100的分辨率规格进行设定，本申请对此不作具体限定。
其中，第一子像素电极21和第二子像素电极22电连接至同一条数据线12，也即采用了DLS驱动方式，减少数据线12的数量，进而减少了源极驱动芯片的数量，降低了生产成本。
其中，由于扫描线11逐行打开，因此在每一像素单元20中，与先打开的扫描线11电连接的子像素电极为第一子像素电极21。与后打开的扫描线11电连接的子像素电极为第二子像素电极22。
在本申请实施例中，在每一行像素单元20中，设置第一子像素电极21和第二子像素电极22交替排布。并且设置每一第一子像素电极21均与位于像素单元20上方且邻近的一条扫描线11电连接，每一第二子像素电极22均与位于像素单元20下方且邻近的一条扫描线11电连接，使得每一行像素单元20中的第一子像素电极21和第二子像素电极22与扫描线11以及数据线12之间的连接方式比较单一。从而能够减少第一子像素电极21和第二子像素电极22的连接类型，减小各子像素之间受到的干扰差异，进而减小各子像素之间的亮度差异，改善摇头纹问题。
需要说明的是，在本申请实施例中，至少位于奇数行的像素单元20的像素连接类型均相同，位于偶数行的像素单元20的像素连接类型均相同。因此，图中仅示出第一行像素单元20和第二行像素单元20作为示例。
请继续参阅图6，在本申请实施例中，沿第一方向Y，位于相邻两行像素单元20中的第一子像素电极21交错设置。在同一列像素单元20中，相邻的两个像素单元20分别连接至相邻的两条数据线12。
具体的，其中一行像素单元20中的每一像素单元20均与左侧邻近的一条数据线12电连接。另一行像素单元20中的每一像素单元20均与右侧邻近的一条数据线12电连接。
本申请实施例中，位于相邻两行像素单元20中的第一子像素电极21交错设置，且同一列中，相邻的像素单元20连接至不同的数据线12。在减少阵列基板100中第一子像素电极21和第二子像素电极22的像素连接类型的同时，通过改变相邻数据线12传输的数据电压的极性，即可控制第一子像素电极21和第二子像素电极22的极性。从而在第一方向Y上，可实现更多电压反转的功能。
进一步的，在同一个像素单元20中，第一子像素电极21更靠近同时连接第一子像素电极21和第二子像素电极22的数据线12。
具体的，在与左侧邻近的一条数据线12电连接的像素单元20中，第一子像素电极21位于第一列，第二子像素电极22位于第二列。在与右侧邻近的一条数据线12电连接的像素单元20中，第一子像素电极21位于第二列，第二子像素电极22位于第一列。
可以理解的是，在本申请实施例的阵列基板100中，第一子像素电极21的像素连接类型均为C型，即从上短轴连接。第二子像素电极22的像素连接类型均为B型，即从下长轴连接。
可知，本申请实施例提供的阵列基板100仅包括两种像素连接类型。且由上述分析可知，C型的栅源电容Cgs较小，B型的耦合电容Cpg较小。因此，本申请实施例中的像素连接类型对第一子像素电极21和第二子像素电极22的影响更小，从而进一步减小各子像素之间的亮度差异，改善摇头纹问题。
进一步的，在同一帧显示画面中，相邻两条数据线12被配置为传输极性相反的数据电压。
由此，在本申请实施例中，沿第二方向X，阵列基板100采用2点反转的驱动方式，且沿第一方向Y，同样采用2点反转的驱动方式，可以进一步改善显示画面的质量。
需要说明的是，本申请以下实施例均以在每一行像素单元20中，多个第一子像素电极21以及多个第二子像素电极22对应的子像素以RGB为重复单元重复排列，且位于同一列的第一子像素电极21或第二子像素电极22对应的子像素颜色都相同为例进行说明，但不能理解为对本申请的限定。
此外，请参阅图7，图7是本申请提供的图6中相邻列绿色子像素的亮度分布示意图。由上述分析可知，在本申请实施例中，当相邻两条数据线12被配置为传输极性相反的数据电压时，在第一行像素单元20中，第一个绿色子像素为正极性像素，且为从下长轴连接的B型，第二个绿色子像素为正极性像素，且为从上短轴连接的C型，第三个绿色子像素为负极性像素，且为从下长轴连接的B型，第四个绿色子像素为负极性像素，且为从上短轴连接的C型。第二行像素单元20、第三行像素单元20以及第四行像素单元20（图中未示出）中的绿色子像素的像素连接类型均可根据上述内容得到，在此不一一赘述。
其中，在第一行像素单元20中，对于第一个绿色子像素而言，栅源电容Cgs较大，耦合电容Cpg忽略。对于第二个绿色子像素而言，栅源电容Cgs较小，耦合电容Cpg较大。因此，综合考虑栅源电容Cgs和耦合电容Cpg对子像素的亮度影响，B型和C型的馈路电压Vft可视为相同。且第一个绿色子像素和第二个绿色子像素均为正极性像素。因此，第一个绿色子像素和第二个绿色子像素的亮度视为相同。同理，第三个绿色子像素和第四个绿色子像素的亮度视为相同。又因为，相同馈路电压Vft下，负极性像素的亮度大于正极性像素的亮度，因此，将第一个绿色子像素和第二个绿色子像素的亮度设为2，第三个绿色子像素和第四个绿色子像素的亮度设为3。第二行像素单元20、第三行像素单元20以及第四行像素单元20的亮度排布均可根据上述分析得到，在此不再赘述。
由此可知，在本申请实施例的阵列基板100的亮度分布中，相邻列绿色子像素的亮度总和均为10，本身没有列亮度差异，则不会形成条纹状的摇头纹现象。
当然，在本申请其它实施例中，在同一帧显示画面中，每条数据线12均可被配置为传输极性相同的数据电压。在相邻两帧显示画面中，数据线12被配置为传输极性相反的数据电压。
由此，阵列基板100采用帧反转的驱动方式，在改善显示画面质量的同时，降低数据电压的变化复杂性，降低提供数据电压的驱动芯片的功耗。且此时，若同一帧画面中不存在正负极性的差异，由于第一子像素电极21和第二子像素电极22的像素连接类型固定，相邻列绿色子像素的亮度总和也均相同，不会产生摇头纹问题。
请参阅图8，图8是本申请提供的阵列基板的第二结构示意图。与图6所示的阵列基板100的不同之处在于，在本申请实施例中，在同一个像素单元20中，第二子像素电极22更靠近同时连接第一子像素电极21和第二子像素电极22的数据线12。
具体的，在与左侧邻近的一条数据线12电连接的像素单元20中，第一子像素电极21位于第二列，第二子像素电极22位于第一列。在与右侧邻近的一条数据线12电连接的像素单元20中，第一子像素电极21位于第一列，第二子像素电极22位于第二列。
在本申请实施例的阵列基板100中，第一子像素电极21的像素连接类型均为D型，即从上长轴连接。第二子像素电极22的像素连接类型均为A型，即从下短轴连接。
可知，本申请实施例提供的阵列基板100仅包括两种像素连接类型，可以减小各子像素之间的亮度差异，改善摇头纹问题。
进一步的，相邻两条数据线12也可被配置为传输极性相反的数据电压。此时，第一行像素单元20中，第一个绿色子像素为正极性像素，且为从上长轴连接的D型，第二个绿色子像素为正极性像素，且为从下短轴连接的A型，第三个绿色子像素为负极性像素，且为从上长轴连接的D型，第四个绿色子像素为负极性像素，且为从下短轴连接的A型。第二行像素单元20、第三行像素单元20以及第四行像素单元20中的绿色子像素的像素连接类型均可根据上述内容得到，在此不一一赘述。
请参阅图9，图9是本申请提供的图8中相邻列绿色子像素的亮度分布示意图。由图可知，在本申请实施例的阵列基板100的亮度分布中，相邻列绿色子像素的亮度总和均为10，本身没有列亮度差异，则不会形成条纹状的摇头纹现象。
请参阅图10，图10是本申请提供的阵列基板的第三结构示意图。与图6所示的阵列基板100的不同之处在于，在本实施例中，位于相邻两行像素单元20中的第一子像素电极21一一对应设置，且位于同一列的像素单元20与同一条数据线12电连接。其中，在每一像素单元20中，第一子像素电极21位于第一列，第二子像素电极22位于第二列。
在本申请实施例中，第一子像素电极21的像素连接类型均为C型，即从上短轴连接。第二子像素电极22的像素连接类型均为B型，即从下长轴连接。第一子像素电极21和第二子像素电极22的像素连接类型固定，减少了阵列基板100中像素连接类型，减小了各子像素之间受到的干扰差异。
此外，由于每一行像素单元20中，第一子像素电极21和第二子像素电极22的位置相同，使得第一子像素电极21和第二子像素电极22与扫描线11以及数据线12的连接更加规律，简化了制程工艺。
进一步的，当相邻两条数据线12也可被配置为传输极性相反的数据电压时，沿第二方向X，采用2点反转的驱动方式，沿第一方向Y，每一像素单元20接入的数据电压的极性均相同。
当然，在其它实施例中，也可以通过改变每条数据线12在每行扫描线11打开时传输的数据电压的极性，使得沿第一方向Y，共用同一条数据线12的相邻两个像素单元20接收的数据电压的极性相反。在简化制成工艺的同时，通过数据电压极性的改变，实现2点反转，进一步改善显示画面。
请参阅图11，图11是本申请提供的阵列基板的第四结构示意图。与图10所示的阵列基板100的不同之处在于，在本实施例中，在每一像素单元20中，第一子像素电极21位于第二列，第二子像素电极22位于第一列。
在本申请实施例中，第一子像素电极21的像素连接类型均为A型，即从上长轴连接。第二子像素电极22的像素连接类型均为D型，即从下短轴连接。第一子像素电极21和第二子像素电极22的像素连接类型固定，减少了阵列基板100中的像素连接类型，减小了各子像素之间受到的干扰差异。
同理，由于每一行像素单元20中，第一子像素电极21和第二子像素电极22的位置相同，使得第一子像素电极21和第二子像素电极22与扫描线11以及数据线12的连接更加规律，简化了制程工艺。
相应的，本申请还提供一种液晶显示面板。具体的，请参阅图12，图12是本申请提供的液晶显示面板的一种结构示意图。
液晶显示面板1000包括相对设置的阵列基板100和彩膜基板200。阵列基板100和彩膜基板200之间设有液晶层30。阵列基板100包括功能膜层101以及设置在功能膜层101上的第一子像素电极21和第二子像素电极22。彩膜基板200包括衬底201和设置在衬底201上的色阻202。每一色阻202对应一第一子像素电极21或一第二子像素电极22设置。
在液晶显示面板1000中，显示画面中呈现的子像素可以是红色子像素、绿色子像素、蓝色子像素、白色子像素、黄色子像素等，本申请对此不作具体限定。本申请提供的液晶显示面板1000可以采用标准RGB像素排列架构、RGB PenTile像素排列架构、RGB Delta像素排列架构、RGBW像素排列架构等，具体可根据液晶显示面板1000的显示需求进行设置。
对此，在本申请一些实施例中，多个色阻202可以包括红色色阻、绿色色阻、蓝色色阻等，以对应形成红色子像素、绿色子像素以及蓝色子像素。
其中，在本申请实施例中，对应一行像素单元20设置的红色色阻、绿色色阻以及蓝色色阻以任一排列组合重复排列。位于同一列的第一子像素电极21或第二子像素电极22对应的色阻202的颜色相同。
其中，RGB像素排列架构结构简单，工艺成熟，应用在本申请中，可以简化工艺制程，降低生产成本。
相应的，本申请还提供一种显示装置，显示装置包括阵列基板、源极驱动芯片和栅极驱动电路。源极驱动芯片用于提供数据电压至阵列基板。栅极驱动电路用于提供扫描信号至阵列基板。该阵列基板为上述任一实施例所述的阵列基板，具体可参阅上述内容，在此不再赘述。
此外，显示装置可以是智能手机、平板电脑、电子书阅读器、智能手表、摄像机、游戏机等，本申请对此不作限定。
具体的，请参阅图13，图13是本申请提供的显示装置的一种结构示意图。其中，显示装置2000包括液晶显示面板1000、栅极驱动电路500、源极驱动芯片300以及时序控制器400。
其中，液晶显示面板1000包括阵列基板。阵列基板包括多条扫描线11和多条数据线12。多条扫描线11沿第一方向Y排布。多条数据线12沿第二方向X排布。液晶显示面板1000包括多个子像素（图中未标示），每一子像素均与相应的扫描线11以及数据线12电连接。
时序控制器400可以响应于外部接收的控制信号生成用于控制栅极驱动电路500的扫描控制信号以及用于控制源极驱动芯片300的数据控制信号。例如，控制信号可以包括点时钟、数据使能信号、垂直同步信号和水平同步信号。时序控制器400可以将扫描控制信号供应给栅极驱动电路500，并且可以将数据控制信号供应给源极驱动芯片300。
栅极驱动电路500通过扫描线11传输扫描信号至液晶显示面板1000。在一些实施例中，栅极驱动电路500可以是独立设置的栅极芯片。在另一些实施例中，栅极驱动电路500可以是设置在阵列基板内的GOA（阵列基板栅极驱动技术），本申请对此不做具体限定。
源极驱动芯片300通过数据线12传输数据信号至液晶显示面板1000。在一些实施例中，源极驱动芯片300可以通过COF（Chip On Film，覆晶薄膜）绑定在阵列基板上，本申请对此不做具体限定。
本申请提供一种显示装置2000。显示装置2000包括液晶显示面板1000。在液晶显示面板1000的每一行像素单元中，设置第一子像素电极和第二子像素电极交替排布，在相邻两行像素单元中设置第一子像素电极交错设置或一一对应设置。并且设置每一第一子像素电极均与位于像素单元上方且邻近的一条扫描线电连接，每一第二子像素电极均与位于像素单元下方且邻近的一条扫描线电连接，使得每一行像素单元中的第一子像素电极和第二子像素电极与扫描线以及数据线之间的连接方式比较单一。从而能够减少第一子像素电极和第二子像素电极的连接类型，减小各子像素之间受到的干扰差异，进而减小各子像素之间的亮度差异，改善摇头纹问题。
以上对本申请提供的阵列基板、液晶显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    多条扫描线，多条所述扫描线沿第一方向排布；
    多条数据线，多条所述数据线沿第二方向排布，所述第二方向与所述第一方向交叉；
    多个像素单元，多个所述像素单元呈阵列排布，每一所述像素单元均包括第一子像素电极和第二子像素电极，所述第一子像素电极和所述第二子像素电极连接至同一条所述数据线；
    其中，相邻的两列所述像素单元之间均设有一条所述数据线，相邻的两行所述像素单元之间均设有两条所述扫描线；在每一行所述像素单元中，所述第一子像素电极和所述第二子像素电极交替排布，每一所述第一子像素电极均与所述像素单元所在行的上一级且邻近的一条所述扫描线电连接，每一所述第二子像素电极均与所述像素单元所在行的下一级且邻近的一条所述扫描线电连接。
  2. 根据权利要求1所述的阵列基板，其中，沿所述第一方向，位于相邻两行所述像素单元中的所述第一子像素电极交错设置，在同一列所述像素单元中，相邻的两个所述像素单元分别连接至相邻的两条所述数据线。
  3. 根据权利要求2所述的阵列基板，其中，在同一个所述像素单元中，所述第一子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
  4. 根据权利要求2所述的阵列基板，其中，在同一个所述像素单元中，所述第二子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
  5. 根据权利要求2所述的阵列基板，其中，在同一帧显示画面中，相邻两条所述数据线被配置为传输极性相反的数据电压。
  6. 根据权利要求2所述的阵列基板，其中，在同一帧显示画面中，每条所述数据线均被配置为传输极性相同的数据电压，在相邻两帧显示画面中，同一条所述数据线被配置为传输极性相反的数据电压。
  7. 根据权利要求1所述的阵列基板，其中，位于相邻两行所述像素单元中的所述第一子像素电极一一对应设置，且位于同一列的所述像素单元与同一条所述数据线电连接；
    其中，在每一所述像素单元中，所述第一子像素电极位于第二列，所述第二子像素电极位于第一列，或者所述第一子像素电极位于第一列，所述第二子像素电极位于第二列。
  8. 根据权利要求7所述的阵列基板，其中，沿所述第一方向，共用同一条所述数据线的相邻两个所述像素单元接收的数据电压的极性相反。
  9. 一种液晶显示面板，其包括相对设置的阵列基板和彩膜基板，所述阵列基板包括：
    多条扫描线，多条所述扫描线沿第一方向排布；
    多条数据线，多条所述数据线沿第二方向排布，所述第二方向与所述第一方向交叉；
    多个像素单元，多个所述像素单元呈阵列排布，每一所述像素单元均包括第一子像素电极和第二子像素电极，所述第一子像素电极和所述第二子像素电极连接至同一条所述数据线；
    其中，相邻的两列所述像素单元之间均设有一条所述数据线，相邻的两行所述像素单元之间均设有两条所述扫描线；在每一行所述像素单元中，所述第一子像素电极和所述第二子像素电极交替排布，每一所述第一子像素电极均与所述像素单元所在行的上一级且邻近的一条所述扫描线电连接，每一所述第二子像素电极均与所述像素单元所在行的下一级且邻近的一条所述扫描线电连接。
  10. 根据权利要求9所述的液晶显示面板，其中，所述彩膜基板包括多个色阻，所述多个色阻包括红色色阻、绿色色阻以及蓝色色阻；
    其中，每一所述色阻对应一所述第一子像素电极或一所述第二子像素电极设置，对应一行所述像素单元设置的所述红色色阻、所述绿色色阻以及所述蓝色色阻以任一排列组合重复排列，位于同一列的所述第一子像素电极或所述第二子像素电极对应的所述色阻的颜色相同。
  11. 根据权利要求9所述的液晶显示面板，其中，沿所述第一方向，位于相邻两行所述像素单元中的所述第一子像素电极交错设置，在同一列所述像素单元中，相邻的两个所述像素单元分别连接至相邻的两条所述数据线。
  12. 根据权利要求11所述的液晶显示面板，其中，在同一个所述像素单元中，所述第一子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
  13. 根据权利要求11所述的液晶显示面板，其中，在同一个所述像素单元中，所述第二子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
  14. 根据权利要求9所述的液晶显示面板，其中，位于相邻两行所述像素单元中的所述第一子像素电极一一对应设置，且位于同一列的所述像素单元与同一条所述数据线电连接；
    其中，在每一所述像素单元中，所述第一子像素电极位于第二列，所述第二子像素电极位于第一列，或者所述第一子像素电极位于第一列，所述第二子像素电极位于第二列。
  15. 一种显示装置，其中，所述显示装置包括液晶显示面板、源极驱动芯片和栅极驱动电路，所述源极驱动芯片用于提供数据电压至所述液晶显示面板，所述栅极驱动电路用于提供扫描信号至所述液晶显示面板，所述液晶显示面板包括阵列基板，所述阵列基板包括：
    多条扫描线，多条所述扫描线沿第一方向排布；
    多条数据线，多条所述数据线沿第二方向排布，所述第二方向与所述第一方向交叉；
    多个像素单元，多个所述像素单元呈阵列排布，每一所述像素单元均包括第一子像素电极和第二子像素电极，所述第一子像素电极和所述第二子像素电极连接至同一条所述数据线；
    其中，相邻的两列所述像素单元之间均设有一条所述数据线，相邻的两行所述像素单元之间均设有两条所述扫描线；在每一行所述像素单元中，所述第一子像素电极和所述第二子像素电极交替排布，每一所述第一子像素电极均与所述像素单元所在行的上一级且邻近的一条所述扫描线电连接，每一所述第二子像素电极均与所述像素单元所在行的下一级且邻近的一条所述扫描线电连接。
  16. 根据权利要求15所述的显示装置，其中，所述液晶显示面板包括与所述阵列基板相对设置的彩膜基板；
    所述彩膜基板包括多个色阻，所述多个色阻包括红色色阻、绿色色阻以及蓝色色阻；
    其中，每一所述色阻对应一所述第一子像素电极或一所述第二子像素电极设置，对应一行所述像素单元设置的所述红色色阻、所述绿色色阻以及所述蓝色色阻以任一排列组合重复排列，位于同一列的所述第一子像素电极或所述第二子像素电极对应的所述色阻的颜色相同。
  17. 根据权利要求15所述的显示装置，其中，沿所述第一方向，位于相邻两行所述像素单元中的所述第一子像素电极交错设置，在同一列所述像素单元中，相邻的两个所述像素单元分别连接至相邻的两条所述数据线。
  18. 根据权利要求17所述的显示装置，其中，在同一个所述像素单元中，所述第一子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
  19. 根据权利要求17所述的显示装置，其中，在同一个所述像素单元中，所述第二子像素电极更靠近同时连接所述第一子像素电极和所述第二子像素电极的所述数据线。
  20. 根据权利要求15所述的显示装置，其中，位于相邻两行所述像素单元中的所述第一子像素电极一一对应设置，且位于同一列的所述像素单元与同一条所述数据线电连接；
    其中，在每一所述像素单元中，所述第一子像素电极位于第二列，所述第二子像素电极位于第一列，或者所述第一子像素电极位于第一列，所述第二子像素电极位于第二列。
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