WO2023179713A1 - 显示基板 - Google Patents

显示基板 Download PDF

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Publication number
WO2023179713A1
WO2023179713A1 PCT/CN2023/083379 CN2023083379W WO2023179713A1 WO 2023179713 A1 WO2023179713 A1 WO 2023179713A1 CN 2023083379 W CN2023083379 W CN 2023083379W WO 2023179713 A1 WO2023179713 A1 WO 2023179713A1
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WO
WIPO (PCT)
Prior art keywords
substrate
base substrate
display
display area
orthographic projection
Prior art date
Application number
PCT/CN2023/083379
Other languages
English (en)
French (fr)
Other versions
WO2023179713A9 (zh
Inventor
代俊秀
周洋
白露
屈忆
刘松
张波
吴董杰
张锴
胡明
胡文博
王刚
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023179713A1 publication Critical patent/WO2023179713A1/zh
Publication of WO2023179713A9 publication Critical patent/WO2023179713A9/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to a display substrate.
  • OLED Organic Light Emitting Diode
  • OLED display devices have a series of advantages such as self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost, and have become a new generation of display devices.
  • OLED display devices are developing towards narrow bezels and large screens to meet the needs of users.
  • At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a first barrier dam, a first power signal line, and a crack detection circuit.
  • a first barrier dam is disposed on the substrate substrate and in the peripheral area, and at least partially surrounds the display area; a first power signal line is disposed between the substrate substrate and the first barrier dam.
  • a crack detection circuit is disposed between the base substrate and the first barrier dam, and is disposed in the peripheral area and at least partially surrounds the display area, wherein the An orthographic projection of the crack detection circuit on the base substrate at least partially overlaps an orthographic projection of the first barrier dam on the base substrate.
  • the crack detection circuit includes a first wiring portion disposed on the base substrate and a remote control portion disposed on the first wiring portion.
  • the second wiring part on one side of the base substrate, the second wiring part is electrically connected to the first wiring part through a via hole, the second wiring part is on the side of the base substrate.
  • the orthographic projection is located inside the orthographic projection of the first barrier dam on the base substrate.
  • the second wiring portion and the first power signal line are arranged on the same layer.
  • the second wiring portion is provided on a side of the first power signal line away from the display area, and the first wiring portion is provided on the side of the first power signal line away from the display area.
  • the first wiring part includes a plurality of first wirings, and the boundary of the first barrier dam away from the display area is on the substrate substrate.
  • the orthographic projection of the plurality of first traces on the base substrate is located inside, or the orthographic projection of the boundary of the first barrier dam away from the display area on the base substrate is located on the base substrate.
  • the spacing between two adjacent first traces among the plurality of first traces is within the orthographic projection on the substrate.
  • the orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is located on one of the plurality of first traces.
  • the middle part of the orthographic projection of the first trace on the base substrate, or the orthographic projection of the boundary of the first barrier dam away from the display area on the base substrate is in the middle of the orthogonal projection of the first traces.
  • the spacing between two adjacent first traces among the lines is inside the orthographic projection on the substrate, and the distance between the two adjacent first traces and the first trace away from the display area is between The distance of the orthographic projection on the substrate is greater than or equal to 3 microns.
  • the display area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit that drives the light-emitting device, and the pixel driving circuit
  • the circuit includes a thin film transistor and a storage capacitor.
  • the thin film transistor includes a gate electrode provided on the base substrate and a source and drain electrode provided on a side of the gate electrode away from the base substrate.
  • the storage capacitor includes a first capacitor electrode disposed on the base substrate and a second capacitor electrode disposed on a side of the first capacitor electrode away from the base substrate; the gate electrode and the first capacitor electrode are in the same layer.
  • the second capacitor electrode and the first wiring part are arranged on the same layer, and the source and drain electrodes are arranged on the same layer as the second wiring part.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a crack blocking dam, wherein the crack blocking dam is disposed on a side of the crack detection circuit away from the display area.
  • the peripheral area includes an inorganic layer
  • the crack barrier dam includes a groove disposed in the inorganic layer
  • the display area further includes a planarization layer disposed on a side of the pixel driving circuit away from the base substrate, and a planarization layer disposed on a side of the planarization layer away from the base substrate.
  • the pixel definition layer on one side of the base substrate and the spacer provided on the side of the pixel definition layer away from the base substrate, the first barrier dam and the planarization layer, the pixel definition layer and At least one of the spacers is arranged on the same layer.
  • the orthographic projection of at least part of the boundary of the crack detection circuit away from the display area on the base substrate is located on the first barrier dam on the substrate. Orthographic projection interior on base substrate.
  • the orthographic projection of the crack detection circuit on the base substrate at least partially overlaps the orthographic projection of the first power signal line on the base substrate.
  • the first power signal line is provided on a side of the crack detection circuit away from the base substrate.
  • the peripheral area further includes at least one auxiliary line
  • the first power signal line is electrically connected to the at least one auxiliary line through a via hole to connect to the at least one auxiliary line.
  • At least one of the above auxiliary traces should be connected in parallel.
  • the display area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit that drives the light-emitting device, and the pixel driving circuit
  • the circuit includes a thin film transistor and a storage capacitor.
  • the thin film transistor includes a gate electrode provided on the base substrate and a source and drain electrode provided on a side of the gate electrode away from the base substrate.
  • the storage capacitor includes a first capacitor electrode disposed on the base substrate and a second capacitor electrode disposed on a side of the first capacitor electrode away from the base substrate; the gate electrode and the first capacitor electrode are in the same layer It is arranged that the second capacitor electrode is arranged on the same layer as the at least one auxiliary wiring, and the source-drain electrode is arranged on the same layer as the first power signal line.
  • the crack detection circuit and the at least one auxiliary trace are arranged on the same layer.
  • the thin film transistor further includes an active layer, and the active layer is disposed on a side of the gate close to the base substrate, and the display area It also includes a light-shielding pattern, the light-shielding pattern being disposed between the active layer and the base substrate.
  • the orthographic projection of the active layer on the base substrate and the orthographic projection of the light-shielding pattern on the base substrate at least partially overlap.
  • the crack detection circuit and the light-shielding pattern are arranged in the same layer.
  • the orthographic projection of the crack detection circuit on the base substrate at least partially intersects the orthographic projection of the at least one auxiliary trace on the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a crack barrier dam disposed in the peripheral area and on a side of the first barrier dam close to the display area, at least partially surrounding the display In a region, the orthographic projection of the crack barrier on the base substrate at least partially overlaps the orthographic projection of the first power signal line on the base substrate.
  • the crack barrier dam is provided in the same layer as at least one of the gate electrode and the second capacitor electrode.
  • the crack barrier dam in the display substrate provided by at least one embodiment of the present disclosure, includes a plurality of sub-crack barrier dams arranged at intervals.
  • the length of each of the plurality of sub-crack barrier dams is less than 50 mm.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a second barrier dam, disposed on a side of the first barrier dam close to the display area, and disposed on a side of the crack barrier dam away from the One side of the base substrate, wherein an orthographic projection of the crack barrier dam on the base substrate at least partially overlaps an orthographic projection of the second barrier dam on the base substrate.
  • the first power signal line is configured to provide a first power signal to the display area
  • the display substrate further includes a second power signal line
  • the second The power signal line is configured to provide a second power signal to the display area, the potential of the second power signal being higher than the potential of the first power signal.
  • Figure 1 is a schematic diagram showing the arrangement of circuits and structures in the peripheral area of a display substrate
  • Figure 2 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • Figure 3 is an enlarged schematic diagram of the display substrate in the dotted frame area in Figure 2;
  • Figure 4 is a schematic cross-sectional view of the display substrate in Figure 3 along line A-A;
  • FIG. 5A is a partial cross-sectional schematic diagram of a sub-pixel in the display area of the display substrate provided by at least one embodiment of the present disclosure
  • 5B is another partial cross-sectional schematic diagram of a sub-pixel in the display area of the display substrate provided by at least one embodiment of the present disclosure
  • Figure 6A is another enlarged schematic diagram of the display substrate in Figure 2 in the dotted frame area;
  • Figure 6B is a schematic cross-sectional view of the display substrate in Figure 6A along line B-B;
  • Figure 7A is another enlarged schematic diagram of the display substrate in Figure 2 in the dotted frame area;
  • Figure 7B is a schematic cross-sectional view of the display substrate in Figure 7A along line D-D;
  • Figure 8A is another enlarged schematic diagram of the display substrate in Figure 2 in the dotted frame area;
  • Figure 8B is a schematic cross-sectional view of the display substrate in Figure 8A along line E-E;
  • Figure 9 is a schematic diagram of a scanning electron microscope showing that the packaging layer in the substrate is broken next to the first trace;
  • Figure 10 is a schematic plan view of another display substrate provided by at least one embodiment of the present disclosure.
  • Figure 11 is a schematic cross-sectional view of the display substrate in Figure 10 along line C-C;
  • Figure 12 is another schematic cross-sectional view of the display substrate in Figure 10 along line C-C;
  • Figure 13 is another partial cross-sectional schematic diagram of a sub-pixel in the display area of the display substrate provided by at least one embodiment of the present disclosure
  • Figure 14 is another schematic cross-sectional view of the display substrate in Figure 10 along line C-C;
  • Figure 15 is an enlarged schematic diagram of the display substrate in the dotted frame area in Figure 10;
  • Figure 16 is another schematic cross-sectional view of the display substrate in Figure 10 along line C-C;
  • FIG. 17 is a schematic diagram of the arrangement of circuits and structures in the peripheral area of a display substrate according to at least one embodiment of the present disclosure.
  • a crack detection circuit (Panel Crack Detection, PCD) is usually provided to detect whether there are cracks in the display panel.
  • the circuit pattern in the crack inspection circuit needs to be protected by a protective layer.
  • the organic protective layer usually needs to be covered with an inorganic layer to avoid undesirable phenomena such as water absorption and expansion of the organic protective layer.
  • the thickness of the inorganic layer is often insufficient. Where there are slits, the inorganic layer is prone to breakage, causing the organic protective layer to be exposed, which in turn causes water expansion and packaging failure.
  • it is necessary to increase the steps of depositing the inorganic material and preparing the inorganic protective layer that is, one more preparation process, which will reduce the production capacity.
  • FIG. 1 shows a frame of a display substrate, that is, a schematic structural arrangement diagram of a non-display area surrounding a display area.
  • the non-display area is provided with an edge cutting area A, a crack blocking area B, a power wiring area C, a circuit setting area D, and a connection area E.
  • the edge cutting area A is an area reserved for the cutting operation of forming a single display substrate by cutting the master.
  • the width of this area is usually about 110 microns;
  • the crack blocking area B is provided with a crack blocking structure and a crack inspection circuit to cope with the cutting process.
  • the cutting operation when forming a single display substrate may cause the formation of cracks in the display substrate.
  • the width of this area is usually about 100 microns;
  • the power supply wiring area C is, for example, a power supply that transmits low-level voltage signals to multiple sub-pixels in the display area.
  • the bus setting area, the width of this area is usually about 150 microns;
  • the circuit setting area D is the GOA (Gate on Array) driver that provides driving signals to the pixel driving circuits of multiple sub-pixels in the display area.
  • connection area E is the area where the structures in the peripheral area (such as wiring and circuits) are connected to the structure of the display area (such as wiring and circuits), the width of this area Typically about 90 microns.
  • the sum of the widths of each of the above areas is the frame width of the display substrate, which is about 850 microns.
  • This width is basically the narrowest width achieved through precision design on the basis of realizing the basic functions of the circuits and functional structures of each area. The width is difficult to reduce further, thus posing a greater challenge for technicians to further narrow the bezel.
  • At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a first barrier dam, a first power signal line and a crack detection circuit,
  • the first barrier dam is disposed on the substrate substrate and in the peripheral area, and at least partially surrounds the display area; the first power signal line is disposed between the substrate substrate and the first barrier dam, and extends at least in the peripheral area.
  • the orthographic projection of at least part of the boundary of the power signal line away from the display area on the substrate substrate is located inside the orthographic projection of the first barrier dam on the substrate substrate;
  • the crack detection circuit is disposed between the substrate substrate and the first barrier dam, And it is arranged in the peripheral area and at least partially surrounds the display area, and the orthographic projection of the crack detection circuit on the base substrate at least partially overlaps the orthographic projection of the first barrier dam on the base substrate.
  • the frame of the display substrate can be further narrowed, for example, the frame can be reduced to 720 Below microns, for example, an extremely narrow frame design of 600 microns or 650 microns can be achieved; and, while the first barrier dam achieves a blocking function, it can also protect the crack inspection circuit and facilitate the subsequent packaging process, improving Encapsulates reliability.
  • the display substrate of the present disclosure will be described below through several specific embodiments.
  • FIGS. 2 to 4 show a schematic plan view of the display substrate.
  • Figure 3 shows an enlarged schematic view of the display substrate in the dotted frame area in Figure 2.
  • Figure 4 shows a schematic diagram of Figure 3 A schematic cross-sectional view of the display substrate along line A-A.
  • the display substrate has a display area AA and a peripheral area NA at least partially surrounding the display area AA, and includes a base substrate 110 , a first barrier dam D1 , a first power signal line VSS and a crack detection Circuit PCD.
  • the first barrier dam D1 is disposed on the substrate substrate 110 and is disposed in the peripheral area NA, and at least partially surrounds the display area AA, for example, surrounding the display area AA around the display area AA, so as to Material formed (eg inkjet printing) in the display area AA is blocked from flowing into the peripheral area NA.
  • the first power signal line VSS is disposed between the substrate substrate 110 and the first barrier dam D1 and extends at least in the peripheral area NA, for example, in some embodiments, extends from the display area AA to the peripheral area NA.
  • the orthographic projection of at least part of the boundary B2 of the first power signal line VSS away from the display area AA on the base substrate 110 is located inside the orthographic projection of the first barrier dam D1 on the base substrate 110 . Therefore, the first barrier dam D1 covers at least part of the boundary B2 of the first power signal line VSS away from the display area AA to protect the first power signal line VSS.
  • the crack detection circuit PCD is disposed between the substrate substrate 110 and the first barrier dam D1, and is disposed in the peripheral area NA, and at least partially surrounds the display area AA, for example, surrounding the display area on the left, upper and right sides of the display area AA. In the area AA, the crack detection circuit PCD can detect whether the display substrate has defects such as breakage due to cutting.
  • the orthographic projection of the crack detection circuit PCD on the base substrate 110 at least partially overlaps the orthographic projection of the first barrier dam D1 on the base substrate 110 , so that the first barrier dam D1 can also protect at least part of the crack detection circuit PCD.
  • An additional protective layer needs to be formed to protect the crack detection circuit PCD, thereby simplifying the preparation process of the display substrate.
  • the above arrangement can also shorten the distance between the first barrier dam D1 and the cutting line CL (refer to FIG. 6A, FIG. 7A, and FIG. 8A) to further narrow the frame.
  • the crack detection circuit PCD includes a first wiring portion P1 provided on the base substrate 110 and a second wiring portion provided on a side of the first wiring portion P1 away from the base substrate 110 P2, the second wiring part P2 is electrically connected to the first wiring part P1 through the via V, and the orthographic projection of the second wiring part P2 on the base substrate 110 is located at the position of the first barrier dam D1 on the base substrate 110 Orthographic projection interior.
  • the first barrier dam D1 may be disposed directly above the second wiring part P2 to contact the second wiring part P2 to achieve protection.
  • the crack detection circuit PCD by arranging the crack detection circuit PCD to include a first trace portion P1 and a second trace portion P2 that are electrically connected and located on different conductive layers, long traces (long-distance traces) can be prevented. ) appears electrostatic interference and other undesirable phenomena, thereby achieving the technical effect of anti-static.
  • the second wiring part P2 and the first power signal line VSS are arranged on the same layer to simplify the preparation process of the display substrate.
  • “same layer arrangement” means that two functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate. That is, in the preparation process, the two functional layers or structural layers are formed on the same layer.
  • the layers or structural layers can be formed from the same material layer and can be formed into the desired patterns and structures by the same patterning process.
  • the second wiring portion P2 is provided on a side of the first power signal line VSS away from the display area AA, and the first wiring portion P1 is provided on a side of the second wiring portion P2 away from the display area AA. side. That is, the first wiring part P1, the second wiring part P2 and the first power signal line VSS are arranged in sequence in a direction close to the display substrate AA.
  • the first trace portion P1 includes a plurality of first traces 111 (ie, the number of first traces arranged side by side on one side of the display substrate), such as two to six first traces. 111.
  • the second wiring part P2 includes at least one second wiring 112 (that is, the number of second wirings arranged side by side on the display substrate), for example, one to three second wirings 112. The embodiments of the present disclosure do not specifically limit this.
  • the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 is located inside the orthographic projection of the plurality of first traces 111 on the substrate, that is, the orthogonal projection of the first barrier dam D1
  • the boundary B1 away from the display area AA is located directly above any one of the plurality of first traces 111; or, in other embodiments, the boundary B1 away from the display area AA of the first barrier dam D1 is on the substrate 110
  • the orthographic projection is located inside the orthographic projection of the adjacent two first traces 111 among the plurality of first traces 111 on the base substrate 110 , that is, the boundary B1 of the first barrier dam D1 away from the display area AA. Located directly above the intervals between the plurality of first traces 111 .
  • the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 is located on one of the plurality of first traces 111 on the substrate.
  • the boundary B1 of the first barrier dam D1 away from the display area AA is located in the positive direction of the middle part of a first trace 111; or, in other embodiments, As shown in FIG. 3 , the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 is between two adjacent first traces 111 among the plurality of first traces 111 .
  • the distance L1 between the orthographic projection on the base substrate 110 and the front projection of the first line 111 away from the display area AA among the two adjacent first lines 111 on the base substrate 110 is greater than or equal to 3 microns, to have sufficient distance from the first trace 111 .
  • FIG. 7A also shows the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 and the two adjacent first traces 111 among the plurality of first traces 111 .
  • the distance L1 is greater than or equal to 3 from the orthographic projection on the base substrate 110 of the first trace 111 of the two adjacent first traces 111 that is far away from the display area AA.
  • FIG. 7B is a schematic cross-sectional view of the display substrate in FIG. 7A along line D-D.
  • the inorganic encapsulation layer formed above the first barrier dam D1 is The boundary position of the trace 111 is broken, for example, when the boundary B1 of the first barrier dam D1 away from the display area AA and the orthographic projection on the substrate 110 are two adjacent first traces 111
  • the spacing of the traces 111 is within the orthographic projection on the base substrate 110 and is the distance from the orthographic projection of the first trace 111 away from the display area AA among the two adjacent first traces 111 on the base substrate 110
  • L1 is close, for example, less than 3 microns, as shown in Figure 9, the first inorganic encapsulation layer 1051 (described in detail later) formed above the first barrier dam D1 is prone to breakage next to the first trace 111, thus affecting the display.
  • the encapsulation effect of the substrate Through the above settings of the embodiment of the present disclosure, the risk of breakage of the first inorganic encapsulation layer 1051 can be fully avoided, and the encapsulation effect of the
  • the crack detection circuit PCD may include a circuit that uses two principles to detect whether the display substrate is broken, namely, a bright line detection circuit PCD1 and a resistance detection circuit PCD2.
  • the bright line detection circuit PCD1 can be connected to some sub-pixels through the bright line detection data line PD, and detects whether the bright line detection circuit PCD1 is broken by detecting whether the sub-pixels can be lit, and then infers whether the display substrate is broken.
  • the resistance detection circuit PCD2 includes, for example, two ends. The detection circuit detects the resistance level of the resistance detection circuit PCD2 to determine whether the resistance detection circuit PCD2 is broken, and then to infer whether the display substrate is broken.
  • the bright line detection circuit PCD1 and the resistance detection circuit PCD2 can be connected to the circuit board FPC, and the detection process is controlled through the circuit board FPC.
  • the display area AA includes a plurality of sub-pixels S, each of the plurality of sub-pixels S includes a light-emitting device EN and a pixel driving circuit that drives the light-emitting device EM.
  • the pixel driving circuit may include a plurality of thin film transistors and storage capacitors, and may be formed, for example, as 2T1C (that is, including two thin film transistors and one storage capacitor), 7T1C (that is, as including seven thin film transistors and one storage capacitor), or 8T2C (that is, as including eight thin film transistors and one storage capacitor).
  • a thin film transistor and two storage capacitors) and other structures are not limit the specific form of the pixel driving circuit.
  • FIG. 5A shows a partial cross-sectional schematic diagram of a sub-pixel S.
  • the pixel driving circuit includes a thin film transistor T and a storage capacitor C.
  • the thin film transistor C includes an active layer 1021 disposed on the base substrate 110 , a gate electrode 1022 , and source and drain electrodes 1023 and 1024 disposed on a side of the gate electrode 1022 away from the base substrate 110 .
  • the storage capacitor C includes a first capacitor electrode 1031 disposed on the base substrate 110 and a second capacitor electrode 1032 disposed on a side of the first capacitor electrode 1031 away from the base substrate 110.
  • the gate electrode 1022 and the first capacitor electrode 1031 are the same.
  • the second capacitor electrode 1032 is arranged on the same layer as the first wiring part P1, the source and drain electrodes 1023 and 1024, the first power signal line VSS and the second wiring part P2 are arranged on the same layer. This simplifies the preparation of display substrates Craftsmanship.
  • the light-emitting device EM includes a first electrode layer 1041 (eg, an anode layer), a luminescent material layer 1042, and a second electrode layer 1043 (eg, a cathode layer).
  • the first electrode layer 1041 is electrically connected to the pixel driving circuit (for example, the source and drain electrodes 1023 of the thin film transistor T), and the second electrode layer 1043 is electrically connected to the first power signal line VSS.
  • the luminescent material layer 1042 can emit light.
  • FIG. 6A shows another schematic plan view of the display substrate in FIG. 2 in the dotted frame area
  • FIG. 6B is a schematic cross-sectional view of the display substrate in FIG. 6A along line B-B.
  • the display substrate may further include a crack barrier D3 , for example, a plurality of crack barrier dams D3 .
  • Five crack barrier dams are shown in FIGS. 6A and 6B as an example.
  • the barrier dam D3 is disposed on a side of the crack detection circuit PCD away from the display area AA, and at least partially surrounds the display area AA.
  • the crack blocking dam D3 can block the formation and propagation of cracks, such as blocking cracks from forming when cutting the display substrate or blocking already formed cracks from extending to the display area AA, thereby protecting the display substrate in the peripheral area NA.
  • the peripheral area NA includes an inorganic layer IN
  • the crack barrier D3 includes a groove GV disposed in the inorganic layer IN. Since most cracks are generated in the inorganic layer due to stress and spread along the inorganic layer, etching part of the inorganic layer, for example, forming multiple inorganic grooves, can effectively block the expansion of micro-cracks to the display area AA.
  • the inorganic layer IN may be provided in the same layer as at least one (eg, all) of the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 .
  • the crack barrier D3 is covered with a partial planarization layer 1016 to protect the crack barrier D3.
  • first gate insulating layer 1014A, the second gate insulating layer 1014B, the interlayer insulating layer 1015 and the barrier are not shown respectively in FIGS. 4, 6B and the following FIGS. 7B and 8B.
  • Layer 1112, buffer layer 1013, base substrate 110 and other structures, the stacking relationship of these structures can be seen in Figure 5A and Figure 5B.
  • the display substrate may further include a second power supply line VDD, a first power signal line VSS configured to provide a first power signal to the display area AA, and a second power signal line VDD. It is configured to provide a second power signal to the display area AA, the potential of the second power signal is higher than the potential of the first power signal, that is, the second power signal is a high-level signal and the first power signal is a low-level signal.
  • the peripheral area NA of the display substrate may also be Including the wiring fan-out area F1/F2, the bending area B and the integrated circuit IC, etc.
  • the wiring fan-out areas F1/F2 include multiple connecting wires to connect multiple lead lines (such as data lines) in the display area AA to the integrated circuit IC.
  • the bending area B has better flexibility to connect the integrated circuits.
  • the circuit IC and circuit board FPC are bent to the non-display side of the display substrate to achieve a narrow frame design.
  • the display area further includes a planarization layer 1016 disposed on a side of the pixel driving circuit away from the substrate 110 , and a planarization layer 1016 disposed on a side away from the substrate.
  • the planarization layer 1016 may function to planarize the pixel driving circuit.
  • the pixel defining layer 1017 includes a plurality of sub-pixel openings PO that expose the first electrode layers 1041 of the plurality of light-emitting devices EM to define light-emitting areas of the sub-pixels.
  • the spacer 1018 can function as a spacer and a support, for example, supporting devices such as masks that may be used in the preparation process.
  • the first barrier dam D1 may be disposed in the same layer as at least one of the planarization layer 1016, the pixel definition layer 1017, and the spacer 1018.
  • the first barrier dam D1 may include three sub-layers D11/D12/D13. The three sub-layers D11/D12/D13 are respectively connected with the planarization layer 1016 and the pixel definition layer 1017. It is arranged on the same layer as the spacer 1018 to simplify the preparation process of the display substrate.
  • the display substrate further includes a connection electrode CEL disposed on a side of the pixel driving circuit away from the substrate substrate.
  • the connection electrode CEL connects the pixel driving circuit with the first electrode layer 1041 Electrical connection, at this time, another planarization layer 1019 is provided on the side of the connection electrode CEL away from the base substrate.
  • the first barrier dam D1 may be disposed in the same layer as at least one of the planarization layer 1016, the other planarization layer 1019, the pixel definition layer 1017 and the spacer 1018.
  • the pixel definition layer 1017 and the spacer 1018 can be formed through the same patterning process using a gray tone mask to simplify the preparation process of the display substrate.
  • a gray tone mask can also be used to form the portions with different thicknesses through the same patterning process.
  • the display substrate further includes a second barrier dam D2.
  • the second barrier dam D2 is disposed on a side of the first barrier dam D1 close to the display area AA and at least partially surrounds the display area AA.
  • the second barrier dam D2 may also be provided in the same layer as at least one of the planarization layer 1016/1019, the pixel definition layer 1017, and the spacer 1018.
  • the height of the first barrier dam D1 relative to the base substrate 110 is greater than the height of the second barrier dam D2 relative to the base substrate 110 .
  • the second barrier dam D2 may include two sub-layers, which are respectively connected to two of the planarization layer 1016/1019, the pixel definition layer 1017 and the spacer 1018. are arranged on the same layer to simplify the preparation process of the display substrate.
  • the second barrier dam D2 includes two sub-layers D21 and D22.
  • the sub-layer D21 is arranged in the same layer as the planarization layer 1016 or the planarization layer 1019, and the sub-layer D22 is arranged in the same layer as the pixel definition layer 1017 or the spacer 1018.
  • the first barrier dam D1 and the second barrier dam D2 can play multiple blocking roles to improve the blocking effect.
  • the crack detection circuit PCD may only have the first wiring part P1.
  • the number (length) of the first wiring parts 111 included in the first wiring part P1 may be appropriately reduced to Avoid electrostatic interference.
  • FIG. 8A shows the case where the crack detection circuit PCD only includes the first wiring part P1
  • FIG. 8B is a schematic cross-sectional view of the display substrate along line E-E in FIG. 8A. As shown in FIGS.
  • the crack detection circuit PCD only includes the first wiring part P1 and does not include the second wiring part P2, and the first wiring part P1 includes four first wirings 111 , the four first wirings 111
  • the trace 111 can also use bright line detection and/or resistance detection to implement the crack detection function. This technical solution can further shorten the distance between the first barrier dam D1 and the cutting line CL and narrow the frame.
  • the display substrate may further include a barrier layer 1112 and a buffer layer 1013 disposed on the base substrate 110 .
  • the barrier layer 1112 and the buffer layer 1013 may prevent impurities in the base substrate 110 from entering. multiple functional layers on the display substrate 110, thereby playing a protective role.
  • the barrier layer 1112 and the buffer layer 1013 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the display substrate may further include a first gate insulating layer 1014A disposed on a side of the active layer 1021 away from the base substrate 110 , and a first gate insulating layer 1014A disposed on the gate electrode 1022 and the first capacitor electrode 1031 .
  • the second gate insulating layer 1014B on the side away from the base substrate 110 and the interlayer insulating layer 1015 provided on the side of the second capacitor electrode 1032 away from the base substrate 110 .
  • the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the display substrate may also include an encapsulation layer EN disposed on a side of the light-emitting device EM away from the substrate substrate 110 .
  • the encapsulation layer EN may be a composite encapsulation layer, including the first inorganic encapsulation layer 1051 , the first organic encapsulation layer 1052 and the second inorganic Encapsulation layer 1053.
  • the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the first organic encapsulation layer 1052 may be made of organic insulating materials such as resin and polyimide.
  • the substrate substrate 110 can be a flexible substrate such as polyimide
  • the gate 1022 can be a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc.
  • an alloy material for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium/aluminum/titanium or other multi-layer metal layer structure.
  • the first source and drain electrodes 1023 and 1024 can be made of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) and other metal materials or alloy materials, for example, formed into a single-layer metal layer structure or Multi-layer metal layer structures, such as titanium/aluminum/titanium and other multi-layer metal layer structures.
  • the materials of the first capacitor electrode 1031 and the second capacitor electrode 1032 include metals or alloy materials such as aluminum, titanium, cobalt, and copper.
  • the active layer 1021 may be made of materials such as polysilicon and metal oxide.
  • the planarization layer 1016, the pixel definition layer 1017, the spacer layer 1018, and the first organic encapsulation layer 1052 of the encapsulation layer EN may use organic insulating materials such as polyimide and resin.
  • the second motor layer 1043 of the light emitting device EM may be formed entirely on the display substrate, thus extending from the display area to the peripheral area NA, and the peripheral area
  • the area NA may also have an electrode material layer 1041A and a luminescent material 1042A, which are respectively provided in the same layer as the first electrode layer 1041 and the luminescent material layer 1042 of the light-emitting device EM.
  • a gate scanning driving circuit GOA is also provided in the peripheral area NA.
  • the gate scanning driving circuit GOA also includes structures such as thin film transistors and storage capacitors. These structures can be combined with the thin film transistors T and storage capacitors C of the pixel driving circuit in the display area AA. Same structure and same layer settings.
  • the peripheral area NA may also include some traces W, and these traces W may be arranged on the same layer as the connection electrode CEL.
  • the display substrate may also include other structures besides the above-mentioned structures.
  • the display substrate may also include other structures besides the above-mentioned structures.
  • other structures please refer to related technologies, which will not be described again here.
  • each thin film transistor may be a P-type thin film transistor or an N-type thin film transistor, and the structure may be a bottom gate type, a top gate type, or a double gate type.
  • the structures shown in the drawings are only exemplary. , this disclosure The embodiment does not limit the specific form of each thin film transistor.
  • FIG. 10 shows a schematic plan view of another display substrate provided by at least one embodiment of the present disclosure, which mainly shows the arrangement of the crack detection circuit PCD.
  • FIG. 11 shows the display panel in FIG. 10 along line C-C. Cross-sectional diagram.
  • the display substrate has a display area AA and a peripheral area NA at least partially surrounding the display area AA, and includes a base substrate 110 , a first barrier dam D1 , a first power signal line VSS and a crack detection Circuit PCD.
  • the first barrier dam D1 is disposed on the base substrate 110 and in the peripheral area NA, and at least partially surrounds the display area AA to block, for example, materials formed in the display area AA from flowing into the peripheral area NA.
  • the first power signal line VSS is disposed between the substrate substrate 110 and the first barrier dam D1 and extends at least in the peripheral area NA, for example, in some embodiments, extends from the display area AA to the peripheral area NA.
  • the orthographic projection of at least part of the boundary B2 of the first power signal line VSS away from the display area AA on the base substrate 110 is located inside the orthographic projection of the first barrier dam D1 on the base substrate 110 . Therefore, the first barrier dam D1 covers at least part of the boundary B2 of the first power signal line VSS away from the display area AA.
  • the crack detection circuit PCD is disposed between the base substrate 110 and the first barrier dam D1 and is disposed in the peripheral area NA and at least partially surrounds the display area AA.
  • the crack detection circuit PCD can detect whether the display substrate has cracks or other undesirable phenomena.
  • the orthographic projection of the crack detection circuit PCD on the base substrate 110 at least partially overlaps the orthographic projection of the first barrier dam D1 on the base substrate 110 .
  • the orthographic projection of at least part of the boundary B3 of the crack detection circuit PCD away from the display area AA on the substrate 110 is located inside the orthographic projection of the first barrier dam D1 on the substrate 110 . That is, the overall structure of the crack detection circuit PCD is located on the side of the first barrier dam D1 away from the boundary B1 of the display area AA and close to the display area AA.
  • the crack detection circuit PCD includes a first part PCD3 and a second part PCD4.
  • the first part PCD3 and the second part PCD4 may be connected end-to-end to form a detection circuit, or the first part PCD3 and the second part PCD4 may be connected end-to-end to form a detection circuit.
  • the second part PCD4 can also be two detection circuits respectively.
  • the second part PCD4 is located on a side of the first part PCD3 close to the display area AA.
  • the orthographic projection of the first portion PCD3 on the base substrate 110 is located inside the orthographic projection of the first barrier dam D1 on the base substrate 110 .
  • the second part PCD4 is located on a side of the first barrier dam D1 close to the display area AA.
  • the front projection of the crack detection circuit PCD on the base substrate 110 The shadow at least partially overlaps with the orthographic projection of the first power signal line VSS on the base substrate 110 . Therefore, the crack detection circuit PCD and the first power signal line VSS occupy substantially the same space on the base substrate 110, so as to fully utilize the layout space and facilitate narrow frame design.
  • the first power signal line VSS is disposed on a side of the crack detection circuit PCD away from the base substrate 110 .
  • the display area AA includes a plurality of sub-pixels S, each of the plurality of sub-pixels S including a light-emitting device EN and a pixel driving circuit that drives the light-emitting device EM.
  • the display area AA includes A plurality of sub-pixels S.
  • Each of the plurality of sub-pixels S includes a light-emitting device EM and a pixel driving circuit that drives the light-emitting device EM.
  • the pixel driving circuit includes a thin film transistor T and a storage capacitor C.
  • the thin film transistor T is provided on the substrate 110
  • the gate electrode 1022 and the source and drain electrodes 1023 and 1024 are provided on the side of the gate electrode 1022 away from the base substrate 110 .
  • the storage capacitor C includes a first capacitor electrode 1031 disposed on the base substrate 110 and a second capacitor electrode 1032 disposed on a side of the first capacitor electrode 1031 away from the base substrate 110.
  • the gate electrode 1022 and the first capacitor electrode 1031 are the same. Layer settings. For other structures of the light-emitting device EM and the pixel driving circuit, reference can be made to FIG. 5A and FIG. 5B and their descriptions, which will not be described again here.
  • the crack detection circuit PCD is placed on the same layer as the second capacitor electrode 1032, and the first power signal line VSS is placed on the same layer as the source and drain electrodes 1023 and 1024 to simplify the preparation process of the display substrate.
  • the light-emitting device EM is electrically connected to the pixel driving circuit through the connecting electrode CEL.
  • the display substrate further includes a first power signal line VSS disposed far away from the substrate substrate.
  • the wiring SG is, for example, provided in the same layer as the connection electrode CEL.
  • the electrode material layer 1041A is formed at the same time as the first electrode layer 1041, for example.
  • the material layer of the surrounding area NA is disposed far away from the substrate substrate.
  • the peripheral area NA also includes at least one auxiliary wire AL, such as a plurality of auxiliary wires AL (five auxiliary wires AL are shown in the figure as an example), the first power supply
  • the signal line VSS is electrically connected to at least one auxiliary line AL through the via V2 so as to be connected in parallel with the at least one auxiliary line AL.
  • the auxiliary line AL is provided on the same layer as the crack detection circuit PCD and the second capacitor electrode 1032 to simplify the preparation process of the display substrate.
  • the thin film transistor T further includes an active layer 1021.
  • the active layer 1021 is disposed on a side of the gate 1022 close to the base substrate 110.
  • the display area AA also includes a light-shielding pattern SH.
  • the light-shielding pattern SH is disposed between the active layer 1021 and the base substrate 110.
  • the active layer The orthographic projection of 1021 on the base substrate 110 and the orthographic projection of the light shielding pattern SH on the base substrate 110 at least partially overlap. Therefore, the light-shielding pattern SH can shield the active layer 1021 from light, preventing light from irradiating the active layer 1021 and affecting the normal operation of the thin film transistor T.
  • the crack detection circuit PCD can be placed on the same layer as the light shielding pattern SH to simplify the preparation process of the display substrate.
  • the embodiment of FIG. 14 can be provided with two more auxiliary lines AL (seven auxiliary lines AL are shown as an example) to further reduce the resistance and transmission of the first power signal line VSS. signal voltage drop.
  • an auxiliary trace AL is provided above the first part PCD3 and the second part PCD4 of the crack detection circuit PCD.
  • the orthographic projection of the crack detection circuit PCD on the substrate 110 is in line with the above-mentioned auxiliary trace AL.
  • the orthographic projections on the base substrate 110 at least partially overlap, so that the crack detection circuit PCD and the above-mentioned auxiliary wiring AL occupy basically the same area on the display substrate, thereby making full use of the layout space of the display substrate and realizing a narrow frame design. .
  • the display substrate further includes a crack barrier D3, such as a plurality of crack barrier dams D3, and five crack barrier dams D3 are shown in the figure as an example.
  • the crack barrier dam D3 is disposed in the peripheral area NA and on a side of the first barrier dam D1 close to the display area AA, at least partially surrounding the display area AA.
  • the crack blocking dam D3 can block the formation and propagation of cracks, such as blocking cracks from forming when cutting the display substrate or blocking already formed cracks from extending to the display area AA, thereby protecting the display substrate in the peripheral area NA.
  • the orthographic projection of the crack barrier D3 on the base substrate 110 at least partially overlaps the orthographic projection of the first power signal line VSS on the base substrate 110 .
  • the orthographic projection of the crack barrier D3 on the base substrate 110 is located within the orthographic projection of the first power signal line VSS on the base substrate 110 .
  • the orthographic projection of the crack barrier dam D3 on the base substrate 110 is located between the orthographic projections of the first part PCD3 and the second part PCD4 of the crack detection circuit PCD on the base substrate 110 , that is, the crack detection circuit PCD may be at least partially Surrounding the crack barrier D3.
  • the crack barrier D3 includes two metal layers D31 and D32, which are respectively arranged in the same layer as the gate electrode 1022 and the second capacitor electrode 1032, To simplify the preparation process of the display substrate.
  • the crack barrier D3 includes two metal layers D31 and D32, the two metal layers D31 and D32 is provided in the same layer as the light shielding pattern SH and the gate electrode 1022 respectively to simplify the preparation process of the display substrate.
  • FIG. 15 shows an enlarged schematic diagram of the display substrate in the dotted box area in FIG. 10.
  • the crack barrier dam D3 in the extending direction of the crack barrier D3, that is, the vertical direction in the figure.
  • the crack barrier dam D3 includes a plurality of sub-crack barrier dams D3A arranged at intervals.
  • the inventor of the present disclosure found during research that if the length of the crack barrier D3 is too long, the crack barrier D3 will easily accumulate charges, resulting in a large electrostatic charge that cannot be exported. Therefore, the tip power generation phenomenon will easily occur at the end of the crack barrier D3. This in turn melts the metal, causing oxidation and corrosion of the metal.
  • the crack barrier dam D3 By arranging the crack barrier dam D3 to include a plurality of sub-crack barrier dams D3A arranged at intervals, the above undesirable phenomenon can be avoided.
  • the length L0 of each of the plurality of sub-crack barrier dams D3A is less than 50 mm, such as 47 mm, 45 mm, or 40 mm.
  • the crack barrier dam D3 will basically not cause oxidation corrosion and other adverse phenomena.
  • the display substrate further includes a second barrier dam D2, the second barrier dam D2 is disposed on a side of the first barrier dam D1 close to the display area AA, and Disposed on a side of the crack barrier dam D3 away from the base substrate 110 , the orthographic projection of the crack barrier dam D3 on the base substrate 110 at least partially overlaps with the orthographic projection of the second barrier dam D2 on the base substrate 110 .
  • the height of the first barrier dam D1 relative to the base substrate 110 is greater than the height of the second barrier dam D2 relative to the base substrate 110 , so the first barrier dam D1 and the second barrier dam D2 are at different positions and in different locations. It plays a double blocking role to a certain extent.
  • a planarization layer 1016 is provided below the first barrier dam D1 so as to have a higher height.
  • the first barrier dam D1 and the second barrier dam D2 may be disposed in the same layer as at least one of the pixel definition layer 1017 , the spacer 1018 , or other planarization layers (not shown) disposed on the planarization layer 1016 .
  • the display substrate may not include the second barrier dam D2 .
  • the number of crack barrier dams D3 may be appropriately reduced. Three crack barrier dams D3 are shown in FIG. 16 As an example, the area occupied by the crack barrier D3 is thus reduced to further narrow the frame.
  • the display substrate further includes a second power signal line VDD
  • the first power signal line VSS is configured to provide the first power signal to the display area AA
  • the second power signal line VDD is configured to provide a second power signal to the display area AA
  • the potential of the second power signal is higher than the potential of the first power signal, that is, the second power signal is configured to provide a high-level voltage.
  • the first power supply signal line VSS is electrically connected to the second electrode layer 1043 of the light emitting device EM to provide a low-level voltage.
  • FIG. 9 shows the circuit/structural arrangement of the non-display area NA in the display substrate provided by the embodiment of the present disclosure.
  • the non-display area NA in the direction close to the display area AA, includes an edge cutting area A1, a crack barrier and power wiring area B0, a circuit setting area C1, and a connection area D1.
  • the length of the edge cutting area A1 is about 110 microns; the width of the crack barrier and power trace area B0 is about 100 microns; the width of the circuit setting area C1 is about 350 microns; and the width of the connection area D1 is usually about 90 microns.
  • the total width of each of these regions is approximately 650 microns. It can be seen that through the above design of the embodiment of the present disclosure, the frame of the display substrate can be further narrowed, achieving an extremely narrow frame design effect.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

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Abstract

一种显示基板，该显示基板具有显示区域(AA)以及至少部分围绕显示区域(AA)的周边区域(NA)，且包括衬底基板(110)、第一阻隔坝(D1)、第一电源信号线(VSS)和裂纹检测电路(PCD)；第一阻隔坝(D1)设置在衬底基板(110)上且设置在周边区域(NA)，并至少部分围绕显示区域(AA)；第一电源信号线设置在衬底基板(110)与第一阻隔坝(D1)之间，且至少在周边区域(NA)延伸，第一电源信号线(VSS)的远离显示区域(AA)的至少部分边界在衬底基板(110)上的正投影位于第一阻隔坝(D1)在衬底基板(110)上的正投影内部；裂纹检测电路(PCD)设置在衬底基板(110)与第一阻隔坝(D1)之间，且设置在周边区域(NA)，并至少部分围绕显示区域(AA)，裂纹检测电路(PCD)在衬底基板(110)上的正投影与第一阻隔坝(D1)在衬底基板(110)上的正投影至少部分重叠。该显示基板可以实现窄边框设计并具有较高的封装信赖性。

Description

显示基板
相关申请的交叉引用
本专利申请要求于2022年3月25日递交的中国专利申请第202210307455.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。目前，OLED显示装置正往窄边框、大屏化方向发展，以满足用户的需求。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有显示区域以及至少部分围绕所述显示区域的周边区域，且包括衬底基板、第一阻隔坝、第一电源信号线和裂纹检测电路，第一阻隔坝设置在所述衬底基板上且设置在所述周边区域，并至少部分围绕所述显示区域；第一电源信号线设置在所述衬底基板与所述第一阻隔坝之间，且至少在所述周边区域延伸，其中，所述第一电源信号线的远离所述显示区域的至少部分边界在所述衬底基板上的正投影位于所述第一阻隔坝在所述衬底基板上的正投影内部；裂纹检测电路设置在所述衬底基板与所述第一阻隔坝之间，且设置在所述周边区域，并至少部分围绕所述显示区域，其中，所述裂纹检测电路在所述衬底基板上的正投影与所述第一阻隔坝在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述裂纹检测电路包括设置在所述衬底基板上的第一走线部分和设置在所述第一走线部分的远离 所述衬底基板一侧的第二走线部分，所述第二走线部分通过过孔与所述第一走线部分电连接，所述第二走线部分在所述衬底基板上的正投影位于所述第一阻隔坝在所述衬底基板上的正投影内部。
例如，本公开至少一实施例提供的显示基板中，所述第二走线部分与所述第一电源信号线同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二走线部分设置在所述第一电源信号线的远离所述显示区域的一侧，所述第一走线部分设置在所述第二走线部分的远离所述显示区域的一侧。
例如，本公开至少一实施例提供的显示基板中，所述第一走线部分包括多条第一走线，所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影位于所述多条第一走线在所述衬底基板上的正投影内部，或者所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影位于所述多条第一走线中相邻的两条第一走线的间隔在所述衬底基板上的正投影内部。
例如，本公开至少一实施例提供的显示基板中，所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影位于所述多条第一走线中的一条第一走线在所述衬底基板上的正投影的中部，或者所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影在所述多条第一走线中相邻的两条第一走线的间隔在所述衬底基板上的正投影内部，且与所述相邻的两条第一走线中远离所述显示区域的第一走线在衬底基板上的正投影的距离大于等于3微米。
例如，本公开至少一实施例提供的显示基板中，所述显示区域包括多个子像素，所述多个子像素中的每个包括发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括设置在所述衬底基板上的栅极和设置在所述栅极的远离所述衬底基板一侧的源漏电极，所述存储电容包括设置在所述衬底基板上的第一电容电极和设置在所述第一电容电极的远离所述衬底基板一侧的第二电容电极，所述栅极和所述第一电容电极同层设置，所述第二电容电极与所述第一走线部分同层设置，所述源漏电极与所述第二走线部分同层设置。
例如，本公开至少一实施例提供的显示基板还包括裂纹阻隔坝，其中，所述裂纹阻隔坝设置在所述裂纹检测电路的远离所述显示区域的一侧。
例如，本公开至少一实施例提供的显示基板中，所述周边区包括无机层，所述裂纹阻隔坝包括设置在所述无机层中的凹槽。
例如，本公开至少一实施例提供的显示基板中，所述显示区域还包括设置在所述像素驱动电路的远离所述衬底基板一侧的平坦化层、设置在所述平坦化层的远离所述衬底基板一侧的像素界定层和设置在所述像素界定层的远离所述衬底基板一侧的隔垫物，所述第一阻隔坝与所述平坦化层、像素界定层和隔垫物中的至少一个同层设置。
例如，本公开至少一实施例提供的显示基板中，所述裂纹检测电路的远离所述显示区域的至少部分边界在所述衬底基板上的正投影位于所述第一阻隔坝在所述衬底基板上的正投影内部。
例如，本公开至少一实施例提供的显示基板中，所述裂纹检测电路在所述衬底基板上的正投影与所述第一电源信号线在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述第一电源信号线设置在所述裂纹检测电路的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述周边区域还包括至少一条辅助走线，所述第一电源信号线通过过孔与所述至少一条辅助走线电连接，以与所述至少一条辅助走线并联。
例如，本公开至少一实施例提供的显示基板中，所述显示区域包括多个子像素，所述多个子像素中的每个包括发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括设置在所述衬底基板上的栅极和设置在所述栅极的远离所述衬底基板一侧的源漏电极，所述存储电容包括设置在所述衬底基板上的第一电容电极和设置在所述第一电容电极的远离所述衬底基板一侧的第二电容电极，所述栅极和所述第一电容电极同层设置，所述第二电容电极与所述至少一条辅助走线同层设置，所述源漏电极与所述第一电源信号线同层设置。
例如，本公开至少一实施例提供的显示基板中，所述裂纹检测电路与所述至少一条辅助走线同层设置。
例如，本公开至少一实施例提供的显示基板中，所述薄膜晶体管还包括有源层，所述有源层设置在所述栅极的靠近所述衬底基板的一侧，所述显示区域还包括遮光图案，所述遮光图案设置在所述有源层和所述衬底基板之 间，所述有源层在所述衬底基板上的正投影与所述遮光图案在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述裂纹检测电路与所述遮光图案同层设置。
例如，本公开至少一实施例提供的显示基板中，所述裂纹检测电路在所述衬底基板上的正投影与所述至少一条辅助走线在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板还包括：裂纹阻隔坝，设置在所述周边区域且设置在所述第一阻隔坝的靠近所述显示区域的一侧，至少部分围绕所述显示区域，所述裂纹阻隔坝在所述衬底基板上的正投影与所述第一电源信号线在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述裂纹阻隔坝与所述栅极和第二电容电极中的至少一个同层设置。
例如，本公开至少一实施例提供的显示基板中，在所述裂纹阻隔坝的延伸方向上，所述裂纹阻隔坝包括间隔设置的多个子裂纹阻隔坝。
例如，本公开至少一实施例提供的显示基板中，在所述裂纹阻隔坝的延伸方向上，所述多个子裂纹阻隔坝中每个子裂纹阻隔坝的长度小于50毫米。
例如，本公开至少一实施例提供的显示基板还包括：第二阻隔坝，设置在所述第一阻隔坝的靠近所述显示区域的一侧，且设置在所述裂纹阻隔坝的远离所述衬底基板的一侧，其中，所述裂纹阻隔坝在所述衬底基板上的正投影与所述第二阻隔坝在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述第一电源信号线配置为向所述显示区域提供第一电源信号，所述显示基板还包括第二电源信号线，所述第二电源信号线配置为向所述显示区域提供第二电源信号，所述第二电源信号的电位高于所述第一电源信号的电位。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的周边区域的电路和结构的排布示意图；
图2为本公开至少一实施例提供的显示基板的平面示意图；
图3为图2中的显示基板在虚线框区域的放大示意图；
图4为图3中的显示基板沿A-A线的截面示意图；
图5A为本公开至少一实施例提供的显示基板的显示区域的一个子像素的部分截面示意图；
图5B为本公开至少一实施例提供的显示基板的显示区域的一个子像素的另一部分截面示意图；
图6A为图2中的显示基板在虚线框区域的另一放大示意图；
图6B为图6A中的显示基板沿B-B线的截面示意图；
图7A为图2中的显示基板在虚线框区域的再一放大示意图；
图7B为图7A中的显示基板沿D-D线的截面示意图；
图8A为图2中的显示基板在虚线框区域的再另一放大示意图；
图8B为图8A中的显示基板沿E-E线的截面示意图；
图9为一种显示基板中封装层在第一走线旁断裂的扫描电镜示意图；
图10为本公开至少一实施例提供的另一显示基板的平面示意图；
图11为图10中的显示基板沿C-C线的截面示意图；
图12为图10中的显示基板沿C-C线的另一截面示意图；
图13为本公开至少一实施例提供的显示基板的显示区域的一个子像素的另一部分截面示意图；
图14为图10中的显示基板沿C-C线的再一截面示意图；
图15为图10中的显示基板在虚线框区域的放大示意图；
图16为图10中的显示基板沿C-C线的再另一截面示意图；以及
图17为本公开至少一实施例提供的显示基板的周边区域的电路和结构的排布示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板中，如何进一步缩窄边框，并在窄边框下保证显示面板的封装信赖性，是本领域技术人员的共同努力方向。
在显示面板中，通常设置裂纹检查电路(Panel Crack Detection，PCD)以检测显示面板是否存在裂纹。裂纹检查电路中的电路图案需要保护层保护，常见的有两种保护层，一种是有机保护层，另一种是无机保护层。在使用有机保护层的情况下，有机保护层上通常还需要覆盖无机层，以免有机保护层出现吸水膨胀等不良现象。但是，在实际工艺中，由于工艺波动，常存在无机层厚度不足的情况，在有狭缝的位置，无机层容易发生断裂，导致有机保护层被暴露出来，进而引发吸水膨胀，封装失效。在使用无机保护层的情况下，需要增加沉积无机材料以无机保护层的制备过步骤，也即多一道制备工序，会降低产能。
另外，在进行窄边框设计时，例如，图1示出了一种显示基板的边框，即围绕显示区域的非显示区域的结构排布示意图。如图1所示，在一些窄边框显示基板中，非显示区域设置有边缘切割区域A、裂纹阻挡区域B、电源走线区域C、电路设置区域D以及与连接区域E。
边缘切割区域A是为通过切割母版形成单个显示基板的切割操作预留的区域，该区域的宽度通常为约110微米；裂纹阻挡区域B设置有裂纹阻挡结构以及裂纹检查电路，以应对通过切割形成单个显示基板时的切割操作可能造成的显示基板中形成裂纹，该区域的宽度通常为约100微米；电源走线区域C例如为向显示区域中的多个子像素传输低电平电压信号的电源总线的设置区域，该区域的宽度通常为约150微米；电路设置区域D为向显示区域的多个子像素的像素驱动电路提供驱动信号的GOA(Gate on Array)驱动 电路的设置区域，该区域的宽度通常为约350微米；连接区域E为周边区域的结构(例如走线和电路)与显示区域的结构(例如走线和电路)连接的区域，该区域的宽度通常为约90微米。
上述各个区域的宽度之和即为显示基板的边框宽度，为约850微米，该宽度基本是在实现各个区域的电路以及功能结构的基本功能的基础上通过精密设计所达到的最窄宽度，该宽度难以进一步降低，因此对技术人员进一步缩窄边框提出的更大的挑战。
本公开至少一实施例提供一种显示基板，使该显示基板具有显示区域以及至少部分围绕显示区域的周边区域，且包括衬底基板、第一阻隔坝、第一电源信号线和裂纹检测电路，第一阻隔坝设置在衬底基板上且设置在周边区域，并至少部分围绕显示区域；第一电源信号线设置在衬底基板与第一阻隔坝之间，且至少在周边区域延伸，第一电源信号线的远离显示区域的至少部分边界在衬底基板上的正投影位于第一阻隔坝在衬底基板上的正投影内部；裂纹检测电路设置在衬底基板与第一阻隔坝之间，且设置在周边区域，并至少部分围绕显示区域，裂纹检测电路在衬底基板上的正投影与第一阻隔坝在衬底基板上的正投影至少部分重叠。
在本公开实施例提供的上述显示基板中，通过设计裂纹检查电路与其附近的第一电源信号线、第一阻隔坝的位置关系，可以进一步缩窄系显示基板的边框，例如将边框缩小至720微米以下，例如可以实现600微米或者650微米的极窄边框设计；并且，第一阻隔坝在实现阻隔作用的同时，还可以实现对裂纹检查电路的保护作用，并利于后续封装工艺的进行，提高封装信赖性。
下面通过几个具体的实施例对本公开的显示基板进行说明。
本公开至少一实施例提供一种显示基板，图2示出了该显示基板的平面示意图，图3示出了图2中的显示基板在虚线框区域的放大示意图，图4示出了图3中的显示基板沿A-A线的截面示意图。如图2-图4所示，该显示基板具有显示区域AA以及至少部分围绕显示区域AA的周边区域NA，且包括衬底基板110、第一阻隔坝D1、第一电源信号线VSS和裂纹检测电路PCD。
第一阻隔坝D1设置在衬底基板110上且设置在周边区域NA，并至少部分围绕显示区域AA，例如在显示区域AA的四周围绕显示区域AA，以 阻挡例如显示区域AA中形成(例如喷墨打印)的材料流入到周边区域NA中。第一电源信号线VSS设置在衬底基板110与第一阻隔坝D1之间，且至少在周边区域NA延伸，例如在一些实施例中从显示区域AA延伸至周边区域NA。第一电源信号线VSS的远离显示区域AA的至少部分边界B2在衬底基板110上的正投影位于第一阻隔坝D1在衬底基板110上的正投影内部。由此，第一阻隔坝D1覆盖第一电源信号线VSS的远离显示区域AA的至少部分边界B2，以保护第一电源信号线VSS。
裂纹检测电路PCD设置在衬底基板110与第一阻隔坝D1之间，且设置在周边区域NA，并至少部分围绕显示区域AA，例如在显示区域AA的左侧、上侧和右侧围绕显示区域AA，通过裂纹检测电路PCD可以检测显示基板是否存在例如由于切割造成的断裂等不良现象。
裂纹检测电路PCD在衬底基板110上的正投影与第一阻隔坝D1在衬底基板110上的正投影至少部分重叠，从而第一阻隔坝D1还可以保护裂纹检测电路PCD的至少部分，不需要额外形成保护层来保护裂纹检测电路PCD，由此可以简化显示基板的制备工艺。另外，上述设置还可以缩短第一阻隔坝D1到切割线CL(参考图6A、图7A和图8A)的距离，以进一步缩窄边框。
例如，在一些实施例中，裂纹检测电路PCD包括设置在衬底基板110上的第一走线部分P1和设置在第一走线部分P1的远离衬底基板110一侧的第二走线部分P2，第二走线部分P2通过过孔V与第一走线部分P1电连接，第二走线部分P2在衬底基板110上的正投影位于第一阻隔坝D1在衬底基板110上的正投影内部。例如，第一阻隔坝D1可以直接设置在第二走线部分P2上方以与第二走线部分P2接触，实现保护作用。
本公开的实施例中，通过将裂纹检测电路PCD设置为包括电连接的且位于不同导电层的第一走线部分P1和第二走线部分P2，可以防止较长的走线(长程走线)出现静电干扰等不良现象，从而达到防静电的技术效果。
例如，在一些实施例中，第二走线部分P2与第一电源信号线VSS同层设置，以简化显示基板的制备工艺。
需要注意的是，在本公开的实施例中，“同层设置”为两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，在一些实施例中，第二走线部分P2设置在第一电源信号线VSS的远离显示区域AA的一侧，第一走线部分P1设置在第二走线部分P2的远离显示区域AA的一侧。也即，第一走线部分P1、第二走线部分P2和第一电源信号线VSS在靠近显示基板AA的方向依次排布。
例如，在一些实施例中，第一走线部分P1包括多条第一走线111(即在显示基板一侧并列排布的第一走线的数量)，例如两条-六条第一走线111，第二走线部分P2包括至少一条第二走线112(即在显示基板一侧并列排布的第二走线的数量)，例如一条-三条第二走线112。本公开的实施例对此不做具体限定。
例如，第一阻隔坝D1的远离显示区域AA的边界B1在衬底基板110上的正投影位于多条第一走线111在衬底基板上的正投影内部，也即第一阻隔坝D1的远离显示区域AA的边界B1位于多条第一走线111中任一的正上方；或者，在另一些实施例中，第一阻隔坝D1的远离显示区域AA的边界B1在衬底基板110上的正投影位于多条第一走线111中相邻的两条第一走线111的间隔在衬底基板110上的正投影内部，也即第一阻隔坝D1的远离显示区域AA的边界B1位于多条第一走线111的间隔的正上方。
例如，在一些实施例中，第一阻隔坝D1的远离显示区域AA的边界B1在衬底基板110上的正投影位于多条第一走线111中的一条第一走线111在衬底基板110上的正投影的中部，如图6A所示，第一阻隔坝D1的远离显示区域AA的边界B1位于一条第一走线111的中间部位的正方向；或者，在另一些实施例中，如图3所示，第一阻隔坝D1的远离显示区域AA的边界B1在衬底基板110上的正投影在多条第一走线111中相邻的两条第一走线111的间隔在衬底基板110上的正投影内部，且与相邻的两条第一走线111中远离显示区域AA的第一走线111在衬底基板110上的正投影的距离L1大于等于3微米，以与第一走线111具有足够的间隔。
例如，图7A也示出了第一阻隔坝D1的远离显示区域AA的边界B1在衬底基板110上的正投影在多条第一走线111中相邻的两条第一走线111的间隔在衬底基板110上的正投影内部，且与相邻的两条第一走线111中远离显示区域AA的第一走线111在衬底基板110上的正投影的距离L1大于等于3微米的一种情况，图7B为图7A中的显示基板沿D-D线的截面示意图。
通过上述设置，可以避免第一阻隔坝D1上方形成的无机封装层在第一 走线111的边界位置断裂，例如，当第一阻隔坝D1的远离显示区域AA的边界B1与在衬底基板110上的正投影在多条第一走线111中相邻的两条第一走线111的间隔在衬底基板110上的正投影内部，且与相邻的两条第一走线111中远离显示区域AA的第一走线111在衬底基板110上的正投影的距离L1较近，例如小于3微米时，如图9所示，第一阻隔坝D1上方形成的第一无机封装层1051(稍后详细介绍)容易在第一走线111旁发生断裂，因此影响显示基板的封装效果。通过本公开实施例的上述设置，可以充分避免第一无机封装层1051出现断裂的风险，提高显示基板的封装效果。
例如，在一些实施例中，如图2所示，裂纹检测电路PCD可以包括采用两种原理检测显示基板是否发生断裂的电路，也即亮线检测电路PCD1和电阻检测电路PCD2。亮线检测电路PCD1可以通过亮线检测数据线PD连接至一些子像素，并通过检测子像素是否可以被点亮来检测亮线检测电路PCD1是否发生断路，进而推断显示基板是否发生断裂。电阻检测电路PCD2例如包括两个端部，通过检测电路检测电阻检测电路PCD2的电阻高低来判断电阻检测电路PCD2是否发生断路，进而推断显示基板是否发生断裂。例如，亮线检测电路PCD1和电阻检测电路PCD2可以连接至电路板FPC，并通过电路板FPC控制检测过程。
例如，在一些实施例中，如图2所示，显示区域AA包括多个子像素S，多个子像素S中的每个包括发光器件EN和驱动发光器件EM的像素驱动电路。像素驱动电路可以包括多个薄膜晶体管和存储电容，例如可以形成为2T1C(即包括两个薄膜晶体管和一个存储电容)、7T1C(即包括七个薄膜晶体管和一个存储电容)、8T2C(即包括八个薄膜晶体管和两个存储电容)等多种结构，本公开的实施例对像素驱动电路的具体形式不做限定。
例如，图5A示出了一个子像素S的部分截面示意图，如图5A所示，该像素驱动电路包括薄膜晶体管T和存储电容C。薄膜晶体管C包括设置在衬底基板110上的有源层1021、栅极1022和设置在栅极1022的远离衬底基板110一侧的源漏电极1023和1024。存储电容C包括设置在衬底基板110上的第一电容电极1031和设置在第一电容电极1031的远离衬底基板110一侧的第二电容电极1032，栅极1022和第一电容电极1031同层设置，第二电容电极1032与第一走线部分P1同层设置，源漏电极1023和1024、第一电源信号线VSS与第二走线部分P2同层设置。由此可以简化显示基板的制备 工艺。
例如，发光器件EM包括第一电极层1041(例如阳极层)、发光材料层1042以及第二电极层1043(例如阴极层)。例如，第一电极层1041与像素驱动电路(例如薄膜晶体管T的源漏电极1023)电连接，第二电极层1043与第一电源信号线VSS电连接。在第一电极层1041和第二电极层1043施加的电压驱动下，发光材料层1042可以发光。
例如，图6A示出了图2中的显示基板在虚线框区域的另一平面示意图，图6B为图6A中的显示基板沿B-B线的截面示意图。如图6A和图6B所示，在一些实施例中，显示基板还可以包括裂纹阻隔坝D3，例如多个裂纹阻隔坝D3，图6A和图6B中示出五个裂纹阻挡坝作为示例，裂纹阻隔坝D3设置在裂纹检测电路PCD的远离显示区域AA的一侧，并至少部分围绕显示区域AA。裂纹阻隔坝D3可以阻挡裂纹形成以及扩展，例如阻挡切割显示基板时形成裂纹或者阻挡已经形成的裂纹扩展至显示区域AA，从而在周边区域NA起到保护显示基板的作用。
例如，在一些实施例中，周边区NA包括无机层IN，裂纹阻隔坝D3包括设置在无机层IN中的凹槽GV。由于裂纹多数受应力作用而产生于无机层，并沿着无机层扩散、蔓延，因此，对部分无机层进行刻蚀，例如形成多条无机凹槽，可以有效阻挡微裂纹向显示区域AA扩展。例如，无机层IN可以与第一栅绝缘层1014A、第二栅绝缘层1014B以及层间绝缘层1015中的至少一个(例如全部)同层设置。例如，裂纹阻隔坝D3上方覆盖有部分平坦化层1016，以保护裂纹阻隔坝D3。
需要注意的是，为示出简洁，图4、图6B以及之后的图7B和图8B中没有分别示出与第一栅绝缘层1014A、第二栅绝缘层1014B、层间绝缘层1015以及阻挡层1112、缓冲层1013、衬底基板110等结构，这些结构的叠层关系可以参见图5A和图5B。
例如，在一些实施例中，如图2所示，显示基板还可以包括第二电源走线VDD，第一电源信号线VSS配置为向显示区域AA提供第一电源信号，第二电源信号线VDD配置为向显示区域AA提供第二电源信号，第二电源信号的电位高于第一电源信号的电位，也即第二电源信号为高电平信号，第一电源信号为低电平信号。
例如，在一些实施例中，如图2所示，显示基板的周边区域NA还可以 包括走线扇出区域F1/F2、弯折区B以及集成电路IC等。走线扇出区域F1/F2包括多条连接走线，以将显示区域AA的多条引出线(例如数据线)等连接至集成电路IC，弯折区B具有较好的柔性，以将集成电路IC以及电路板FPC等弯折至显示基板的非显示侧，从而实现窄边框设计。
例如，在一些实施例中，如图5A和图5B所示，显示区域还包括设置在像素驱动电路的远离衬底基板110一侧的平坦化层1016、设置在平坦化层1016的远离衬底基板110一侧的像素界定层1017和设置在像素界定层1017的远离衬底基板一侧的隔垫物1018。平坦化层1016可以起到平坦化像素驱动电路的作用。像素界定层1017包括多个子像素开口PO，多个子像素开口PO分贝暴露多个发光器件EM的第一电极层1041，以限定子像素的发光区域。隔垫物1018可以起到隔垫、支撑的作用，例如支撑在制备过程中可能采用的掩模板等器件。
例如，第一阻隔坝D1可以与平坦化层1016、像素界定层1017和隔垫物1018中的至少一个同层设置。例如，在一些实施例中，如图4所示，第一阻隔坝D1可以包括三个子层D11/D12/D13，该三个子层D11/D12/D13分别与平坦化层1016、像素界定层1017和隔垫物1018同层设置，以简化显示基板的制备工艺。
例如，在另一些实施例中，如图5B所示，显示基板还包括设置在像素驱动电路的远离衬底基板一侧的连接电极CEL，该连接电极CEL将像素驱动电路与第一电极层1041电连接，此时，连接电极CEL的远离衬底基板的一侧还设置有另一平坦化层1019。例如，第一阻隔坝D1可以与平坦化层1016、上述另一平坦化层1019、像素界定层1017和隔垫物1018中的至少一个同层设置。例如，在制备过程中，像素界定层1017和隔垫物1018可以采用灰色调掩模板通过同一构图工艺形成，以简化显示基板的制备工艺。例如，当平坦化层1016或者上述另一平坦化层需要在显示基板中形成具有不同厚度的部分时，也可以采用灰色调掩模板通过同一构图工艺形成不同厚度的部分。
例如，在一些实施例中，显示基板还包括第二阻隔坝D2，第二阻隔坝D2设置在第一阻隔坝D1的靠近显示区域AA的一侧，并且至少部分围绕显示区域AA。例如，第二阻隔坝D2也可以与平坦化层1016/1019、像素界定层1017和隔垫物1018中的至少一个同层设置。
例如，第一阻隔坝D1相对于衬底基板110的高度大于第二阻隔坝D2相对于衬底基板110的高度。例如，在一些实施例中，如图4所示，第二阻隔坝D2可以包括两个子层，该两个子层分别与平坦化层1016/1019、像素界定层1017和隔垫物1018中的两个同层设置，以简化显示基板的制备工艺。例如，第二阻隔坝D2包括两个子层D21和D22，子层D21与平坦化层1016或平坦化层1019同层设置，子层D22与像素界定层1017或隔垫物1018同层设置。第一阻隔坝D1和第二阻隔坝D2可以起到多重阻挡作用，以提高阻挡效果。
例如，在一些实施例中，裂纹检测电路PCD也可以只具有第一走线部分P1，此时，可以适当减少第一走线部分P1包括的第一走线111的条数(长度)，以避免发生静电干扰现象。例如，图8A示出了裂纹检测电路PCD只包括第一走线部分P1的情况，图8B为图8A中的显示基板沿E-E线的截面示意图。如图8A和图8B所示，裂纹检测电路PCD只包括第一走线部分P1，不包括第二走线部分P2，并且第一走线部分P1包括四条第一走线111，该四条第一走线111同样可以采用亮线检测和/或电阻检测等方式实现裂纹检测功能。该技术方案可以进一步缩短第一阻隔坝D1与切割线CL之间的距离，缩窄边框。
例如，如图5A和图5B所示，显示基板还可以包括设置在衬底基板110上的阻挡层1112和缓冲层1013，阻挡层1112和缓冲层1013可以防止衬底基板110中的杂质进入到显示基板110上的多个功能层中，从而起到保护作用。例如，阻挡层1112、缓冲层1013可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。
例如，如图5A和图5B所示，显示基板还可以包括设置在有源层1021的远离衬底基板110一侧的第一栅绝缘层1014A、设置在栅极1022和第一电容电极1031的远离衬底基板110一侧的第二栅绝缘层1014B以及设置在第二电容电极1032的远离衬底基板110一侧的层间绝缘层1015。例如，第一栅绝缘层1014A、第二栅绝缘层1014B、层间绝缘层1015可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。
例如，如图5A和图5B所示，显示基板还可以包括设置在发光器件EM的远离衬底基板110一侧的封装层EN，封装层EN可以为复合封装层，包括第一无机封装层1051、第一有机封装层1052和第二无机 封装层1053。第一无机封装层1051和第二无机封装层1053可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。第一有机封装层1052可以采用树脂、聚酰亚胺等有机绝缘材料。
例如，本公开的实施例中，衬底基板110可以采用聚酰亚胺等柔性基板，栅极1022可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。第一源漏电极1023和第一源漏电极1024可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。第一电容电极1031以及第二电容电极1032的材料包括铝、钛、钴、铜等金属或者合金材料。有源层1021可以采用多晶硅和金属氧化物等材料。
例如，平坦化层1016、像素界定层1017、隔垫物层1018以及封装层EN的第一有机封装层1052可以采用聚酰亚胺、树脂等有机绝缘材料。
例如，如图6B、图7B和图8B所示，在一些实施例中，发光器件EM的第二电机层1043可以整面形成在显示基板上，因此从显示区域延伸至周边区域NA，并且周边区域NA中还可以具有电极材料层1041A以及发光材料1042A，这些材料分别与发光器件EM的第一电极层1041和发光材料层1042同层设置。
例如，周边区域NA中还设置有栅扫描驱动电路GOA，栅扫描驱动电路GOA也包括薄膜晶体管和存储电容等结构，这些结构可以与显示区域AA中的像素驱动电路的薄膜晶体管T和存储电容C等结构同层设置。周边区域NA还可以包括一些走线W，这些走线W可以与连接电极CEL同层设置。
例如，显示基板还可以包括除上述结构以外的其他结构，具体可以参考相关技术，这里不再赘述。
另外，需要说明的是，本公开的实施例对各功能层的材料不做限定，且各功能层的材料并不局限于上述示例。在本公开的实施例中，各薄膜晶体管可以为P型薄膜晶体管或者N型薄膜晶体管，结构可以为底栅型、顶栅型或者双栅型，附图中示出的结构仅仅是示例性的，本公开 的实施例对各薄膜晶体管的具体形式不做限定。
例如，图10示出了本公开至少一实施例提供的另一显示基板的平面示意图，其主要示出了裂纹检测电路PCD的排布，图11示出了图10中的显示面板沿C-C线的截面示意图。
如图10和图11所示，该显示基板具有显示区域AA以及至少部分围绕显示区域AA的周边区域NA，且包括衬底基板110、第一阻隔坝D1、第一电源信号线VSS和裂纹检测电路PCD。
第一阻隔坝D1设置在衬底基板110上且设置在周边区域NA，并至少部分围绕显示区域AA，以阻挡例如显示区域AA中形成的材料流入到周边区域NA中。第一电源信号线VSS设置在衬底基板110与第一阻隔坝D1之间，且至少在周边区域NA延伸，例如在一些实施例中从显示区域AA延伸至周边区域NA。第一电源信号线VSS的远离显示区域AA的至少部分边界B2在衬底基板110上的正投影位于第一阻隔坝D1在衬底基板110上的正投影内部。由此，第一阻隔坝D1覆盖第一电源信号线VSS的远离显示区域AA的至少部分边界B2。
裂纹检测电路PCD设置在衬底基板110与第一阻隔坝D1之间，且设置在周边区域NA，并至少部分围绕显示区域AA，通过裂纹检测电路PCD可以检测显示基板是否存在断裂等不良现象。裂纹检测电路PCD在衬底基板110上的正投影与第一阻隔坝D1在衬底基板110上的正投影至少部分重叠。
例如，在一些实施例中，裂纹检测电路PCD的远离显示区域AA的至少部分边界B3在衬底基板110上的正投影位于第一阻隔坝D1在衬底基板110上的正投影内部。也即，裂纹检测电路PCD的整体结构位于第一阻隔坝D1的远离显示区域AA的边界B1的靠近显示区域AA的一侧。
例如，在一些实施例中，如图11所示，裂纹检测电路PCD包括第一部分PCD3和第二部分PCD4，第一部分PCD3和第二部分PCD4可以首尾连接以形成一个检测电路，或者第一部分PCD3和第二部分PCD4也可以分别为两个检测电路。例如，第二部分PCD4位于第一部分PCD3的靠近显示区域AA的一侧。例如，第一部分PCD3在衬底基板110上的正投影位于第一阻隔坝D1在衬底基板110上的正投影内部。第二部分PCD4位于第一阻隔坝D1的靠近显示区域AA的一侧。
例如，在一些实施例中，裂纹检测电路PCD在衬底基板110上的正投 影与第一电源信号线VSS在衬底基板110上的正投影至少部分重叠。由此，裂纹检测电路PCD与第一电源信号线VSS在衬底基板110上占据了基本相同的空间，以达到充分利用排布空间的效果，利于窄边框设计。
例如，在一些实施例中，第一电源信号线VSS设置在裂纹检测电路PCD的远离衬底基板110的一侧。
例如，如图10所示，显示区域AA包括多个子像素S，多个子像素S中的每个包括发光器件EN和驱动发光器件EM的像素驱动电路，参考图5A和图5B，显示区域AA包括多个子像素S，多个子像素S中的每个包括发光器件EM和驱动发光器件EM的像素驱动电路，像素驱动电路包括薄膜晶体管T和存储电容C，薄膜晶体管T包括设置在衬底基板110上的栅极1022和设置在栅极1022的远离衬底基板110一侧的源漏电极1023和1024。存储电容C包括设置在衬底基板110上的第一电容电极1031和设置在第一电容电极1031的远离衬底基板110一侧的第二电容电极1032，栅极1022和第一电容电极1031同层设置。对于发光器件EM和像素驱动电路的其他结构可以参照图5A、图5B及其描述，这里不再赘述。
例如，裂纹检测电路PCD与第二电容电极1032同层设置，第一电源信号线VSS与源漏电极1023和1024同层设置，以简化显示基板的制备工艺。
例如，在一些实施例中，如图5B所示，发光器件EM与像素驱动电路通过连接电极CEL电连接，如图11所示，显示基板还包括设置在第一电源信号线VSS远离衬底基板110一侧的走线SG以及与第一电极层1041同层的电极材料层1041A，走线SG例如与连接电极CEL同层设置，电极材料层1041A例如为形成第一电极层1041的同时形成在周边区域NA的材料层。
例如，在一些实施例中，如图12所示，周边区域NA还包括至少一条辅助走线AL，例如多条辅助走线AL(图中示出五条辅助走线AL作为示例)，第一电源信号线VSS通过过孔V2与至少一条辅助走线AL电连接，以与该至少一条辅助走线AL并联。通过将辅助走线AL与第一电源信号线VSS并联可以降低第一电源信号线VSS的电阻以及传输信号的压降，从而减小为不同位置的子像素提供的信号差异。
例如，在一些实施例中，辅助走线AL与裂纹检测电路PCD以及第二电容电极1032同层设置，以简化显示基板的制备工艺。
例如，在另一些实施例中，如图13所示，薄膜晶体管T还包括有源层 1021，有源层1021设置在栅极1022的靠近衬底基板110的一侧，显示区域AA还包括遮光图案SH，遮光图案SH设置在有源层1021和衬底基板110之间，有源层1021在衬底基板110上的正投影与遮光图案SH在衬底基板110上的正投影至少部分重叠。由此，遮光图案SH可以为有源层1021遮光，防止光照射到有源层1021而影响薄膜晶体管T的正常工作。
例如，在上述实施例中，如图14所示，裂纹检测电路PCD可以与遮光图案SH同层设置，以简化显示基板的制备工艺。
例如，图14的实施例相对于图12的实施例可以多设置两条辅助走线AL(图中示出七条辅助走线AL作为示例)，以进一步降低第一电源信号线VSS的电阻以及传输信号的压降。如图14所示，裂纹检测电路PCD的第一部分PCD3和第二部分PCD4的上方分别设置有一条辅助走线AL，裂纹检测电路PCD在衬底基板110上的正投影与上述辅助走线AL在衬底基板110上的正投影至少部分交叠，从而裂纹检测电路PCD与上述辅助走线AL占据了显示基板上基本相同的区域，由此可以充分利用显示基板的排布空间，实现窄边框设计。
例如，在一些实施例中，如图11和图14所示，显示基板还包括裂纹阻隔坝D3，例如多个裂纹阻隔坝D3，图中示出五个裂纹阻隔坝D3作为示例。裂纹阻隔坝D3设置在周边区域NA且设置在第一阻隔坝D1的靠近显示区域AA的一侧，至少部分围绕显示区域AA。裂纹阻隔坝D3可以阻挡裂纹形成以及扩展，例如阻挡切割显示基板时形成裂纹或者阻挡已经形成的裂纹扩展至显示区域AA，从而在周边区域NA起到保护显示基板的作用。
例如，裂纹阻隔坝D3在衬底基板110上的正投影与第一电源信号线VSS在衬底基板110上的正投影至少部分交叠。例如，裂纹阻隔坝D3在衬底基板110上的正投影位于第一电源信号线VSS在衬底基板110上的正投影内。
例如，裂纹阻隔坝D3在衬底基板110上的正投影位于裂纹检测电路PCD的第一部分PCD3和第二部分PCD4在衬底基板110上的正投影之间，也即裂纹检测电路PCD可以至少部分包围裂纹阻隔坝D3。
例如，在一些实施例中，如图11所示，裂纹阻隔坝D3包括两个金属层D31和D32，该两个金属层D31和D32分别与栅极1022和第二电容电极1032同层设置，以简化显示基板的制备工艺。例如，在另一些实施例中，如图14所示，裂纹阻隔坝D3包括两个金属层D31和D32，该两个金属层D31和 D32分别与遮光图案SH和栅极1022同层设置，以简化显示基板的制备工艺。
例如，图15示出了图10中的显示基板在虚线框区域的放大示意图，如图15所示，在一些实施例中，在裂纹阻隔坝D3的延伸方向上，即图中的竖直方向上，裂纹阻隔坝D3包括间隔设置的多个子裂纹阻隔坝D3A。
本公开的发明人在研究中发现，若裂纹阻隔坝D3的长度过长，裂纹阻隔坝D3容易累积电荷，导致静电荷较大且无法导出，因此在裂纹阻隔坝D3末端容易发生尖端发电现象，进而融化金属，导致金属氧化腐蚀。通过将裂纹阻隔坝D3设置为包括间隔设置的多个子裂纹阻隔坝D3A，可以避免上述不良现象发生。
例如，在一些实施例中，在裂纹阻隔坝D3的延伸方向上，多个子裂纹阻隔坝D3A中每个子裂纹阻隔坝D3A的长度L0小于50毫米，例如为47毫米、45毫米或者40毫米等。通过实验测试，在上述条件下，裂纹阻隔坝D3基本不会发生氧化腐蚀等不良现象。
例如，在一些实施例中，如图11、12和14所示，显示基板还包括第二阻隔坝D2，第二阻隔坝D2设置在第一阻隔坝D1的靠近显示区域AA的一侧，且设置在裂纹阻隔坝D3的远离衬底基板110的一侧，裂纹阻隔坝D3在衬底基板110上的正投影与第二阻隔坝D2在衬底基板110上的正投影至少部分交叠。
例如，第一阻隔坝D1相对于衬底基板110的高度大于第二阻隔坝D2相对于衬底基板110的高度，由此第一阻隔坝D1和第二阻隔坝D2在不同的位置以及在不同程度上起到双重阻挡作用。
例如，如图11所示，第一阻隔坝D1下方设置有平坦化层1016，从而具有更高的高度。例如，第一阻隔坝D1和第二阻隔坝D2可以与像素界定层1017、隔垫物1018或者平坦化层1016上设置的其他平坦化层(未示出)中的至少一个同层设置。
例如，在一些实施例中，如图16所示，显示基板也可以不包括第二阻隔坝D2，此时，裂纹阻隔坝D3的数量可以适当减少，图16中示出三个裂纹阻隔坝D3作为示例，由此缩小裂纹阻隔坝D3所占据的区域面积，以进一步缩窄边框。
例如，在一些实施例中，显示基板还包括第二电源信号线VDD，第一电源信号线VSS配置为向显示区域AA提供第一电源信号，第二电源信号线 VDD配置为向显示区域AA提供第二电源信号，第二电源信号的电位高于第一电源信号的电位，也即第二电源信号配置为提供高电平电压。例如，第一电源信号线VSS与发光器件EM的第二电极层1043电连接，以提供低电平电压。
例如，图9示出了本公开的实施例提供的显示基板中非显示区域NA的电路/结构排布。如图9所示，在靠近显示区域AA的方向上，非显示区域NA包括边缘切割区域A1、裂纹阻挡和电源走线区域B0、电路设置区域C1以及与连接区域D1。例如，边缘切割区域A1的长度为约110微米；裂纹阻挡和电源走线区域B0的宽度为约100微米；电路设置区域C1的宽度为约350微米；连接区域D1的宽度通常为约90微米。上述各个区域的总宽度为约650微米。可见，通过本公开实施例的上述设计，显示基板的边框可以进一步缩窄，达到极窄边框的设计效果。
本公开至少一实施例提供一种显示装置，该显示装置包括上述任一的显示基板。例如，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种显示基板，具有显示区域以及至少部分围绕所述显示区域的周边区域，且包括：
    衬底基板；
    第一阻隔坝，设置在所述衬底基板上且设置在所述周边区域，并至少部分围绕所述显示区域；
    第一电源信号线，设置在所述衬底基板与所述第一阻隔坝之间，且至少在所述周边区域延伸，其中，所述第一电源信号线的远离所述显示区域的至少部分边界在所述衬底基板上的正投影位于所述第一阻隔坝在所述衬底基板上的正投影内部；以及
    裂纹检测电路，设置在所述衬底基板与所述第一阻隔坝之间，且设置在所述周边区域，并至少部分围绕所述显示区域，其中，所述裂纹检测电路在所述衬底基板上的正投影与所述第一阻隔坝在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述裂纹检测电路包括设置在所述衬底基板上的第一走线部分和设置在所述第一走线部分的远离所述衬底基板一侧的第二走线部分，所述第二走线部分通过过孔与所述第一走线部分电连接，
    所述第二走线部分在所述衬底基板上的正投影位于所述第一阻隔坝在所述衬底基板上的正投影内部。
  3. 根据权利要求2所述的显示基板，其中，所述第二走线部分与所述第一电源信号线同层设置。
  4. 根据权利要求2或3所述的显示基板，其中，所述第二走线部分设置在所述第一电源信号线的远离所述显示区域的一侧，所述第一走线部分设置在所述第二走线部分的远离所述显示区域的一侧。
  5. 根据权利要求2-4任一所述的显示基板，其中，所述第一走线部分包括多条第一走线，
    所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影位于所述多条第一走线在所述衬底基板上的正投影内部，或者
    所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投 影位于所述多条第一走线中相邻的两条第一走线的间隔在所述衬底基板上的正投影内部。
  6. 根据权利要求5所述的显示基板，其中，所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影位于所述多条第一走线中的一条第一走线在所述衬底基板上的正投影的中部，或者
    所述第一阻隔坝的远离所述显示区域的边界在所述衬底基板上的正投影在所述多条第一走线中相邻的两条第一走线的间隔在所述衬底基板上的正投影内部，且与所述相邻的两条第一走线中远离所述显示区域的第一走线在衬底基板上的正投影的距离大于等于3微米。
  7. 根据权利要求2-6任一所述的显示基板，其中，所述显示区域包括多个子像素，所述多个子像素中的每个包括发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括设置在所述衬底基板上的栅极和设置在所述栅极的远离所述衬底基板一侧的源漏电极，所述存储电容包括设置在所述衬底基板上的第一电容电极和设置在所述第一电容电极的远离所述衬底基板一侧的第二电容电极，
    所述栅极和所述第一电容电极同层设置，所述第二电容电极与所述第一走线部分同层设置，所述源漏电极与所述第二走线部分同层设置。
  8. 根据权利要求7所述的显示基板，还包括裂纹阻隔坝，其中，所述裂纹阻隔坝设置在所述裂纹检测电路的远离所述显示区域的一侧。
  9. 根据权利要求8所述的显示基板，其中，所述周边区包括无机层，所述裂纹阻隔坝包括设置在所述无机层中的凹槽。
  10. 根据权利要求7-9任一所述的显示基板，其中，所述显示区域还包括设置在所述像素驱动电路的远离所述衬底基板一侧的平坦化层、设置在所述平坦化层的远离所述衬底基板一侧的像素界定层和设置在所述像素界定层的远离所述衬底基板一侧的隔垫物，
    所述第一阻隔坝与所述平坦化层、像素界定层和隔垫物中的至少一个同层设置。
  11. 根据权利要求1所述的显示基板，其中，所述裂纹检测电路的远离所述显示区域的至少部分边界在所述衬底基板上的正投影位于所述第一阻隔坝在所述衬底基板上的正投影内部。
  12. 根据权利要求11所述的显示基板，其中，所述裂纹检测电路在所 述衬底基板上的正投影与所述第一电源信号线在所述衬底基板上的正投影至少部分重叠。
  13. 根据权利要求12所述的显示基板，其中，所述第一电源信号线设置在所述裂纹检测电路的远离所述衬底基板的一侧。
  14. 根据权利要求13所述的显示基板，其中，所述周边区域还包括至少一条辅助走线，所述第一电源信号线通过过孔与所述至少一条辅助走线电连接，以与所述至少一条辅助走线并联。
  15. 根据权利要求14所述的显示基板，其中，所述显示区域包括多个子像素，所述多个子像素中的每个包括发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括设置在所述衬底基板上的栅极和设置在所述栅极的远离所述衬底基板一侧的源漏电极，所述存储电容包括设置在所述衬底基板上的第一电容电极和设置在所述第一电容电极的远离所述衬底基板一侧的第二电容电极，
    所述栅极和所述第一电容电极同层设置，所述第二电容电极与所述至少一条辅助走线同层设置，所述源漏电极与所述第一电源信号线同层设置。
  16. 根据权利要求15所述的显示基板，其中，所述裂纹检测电路与所述至少一条辅助走线同层设置。
  17. 根据权利要求15所述的显示基板，其中，所述薄膜晶体管还包括有源层，所述有源层设置在所述栅极的靠近所述衬底基板的一侧，所述显示区域还包括遮光图案，所述遮光图案设置在所述有源层和所述衬底基板之间，所述有源层在所述衬底基板上的正投影与所述遮光图案在所述衬底基板上的正投影至少部分重叠。
  18. 根据权利要求17所述的显示基板，其中，所述裂纹检测电路与所述遮光图案同层设置。
  19. 根据权利要求18所述的显示基板，其中，所述裂纹检测电路在所述衬底基板上的正投影与所述至少一条辅助走线在所述衬底基板上的正投影至少部分交叠。
  20. 根据权利要求15-19任一所述的显示基板，其中，还包括裂纹阻隔坝，设置在所述周边区域且设置在所述第一阻隔坝的靠近所述显示区域的一侧，至少部分围绕所述显示区域，
    所述裂纹阻隔坝在所述衬底基板上的正投影与所述第一电源信号线在 所述衬底基板上的正投影至少部分交叠。
  21. 根据权利要求20所述的显示基板，其中，所述裂纹阻隔坝与所述栅极和第二电容电极中的至少一个同层设置。
  22. 根据权利要求20或21所述的显示基板，其中，在所述裂纹阻隔坝的延伸方向上，所述裂纹阻隔坝包括间隔设置的多个子裂纹阻隔坝。
  23. 根据权利要求22所述的显示基板，其中，在所述裂纹阻隔坝的延伸方向上，所述多个子裂纹阻隔坝中每个子裂纹阻隔坝的长度小于50毫米。
  24. 根据权利要求20-23任一所述的显示基板，还包括：
    第二阻隔坝，设置在所述第一阻隔坝的靠近所述显示区域的一侧，且设置在所述裂纹阻隔坝的远离所述衬底基板的一侧，
    其中，所述裂纹阻隔坝在所述衬底基板上的正投影与所述第二阻隔坝在所述衬底基板上的正投影至少部分交叠。
  25. 根据权利要求1-24任一所述的显示基板，其中，所述第一电源信号线配置为向所述显示区域提供第一电源信号，
    所述显示基板还包括第二电源信号线，所述第二电源信号线配置为向所述显示区域提供第二电源信号，所述第二电源信号的电位高于所述第一电源信号的电位。
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