WO2023178771A1 - 栅极驱动电路和显示面板 - Google Patents

栅极驱动电路和显示面板 Download PDF

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Publication number
WO2023178771A1
WO2023178771A1 PCT/CN2022/087288 CN2022087288W WO2023178771A1 WO 2023178771 A1 WO2023178771 A1 WO 2023178771A1 CN 2022087288 W CN2022087288 W CN 2022087288W WO 2023178771 A1 WO2023178771 A1 WO 2023178771A1
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WIPO (PCT)
Prior art keywords
pull
transistor
signal
auxiliary
gate
Prior art date
Application number
PCT/CN2022/087288
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English (en)
French (fr)
Inventor
陈志祥
Original Assignee
Tcl华星光电技术有限公司
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Publication date
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Priority to US17/771,913 priority Critical patent/US20240169873A1/en
Publication of WO2023178771A1 publication Critical patent/WO2023178771A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present application relates to the field of display technology, particularly to the field of display panel manufacturing technology, and specifically to gate drive circuits and display panels.
  • GOA Gate Driver on Array, array substrate gate drive
  • the pull-down holding unit is an essential circuit structure in each level of GOA circuit. It can maintain the output gate signal of the GOA circuit at a low voltage after it is pulled down.
  • the gate of the pull-down sustain transistor in the pull-down sustain unit is caused to be positive, and the pull-down sustain transistor is superimposed and continues to work, causing the threshold voltage of the pull-down sustain transistor to shift, causing the pull-down sustain transistor to be unable to maintain the gate signal normally in the later stage. , causing abnormal gate signal output and reducing the quality of the display panel.
  • the pull-down sustain transistor in the existing GOA circuit will continue to work, resulting in abnormal gate signal output, resulting in a reduction in the quality of the display panel's display image, which is in urgent need of improvement.
  • Embodiments of the present application provide a gate drive circuit and a display panel to solve the technical problem of abnormal gate signal output caused by the continuous operation of the pull-down sustain transistor in the existing GOA circuit.
  • Embodiments of the present application provide a gate drive circuit, including a plurality of cascaded gate drive units, where the gate drive units include:
  • the pull-up module is electrically connected to the pull-up control module through the first node, and is electrically connected to the scan line;
  • a pull-down module is electrically connected to the scan line
  • a first pull-down maintenance module, the first pull-down maintenance module includes:
  • a first pull-down sustain transistor the drain of the first pull-down sustain transistor is electrically connected to the first node
  • the first auxiliary module is electrically connected to the gate of the first pull-down holding transistor, and the first auxiliary module is used to control the on-off state of the first pull-down holding transistor.
  • the first auxiliary module includes:
  • a first auxiliary transistor the drain of the first auxiliary transistor is electrically connected to the gate of the first pull-down holding transistor, and the source of the first auxiliary transistor is electrically connected to the auxiliary power line to load As an auxiliary signal, the gate of the first auxiliary transistor is connected to the first control signal line to be loaded as the first control signal;
  • the first control signal is used to control the first auxiliary transistor to turn on, so as to control the on-off state of the first pull-down holding transistor through the auxiliary signal.
  • the present application provides a gate drive circuit and a display panel, including a plurality of cascaded gate drive units.
  • the gate drive unit includes: a pull-up control module; a pull-up module electrically connected to the gate drive unit through a first node.
  • the pull-up control module is electrically connected to the scan line;
  • the pull-down module is electrically connected to the scan line;
  • the first pull-down sustain module includes: a first pull-down sustain transistor, so The drain of the first pull-down sustain transistor is electrically connected to the first node;
  • a first auxiliary module is electrically connected to the gate of the first pull-down sustain transistor, and the first auxiliary module is used to control The first pull-down maintains the on-off state of the transistor.
  • a first auxiliary module electrically connected to the gate of the first pull-down holding transistor is provided to control the first pull-down holding transistor to have a closed state, thereby preventing the first pull-down holding transistor from being in an on state for a long time.
  • the resulting threshold voltage shift reduces the risk that the first pull-down holding transistor cannot normally maintain the pull-down of the first node, thereby reducing the risk that the pull-up control module cannot control the scan line to output the correct gate signal, thereby reducing This eliminates the risk of abnormal screen display and improves the quality of screen display.
  • FIG. 1 is a circuit diagram of a first gate driving unit provided by an embodiment of the present application.
  • FIG. 2 is a circuit diagram of a second gate driving unit provided by an embodiment of the present application.
  • FIG. 3 is a circuit diagram of a third gate driving unit provided by an embodiment of the present application.
  • FIG. 4 is a circuit diagram of a fourth gate driving unit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the transfer characteristic curve shift of a transistor provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a shifted transfer characteristic curve of a transistor provided by an embodiment of the present application.
  • Figure 7 is a waveform diagram of some signals provided by the embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Embodiments of the present application provide a gate driving circuit, which includes but is not limited to the following embodiments and combinations of the following embodiments.
  • the gate driving circuit includes a plurality of cascaded gate driving units.
  • the n-th level gate driving unit is taken as an example.
  • the n-th level gate driving unit is The pole driving unit 100 includes: a pull-up control module 10; a pull-up module 20, which is electrically connected to the pull-up control module 10 through the first node Q(n) and is electrically connected to the scan line; a pull-down module 30, which is electrically connected to the scan line.
  • the first pull-down sustain module 40, the first pull-down sustain module 40 includes: a first pull-down sustain transistor T42, the drain of the first pull-down sustain transistor T42 is electrically connected to the first node Q(n); the first auxiliary module 401 is electrically connected to the gate of the first pull-down holding transistor T42, and the first auxiliary module 401 is used to control the first pull-down The on-off state of transistor T42 is maintained.
  • the pull-up control module 10 can control the operation of the pull-up module 20 by controlling the potential of the first node Q(n), thereby controlling the gate signal G(n) output by the scan line.
  • the pull-down module 30 can control the gate signal G(n) output by the scan line to be the corresponding non-working voltage, and the first pull-down maintaining module 40 can maintain the first node Q(n) at the previous potential.
  • the gate signal G(n) can be loaded onto the corresponding multiple sub-pixels, wherein the operating voltage in the gate signal G(n) can control the corresponding multiple sub-pixels to turn on to display the corresponding image.
  • the corresponding multiple sub-pixels can maintain the corresponding image, and at the same time, the next-level gate signal G(n+1) presents the corresponding operating voltage to control the corresponding multiple sub-pixels. Pixels are turned on to display the corresponding image. Therefore, when the gate signal G(n) cannot be converted from the corresponding working voltage to the corresponding non-working voltage in time, the data information corresponding to multiple sub-pixels in the next row will be loaded again to multiple sub-pixels in the current row. Causes abnormal screen display.
  • this application does not limit the type of transistors in the gate driving unit 100 and the relationship between the working voltage and the non-working voltage of each level of gate signal.
  • the type of each transistor in the gate driving unit 100 is All are N-type transistors, and the threshold voltage of the first pull-down holding transistor T42 is greater than or equal to 0, and the operating voltage of the gate signal of each stage is greater than the non-operating voltage.
  • the pull-up control module 10 may include a pull-up control transistor T11 , and the gate of the pull-up control transistor T11 is loaded with the (n-6)th stage transmission signal ST(n-6 ), the source of the pull-up control transistor T11 is loaded with the (n-6)th stage gate signal G(n-6), and the drain of the pull-up control transistor T11 is electrically connected to the first node Q(n);
  • the pull-up module 20 may include a pull-up transistor T21.
  • the gate of the pull-up transistor T21 may be electrically connected to the first node Q(n).
  • the source of the pull-up transistor T21 may be loaded with the clock signal CK(n).
  • the pull-up transistor T21 may be electrically connected to the first node Q(n).
  • the drain of T21 may be electrically connected to the scan line, and the gate driving unit 100 may further include a bootstrap capacitor Cbt electrically connected between the gate of the pull-up transistor T21 and the drain of the pull-up transistor T21; the pull-down module 30 It may include a first pull-down transistor T41 and a second pull-down transistor T31.
  • the gate electrode of the first pull-down transistor T41 and the gate electrode of the second pull-down transistor T31 are both loaded with the (n+8)th stage transmission signal ST(n+ 8), the source of the first pull-down transistor T41 can be loaded with the first pull-down signal, the drain of the first pull-down transistor T41 can be electrically connected to the first node (Q), and the source of the second pull-down transistor T31 can be loaded as a second pull-down signal, and the drain of the second pull-down transistor T31 can be electrically connected to the scan line.
  • the (n-6)th stage transmission signal ST(n-6) is the corresponding high potential
  • the (n-6)th stage gate signal G(n-6) is also the corresponding high potential.
  • the pull-up control transistor T11 is turned on so that the first node Q(n) rises to the first high potential under the action of the (n-6)th stage transmission signal ST(n-6); thereafter the clock signal CK(n) is The corresponding high potential
  • the scan line can output the corresponding high potential as the operating voltage of the gate signal G(n), and at the same time, the clock signal Under the action of CK(n) and bootstrap capacitor Cbt, the first node Q(n) rises from the first high potential to the second high potential; thereafter, the (n+8)th stage transmission signal ST(n+8) is Corresponding to the high potential
  • the first pull-down signal can pull down the potential of the first node (Q
  • L1 is the transfer characteristic curve in the saturation region when the threshold voltage of the transistor does not shift.
  • the abscissa represents the The gate voltage Vg
  • the ordinate represents the drain current Ids of the transistor. It can be found that under the premise that the difference between the gate voltage Vg and the source voltage Vs of the transistor is greater than the threshold voltage Vth, that is, when the gate voltage Vg of the transistor is greater than ( Under the premise of Vs+Vth), the drain current Ids of the transistor increases as the gate voltage Vg of the transistor increases.
  • the drain of the first pull-down sustain transistor T42 in the pull-down sustain module 40 is electrically connected to the first node Q(n), that is, the first pull-down sustain transistor T42 can control the first node in the on state.
  • the potential of Q(n) is pulled down to maintain the gate signal G(n) output by the scan line at the corresponding non-operating voltage.
  • the first pull-down holding transistor T42 appears to be forward biased.
  • the gate voltage of the first pull-down sustaining transistor T42 will still be equal to the source voltage of the first pull-down sustaining transistor T42, resulting in the first pull-down sustaining transistor T42.
  • the sustaining transistor T42 continues to be forward biased. As shown in Figures 5 and 6, the threshold voltage of the pull-down sustaining transistor T42 is shifted forward to Vth', which causes the transfer characteristic curve of the first pull-down sustaining transistor T42 to change from L1 to Shift to the right to L2, so that the drain current Ids corresponding to the gate voltage Vg of the first pull-down holding transistor T42 will decrease in the later period, and the pull-down holding transistor T42 cannot be turned on properly, causing the first pull-down holding transistor T42 to not function normally.
  • the first auxiliary module 401 in this embodiment is electrically connected to the gate of the first pull-down sustaining transistor T42, and the first auxiliary module 401 is used to control the first pull-down sustaining transistor T42 to turn off, that is, the first The auxiliary module 401 controls the gate voltage of the first pull-down sustaining transistor T42, thereby turning off the first pull-down sustaining transistor T42, so as to avoid the threshold voltage deviation caused by the first pull-down sustaining transistor T42 being turned on for a long time, thereby reducing the threshold voltage of the first pull-down sustaining transistor T42.
  • the risk that the pull-up holding transistor T42 cannot normally maintain the pull-down of the first node Q(n) reduces the risk that the pull-up control module 10 cannot control the scan line to output the correct gate signal G(n), thereby reducing This eliminates the risk of abnormal screen display and improves the quality of screen display.
  • the first auxiliary module 401 includes: a first auxiliary transistor T62, the drain of the first auxiliary transistor T62 is electrically connected to the first pull-down The gate of the holding transistor T42 is maintained, the source of the first auxiliary transistor T62 is electrically connected to the auxiliary power line to load an auxiliary signal, and the gate of the first auxiliary transistor T62 is connected to the first control signal line to Loaded as a first control signal; wherein, the first control signal is used to control the first auxiliary transistor T62 to turn on, so as to control the on-off state of the first pull-down sustaining transistor T42 through the auxiliary signal.
  • both the first auxiliary transistor T62 and the first pull-down holding transistor T42 are N-type transistors, when the voltage value of the first control signal loaded to the gate of the first auxiliary transistor T62 is greater than the voltage value loaded to the gate of the first auxiliary transistor T62 When the voltage value of the auxiliary signal at the source of T62 and the absolute value of the difference between the two is greater than the threshold voltage of the first auxiliary transistor T62, the first auxiliary transistor T62 is turned on.
  • the first pull-down holding transistor T42 can control the potential of the first node Q(n) to pull down when in the on state, that is, the potential of the source of the first pull-down holding transistor T42 can be considered to be smaller than the auxiliary The voltage value of the signal, and the absolute value of the difference between the two is greater than the threshold voltage of the first pull-down holding transistor T42, that is, the auxiliary signal can be loaded to the gate of the first auxiliary transistor T62 through the first auxiliary transistor T62 to turn off the first auxiliary transistor T62.
  • a pull-down holding transistor T42 is used to prevent the first pull-down holding transistor T42 from being turned on for a long time and cause a threshold voltage deviation, thereby reducing the failure of the first pull-down holding transistor T42 to normally maintain the pull-down of the first node Q(n). This reduces the risk that the pull-up control module 10 cannot control the scan line to output the correct gate signal G(n), thereby reducing the risk of abnormal screen display and improving the quality of the screen display.
  • the gate driving unit 100 further includes a second pull-down sustain module 50 .
  • the second pull-down sustain module 50 includes: a second pull-down sustain transistor T43 .
  • the gate of the second pull-down sustain transistor T43 is electrically connected to the second pull-down sustain line to load the second pull-down sustain signal LC2.
  • the source of the second pull-down sustain transistor T43 and the first pull-down sustain transistor T42 The source is electrically connected to the first power line to load the first power signal VSSQ, and the drain of the second pull-down holding transistor T43 is electrically connected to the first node Q(n); wherein, the second pull-down holding transistor T43
  • the sustain signal LC2 includes alternately arranged high and low voltages.
  • the second pull-down sustain signal LC2 is used to control the second pull-down sustain transistor T43 to turn on to control the first node Q through the first power supply signal VSSQ. (n) potential, the first control signal and the second pull-down sustain signal LC2 are the same.
  • the drain of the first pull-down sustain transistor T42 in the first pull-down sustain module 40 and the drain of the second pull-down sustain transistor T43 in the second pull-down sustain module 50 are both electrically connected. to the first node Q(n), that is, both can maintain the first node Q(n) at the previous potential.
  • the second pull-down sustain signal LC2 includes alternately arranged high potentials and low potentials, that is, in this embodiment, the second pull-down sustain signal LC2 loaded on the gate of the second pull-down sustain transistor T43 is the corresponding high potential.
  • the second pull-down holding transistor T43 can be controlled to turn on, so that the first power signal VSSQ is loaded to the first node Q(n) through the second pull-down holding transistor T43.
  • the pull-up transistor T21 is an N-type transistor
  • the first power signal VSSQ VSSQ can be considered as a constant voltage signal used to pull down the potential of the first node Q(n), thereby turning off the pull-up transistor T21.
  • the first power supply signal VSSQ loaded to the source of the first pull-down sustain transistor T42 can also pull down the potential of the first node Q(n) when the first pull-down sustain transistor T42 is turned on.
  • the high potential in the second pull-down sustain signal LC2 can control the second pull-down sustain transistor T43 to turn on.
  • the first control signal in this embodiment is the same as the second pull-down sustain signal LC2.
  • the high potential in the second pull-down sustain signal LC2 can also be controlled.
  • the first auxiliary transistor T62 is turned on to control the first pull-down holding transistor T42 to turn off through the auxiliary signal. Therefore, in this embodiment, by setting the first control signal to be the same as the second pull-down sustain signal LC2, the first pull-down sustain transistor T42 can be turned off while the second pull-down sustain transistor T43 is turned on.
  • the signal can be saved. type, on the other hand, during the period when the second pull-down sustain transistor T43 is turned on, the first pull-down sustain transistor T42 can be turned off in time to avoid the first pull-down sustain transistor T42 from continuing to operate, and at the same time, the first node Q(n ) and alleviate the shift in the threshold voltage of the first pull-down holding transistor T42.
  • the auxiliary power line and the first power line are the same line.
  • the first power line is loaded with the first power signal VSSQ, that is, the auxiliary power line in this embodiment is also loaded with the first power signal VSSQ, so that the source of the first auxiliary transistor T62 and the first pull-down
  • the sources of the sustaining transistors T42 are loaded with the first power signal VSSQ through the same line called the auxiliary power line or the first power line.
  • the source of the first pull-down sustaining transistor T42 is electrically connected to the first power line to load the first power supply signal VSSQ, and the threshold voltage of the first pull-down sustaining transistor T42 is greater than or equal to 0, this embodiment
  • the source of the first auxiliary transistor T62 is loaded with the first power supply signal VSSQ, so that when the first auxiliary transistor T62 is turned on, the potential of the gate of the second pull-down holding transistor T43 is equal to the first power signal VSSQ, that is, the first pull-down
  • the difference between the gate potential and the source potential of the sustain transistor T42 is 0, that is, less than the threshold voltage of the first pull-down sustain transistor T42 , the first pull-down sustain transistor T42 can be turned off.
  • the auxiliary power line and the first power line are different lines, so that the auxiliary signal is different from the first power signal VSSQ.
  • the auxiliary signal VSSR loaded on the auxiliary power line can also be a constant voltage signal.
  • the auxiliary signal controls the first pull-down holding transistor T42 to turn off, based on the threshold voltage of the first pull-down holding transistor T42 being greater than or equal to 0.
  • the voltage value of the auxiliary signal VSSR in this embodiment can be smaller than the voltage value of the first power signal VSSQ, so that when the first auxiliary transistor T62 is turned on, the potential of the gate of the first pull-down holding transistor T42 is smaller than the first power signal VSSQ, that is, the potential of the gate of the first pull-down sustain transistor T42 is smaller than the source of the first pull-down sustain transistor T42, that is, further smaller than the threshold voltage of the first pull-down sustain transistor T42.
  • the second pull-down sustaining module 50 further includes: a second auxiliary module 501 electrically connected to the gate of the second pull-down sustaining transistor T43.
  • the second auxiliary module 501 is used to control the on-off state of the second pull-down holding transistor T43.
  • the gate of the second pull-down sustain transistor T43 is electrically connected to the second pull-down sustain line to be loaded as the second pull-down sustain signal LC2, and the source of the second pull-down sustain transistor T43 is electrically connected to The first power line is loaded with the first power signal VSSQ, the drain of the second pull-down sustaining transistor T43 is electrically connected to the first node Q(n), and the high potential in the second pull-down sustaining signal LC2 controls the second pull-down sustaining transistor.
  • the second auxiliary module 501 in this embodiment can control the second pull-down holding transistor T43 to turn off.
  • the gate voltage of the second pull-down holding transistor T43 in this embodiment can be controlled by the second auxiliary module 501 to turn off the second pull-down holding transistor T42.
  • the pull-down holding transistor T43 is used to avoid the threshold voltage deviation caused by the second pull-down holding transistor T43 being on for a long time, and reduces the risk that the first pull-down holding transistor T42 cannot normally maintain the pull-down of the first node Q(n). This reduces the risk that the pull-up control module 10 cannot control the scan line to output the correct gate signal G(n), thereby reducing the risk of abnormal screen display and improving the quality of the screen display.
  • the second auxiliary module 501 includes: a second auxiliary transistor T63, the drain of the second auxiliary transistor T63 is electrically connected to the second pull-down sustain The gate of the transistor T43 and the source of the second auxiliary transistor T63 are electrically connected to the auxiliary power line to be loaded as the auxiliary signal.
  • the gate of the second auxiliary transistor T63 is connected to the second control The signal line is loaded with the second control signal; wherein, the gate of the first pull-down sustain transistor T42 is electrically connected to the first pull-down sustain line to be loaded with the first pull-down sustain signal LC1; wherein, the gate of the first pull-down sustain transistor T42 is loaded with the first pull-down sustain signal LC1; A pull-down sustain signal LC1 is used to control the first pull-down sustain transistor T42 to turn on to control the potential of the first node Q(n) through the first power supply signal VSSQ.
  • the first pull-down sustain signal LC1 includes the high potential and the low potential arranged alternately. As shown in FIG.
  • the high potential vgh in the first pull-down sustain signal LC1 and the vgh in the second pull-down sustain signal LC2 The low potential vgl is arranged correspondingly; wherein the second control signal is the same as the first pull-down sustain signal LC1.
  • the control method of the second auxiliary transistor T63 on the second pull-down sustaining transistor T43 may refer to the above related description on the control method of the first auxiliary transistor T62 on the first pull-down sustaining transistor T42.
  • the second pull-down sustain transistor T43 is controlled to be turned on and the first pull-down sustain transistor T42 is controlled to be turned off.
  • the first pull-down sustain signal LC1 is at the corresponding high potential vgh.
  • the first pull-down sustain transistor T42 is controlled to be turned on and the second pull-down sustain transistor T43 is controlled to be turned off. Therefore, in this embodiment, by setting the second control signal to be the same as the first pull-down sustain signal LC1, on the one hand The types of signals can be saved.
  • the second pull-down sustain transistor T43 can be turned off in time to avoid the second pull-down sustain transistor T43 from continuing to operate, and the first node can be taken into consideration at the same time.
  • the potential of Q(n) is pulled down and the shift in the threshold voltage of the second pull-down holding transistor T43 is relieved.
  • the high potential vgh in the first pull-down sustain signal LC1 and the low potential vgl in the second pull-down sustain signal LC2 are arranged correspondingly.
  • the first pull-down sustain signal The low potential vgl in LC1 and the high potential vgh in the second pull-down sustain signal LC2 are arranged correspondingly.
  • the high potential vgh in the first pull-down sustain signal LC1 and the high potential vgh in the second pull-down sustain signal LC2 are staggered, which can cause the first pull-down sustain transistor T42 and the second pull-down sustain transistor T43 to turn on alternately.
  • the second pull-down sustaining transistor T43 and the first pull-down sustaining transistor T42 can be turned off alternately, so that the potential of the first node Q(n) can be continuously pulled low, and at the same time, the second pull-down sustaining transistor T43 and the first pull-down sustaining transistor T42 can be realized.
  • the pull-down holding transistor T42 is turned off alternately to prevent either one of the two from continuing to work, thereby reducing the risk that either one of the two cannot normally maintain the pull-down of the first node Q(n), thereby reducing the upper
  • the pull control module 10 is unable to control the risk of the scan line outputting the correct gate signal G(n), thereby reducing the risk of abnormal screen display and improving the quality of the screen display.
  • the first auxiliary module 401 includes: a control signal line loaded as a control signal CTR, and the control signal line is electrically connected to the first pull-down holding transistor T42 The gate; wherein, the control signal CTR includes a plurality of effective potentials arranged at intervals, and each of the effective potentials is used to control the on-off state of the first pull-down holding transistor T42.
  • the first auxiliary module 401 is configured to include the first auxiliary transistor T62, and combine the auxiliary signal and the first control signal to jointly control the first pull-down holding transistor T42 gate voltage, thereby controlling the first pull-down holding transistor T42 to have an off period.
  • control signal CTR in this embodiment can be understood as a signal generated from the gate of the first pull-down holding transistor T42 through the cooperation of the first auxiliary transistor T62, the auxiliary signal and the first control signal. It can be understood that, When the first auxiliary transistor T62, the auxiliary signal and the first control signal and their connection relationships are determined, the signal generated from the gate of the first pull-down holding transistor T42 is also determined, that is, the control signal CTR in this embodiment It can be determined based on factors such as those mentioned above.
  • the control signal CTR is the same as the signal generated by the first auxiliary transistor T62, the auxiliary signal and the first control signal as an example.
  • Each effective potential in the control signal CTR can be understood as equal to the potential of the auxiliary signal.
  • the time period in which each effective potential is located may correspond to the time period in which the first control signal controls the first auxiliary transistor T62 to turn on, that is, each effective potential in the control signal CTR in this embodiment acts on the first auxiliary transistor T62 , which is equivalent to the auxiliary signal acting on the first pull-down holding transistor T42 through the first auxiliary transistor T62, and the effect is to turn off the first pull-down holding transistor T42.
  • the first auxiliary module 401 in this embodiment is configured to include a control signal line loaded with the control signal CTR, which can save periods and the number of wires, and simplify the circuit structure of the gate driving unit 100 .
  • the second auxiliary module 501 can refer to the settings in Figures 2 and 3, or can be as shown in Figure 4.
  • the first auxiliary module 401 includes: a third control signal line, loaded as a third control signal CTR. ', the control signal line is electrically connected to the gate of the second pull-down holding transistor T43; wherein the third control signal CTR' also includes a plurality of effective potentials arranged at intervals, each of which The effective potential is used to control the second pull-down holding transistor T43 to turn off.
  • the first pull-down maintenance module 40 further includes: a first reverse module 402, electrically connected to the first node Q(n), and electrically connected to the first node Q(n). is electrically connected to the gate of the first pull-down sustaining transistor T42 to control the first pull-down sustaining transistor T42 to turn on.
  • the first reverse module 402 can output the opposite value of the potential of the first node Q(n) to the gate of the first pull-down holding transistor T42. For example, when the first node Q(n) is at the corresponding low potential, The gate of the first pull-down holding transistor T42 is at a corresponding high potential to turn on the first pull-down holding transistor T42.
  • turning on the first pull-down holding transistor T42 can maintain the potential of the first node Q(n) and continue to pull it down.
  • the gate of the first pull-down holding transistor T42 is at the corresponding high potential, and the first pull-down holding transistor T42 cannot be turned on, and the first node Q(n) cannot be pulled down. potential.
  • the first reverse module 402 may include a first reverse transistor T51 , a second reverse transistor T52 , a third reverse transistor T53 and a fourth reverse transistor T54 .
  • the source of the reverse transistor T51, the gate of the first reverse transistor T51 and the source of the third reverse transistor T53 are loaded with the first pull-down sustain signal LC1, and the drain of the first reverse transistor T51 is electrically connected to The gate of the third reverse transistor T53; the gate of the second reverse transistor T52; and the gate of the fourth reverse transistor T54 are electrically connected to the first node Q(n), and the drain of the second reverse transistor T52 , the drain of the fourth reverse transistor T54 is loaded with the first power signal VSSQ, the source of the second reverse transistor T52 is electrically connected to the drain of the first reverse transistor T51, and the source of the fourth reverse transistor T54 Electrically connected to the drain of the third reverse transistor T53.
  • the second reverse transistor T52 and the fourth reverse transistor T54 are turned off, and the first reverse transistor T52 is turned off.
  • the reverse transistor T51 and the third reverse transistor T53 are turned on, so that the first pull-down sustaining transistor T42 is turned on to load the first power signal VSSQ to the first node Q(n) to achieve the first node Q(n). of pull down.
  • the first pull-down sustaining module 40 may also include a third pull-down sustaining transistor T32 .
  • the gate of the third pull-down sustaining transistor T32 is electrically connected to the first pull-down sustaining transistor T42 .
  • the gate and the source of the third pull-down sustain transistor T32 are electrically connected to the second power line to load the second power signal VSSG.
  • the drain of the third pull-down sustain transistor T32 is electrically connected to the scan line, that is, the third pull-down sustain transistor T32 is electrically connected to the scan line.
  • the transistor T32 can pull down the gate signal G(n) on the scan line under the control of the first reverse module 402, and can be turned off under the control of the first auxiliary module 401 to avoid continuous operation.
  • the second power signal VSSG can be considered as a constant voltage signal used to pull down the gate signal G(n).
  • the source of the third pull-down sustaining transistor T32 can also be electrically connected to the first pull-down sustaining transistor T42 The sources share the first power signal VSSQ to save the number of wires.
  • the gate driving unit 100 may also include a stage pass module 60 .
  • the stage pass module 60 may include a stage pass transistor T22 .
  • the gate of the stage pass transistor T22 is electrically connected to the first node. Q(n), the source of the stage pass transistor T22 is loaded with the clock signal CK(n), and the drain of the stage pass transistor T22 outputs the stage pass signal ST(n), that is, by controlling the potential of the first node Q(n)
  • the stage pass transistor T22 can be controlled to turn on, and the stage pass signal ST(n) can be controlled in combination with the clock signal CK(n) to control the working state of the pull-up control module 10 in at least one subsequent gate driving unit 100.
  • the first pull-down sustaining module 40 may further include a fourth pull-down sustaining transistor T72 .
  • the gate of the fourth pull-down sustaining transistor T72 is electrically connected to the gate of the first pull-down sustaining transistor T42 .
  • the fourth pull-down sustaining transistor T72 The source of the first pull-down sustain transistor T42 is electrically connected to the source of the first pull-down sustain transistor T42, and the drain of the fourth pull-down sustain transistor T72 is electrically connected to the drain of the stage pass transistor T22. That is, the fourth pull-down sustain transistor T72 is in the first inverter state.
  • the pull-down of the stage transmission signal ST(n) can be implemented under the control of the forwarding module 402, and can be turned off under the control of the first auxiliary module 401 to avoid continuous operation.
  • the first pull-down sustain transistor T42, the fourth pull-down sustain transistor T72 and the third pull-down sustain transistor T32 can form the first pull-down sustain sub-module 403 to achieve the first node Q(n) and the stage transmission signal ST( n) and the pull-down of the gate signal G(n).
  • the second pull-down maintenance module 50 can also be configured with reference to the first pull-down maintenance module 40 .
  • the second pull-down maintenance module 50 can include a second reverse module 502 and a second pull-down maintenance module 502 .
  • the second reverse module 502 may include a fifth reverse transistor T81, a sixth reverse transistor T82, a seventh reverse transistor T83, and an eighth reverse transistor T84.
  • the fifth reverse transistor T81 may refer to the first reverse transistor T81.
  • the sixth reverse transistor T82 can refer to the setting method of the second reverse transistor T52
  • the seventh reverse transistor T83 can refer to the setting method of the third reverse transistor T53
  • the eighth reverse transistor T84 can refer to
  • the only difference in the arrangement of the fourth reverse transistor T54 is that the first pull-down sustain signal LC1 is replaced by the second pull-down sustain signal LC2; the second pull-down sustain sub-module 503 may include the aforementioned second pull-down sustain transistor T43 and
  • the fifth pull-down sustain transistor T33 can refer to the setting method of the third pull-down sustain transistor T32
  • the sixth pull-down sustain transistor T73 can refer to the setting method of the fourth pull-down sustain transistor T72.
  • the gate driving unit 100 may also include a reset module 70
  • the reset module 70 may include a reset transistor T44
  • the gate of the reset transistor T44 is loaded with the reset signal STV
  • the source of the reset transistor T44 The pole is loaded with the first power signal VSSQ
  • the drain of the reset transistor T44 is electrically connected to the first node Q(n). That is, the reset transistor T44 can be controlled to turn on by the reset signal STV to realize the potential of the first node Q(n). Reset, thereby preventing the potential of the first point Q(n) from being at a high potential for a long time, and reducing the risk of threshold voltage drift of the stage pass transistor T22, for example but not limited to.
  • Embodiments of the present application provide a display panel, which includes a gate driving circuit as described in any one of the above.
  • the present application provides a gate drive circuit and a display panel, including a plurality of cascaded gate drive units.
  • the gate drive unit includes: a pull-up control module; a pull-up module electrically connected to the gate drive unit through a first node.
  • the pull-up control module is electrically connected to the scan line;
  • the pull-down module is electrically connected to the scan line;
  • the first pull-down sustain module includes: a first pull-down sustain transistor, so The drain of the first pull-down sustain transistor is electrically connected to the first node;
  • a first auxiliary module is electrically connected to the gate of the first pull-down sustain transistor, and the first auxiliary module is used to control The first pull-down holding transistor is turned off.
  • a first auxiliary module electrically connected to the gate of the first pull-down holding transistor is provided to control the first pull-down holding transistor to have a closed state, thereby preventing the first pull-down holding transistor from being in an on state for a long time.
  • the resulting threshold voltage shift reduces the risk that the first pull-down holding transistor cannot normally maintain the pull-down of the first node, thereby reducing the risk that the pull-up control module cannot control the scan line to output the correct gate signal, thereby reducing This eliminates the risk of abnormal screen display and improves the quality of screen display.

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Abstract

栅极驱动电路和显示面板，包括级联的多个栅极驱动单元(100)，栅极驱动单元(100)包括上拉控制模块(10)、通过第一节点(Q(n))连接于上拉控制模块(10)且连接于扫描线的上拉模块(20)、连接于扫描线的下拉模块(30)以及第一下拉维持模块(40)、第一辅助模块(401)，第一下拉维持模块(40)中的第一下拉维持晶体管(T42)的栅极、漏极分别连接至第一节点(Q(n))和第一辅助模块(401)。

Description

栅极驱动电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及显示面板制造技术领域，具体涉及栅极驱动电路和显示面板。
 背景技术
GOA(Gate Driver on Array,阵列基板栅极驱动)技术有利于显示屏的窄边框的设计，因此得到了广泛的应用。
其中，下拉维持单元作为每一级GOA电路中必不可少的电路结构，在GOA电路的输出的栅极信号被拉低后可以维持其为低电压，然而，由于实际制程以及电路设计等原因，造成下拉维持单元中的下拉维持晶体管的栅极为正，再叠加下拉维持晶体管而持续工作，造成下拉维持晶体管的阈值电压发生偏移，导致在后期下拉维持晶体管无法正常维持对于栅极信号的拉低，造成栅极信号输出异常，降低了显示面板的显示画面的质量。
因此，现有的GOA电路中下拉维持晶体管会持续工作导致栅极信号输出异常，造成显示面板的显示画面的质量降低，急需改进。
 技术问题
本申请实施例提供栅极驱动电路和显示面板，以解决现有的GOA电路中下拉维持晶体管持续工作导致的栅极信号输出异常的技术问题。
 技术解决方案
本申请实施例提供栅极驱动电路，包括级联的多个栅极驱动单元，所述栅极驱动单元包括：
上拉控制模块；
上拉模块，通过第一节点电性连接于所述上拉控制模块，并电性连接于扫描线；
下拉模块，电性连接于所述扫描线；
第一下拉维持模块，所述第一下拉维持模块包括：
第一下拉维持晶体管，所述第一下拉维持晶体管的漏极电性连接至所述第一节点；
第一辅助模块，电性连接至所述第一下拉维持晶体管的栅极，所述第一辅助模块用于控制所述第一下拉维持晶体管的通断情况。
在一实施例中，所述第一辅助模块包括：
第一辅助晶体管，所述第一辅助晶体管的漏极电性连接至所述第一下拉维持晶体管的所述栅极，所述第一辅助晶体管的源极电性连接于辅助电源线以加载为辅助信号，所述第一辅助晶体管的栅极连接于第一控制信号线以加载为第一控制信号；
其中，所述第一控制信号用于控制所述第一辅助晶体管开启，以通过所述辅助信号控制所述第一下拉维持晶体管的通断情况。
 有益效果
本申请提供了栅极驱动电路和显示面板，包括级联的多个栅极驱动单元，所述栅极驱动单元包括：上拉控制模块；上拉模块，通过第一节点电性连接于所述上拉控制模块，并电性连接于扫描线；下拉模块，电性连接于所述扫描线；第一下拉维持模块，所述第一下拉维持模块包括：第一下拉维持晶体管，所述第一下拉维持晶体管的漏极电性连接至所述第一节点；第一辅助模块，电性连接至所述第一下拉维持晶体管的栅极，所述第一辅助模块用于控制所述第一下拉维持晶体管的通断情况。其中，本申请中通过设置电性连接至所述第一下拉维持晶体管的栅极的第一辅助模块，以控制一下拉维持晶体管具有关闭状态，可以避免第一下拉维持晶体管长期处于开启状态而造成阈值电压偏移，降低了第一下拉维持晶体管无法正常维持对于第一节点的拉低的风险，以降低了上拉控制模块无法控制扫描线输出正确的栅极信号的风险，从而降低了画面显示异常的风险，提高了画面显示的质量。
 附图说明
下面通过附图来对本申请进行进一步说明。需要说明的是，下面描述中的附图仅仅是用于解释说明本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的第一种栅极驱动单元的电路图。
图2为本申请实施例提供的第二种栅极驱动单元的电路图。
图3为本申请实施例提供的第三种栅极驱动单元的电路图。
图4为本申请实施例提供的第四种栅极驱动单元的电路图。
图5为本申请实施例提供的晶体管的转移特性曲线偏移示意图。
图6为本申请实施例提供的晶体管的转移特性曲线偏移后的示意图。
图7为本申请实施例提供的部分信号的波形图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或模块的过程、方法、***、产品或设备没有限定于已列出的步骤或模块，而是可选地还包括没有列出的步骤或模块，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或模块。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请实施例提供了栅极驱动电路，所述栅极驱动电路包括但不限于以下实施例以及以下实施例的组合。
在一实施例中，所述栅极驱动电路包括级联的多个栅极驱动单元，此处第n级栅极驱动单元为例进行说明，如图1至图4所示，第n级栅极驱动单元100包括：上拉控制模块10；上拉模块20，通过第一节点Q(n)电性连接于所述上拉控制模块10，并电性连接于扫描线；下拉模块30，电性连接于所述扫描线；第一下拉维持模块40，所述第一下拉维持模块40包括：第一下拉维持晶体管T42，所述第一下拉维持晶体管T42的漏极电性连接至所述第一节点Q(n)；第一辅助模块401，电性连接至所述第一下拉维持晶体管T42的栅极，所述第一辅助模块401用于控制所述第一下拉维持晶体管T42的通断情况。
具体的，如图1至图4所示，上拉控制模块10可以通过控制第一节点Q(n)的电位以控制上拉模块20工作，从而控制扫描线输出的栅极信号G(n)为对应的工作电压，下拉模块30可以控制扫描线输出的栅极信号G(n)为对应的非工作电压，第一下拉维持模块40可以将第一节点Q(n)维持为之前的电位。进一步的，栅极信号G(n)可以加载至对应的多个子像素上，其中，栅极信号G(n)中的工作电压可以控制对应的多个子像素开启以显示对应的图像，当栅极信号G(n)呈现为对应的非工作电压时，对应的多个子像素可以维持对应的图像，同时下一级栅极信号G(n+1)呈现为对应的工作电压以控制对应的多个子像素开启以显示对应的图像。因此，当栅极信号G(n)不能及时地由对应的工作电压转化为对应的非工作电压时，会导致下一行的多个子像素对应的数据信息再次加载至本行的多个子像素上，造成画面显示异常。
其中，本申请对栅极驱动单元100中的晶体管的类型、每一级栅极信号的工作电压与非工作电压的大小关系不作限定，本申请中仅以栅极驱动单元100中的每一晶体管均为N型晶体管，且第一下拉维持晶体管T42的阈值电压大于或者等于0，且每一级栅极信号的工作电压大于非工作电压为例进行说明。
具体的，如图2至图4所示，上拉控制模块10可以包括上拉控制晶体管T11，上拉控制晶体管T11的栅极加载为第(n-6)级级传信号ST(n-6)，上拉控制晶体管T11的源极加载为第(n-6)级栅极信号G(n-6)，上拉控制晶体管T11的漏极电性连接至第一节点Q(n)；上拉模块20可以包括上拉晶体管T21，上拉晶体管T21的栅极可以电性连接至第一节点Q(n)，上拉晶体管T21的源极可以加载为时钟信号CK(n)，上拉晶体管T21的漏极可以电性连接至扫描线，栅极驱动单元100还可以包括电性连接于上拉晶体管T21的栅极和上拉晶体管T21的漏极之间的自举电容Cbt；下拉模块30可以包括第一下拉晶体管T41和第二下拉晶体管T31，第一下拉晶体管T41的栅极和第二下拉晶体管T31的栅极均加载为第(n+8)级级传信号ST(n+8)，第一下拉晶体管T41的源极可以加载为第一下拉信号，第一下拉晶体管T41的漏极可以电性连接至第一节点(Q)，第二下拉晶体管T31的源极可以加载为第二下拉信号，第二下拉晶体管T31的漏极可以电性连接至扫描线。
基于上文论述，第(n-6)级级传信号ST(n-6)为对应的高电位时，第(n-6)级栅极信号G(n-6)也为对应的高电位，上拉控制晶体管T11开启使得第一节点Q(n)在第(n-6)级级传信号ST(n-6)的作用下上升为第一高电位；此后时钟信号CK(n)为对应的高电位，由于第一节点Q(n)为第一高电位，即上拉晶体管T21开启，扫描线可以输出对应的高电位作为栅极信号G(n)的工作电压，同时在时钟信号CK(n)和自举电容Cbt的作用下，第一节点Q(n)由第一高电位上升为第二高电位；此后第(n+8)级级传信号ST(n+8)为对应的高电位，第一下拉信号可以通过第一下拉晶体管T41下拉第一节点(Q)的电位，第二下拉信号可以通过第二下拉晶体管T31下拉扫描线的电位；此后至少第一下拉维持模块40中的第一下拉维持晶体管T42开启以维持第一节点Q(n)的电位继续下拉。需要注意的是，以上仅对上拉控制模块10、上拉模块20和下拉模块30的电路结构和信号作出举例说明，并不能对本申请中的电路结构和信号作出如上限定。
其中，如图5所示，L1为晶体管的阈值电压未发生偏移时在饱和区的转移特性曲线，基于晶体管的漏极和源极之间的压差恒定的情况下，横坐标表示晶体管的栅极电压Vg，纵坐标表示晶体管的漏极电流Ids，可以发现在晶体管的栅极电压Vg和源极电压Vs的差值大于阈值电压Vth的前提下，即在晶体管的栅极电压Vg大于(Vs+Vth)的前提下，晶体管的漏极电流Ids随着晶体管的栅极电压Vg的增加而增加。结合上文论述，下拉维持模块40中的第一下拉维持晶体管T42的漏极电性连接至第一节点Q(n)，即第一下拉维持晶体管T42在开启状态下可以控制第一节点Q(n)的电位下拉，以控制扫描线输出的栅极信号G(n)维持为对应的非工作电压，在此过程中第一下拉维持晶体管T42呈现为正偏。然而，由于实际制程等原因，在第一下拉维持晶体管T42关闭时，第一下拉维持晶体管T42的栅极电压仍然会等于第一下拉维持晶体管T42的源极电压，造成第一下拉维持晶体管T42持续正偏，结合图5和图6所示，造成下拉维持晶体管T42的阈值电压发生正向偏移为Vth’，从而会造成第一下拉维持晶体管T42的转移特性曲线从L1向右偏移至L2，这样后期第一下拉维持晶体管T42的栅极电压Vg所对应的漏极电流Ids会降低，无法较好的开启下拉维持晶体管T42，导致第一下拉维持晶体管T42无法正常维持对于栅极信号G(n)的拉低，从而造成画面显示异常，并且如图6所示，在晶体管的栅极电压Vg小于(Vs+Vth)的前提下，晶体管的漏极电流Ids仍然存在，导致第一下拉维持晶体管T42无法正常关闭。
可以理解的，本实施例中的第一辅助模块401电性连接至第一下拉维持晶体管T42的栅极，且第一辅助模块401用于控制第一下拉维持晶体管T42关闭，即第一辅助模块401控制第一下拉维持晶体管T42的栅极电压，从而使得第一下拉维持晶体管T42关闭，以避免第一下拉维持晶体管T42长期处于开启状态而造成阈值电压偏移，降低了第一下拉维持晶体管T42无法正常维持对于第一节点Q(n)的拉低的风险，以降低了上拉控制模块10无法控制扫描线输出正确的栅极信号G(n)的风险，从而降低了画面显示异常的风险，提高了画面显示的质量。
在一实施例中，如图2至图3所示，所述第一辅助模块401包括：第一辅助晶体管T62，所述第一辅助晶体管T62的漏极电性连接至所述第一下拉维持晶体管T42的所述栅极，所述第一辅助晶体管T62的源极电性连接于辅助电源线以加载为辅助信号，所述第一辅助晶体管T62的栅极连接于第一控制信号线以加载为第一控制信号；其中，所述第一控制信号用于控制所述第一辅助晶体管T62开启，以通过所述辅助信号控制所述第一下拉维持晶体管T42的通断情况。
可以理解的，基于第一辅助晶体管T62和第一下拉维持晶体管T42均为N型晶体管，当加载至第一辅助晶体管T62的栅极的第一控制信号的电压值大于加载至第一辅助晶体管T62的源极的辅助信号的电压值，且两者的差值的绝对值大于第一辅助晶体管T62的阈值电压时，第一辅助晶体管T62开启。进一步的，结合上文论述，由于第一下拉维持晶体管T42在开启状态下可以控制第一节点Q(n)的电位下拉，即第一下拉维持晶体管T42的源极的电位可以认为小于辅助信号的电压值，且两者的差值的绝对值大于第一下拉维持晶体管T42的阈值电压，即辅助信号可以通过第一辅助晶体管T62加载至第一辅助晶体管T62的栅极，以关闭第一下拉维持晶体管T42，以避免第一下拉维持晶体管T42长期处于开启状态而造成阈值电压偏移，降低了第一下拉维持晶体管T42无法正常维持对于第一节点Q(n)的拉低的风险，以降低了上拉控制模块10无法控制扫描线输出正确的栅极信号G(n)的风险，从而降低了画面显示异常的风险，提高了画面显示的质量。
在一实施例中，如图2至图3所示，所述栅极驱动单元100还包括第二下拉维持模块50，所述第二下拉维持模块50包括：第二下拉维持晶体管T43，所述第二下拉维持晶体管T43的栅极电性连接至第二下拉维持线以加载为第二下拉维持信号LC2，所述第二下拉维持晶体管T43的源极和所述第一下拉维持晶体管T42的源极电性连接至第一电源线以加载第一电源信号VSSQ，所述第二下拉维持晶体管T43的漏极电性连接至所述第一节点Q(n)；其中，所述第二下拉维持信号LC2包括交替排列的高电位和低电位，所述第二下拉维持信号LC2用于控制所述第二下拉维持晶体管T43开启，以通过所述第一电源信号VSSQ控制所述第一节点Q(n)的电位，所述第一控制信号与所述第二下拉维持信号LC2相同。
具体的，结合上文论述可知，第一下拉维持模块40中的第一下拉维持晶体管T42的漏极、第二下拉维持模块50中的第二下拉维持晶体管T43的漏极均电性连接至第一节点Q(n)，即两者均可以将第一节点Q(n)维持为之前的电位。进一步的，所述第二下拉维持信号LC2包括交替排列的高电位和低电位，即本实施例中的加载于第二下拉维持晶体管T43的栅极上的第二下拉维持信号LC2为对应的高电位时可以控制第二下拉维持晶体管T43开启，以使得第一电源信号VSSQ通过第二下拉维持晶体管T43加载至第一节点Q(n)，基于上拉晶体管T21为N型晶体管，第一电源信号VSSQ可以认为是用于拉低第一节点Q(n)的电位的恒压信号，从而关闭上拉晶体管T21。当然，加载至第一下拉维持晶体管T42的源极的第一电源信号VSSQ也可以在第一下拉维持晶体管T42开启时拉低第一节点Q(n)的电位。
结合上文论述，由于第二下拉维持信号LC2中的高电位可以控制第二下拉维持晶体管T43开启。可以理解的，本实施例中的第一控制信号与第二下拉维持信号LC2相同，结合第一控制信号的作用，即此处可以理解为，第二下拉维持信号LC2中的高电位还可以控制第一辅助晶体管T62开启，以通过辅助信号控制第一下拉维持晶体管T42关闭。因此，本实施例中通过将第一控制信号设置为与第二下拉维持信号LC2相同，可以实现于第二下拉维持晶体管T43开启的同时关闭第一下拉维持晶体管T42，一方面可以节省信号的种类，另一方面可以于第二下拉维持晶体管T43开启工作的期间，及时地关闭第一下拉维持晶体管T42以避免第一下拉维持晶体管T42持续工作，可以同时兼顾对于第一节点Q(n)的电位的拉低以及缓解第一下拉维持晶体管T42的阈值电压的偏移。
在一实施例中，如图2所示，所述辅助电源线与所述第一电源线为同一线路。结合上文论述，第一电源线加载有第一电源信号VSSQ，即本实施例中的辅助电源线也加载有第一电源信号VSSQ，以使得第一辅助晶体管T62的源极和第一下拉维持晶体管T42的源极均通过称之为辅助电源线或者第一电源线的同一线路以加载第一电源信号VSSQ。可以理解的，基于第一下拉维持晶体管T42的源极电性连接至第一电源线以加载第一电源信号VSSQ，且第一下拉维持晶体管T42的阈值电压大于或者等于0，本实施例中将第一辅助晶体管T62的源极加载为第一电源信号VSSQ，以使得第一辅助晶体管T62开启时第二下拉维持晶体管T43的栅极的电位等于第一电源信号VSSQ，即第一下拉维持晶体管T42的栅极的电位、源极的电位两者的差值为0，即小于第一下拉维持晶体管T42的阈值电压，可以实现第一下拉维持晶体管T42的关闭。
在一实施例中，如图3所示，所述辅助电源线与所述第一电源线为不同的线路，以使所述辅助信号不同于所述第一电源信号VSSQ。具体的，辅助电源线加载的辅助信号VSSR也可以为恒压信号，结合上文论述，辅助信号控制第一下拉维持晶体管T42关闭，基于第一下拉维持晶体管T42的阈值电压大于或者等于0，即本实施例中的辅助信号VSSR的电压值可以小于第一电源信号VSSQ的电压值，以使第一辅助晶体管T62开启时第一下拉维持晶体管T42的栅极的电位小于第一电源信号VSSQ，即第一下拉维持晶体管T42的栅极的电位小于第一下拉维持晶体管T42的源极，即进一步小于第一下拉维持晶体管T42的阈值电压，结合图5中的曲线L1可知，第一下拉维持晶体管T42的栅极的电位越小，越有利于第一下拉维持晶体管T42的漏极电流Ids的减小，可以更好地实现对于第一下拉维持晶体管T42的关闭。
在一实施例中，如图2至图3所示，所述第二下拉维持模块50还包括：第二辅助模块501，电性连接至所述第二下拉维持晶体管T43的栅极，所述第二辅助模块501用于控制所述第二下拉维持晶体管T43的通断情况。具体的，结合上文论述可知，第二下拉维持晶体管T43的栅极电性连接至第二下拉维持线以加载为第二下拉维持信号LC2，第二下拉维持晶体管T43的源极电性连接至第一电源线以加载第一电源信号VSSQ，第二下拉维持晶体管T43的漏极电性连接至第一节点Q(n)，且第二下拉维持信号LC2中的高电位控制第二下拉维持晶体管T43开启，以通过第一电源信号VSSQ拉低第一节点Q(n)的电位；基于此，本实施例中的第二辅助模块501可以控制第二下拉维持晶体管T43关闭，同理，参考上文关于第一辅助模块401用于控制第一下拉维持晶体管T42关闭的相关描述可知，本实施例中的第二下拉维持晶体管T43的栅极电压可以被第二辅助模块501控制而关闭第二下拉维持晶体管T43，以避免第二下拉维持晶体管T43长期处于开启状态而造成阈值电压偏移，降低了第一下拉维持晶体管T42无法正常维持对于第一节点Q(n)的拉低的风险，以降低了上拉控制模块10无法控制扫描线输出正确的栅极信号G(n)的风险，从而降低了画面显示异常的风险，提高了画面显示的质量。
在一实施例中，如图2至图3所示，所述第二辅助模块501包括：第二辅助晶体管T63，所述第二辅助晶体管T63的漏极电性连接至所述第二下拉维持晶体管T43的所述栅极，所述第二辅助晶体管T63的源极电性连接于所述辅助电源线以加载为所述辅助信号，所述第二辅助晶体管T63的栅极连接于第二控制信号线以加载为第二控制信号；其中，所述第一下拉维持晶体管T42的栅极电性连接至第一下拉维持线以加载为第一下拉维持信号LC1；其中，所述第一下拉维持信号LC1用于控制所述第一下拉维持晶体管T42开启，以通过所述第一电源信号VSSQ控制所述第一节点Q(n)的电位，所述第一下拉维持信号LC1包括交替排列的所述高电位和所述低电位，如图7所示，所述第一下拉维持信号LC1中的所述高电位vgh和所述第二下拉维持信号LC2中的所述低电位vgl对应排列；其中，所述第二控制信号与所述第一下拉维持信号相同LC1。
其中，第二辅助晶体管T63对第二下拉维持晶体管T43的控制方式可以参考上文关于第一辅助晶体管T62对第一下拉维持晶体管T42的控制方式的相关描述。
结合上文论述，第二下拉维持信号LC2为对应的高电位vgh时控制第二下拉维持晶体管T43开启以及控制第一下拉维持晶体管T42关闭，同理，第一下拉维持信号LC1为对应的高电位vgh时控制第一下拉维持晶体管T42开启以及控制第二下拉维持晶体管T43关闭，因此，本实施例中通过将第二控制信号设置为与第一下拉维持信号相同LC1相同，一方面可以节省信号的种类，另一方面可以于第一下拉维持晶体管T42开启工作的期间，及时地关闭第二下拉维持晶体管T43以避免第二下拉维持晶体管T43持续工作，可以同时兼顾对于第一节点Q(n)的电位的拉低以及缓解第二下拉维持晶体管T43的阈值电压的偏移。
进一步的，如图7所示，本实施例中的第一下拉维持信号LC1中的高电位vgh和第二下拉维持信号LC2中的低电位vgl对应排列，相应的，第一下拉维持信号LC1中的低电位vgl和第二下拉维持信号LC2中的高电位vgh对应排列。结合上文论述，第一下拉维持信号LC1中的高电位vgh和第二下拉维持信号LC2中的高电位vgh交错排列，可以使得第一下拉维持晶体管T42和第二下拉维持晶体管T43交替开启，对应的，可以使得第二下拉维持晶体管T43和第一下拉维持晶体管T42交替关闭，实现第一节点Q(n)的电位可以持续拉低的同时，实现第二下拉维持晶体管T43和第一下拉维持晶体管T42交替关闭，以避免两者中的任一者持续工作，降低了两者中的任一者无法正常维持对于第一节点Q(n)的拉低的风险，以降低了上拉控制模块10无法控制扫描线输出正确的栅极信号G(n)的风险，从而降低了画面显示异常的风险，提高了画面显示的质量。
在一实施例中，如图4所示，所述第一辅助模块401包括：控制信号线，加载为控制信号CTR，所述控制信号线电性连接至所述第一下拉维持晶体管T42的所述栅极；其中，所述控制信号CTR包括间隔排列的多个有效电位，每一所述有效电位用于控制所述第一下拉维持晶体管T42的通断情况。具体的，结合上文论述，如图2至图4所示，第一辅助模块401设置为包括第一辅助晶体管T62，并且结合辅助信号和第一控制信号，共同控制第一下拉维持晶体管T42的栅极电压，从而控制第一下拉维持晶体管T42具有关闭的期间。具体的，本实施例中的控制信号CTR可以理解为经由第一辅助晶体管T62、辅助信号和第一控制信号共同作用而产生于第一下拉维持晶体管T42的栅极的信号，可以理解的，当第一辅助晶体管T62、辅助信号和第一控制信号三者及其连接关系确定后，产生于第一下拉维持晶体管T42的栅极的信号也是确定的，即本实施例中的控制信号CTR可以根据例如上述的因素所确定。
具体的，此处以控制信号CTR相同于第一辅助晶体管T62、辅助信号和第一控制信号共同作用产生的信号为例进行说明，控制信号CTR中的每一有效电位可以理解为等于辅助信号的电位，每一有效电位所处的时间段可以对应于第一控制信号控制第一辅助晶体管T62开启的时间段，即本实施例中的控制信号CTR中的每一有效电位作用于第一辅助晶体管T62，相当于辅助信号通过第一辅助晶体管T62作用于第一下拉维持晶体管T42，作用均为关闭第一下拉维持晶体管T42。可以理解的，本实施例中的第一辅助模块401设置为包括加载控制信号CTR的控制信号线，可以节省期间和导线的数量，简化了栅极驱动单元100的电路结构。
对应的，第二辅助模块501可以参考如图2和图3的设置方式，也可以如图4所示，所述第一辅助模块401包括：第三控制信号线，加载为第三控制信号CTR’，所述控制信号线电性连接至所述第二下拉维持晶体管T43的所述栅极；其中，所述第三控制信号CTR’也包括间隔排列的多个所述有效电位，每一所述有效电位用于控制所述第二下拉维持晶体管T43关闭。
在一实施例中，如图2至图4所示，所述第一下拉维持模块40还包括：第一反向模块402，电性连接于所述第一节点Q(n)，并电性连接于所述第一下拉维持晶体管T42的所述栅极，以控制所述第一下拉维持晶体管T42开启。其中，第一反向模块402可以将第一节点Q(n)的电位的相反值输出至第一下拉维持晶体管T42的栅极，例如第一节点Q(n)为对应的低电位时，第一下拉维持晶体管T42的栅极为对应的高电位以打开第一下拉维持晶体管T42，结合上文论述，第一下拉维持晶体管T42开启可以维持第一节点Q(n)的电位继续下拉，又例如第一节点Q(n)为对应的高电位时，第一下拉维持晶体管T42的栅极为对应的高电位无法打开第一下拉维持晶体管T42，无法下拉第一节点Q(n)的电位。
具体的，如图2至图4所示，第一反向模块402可以包括第一反向晶体管T51、第二反向晶体管T52、第三反向晶体管T53和第四反向晶体管T54，第一反向晶体管T51的源极、第一反向晶体管T51的栅极和第三反向晶体管T53的源极加载为第一下拉维持信号LC1，第一反向晶体管T51的漏极电性连接至第三反向晶体管T53的栅极；第二反向晶体管T52的栅极、第四反向晶体管T54的栅极电性连接至第一节点Q(n)，第二反向晶体管T52的漏极、第四反向晶体管T54的漏极加载为第一电源信号VSSQ，第二反向晶体管T52的源极电性连接至第一反向晶体管T51的漏极，第四反向晶体管T54的源极电性连接至第三反向晶体管T53的漏极。结合上文论述，基于第一节点Q(n)为对应的低电位，第一下拉维持信号LC1为对应的高电位时，第二反向晶体管T52和第四反向晶体管T54关闭，第一反向晶体管T51和第三反向晶体管T53开启，以使得第一下拉维持晶体管T42开启，以将第一电源信号VSSQ加载至第一节点Q(n)，实现对于第一节点Q(n)的拉低。
进一步的，如图2至图4所示，第一下拉维持模块40还可以包括第三下拉维持晶体管T32，第三下拉维持晶体管T32的栅极电性连接至第一下拉维持晶体管T42的栅极，第三下拉维持晶体管T32的源极电性连接至第二电源线以加载为第二电源信号VSSG，第三下拉维持晶体管T32的漏极电性连接至扫描线，即第三下拉维持晶体管T32在第一反向模块402的控制下可以实现对于扫描线上的栅极信号G(n)的下拉，并且在第一辅助模块401的控制下可以关闭以避免持续工作。其中，第二电源信号VSSG可以认为是用于拉低栅极信号G(n)的恒压信号，当然，第三下拉维持晶体管T32的源极也可以电性连接至第一下拉维持晶体管T42的源极以共用第一电源信号VSSQ，以节省导线的数量。
具体的，如图2至图4所示，栅极驱动单元100还可以包括级传模块60，级传模块60可以包括级传晶体管T22，级传晶体管T22的栅极电性连接至第一节点Q(n)，级传晶体管T22的源极加载为时钟信号CK(n)，级传晶体管T22的漏极输出为级传信号ST(n)，即通过控制第一节点Q(n)的电位可以控制级传晶体管T22开启，结合时钟信号CK(n)可以控制级传信号ST(n)，以控制后面至少一级栅极驱动单元100中的上拉控制模块10的工作状态。基于此，第一下拉维持模块40还可以包括第四下拉维持晶体管T72，第四下拉维持晶体管T72的栅极电性连接至第一下拉维持晶体管T42的栅极，第四下拉维持晶体管T72的源极电性连接至第一下拉维持晶体管T42的源极，第四下拉维持晶体管T72的漏极电性连接至级传晶体管T22的漏极，即第四下拉维持晶体管T72在第一反向模块402的控制下可以实现对于级传信号ST(n)的下拉，并且在第一辅助模块401的控制下可以关闭以避免持续工作。其中，第一下拉维持晶体管T42、第四下拉维持晶体管T72和第三下拉维持晶体管T32可以组成第一下拉维持子模块403，以实现对于第一节点Q(n)、级传信号ST(n)和栅极信号G(n)的下拉。
同样的，如图2至图4所示，第二下拉维持模块50也可以参考第一下拉维持模块40设置，具体的，第二下拉维持模块50可以包括第二反向模块502和第二下拉维持子模块503。其中，第二反向模块502可以包括第五反向晶体管T81、第六反向晶体管T82、第七反向晶体管T83和第八反向晶体管T84，第五反向晶体管T81可以参考第一反向晶体管T51的设置方式，第六反向晶体管T82可以参考第二反向晶体管T52的设置方式，第七反向晶体管T83可以参考第三反向晶体管T53的设置方式，第八反向晶体管T84可以参考第四反向晶体管T54的设置方式，区别仅在于将第一下拉维持信号LC1替换为第二下拉维持信号LC2；第二下拉维持子模块503可以包括前文提及的第二下拉维持晶体管T43以及第五下拉维持晶体管T33、第六下拉维持晶体管T73，第五下拉维持晶体管T33可以参考第三下拉维持晶体管T32的设置方式，第六下拉维持晶体管T73可以参考第四下拉维持晶体管T72的设置方式。
进一步的，如图2至图4所示，栅极驱动单元100还可以包括复位模块70，复位模块70可以包括复位晶体管T44，复位晶体管T44的栅极加载为复位信号STV，复位晶体管T44的源极加载为第一电源信号VSSQ，复位晶体管T44的漏极电性连接至第一节点Q(n)，即可以通过复位信号STV控制复位晶体管T44开启以实现对第一节点Q(n)的电位复位，从而避免第一点Q(n)的电位长时间处于高电位，降低例如但不限于级传晶体管T22出现阈值电压漂移的风险。
本申请实施例提供了显示面板，所述显示面板包括如上文任一所述的栅极驱动电路。
本申请提供了栅极驱动电路和显示面板，包括级联的多个栅极驱动单元，所述栅极驱动单元包括：上拉控制模块；上拉模块，通过第一节点电性连接于所述上拉控制模块，并电性连接于扫描线；下拉模块，电性连接于所述扫描线；第一下拉维持模块，所述第一下拉维持模块包括：第一下拉维持晶体管，所述第一下拉维持晶体管的漏极电性连接至所述第一节点；第一辅助模块，电性连接至所述第一下拉维持晶体管的栅极，所述第一辅助模块用于控制所述第一下拉维持晶体管关闭。其中，本申请中通过设置电性连接至所述第一下拉维持晶体管的栅极的第一辅助模块，以控制一下拉维持晶体管具有关闭状态，可以避免第一下拉维持晶体管长期处于开启状态而造成阈值电压偏移，降低了第一下拉维持晶体管无法正常维持对于第一节点的拉低的风险，以降低了上拉控制模块无法控制扫描线输出正确的栅极信号的风险，从而降低了画面显示异常的风险，提高了画面显示的质量。
以上对本申请实施例所提供的栅极驱动电路和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种栅极驱动电路，其中，包括级联的多个栅极驱动单元，所述栅极驱动单元包括：
    上拉控制模块；
    上拉模块，通过第一节点电性连接于所述上拉控制模块，并电性连接于扫描线；
    下拉模块，电性连接于所述扫描线；
    第一下拉维持模块，所述第一下拉维持模块包括：
    第一下拉维持晶体管，所述第一下拉维持晶体管的漏极电性连接至所述第一节点；
    第一辅助模块，电性连接至所述第一下拉维持晶体管的栅极，所述第一辅助模块用于控制所述第一下拉维持晶体管的通断情况；
    其中，所述第一辅助模块包括：
    第一辅助晶体管，所述第一辅助晶体管的漏极电性连接至所述第一下拉维持晶体管的所述栅极，所述第一辅助晶体管的源极电性连接于辅助电源线以加载为辅助信号，所述第一辅助晶体管的栅极连接于第一控制信号线以加载为第一控制信号，所述第一控制信号用于控制所述第一辅助晶体管开启，以通过所述辅助信号控制所述第一下拉维持晶体管的通断情况；
    其中，所述第一辅助模块包括：
    控制信号线，加载为控制信号，所述控制信号线电性连接至所述第一下拉维持晶体管的所述栅极，所述控制信号包括间隔排列的多个有效电位，每一所述有效电位用于控制所述第一下拉维持晶体管的通断情况。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括第二下拉维持模块，所述第二下拉维持模块包括：
    第二下拉维持晶体管，所述第二下拉维持晶体管的栅极电性连接至第二下拉维持线以加载为第二下拉维持信号，所述第二下拉维持晶体管的源极和所述第一下拉维持晶体管电性连接至第一电源线以加载第一电源信号，所述第二下拉维持晶体管的漏极电性连接至所述第一节点；
    其中，所述第二下拉维持信号包括交替排列的高电位和低电位，所述第二下拉维持信号用于控制所述第二下拉维持晶体管开启，以通过所述第一电源信号控制所述第一节点的电位，所述第一控制信号与所述第二下拉维持信号相同。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述辅助电源线与所述第一电源线为同一线路。
  4. 根据权利要求2所述的栅极驱动电路，其中，所述辅助电源线与所述第一电源线为不同的线路，以使所述辅助信号不同于所述第一电源信号。
  5. 根据权利要求2所述的栅极驱动电路，其中，所述第二下拉维持模块还包括：
    第二辅助模块，电性连接至所述第二下拉维持晶体管的栅极，所述第二辅助模块用于控制所述第二下拉维持晶体管的通断情况。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述第二辅助模块包括：
    第二辅助晶体管，所述第二辅助晶体管的漏极电性连接至所述第二下拉维持晶体管的所述栅极，所述第二辅助晶体管的源极电性连接于所述辅助电源线以加载为所述辅助信号，所述第二辅助晶体管的栅极连接于第二控制信号线以加载为第二控制信号；
    其中，所述第一下拉维持晶体管的栅极电性连接至第一下拉维持线以加载为第一下拉维持信号；
    其中，所述第一下拉维持信号用于控制所述第一下拉维持晶体管开启，以通过所述第一电源信号控制所述第一节点的电位，所述第一下拉维持信号包括交替排列的所述高电位和所述低电位，所述第一下拉维持信号中的所述高电位和所述第二下拉维持信号中的所述低电位对应排列；
    其中，所述第二控制信号与所述第一下拉维持信号相同。
  7. 根据权利要求1所述的栅极驱动电路，其中，所述第一下拉维持模块还包括：
    第一反向模块，电性连接于所述第一节点，并电性连接于所述第一下拉维持晶体管的所述栅极，以控制所述第一下拉维持晶体管开启。
  8. 一种栅极驱动电路，其中，包括级联的多个栅极驱动单元，所述栅极驱动单元包括：
    上拉控制模块；
    上拉模块，通过第一节点电性连接于所述上拉控制模块，并电性连接于扫描线；
    下拉模块，电性连接于所述扫描线；
    第一下拉维持模块，所述第一下拉维持模块包括：
    第一下拉维持晶体管，所述第一下拉维持晶体管的漏极电性连接至所述第一节点；
    第一辅助模块，电性连接至所述第一下拉维持晶体管的栅极，所述第一辅助模块用于控制所述第一下拉维持晶体管的通断情况。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述第一辅助模块包括：
    第一辅助晶体管，所述第一辅助晶体管的漏极电性连接至所述第一下拉维持晶体管的所述栅极，所述第一辅助晶体管的源极电性连接于辅助电源线以加载为辅助信号，所述第一辅助晶体管的栅极连接于第一控制信号线以加载为第一控制信号；
    其中，所述第一控制信号用于控制所述第一辅助晶体管开启，以通过所述辅助信号控制所述第一下拉维持晶体管的通断情况。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述栅极驱动电路还包括第二下拉维持模块，所述第二下拉维持模块包括：
    第二下拉维持晶体管，所述第二下拉维持晶体管的栅极电性连接至第二下拉维持线以加载为第二下拉维持信号，所述第二下拉维持晶体管的源极和所述第一下拉维持晶体管电性连接至第一电源线以加载第一电源信号，所述第二下拉维持晶体管的漏极电性连接至所述第一节点；
    其中，所述第二下拉维持信号包括交替排列的高电位和低电位，所述第二下拉维持信号用于控制所述第二下拉维持晶体管开启，以通过所述第一电源信号控制所述第一节点的电位，所述第一控制信号与所述第二下拉维持信号相同。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述辅助电源线与所述第一电源线为同一线路。
  12. 根据权利要求10所述的栅极驱动电路，其中，所述辅助电源线与所述第一电源线为不同的线路，以使所述辅助信号不同于所述第一电源信号。
  13. 根据权利要求10所述的栅极驱动电路，其中，所述第二下拉维持模块还包括：
    第二辅助模块，电性连接至所述第二下拉维持晶体管的栅极，所述第二辅助模块用于控制所述第二下拉维持晶体管的通断情况。
  14. 根据权利要求10所述的栅极驱动电路，其中，所述第二辅助模块包括：
    第二辅助晶体管，所述第二辅助晶体管的漏极电性连接至所述第二下拉维持晶体管的所述栅极，所述第二辅助晶体管的源极电性连接于所述辅助电源线以加载为所述辅助信号，所述第二辅助晶体管的栅极连接于第二控制信号线以加载为第二控制信号；
    其中，所述第一下拉维持晶体管的栅极电性连接至第一下拉维持线以加载为第一下拉维持信号；
    其中，所述第一下拉维持信号用于控制所述第一下拉维持晶体管开启，以通过所述第一电源信号控制所述第一节点的电位，所述第一下拉维持信号包括交替排列的所述高电位和所述低电位，所述第一下拉维持信号中的所述高电位和所述第二下拉维持信号中的所述低电位对应排列；
    其中，所述第二控制信号与所述第一下拉维持信号相同。
  15. 根据权利要求10所述的栅极驱动电路，其中，所述第一辅助模块包括：
    控制信号线，加载为控制信号，所述控制信号线电性连接至所述第一下拉维持晶体管的所述栅极；
    其中，所述控制信号包括间隔排列的多个有效电位，每一所述有效电位用于控制所述第一下拉维持晶体管的通断情况。
  16. 根据权利要求10所述的栅极驱动电路，其中，所述第一下拉维持模块还包括：
    第一反向模块，电性连接于所述第一节点，并电性连接于所述第一下拉维持晶体管的所述栅极，以控制所述第一下拉维持晶体管开启。
  17. 一种显示面板，其中，所述显示面板包括如权利要求8所述的栅极驱动电路。
  18. 根据权利要求17所述的显示面板，其中，所述第一辅助模块包括：
    第一辅助晶体管，所述第一辅助晶体管的漏极电性连接至所述第一下拉维持晶体管的所述栅极，所述第一辅助晶体管的源极电性连接于辅助电源线以加载为辅助信号，所述第一辅助晶体管的栅极连接于第一控制信号线以加载为第一控制信号；
    其中，所述第一控制信号用于控制所述第一辅助晶体管开启，以通过所述辅助信号控制所述第一下拉维持晶体管的通断情况。
  19. 根据权利要求18所述的显示面板，其中，所述栅极驱动电路还包括第二下拉维持模块，所述第二下拉维持模块包括：
    第二下拉维持晶体管，所述第二下拉维持晶体管的栅极电性连接至第二下拉维持线以加载为第二下拉维持信号，所述第二下拉维持晶体管的源极和所述第一下拉维持晶体管电性连接至第一电源线以加载第一电源信号，所述第二下拉维持晶体管的漏极电性连接至所述第一节点；
    其中，所述第二下拉维持信号包括交替排列的高电位和低电位，所述第二下拉维持信号用于控制所述第二下拉维持晶体管开启，以通过所述第一电源信号控制所述第一节点的电位，所述第一控制信号与所述第二下拉维持信号相同。
  20. 根据权利要求19所述的显示面板，其中，所述辅助电源线与所述第一电源线为同一线路。
PCT/CN2022/087288 2022-03-24 2022-04-18 栅极驱动电路和显示面板 WO2023178771A1 (zh)

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