WO2023169345A1 - 数据模拟任务的处理方法、装置、电子设备及存储介质 - Google Patents
数据模拟任务的处理方法、装置、电子设备及存储介质 Download PDFInfo
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- G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
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- the embodiments of this specification relate to the field of data processing, and specifically relate to a processing method, device, electronic equipment and storage medium for data simulation tasks.
- data can be used to simulate transactions in the real world.
- the simulation of the change process of transactions in the real world can be realized. .
- Quantum simulation has a wide range of applications: research on many-body localization, time crystals, high-temperature superconductivity, and topological order in condensed matter physics; molecular dynamics simulation and reaction simulation in quantum chemistry; field theory simulation in high-energy physics; and even related research in nuclear physics and cosmology.
- Quantum computer is a type of physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers therefore have the ability to handle mathematical problems more efficiently than ordinary computers.
- the embodiments of this specification provide a processing method, device, electronic equipment and storage medium for data simulation tasks to solve the problem of difficulty in using classical computers to simulate the Hamiltonian of a quantum mechanical system.
- An embodiment of the present specification provides a method for processing a data simulation task.
- the processing method includes: obtaining target data of the data simulation task; wherein the data simulation task is to simulate a Hamiltonian; the target data is a Hamiltonian.
- the amount of time H is expressed in the form of a square matrix and is independent of time; the operation process is executed according to the target data and the specified operation conditions to obtain the calculation data of the data simulation task; wherein, the operation process is calculation;
- a collection of quantum circuits is constructed for simulation, and when the similarity between the circuit matrix corresponding to the quantum circuit and the calculation data meets specified conditions, the simulation data obtained by the simulation of the quantum circuit is used as the target data.
- the operation process includes: performing eigenvalue decomposition or singular value decomposition on the square matrix A to obtain the decomposition result A'; and calculating e iA' based on Taylor's formula and Euler's formula.
- the calculation data is a calculation result matrix B; the step of decomposing the calculation data into a set of finite quantum gates includes: converting non-zero values in the calculation result matrix B The element subscripts are converted into binary representations; wherein, the calculation result matrix B is a square matrix and the non-0 elements in the square matrix are complex numbers; according to the binary representation of the non-0 element subscripts in the calculation result matrix B, Each item in the calculation result matrix B is expanded and re-expressed as a matrix B'; according to the value of the sub-item in each item of the matrix B', the sub-items in each item of the matrix B' are determined.
- the logic gate type corresponding to the item.
- constructing a quantum circuit for simulation based on the limited set of quantum gates includes:
- the logic gate type corresponding to the sub-item in each item in the matrix B' determine the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit; wherein, the quantum sub-circuit corresponds to the calculation result matrix B non-zero elements; construct the quantum circuit according to the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit.
- the non-0 elements in the calculation result matrix B are B kj ; where k and j respectively correspond to the row subscripts and column subscripts of the non-0 elements; S is the calculation result The set of non-zero elements in the result matrix B, s is the non-zero element in the calculation result matrix B Iteration index of 0 elements; the binary representation of the subscripts of non-0 elements in the calculation result matrix B is:
- n is the number of decimal row subscripts or decimal column subscripts converted to binary
- m is an integer between 1 and n. .
- the values of the sub-items in each item of the matrix B' are
- the step of determining the logic gate type corresponding to the sub-item in each item of the matrix B' according to the value of the sub-item in each item of the matrix B' includes:
- X is the Pauli X gate
- Y is the Pauli Y gate
- Z is the Pauli Z gate
- I is the I gate
- i is an imaginary number.
- the step of determining the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to the sub-item in each item in the matrix B' includes: The logic gate type corresponding to each item in the matrix B' determines the quantum sub-circuit; according to the value of the matrix corresponding to the quantum sub-circuit and the value of the non-0 element in the matrix B', the quantum sub-circuit is determined. The coefficient corresponding to the quantum subcircuit.
- the step of determining the coefficients corresponding to the quantum sub-circuit based on the values of the matrix corresponding to the quantum sub-circuit and the values of non-zero elements in the matrix B' includes: Execute the specified division operation, and use the operation result of the division operation as the coefficient corresponding to the quantum sub-circuit; wherein the specified division operation is to divide the value of the non-0 element in the matrix B' by the corresponding coefficient of the quantum sub-circuit The value of the matrix.
- determining the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to the sub-item in each item in the matrix B' also includes: determining the existence of The same quantum sub-circuit; merge the same quantum sub-circuit; where, the coefficient of the merged quantum sub-circuit is the sum of the corresponding coefficients of each quantum sub-circuit before the merger.
- decomposing the calculation data into a set of limited quantum gates includes: confirming that the calculation data is a unitary matrix; in the case that the calculation data is a unitary matrix, based on Hao
- the Scholder transform decomposes the computational data into a collection of single-qubit gates and controlled NOT gates.
- the method further includes: operating the quantum circuit according to a preset quantum operation object; wherein the operation object is a set of operation instructions of the quantum circuit.
- the set of operating instructions for the quantum circuit includes: instructions for obtaining the corresponding matrix of the quantum circuit; instructions for assembling the quantum circuit into program code; and determining the Instructions where the quantum circuit corresponding matrix is a unitary matrix; instructions for operating the quantum circuit corresponding matrix; instructions for operating the quantum circuit.
- a quantum circuit is constructed for simulation based on the limited set of quantum gates, until the similarity between the circuit matrix corresponding to the quantum circuit and the calculated data satisfies the specified conditions, the step of using the simulated data obtained according to the simulation as the target data includes: according to the dimension of the circuit matrix U corresponding to the quantum circuit Or the dimensions of the calculation result matrix B, the line matrix U and the calculation result matrix B, and obtain the process fidelity from the calculation result matrix B to the line matrix U; wherein, the quantum circuit corresponds to The line matrix U is a square matrix; according to the dimensions of the line matrix U or the dimensions of the calculation result matrix B and the process fidelity from the calculation result matrix B to the line matrix U, calculate the line matrix U and The similarity of the calculation result matrix B; when the similarity between the line matrix U and the calculation result matrix B meets the specified conditions, the simulation data obtained according to the quantum circuit simulation is used as the Hamiltonian H.
- the simulation data obtained by the quantum circuit simulation is used as the Hamiltonian H
- the step includes: when the similarity F ave_fid (B, U) of the circuit matrix U and the calculation result matrix B satisfies the following inequality, using the simulation data obtained according to the quantum circuit simulation as the Hamlet Day amount H:
- the obtained The steps of calculating the process fidelity from the result matrix B to the line matrix U include: calculating the matrix B1; where, dim(B) is the dimension of the calculation result matrix B; calculate the conjugate matrix U1 of the line matrix U; use the norm value after the dot multiplication of the matrix B1 and the conjugate matrix U1 as the calculation result matrix B to the process fidelity of the line matrix U.
- res is the dot product result of the matrix B1 and the conjugate matrix U1
- res_vec is the row-expanded vector of res
- l is the square of the dimension of the calculation result matrix B
- 2 is the matrix B1 The norm value after dot multiplication with the conjugate matrix U1.
- the line matrix U and the line matrix U are calculated based on the dimensions of the line matrix U or the dimensions of the calculation result matrix B and the process fidelity of the calculation result matrix B to the line matrix U.
- the step of calculating the similarity of the result matrix B includes: calculating the similarity of the line matrix U and the calculation result matrix B through the following formula:
- F ave_fid (B, U) is the similarity between the line matrix U and the calculation result matrix B
- F state_fid (B, U) is the process fidelity from the calculation result matrix B to the line matrix U.
- the method further includes: before obtaining the process fidelity of the calculation result matrix B to the line matrix U, confirming the dimensions of the line matrix U and the calculation result matrix The dimensions of B are consistent.
- the processing device includes: an acquisition module for acquiring target data of the data simulation task; wherein the data simulation task is a simulated Hamiltonian;
- the target data is the Hamiltonian H, H is expressed in the form of a square matrix and is independent of time;
- the operation module is used to perform the operation process according to the target data and specified operation conditions to obtain the calculation data of the data simulation task; wherein the operation process is to calculate e iA ;
- the calculation data is expressed in the form of a square matrix;
- the decomposition module is used to decompose the calculation data into a set of finite quantum gates ;
- Building module used to construct a quantum circuit for simulation based on the set of limited quantum gates, until the similarity between the circuit matrix corresponding to the quantum circuit and the calculation data meets the specified conditions, according to The simulation data obtained by the quantum circuit simulation is used as target data.
- One embodiment of the present specification provides an electronic device, including a memory and a processor.
- a computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above. method.
- One embodiment of the present specification provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute any of the methods described above when running.
- this application obtains the target data of the data simulation task, performs the operation process according to the target data and specified operation conditions, obtains the calculation data of the data simulation task, and decomposes the calculation data into finite numbers.
- a set of quantum gates to construct a quantum circuit for simulation based on the limited set of quantum gates. When the similarity between the circuit matrix corresponding to the quantum circuit and the calculation data meets the specified conditions, the quantum circuit will be constructed according to the specified conditions.
- the simulation data obtained by the quantum circuit simulation is used as target data to simulate the evolution of the Hamiltonian, which solves the technical problem of difficulty in using classical computers to simulate the Hamiltonian.
- Figure 1 is a hardware structure block diagram of a computer terminal for a data simulation task processing method provided by an embodiment of this specification
- Figure 2 is a schematic diagram of a quantum circuit display method provided by the embodiment of this specification.
- Figure 3 is a schematic flowchart of a method for processing a data simulation task provided by an embodiment of this specification
- Figure 4 is a schematic flowchart of another method for processing a data simulation task provided by an embodiment of this specification
- FIG. 5 is a schematic flowchart of another data simulation task processing method provided by the embodiment of this specification.
- FIG. 6 is a schematic structural diagram of a data simulation task processing device provided in an embodiment of this specification.
- One embodiment of this specification provides a method for processing data simulation tasks, which method can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.
- Figure 1 is a hardware structure block diagram of a computer terminal of a data simulation task processing method provided by an embodiment of this specification.
- the computer terminal may include one or more (only one is shown in Figure 1) processors 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a microprocessor (Microprocessor). Controller Unit, MCU) or programmable logic device (Field Programmable Gate Array, FPGA) and other processing devices.
- the above-mentioned computer terminal may also include a transmission device 106 for communication functions and an input and output device 108.
- Figure 1 is only illustrative, and it does not limit the structure of the above-mentioned computer terminal.
- the computer terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than shown in FIG. 1 .
- the memory 104 can be used to store software programs and modules of application software, such as the program instructions/modules corresponding to the processing method for implementing a data simulation task in the embodiment of this specification.
- the processor 102 runs the software programs stored in the memory 104 and module to perform various functional applications and data processing, that is, to implement the above method.
- Memory 104 may include high-speed random access memory and may also include non-volatile Volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
- the memory 104 may further include memory located remotely relative to the processor 102, and these remote memories may be connected to the computer terminal through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.
- the transmission device 106 is used to receive or send data via a network.
- Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of the computer terminal.
- the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station to communicate with the Internet.
- the transmission device 106 may be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.
- RF Radio Frequency
- a real quantum computer is a hybrid structure, which consists of two parts: one part is a classical computer, responsible for performing classical calculations and control; the other part is a quantum device, responsible for running quantum programs to achieve quantum computing.
- a quantum program is a sequence of instructions written in a quantum language such as QRunes that can be run on a quantum computer. It supports quantum logic gate operations and ultimately realizes quantum computing.
- a quantum program is a series of instruction sequences that operate quantum logic gates in a certain time sequence.
- Quantum computing simulation is a process in which a virtual architecture (i.e., quantum virtual machine) built with the resources of ordinary computers is used to realize the simulated operation of quantum programs corresponding to specific problems. Often, a quantum program corresponding to a specific problem needs to be constructed.
- the quantum program referred to in the implementation mode of this specification is a program written in classical language that represents qubits and their evolution. Among them, qubits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.
- quantum circuits are also called quantum logic circuits. They are the most commonly used universal quantum computing model. They represent circuits that operate on qubits under an abstract concept. Its components include qubits, circuits (timelines) , and various quantum logic gates, and finally the results often need to be read out through quantum measurement operations.
- the way quantum circuits are displayed can be a sequence of quantum logic gates arranged in a certain time sequence. Specifically, for example:
- a quantum program as a whole corresponds to a total quantum circuit.
- the quantum program mentioned in this specification refers to the total quantum circuit, where the total number of qubits in the total quantum circuit is the same as the total number of qubits in the quantum program. It can be understood as: a quantum program can be composed of quantum circuits, measurement operations for qubits in the quantum circuit, registers to save measurement results, and control flow nodes (jump instructions).
- a quantum circuit can contain dozens, hundreds or even thousands of Tens of thousands of quantum logic gate operations.
- the execution process of a quantum program is a process of executing all quantum logic gates in a certain time sequence. It should be noted that timing is the time sequence in which a single quantum logic gate is executed.
- Quantum logic gates are the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates, such as Hadamard gates (H gates, Hadamard gates) and Pauli-X gates. (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, etc.; multi-bit quantum logic gates, such as CNOT gate, CR gate, iSWAP Doors, Toffoli doors, etc.
- Quantum logic gates are generally represented by unitary matrices, which are not only matrix forms, but also operations and transformations. Generally, the effect of a quantum logic gate on a quantum state is calculated by multiplying the unitary matrix on the left by the matrix corresponding to the right vector of the quantum state.
- the basic unit of information is a bit, and a bit has two states: 0 and 1.
- the most common physical implementation method is to represent these two states through the high and low levels.
- the basic unit of information is a qubit.
- a qubit also has two states, 0 and 1, recorded as
- the state of the qubit will collapse to a certain state (eigenstate, here
- 2 1, and
- Quantum state refers to the state of a quantum bit, and its eigenstate is expressed in binary in a quantum algorithm (or quantum program).
- a group of qubits is q0, q1, q2, which represents the 0th, 1st, and 2nd qubits. The order from high to low is q2q1q0.
- the quantum state of this group of qubits is 2 3 eigenstates.
- the superposition state of Each eigenstate corresponds to the qubit bit, such as
- a quantum state is a superposition of eigenstates. When the probability amplitude of other states is 0, it is in one of the certain eigenstates.
- Figure 3 is a schematic flowchart of a method for processing a data simulation task provided by an embodiment of this specification, including steps S110 to S140, wherein:
- the target data of the data simulation task is to simulate a Hamiltonian
- the target data is a Hamiltonian H, where H is expressed in the form of a square matrix and is independent of time.
- the Heisenberg model is a very important model in the research of quantum magnetism and quantum many-body physics.
- the Hamiltonian H to be simulated in the Heisenberg model can be written as the following formula:
- ⁇ i, j> depends on the specific grid geometric structure
- J x , J y , and J z are the spin coupling strengths in the three directions of xyz, respectively
- h z is the external magnetic field in the z direction.
- ⁇ and P are Pauli operators, and they can also be represented by XYZ operators.
- Each element of the Hamiltonian H is in complex form, that is, each element contains a real part and an imaginary part.
- step S120 is executed.
- e -iHt there are many ways to calculate e -iHt , mainly due to different simulation approximation algorithms, and t generally defaults to 1.
- Taylor's formula and Euler's formula can be used to approximately calculate e iA
- Padé's approximate calculation can be used to calculate e iA .
- this implementation performs the decomposition operation on A in advance. Since A is a square matrix, perform singular value decomposition (SVD) or eigenvalue decomposition on the square matrix A; where the decomposition result is A’. Take singular value decomposition as an example to illustrate.
- SVD singular value decomposition
- eigenvalue decomposition eigenvalue decomposition
- Singular value decomposition is an important matrix decomposition in linear algebra and has important applications in signal processing, statistics and other fields.
- a n ⁇ n For the square matrix A n ⁇ n , after singular value decomposition, it can be represented by the multiplication of three matrices:
- U is an n ⁇ n order unitary matrix, also called a left singular vector matrix
- ⁇ is an r ⁇ n order nonnegative real diagonal matrix
- V * the conjugate transpose of V, is an n ⁇ n order unitary matrix.
- This decomposition is called the singular value decomposition of A, and the elements on the ⁇ diagonal are the singular values of A.
- step S130 is executed.
- decomposing the computational data into a limited set of quantum gates may include the following steps:
- the calculation data of the data simulation task can be the calculation result matrix B of e iA .
- B is a square matrix.
- the non-zero elements in the square matrix B are B kj . k and j respectively correspond to the row subscripts and column subscripts of B kj .
- the square Array B can be expressed as Among them, S is the set of non-zero elements in square matrix B, which can also be understood as the number of terms of the linear combination before merging coefficients; s is the iteration index of non-zero elements in square matrix B, which can also be understood as the number of non-zero elements in square matrix B. 0 elements.
- non-zero element B kj subscript in square matrix B can be converted into the following binary representation:
- n is the number of decimal row subscripts or decimal column subscripts converted to binary
- m is an integer between 1 and n.
- each item in the square matrix B is each item in the set of non-zero elements in the square matrix B.
- the value of can only be 0 or 1
- the value of can only be 0 or 1. That is, for each sub-item in matrix B′ Its value can only be one of
- each value corresponds to a logic gate type formed by a combination of Pauli gates and I gates (second-order identity matrix).
- the corresponding relationship is as follows:
- i an imaginary number.
- S1304 Determine the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to the sub-item in each item in the matrix B′.
- the quantum sub-circuit corresponds to a non-zero element.
- step S1304 may include the following steps:
- the logic gates in the logic gate type act on the qubits in time sequence to construct a quantum circuit.
- the matrix B′′ corresponding to the constructed quantum circuit is represented as follows:
- L is the set of Pauli operator sub-circuits
- l is the iteration index of Pauli operator sub-circuits
- ⁇ refers to the sub-circuit.
- S13042 Determine the coefficient corresponding to the quantum sub-circuit based on the value of the matrix corresponding to the quantum sub-circuit and the value of the non-zero element.
- the coefficient corresponding to the quantum sub-circuit can be determined by the following calculation method: dividing the value of the non-zero element by the value of the matrix corresponding to the quantum sub-circuit, the quantum sub-circuit and coefficient corresponding to the non-zero element can be obtained.
- step S1304 may also include the following steps:
- step S13042 it is necessary to determine whether the same quantum sub-circuit exists. If the same quantum sub-circuit exists, step S13044 is executed. If the same quantum sub-circuit does not exist, step S140 is performed.
- the coefficient of the quantum sub-circuit after merging is the sum of the corresponding coefficients of each quantum circuit before merging.
- step S140 can be performed to construct the quantum circuit for simulation.
- a complete quantum circuit can be constructed by encoding the coefficients into quantum sub-circuits and connecting each quantum sub-circuit in time sequence.
- the following determination may also be performed: determining whether the calculation result of e iA is a unitary matrix. If it is not a unitary matrix, the calculation result of e iA is directly decomposed into a linear combination of a limited number of Pauli gates. If it is a unitary matrix, the calculation result of e iA is decomposed into a set of single qubit gates and controlled NOT gates based on Householder transformation.
- the decomposition process is as follows:
- e iA is a unitary matrix B
- n is the number of qubits contained in the quantum circuit to be encoded
- H j is unitary
- the unitary matrix corresponding to the quantum logic gate satisfies Among them, U m is the unitary matrix corresponding to the (m+1)th single quantum logic gate carrying controlled information, 0 ⁇ m ⁇ 2 n-1 -1; it is determined to contain the 2 n-1 controlled information carrying
- the sequence of single quantum logic gates is the sub-quantum circuit Cir R .
- step S140 can be performed to construct a quantum circuit based on the set of limited quantum gates. That is, according to the unitary matrix corresponding to the single quantum logic gate carrying controlled information and the sequence of single quantum logic gate carrying controlled information, the sub-quantum circuits Cir R , Cir N-1 ,...Cir j ,... are connected in sequence. , Cir 1 generates a quantum circuit corresponding to the unitary matrix B.
- S140 Construct a quantum circuit for simulation based on the set of limited quantum gates. When the similarity between the circuit matrix corresponding to the quantum circuit and the calculation data meets specified conditions, the quantum circuit will be constructed according to the set of quantum gates. The simulated data obtained from the simulation is used as target data.
- the operation instruction set of the quantum circuit includes: instructions for obtaining the constructed corresponding matrix of the quantum circuit; instructions for assembling the quantum circuit into program code; and determining whether the quantum circuit corresponding matrix is a unitary matrix. Instructions; instructions for operating the corresponding matrix of the quantum circuit; instructions for operating the quantum circuit.
- the program code may be OriginIR of Origin Quantum Company, or may be a program corresponding to IBM's OpenQASM or other quantum application software. Instructions for operating the quantum circuit may include instructions for inserting logic gates, applying transposed conjugation and controlled operations, adding control bits, measuring, etc.
- whether the Hamiltonian is effectively simulated by the quantum circuit can be measured by calculating the similarity of the matrix.
- a square matrix is a matrix with the same number of rows and columns, and the dimensions of a square matrix are the number of rows or columns. You can determine whether the number of rows and columns of the line matrix U are the same and whether the number of rows and columns of the calculation result matrix B are the same. If the number of rows and columns of the line matrix U are the same and the number of rows and columns of the calculation result matrix B If they are the same, it is determined that the line matrix U and the calculation result matrix B are both square matrices. Next, it is determined whether the number of rows or columns of the line matrix U is the same as the number of rows or columns of the calculation result matrix B. If the number of rows or columns of the line matrix U is the same as the number of rows or columns of the calculation result matrix B, it is determined that the dimensions of the line matrix U and the calculation result matrix B are consistent, and S1601 is continued.
- the process fidelity is a fidelity measurement value of two matrices, which is used to measure the fidelity relationship between the two matrices.
- the line matrix U and the calculation result matrix B obtaining the process fidelity from the calculation result matrix B to the line matrix U may include the following steps:
- dim(B) is the dimension of the calculation result matrix B.
- the norm value is the process fidelity from the calculation result matrix B to the line matrix U.
- res_vec (res 1 , res 2 ,..., res i ,...res n )
- n is the square of the dimension of the calculation result matrix B.
- the norm value is obtained by the following formula:
- 2 is the norm value, that is, the process fidelity from the calculation result matrix B to the line matrix U.
- step S220 After obtaining the process fidelity from the calculation result matrix B to the line matrix U, step S220 is executed.
- S220 Calculate the line matrix U and the calculation result matrix according to the dimension of the line matrix U or the dimension of the calculation result matrix B and the process fidelity from the calculation result matrix B to the line matrix U.
- B is similarity.
- F ave_fid (B, U) is the similarity between the line matrix U and the calculation result matrix B
- F state_fid (B, U) is the process fidelity from the calculation result matrix B to the line matrix U.
- step S230 After obtaining the similarity between the line matrix U and the calculation result matrix B, step S230 can be performed.
- the Hamiltonian H to be simulated is effectively simulated by the quantum circuit, including:
- ⁇ is the threshold, and the value can be set manually.
- the simulation degree of the calculation data can be determined after obtaining the calculation data of the data simulation task, so as to improve the processing level of the data simulation task.
- Figure 6 is a schematic structural diagram of a data simulation task processing device provided in an embodiment of this specification.
- the device may include:
- the first acquisition module 410 is used for the target data of the data simulation task; wherein the data simulation task is to simulate the Hamiltonian; the target data is the Hamiltonian H, which is expressed in the form of a square matrix and is independent of time. ;
- Decomposition module 430 used to decompose the calculation data into a set of limited quantum gates
- the construction module 440 is used to construct a quantum circuit for simulation based on the set of limited quantum gates. When the similarity between the circuit matrix corresponding to the quantum circuit and the calculation data meets specified conditions, the circuit will be constructed according to the specified conditions. The simulation data obtained by the quantum circuit simulation is used as target data.
- computing module 420 may include:
- the first decomposition unit is used to perform eigenvalue decomposition or singular value decomposition on the square matrix A; where the decomposition result is A';
- the calculation unit is used to calculate e iA′ based on Taylor's formula and Euler's formula.
- the calculation result is the calculation result matrix B; the decomposition module 430 includes:
- a conversion unit used to convert the non-zero element subscripts in the calculation result matrix B into binary representation
- the second decomposition unit is used to expand and re-express each item in the calculation result matrix B into a matrix B' according to the binary representation of the non-zero element subscript in the calculation result matrix B;
- the first determination unit is used to determine the logic gate type corresponding to the sub-item in each item of the matrix B' based on the value of the sub-item in each item of the matrix B';
- the second determination unit is used to determine the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to the sub-item in each item in the matrix B'; wherein the quantum sub-circuit corresponds to non-0 element.
- decomposition module 430 may also include:
- a confirmation unit used to confirm whether the calculation result is a unitary matrix
- the third decomposition unit is configured to decompose the calculation result into a set of single qubit gates and controlled NOT gates based on Householder transformation when the calculation result is a unitary matrix.
- the data simulation task processing device further includes:
- An operation module configured to operate the constructed quantum circuit according to a preset quantum operation object, wherein the operation object is a set of operation instructions for the quantum circuit.
- the set of operating instructions for the quantum circuit includes: instructions for obtaining the constructed corresponding matrix of the quantum circuit; instructions for assembling the quantum circuit into program code; and instructions for judging the quantum circuit. Instructions for determining whether the line corresponding matrix is a unitary matrix; instructions for operating the quantum circuit corresponding matrix; instructions for operating the quantum circuit.
- the Hamiltonian simulation device 400 also includes:
- the second acquisition module is used to obtain the calculation result matrix according to the dimensions of the line matrix corresponding to the constructed quantum circuit or the dimensions of the calculation result matrix corresponding to the calculation result, the line matrix and the calculation result matrix. process fidelity to said line matrix;
- a second calculation module configured to calculate the line matrix and the calculation result matrix according to the dimensions of the line matrix or the dimensions of the calculation result matrix and the process fidelity from the calculation result matrix to the line matrix. similarity;
- a confirmation module configured to confirm that the Hamiltonian is effectively simulated by the quantum circuit based on the similarity between the circuit matrix and the calculation result matrix.
- Embodiments of this specification also provide an electronic device, including a memory and a processor.
- a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any of the above embodiments. .
- the above-mentioned electronic device may also include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.
- processors there may be one or more processors in the electronic device.
- the processor can be implemented in hardware or software.
- the processor may be a logic circuit, an integrated circuit, or the like.
- the processor may be a general-purpose processor implemented by reading software code stored in memory.
- the memory may be integrated with the processor or may be provided separately from the processor, which is not limited by this application.
- the memory can be a non-transient processor, such as a read-only memory ROM, which can be integrated on the same chip as the processor, or can be separately provided on different chips.
- This application describes the type of memory, and the relationship between the memory and the processor. There is no specific limitation on how the processor is configured.
- the electronic device may be a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or a System On Chip (SoC). It can also be a central processing unit (Central Processor Unit, CPU), a network processor (Network Processor, NP), a digital signal processing circuit (Digital Signal Processor, DSP), or a microcontroller (Micro Controller Unit (MCU), or a programmable logic device (PLD) or other integrated chip.
- FPGA Field Programmable Gate Array
- ASIC Application Specific Integrated Circuit
- SoC System On Chip
- CPU Central Processor Unit
- NP Network Processor
- DSP Digital Signal Processor
- MCU Micro Controller Unit
- PLD programmable logic device
- the processor in the embodiment of this specification can be a central processing unit (Central Processing Unit, CPU), and the processor can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), special integrated Circuit (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
- a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
- non-volatile memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
- non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase electrically programmable read-only memory (EPROM, EEPROM) or flash memory.
- Volatile memory can be random access memory (RAM), which is used as an external cache.
- RAM random access memory
- static random access memory static random access memory
- DRAM dynamic random access memory
- RAM synchronous dynamic random access memory
- SDRAM synchronous dynamic random access memory
- double data rate SDRAM double data rate SDRAM
- DDR SDRAM double data rate SDRAM
- enhanced SDRAM enhanced synchronous dynamic random access memory
- SLDRAM synchronous connection dynamic random access memory access memory
- direct rambus RAM direct rambus RAM, DR RAM
- the embodiments of this specification also provide a quantum computer operating system, which realizes the simulation of a Hamiltonian according to any of the above method embodiments provided in the embodiments of the present invention.
- the embodiments of this specification also provide a quantum computer, which includes the above-mentioned quantum computer operating system.
- Embodiments of this specification also provide a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any of the above embodiments when running.
- the above-mentioned storage medium may include but is not limited to: U disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), mobile hard disk, magnetic disk Or various media such as optical discs that can store computer programs.
- the above embodiments may be implemented in whole or in part by software, hardware (such as circuits), firmware, or any other combination.
- the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
- the computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on the computer, the processes or functions described in the embodiments of the present application are generated in whole or in part.
- the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
- the computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmit to another website, computer, server or data center through wired (such as infrared, wireless, microwave, etc.) means.
- the computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server or a data center that contains one or more sets of available media.
- the usable media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, DVD), or semiconductor media.
- the semiconductor medium may be a solid state drive.
- At least one refers to one or more, and “plurality” refers to two or more.
- At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
- at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
- the size of the sequence numbers of the above-mentioned processes does not mean the order of execution.
- the execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application.
- the implementation process constitutes any limitation.
- the disclosed systems, devices and methods can be implemented in other ways.
- the device embodiments described above are only illustrative.
- the division of the units is only a logical function division. In actual implementation, there may be other division methods.
- multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
- the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
- the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
- each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
- the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
- the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product.
- the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
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Abstract
一种数据模拟任务的处理方法、装置、电子设备和存储介质,所述方法包括:获取数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量(S110);根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据(S120);将所述计算数据分解为有限个量子门的集合(S130);根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据(S140)。该方法能够实现利用量子线路对哈密顿量进行模拟,以解决利用经典计算机难以模拟哈密顿量的问题。
Description
本说明书实施方式涉及数据处理领域,具体涉及一种数据模拟任务的处理方法、装置、电子设备及存储介质。
在数据处理领域,通过建立数据模拟任务,可以利用数据模拟现实世界中的事务,通过输入初始数据并执行数据模拟任务的处理过程以得到输出数据,实现对现实世界中的事务的变化过程的模拟。
量子力学中***的能量由哈密顿量算符H描述,求解给定***的哈密顿量的全部或者部分性质,构成了凝聚态物理、计算化学和高能物理等一系列学科的核心问题。量子模拟的应用十分广泛:凝聚态物理中的多体局域化、时间晶体、高温超导、拓扑序的研究;量子化学中的分子动力学模拟、反应模拟;高能物理中的场论模拟;乃至核物理和宇宙学中的相关研究。
但是,***的自由度随***增大呈指数级增加,导致一般情况下无法利用经典计算机有效模拟量子***。
量子计算机是一类遵循量子力学规律进行高速数学和逻辑运算、存储及处理量子信息的物理装置。当某个装置处理和计算的是量子信息,运行的是量子算法时,它就是量子计算机。量子计算机因此具有相对普通计算机更高效的处理数学问题的能力。
因此,需要提供一种能够在通用量子计算机上进行数字量子模拟(digital quantum simulation)——利用量子门构造量子线路以实现量子模拟的方法。
发明内容
本说明书实施方式提供了一种数据模拟任务的处理方法、装置、电子设备及存储介质,以解决难以利用经典计算机模拟量子力学***的哈密顿量的问题。
本说明书的一个实施方式提供了一种数据模拟任务的处理方法,所述处理方法包括:获取数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量;所述目标数据为哈密顿量H,H以方阵形式表示,且与时间相互独立;根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据;其中,所述运算过程为计算;所述指定运算条件为A为方阵且A=-Ht,t为常数;所述计算数据以方阵形式表示;将所述计算数据分解为有限个量子门的集合;根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据。
本说明书的另一个实施方式中,所述运算过程包括:对方阵A进行特征值分解或奇异值分解以得到分解结果A';基于泰勒公式和欧拉公式,计算eiA′。
本说明书的另一个实施方式中,所述计算数据为计算结果矩阵B;所述将所述计算数据分解为有限个量子门的集合的步骤,包括:将所述计算结果矩阵B中的非0元素下标转换成二进制表示形式;其中,所述计算结果矩阵B为方阵且方阵中的非0元素为复数;根据所述计算结果矩阵B中的非0元素下标的二进制表示形式,将所述计算结果矩阵B中的每一项展开并重新表示为矩阵B';根据所述矩阵B'的每一项中的子项的值,确定所述矩阵B'的每一项中的子项对应的逻辑门类型。
本说明书的另一个实施方式中,所述根据所述有限个量子门的集合,构建量子线路以进行模拟,包括:
根据所述矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数;其中,所述量子子线路对应于所述计算结果矩阵B中的非0元素;根据所述量子子线路和所述量子子线路对应的系数,构建所述量子线路。
本说明书的另一个实施方式中,所述计算结果矩阵B中的非0元素为Bkj;其中,k、j分别对应所述非0元素的行下标和列下标;S为所述计算结果矩阵B中非0元素的集合,s为所述计算结果矩阵B中非
0元素的迭代指标;所述计算结果矩阵B中的非0元素下标的二进制表示形式为:
所述计算结果矩阵B的表示形式为:
矩阵B'的表示形式为:
其中,n为十进制行下标或十进制列下标换算为二进制后的位数,m为1和n之间的整数。。
本说明书的另一个实施方式中,所述矩阵B'的每一项中的子项的值为|0><0|、|0><1|、|1><0|、|1><1|中的一种;
所述根据所述矩阵B'的每一项中的子项的值,确定所述矩阵B'的每一项中的子项对应的逻辑门类型的步骤,包括:
根据下述公式表示的所述子项的值与所述逻辑门类型之间的对应关系,确定所述矩阵B'的每一项中的子项对应的逻辑门类型;
其中,X为泡利X门,Y为泡利Y门,Z为泡利Z门,I为I门,i为虚数。
本说明书的另一个实施方式中,所述根据所述矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数的步骤,包括:根据矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路;根据所述量子子线路对应矩阵的值,以及所述矩阵B'中的非0元素的值,确定所述量子子线路对应的系数。
本说明书的另一个实施方式中,所述根据所述量子子线路对应矩阵的值,以及所述矩阵B'中的非0元素的值,确定所述量子子线路对应的系数的步骤,包括:执行指定除运算,将所述除运算的运算结果作为所述量子子线路对应的系数;其中,所述指定除运算为将矩阵B'中的非0元素的值除以所述量子子线路对应矩阵的值。
本说明书的另一个实施方式中,所述根据所述矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数,还包括:确定存在相同的量子子线路;合并相同的量子子线路;其中,合并后的量子子线路的系数为合并前各量子子线路对应系数之和。
本说明书的另一个实施方式中,所述将所述计算数据分解为有限个量子门的集合,包括:确认所述计算数据为酉矩阵;在所述计算数据是酉矩阵的情况下,基于豪斯霍尔德变换将所述计算数据分解为单量子位门和受控NOT门的集合。
本说明书的另一个实施方式中,所述方法还包括:根据预设的量子操作对象操作所述量子线路;其中,所述操作对象为所述量子线路的操作指令集合。
本说明书的另一个实施方式中,所述量子线路的操作指令集合包括:用于获取所述量子线路对应矩阵的指令;用于将所述量子线路汇编为程序代码的指令;用于判断所述量子线路对应矩阵为酉矩阵的指令;用于操作所述量子线路对应矩阵的指令;用于操作所述量子线路的指令。
本说明书的另一个实施方式中,根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述
量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述模拟得到的模拟数据作为目标数据的步骤,包括:根据所述量子线路对应的线路矩阵U的维度或所述计算结果矩阵B的维度、所述线路矩阵U以及所述计算结果矩阵B,获取所述计算结果矩阵B到所述线路矩阵U的过程保真度;其中,所述量子线路对应的线路矩阵U为方阵;根据所述线路矩阵U的维度或所述计算结果矩阵B的维度以及所述计算结果矩阵B到所述线路矩阵U的过程保真度,计算所述线路矩阵U和所述计算结果矩阵B的相似度;在所述线路矩阵U和所述计算结果矩阵B的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为所述哈密顿量H。
本说明书的另一个实施方式中,在所述线路矩阵U和所述计算结果矩阵B的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为所述哈密顿量H的步骤,包括:在所述线路矩阵U和所述计算结果矩阵B的相似度Fave_fid(B,U)满足以下不等式的情况下,将根据所述量子线路模拟得到的模拟数据作为所述哈密顿量H:
|Fave_fid(B,U)-1|<α
|Fave_fid(B,U)-1|<α
其中,α为阈值;B=e-iHt。
本说明书的另一个实施方式中,所述根据所述量子线路对应的线路矩阵U的维度或计算数据对应的计算结果矩阵B的维度、所述线路矩阵U以及所述计算结果矩阵B,获取所述计算结果矩阵B到所述线路矩阵U的过程保真度的步骤,包括:计算矩阵B1;其中,dim(B)为所述计算结果矩阵B的维度;计算所述线路矩阵U的共轭矩阵U1;将所述矩阵B1和所述共轭矩阵U1点乘后的范数值作为所述计算结果矩阵B到所述线路矩阵U的过程保真度。
本说明书的另一个实施方式中,所述方法还包括:所述矩阵B1和所述共轭矩阵U1点乘后的范数值通过以下算式得到:
res=B1·U1
res_vec=(res1,res2,...,resi,...resl)
res=B1·U1
res_vec=(res1,res2,...,resi,...resl)
其中,res为所述矩阵B1和共轭矩阵U1的点乘结果,res_vec为res按行展开后的向量,l为计算结果矩阵B的维度的平方,||res||2为所述矩阵B1和所述共轭矩阵U1点乘后的范数值。
本说明书的另一个实施方式中,所述根据所述线路矩阵U的维度或计算结果矩阵B的维度以及计算结果矩阵B到所述线路矩阵U的过程保真度,计算所述线路矩阵U和所述计算结果矩阵B的相似度的步骤,包括:通过以下算式计算所述线路矩阵U和所述计算结果矩阵B的相似度:
Fstate_fid(B,U)=||res||2
其中,Fave_fid(B,U)为所述线路矩阵U和所述计算结果矩阵B的相似度,Fstate_fid(B,U)为所述计算结果矩阵B到所述线路矩阵U的过程保真度。
本说明书的另一个实施方式中,所述方法还包括:在获取所述计算结果矩阵B到所述线路矩阵U的过程保真度之前,确认所述线路矩阵U的维度和所述计算结果矩阵B的维度一致。
本说明书的一个实施方式提供了一种数据模拟任务的处理装置,所述处理装置包括:获取模块,用于获取数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量;所述目标数据为哈密顿量H,
H以方阵形式表示,且与时间相互独立;运算模块,用于根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据;其中,所述运算过程为计算eiA;所述指定运算条件为A为方阵且A=-Ht,t为常数;所述计算数据以为方阵形式表示;分解模块,用于将所述计算数据分解为有限个量子门的集合;构建模块,用于根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据。
本说明书的一个实施方式提供了一种电子设备,包括存储器和处理器,所述存储器中存储有计算机程序,所述处理器被设置为运行所述计算机程序以执行上述任一项中所述的方法。
本说明书的一个实施方式提供了一种存储介质,所述存储介质中存储有计算机程序,其中,所述计算机程序被设置为运行时执行上述任一项中所述的方法。
与相关技术相比,本申请通过获取数据模拟任务的目标数据,根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据,并将所述计算数据分解为有限个量子门的集合,以根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据,以实现对哈密顿量的演化模拟,解决了难以利用经典计算机模拟哈密顿量的技术问题。
为了更清楚地说明本说明书实施方式或相关技术中的技术方案,下面将对实施方式或相关技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本说明书的一些实施方式,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本说明书实施方式提供的一种数据模拟任务的处理方法的计算机终端的硬件结构框图;
图2为本说明书实施方式提供的一种量子线路的展示方式的示意图;
图3为本说明书实施方式提供的一种数据模拟任务的处理方法的流程示意图;
图4为本说明书实施方式提供的另一种数据模拟任务的处理方法的流程示意图;
图5为本说明书实施方式提供的另一种数据模拟任务的处理方法的流程示意图;
图6为本说明书实施方式提供的一种数据模拟任务的处理装置的结构示意图。
下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
本说明书的一个实施方式提供了一种数据模拟任务的处理方法,该方法可以应用于电子设备,如计算机终端,具体如普通电脑、量子计算机等。
下面以运行在计算机终端上为例对其进行详细说明。图1为本说明书实施方式提供的一种数据模拟任务的处理方法的计算机终端的硬件结构框图。如图1所示,计算机终端可以包括一个或多个(图1中仅示出一个)处理器102和用于存储数据的存储器104,其中,处理器102可以包括但不限于微处理器(Micro Controller Unit,MCU)或可编程逻辑器件(Field Programmable Gate Array,FPGA)等的处理装置。在一些实施方式中,上述计算机终端还可以包括用于通信功能的传输装置106以及输入输出设备108。本领域普通技术人员可以理解,图1所示的结构仅为示意,其并不对上述计算机终端的结构造成限定。例如,计算机终端还可包括比图1中所示更多或者更少的组件,或者具有与图1所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块,如本说明书实施方式中的实现一种数据模拟任务的处理方法对应的程序指令/模块,处理器102通过运行存储在存储器104内的软件程序以及模块,从而执行各种功能应用以及数据处理,即实现上述的方法。存储器104可包括高速随机存储器,还可包括非易
失性存储器,如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中,存储器104可进一步包括相对于处理器102远程设置的存储器,这些远程存储器可以通过网络连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端的通信供应商提供的无线网络。在一个实例中,传输装置106包括一个网络适配器(Network Interface Controller,NIC),其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中,传输装置106可以为射频(Radio Frequency,RF)模块,其用于通过无线方式与互联网进行通讯。
需要说明的是,真正的量子计算机是混合结构的,它包含两大部分:一部分是经典计算机,负责执行经典计算与控制;另一部分是量子设备,负责运行量子程序进而实现量子计算。而量子程序是由量子语言如QRunes语言编写的一串能够在量子计算机上运行的指令序列,实现了对量子逻辑门操作的支持,并最终实现量子计算。具体的说,量子程序就是一系列按照一定时序操作量子逻辑门的指令序列。
在实际应用中,因受限于量子设备硬件的发展,通常需要进行量子计算模拟以验证量子算法、量子应用等等。量子计算模拟即借助普通计算机的资源搭建的虚拟架构(即量子虚拟机)实现特定问题对应的量子程序的模拟运行的过程。通常,需要构建特定问题对应的量子程序。本说明书实施方式所指量子程序,即是经典语言编写的表征量子比特及其演化的程序,其中与量子计算相关的量子比特、量子逻辑门等等均有相应的经典代码表示。
量子线路作为量子程序的一种体现方式,也称量子逻辑电路,是最常用的通用量子计算模型,表示在抽象概念下对于量子比特进行操作的线路,其组成包括量子比特、线路(时间线),以及各种量子逻辑门,最后常需要通过量子测量操作将结果读取出来。
量子线路的展现方式可以是按一定时序排列的量子逻辑门序列,具体的,例如:
q0:RX(q0)、H(q0)、CNOT(q0,q2)、X(q0)
q1:X(q1)、RY(q1)、H(q1)、CNOT(q2,q1)
q2:H(q2)、X(q2)、CNOT(q0,q2)、CNOT(q2,q1)、RZ(q2)
与上述量子逻辑门序列对应的量子线路的更为形象的一种展现方式,参照图2所示。
不同于传统电路是用金属线所连接以传递电压信号或电流信号,在量子线路中,线路可看成是由时间所连接,亦即量子比特的状态随着时间自然演化,在这过程中按照哈密顿运算符的指示,一直到遇上逻辑门而***作。
一个量子程序整体上对应有一条总的量子线路,本说明书所述量子程序即指该条总的量子线路,其中,该总的量子线路中的量子比特总数与量子程序的量子比特总数相同。可以理解为:一个量子程序可以由量子线路、针对量子线路中量子比特的测量操作、保存测量结果的寄存器及控制流节点(跳转指令)组成,一条量子线路可以包含几十上百个甚至千上万个量子逻辑门操作。量子程序的执行过程,就是对所有的量子逻辑门按照一定时序执行的过程。需要说明的是,时序即单个量子逻辑门被执行的时间顺序。
需要说明的是,经典计算中,最基本的单元是比特,而最基本的控制模式是逻辑门,可以通过逻辑门的组合来达到控制电路的目的。类似地,处理量子比特的方式就是量子逻辑门。使用量子逻辑门,能够使量子态发生演化,量子逻辑门是构成量子线路的基础,量子逻辑门包括单比特量子逻辑门,如Hadamard门(H门,哈德玛门)、泡利-X门(X门)、泡利-Y门(Y门)、泡利-Z门(Z门)、RX门、RY门、RZ门等等;多比特量子逻辑门,如CNOT门、CR门、iSWAP门、Toffoli门等等。量子逻辑门一般使用酉矩阵表示,而酉矩阵不仅是矩阵形式,也是一种操作和变换。一般量子逻辑门在量子态上的作用是通过酉矩阵左乘以量子态右矢对应的矩阵进行计算的。
本领域技术人员可以理解的是,在经典计算机中,信息的基本单元是比特,一个比特有0和1两种状态,最常见的物理实现方式是通过电平的高低来表示这两种状态。在量子计算中,信息的基本单元是量子比特,一个量子比特也有0和1两种状态,记为|0>和|1>,但它可以处于0和1两种状态的叠加态,可表示
为其中,a、b为表示|0>态、|1>态振幅(概率幅)的复数,这是经典比特不具备的。测量后,量子比特的状态会塌缩至一个确定的状态(本征态,此处为|0>态、|1>态),其中,塌缩至|0>的概率是|a|2,塌缩至|1>的概率是|b|2,|a|2+|b|2=1,|>为狄拉克符号。
量子态,即指量子比特的状态,其本征态在量子算法(或称量子程序)中用二进制表示。例如,一组量子比特为q0、q1、q2,表示第0位、第1位、第2位量子比特,从高位到低位排序为q2q1q0,该组量子比特的量子态为23个本征态的叠加态,8个本征态(确定的状态)是指:|000>、|001>、|010>、|011>、|100>、|101>、|110>、|111>,每个本征态与量子比特位对应一致,如|000>态,000从高位到低位对应q2q1q0。简言之,量子态是各本征态组成的叠加态,当其他态的概率幅为0时,即处于其中一个确定的本征态。
下面对本说明书实施方式提供的一种数据模拟任务的处理方法作进一步描述说明。
参见图3,图3是本说明书一实施方式提供的一种数据模拟任务的处理方法流程示意图,包括步骤S110至S140,其中:
S110,获取数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量;所述目标数据为哈密顿量H,H以方阵形式表示,且与时间相互独立。
模拟一个量子***的性质,是量子计算机的重要应用之一。一般来说,分析一个量子***的性质需要先写出其哈密顿量,而对于不同尺度下的物理***而言,这个哈密顿量往往具有不同的形式。以量子化学为例,一个分子的性质主要由电子-电子之间的库伦相互作用而决定,因此,其哈密顿量中的每一项都是由作用在电子波函数上的费米子算符写成的。而量子计算机的基本组成单元量子比特(qubit)以及常用的泡利算符,对应着物理上的自旋和自旋算符。
以海森堡(Heisenberg)模型为例,海森堡模型是量子磁性以及量子多体物理研究中十分重要的一个模型。海森堡模型的待模拟哈密顿量H可以写为如下算式:
其中,<i,j>取决于具体的格点几何结构,Jx、Jy、Jz分别为xyz三个方向上的自旋耦台强度,hz是z方向上的外加磁场。若取Jz=0,上述海森堡模型的哈密顿量H算式也可以用来描述XY模型的哈密顿量;若取Jx=Jy=0,海森堡模型的待模拟哈密顿量H算式则可以用来描述伊辛(Ising)模型的哈密顿量。注意在这里,我们使用了量子多体物理里面比较常用的多体自旋算符它是一个作用在多体波函数上的算符。对于自旋-1/2***而言,多体自旋算符可以被简单地写为如下形式泡利算符的张量积形式(省略一个的系数):
其中,σ、P是泡利算符,也可以用XYZ算符来表示它们。
在获得一个量子***的算式表达后,可以通过设置算式中的参数获得哈密顿量H的矩阵表示形式,在该矩阵表示形式是方阵表示形式的情况下,则可以作为本实施方式中的目标数据。例如,哈密顿量H的阶数N=2n,n为待编码量子线路包含的量子比特数。
哈密顿量H的每一个元素都是复数形式,即每一个元素包含实部和虚部。
在获取数据模拟任务的目标数据后,执行步骤S120。
S120,根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据;其中,所述运算过程为计算eiA;所述指定运算条件为A为方阵且A=-Ht,t为常数;所述计算数据以方阵形式表示。
由于哈密顿量H与时间相互独立,t可以为常数,比如可以设置t=1。通过哈密顿量H放在指数上模拟,从而可以在物理***上操作不同的哈密顿量,就可以实现从初态到末态的时间演化。
计算e-iHt的方法有很多,主要是模拟近似算法的不同,同时t一般默认为1。比如,可以使用泰勒公式和欧拉公式近似计算eiA,也可以使用帕德近似计算eiA。以下以泰勒公式和欧拉公式为例对计算eiA的方法进行具体说明:
eiA=cos A+i sin A
eiA=cos A+i sin A
为减少计算量,本实施方式对A提前做分解操作。由于A是方阵,对方阵A进行奇异值分解(Singular Value Decomposition,SVD)或特征值分解;其中,分解结果为A’。以奇异值分解为例进行阐述。
奇异值分解是线性代数中一种重要的矩阵分解,在信号处理、统计学等领域有重要应用。对于方阵An×n经过奇异值分解后,可以由3个矩阵相乘来表示:
其中,U是n×n阶酉矩阵,也叫左奇异向量矩阵;∑是r×n阶非负实数对角矩阵;而V*,即V的共轭转置,是n×n阶酉矩阵,也叫右奇异向量矩阵。这样的分解就称作A的奇异值分解,∑对角线上的元素即为A的奇异值。
将方阵A进行奇异值分解后,进行乘方计算操作,就只需对分解后的对角矩阵∑做乘方计算,也就是对对角矩阵∑中的主对角元素做乘方计算,这就大大简化了计算量,并降低了时间复杂度和空间复杂度。
eiA的计算结果也为方阵表示形式,在得到数据模拟任务的计算数据后,执行步骤S130。
S130:将所述计算数据分解为有限个量子门的集合。
参见图4。在一些实施方式中,将计算数据分解为有限个量子门的集合可以包括如下步骤:
S1301,将方阵B中的非0元素下标转换成二进制表示形式。数据模拟任务的计算数据可以为eiA的计算结果矩阵B,B为方阵,方阵B中非零元素为Bkj,k、j分别对应Bkj的行下标和列下标,则方阵B可以表示为其中,S为方阵B中非0元素的集合,也可以理解为未合并系数前的线性组合的项数;s为方阵B中非0元素的迭代指标,也可以理解为第几个非0元素。
其中,方阵B中的非零元素Bkj下标可以转换成如下的二进制表示形式:
其中,n为十进制行下标或十进制列下标换算为二进制后的位数,m为1和n之间的整数。
S1302,根据方阵B中的非0元素下标的二进制表示形式,将方阵B中的每一项展开并重新表示为矩阵B′。其中,方阵B中的每一项为方阵B中非0元素集合中的每一项。
将方阵B的每一项展开后,重新表示后的矩阵B′的表示形式如下:
S1303,根据矩阵B′的每一项中的子项的值,确定矩阵B′的每一项中的子项对应的逻辑门类型。
根据矩阵B′的表示形式,其中,的值只可能是0或1,的值也只可能是0或1。也就是说,对于矩阵B′中的每一项中的子项其值只能为|0><0|、|0><1|、|1><0|、|1><1|中的一种。
根据矩阵B′中的每一项中的子项取值状况,则可以定义每一种取值对应一个由泡利门和I门(2阶单位矩阵)组合形成的逻辑门类型。对应关系如下所示:
其中,i表示虚数。
S1304,根据矩阵B′中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数。
其中,所述量子子线路对应于非0元素。
具体地,步骤S1304可以包括如下步骤:
S13041,根据矩阵B′中每一项中的子项对应的逻辑门类型,确定量子子线路;
定义有限个需要经量子逻辑门作用的量子比特,根据矩阵B′中每一项中的子项对应的逻辑门类型,将逻辑门类型中的逻辑门按照时序作用在量子比特上以构建量子线路。
构建的量子线路对应的矩阵B″表示形式如下:
其中,L为泡利算符子线路的集合,l为泡利算符子线路的迭代指标,ω代指子线路。
S13042,根据所述量子子线路对应矩阵的值,以及非0元素的值,确定所述量子子线路对应的系数。
所述量子子线路对应的系数可以通过如下计算方式确定:将非0元素的值除以所述量子子线路对应矩阵的值,就可以得到该非0元素对应的量子子线路和系数。
由于集合的基本性质包括独立性、互异性和无序性。即,对于集合中的所有元素,不存在两个相同的元素。因此,可选地,步骤S1304还可以包括如下步骤:
S13043,确定存在相同的量子子线路。
即在执行完步骤S13042后,需要判断是否存在相同的量子子线路。如果存在相同的量子子线路,则执行步骤S13044。如果不存在相同的量子子线路,则执行步骤S140。
S13044,将相同的量子子线路合并为一项。
其中,合并后量子子线路的系数为合并前各量子线路对应系数之和。
在确定量子子线路和所述量子子线路对应的系数后,就可以执行步骤S140,构建量子线路以进行模拟。此时,可以通过将系数编码到量子子线路后,按照时序连接各个量子子线路,进而构建成完整的量子线路。
与相关技术相比,基于图4所示出的将计算数据分解为有限个量子门的集合的方法,通过将矩阵中的非0元素下标转换成二进制表示形式,根据矩阵中的每一项展开后的子项对应的逻辑门类型确定量子子线路和所述量子子线路对应的系数,为后续构建量子线路提供了基础。由于该方法只要求矩阵是方阵,没有矩阵为密度矩阵或者厄米矩阵等其它要求,从而实现了对任意方阵类型的复数矩阵的泡利算符分解解决了相关技术中存在的难以将矩阵编码成对应的量子线路的技术问题。
在一些实施方式中,在执行步骤S130之前,也可以先执行如下判断:判断eiA的计算结果是否为酉矩阵。如果不是酉矩阵,则将eiA的计算结果直接分解为有限个泡利门的线性组合。如果是酉矩阵,则基于豪斯霍尔德变换将eiA的计算结果分解为单量子位门和受控NOT门的集合,分解过程如下:
假设eiA的计算结果为酉矩阵B,B的阶数N=2n,n为待编码量子线路包含的量子比特数;基于豪斯霍尔德变换确定对角矩阵R和(N-1)个豪斯霍尔德矩阵使酉矩阵B=H1H2…Hj…HN-1R,其中,Hj为酉
矩阵B第j次豪斯霍尔德变换时对应的豪斯霍尔德矩阵,1≤j≤N-1;将所述对角矩阵R拆分成2n-1个携带受控信息的单量子逻辑门对应的酉矩阵,且满足其中,Um为第(m+1)个携带受控信息的单量子逻辑门对应的酉矩阵,0≤m≤2n-1-1;确定包含所述2n-1个携带受控信息的单量子逻辑门的序列为所述子量子线路CirR。此时,可以执行步骤S140,根据所述有限个量子门的集合,构建量子线路。即根据携带受控信息的单量子逻辑门对应的酉矩阵以及携带受控信息的单量子逻辑门的序列,依次连接子量子线路CirR、CirN-1、...Cirj、...、Cir1生成与酉矩阵B对应的量子线路。
S140,根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据。
定义有限个需要经量子逻辑门作用的量子比特,通过将集合中的量子门按照时序作用在量子比特上以构建量子线路。
构建量子线路后,可以通过操作量子线路进行模拟。
本说明书实施方式提供的数据模拟任务的处理方法还可以包括如下步骤:
S150,根据预设的量子操作对象操作构建的所述量子线路,其中,所述操作对象为所述量子线路的操作指令集合。
所述量子线路的操作指令集合包括:用于获取构建的所述量子线路对应矩阵的指令;用于将所述量子线路汇编为程序代码的指令;用于判断所述量子线路对应矩阵是否酉矩阵的指令;用于操作所述量子线路对应矩阵的指令;用于操作所述量子线路的指令。
其中,所述程序代码可以是本源量子公司的OriginIR,也可以是IBM公司的OpenQASM或者其它量子应用软件对应的程序。操作所述量子线路的指令可以包括***逻辑门、施加转置共轭和受控操作、添加控制比特、测量等指令。
参见图5。在一些实施方式中,在得到数据模拟任务的计算数据后,可以通过计算矩阵的相似度来衡量哈密顿量是否被量子线路有效模拟。
计算矩阵相似度来衡量哈密顿量是否被量子线路有效模拟的方法可以包括如下步骤:
S210,根据构建的所述量子线路对应的线路矩阵U的维度或所述计算结果矩阵B的维度、所述线路矩阵U以及所述计算结果矩阵B,获取所述计算结果矩阵B到所述线路矩阵U的过程保真度。
获取构建的所述量子线路对应的线路矩阵U和所述计算结果矩阵B后,可以先确定线路矩阵U和计算结果矩阵B是否均为方阵且维度一致。
方阵即矩阵的行数和列数相同,方阵的维度即是行数或者列数。可以通过判断线路矩阵U的行数和列数是否相同以及计算结果矩阵B的行数和列数是否相同,如果线路矩阵U的行数和列数相同以及计算结果矩阵B的行数和列数相同,则确定线路矩阵U和计算结果矩阵B均为方阵。接着,判断线路矩阵U的行数或列数是否和计算结果矩阵B的行数或列数相同。如果线路矩阵U的行数或列数是和计算结果矩阵B的行数或列数相同,则确定线路矩阵U和计算结果矩阵B维度一致,继续执行S1601。
在S210中,所述过程保真度为两个矩阵的保真度衡量值,用于衡量两个矩阵之间保真度关系的度量。
根据线路矩阵U或计算结果矩阵B的维度、线路矩阵U以及计算结果矩阵B,获取计算结果矩阵B到线路矩阵U的过程保真度,可以包括如下步骤:
S2101,计算B1。
其中,dim(B)为计算结果矩阵B的维度。
S2102,计算线路矩阵U的共轭矩阵U1。
即
S2103,获取B1和共轭矩阵U1点乘后的范数值,所述范数值为计算结果矩阵B到线路矩阵U的过程保真度。
B1和共轭矩阵U1点乘结果为res,即res=B1·U1。
也就是说,res按行展开后的向量为:
res_vec=(res1,res2,...,resi,...resn)
res_vec=(res1,res2,...,resi,...resn)
其中,n为计算结果矩阵B的维度的平方。
所述范数值通过以下算式获取:
其中,||res||2为范数值,即计算结果矩阵B到线路矩阵U的过程保真度。
获取计算结果矩阵B到线路矩阵U的过程保真度后,执行步骤S220。
S220,根据所述线路矩阵U的维度或所述计算结果矩阵B的维度以及所述计算结果矩阵B到所述线路矩阵U的过程保真度,计算所述线路矩阵U和所述计算结果矩阵B的相似度。
其中,线路矩阵U和计算结果矩阵B的相似度通过以下算式获得:
Fstate_fid(B,U)=||res||2
Fstate_fid(B,U)=||res||2
其中,Fave_fid(B,U)为所述线路矩阵U和计算结果矩阵B的相似度,Fstate_fid(B,U)为计算结果矩阵B到线路矩阵U的过程保真度。
在获取线路矩阵U和计算结果矩阵B的相似度后,可以执行步骤S230。
S230,根据所述线路矩阵U和所述计算结果矩阵B的相似度,确认哈密顿量H被量子线路有效模拟。
具体地,所述根据线路矩阵U和计算结果矩阵B的相似度,确认待模拟哈密顿量H被量子线路有效模拟,包括:
判断所述线路矩阵U和计算结果矩阵A的相似度Fave_fid(B,U)是否满足以下不等式:
|Fave_fid(B,U)-1|<α
其中,α为阈值,可以人为设置数值。
若是上述不等式成立,即可以认为所述线路矩阵U和计算结果矩阵B的相似度Fave_fid(B,U)接近于1,则确认待模拟哈密顿量H能够被量子线路有效模拟。若是上述不等式不成立,则待模拟哈密顿量H不能被量子线路有效模拟。
与现有技术相比,基于图5所示出的数据模拟任务的处理方法,可以在得到数据模拟任务的计算数据后对计算数据的模拟程度进行确定,以提高数据模拟任务的处理水平。
参见图6,图6为本说明书一个实施方式提供的一种数据模拟任务的处理装置的结构示意图,与图3所示的流程相对应,所述装置可以包括:
第一获取模块410,用于数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量;所述目标数据为哈密顿量H,H以方阵形式表示,且与时间相互独立;
第一计算模块420,根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据;其中,所述运算过程为计算eiA;所述指定运算条件为A为方阵且A=-Ht,t为常数;所述计算数据以方阵形式表示;
分解模块430,用于将所述计算数据分解为有限个量子门的集合;
构建模块440,用于根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据。
在一些实施方式中,计算模块420可以包括:
第一分解单元,用于对方阵A进行特征值分解或奇异值分解;其中,分解结果为A';
计算单元,用于基于泰勒公式和欧拉公式,计算eiA′。
在一些实施方式中,所述计算结果为计算结果矩阵B;分解模块430包括:
转换单元,用于将计算结果矩阵B中的非0元素下标转换成二进制表示形式;
第二分解单元,用于根据计算结果矩阵B中的非0元素下标的二进制表示形式,将计算结果矩阵B中的每一项展开并重新表示为矩阵B';
第一确定单元,用于根据矩阵B'的每一项中的子项的值,确定矩阵B'的每一项中的子项对应的逻辑门类型;
第二确定单元,用于根据矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数;其中,所述量子子线路对应于非0元素。
在一些实施方式中,分解模块430还可以包括:
确认单元,用于确认所述计算结果是否为酉矩阵;
第三分解单元,用于当所述计算结果是酉矩阵时,基于豪斯霍尔德变换将所述计算结果分解为单量子位门和受控NOT门的集合。
在一些实施方式中,数据模拟任务的处理装置还包括:
操作模块,用于根据预设的量子操作对象操作构建的所述量子线路,其中,所述操作对象为所述量子线路的操作指令集合。
在一些实施方式中,所述量子线路的操作指令集合包括:用于获取构建的所述量子线路对应矩阵的指令;用于将所述量子线路汇编为程序代码的指令;用于判断所述量子线路对应矩阵是否酉矩阵的指令;用于操作所述量子线路对应矩阵的指令;用于操作所述量子线路的指令。
可选地,哈密顿量的模拟装置400还包括:
第二获取模块,用于根据构建的所述量子线路对应的线路矩阵的维度或所述计算结果对应的计算结果矩阵的维度、所述线路矩阵以及所述计算结果矩阵,获取所述计算结果矩阵到所述线路矩阵的过程保真度;
第二计算模块,用于根据所述线路矩阵的维度或所述计算结果矩阵的维度以及所述计算结果矩阵到所述线路矩阵的过程保真度,计算所述线路矩阵和所述计算结果矩阵的相似度;
确认模块,用于根据所述线路矩阵和所述计算结果矩阵的相似度,确认哈密顿量被所述量子线路有效模拟。
本说明书实施方式还提供了一种电子设备,包括存储器和处理器,所述存储器中存储有计算机程序,所述处理器被设置为运行所述计算机程序以执行上述任一项实施方式中的步骤。
具体的,上述电子设备还可以包括传输设备以及输入输出设备,其中,该传输设备和上述处理器连接,该输入输出设备和上述处理器连接。
在一些实施方式中,该电子设备中的处理器可以为一个或多个。该处理器可以通过硬件实现也可以通过软件实现。当通过硬件实现时,该处理器可以是逻辑电路、集成电路等。当通过软件实现时,该处理器可以是一个通用处理器,通过读取存储器中存储的软件代码来实现。
在一些实施方式中,该电子装置中的存储器也可以为一个或多个。该存储器可以与处理器集成在一起,也可以和处理器分离设置,本申请并不限定。示例性的,存储器可以是非瞬时性处理器,例如只读存储器ROM,其可以与处理器集成在同一块芯片上,也可以分别设置在不同的芯片上,本申请对存储器的类型,以及存储器与处理器的设置方式不作具体限定。
示例性的,该电子设备可以是现场可编程门阵列(Field Programmable Gate Array,FPGA),可以是专用集成芯片(Application Specific Integrated Circuit,ASIC),还可以是***芯片(System On Chip,SoC),还可以是中央处理器(Central Processor Unit,CPU),还可以是网络处理器(Network Processor,NP),还可以是数字信号处理电路(Digital Signal Processor,DSP),还可以是微控制器(Micro Controller Unit,MCU),还可以是可编程控制器(Programmable Logic Device,PLD)或其他集成芯片。
应理解,在本说明书实施方式中的处理器可以是中央处理单元(Central Processing Unit,CPU),该处理器还可以是其他通用处理器、数字信号处理器(Digital Signal Processor,DSP)、专用集成电路(Application Specific Integrated Circuit,ASIC)、现成可编程门阵列(Field Programmable Gate Array,FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解,本申请实施例中的存储器可以是易失性存储器或非易失性存储器,或可包括易失性和非易失性存储器两者。其中,非易失性存储器可以是只读存储器(read-only memory,ROM)、可编程只读存储器(programmable ROM,PROM)、可擦除可编程只读存储器(erasable PROM,EPROM)、电可擦除可编程只读存储器(electrically EPROM,EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory,RAM),其用作外部高速缓存。通过示例性但不是限制性说明,许多形式的随机存取存储器(random access memory,RAM)可用,例如静态随机存取存储器(static RAM,SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM,SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM,DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM,ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM,SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM,DR RAM)。
本说明书实施方式还提供了一种量子计算机操作***,所述量子计算机操作***根据本发明实施例中提供的上述任一方法实施例实现种哈密顿量的模拟。
本说明书实施方式还提供了一种量子计算机,所述量子计算机包括上述的量子计算机操作***。
本说明书实施方式还提供了一种存储介质,所述存储介质中存储有计算机程序,其中,所述计算机程序被设置为运行时执行上述任一项实施方式中的步骤。
具体的,在本实施方式中,上述存储介质可以包括但不限于:U盘、只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory,RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
上述实施方式,可以全部或部分地通过软件、硬件(如电路)、固件或其他任意组合来实现。当使用软件实现时,上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令或计算机程序。在计算机上加载或执行所述计算机指令或计算机程序时,全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中,或者从一个计算机可读存储介质向另一个计算机可读存储介质传输,例如,所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如,软盘、硬盘、磁带)、光介质(例如,DVD)、或者半导体介质。半导体介质可以是固态硬盘。
应理解,本文中术语“和/或”,仅仅是一种描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B这三种情况,其中A,B可以是单数或者复数。另外,本文中字符“/”,一般表示前后关联对象是一种“或”的关系,但也可能表示的是一种“和/或”的关系,具体可参考前后文进行理解。
本申请中,“至少一个”是指一个或者多个,“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达,是指的这些项中的任意组合,包括单项(个)或复数项(个)的任意组合。例如,a,b,或c中的至少一项(个),可以表示:a,b,c,a-b,a-c,b-c,或a-b-c,其中a,b,c可以是单个,也可以是多个。
应理解,在本申请的各种实施例中,上述各过程的序号的大小并不意味着执行顺序的先后,各过程的执行顺序应以其功能和内在逻辑确定,而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到,结合本文中所公开的实施例描述的各示例的单元及算法步骤,能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到,为描述的方便和简洁,上述描述的***、装置和单元的具体工作过程,可以参考前述方法实施例中的对应过程,在此不再赘述。
在本申请所提供的几个实施例中,应该理解到,所揭露的***、装置和方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个***,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外,在本申请各个实施例中的各功能单元可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。基于这样的理解,本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质中,包括若干指令用以使得一台计算机设备(可以是个人计算机,服务器,或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。。
Claims (21)
- 一种数据模拟任务的处理方法,其特征在于,所述方法包括:获取数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量;所述目标数据为哈密顿量H,H以方阵形式表示,且与时间相互独立;根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据;其中,所述运算过程为计算eiA;所述指定运算条件为A为方阵且A=-Ht,t为常数;所述计算数据以方阵形式表示;将所述计算数据分解为有限个量子门的集合;根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据。
- 根据权利要求1所述的方法,其特征在于,所述运算过程包括:对方阵A进行特征值分解或奇异值分解以得到分解结果A';基于泰勒公式和欧拉公式,计算eiA′。
- 根据权利要求1或2所述的方法,其特征在于,所述计算数据为计算结果矩阵B;所述将所述计算数据分解为有限个量子门的集合的步骤,包括:将所述计算结果矩阵B中的非0元素下标转换成二进制表示形式;其中,所述计算结果矩阵B为方阵且方阵中的非0元素为复数;根据所述计算结果矩阵B中的非0元素下标的二进制表示形式,将所述计算结果矩阵B中的每一项展开并重新表示为矩阵B';根据所述矩阵B'的每一项中的子项的值,确定所述矩阵B'的每一项中的子项对应的逻辑门类型。
- 根据权利要求3所述的方法,其特征在于,所述根据所述有限个量子门的集合,构建量子线路以进行模拟,包括:根据所述矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数;其中,所述量子子线路对应于所述计算结果矩阵B中的非0元素;根据所述量子子线路和所述量子子线路对应的系数,构建所述量子线路。
- 根据权利要求3或4所述的方法,其特征在于,所述计算结果矩阵B中的非0元素为Bkj;其中,k、j分别对应所述非0元素的行下标和列下标;S为所述计算结果矩阵B中非0元素的集合,s为所述计算结果矩阵B中非0元素的迭代指标;所述计算结果矩阵B中的非0元素下标的二进制表示形式为:
所述计算结果矩阵B的表示形式为:矩阵B'的表示形式为:
其中,n为十进制行下标或十进制列下标换算为二进制后的位数,m为1和n之间的整数。 - 根据权利要求3至5中任一项所述的方法,其特征在于,所述矩阵B'的每一项中的子项的值为|0><0|、|0><1|、|1><0|、|1><1|中的一种;所述根据所述矩阵B'的每一项中的子项的值,确定所述矩阵B'的每一项中的子项对应的逻辑门类型的步骤,包括:根据下述公式表示的所述子项的值与所述逻辑门类型之间的对应关系,确定所述矩阵B'的每一 项中的子项对应的逻辑门类型;
其中,X为泡利X门,Y为泡利Y门,Z为泡利Z门,I为I门,i为虚数。 - 根据权利要求4至6中任一项所述的方法,其特征在于,所述根据所述矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数的步骤,包括:根据矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路;根据所述量子子线路对应矩阵的值,以及所述矩阵B'中的非0元素的值,确定所述量子子线路对应的系数。
- 根据权利要求7所述的方法,其特征在于,所述根据所述量子子线路对应矩阵的值,以及所述矩阵B'中的非0元素的值,确定所述量子子线路对应的系数的步骤,包括:执行指定除运算,将所述除运算的运算结果作为所述量子子线路对应的系数;其中,所述指定除运算为将矩阵B'中的非0元素的值除以所述量子子线路对应矩阵的值。
- 根据权利要求4至8中任一项所述的方法,其特征在于,所述根据所述矩阵B'中每一项中的子项对应的逻辑门类型,确定量子子线路和所述量子子线路对应的系数,还包括:确定存在相同的量子子线路;合并相同的量子子线路;其中,合并后的量子子线路的系数为合并前各量子子线路对应系数之和。
- 根据权利要求1或2所述的方法,其特征在于,所述将所述计算数据分解为有限个量子门的集合,包括:确认所述计算数据为酉矩阵;在所述计算数据是酉矩阵的情况下,基于豪斯霍尔德变换将所述计算数据分解为单量子位门和受控NOT门的集合。
- 根据权利要求1至10中任一项所述的方法,其特征在于,所述方法还包括:根据预设的量子操作对象操作所述量子线路;其中,所述操作对象为所述量子线路的操作指令集合。
- 根据权利要求11所述的方法,其特征在于,所述量子线路的操作指令集合包括:用于获取所述量子线路对应矩阵的指令;用于将所述量子线路汇编为程序代码的指令;用于判断所述量子线路对应矩阵为酉矩阵的指令;用于操作所述量子线路对应矩阵的指令;用于操作所述量子线路的指令。
- 根据权利要求1所述的方法,其特征在于,根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述模拟得到的模拟数据作为目标数据的步骤,包括:根据所述量子线路对应的线路矩阵U的维度或所述计算结果矩阵B的维度、所述线路矩阵U以及所述计算结果矩阵B,获取所述计算结果矩阵B到所述线路矩阵U的过程保真度;其中,所述量子线路对应的线路矩阵U为方阵;根据所述线路矩阵U的维度或所述计算结果矩阵B的维度以及所述计算结果矩阵B到所述线路矩阵U的过程保真度,计算所述线路矩阵U和所述计算结果矩阵B的相似度;在所述线路矩阵U和所述计算结果矩阵B的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为所述哈密顿量H。
- 根据权利要求13所述的方法,其特征在于,在所述线路矩阵U和所述计算结果矩阵B的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为所述哈密顿量H的步骤,包括:在所述线路矩阵U和所述计算结果矩阵B的相似度Fave_fid(B,U)满足以下不等式的情况下,将根据所述量子线路模拟得到的模拟数据作为所述哈密顿量H:
|Fave_fid(B,U)-1|<α其中,α为阈值;B=e-iHt。 - 根据权利要求13或14所述的方法,其特征在于,所述根据所述量子线路对应的线路矩阵U的维度或计算数据对应的计算结果矩阵B的维度、所述线路矩阵U以及所述计算结果矩阵B,获取所述计算结果矩阵B到所述线路矩阵U的过程保真度的步骤,包括:计算矩阵B1;其中,dim(B)为所述计算结果矩阵B的维度;计算所述线路矩阵U的共轭矩阵U1;将所述矩阵B1和所述共轭矩阵U1点乘后的范数值作为所述计算结果矩阵B到所述线路矩阵U的过程保真度。
- 根据权利要求15所述的方法,其特征在于,所述矩阵B1和所述共轭矩阵U1点乘后的范数值通过以下算式得到:
res=B1·U1
res_vec=(res1,res2,...,resi,...resl)
其中,res为所述矩阵B1和共轭矩阵U1的点乘结果,res_vec为res按行展开后的向量,l为计算结果矩阵B的维度的平方,||res||2为所述矩阵B1和所述共轭矩阵U1点乘后的范数值。 - 根据权利要求13至16任一项所述的方法,其特征在于,所述根据所述线路矩阵U的维度或计算结果矩阵B的维度以及计算结果矩阵B到所述线路矩阵U的过程保真度,计算所述线路矩阵U和所述计算结果矩阵B的相似度的步骤,包括:通过以下算式计算所述线路矩阵U和所述计算结果矩阵B的相似度:
Fstate_fid(B,U)=||res||2其中,Fave_fid(B,U)为所述线路矩阵U和所述计算结果矩阵B的相似度,Fstate_fid(B,U)为所述计算结果矩阵B到所述线路矩阵U的过程保真度。 - 根据权利要求13至17任一项所述的方法,其特征在于,所述方法还包括:在获取所述计算结果矩阵B到所述线路矩阵U的过程保真度之前,确认所述线路矩阵U的维度 和所述计算结果矩阵B的维度一致。
- 一种数据模拟任务的处理装置,其特征在于,所述装置包括:获取模块,用于获取数据模拟任务的目标数据;其中,所述数据模拟任务为模拟哈密顿量;所述目标数据为哈密顿量H,H以方阵形式表示,且与时间相互独立;运算模块,用于根据所述目标数据和指定运算条件执行运算过程,得到所述数据模拟任务的计算数据;其中,所述运算过程为计算eiA;所述指定运算条件为A为方阵且A=-Ht,t为常数;所述计算数据以为方阵形式表示;分解模块,用于将所述计算数据分解为有限个量子门的集合;构建模块,用于根据所述有限个量子门的集合,构建量子线路以进行模拟,至在所述量子线路对应的线路矩阵和所述计算数据的相似度满足指定条件的情况下,将根据所述量子线路模拟得到的模拟数据作为目标数据。
- 一种电子设备,包括存储器和处理器,其特征在于,所述存储器中存储有计算机程序,所述处理器被设置为运行所述计算机程序以执行所述权利要求1至18任一项所述的方法。
- 一种存储介质,其特征在于,所述存储介质中存储有计算机程序,其中,所述计算机程序被设置为运行时执行所述权利要求1至18任一项所述的方法。
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