WO2023169289A1 - 一种进程的执行状态切换方法及装置 - Google Patents

一种进程的执行状态切换方法及装置 Download PDF

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Publication number
WO2023169289A1
WO2023169289A1 PCT/CN2023/079222 CN2023079222W WO2023169289A1 WO 2023169289 A1 WO2023169289 A1 WO 2023169289A1 CN 2023079222 W CN2023079222 W CN 2023079222W WO 2023169289 A1 WO2023169289 A1 WO 2023169289A1
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logical core
core
slave
state
exception
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PCT/CN2023/079222
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English (en)
French (fr)
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童甜根
郭寒军
王克锋
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华为技术有限公司
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Publication of WO2023169289A1 publication Critical patent/WO2023169289A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • the present application relates to the field of processors, and in particular, to a method and device for switching execution states of a process.
  • heterogeneous computing refers to the combination of CPU, digital signal processing (DSP), graphics processing unit (GPU), application specific integrated circuit (ASIC), field programmable logic gate array (field Computing units with different process architectures, different instruction sets, and different functions such as programmable gate array (FPGA) are combined to form a hybrid computing system.
  • DSP digital signal processing
  • GPU graphics processing unit
  • ASIC application specific integrated circuit
  • FPGA field programmable logic gate array
  • the CPU physical core includes the ARM64 logical core and the ARM32 logical core.
  • the ARM64 logical core can execute one of the privilege levels EL0 to EL4, and the ARM32 logical core can execute the privilege level EL0, among which the privileges of EL0 The lowest level.
  • the ARM32 process specifically runs in the ARM32 logical core.
  • the ARM64 logic core and the ARM32 logic core need to be tightly coupled.
  • the ARM64 logic core needs to add new registers and vector table entries to support the ARM32 logic core.
  • the two logic cores cannot evolve independently.
  • This application provides a process execution state switching method and device, which are used to decouple two logical cores on the premise of flexibly switching the corresponding execution states of two logical cores, so that one of the logical cores can be independently evolved.
  • this application provides a method for switching the execution state of a process, which is applied to a CPU.
  • the CPU includes a physical core, and the physical core includes a master logical core and a slave logical core.
  • the method includes: if running on the slave When the process of the logical core meets the first condition, the running process is suspended from the logical core, and the pause position of the process is recorded.
  • the pause position can be used to determine the execution position when the process is run from the logical core next time, where the first condition is Instructs the process to perform the target operation, and the target operation can be executed when the execution state of the process is in the privileged state of the main logical core; switches the execution state of the process from the user mode of the slave logical core to the privileged state of the main logical core; in Processes run in the main logical core for the process to perform target operations.
  • the process when a process is run from a logical core and the process needs to perform a target operation, the process is run from the logical core Record the pause position of the process, which can be used to determine the execution position the next time the process is run in the slave logical core.
  • the master logical core and the slave logical core do not need to share registers, and can flexibly switch the corresponding execution states of the two logical cores.
  • one of the logic cores can be evolved independently.
  • recording the pause position of the process includes writing the pause position information into the configuration space through the slave logical core, and the configuration space is used for information interaction between the master logical core and the slave logical core.
  • the configuration space is used for information interaction between the slave logic core and the slave logical core.
  • the method also includes: switching the execution state of the process from the privileged state of the main logical core to the user state of the slave logical core; reading the pause position information from the configuration space through the slave logical core; In the logical core, the process continues from the paused position. In this way, after the main logical core completes the target operation, the slave logical core can continue to be started to continue running the process. Since the slave logical core has previously recorded the pause position, the slave logical core can continue to run from the pause position, thereby realizing that the process can Switch between two logical cores and the process can run without interruption.
  • the first condition includes the process triggering a first type of exception, and the first type of exception includes other exceptions except reliability exceptions, availability exceptions, and serviceability RAS exceptions;
  • the method before switching the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, the method further includes: obtaining the virtual memory address corresponding to the target privilege level; determining the virtual memory address of the target privilege level; The memory address is not mapped to the physical memory address.
  • the main logical core accesses the virtual memory address corresponding to the target privilege level. If it is determined that the virtual memory address does not establish a mapping relationship with the physical memory address, a page fault is triggered.
  • the main logical core can process the process based on the triggered page fault.
  • the execution state falls from the user state of the main logical core to the target privilege level of the privileged state of the main logical core. In this way, by constructing a special exception (ie, page fault), the execution state of the process is dropped from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, thereby reducing the complexity of the execution of the process falling into the privileged state.
  • a special exception ie, page fault
  • the first condition includes the process receiving an interrupt, or the process triggering a RAS exception. Since interrupts or RAS exceptions are asynchronous events and need to be processed quickly, when the process running on the slave logical core receives an interrupt or triggers a RAS exception, the process can be processed through the hardware unit (or hardware part) in the CPU physical core. The execution state falls from the user state of the slave logical core to the target privilege level of the privileged state of the main logical core.
  • the method also includes: starting the process in the main logical core; if the instruction set of the process belongs to the instruction set running from the slave logical core, recording the starting position of the process and triggering the slave logical core to enter the running state. ;In the slave logical core, run the process from the starting position.
  • some processes such as mySql process, graph calculation process or encryption and decryption operators
  • start these processes in the main logical core it can be determined that these processes need to run in the slave logical core.
  • the starting position of the process is recorded through the main logical core, and the slave logical core is triggered to enter the running state, so that the slave logical core reads the starting position and runs the process at the starting position.
  • the method further includes: releasing the hardware resources of the physical core occupied by the main logical core when running the process; where the hardware resources include memory resources and/or input and output resources. In this way, the released hardware resources can be reused to run other processes, which helps to fully utilize the hardware resources.
  • the method also includes: recording one or more of the following information from the logical core: the reason why the running process is suspended on the logical core, the execution parameters corresponding to the target operation, and when the running process is suspended. Environment information, or privilege level information; where the privilege level information is used to indicate the privilege level of the privileged state of the main logical core when the process performs the target operation. In this way, the main logic core can correctly handle the target operation based on these parameters.
  • the slave logical core can run acceleration engines and algorithms, such as one or more of the mySql process, graph calculation process, or encryption and decryption operators. Compared with running these processes on the main logical core, it can Improve computing speed.
  • this application provides a device for switching the execution state of a process, and the device may be a CPU.
  • the device includes a processor and a memory; the memory is used to store a computer program; the processor is used to call the computer program stored in the memory to perform the following steps: if the process running in the slave logical core meets the first condition, the process in the slave logical core is suspended. process, and record the pause position of the process. The pause position is used to determine the execution position the next time the process is run from the logical core.
  • the first condition is used to indicate that the process is to perform the target operation, and the target operation is in the execution state of the process.
  • the processor when the processor records the pause position of the process, it is specifically used to: write the pause position information into the configuration space through the slave logical core, and the configuration space is used for information exchange between the master logical core and the slave logical core. Interaction.
  • the processor is also used to: switch the execution state of the process from the privileged state of the main logical core to the user state of the slave logical core; read the pause position information from the configuration space through the slave logical core; In the secondary logical core, the process continues from the pause position.
  • the first condition includes the process triggering a first type of exception, and the first type of exception includes other exceptions except reliability exceptions, availability exceptions, and serviceability RAS exceptions;
  • the execution state is switched from the user state of the slave logical core to the privileged state of the master logical core, it is specifically used to: trigger the master logical core to run the process, so as to switch the execution state of the process from the user state of the slave logical core to the user state of the master logical core. state; determine the target privilege level corresponding to the first type of exception from the multiple privilege levels of the privileged state of the main logical core; switch the execution state of the process from the user mode of the main logical core to the target privilege level of the privileged state of the main logical core .
  • the processor before switching the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, the processor is also used to: obtain the virtual memory corresponding to the target privilege level. Address; determine that the virtual memory address is not mapped to the physical memory address.
  • the first condition includes the process receiving an interrupt or triggering a RAS exception.
  • the processor is also used to: start a process in the main logical core; if the instruction set of the process belongs to the instruction set running from the slave logical core, record the starting position of the process, and trigger entry from the slave logical core Running status; in the slave logical core, start running the process from the starting position.
  • the processor is also used to: release hardware resources of the physical core occupied by the main logical core when running the process; where the hardware resources include memory resources and/or input and output resources.
  • the processor is also used to record one or more of the following information from the logical core: the reason for suspending the running process on the slave logical core, the execution parameters corresponding to the target operation, and the suspension of operation.
  • this application provides a device for switching the execution state of a process, and the device may be a CPU.
  • the device includes a main logic core module and a slave logic core module.
  • the slave logic core module is used to determine that when the process running in the slave logic core module meets the first condition, it pauses the running process and records the pause position of the process. The pause position is used for next time.
  • the execution position is determined when the process is running in the slave logical core module, where the first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the execution state of the process is in the privileged state of the main logical core module; the slave logical core module
  • the core module is also used to switch the execution state of the process from the user state of the slave logical core module to the privileged state of the main logical core module; the main logical core module is used to run the process so that the process can perform target operations.
  • the slave logical core module when the slave logical core module records the pause position of the process, it is specifically used to write the pause position information into the configuration space.
  • the configuration space is used for information interaction between the master logical core module and the slave logical core module. .
  • the main logical core module is also used to switch the execution state of the process from the privileged state of the main logical core module to the user mode of the slave logical core module; the slave logical core module is also used to read from the configuration space. Get the information of the pause position and continue running the process from the pause position.
  • the first condition includes the process triggering the first type of exception, and the first type of exception includes other exceptions except reliability exceptions, availability exceptions, and serviceability RAS exceptions; from the specific use of the logical core module It is used to trigger the main logical core module to run the process, so as to switch the execution state of the process from the user mode of the slave logical core module to the user mode of the main logical core module; the main logical core module is specifically used for multiple privileged states of the slave main logical core module.
  • the target privilege level corresponding to the first type of exception is determined among the privilege levels, and the target privilege level is used to switch the execution state of the process from the user state of the main logical core module to the privileged state of the main logical core module.
  • the main logical core module is also used to obtain the corresponding target privilege level before switching the execution state of the process from the user mode of the main logical core module to the target privilege level of the privileged state of the main logical core module.
  • the virtual memory address determine that the virtual memory address does not have a mapping relationship with the physical memory address.
  • the first condition includes the process receiving an interrupt or triggering a RAS exception.
  • the main logical core module is also used to start the process. If the instruction set of the process belongs to the instruction set running from the slave logical core, the starting position of the process is recorded and the slave logical core module is triggered to enter the running state. ; The slave logic core module is also used to run the process from the starting position.
  • the main logical core module releases the hardware resources of the physical core occupied when running the process; where the hardware resources include memory resources and/or input and output resources.
  • the slave logical core module is also used to record one or more of the following information: the reason for suspending the running process on the slave logical core, the execution parameters corresponding to the target operation, and the reasons for suspending the running process. Environment information, or privilege level information; where the privilege level information is used to indicate the privilege level of the privileged state of the main logical core when the process performs the target operation.
  • embodiments of the present application provide a chip system, including: a processor and a memory.
  • the processor is coupled to the memory.
  • the memory is used to store programs or instructions. When the program or instructions are processed by the processor When executed, the chip system is caused to implement the method in the above first aspect or any possible implementation manner of the first aspect.
  • the present application provides a computer program product.
  • the computer program product includes a computer program or instructions.
  • the computer program or instructions are executed by a device, the first aspect or any possible implementation manner of the first aspect is implemented. Methods.
  • the present application provides a computer-readable storage medium.
  • Computer programs or instructions are stored in the computer-readable storage medium.
  • the above-mentioned first aspect or any of the first aspects is implemented. method in one possible implementation.
  • the present application provides a computing device, including a processor, the processor is connected to a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that The computing device executes the method in the above first aspect or any possible implementation of the first aspect.
  • Figure 1 is a schematic diagram of an ARMv8-A architecture
  • Figure 2 is a schematic diagram of the process of switching between AArch64 and AArch32 execution states
  • FIG. 3 is an architectural schematic diagram of a chip system provided by this application.
  • Figure 4 is a schematic diagram of the running processes in a Master logical core and a Slave logical core provided by this application;
  • FIG. 5 is a schematic flow chart of an execution state switching method provided by this application.
  • FIG. 6 is a schematic diagram of a startup process provided by this application.
  • Figure 7 is a schematic diagram of a method for switching the execution state of a process provided by this application.
  • Figure 8 is a schematic diagram of a Master logical core provided by this application trapping a process into a target privilege level
  • Figure 9 is a schematic diagram of yet another method for switching the execution status of a process provided by this application.
  • Figure 10 is a schematic diagram of another method for switching the execution status of a process provided by this application.
  • FIG 11 is a schematic flowchart of yet another execution state switching method provided by this application.
  • a program is an ordered collection of instructions, it is just a static entity.
  • a process is the execution of a program on some data set.
  • a process is a dynamic entity with its own life cycle. Processes are created due to creation, run due to scheduling, placed in a waiting state due to waiting for resources or events, and canceled due to completion of tasks.
  • a process reflects the entire dynamic process of a program running on a certain data set.
  • a process When a process is executing user code, it is in the user running state (also called user mode). When a process is trapped in kernel code for execution due to a system call, the process is in the kernel running state (also called kernel state). The executed kernel code will use the kernel stack of the current process, and each process has its own kernel stack.
  • the user runs a program, and the process created by the program starts by running its own code in user mode.
  • the kernel code is called through system calls such as write and send.
  • the process enters the kernel address space to execute kernel code to complete the corresponding operation. After the kernel mode process is executed, it will return to the user mode.
  • User-mode processes cannot manipulate the kernel address space at will.
  • CPU is not equal to physical core, nor is it equal to logical core.
  • the physical core (physical core/processor) is a visible, real CPU core.
  • the physical core has independent circuit components and L1 and L2 caches, and can execute instructions independently.
  • Logical core/processor A core at the logical level within the same physical core.
  • a CPU can have multiple physical cores.
  • a physical core can be divided into multiple logical cores.
  • Real-time operating system refers to the core part of most operating systems. It consists of the parts of the operating system that manage memory, files, peripherals, and system resources.
  • Executable and Linkable Format (ELF) files refer to target files on Unix and X86-64 Linux.
  • the target file refers to the computer file used to store the target code.
  • the target file can contain machine code, data used by the code when running, debugging information, etc. It is the process of generating program files from source code files. mid product.
  • Synchronous operation means that when the caller calls, it needs to wait for the call to return the result before continuing to execute.
  • Asynchronous operations are the opposite of synchronous operations. After the caller issues a call, it does not need to wait for the call result, but continues to perform subsequent operations. The callee notifies the caller through the status, or handles the call by calling back the function.
  • Reliability means that the system must be as reliable as possible without unexpected crashes, restarts or even physical damage to the system.
  • Availability refers to the fact that the system must be able to work as long as possible without going offline. Even if some minor problems occur in the system, it will not affect the normal operation of the entire system.
  • Serviceability refers to the ability of the system to provide convenient diagnostic functions, such as system logs, dynamic detection and other means to facilitate system diagnosis and maintenance operations by managers, so as to detect and repair errors as early as possible. As a whole, the role of RAS is to ensure that the entire system runs reliably for as long as possible without going offline, and has a sufficiently powerful fault-tolerant mechanism.
  • Firmware is generally stored in the electrically erasable programmable ROM (EEPROM) or FLASH chip in the device.
  • Firmware is, for example, the basic input/output system BIOS (basic input/output system) on the computer motherboard.
  • Register is an integral part of the central processing unit. Registers are high-speed storage components with limited storage capacity. Registers can be used to temporarily store instructions, data and addresses.
  • the program status saving register (saved program status register, SPSR) is used to save the status of the program status register (current program status register, CPSR) so that the working status when the exception occurs can be restored after an exception returns. When a specific exception interrupt occurs, this register is used to store the contents of the current program status register. When exiting from an abnormal interrupt, SPSR can be used to restore CPSR.
  • the CPU physical core can include a master logical core and a slave logical core.
  • the CPU physical core can run multiple processes, and the multiple processes can run on the Master logical core or the Slave logical core.
  • the Master logical core is an ARM64 logical core and the Slave logical core is an ARM32 logical core
  • the ARM64 process can run in the ARM64 logical core
  • the ARM32 process can run in the ARM32 logical core.
  • no matter what kind of logical core a process is running in it can be started by the Master logical core.
  • the Master logical core determines that the process needs to run on the Slave logical core, it can call the Slave logical core so that the process Runs in the Slave logical core.
  • AArch32 (or ARM32) and AArch64 (or ARM64) can be supported at the same time.
  • the AArch64 execution state supports the A64 instruction set and can run ARM64 processes.
  • AArch32 execution state supports T32 and A32 instruction sets and can run ARM32 processes.
  • exception level A logical division of privilege levels at which a program runs. Exception levels are divided into the following four types:
  • EL1 operating system kernel
  • EL3 Low-level firmware, including Secure Monitor.
  • a piece of software such as an application, operating system kernel, or virtual machine monitor, occupies only one exception level.
  • the ARMv8-A architecture can be seen in Figure 1.
  • the execution state of the ARM32 logical core is AArch32
  • the execution state of the ARM64 logical core is AArch64.
  • AArch32 can correspond to the EL0 privilege level
  • AArch64 can correspond to the EL0 and EL1 privilege levels.
  • user-mode processes can be run in AARCH64 and AARCH32 execution states
  • kernel-mode processes can be run in the AArch64 execution state.
  • the ARMv8-A architecture can have the following characteristics:
  • A32 and T32 instruction sets supported by AArch32, and the A64 instruction set supported by AArch64 can be encapsulated through execution state.
  • the CPU must be in the execution state of AArch32 or AArch64 at any time. When switching between the two execution states of AArch32 and AArch64, the CPU needs to fall into a high privilege level through an exception.
  • AArch32 and AArch64 are tightly coupled, and they can share registers.
  • AArch32 and AArch64 cannot call each other (for example, functions in the A64 instruction set cannot call functions in the A32 instruction set or T32 instruction set), and AArch32 and AArch64 cannot be used as extensions of each other.
  • the exception vector table includes the correspondence between exceptions and exception handlers.
  • AArch32 needs to trap the low privilege level to the high privilege level when an exception occurs.
  • AArch64 accesses the exception vector table when the high privilege level determines the exception handler that needs to be scheduled.
  • Figure 2 illustrates a process of switching between AArch64 and AArch32 execution states provided by this application. Specifically, the process is to run an ARM32 executable program (which can be referred to as a program) in the AArch64 execution state.
  • an ARM32 executable program which can be referred to as a program
  • Step 201 In the AArch64 execution state, the EL0 user state loads the ARM32 process and will fall into the EL1 kernel state.
  • the ELF file format is parsed in the EL1 kernel and it is found that the EL0 user state needs to run the program of the A32 instruction set. Then, return to the EL0 user state. When in the state, it will switch to the AArch32 execution state by setting the SPSR, that is, the execution state switches from AArch64 to AArch32.
  • Step 202 When the ARM32 process running in the AArch32 execution state needs to handle an exception, it needs to do so by falling into the EL1 kernel state, that is, the execution state is switched from AArch32 to AArch64 again. After handling the exception, the EL1 kernel state returns to the AArch32 execution state of EL0 as required. Or, after the ARM32 process running in the AArch32 execution state finishes running, it needs to be completed by falling into the EL1 kernel state.
  • the logical core run by the ARM32 process needs to frequently switch between the ARM64 logical core and the ARM32 logical core.
  • This abnormal switching requires the hardware to complete a lot of work.
  • Switching between the ARM64 logic core and the ARM32 logic core needs to be based on the exception recorded in the exception vector table and the handler corresponding to the exception.
  • the exception vector table is stored in a register, and the exception vector table needs to occupy a large number of registers.
  • the ARM64 logic core and the ARM32 logic core share registers, and they are tightly coupled and cannot evolve independently.
  • This application provides a method and device for switching the execution state of a process, which is used to flexibly switch the execution state of two logical cores. Under the premise of running status, the two logical cores are decoupled, so that one of the logical cores can be independently evolved.
  • FIG. 3 is a schematic diagram of the architecture of a chip system.
  • the chip system includes multiple CPU physical cores.
  • Each CPU physical core can include two logical cores, which can be represented as Master logical core and Slave logical core respectively.
  • the Master logical core can be used to perform privileged state operations, and the Slave logical core can be used to perform user state operations. Among them, multiple privilege levels in the privileged state are higher than those in the user state.
  • the Master logical core is ARM64.
  • the privileged state implemented by the Master logical core corresponds to the three privilege levels of EL1, EL2 and EL3.
  • the Slave logical core implements the privileged level of the user state. Among them, the three privileged levels of EL1, EL2 and EL3 are higher than User mode privilege level.
  • the Master logical core can also be used to perform user-mode operations, which can achieve user-mode privilege levels. Still taking the Master logical core as ARM64 as an example, the user mode implemented by the Master logical core includes the EL0 privilege level. The user-mode privilege level implemented by the Master logical core can be the same privilege level as the user-mode privilege level implemented by the Slave logical core.
  • the user mode program can run in the Master logical core according to its instruction set, or it can also run in the Slave logical core.
  • System software (such as Kernel/Hypervisor/Firmware) can only run in the Master logical core.
  • the Master logic core and the Slave logic core use different instruction sets.
  • the instruction set of the Master logic core can be the current mainstream instruction set such as X86 or ARM.
  • the instruction set of the slave logic core can be a self-developed instruction set.
  • the computing power of the Slave logical core can be higher than the computing power of the Master logical core.
  • the process running on the Slave logical core includes an executable code segment.
  • the executable code segment may include two parts: a springboard code segment (which can be expressed as trampoline code in English) and a main body code segment.
  • the springboard code segment runs in the Master logical core and is used to call the Slave logical core to run the process. It can be understood that since the loading of the process occurs in the Master logical core and the running of the process occurs in the Slave logical core, a springboard code segment in the Master logical core is needed to switch the process from running on the Master logical core to running on the Slave logic. nuclear.
  • the main code segment runs in the Slave logical core, where the main code segment is the main code of the running process.
  • This configuration space can be understood as the interactive interface between the two logical cores.
  • the configuration space can be a register group or a special memory space.
  • This configuration space can be used for information exchange between the Master logical core and the Slave logical core. For example, when the Master logical core starts a process, it can determine that the process needs to run in the Slave logical core, and then execute the Slave logical core. The relevant parameters of the process are written into the configuration space. The Slave logic core reads the relevant parameters from the configuration space and starts executing the process based on the read parameters.
  • Each CPU physical core corresponds to an extra-core resource, such as a cache or a memory management unit (MMU).
  • MMU memory management unit
  • Multiple CPU physical cores and corresponding extra-core resources of the multiple CPU physical cores can be packaged together in a chip system, and the chip system can be connected to memory and peripherals.
  • the Master logical core as an ARM64 logical core as an example, explain the processes running in the Master logical core and Slave logical core.
  • the Master instruction set in the ARM64 logical core can also be called the A64 instruction set
  • the process running on the ARM64 logical core can also be called the A64 process.
  • the chip system corresponds to the user state, privileged state and hardware part.
  • the user-mode processes and system software (such as Kernel/Hypervisor/Firmware) of the A64 instruction set run on the ARM64 logical core
  • the user-mode processes ie processes) of the Slave instruction set run on the Slave logical core.
  • Step 501 Start the process on the Master logical core and determine that the process needs to run on the Slave logical core. Start the Slave logical core so that the Slave logical core runs the process. Among them, when running a process on the Slave logical core, the process can only perform user-mode operations.
  • Step 502 When it is determined that the process needs to perform operations in the privileged state, the execution state of the process is switched from the user state to the privileged state. Correspondingly, the process needs to be switched to run in the Master logical core.
  • Step 503 After the process in the Master logical core processes the privileged state operation, the execution state of the process can be switched from the privileged state back to the user state. Correspondingly, the process is switched back to the Slave logical core to run.
  • the Master logical core and the Slave logical core can exchange information with each other through the configuration space.
  • FIG. 6 is a schematic diagram of a Master logical core startup process provided by this application.
  • the above-mentioned step 501 is explained with reference to Figure 6, in which the text in the dotted box may represent the actions performed by the Master logical core or the Slave logical core.
  • the Master logical core starts the running process in the user state and traps the process from the user state to the privileged state.
  • the Master logical core loads the process data from memory.
  • the data of the process such as the code segment/text segment, data segment, executable file, etc. of the process.
  • a code segment is usually an area of memory used to store program execution code.
  • the data segment usually refers to the memory area used to store initialized global variables in the program.
  • An executable file is, for example, an ELF file.
  • the executable file of the process records the identification of whether the process needs to run on the slave logical core.
  • the Master logical core determines whether the process needs to run on the Slave logical core based on the identification.
  • the Master logical core determines, based on the code segment, that the instruction set executed by the process belongs to the instruction set run by the Slave logical core, and then determines that the process needs to run on the Slave logical core.
  • the Master logical core determines that the process needs to run in the Slave logical core, it can return the process from the privileged state to the user mode of the Slave logical core, so that the Slave logical core executes the process in the user mode. Specifically, when the Master logical core returns the process from the privileged state to the user state of the Slave logical core, it can return the process to the entry of the springboard code segment in the Master logical core, and write the entry of the process through the springboard code segment. Enter the configuration space, thereby triggering the Slave logical core to start executing the process from this entry.
  • the Master logical core can write the starting position (or starting position information) of the process into the configuration space through the springboard code segment, and then the Master logical core operates the configuration space through the springboard code segment to trigger the startup command (available in English). This is called the slave call instruction), thereby starting the Slave logical core through the slave call instruction.
  • the slave logic core reads the starting position from the configuration space and starts the process based on the read starting position.
  • the Master logical core can release the hardware resources of the physical core occupied by the Master logical core when running the process.
  • the hardware resources can include memory resources, input/output (I/O) One or more resources. In this way, this part of the released hardware resources can be reused to execute other processes, which helps to make full use of the hardware resources.
  • the Master logic core writes the position of the next instruction of the slave call instruction (this position can be recorded as master.pc) into the configuration space.
  • This master.pc can be used by the Master logical core to know from which position to start executing the process when it needs to execute the process again.
  • the next instruction of the slave call instruction can be called the master.pc instruction.
  • the first condition can be used to indicate that the process needs to perform an operation in a privileged state.
  • the operation in the privileged state can be called a target operation. That is, the first condition can be used to indicate that the process needs to perform the target operation.
  • the Slave logic core needs to suspend the current running The process in the Slave logical core is then switched to be run by the Master logical core, so that the process running in the Master logical core can perform the target operation.
  • the pauses triggered by the target operations can be divided into exceptions (Exception) and interruptions (Interruption).
  • Exceptions refer to events from within the CPU executing instructions. Abnormalities can be divided into first-type exceptions and second-type exceptions.
  • the first-type exceptions can be ordinary exceptions
  • the second-type exceptions can be RAS exceptions.
  • RAS exceptions include physical damage to memory pages.
  • Common exceptions are exceptions other than RAS exceptions. Common exceptions include system calls (or syscalls for short), page faults, instruction faults, etc.
  • Interrupts refer to events that occur other than when the CPU executes instructions, such as clock interrupts, serial port interrupts, network interrupts, I/O interrupt stops, etc. Take the clock interrupt as an example.
  • the clock interrupt indicates that a fixed time slice has arrived, allowing the CPU to process timing, start scheduled tasks, etc.
  • step 502 is explained as follows based on three situations: ordinary exception, interruption, and RAS exception.
  • Figure 7 shows a schematic diagram of a method for switching the execution state of a process when a process triggers a common exception.
  • the text in the dotted box can represent the actions performed by the Master logical core or the Slave logical core.
  • the process triggers a common exception because it needs to perform the target operation.
  • the slave logical core needs to write the running context (or common exception information) of the process into the configuration space.
  • Ordinary exception information may include one or more of the following: privilege level information, instruction location that triggered the exception, exception cause, exception occurrence address, exception parameters, register information, etc.
  • the privilege level information is used to indicate the privilege level corresponding to the target operation (which can be called the target privilege level), that is, which privilege level the Master logical core needs to use to handle this exception. For example, if the target operation is a system call, the target privilege level is EL1.
  • the instruction location that triggers the exception can be considered as the location where the process was interrupted, and can be recorded as slave.pc.
  • the Slave logical core resumes execution, the Slave logical core can continue execution from this location slave.pc.
  • the instruction corresponding to the location slave.pc can be called the slave.pc instruction.
  • Exception cause indicates the reason for suspending the running process on the secondary logical core, or indicates the reason for the exception, such as system call, page fault, instruction failure, etc.
  • the address where the exception occurred such as the location in memory being accessed.
  • Exception parameters such as parameters that need to be passed in system calls.
  • Register information is used to indicate the running environment information in the Slave logical core when the running process is suspended in the Slave logical core. This running environment information can be used by the Slave logical core to continue executing the process. Register information is, for example, SPSR information.
  • the hardware resources corresponding to the Slave logical core can be released (Retired) at the instruction location that triggers the target operation.
  • the Slave hardware unit switches the process from running on the Slave logical core to running on the Master logical core.
  • the Master logical core reads the location master.pc in the configuration space, and then continues execution from the next instruction of the slave call instruction in the springboard code segment (ie, the master.pc instruction) based on the location master.pc.
  • the execution state of the process is switched from the user state of the Slave logical core to the user state of the Master logical core.
  • the Master logical core needs to further switch the process from the user state of the Master logical core to the privileged state of the Master logical core.
  • the Master logical core can also read the common exception information of the process in the configuration space, and according to the common exception information of the process, the execution state of the process is dropped from the user state of the Master logical core to the privileged state of the Master logical core.
  • the Master logical core can determine whether to trap the process based on the privilege level information in the ordinary exception information. Enter the target privilege level of the privileged state.
  • the Master logic core After the process falls into the target privilege level, the Master logic core further performs the target operation based on the exception cause, exception occurrence address, exception parameters and other information in the ordinary exception information, that is, handles the ordinary exception.
  • exception parameters may include system call identification (syscall id) and system call input parameters.
  • the Master logical core can read the system call identifier and system call input parameters from the common exception information in the configuration space, construct a system call based on these two parameters, and then issue the system call, that is, the Master logical core privileged state sees is the converted system call. After the system call is executed, the Master logical core can write the return value of the system call into the configuration space. In this way, the Slave logical core can read the return value of the system call from the configuration space.
  • the Master logical core can construct the system call according to the application binary interface (ABI) rules of the corresponding architecture of the Master logical core, so that it is applicable to different CPUs.
  • the Master logical core still writes the return value of the system call to the configuration space according to the ABI rules.
  • ABSI application binary interface
  • exception parameters may include the virtual page address corresponding to the page fault.
  • the Master logical core can read the virtual page address from the common exception information in the configuration space, apply for a physical page address for the virtual page address, and then establish a mapping relationship between the virtual page address and the physical page address, and update the page table.
  • the virtual page address can also be called a virtual memory address
  • the physical page address can also be called a physical memory address.
  • this application can determine the privilege levels corresponding to these common exceptions for different common exceptions. It can be understood that one privilege level can correspond to a variety of common exceptions.
  • the EL1 privilege level corresponds to system calls, page faults, instruction failures, etc. When such exceptions occur, the Master logical core can trap the process into the EL1 privilege level for processing. .
  • the Master logical core changes the execution state of the process from the user state of the Master logical core to the target privilege level of the Master logical core's privileged state. This can be achieved by constructing a special exception. For details, please refer to the trapping method shown in Figure 8 .
  • two virtual page addresses can be added in the real-time operating system, and the two virtual page addresses respectively correspond to two privilege levels of the privileged state (specifically, the kernel state).
  • the two privilege levels in the kernel state are EL1 privilege level and EL2 privilege level.
  • virtual page address 1 corresponds to the EL1 privilege level
  • virtual page address 2 corresponds to the EL2 privilege level.
  • the two virtual page addresses do not establish a mapping relationship with the physical page addresses.
  • the Master logical core can select the target privilege level corresponding to the ordinary exception from multiple privilege levels corresponding to the privileged state based on the type of ordinary exception triggered by the Slave logical core; and then determine the target privilege level from multiple virtual page addresses.
  • the Master logical core accesses the virtual page address corresponding to the target privilege level by executing the page access instruction and determines that the virtual page address does not establish a mapping relationship with the physical page address, so an exception (i.e., page fault) is triggered. Subsequently, the Master logical core falls from the user state to the target privilege level in the privileged state.
  • the Master logical core determines that the exception triggered by the process is a system call, and the Master logical core determines that the process needs to be trapped into the EL1 privilege level based on the system call.
  • the master logical core accesses virtual page address 1 and determines that the current virtual page address 1 does not correspond to the physical page address, that is, the virtual page address 1 access error.
  • the Master logical core triggers a page fault exception and traps the process into the EL1 privilege level. In this way, the process runs at the EL1 privilege level of the Master logical core, and the Master logical core can perform the target operation, that is, process the system call.
  • the Master logical core can repeatedly trigger page fault exceptions, thereby trapping the execution state of the process from the user state of the Master logical core to the target privilege level of the Master logical core's privileged state.
  • the page fault here is used to change the execution state of the process from the user state of the Master logical core to the target privilege level of the privileged state of the Master logical core. This page fault is different from the one triggered when the Slave logical core runs the process. Page fault, the latter is an exception that really needs to be handled during the running of the process.
  • the Master logic core After the Master logic core completes the target operation in the privileged state (or is understood to have handled ordinary exceptions), it can return to the springboard code segment. Specifically, the Master logic core can return to the page access instruction in the springboard code segment. After the page access instruction, the Master logical core continues to execute the slave call instruction, thereby triggering the operation of the Slave logical core. The Slave logical core continues execution from the interrupted position slave.pc. Furthermore, the Slave logical core can read the register information from the ordinary exception information in the configuration space, and based on the read register information, restore the running environment information of the process before the Slave logical core triggered the exception.
  • Figure 9 shows a schematic diagram of a method for switching the execution state of a process when the process receives an interrupt.
  • the text in the dotted box can represent the actions performed by the Master logical core or the Slave logical core.
  • the process receives an interrupt during the running of the Slave logical core.
  • the Slave logical core needs to write the running context (or interrupt information) of the process into the configuration space.
  • the interrupt information may include one or more of the following: privilege level information, instruction location where the interrupt was received, interrupt cause, interrupt occurrence address, interrupt parameters, register information, etc.
  • the privilege level information, interrupt parameters, register information, and interrupt occurrence address can be found in the description of the running context in the above common exception.
  • the instruction location that received the interrupt can also be recorded as slave.pc.
  • the Slave logical core resumes execution the Slave logical core can continue execution from this location slave.pc.
  • Interruption reason indicates the cause of the interruption, such as clock interruption, serial port interruption, network interruption, etc.
  • the hardware unit of the Slave logical core can trap the execution state of the process into a privileged state.
  • the hardware unit of the Slave logical core can also determine which privilege level the process will fall into in the privileged state based on the type of interrupt, such as falling into the EL1 privilege level or the EL2 privilege level.
  • the Slave logical core undergoes many operations during the execution of the salve.call instruction, such as the Master logical core sleeping, the Slave logical core triggering a running instruction, etc.
  • the time when an interrupt occurs is during the execution of salve.call.
  • the time point when the Master logic core responds to the interrupt is after the salve.call instruction is executed and the next instruction (ie, the master.pc instruction) is executed. before execution.
  • the Master logical core After the Master logical core completes the target operation in the privileged state (or is understood to have processed the interrupt), the Master logical core returns to master.pc in the springboard code segment. Subsequently, the Master logical core continues to execute the slave call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.
  • Figure 10 shows a schematic diagram of a method for switching the execution state of a process when a process triggers a RAS exception.
  • the text in the dotted box can represent the actions performed by the Master logical core or the Slave logical core.
  • RAS exceptions can be further divided into synchronous abort (SErrors for short) and asynchronous abort (SEI for short).
  • SErrors are related to the execution of instructions.
  • the return address maintained by SErrors when entering the exception state accurately reflects the instruction in which the exception occurred, and may occur at any step during the execution of the instruction. For example, failure in the instruction fetch phase, failure in the decoding phase, failure in the instruction execution phase, etc.
  • SErrors are similar to ordinary exceptions and are a synchronous event.
  • SEI has nothing to do with the executed instructions. SEI comes from an external memory system or an error on the bus, such as an unrecoverable error correcting code error (ECC error). SEI is similar to an interrupt and is an asynchronous event.
  • ECC error unrecoverable error correcting code error
  • RAS exception information may include one or more of the following: privilege level information, instruction location that triggers RAS exception, RAS exception cause, RAS exception occurrence address, RAS exception parameters, register information, etc.
  • the privilege level information, RAS exception parameters, register information, and RAS exception occurrence address can be found in the description of the running context in the above common exceptions.
  • the instruction location that triggers the RAS exception can also be recorded as slave.pc.
  • the Slave logical core resumes execution the Slave logical core can continue execution from the slave.pc.
  • RAS abnormality reason indicating the cause of RAS abnormality, such as error correction code error, etc.
  • the hardware unit of the Slave logical core can drop the execution state of the process from the original user state to the privileged state.
  • the privileged state can specifically be a firmware state.
  • the firmware state corresponds to the EL3 privilege level.
  • the hardware unit of the Slave logical core can trap the execution state of the process to the EL3 privilege level.
  • the user state can also be called the EL0 privilege level in the privileged state.
  • the EL0 privilege level is lower than other privilege levels in the privileged state.
  • the RAS exception occurs in master.pc.
  • the explanation is that the salve logical core undergoes many operations during the execution of the salve.call instruction, such as the Master logical core sleeping, the Slave logical core triggering a running instruction, etc.
  • the time when a RAS exception occurs is during the execution of salve.call.
  • the time point when the Master logical core responds to the RAS exception is after the salve.call instruction is executed, and the next instruction (i.e. the master.pc instruction ) before execution.
  • the Master logical core handles RAS exceptions in the EL3 privilege level and obtains the RAS exception processing results.
  • the RAS exception processing result can be used to indicate whether the RAS exception is recoverable.
  • the Master logical core returns from the EL3 privilege level to the EL1 privilege level, or in other words, returns from the firmware state to the kernel state.
  • the Master logical core obtains the RAS exception processing result at the EL1 privilege level.
  • the Master logical core performs the target operation at the EL1 privilege level and returns to the master recorded in the configuration space.
  • the instruction corresponding to the .pc position that is, the master.pc instruction.
  • the Master logical core performs panic kernel processing at the EL1 privilege level.
  • the firmware of the Master logical core may perform the following steps (a) to (c):
  • the Master logical core After the privileged state of the Master logical core processes the target operation, the Master logical core returns to the master.pc instruction in the springboard code segment. Subsequently, the Master logical core continues to execute the slave call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.
  • the above-mentioned general exception information, interrupt information, and RAS exception information can be collectively referred to as the running context of the process.
  • the exception cause, interrupt cause, and RAS exception cause can be collectively referred to as the suspension of the running process on the Slave logical core.
  • Reason that is, the reason for the suspension of the process; exception parameters, interrupt parameters, and RAS exception parameters can be collectively referred to as the execution parameters corresponding to the target operation of the process; the instruction location that triggers the exception, the instruction location that receives the interrupt, and the instruction location that triggers the RAS exception.
  • the location where the process was interrupted can be collectively referred to as the location where the process was interrupted, or the pause location of the process (slave.pc), or the information of the pause location of the process.
  • the running context of a process may include one or more of the following: the pause position of the process on the Slave logical core, the reason for the suspension of the process on the Slave logical core, execution parameters corresponding to the target operation, and register information. (ie, environment information when the running process is suspended) or privilege level information.
  • the Slave logical core runs the process and determines that the process triggers a common exception.
  • the Slave logical core switches the execution state of the process from the user mode of the Slave logical core to the user mode of the Master logical core.
  • the Master logical core starts executing from the instruction at the master.pc location (i.e., the master.pc instruction), and determines that it needs to go to the EL1 privilege level for processing based on the common exception, so it accesses the virtual page address 1 corresponding to the EL1 privilege level (shown as in Figure 11 page1), and then, after the Master logical core triggers the page fault exception corresponding to page1, the execution state of the process falls into the EL1 privilege level to perform the target operation.
  • the Master logic core After completing the target operation, the Master logic core returns to the instruction that accesses page1 (that is, the page access instruction), and then returns to instruction 1. Further, the Master logical core calls the slave.call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.
  • the Slave logical core runs the process and determines that the process has received an interrupt.
  • the hardware unit of the Slave logical core changes the execution state of the process from the user state of the Slave logical core directly to the privileged state of the Master logical core (such as EL1 privilege level).
  • the Master logical core runs the process so that the process performs the target operation. After the process completes the target operation, it returns to the instruction at the master.pc location (that is, the master.pc instruction), and then returns to instruction 1. Further, the Master logical core calls the slave.call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.
  • the Slave logical core runs the process and determines that the process triggers a RAS exception.
  • the hardware unit of the Slave logical core changes the execution state of the process from the user state of the Slave logical core directly to the privileged state of the Master logical core (such as EL3 privilege level).
  • the Master logical core runs the process so that the process performs the target operation. After the process completes the target operation, it returns to the instruction at the master.pc location (that is, the master.pc instruction), and then returns to instruction 1.
  • the Master logical core calls the slave.call instruction to trigger the Slave logical core to run.
  • the Slave logical core continues execution from the interrupted location slave.pc.
  • the Master logic core and the Slave logic core exchange information through the configuration space to realize the decoupling of the Master logic core and the Slave logic core, so that the Master logic core and the Slave logic core can develop independently, that is, Without destroying the architectural semantics/instruction space corresponding to the Master logical core, the independent evolution of the instruction set corresponding to the Slave logical core can be achieved.
  • the Slave logical core can run acceleration engines and algorithms, such as mySql One or more of the processes, graph calculation processes, or encryption and decryption operators can increase the computing speed compared to the Master logical core.
  • the Slave logical core can write the running context of the process into the configuration space.
  • the running context includes the pause location corresponding to the paused process of the Slave logical core.
  • the Slave logical core can read the pause position from the configuration space and continue to execute the process at the pause position. process. In this way, the process can switch the running state between the Master logical core and the Slave logical core.
  • the relationship between the logical core, the process and the target operation can be understood as the process runs in the logical core (Slave logical core or Master logical core), and the process executes the target operation, that is, its runtime
  • the logical core where it is located (such as the Master logical core) performs the target operation.
  • the computer program product includes a computer program or instructions.
  • the method in the above method embodiment is implemented.
  • this application provides a computer-readable storage medium.
  • Computer programs or instructions are stored in the computer-readable storage medium.
  • the computer program or instructions are executed by a computing device, the method in the above method embodiment is implemented. .
  • this application provides a computing device, including a processor.
  • the processor is connected to a memory.
  • the memory is used to store computer programs.
  • the processor is used to execute the computer program stored in the memory, so that the computing device implements the above method. Methods in Examples.

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Abstract

一种进程的执行状态切换方法及装置，用于在主逻辑核和从逻辑核二者解耦合情况下，实现运行在从逻辑核中的进程切换至主逻辑核中运行。在本申请中，方法包括：如果运行在从逻辑核的进程满足第一条件，在从逻辑核中暂停运行进程，并记录进程的暂停位置，暂停位置用于下次在从逻辑核中运行进程时确定执行位置，其中，第一条件用于指示进程待执行目标操作，且目标操作在进程的执行状态处于主逻辑核的特权态时能够被执行；将进程的执行状态由从逻辑核的用户态切换为主逻辑核的特权态；在主逻辑核中运行进程，以供进程执行目标操作。

Description

一种进程的执行状态切换方法及装置
相关申请的交叉引用
本申请要求在2022年03月11日提交中国专利局、申请号为202210238502.2、申请名称为“一种进程的执行状态切换方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及处理器领域，尤其涉及一种进程的执行状态切换方法及装置。
背景技术
现代计算机面对越来越复杂的计算需求，一种架构的中央处理器(central processing unit，CPU)已经无法满足业务的需要，很多方案会选择异构计算。所谓异构，就是将CPU、数字信号处理(digital signal processing，DSP)、图形处理器(graphics processing unit，GPU)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程逻辑门阵列(field programmable gate array，FPGA)等不同制程架构、不同指令集、不同功能的计算单元，组合起来形成一个混合的计算***。
以ARMv8-A体系架构为例，CPU物理核包括ARM64逻辑核和ARM32逻辑核，其中，ARM64逻辑核可执行特权级EL0至EL4中的一个，ARM32逻辑核可执行特权级EL0，其中EL0的特权级最低。在ARMv8-A体系架构中运行一个ARM32进程时，该ARM32进程具体是运行在ARM32逻辑核中，但是当ARM32进程需要执行高特权级操作(比如***调用)时，需要触发异常，以使得ARM32进程的执行状态由特权级EL0陷入至特权级EL1中，从而在ARM64逻辑核中执行该高特权级操作。随后，ARM32进程的执行状态再次由特权级EL1返回至特权级EL0，在ARM32逻辑核中继续执行。
在该方式中，ARM64逻辑核和ARM32逻辑核二者需要紧密耦合，比如ARM64逻辑核需要新增寄存器和向量表表项来支持ARM32逻辑核，该两个逻辑核不能独立演进。
发明内容
本申请提供一种进程的执行状态切换方法及装置，用于在灵活切换两个逻辑核对应执行状态的前提下，将两个逻辑核解耦合，从而可独立演进其中的一个逻辑核。
第一方面，本申请提供一种进程的执行状态切换方法，应用于CPU中，CPU包括物理核，物理核包括主(Master)逻辑核和从(Slave)逻辑核，方法包括：如果运行在从逻辑核的进程满足第一条件，在从逻辑核中暂停运行进程，并记录进程的暂停位置，该暂停位置可用于下次在从逻辑核中运行进程时确定执行位置，其中，第一条件用于指示进程待执行目标操作，且目标操作在进程的执行状态处于主逻辑核的特权态时能够被执行；将进程的执行状态由从逻辑核的用户态切换为主逻辑核的特权态；在主逻辑核中运行进程，以供进程执行目标操作。
上述技术方案中，在从逻辑核中运行进程且进程需要执行目标操作时，通过从逻辑核 记录进程的暂停位置，该暂停位置可用于下次在从逻辑核中运行进程时确定执行位置，如此，主逻辑核和从逻辑核无需共享寄存器，可实现在灵活切换两个逻辑核对应执行状态的前提下，将两个逻辑核解耦合，从而可独立演进其中的一个逻辑核。
在一种可能的实现方式中，记录进程的暂停位置，包括：通过从逻辑核将暂停位置的信息写入配置空间，配置空间用于主逻辑核与从逻辑核进行信息交互。通过在物理核中配置用于从逻辑核和主逻辑核进行信息交互的配置空间，实现主逻辑核和从逻辑核的解耦合，从而主逻辑核和从逻辑核二者可以独立发展，在不破坏主逻辑核对应的架构语义/指令空间的前提下，可实现从逻辑核对应指令集的独立演进。
在一种可能的实现方式中，方法还包括：将进程的执行状态由主逻辑核的特权态切换为从逻辑核的用户态；通过从逻辑核从配置空间读取暂停位置的信息；在从逻辑核中，从暂停位置开始继续运行进程。如此，在主逻辑核执行完成目标操作之后，可继续启动从逻辑核来继续运行进程，由于从逻辑核之前记录了暂停位置，则从逻辑核可从该暂停位置处继续运行，从而实现进程可在两个逻辑核之间切换，且进程可不间断地运行。
在一种可能的实现方式中，第一条件包括进程触发第一类异常，第一类异常包括除可靠性异常、可用性异常、以及可服务性RAS异常以外的其它异常；将进程的执行状态由从逻辑核的用户态切换为主逻辑核的特权态，包括：触发主逻辑核运行进程，以将进程的执行状态由从逻辑核的用户态切换为主逻辑核的用户态；从主逻辑核的特权态的多个特权级中确定第一类异常对应的目标特权级；将进程的执行状态由主逻辑核的用户态切换为主逻辑核的特权态的目标特权级。
在一种可能的实现方式中，将进程的执行状态由主逻辑核的用户态切换为主逻辑核的特权态的目标特权级之前，还包括：获取目标特权级对应的虚拟内存地址；确定虚拟内存地址未与物理内存地址建立映射关系。
上述技术方案中，通过主逻辑核访问目标特权级对应的虚拟内存地址，确定虚拟内存地址未与物理内存地址建立映射关系，则触发页面错误，主逻辑核可根据该触发的页面错误，将进程的执行状态由主逻辑核的用户态陷入至主逻辑核的特权态的目标特权级。如此，通过构造特殊异常(即页面错误)实现将进程的执行状态由主逻辑核的用户态陷入主逻辑核的特权态的目标特权级，减少进程陷入特权态的执行的复杂程度。
在一种可能的实现方式中，第一条件包括进程收到中断，或者进程触发RAS异常。由于中断或者RAS异常属于异步事件且需要快速被处理，则当运行在从逻辑核的进程收到中断或者触发RAS异常时，可通过CPU物理核中的硬件单元(或硬件部分)，将进程的执行状态由从逻辑核的用户态陷入至主逻辑核的特权态的目标特权级。
在一种可能的实现方式中，方法还包括：在主逻辑核中启动进程；如果进程的指令集属于从逻辑核运行的指令集，记录进程的起始位置，并触发从逻辑核进入运行状态；在从逻辑核中，从起始位置开始运行进程。上述技术方案中，某些进程(比如mySql进程、图计算进程或加解密算子)是需要运行在从逻辑核中的，当在主逻辑核中启动这些进程时，可确定这些进程需要运行在从逻辑核中，于是通过主逻辑核记录进程的起始位置，并触发从逻辑核进入运行状态，以使得从逻辑核读取该起始位置，并在该起始位置处运行该进程。
在一种可能的实现方式中，方法还包括：释放主逻辑核在运行进程时所占用的物理核的硬件资源；其中，硬件资源包括内存资源和/或输入输出资源。如此，该被释放的硬件资源，可被重新用于运行其他进程，有助于充分利用硬件资源。
在一种可能的实现方式中，方法还包括：通过从逻辑核记录如下信息中的一项或多项：在从逻辑核上暂停运行进程的原因，目标操作对应的执行参数，暂停运行进程时的环境信息，或，特权级信息；其中，特权级信息用于指示进程在执行目标操作时主逻辑核的特权态的特权级。如此，主逻辑核可根据这些参数正确处理目标操作。
在一种可能的实现方式中，从逻辑核可运行加速引擎及算法，比如mySql进程、图计算进程或加解密算子中的一项或多项，相比于主逻辑核运行这些进程，可提高运算速率。
第二方面，本申请提供一种进程的执行状态切换装置，装置可以是CPU。
装置包括处理器和存储器；存储器用于存储计算机程序；处理器用于调用存储器所存储的计算机程序，以执行如下步骤：如果运行在从逻辑核的进程满足第一条件，在从逻辑核中暂停运行进程，并记录进程的暂停位置，暂停位置用于下次在从逻辑核中运行进程时确定执行位置，其中，第一条件用于指示进程待执行目标操作，且目标操作在进程的执行状态处于主逻辑核的特权态时能够被执行；将进程的执行状态由从逻辑核的用户态切换为主逻辑核的特权态；在主逻辑核中运行进程，以供进程执行目标操作。
在一种可能的实现方式中，处理器在记录进程的暂停位置时，具体用于：通过从逻辑核将暂停位置的信息写入配置空间，配置空间用于主逻辑核与从逻辑核进行信息交互。
在一种可能的实现方式中，处理器还用于：将进程的执行状态由主逻辑核的特权态切换为从逻辑核的用户态；通过从逻辑核从配置空间读取暂停位置的信息；在从逻辑核中，从暂停位置开始继续运行进程。
在一种可能的实现方式中，第一条件包括进程触发第一类异常，第一类异常包括除可靠性异常、可用性异常、以及可服务性RAS异常以外的其它异常；处理器在将进程的执行状态由从逻辑核的用户态切换为主逻辑核的特权态时，具体用于：触发主逻辑核运行进程，以将进程的执行状态由从逻辑核的用户态切换为主逻辑核的用户态；从主逻辑核的特权态的多个特权级中确定第一类异常对应的目标特权级；将进程的执行状态由主逻辑核的用户态切换为主逻辑核的特权态的目标特权级。
在一种可能的实现方式中，处理器在将进程的执行状态由主逻辑核的用户态切换为主逻辑核的特权态的目标特权级之前，还用于：获取目标特权级对应的虚拟内存地址；确定虚拟内存地址未与物理内存地址建立映射关系。
在一种可能的实现方式中，第一条件包括进程收到中断或者触发RAS异常。
在一种可能的实现方式中，处理器还用于：在主逻辑核中启动进程；如果进程的指令集属于从逻辑核运行的指令集，记录进程的起始位置，并触发从逻辑核进入运行状态；在从逻辑核中，从起始位置开始运行进程。
在一种可能的实现方式中，处理器还用于：释放主逻辑核在运行进程时所占用的物理核的硬件资源；其中，硬件资源包括内存资源和/或输入输出资源。
在一种可能的实现方式中，处理器还用于：通过从逻辑核记录如下信息中的一项或多项：在从逻辑核上暂停运行进程的原因，目标操作对应的执行参数，暂停运行进程时的环境信息，或，特权级信息；其中，特权级信息用于指示进程在执行目标操作时主逻辑核的特权态的特权级。
第三方面，本申请提供一种进程的执行状态切换装置，装置可以是CPU。
装置包括主逻辑核模块和从逻辑核模块，从逻辑核模块用于确定运行在从逻辑核模块的进程满足第一条件时，暂停运行进程，并记录进程的暂停位置，暂停位置用于下次在从逻辑核模块中运行进程时确定执行位置，其中，第一条件用于指示进程待执行目标操作，且目标操作在进程的执行状态处于主逻辑核模块的特权态时能够被执行；从逻辑核模块还用于将进程的执行状态由从逻辑核模块的用户态切换为主逻辑核模块的特权态；主逻辑核模块用于运行进程，以供进程执行目标操作。
在一种可能的实现方式中，从逻辑核模块在记录进程的暂停位置时，具体用于将暂停位置的信息写入配置空间，配置空间用于主逻辑核模块与从逻辑核模块进行信息交互。
在一种可能的实现方式中，主逻辑核模块还用于将进程的执行状态由主逻辑核模块的特权态切换为从逻辑核模块的用户态；从逻辑核模块还用于从配置空间读取暂停位置的信息，从暂停位置开始继续运行进程。
在一种可能的实现方式中，第一条件包括进程触发第一类异常，第一类异常包括除可靠性异常、可用性异常、以及可服务性RAS异常以外的其它异常；从逻辑核模块具体用于触发主逻辑核模块运行进程，以将进程的执行状态由从逻辑核模块的用户态切换为主逻辑核模块的用户态；主逻辑核模块具体用于从主逻辑核模块的特权态的多个特权级中确定第一类异常对应的目标特权级，以及将进程的执行状态由主逻辑核模块的用户态切换为主逻辑核模块的特权态的目标特权级。
在一种可能的实现方式中，主逻辑核模块在将进程的执行状态由主逻辑核模块的用户态切换为主逻辑核模块的特权态的目标特权级之前，还用于获取目标特权级对应的虚拟内存地址；确定虚拟内存地址未与物理内存地址建立映射关系。
在一种可能的实现方式中，第一条件包括进程收到中断或者触发RAS异常。
在一种可能的实现方式中，主逻辑核模块还用于启动进程，如果进程的指令集属于从逻辑核运行的指令集，则记录进程的起始位置，并触发从逻辑核模块进入运行状态；从逻辑核模块还用于从起始位置开始运行进程。
在一种可能的实现方式中，主逻辑核模块释放在运行进程时所占用的物理核的硬件资源；其中，硬件资源包括内存资源和/或输入输出资源。
在一种可能的实现方式中，从逻辑核模块还用于记录如下信息中的一项或多项：在从逻辑核上暂停运行进程的原因，目标操作对应的执行参数，暂停运行进程时的环境信息，或，特权级信息；其中，特权级信息用于指示进程在执行目标操作时主逻辑核的特权态的特权级。
第四方面，本申请实施例提供一种芯片***，包括：处理器和存储器，所述处理器与存储器耦合，所述存储器用于存储程序或指令，当所述程序或指令被所述处理器执行时，使得该芯片***实现上述第一方面或第一方面的任一种可能的实现方式中的方法。
第五方面，本申请提供一种计算机程序产品，计算机程序产品包括计算机程序或指令，当计算机程序或指令被装置执行时，实现上述第一方面或第一方面的任一种可能的实现方式中的方法。
第六方面，本申请提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序或指令，当计算机程序或指令被计算设备执行时，实现上述第一方面或第一方面的任一种可能的实现方式中的方法。
第七方面，本申请提供一种计算设备，包括处理器，所述处理器与存储器相连，所述存储器用于存储计算机程序，所述处理器用于执行所述存储器中存储的计算机程序，以使得所述计算设备执行上述第一方面或第一方面的任一种可能的实现方式中的方法。
上述第二方面至第七方面中任一方面可以达到的技术效果可以参照上述第一方面中有益效果的描述，此处不再重复赘述。
附图说明
图1为一种ARMv8-A体系架构的示意图；
图2为一种AArch64和AArch32两种执行状态切换的过程的示意图；
图3为本申请提供的一种芯片***的架构示意图；
图4为本申请提供的一种Master逻辑核和Slave逻辑核中运行进程的示意图；
图5为本申请提供的一种执行状态的切换方法流程示意图；
图6为本申请提供的一种启动进程的示意图；
图7为本申请提供的一种切换进程的执行状态的方法示意图；
图8为本申请提供的一种Master逻辑核将进程陷入至目标特权级的示意图；
图9为本申请提供的再一种切换进程的执行状态的方法示意图；
图10为本申请提供的又一种切换进程的执行状态的方法示意图；
图11为本申请提供的再一种执行状态的切换方法流程示意图。
具体实施方式
为了更好的解释本申请实施例，先对本申请中的相关术语或技术解释：
(1)程序和进程
程序是一组指令的有序集合，它只是一个静态的实体。
进程是程序在某个数据集上的执行。进程是一个动态的实体，它有自己的生命周期。进程因创建而产生，因调度而运行，因等待资源或事件而被处于等待状态，因完成任务而被撤消。进程反映了一个程序在一定数据集上运行的全部动态过程。
(2)用户态(user mode)和内核态(kernel mode)
当一个进程在执行用户代码时处于用户运行状态(又可称为是用户态)。当一个进程因为***调用陷入内核代码中执行时，该进程处于内核运行状态(又可称为是内核态)。执行的内核代码会使用当前进程的内核栈，每个进程都有自己的内核栈。
用户运行一个程序，该程序创建的进程开始时运行自己的代码，处于用户态。在进程需要执行文件操作、网络数据发送等操作时，则通过write(写)、send(发送)等***调用来调用内核的代码。进程进入内核地址空间去执行内核代码来完成相应的操作。内核态的进程执行完后又会回到用户态。用户态的进程不能随意操作内核地址空间。
(3)CPU、物理核、逻辑核
CPU不等于物理核，更不等于逻辑核。
物理核(physical core/processor)是可看到的、真实的CPU核，物理核有独立的电路元件以及L1、L2缓存，可以独立地执行指令。
逻辑核(logical core/processor，LCPU):在同一个物理核内，逻辑层面的核。
其中，一个CPU可以有多个物理核。一个物理核可分成多个逻辑核。
(4)实时操作***(kernel)，是指大多数操作***的核心部分。它由操作***中用于管理存储器、文件、外设和***资源的部分组成。
(5)可执行和可连接格式(Executable and Linkable Format,ELF)文件，是指在Unix和X86-64 Linux上的目标文件。其中目标文件指的是，用于存放目标代码的计算机文件，目标文件中可包含着机器代码、代码在运行时使用的数据、调试信息等，是从源代码文件产生程序文件这一过程中的中间产物。
(6)同步操作和异步操作
同步操作，指的是调用方调用时，需要等待这个调用返回结果才能继续往后执行。
异步操作，与同步操作相反，调用方发出调用之后，无需等待调用结果，而是继续执行后续操作，被调用者通过状态来通知调用者，或者通过回掉函数来处理这个调用。
(7)可靠性、可用性、耐用性(reliability、availability、serviceability，RAS)
reliability，指的是***必须尽可能的可靠，不会意外的崩溃，重启甚至导致***物理损坏。availability，指的是***必须能够确保尽可能长时间工作而不下线，即使***出现一些小的问题也不会影响整个***的正常运行。serviceability，指的是***能够提供便利的诊断功能，如***日志，动态检测等手段方便管理人员进行***诊断和维护操作，从而及早的发现错误并且修复错误。RAS作为一个整体，其作用在于确保整个***尽可能长期可靠的运行而不下线，并且具备足够强大的容错机制。
(8)固件(firmware)，一般存储于设备中的电可擦除只读存储器(electrically erasable programmable ROM，EEPROM)或FLASH芯片中。firmware比如是计算机主板上的基本输入/输出***BIOS(basic input/output system)。
(9)寄存器，是中央处理器内的组成部分。寄存器是有限存贮容量的高速存贮部件，寄存器可用于暂存指令、数据和地址。程序状态保存寄存器(saved program status register，SPSR)，用于保存程序状态寄存器(current program status register，CPSR)的状态，以便异常返回后恢复异常发生时的工作状态。当特定的异常中断发生时，这个寄存器用于存放当前程序状态寄存器的内容。在异常中断退出时，可以用SPSR来恢复CPSR。
基于上述相关术语或技术解释，如下解释说明本申请所适用的场景。
在CPU物理核中，可包括主(Master)逻辑核和从(Slave)逻辑核。CPU物理核可运行多个进程，该多个进程可运行于Master逻辑核或Slave逻辑核。比如Master逻辑核是ARM64逻辑核，Slave逻辑核是ARM32逻辑核，则ARM64的进程可运行于ARM64逻辑核中，ARM32的进程可运行于ARM32逻辑核中。而通常情况下，不管是运行于哪种逻辑核中的进程，均可由Master逻辑核来启动，Master逻辑核若确定该进程需要运行于Slave逻辑核，则可调用Slave逻辑核，以使得该进程在Slave逻辑核中运行。
如下，以Master逻辑核是ARM64逻辑核，Slave逻辑核是ARM32逻辑核为例说明ARM64逻辑核如何启动ARM32进程，并将ARM32进程运行于ARM32逻辑核中。
示例性的，在ARMv8体系架构中，可同时支持AArch32(或称为ARM32)和AArch64(或称为ARM64)两种执行状态。其中，AArch64执行状态支持A64指令集，可运行ARM64进程。AArch32执行状态支持T32和A32指令集，可运行ARM32进程。
ARMv8-A中特权级(privilege level)的概念被称为异常级别(EL,exception level)，它是 程序运行所处特权级别的逻辑划分。异常级别被划分为以下四种：
EL0：通常用户程序；
EL1：操作***内核；
EL2：虚拟机监视器；
EL3：低级固件，包括安全监控(Secure Monitor)。
其中，特权级的数字越大，其特权越高。通常情况下，一个软件，例如应用程序，操作***内核或是虚拟机监视器仅占据一个异常级别。
ARMv8-A体系架构可参见图1所示，ARM32逻辑核的执行状态为AArch32，ARM64逻辑核的执行状态为AArch64。其中AArch32可对应于EL0特权级，AArch64可对应于EL0和EL1特权级。或者也可以理解，在EL0特权级，可在AARCH64和AARCH32两种执行状态运行用户态进程；在EL1特权级，可在AArch64执行状态运行内核态进程。
进一步的，ARMv8-A体系架构可具有如下特点：
(1)AArch32支持的A32和T32指令集，以及AArch64支持的A64指令集可通过执行状态(execution state)进行封装。
(2)CPU在任意时刻必须处于AArch32或AArch64的执行状态，AArch32、AArch64两个执行状态在切换时，CPU需要通过异常陷入高特权级。
(3)AArch32和AArch64是紧耦合的，二者可共用寄存器。
(4)AArch32和AArch64不能互相调用(如A64指令集的函数不能调用A32指令集或T32指令集的函数)，AArch32和AArch64二者不能用作对方的扩展。
(5)为了实现AArch64支持AArch32的异常处理，在异常向量表上，增加一组ARM32EL0异常的处理入口。示例性的，异常向量表中包括有异常与异常处理程序之间的对应关系。AArch32在异常时，需要将低特权级陷入至高特权级，AArch64在高特权级时访问异常向量表，从中确定需要调度的异常处理程序。
如图2为本申请示例性提供的一种AArch64和AArch32两种执行状态切换的过程，其中，该过程具体是在AArch64执行状态下，运行ARM32可执行程序(可简称为程序)。
步骤201，在AArch64执行状态下，EL0用户态加载ARM32进程会陷入到EL1内核态，在EL1内核中解析ELF文件格式，发现EL0用户态需要运行的是A32指令集的程序，那么在返回EL0用户态时会通过设置SPSR切换到AArch32执行状态，即执行状态由AArch64切换为AArch32。
步骤202，在AArch32执行状态运行的ARM32进程在需要处理异常时，需要通过陷入至EL1内核态来完成，即执行状态再次由AArch32切换为AArch64。EL1内核态在处理完异常之后根据需求再返回到EL0的AArch32执行状态。或者，在AArch32执行状态运行的ARM32进程运行完毕后，需要通过陷入至EL1内核态来完成。
如此，ARM32进程所运行的逻辑核需要经常地在ARM64逻辑核和ARM32逻辑核之间切换，该异常切换需要硬件完成大量工作。ARM64逻辑核和ARM32逻辑核之间的切换，需要基于异常向量表中记录的异常和该异常对应的处理程序，其中，该异常向量表存储于寄存器中，且该异常向量表需要占用大量寄存器。ARM64逻辑核和ARM32逻辑核共享寄存器，二者处于紧密耦合状态，无法独立演进。
本申请提供一种进程的执行状态切换方法及装置，用于在灵活切换两个逻辑核对应执 行状态的前提下，将两个逻辑核解耦合，从而可独立演进其中的一个逻辑核。
为方便描述本申请中的切换方法，先对本申请适用的***架构解释说明。如图3为一种芯片***的架构示意图，该芯片***中包括有多个CPU物理核，每个CPU物理核中可包括两个逻辑核，可分别表示为Master逻辑核和Slave逻辑核。
Master逻辑核可用于执行特权态的操作，Slave逻辑核用于执行用户态的操作。其中，特权态的多个特权级均高于用户态的特权级。比如，Master逻辑核是ARM64，Master逻辑核实现的特权态对应于EL1、EL2和EL3三个特权级，Slave逻辑核实现用户态的特权级，其中EL1、EL2和EL3三个特权级均高于用户态的特权级。
此外，Master逻辑核还可用于执行用户态的操作，即可实现用户态的特权级。仍然以Master逻辑核是ARM64为例，Master逻辑核实现的用户态包括EL0特权级。Master逻辑核实现的用户态特权级，与Slave逻辑核实现的用户态特权级可为相同特权级。
示例性的，用户态程序可根据其指令集在Master逻辑核中运行，也可以在Slave逻辑核中运行。***软件(如Kernel/Hypervisor/Firmware)只能在Master逻辑核中运行。
进一步的，Master逻辑核与Slave逻辑核采用不同的指令集，其中，Master逻辑核的指令集可以是X86或ARM等当前主流指令集。Slave逻辑核的指令集可以是自研指令集。Slave逻辑核的算力可高于Master逻辑核的算力。
其中，运行在Slave逻辑核的进程(如下可简称为进程)中包括可执行代码段，该可执行代码段可包括跳板代码段(英文可表示为trampoline code)和主体代码段两大部分。
其中，跳板代码段运行在Master逻辑核，用于调用Slave逻辑核运行进程。可以理解，由于进程的加载发生在Master逻辑核，而进程的运行是发生在Slave逻辑核，则需要Master逻辑核中跳板代码段来将进程由原来的运行在Master逻辑核切换至运行在Slave逻辑核。
主体代码段运行在Slave逻辑核，其中主体代码段即运行进程的主要代码。
在Master逻辑核和Slave逻辑核之间包括有配置空间，该配置空间可以理解为两个逻辑核之间的交互界面，该配置空间可以是寄存器组，也可以是一片特殊的内存空间。该配置空间可用于Master逻辑核和Slave逻辑核之间进行信息交互，示例性的，Master逻辑核在启动某个进程时，可确定该进程需要运行在Slave逻辑核中，于是将Slave逻辑核执行该进程的相关参数写入至配置空间中，Slave逻辑核从该配置空间中读取该相关参数，并根据读取到的参数开始执行该进程。
每个CPU物理核对应于一个核外资源，该核外资源比如是cache(缓存)或存储器管理单元(memory management unit，MMU)。
可将多个CPU物理核以及该多个CPU物理核分别对应的核外资源，一起封装于一个芯片***中，该芯片***可以连接有内存和外设。
以Master逻辑核是ARM64逻辑核为例，解释说明Master逻辑核和Slave逻辑核中运行的进程。其中，ARM64逻辑核中的Master指令集又可称为是A64指令集，运行在ARM64逻辑核上的进程又可称为是A64进程。如图4中，该芯片***对应于用户态、特权态和硬件部分。A64指令集的用户态进程和***软件(如Kernel/Hypervisor/Firmware)在ARM64逻辑核上运行，Slave指令集的用户态进程(即进程)在Slave逻辑核上运行。
如下解释说明本申请中进程的执行状态的切换方法，该方法可参见图5所示的流程图。
步骤501，在Master逻辑核上启动进程，并确定该进程需要运行在Slave逻辑核上。 启动Slave逻辑核，以使得Slave逻辑核运行该进程。其中，在Slave逻辑核上运行进程时，进程仅可执行用户态的操作。
步骤502，在确定进程需要执行特权态的操作时，将进程的执行状态由用户态切换至特权态，相应的，需要将该进程切换到Master逻辑核中运行。
步骤503，在Master逻辑核中的进程处理完该特权态的操作之后，进程的执行状态可由特权态再次切换回用户态，相应的，将该进程再次切换回Slave逻辑核中运行。
在上述进程的执行状态由特权态切换至用户态，或者由用户态切换至特权态时，Master逻辑核和Slave逻辑核二者可通过配置空间来相互交换信息。
图6为本申请示例性提供的一种Master逻辑核启动进程的示意图。参照图6解释说明上述步骤501，其中虚线方框中文字可表示Master逻辑核或者Slave逻辑核执行的动作。
Master逻辑核在用户态上启动运行进程，并将该进程由用户态陷入到特权态。Master逻辑核从内存中加载进程的数据。
其中，进程的数据比如进程的代码段(code segment/text segment)、数据段(data segment)、可执行文件等。代码段通常是用来存放程序执行代码的内存区域。数据段通常是指用来存放程序中已初始化的全局变量的内存区域。可执行文件比如是ELF文件。
示例性的，进程的可执行文件中记载有该进程是否需要运行于Slave逻辑核的标识。相应的，Master逻辑核根据该标识，确定该进程是否需要运行于Slave逻辑核。
又示例性的，Master逻辑核根据代码段，确定进程所执行的指令集属于Slave逻辑核运行的指令集，进而确定该进程需要运行于Slave逻辑核。
Master逻辑核若确定该进程需要运行于Slave逻辑核，则可将该进程从特权态返回至Slave逻辑核的用户态，以使得Slave逻辑核在用户态执行该进程。具体的，Master逻辑核在将该进程从特权态返回至Slave逻辑核的用户态时，具体可将该进程返回至Master逻辑核中跳板代码段的入口，并通过跳板代码段将进程的入口写入至配置空间，从而触发Slave逻辑核从该入口处开始执行进程。
具体的，Master逻辑核可通过跳板代码段将进程的起始位置(或者起始位置的信息)写入配置空间中，然后Master逻辑核通过跳板代码段操作配置空间，以触发启动指令(英文可称为是slave call指令)，从而通过slave call指令启动Slave逻辑核。相应的，Slave逻辑核从配置空间中读取该起始位置，根据该读取到的起始位置启动进程。
此外，Master逻辑核在调用slave call指令之后，可释放Master逻辑核在运行进程时所占用的物理核的硬件资源，其中硬件资源可以包括内存资源、输入/输出(input/output，I/O)资源中一项或多项。如此，该部分被释放的硬件资源，可被重新用于执行其他进程，有助于充分利用硬件资源。
进一步的，Master逻辑核将slave call指令的下一条指令的位置(这个位置可记为master.pc)写入至配置空间中。该master.pc可用于Master逻辑核再次需要执行该进程时，知道从哪个位置上开始执行，该实现方式可参见下述实施例中关于步骤502的描述。如下，为方便描述，可将该slave call指令的下一条指令称为是master.pc指令。
在Slave逻辑核执行进程时，可能存在进程满足第一条件的情况，其中，第一条件可用于指示进程需要执行特权态的操作，此处，可将该特权态的操作称为是目标操作，也即第一条件可用于指示进程需要执行目标操作。进一步的，Slave逻辑核需要暂停当前运行在 Slave逻辑核中的进程，然后将该进程切换至由Master逻辑核运行，如此，运行在Master逻辑核中的该进程可执行该目标操作。
进一步的，基于目标操作的不同类型，可将目标操作触发的暂停划分为异常(Exception)和中断(Interruption)。
异常，指来自CPU执行指令内部的事件。异常又可分为第一类异常和第二类异常，其中第一类异常可以是普通异常，第二类异常可以是RAS异常。RAS异常比如内存页面物理损坏，普通异常是除RAS异常以外的其他异常，普通异常比如***调用(system call，或简称为syscall)、页面错误(page fault)，指令故障(instruction fault)等。
中断，指来自CPU执行指令以外的事件发生，比如时钟中断、串口中断、网络中断、I/O中断停止等。以时钟中断为例，时钟中断表示一个固定的时间片已到，让CPU处理计时、启动定时运行的任务等。
如下基于普通异常、中断、RAS异常三种情况解释上述步骤502。
一、普通异常
图7示出一种进程触发普通异常时切换进程的执行状态的方法示意图。其中虚线方框中文字可表示Master逻辑核或者Slave逻辑核执行的动作。
进程在Slave逻辑核的运行过程中，由于需要执行目标操作，则触发了普通异常。Slave逻辑核需要将该进程的运行上下文(或称为普通异常信息)写入至配置空间中。
普通异常信息中可包括如下中一项或多项：特权级信息、触发异常的指令位置、异常原因、异常发生地址、异常参数、寄存器信息等。
其中特权级信息用于指示目标操作对应的特权级(可称为目标特权级)，即Master逻辑核需要通过哪个特权级来处理这个异常。比如目标操作是***调用，则目标特权级为EL1。
触发异常的指令位置，可认为是进程被打断的位置，可记为slave.pc。当Slave逻辑核恢复执行时，Slave逻辑核可从该位置slave.pc继续执行。其中，可将位置slave.pc对应的指令称为是slave.pc指令。
异常原因，指示在从逻辑核上暂停运行进程的原因，或者指示导致异常发生的原因，比如***调用、页面错误、指令故障等。
异常发生地址，比如访问的内存中的位置。
异常参数，比如***调用需要传递的参数。
寄存器信息，用于指示在Slave逻辑核中暂停运行进程时Slave逻辑核中的运行环境信息，该运行环境信息可用于Slave逻辑核继续执行进程。寄存器信息比如是SPSR信息。
相应的，Slave逻辑核对应的硬件资源可在触发目标操作的指令位置处释放(Retired)，Slave硬件单元将该进程由原来的在Slave逻辑核上运行，切换至在Master逻辑核上运行。相应的，Master逻辑核读取配置空间中的位置master.pc，然后根据该位置master.pc，从跳板代码段中slave call指令的下一条指令(即master.pc指令)处继续执行。
可以理解，该进程的执行状态是由Slave逻辑核的用户态，切换至了Master逻辑核的用户态，Master逻辑核需要进一步将该进程由Master逻辑核的用户态切换至Master逻辑核的特权态。具体的，Master逻辑核还可读取配置空间中该进程的普通异常信息，根据该进程的普通异常信息，将进程的执行状态由Master逻辑核的用户态，陷入至Master逻辑核的特权态。其中，Master逻辑核可根据普通异常信息中的特权级信息，确定将该进程陷 入至特权态的目标特权级。
在该进程陷入至目标特权级之后，Master逻辑核进一步根据普通异常信息中异常原因、异常发生地址、异常参数等信息，执行目标操作，也即处理该普通异常。
如下，以普通异常分别为***调用和页面错误为例说明。
1、***调用
进一步的，异常参数中可包括***调用标识(syscall id)和***调用入参。
Master逻辑核可从配置空间的普通异常信息中读取***调用标识和***调用入参，根据这两个参数构造一个***调用，接着下发这个***调用，也即，Master逻辑核特权态看到的是这个转换后的***调用。在***调用执行完毕后，Master逻辑核可将该***调用的返回值写入到配置空间，如此，Slave逻辑核可从配置空间中读取到该***调用的返回值。
示例性的，Master逻辑核可按照Master逻辑核对应架构的二进制接***互(application binary interface，ABI)规则构造该***调用，从而适用于不同CPU。相应的，Master逻辑核仍然按照该ABI规则将***调用的返回值写入到配置空间。
2、页面错误
进一步的，异常参数中可包括页面错误对应的虚拟页面地址。
Master逻辑核可从配置空间的普通异常信息中读取虚拟页面地址，并为该虚拟页面地址申请物理页面地址，随后将该虚拟页面地址和物理页面地址建立映射关系，并更新页表。其中虚拟页面地址又可称为是虚拟内存地址，物理页面地址又可称为是物理内存地址。
需要指出的是，由于进程导致的普通异常数量较多，本申请可针对不同的普通异常，确定这些普通异常所对应的特权级。可以理解，一个特权级可对应于多种普通异常，比如EL1特权级对应于***调用、页面错误、指令故障等，在发生这类异常时，Master逻辑核可将进程陷入至EL1特权级进行处理。
在一种可能实现方式中，Master逻辑核将进程的执行状态由Master逻辑核的用户态，陷入至Master逻辑核的特权态的目标特权级，可以是通过构造特殊异常的方式实现。具体可参见图8示出的陷入方式。
预先说明的是，可在实时操作***中新增两个虚拟页面地址，该两个虚拟页面地址分别对应于特权态(具体可以是内核态)的两个特权级。比如内核态中的两个特权级分别是EL1特权级和EL2特权级，其中，虚拟页面地址1对应于EL1特权级，虚拟页面地址2对应于EL2特权级。进一步的，该两个虚拟页面地址未与物理页面地址建立映射关系。
相应的，Master逻辑核可以根据Slave逻辑核触发的普通异常的类型，从特权态对应的多个特权级中选择该普通异常对应的目标特权级；然后从多个虚拟页面地址中确定出目标特权级对应的虚拟页面地址。Master逻辑核通过执行页面访问指令，来访问该目标特权级对应的虚拟页面地址，确定该虚拟页面地址未与物理页面地址建立映射关系，于是会触发异常(即页面错误)。随后，Master逻辑核由用户态陷入至特权态中的目标特权级。
示例性的，Master逻辑核确定进程触发的异常为***调用，Master逻辑核根据***调用确定需要将进程陷入至EL1特权级。Master逻辑核访问虚拟页面地址1，并确定当前虚拟页面地址1未对应于物理页面地址，也即虚拟页面地址1访问错误。随后，Master逻辑核触发页面错误异常，并将进程陷入至EL1特权级。如此，进程在Master逻辑核的EL1特权级运行，Master逻辑核可执行目标操作，也即处理该***调用。
此处，无需对Master逻辑核访问该虚拟页面地址触发的页面错误，执行缺页处理，如 此，Master逻辑核可以重复触发页面错误异常，从而将进程的执行状态由Master逻辑核的用户态，陷入至Master逻辑核的特权态的目标特权级。
进一步的，此处的页面错误，用于将进程的执行状态由Master逻辑核的用户态，陷入至Master逻辑核的特权态的目标特权级，该页面错误区分于Slave逻辑核运行进程时触发的页面错误，后者是进程运行中的真正需要处理的异常。
Master逻辑核在特权态执行完目标操作(或理解为处理完普通异常)之后，可以返回至跳板代码段中。具体的，Master逻辑核可返回至跳板代码段中的页面访问指令。Master逻辑核在页面访问指令之后，继续执行slave call指令，从而触发Slave逻辑核运行，Slave逻辑核从被打断位置slave.pc位置继续执行。进一步的，Slave逻辑核可从配置空间的普通异常信息中读取寄存器信息，根据读取到的寄存器信息，恢复Slave逻辑核触发异常之前的、该进程的运行环境信息。
二、中断
图9示出一种进程收到中断时切换进程的执行状态的方法示意图。其中虚线方框中文字可表示Master逻辑核或者Slave逻辑核执行的动作。
进程在Slave逻辑核的运行过程中收到了中断，Slave逻辑核需要将该进程的运行上下文(或称为中断信息)写入至配置空间中。
中断信息中可包括如下中一项或多项：特权级信息、收到中断的指令位置、中断原因、中断发生地址、中断参数、寄存器信息等。其中，特权级信息、中断参数、寄存器信息、中断发生地址均可参见上述普通异常中关于运行上下文的描述。
收到中断的指令位置同样可记为slave.pc。当Slave逻辑核恢复执行时，Slave逻辑核可从该位置slave.pc继续执行。
中断原因，指示导致中断发生的原因，比如时钟中断、串口中断、网络中断等。
由于中断属于异步事件且需要快速被处理，则Slave逻辑核的硬件单元可将进程的执行状态陷入至特权态。此处，Slave逻辑核的硬件单元也可根据中断的类型，确定将进程陷入至特权态的哪个特权级，比如陷入至EL1特权级或EL2特权级。
从Master逻辑核的角度来看，中断发生的位置是在master.pc。解释为，Slave逻辑核在执行salve.call指令的过程中发生了很多操作，比如Master逻辑核休眠、Slave逻辑核触发运行指令等。而对于Master逻辑核来说，发生中断的时机是在salve.call的执行过程中，Master逻辑核响应中断的时间点是在salve.call指令执行完，下一条指令(即master.pc指令)的执行前。
Master逻辑核在特权态执行完目标操作(或理解为处理完中断)之后，Master逻辑核返回到跳板代码段中的master.pc。随后，Master逻辑核继续执行slave call指令触发Slave逻辑核运行，Slave逻辑核从被打断位置slave.pc处继续执行。
三、RAS异常
图10示出一种进程触发RAS异常时切换进程的执行状态的方法示意图。其中虚线方框中文字可表示Master逻辑核或者Slave逻辑核执行的动作。
RAS异常可进一步划分为同步中止(Synchronous abort，简称SErrors)和异步中止(Asynchronous abort，简称SEI)。
其中，SErrors与指令的执行有关。SErrors在进入异常状态时候保持的返回地址精准的反应了发生异常的指令，有可能在执行指令过程中的任何一步发生。例如，在取指阶段失败，在译码阶段失败，在指令执行阶段等。SErrors与普通异常类似，是一个同步事件。
SEI与执行的指令无关。SEI是来自于外部的存储***(memory system)，或者来自于总线(bus)上的错误，例如不可恢复的误差校正码错误(error correcting code error，ECC error)。SEI与中断类似，是一个异步事件。
进程在Slave逻辑核的运行过程中，由于需要执行目标操作，则触发了RAS异常。Slave逻辑核需要将该进程的运行上下文(或称为RAS异常信息)写入至配置空间中。
RAS异常信息中可包括如下中一项或多项：特权级信息、触发RAS异常的指令位置、RAS异常原因、RAS异常发生地址、RAS异常参数、寄存器信息等。
其中，特权级信息、RAS异常参数、寄存器信息、RAS异常发生地址均可参见上述普通异常中关于运行上下文的描述。
触发RAS异常的指令位置同样可记为slave.pc。当Slave逻辑核恢复执行时，Slave逻辑核可从该slave.pc继续执行。
RAS异常原因，指示导致RAS异常发生的原因，比如误差校正码错误等。
Slave逻辑核的硬件单元可将进程的执行状态，由原来的用户态陷入至特权态。其中，特权态具体可以固件(firmware)态，比如该firmware态对应于EL3特权级。相应的，Slave逻辑核的硬件单元可将进程的执行状态陷入至EL3特权级。在RAS异常中，还可将用户态称为是特权态中的EL0特权级，该EL0特权级低于特权态中的其他特权级。
从Master逻辑核的特权态角度来看，RAS异常发生的位置是在master.pc。解释为，salve逻辑核在执行salve.call指令的过程中发生了很多操作，比如Master逻辑核休眠、Slave逻辑核触发运行指令等。而对于Master逻辑核来说，发生RAS异常的时机是在salve.call的执行过程中，Master逻辑核响应RAS异常的时间点是在salve.call指令执行完，下一条指令(即master.pc指令)的执行前。
Master逻辑核在EL3特权级中处理RAS异常，得到RAS异常的处理结果。其中RAS异常的处理结果可用于指示RAS异常是否可恢复。Master逻辑核从EL3特权级返回至EL1特权级，或者说，从firmware态返回至内核态。
相应的，Master逻辑核在EL1特权级获取RAS异常的处理结果，根据RAS异常的处理结果确定RAS异常可恢复时，Master逻辑核在EL1特权级执行目标操作，并返回至配置空间中记录的master.pc位置对应的指令(即master.pc指令)。根据RAS异常的处理结果确定RAS异常不可恢复时，Master逻辑核在EL1特权级执行panic内核处理。
在一种可能方式中，Master逻辑核在EL3特权级中处理RAS异常时，具体可以是Master逻辑核的firmware执行如下步骤(a)至(c)：
(a)保存用户态上下文，恢复EL3特权级上下文。
(b)读取配置空间中RAS异常信息，根据RAS异常信息对RAS异常做处理，比如尝试对内存页面进行修复。
(c)保存EL3特权级上下文，恢复用户态上下文，设置ESR_EL1、FAR_EL1、SPSR_EL1等寄存器，由于EL1特权级是通过ESR_EL1、FAR_EL1、SPSR_EL1这些寄存器来获取异常的一些状态，设置这些寄存器的目的是使EL1特权级认为异常的来源为用户态，在EL1特权级处理异常后，通过ERET指令返回用户态，而非返回至EL3特权级对应的Fireware。
Master逻辑核的特权态处理完目标操作之后，Master逻辑核返回到跳板代码段中的master.pc指令。随后，Master逻辑核继续执行slave call指令触发Slave逻辑核运行，Slave逻辑核从被打断位置slave.pc处继续执行。
需要说明的是，上述普通异常信息、中断信息、RAS异常信息均可统称为是进程的运行上下文，其中，异常原因、中断原因、RAS异常原因可统称为是在Slave逻辑核上暂停运行进程的原因，也即进程的暂停原因；异常参数、中断参数、RAS异常参数可统称为是进程的目标操作对应的执行参数；触发异常的指令位置、收到中断的指令位置、触发RAS异常的指令位置可统称为是进程被打断的位置，或者进程的暂停位置(slave.pc)，或者进程的暂停位置的信息。也可以理解，进程的运行上下文可包括如下中一项或多项：Slave逻辑核上暂停运行进程的暂停位置、在Slave逻辑核上暂停运行进程的暂停原因、目标操作对应的执行参数、寄存器信息(即暂停运行进程时的环境信息)或特权级信息。
此外，还需要补充的是，上述图6至图10中仅标注出相关实施例中的主要步骤，且各图中的步骤序号，仅在其所在图中表示各动作的前后顺序。
为了更好的说明本申请实施例中普通异常、中断或RAS异常情况下，Master逻辑核和Slave逻辑核的执行位置，参照图11中例子继续说明，其中图11中左边代码段可认为是Master逻辑核中包含的跳板代码段。
Slave逻辑核运行进程并确定进程触发普通异常，Slave逻辑核将进程的执行状态由Slave逻辑核的用户态，切换至Master逻辑核的用户态。Master逻辑核从master.pc位置的指令(即master.pc指令)开始执行，并根据该普通异常确定需要去EL1特权级处理，于是访问EL1特权级对应的虚拟页面地址1(图11中表示为page1)，随后，Master逻辑核触发该page1对应的页面错误异常之后，将进程的执行状态陷入至EL1特权级执行目标操作。Master逻辑核在执行完成该目标操作之后，返回至该访问page1的指令(即页面访问指令)处，进而返回至指令1。进一步的，Master逻辑核调用slave.call指令，触发Slave逻辑核运行，Slave逻辑核从被打断位置slave.pc处继续执行。
Slave逻辑核运行进程并确定进程收到中断，Slave逻辑核的硬件单元将进程的执行状态由Slave逻辑核的用户态，直接陷入至Master逻辑核的特权态(比如EL1特权级)。Master逻辑核运行该进程，以使得进程执行目标操作。在进程执行完成该目标操作之后，返回至master.pc位置的指令(即master.pc指令)，进而返回至指令1。进一步的，Master逻辑核调用slave.call指令，触发Slave逻辑核运行，Slave逻辑核从被打断位置slave.pc处继续执行。
Slave逻辑核运行进程并确定进程触发RAS异常，Slave逻辑核的硬件单元将进程的执行状态由Slave逻辑核的用户态，直接陷入至Master逻辑核的特权态(比如EL3特权级)。Master逻辑核运行该进程，以使得进程执行目标操作。在进程执行完成该目标操作之后，返回至master.pc位置的指令(即master.pc指令)，进而返回至指令1。Master逻辑核调用slave.call指令，触发Slave逻辑核运行，Slave逻辑核从被打断位置slave.pc处继续执行。
上述技术方案中，Master逻辑核和Slave逻辑核二者通过配置空间进行信息交互，实现Master逻辑核和Slave逻辑核的解耦合，从而Master逻辑核和Slave逻辑核二者可以独立发展，也即，在不破坏Master逻辑核对应的架构语义/指令空间的前提下，可实现Slave逻辑核对应指令集的独立演进。如此，Slave逻辑核可运行加速引擎及算法，比如mySql 进程、图计算进程或加解密算子中的一项或多项，相比于Master逻辑核可提高运算速率。
进一步的，当运行在Slave逻辑核的进程需要执行目标操作时，Slave逻辑核可将进程的运行上下文写入至配置空间，该运行上下文中包括Slave逻辑核暂停运行进程对应的暂停位置。相应的，Master逻辑核执行完成该进程的目标操作之后，可继续启动Slave逻辑核运行该进程，随后，Slave逻辑核可从配置空间中读取该暂停位置，继续在该暂停位置处继续执行该进程。如此，可实现进程在Master逻辑核和Slave逻辑核之间切换运行状态。
需要补充的是，在本申请中，逻辑核、进程和目标操作之间的关系可以理解为，进程运行于逻辑核(Slave逻辑核或Master逻辑核)中，进程执行目标操作也即其运行时所在的逻辑核(比如Master逻辑核)执行目标操作。
基于上述内容和相同构思，本申请提供一种计算机程序产品，计算机程序产品包括计算机程序或指令，当计算机程序或指令被装置执行时，实现上述方法实施例中的方法。
基于上述内容和相同构思，本申请提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序或指令，当计算机程序或指令被计算设备执行时，实现上述方法实施例中的方法。
基于上述内容和相同构思，本申请提供一种计算设备，包括处理器，处理器与存储器相连，存储器用于存储计算机程序，处理器用于执行存储器中存储的计算机程序，以使得计算设备实现上述方法实施例中的方法。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (21)

  1. 一种进程的执行状态切换方法，其特征在于，应用于中央处理器CPU，所述CPU包括物理核，所述物理核包括主逻辑核和从逻辑核，所述方法包括：
    如果运行在所述从逻辑核的进程满足第一条件，在所述从逻辑核中暂停运行所述进程，并记录所述进程的暂停位置，所述暂停位置用于下次在所述从逻辑核中运行所述进程时确定执行位置，其中，所述第一条件用于指示所述进程待执行目标操作，且所述目标操作在所述进程的执行状态处于所述主逻辑核的特权态时能够被执行；
    将所述进程的执行状态由所述从逻辑核的用户态切换为所述主逻辑核的特权态；
    在所述主逻辑核中运行所述进程，以供所述进程执行所述目标操作。
  2. 如权利要求1所述的方法，其特征在于，所述记录所述进程的暂停位置，包括：
    通过所述从逻辑核将所述暂停位置的信息写入配置空间，所述配置空间用于所述主逻辑核与所述从逻辑核进行信息交互。
  3. 如权利要求2所述的方法，其特征在于，所述方法还包括：
    将所述进程的执行状态由所述主逻辑核的特权态切换为所述从逻辑核的用户态；
    通过所述从逻辑核从所述配置空间读取所述暂停位置的信息；
    在所述从逻辑核中，从所述暂停位置开始继续运行所述进程。
  4. 如权利要求1至3任一项所述的方法，其特征在于，所述第一条件包括所述进程触发第一类异常，所述第一类异常包括除可靠性异常、可用性异常、以及可服务性RAS异常以外的其它异常；
    所述将所述进程的执行状态由所述从逻辑核的用户态切换为所述主逻辑核的特权态，包括：
    触发所述主逻辑核运行所述进程，以将所述进程的执行状态由所述从逻辑核的用户态切换为所述主逻辑核的用户态；
    从所述主逻辑核的特权态的多个特权级中确定所述第一类异常对应的目标特权级；
    将所述进程的执行状态由所述主逻辑核的用户态切换为所述主逻辑核的特权态的所述目标特权级。
  5. 如权利要求4所述的方法，其特征在于，所述将所述进程的执行状态由所述主逻辑核的用户态切换为所述主逻辑核的特权态的所述目标特权级之前，还包括：
    获取所述目标特权级对应的虚拟内存地址；
    确定所述虚拟内存地址未与物理内存地址建立映射关系。
  6. 如权利要求1至3任一项所述的方法，其特征在于，所述第一条件包括所述进程收到中断，或者所述进程触发RAS异常。
  7. 如权利要求1至6任一项所述的方法，其特征在于，所述方法还包括：
    在所述主逻辑核中启动所述进程；
    如果所述进程的指令集属于所述从逻辑核运行的指令集，记录所述进程的起始位置，并触发所述从逻辑核进入运行状态；
    在所述从逻辑核中，从所述起始位置开始运行所述进程。
  8. 如权利要求1至7任一项所述的方法，其特征在于，所述方法还包括：
    释放所述主逻辑核在运行所述进程时所占用的所述物理核的硬件资源；
    其中，所述硬件资源包括内存资源和/或输入输出资源。
  9. 如权利要求1至8中任一项所述的方法，其特征在于，所述方法还包括：
    通过所述从逻辑核记录如下信息中的一项或多项：
    在所述从逻辑核上暂停运行所述进程的原因，所述目标操作对应的执行参数，暂停运行所述进程时的环境信息，或，特权级信息；其中，所述特权级信息用于指示所述进程在执行所述目标操作时所述主逻辑核的特权态的特权级。
  10. 一种执行状态的切换装置，其特征在于，包括处理器和存储器；
    所述存储器用于存储计算机程序；
    所述处理器用于调用所述存储器所存储的计算机程序，以执行如下步骤：
    如果运行在所述从逻辑核的进程满足第一条件，在所述从逻辑核中暂停运行所述进程，并记录所述进程的暂停位置，所述暂停位置用于下次在所述从逻辑核中运行所述进程时确定执行位置，其中，所述第一条件用于指示所述进程待执行目标操作，且所述目标操作在所述进程的执行状态处于所述主逻辑核的特权态时能够被执行；
    将所述进程的执行状态由所述从逻辑核的用户态切换为所述主逻辑核的特权态；
    在所述主逻辑核中运行所述进程，以供所述进程执行所述目标操作。
  11. 如权利要求10所述的装置，其特征在于，所述处理器在记录所述进程的暂停位置时，具体用于：通过所述从逻辑核将所述暂停位置的信息写入配置空间，所述配置空间用于所述主逻辑核与所述从逻辑核进行信息交互。
  12. 如权利要求11所述的装置，其特征在于，所述处理器还用于：
    将所述进程的执行状态由所述主逻辑核的特权态切换为所述从逻辑核的用户态；
    通过所述从逻辑核从所述配置空间读取所述暂停位置的信息；
    在所述从逻辑核中，从所述暂停位置开始继续运行所述进程。
  13. 如权利要求10至12任一项所述的装置，其特征在于，所述第一条件包括所述进程触发第一类异常，所述第一类异常包括除可靠性异常、可用性异常、以及可服务性RAS异常以外的其它异常；
    所述处理器在将所述进程的执行状态由所述从逻辑核的用户态切换为所述主逻辑核的特权态时，具体用于：
    触发所述主逻辑核运行所述进程，以将所述进程的执行状态由所述从逻辑核的用户态切换为所述主逻辑核的用户态；
    从所述主逻辑核的特权态的多个特权级中确定所述第一类异常对应的目标特权级；
    将所述进程的执行状态由所述主逻辑核的用户态切换为所述主逻辑核的特权态的所述目标特权级。
  14. 如权利要求13所述的装置，其特征在于，所述处理器在将所述进程的执行状态由所述主逻辑核的用户态切换为所述主逻辑核的特权态的所述目标特权级之前，还用于：
    获取所述目标特权级对应的虚拟内存地址；
    确定所述虚拟内存地址未与物理内存地址建立映射关系。
  15. 如权利要求10至12任一项所述的装置，其特征在于，所述第一条件包括所述进程收到中断，或者所述进程触发RAS异常。
  16. 如权利要求10至15任一项所述的装置，其特征在于，所述处理器还用于：
    在所述主逻辑核中启动所述进程；
    如果所述进程的指令集属于所述从逻辑核运行的指令集，记录所述进程的起始位置，并触发所述从逻辑核进入运行状态；
    在所述从逻辑核中，从所述起始位置开始运行所述进程。
  17. 如权利要求10至16任一项所述的装置，其特征在于，所述处理器还用于：
    释放所述主逻辑核在运行所述进程时所占用的所述物理核的硬件资源；
    其中，所述硬件资源包括内存资源和/或输入输出资源。
  18. 如权利要求10至17中任一项所述的装置，其特征在于，所述处理器还用于：
    通过所述从逻辑核记录如下信息中的一项或多项：
    在所述从逻辑核上暂停运行所述进程的原因，所述目标操作对应的执行参数，暂停运行所述进程时的环境信息，或，特权级信息；其中，所述特权级信息用于指示所述进程在执行所述目标操作时所述主逻辑核的特权态的特权级。
  19. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序或指令，当所述计算机程序或指令被装置执行时，实现如权利要求1至9中任一项所述的方法。
  20. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序或指令，当所述计算机程序或指令被计算设备执行时，实现如权利要求1至9中任一项所述的方法。
  21. 一种计算设备，其特征在于，包括处理器，所述处理器与存储器相连，所述存储器用于存储计算机程序，所述处理器用于执行所述存储器中存储的计算机程序，以使得所述计算设备执行如权利要求1至9中任一项所述的方法。
PCT/CN2023/079222 2022-03-11 2023-03-02 一种进程的执行状态切换方法及装置 WO2023169289A1 (zh)

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