WO2023159557A1 - 显示面板的驱动方法、驱动电路、显示装置 - Google Patents

显示面板的驱动方法、驱动电路、显示装置 Download PDF

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Publication number
WO2023159557A1
WO2023159557A1 PCT/CN2022/078252 CN2022078252W WO2023159557A1 WO 2023159557 A1 WO2023159557 A1 WO 2023159557A1 CN 2022078252 W CN2022078252 W CN 2022078252W WO 2023159557 A1 WO2023159557 A1 WO 2023159557A1
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Prior art keywords
row
sub
pixels
compensation gain
signal
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PCT/CN2022/078252
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English (en)
French (fr)
Inventor
孙建伟
周留刚
刘娇
刘建涛
汪俊
梁云云
李清
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/078252 priority Critical patent/WO2023159557A1/zh
Priority to CN202280000340.7A priority patent/CN117321669A/zh
Priority to US18/016,414 priority patent/US20240249659A1/en
Publication of WO2023159557A1 publication Critical patent/WO2023159557A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving method, a driving circuit and a display device of a display panel.
  • the timing controller (Timing Controller, TCON) provides a clock signal to the gate drive circuit, and then multiple shift register units of the gate drive circuit sequentially output scan signals to multiple gate lines.
  • TCON Timing Controller
  • the pulse widths of the clock signals received by multiple shift register units are likely to be different, resulting in differences in the charging time of pixels in different rows, and resulting in horizontal stripes on the display screen.
  • the present disclosure provides a driving method, a driving circuit and a display device of a display panel.
  • the present disclosure provides a method for driving a display panel, the display panel includes multiple rows of sub-pixels, the driving method includes a display process, and the display process:
  • the initial driving signal of each row of sub-pixels is adjusted to obtain a target driving signal; wherein, the compensation gain of each row of sub-pixels is: When the display panel displays a test grayscale image, the actual luminance coefficient of the row of sub-pixels relative to the reference row of sub-pixels;
  • the sub-pixels of each row are driven to display according to the target driving signal of the sub-pixels of each row, so that the sub-pixels of each row can reach a target brightness.
  • the initial drive signal includes an initial clock signal
  • the initial driving signal of each row of sub-pixels is adjusted, specifically including:
  • each row of subpixels adjust the falling edge time of the initial clock signal of each row of subpixels to adjust the gate output enable time of each row of subpixels, wherein the adjusted gate output of each row of subpixels
  • the enabling time is positively correlated with the compensation gain corresponding to the sub-pixel.
  • the initial drive signal includes an initial data output enable signal; according to the compensation gain of each row of sub-pixels stored in the preset compensation gain table, the initial drive signal for each row of the sub-pixels Make adjustments, including:
  • each row of subpixels adjust the falling edge time of the initial data output enable signal of each row of subpixels to adjust the effective charging time of each row of subpixels, wherein the adjusted effective charging time of each row of subpixels It is positively correlated with the compensation gain corresponding to the sub-pixel.
  • the initial driving signal includes an initial data signal; the initial driving signal of each row of subpixels is adjusted according to the compensation gain of each row of subpixels stored in a preset compensation gain table, Specifically include:
  • the magnitude of the initial data signal of each row of subpixels is adjusted according to the compensation gain of each row of subpixels, wherein the adjusted magnitude of the initial data signal is positively correlated with the corresponding compensation gain of the subpixel.
  • the driving method further includes a test process performed before the display process, the test process comprising:
  • the compensation gain table is stored.
  • the reference sub-pixel row is the sub-pixel row with the lowest brightness when the display panel displays the image of the test gray scale.
  • the test grayscale is greater than 200.
  • an embodiment of the present disclosure further provides a driving circuit for a display panel, where the display panel includes multiple rows of sub-pixels, and the driving circuit includes:
  • an initial signal generating module configured to generate an initial driving signal for each row of sub-pixels according to the image information to be displayed
  • the compensation module is configured to adjust the initial driving signal of each row of sub-pixels according to the compensation gain of each row of sub-pixels stored in the preset compensation gain table to obtain a target driving signal; wherein, each row of sub-pixels
  • the compensation gain of the pixel is: when the display panel displays a test grayscale image, the actual luminance coefficient of the sub-pixels in this row relative to the sub-pixels in the reference row;
  • the driving module is configured to drive the sub-pixels in the corresponding row to display according to the target driving signal of the sub-pixels in each row, so that the sub-pixels in each row can reach the target brightness.
  • the initial driving signal includes an initial clock signal;
  • the compensation module is specifically configured to adjust the falling edge time of the initial clock signal of each row of subpixels according to the compensation gain of each row of subpixels to adjust The gate output enabling time of each row of sub-pixels, wherein the adjusted gate output enabling time of each row of sub-pixels is positively correlated with the compensation gain corresponding to the sub-pixels.
  • the initial driving signal includes an initial data output enable signal; the compensation module is specifically configured to adjust the initial data output enable signal of each row of subpixels according to the compensation gain of each row of subpixels
  • the falling edge time is used to adjust the effective charging time of each row of sub-pixels, wherein the adjusted effective charging time of each row of sub-pixels is positively correlated with the compensation gain corresponding to the sub-pixels.
  • the initial driving signal includes an initial data signal; the compensation module is specifically configured to,
  • the magnitude of the initial data signal of each row of subpixels is adjusted according to the compensation gain of each row of subpixels, wherein the adjusted magnitude of the initial data signal is positively correlated with the corresponding compensation gain of the subpixel.
  • the compensation gain table is generated according to the following steps:
  • the compensation gain of each row of sub-pixels is determined, and the compensation gain table is generated.
  • the driving circuit further includes a storage module configured to store the compensation gain table.
  • the reference sub-pixel row is the sub-pixel row with the lowest brightness when the display panel displays the image of the test gray scale.
  • the test grayscale is greater than 200.
  • an embodiment of the present disclosure further provides a display device, including a display panel and the above-mentioned driving circuit.
  • FIG. 1 is a schematic diagram of a connection between a timing controller and a clock signal line provided in an example.
  • FIG. 2 is a schematic diagram of a driving method of a display panel provided in some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of a testing process provided in some embodiments of the present disclosure.
  • Fig. 4 is a schematic diagram of an adjustment process of an initial clock signal provided in some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a source driver chip provided in some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of adjusting initial driving signals of sub-pixels in each row provided in some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of a driving circuit of a display panel provided in some embodiments of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, the source , Drain is no difference. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of them is called the first pole, the other is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of transistors, transistors can be divided into N-type and P-type. In the following embodiments, N-type transistors are used for illustration. The drain of the N-type transistor, when the gate is input with a high level, the source and drain are turned on, and the P-type is opposite.
  • the working level signal (working level state) in the disclosed embodiment refers to a high level signal (high level state)
  • the non-working level signal is a low-level signal (low-level state);
  • the corresponding working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.
  • a display panel includes a plurality of gate lines and a plurality of data lines, and the intersecting arrangement of the gate lines and the data lines defines a plurality of pixel areas, and each pixel area is provided with a thin film transistor.
  • the structure of the display panel is described by taking the extending direction of each gate line as the row direction and the extending direction of each data line as the column direction as an example.
  • the scan signal is provided by the gate drive circuit
  • the source voltage signal is provided by the source drive circuit
  • the source voltage signal is processed by a series of processes such as digital-to-analog conversion and level conversion on the data signal provided by the timing controller.
  • the timing of the source drive circuit outputting the source voltage signal is related to the data enable (Source Output Enable, SOE) signal output by the timing controller, wherein the starting moment of the source voltage signal is related to the falling edge time of the SOE signal same.
  • SOE Data enable
  • the gate drive circuit can be integrated in the gate drive chip, and the source drive circuit can be integrated in the source drive chip; but currently, in order to reduce the number of chips and realize narrow or no frame, a A technology that integrates the gate drive circuit on the array substrate (Gate On Array; GOA); wherein, the gate drive circuit includes a plurality of cascaded shift register units integrated on the array substrate, and the shift register unit and the gate The lines are connected in one-to-one correspondence, and are used to provide scanning signals for the gate lines connected thereto.
  • GOA Gate On Array
  • the timing controller When driving the display panel for display, the timing controller provides clock signals to multiple shift register units through the clock signal line, wherein, at the output stage of each shift register unit, the clock signal it receives is in a high level state .
  • the clock signal line due to the large resistance R of each clock signal line, and a certain capacitance C (nF level) will be formed between each clock signal line and its adjacent metal, dielectric and other structures; the existence of R and C will cause signal
  • the attenuation, delay, and deformation of different clock signal lines may cause differences in the pulse width of the clock signal transmitted, which may lead to differences in the pulse width of the clock signal received by the shift register unit connected to different clock signal lines , which in turn leads to different charging times between pixels in different rows, resulting in poor horizontal stripes.
  • the clock signal is not an ideal square wave signal, but has a certain rise time and fall time, which will lead to insufficient charging time for pixels.
  • the resistor R0 and the inductor L are connected in series between the timing controller 1 and the clock signal lines (CK1 ⁇ CK2) through the Resistance Inductor Tuning (RLT) technology (as shown in Figure 1), Energy is stored in the inductor L to generate an instantaneous reverse electromotive force, thereby reducing the falling time of the clock signal.
  • RLT Resistance Inductor Tuning
  • the embodiments of the present disclosure provide a driving method, a driving circuit, and a display device of the display panel. The following will describe the driving method, the driving circuit, and the display device of the display panel provided by the present disclosure in conjunction with the accompanying drawings. described in further detail.
  • each sub-pixel is provided with a thin film transistor, the gate of the thin film transistor is connected to a corresponding gate line, and the source of the thin film transistor is connected to a corresponding data line.
  • the driving method of the display panel includes a display process, and the display process includes:
  • the initial driving signal may be generated by a timing controller
  • the initial driving signal of each row of sub-pixels refers to the initial driving signal of each sub-pixel in each row
  • the initial driving signal may include an initial clock signal, an initial data signal and an SOE signal .
  • the initial clock signal of each sub-pixel in the same row is the same
  • the initial data signal can be a digital signal
  • the size of the initial data signal of each sub-pixel is related to the gray scale to be displayed by the sub-pixel, therefore, the same row
  • the voltages of the initial data signals of different sub-pixels may be different.
  • the timing controller can generate the initial driving signal according to the preset timing and the original grayscale of the image to be displayed.
  • the initial clock signals corresponding to subpixels in different rows have the same pulse width, and the SOE signals of different subpixels in the same column have the same pulse width.
  • the size of the initial data signal of each sub-pixel is determined according to the original gray scale of the image to be displayed.
  • the timing controller can generate the original clock signal and the original data signal of each row of sub-pixels according to the preset timing and the original gray scale of the image to be displayed, and then determine the image to be displayed according to the mura compensation table the middle gray scale of the image to be displayed, and determine the initial driving signal of each sub-pixel according to the middle gray scale of the image to be displayed.
  • the original gray scale of the image to be displayed is the gray scale before compensation using the brightness deviation elimination technology (De-Mura), and the intermediate gray scale is compensated for the display brightness of the image to be displayed using the De-Mura compensation technology, so that it can reach The gray scale corresponding to the target brightness.
  • De-Mura brightness deviation elimination technology
  • the initial clock signals corresponding to subpixels in different rows have the same pulse width, and the SOE signals of different subpixels in the same column have the same pulse width.
  • the size of the initial data signal of each sub-pixel is determined according to the middle gray scale of the image to be displayed.
  • the initial driving signal of each row of sub-pixels is adjusted to obtain a target driving signal.
  • the compensation gain of each row of sub-pixels is: the actual luminance gain of the row of sub-pixels relative to the reference row of sub-pixels when the display panel displays a test grayscale image.
  • the compensation gain table is obtained in the test stage before the display stage, and can be stored in the storage module in the timing controller.
  • the reference row of sub-pixels may be one row of sub-pixels in the display panel.
  • the target driving signal may include a target clock signal, a target data signal, and a target SOE signal.
  • the aforementioned compensation gain is used to adjust the initial driving signal.
  • the initial clock signal may be adjusted by using the compensation gain to obtain the target clock signal in the target driving signal. signal; it can also be: using the compensation gain to adjust the initial data signal to obtain the target data signal in the target drive signal; it can also be to use the compensation gain to adjust the initial SOE signal to obtain the target SOE signal in the target drive signal.
  • the preset compensation gain table includes the compensation gain of each row of sub-pixels, and the compensation gain of each row of sub-pixels is the ratio of the row of sub-pixels relative to the reference row when the display panel displays a test grayscale image.
  • FIG. 3 is a schematic diagram of the test process provided in some embodiments of the present disclosure. As shown in FIG. 3 , the test process includes S01 ⁇ S05 :
  • the test gray scale is greater than 200, and optionally, the test gray scale is between 220 ⁇ 255, for example, the test gray scale is 223, 230, 233, 240, 250 or 255.
  • the test grayscale image displayed by the driving display panel is an image after the brightness has been compensated by the De-mura technology, so mura defects will not appear in the display screen.
  • the De-mura technology cannot improve the horizontal streaks in the high grayscale image, that is, in step S01, the image displayed on the display panel may be different due to the difference of the clock signal on the clock signal line mentioned above, Defective stripes occur.
  • S03. Determine the actual brightness of each row of sub-pixels in the display panel according to the collected images.
  • the reference row of sub-pixels is a row of sub-pixels with the lowest brightness in the display panel.
  • Table 1 is the actual luminance table of each row of sub-pixels provided in some embodiments of the present disclosure
  • Table 2 is the compensation gain table provided in the embodiments of the present disclosure, as shown in Table 1 and Table 2, row 3, row 9
  • the brightness of the row is the lowest, and one row is used as the reference row of sub-pixels
  • the actual brightness of the i-th row of sub-pixels is denoted as Li
  • the brightness of the reference row of sub-pixels is denoted as L0
  • the timing controller provides clock signals for the multi-stage shift register units through six clock signal lines as an example for illustration.
  • the shift register unit of the (1+6n) stage is connected to the first clock signal line
  • the shift register unit of the (2+6n) stage is connected to the second clock signal line
  • the shift register unit of the (3+6n) stage The register unit is connected to the third clock signal line
  • the (4+6n) shift register unit is connected to the fourth clock signal line
  • the (5+6n) shift register unit is connected to the fifth clock signal line
  • the (5+6n) shift register unit is connected to the fifth clock signal line.
  • the 6+6n stage shift register unit is connected to the sixth clock signal line, n is an integer, and n ⁇ 0.
  • the initial clock signal of each row of sub-pixels corresponding to the shift register unit connected to the same clock signal line is the same, and the target clock signal of each row of sub-pixels corresponding to the shift register unit connected to the same clock signal line is also the same , and the target clock signal is provided to the clock signal line by the timing controller.
  • the initial clock signal may be adjusted.
  • the above step S2 may specifically include: adjusting the falling edge time of the initial clock signal of each row of subpixels according to the compensation gain of each row of subpixels, so as to adjust the gate output enable time (GOE) of each row of subpixels, wherein, in Before the initial clock signal is adjusted, the GOE time of each row of sub-pixels may be the same.
  • the adjusted gate output enabling time of each row of sub-pixels is positively correlated with the compensation gain corresponding to the sub-pixels.
  • the gate output enable signal (GOE) of each row of subpixels refers to the interval between the falling edge of the clock signal of each row of subpixels and the start moment of the source voltage signal of the next row of subpixels.
  • Interval time that is, the interval time between the falling edge of the clock signal of each row of sub-pixels and the falling edge of the SOE signal of the next row of sub-pixels.
  • j is a positive integer, and j is not greater than the total number of rows of sub-pixels.
  • the purpose of setting the GOE time is to prevent wrong charging. Specifically, after the scanning phase of each row of sub-pixels ends, the thin film transistors in the sub-pixels of this row will not be turned off instantly.
  • the scanning stage of a row of sub-pixels refers to the output stage of the shift register unit corresponding to the row of sub-pixels.
  • FIG. 4 is a schematic diagram of the adjustment process of the initial clock signal provided in some embodiments of the present disclosure.
  • CLK1 to CLK6 are initial clock signals of the sub-pixels in the first row to the sixth row respectively
  • CLK1' to CLK6' are target clock signals of the sub-pixels in the first row to the sixth row respectively
  • Source2 to Source7 are the source voltage signals of the sub-pixels in the second row to the seventh row respectively.
  • T1 to T6 are the GOE times before the adjustment of the sub-pixels in the first row to the sixth row respectively, and T1' to T6' are the adjusted GOE times of the sub-pixels in the first row to the sixth row respectively.
  • the source voltage signals of the sub-pixels in each row do not change.
  • the initial clock signal and the target clock signal of each row of sub-pixels are clock signals switched between high-level state and low-level state.
  • FIG. 4 the initial clock signal/target clock signal of each row of sub-pixels When illustrating the source voltage signal, only one of the high-level states is shown.
  • the pulse width of CLK3 can be increased, that is, the falling edge of CLK3 is moved backward relative to CLK1, Therefore, the GOE time of the sub-pixels in the third row is reduced (from T3 to T3'), which is beneficial to increase the charging time of the sub-pixels in the third row, thereby improving the brightness of the sub-pixels in the third row.
  • Ti' is the adjusted GOE time of the i-th row of sub-pixels
  • T0 is the reference row
  • the adjusted GOE time of the pixel, in FIG. 4, T3' is T0;
  • A is a proportional coefficient related to the charging rate of the display panel, and the charging rate is equal to the ratio of the actual brightness to the theoretical brightness of the display panel.
  • the initial clock signal in the initial driving signal may be adjusted, and the initial data signal may not be adjusted.
  • the adjusted initial clock signal is the target clock signal
  • the target data signal is the same as the initial data signal
  • the target SOE signal is the same as the initial SOE signal.
  • the initial SOE signal may be specifically adjusted.
  • the above step S2 may specifically include: adjusting the falling edge time of the initial SOE signal of each row of subpixels according to the compensation gain of each row of subpixels, so as to adjust the start time of the source driver chip outputting the source voltage signal, thereby adjusting the The effective charging time of the sub-pixels, wherein the adjusted effective charging time of each row of sub-pixels is positively correlated with the compensation gain corresponding to the sub-pixels.
  • FIG. 5 is a schematic structural diagram of the source driver chip provided in some embodiments of the present disclosure.
  • the source driver chip includes : a first buffer unit Latch1, a gate switch K1, a second buffer unit Latch2, a level shifter LS, a digital-to-analog converter DAC, a polarity control unit 21 , an amplifier OP, and an output control unit 22 .
  • the target data signal output by the timing controller is first stored in the first cache unit Latch1, and when the gate switch K1 is turned on in response to the gate signal, the target data signal is transmitted to the second cache unit Latch2, and then the target data
  • the signal is level-converted by the level converter LS, and then digital-to-analog converted by the digital-to-analog converter DAC to generate an analog signal.
  • the polarity control unit 22 controls the polarity of the analog signal, so as to control the polarity of the analog signal as required.
  • the Nth output terminal of the source driver chip needs to output a positive polarity voltage signal
  • the N+1th output terminal needs to output a voltage signal of negative polarity
  • the polarity control unit 21 makes the polarity of the analog signal output by the analog-to-digital converter DAC corresponding to the Nth output terminal through the control of multiple switches inside it.
  • the polarity is positive, and it is transmitted to the corresponding amplifier OP
  • the polarity of the analog signal output by the analog-to-digital converter DAC corresponding to the N+1th output terminal is negative, and it is transmitted to the corresponding amplifier OP.
  • the output control unit 22 transmits the voltage signal output by each amplifier OP to the corresponding output terminal of the source driving circuit in response to the falling edge of the SOE signal.
  • the effective charging time of each row of sub-pixels is the overlapping time of the high-level phase of the clock signal of the row of sub-pixels and the effective phase of the source voltage signal.
  • the "valid phase" of the source voltage signal does not include the transition phase between the invalid phase and the valid phase.
  • the effective charging time of each row of sub-pixels before adjustment is the overlapping time between the high-level phase of the initial clock signal and the effective phase of the source voltage signal before adjustment; the effective charging time after adjustment is , the overlap time between the high level phase of the target clock signal and the valid phase of the adjusted source voltage signal. Since the source voltage signal is output by the source driver chip in response to the falling edge of the SOE signal, the effective charging time of the sub-pixel can be adjusted by adjusting the time of the falling edge of the SOE signal.
  • FIG. 6 is a schematic diagram of the adjustment of the initial driving signals of each row of sub-pixels provided in some embodiments of the present disclosure.
  • the initial clock signals of the three rows of sub-pixels, CLK1 ′ ⁇ CLK3 ′ are respectively target clock signals of the first three rows, wherein the target clock signals of each row of sub-pixels may be the same as the initial clock signals.
  • SOE1-SOE3 are the initial SOE signals of the sub-pixels in the first three rows respectively
  • SOE1'-SOE3' are the target SOE signals of the sub-pixels in the first three rows respectively.
  • Source1-Source3 are respectively unadjusted source voltage signals of the sub-pixels in the first row to the third row, and Source1'-Source3' are respectively adjusted source voltage signals of the sub-pixels in the first row to the third row.
  • the effective charging time before adjustment of each row of sub-pixels may be equal.
  • the falling edge of SOE3 can be moved forward, so that the falling edge of SOE3' is ahead of SOE1' and SOE2' , so as to increase the effective charging time of the sub-pixels in the third row, thereby increasing the brightness of the sub-pixels in the third row.
  • its rising edge may not be adjusted.
  • the size of the initial data signal can be adjusted. Specifically, the size of the initial data signal of each row of sub-pixels may be adjusted according to the compensation gain of each row of sub-pixels, wherein the adjusted size of the initial data signal is positively correlated with the corresponding compensation gain of the sub-pixel.
  • the adjusted initial data signal is the target data signal in the target driving signal, and the target clock signal and the target SOE signal may be the same as the initial clock signal and the initial SOE signal respectively.
  • the size of the target data signal may be determined according to a preset correspondence table.
  • FIG. 7 is a schematic diagram of a driving circuit of a display panel provided in some embodiments of the present disclosure. As shown in FIG. 7 , the driving circuit includes: an initial signal generation module 10 , a compensation module 20 , and a driving module 30 .
  • the initial signal generating module 10 is configured to generate an initial driving signal for each row of sub-pixels according to image information of an image to be displayed.
  • the initial driving signal may specifically include an initial clock signal, an initial data signal, and an initial SOE signal.
  • the compensation module 20 is configured to, according to the compensation gain of each row of sub-pixels stored in the preset compensation gain table, adjust the initial driving signal of each row of sub-pixels to obtain a target driving signal; wherein, the compensation of each row of sub-pixels
  • the gain is: the actual luminance coefficient of the sub-pixels in this row relative to the sub-pixels in the reference row when the display panel displays a test grayscale image.
  • the driving module 30 is configured to drive the sub-pixels of the corresponding row to display according to the target driving signal of the sub-pixels of each row, so that the sub-pixels of each row can reach the target brightness.
  • the initial signal generation module 10 and the compensation module 20 may be integrated in the timing controller, and the driving module 30 may include a gate driving circuit and a source driving circuit.
  • the compensation module 20 is specifically configured to adjust the falling edge time of the initial clock signal of each row of subpixels according to the compensation gain of each row of subpixels, so as to adjust the gate output of each row of subpixels so that Enable time, wherein the adjusted gate output enable time of each row of sub-pixels is positively correlated with the compensation gain corresponding to the sub-pixels.
  • the compensation module 20 is specifically configured to adjust the falling edge time of the initial SOE signal of each row of subpixels according to the compensation gain of each row of subpixels, so as to adjust the effective charging time of each row of subpixels, wherein , the adjusted effective charging time of each row of sub-pixels is positively correlated with the compensation gain corresponding to the sub-pixels.
  • the compensation module 20 is specifically configured to adjust the size of the initial data signal of each row of sub-pixels according to the compensation gain of each row of sub-pixels, wherein the adjusted size of the initial data signal is the same as the The compensation gain corresponding to the sub-pixel is positively correlated.
  • the compensation gain table is generated according to the following steps: driving the display panel to display a test grayscale image; performing image acquisition on the picture displayed on the display panel; Actual luminance of sub-pixels in each row; determining the compensation gain of sub-pixels in each row according to the actual luminance of sub-pixels in each row and the actual luminance of sub-pixels in a reference row, and generating the compensation gain table.
  • the reference sub-pixel row is a sub-pixel row with the lowest brightness when the display panel displays the image of the test gray scale.
  • the test grayscale is greater than 200.
  • the driving circuit further includes a storage module configured to store the compensation gain table.
  • the compensation gain table can be generated in the test process before the display process, and when the image is displayed during the display process, the timing controller can call the compensation gain table stored in the storage module to adjust the initial driving signal, so as to generate the target driving signal.
  • the timing controller can call the compensation gain table stored in the storage module to adjust the initial driving signal, so as to generate the target driving signal.
  • Embodiments of the present disclosure also provide a display device, including a display panel and the driving circuit in the above embodiments.
  • the display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

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Abstract

一种显示面板的驱动方法、驱动电路和显示装置。显示面板包括多行子像素，驱动方法包括显示过程，显示过程包括：根据待显示图像的图像信息生成每行子像素的初始驱动信号（S1）；根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行子像素的初始驱动信号进行调节，得到目标驱动信号（S2）；其中，每行子像素的补偿增益为：显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度系数；根据每行子像素的目标驱动信号驱动相应行的子像素进行显示，以使每行子像素达到目标亮度（S3）。

Description

显示面板的驱动方法、驱动电路、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板的驱动方法、驱动电路和显示装置。
背景技术
随着显示行业的不断发展，液晶显示产品以其低成本、窄边框、轻薄化等优势受到了更多的关注，在此背景下阵列基板栅极驱动技术(Gate Driver on Array，GOA)应运而生。
在大尺寸显示产品中，时序控制器(Timing Controller，TCON)向栅极驱动电路提供时钟信号，进而使栅极驱动电路的多个移位寄存器单元向多条栅线依次输出扫描信号。但实际应用过程中，多个移位寄存器单元接收到的时钟信号的脉宽容易产生差异，从而导致不同行像素的充电时间出现差异，进而导致显示画面出现横纹。
发明内容
本公开提供一种显示面板的驱动方法、驱动电路和显示装置。
第一方面，本公开提供一种显示面板的驱动方法，所述显示面板包括多行子像素，所述驱动方法包括显示过程，所述显示过程：
根据待显示图像的图像信息生成每行所述子像素的初始驱动信号；
根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，得到目标驱动信号；其中，每行子像素的补偿增益为：所述显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度系数；
根据每行所述子像素的所述目标驱动信号驱动相应行的子像素进行显示，以使每行所述子像素达到目标亮度。
在一些实施例中，所述初始驱动信号包括初始时钟信号，
根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，具体包括：
根据每行子像素的补偿增益，调节每行子像素的初始时钟信号的下降沿时间，以调整每行子像素的栅极输出使能时间，其中，每行子像素的调整后的栅极输出使能时间与所述子像素对应的补偿增益正相关。
在一些实施例中，所述初始驱动信号包括初始数据输出使能信号；根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，具体包括：
根据每行子像素的补偿增益，调节每行子像素的初始数据输出使能信号的下降沿时间，以调整每行子像素的有效充电时间，其中，每行子像素的调整后的有效充电时间与所述子像素对应的补偿增益正相关。
在一些实施例中，所述初始驱动信号包括初始数据信号；根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，具体包括：
根据每行子像素的补偿增益，调节每行子像素的初始数据信号的大小，其中，所述初始数据信号调节后的大小与所述子像素对应的补偿增益正相关。
在一些实施例中，所述驱动方法还包括在所述显示过程之前进行的测试过程，所述测试过程包括：
驱动所述显示面板显示测试灰阶的图像；
对所述显示面板所显示画面进行图像采集；
根据采集到的图像，确定所述显示面板中每行子像素的实际亮度；
根据每行子像素的实际亮度和基准行子像素的实际亮度，确定每行子像素的补偿增益，并生成所述补偿增益表；
对所述补偿增益表进行存储。
在一些实施例中，所述基准子像素行为所述显示面板在显示所述测试灰阶的图像时，亮度最低的子像素行。
在一些实施例中，所述测试灰阶大于200。
第二方面，本公开实施例还提供一种显示面板的驱动电路，所述显示面板包括多行子像素，所述驱动电路包括：
初始信号生成模块，被配置为根据待显示的图像信息生成每行所述子像素的初始驱动信号；
补偿模块，被配置为根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，得到目标驱动信号；其中，每行子像素的补偿增益为：所述显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度系数；
驱动模块，被配置为根据每行所述子像素的所述目标驱动信号驱动相应行的子像素进行显示，以使每行所述子像素达到目标亮度。
在一些实施例中，所述初始驱动信号包括初始时钟信号；所述补偿模块具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始时钟信号的下降沿时间，以调整每行子像素的栅极输出使能时间，其中，每行子像素的调整后的栅极输出使能时间与所述子像素对应的补偿增益正相关。
在一些实施例中，所述初始驱动信号包括初始数据输出使能信号；所述补偿模块具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始数据输出使能信号的下降沿时间，以调整每行子像素的有效充电时间，其中，每行子像素的调整后的有效充电时间与所述子像素对应的补偿增益正相关。
在一些实施例中，所述初始驱动信号包括初始数据信号；所述补偿模块具体被配置为，
根据每行子像素的补偿增益，调节每行子像素的初始数据信号的大小， 其中，所述初始数据信号调节后的大小与所述子像素对应的补偿增益正相关。
在一些实施例中，所述补偿增益表根据以下步骤生成：
驱动所述显示面板显示测试灰阶的图像；
对所述显示面板所显示画面进行图像采集；
根据采集到的图像，确定所述显示面板中每行子像素的实际亮度；
根据每行子像素的实际亮度和基准行子像素的实际亮度，确定每行子像素的补偿增益，并生成所述补偿增益表。
在一些实施例中，所述驱动电路还包括存储模块，被配置为对所述补偿增益表进行存储。
在一些实施例中，所述基准子像素行为所述显示面板在显示所述测试灰阶的图像时，亮度最低的子像素行。
在一些实施例中，所述测试灰阶大于200。
第三方面，本公开实施例还提供一种显示装置，包括显示面板和上述的驱动电路。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为一示例中提供的时序控制器与时钟信号线之间的连接示意图。
图2为本公开的一些实施例中提供的显示面板的驱动方法的示意图。
图3为本公开的一些实施例中提供的测试过程的示意图。
图4为本公开的一些实施例中提供的对初始时钟信号的调节过程示意图。
图5为本公开的一些实施例中提供的源极驱动芯片的结构示意图。
图6为本公开的一些实施例中提供的对各行子像素的初始驱动信号的调节示意图。
图7为本公开的一些实施例中提供的显示面板的驱动电路的示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
在此需要说明的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的，当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是，采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内的。其中，由于在本公开实施例中以所采用晶体管为N 型晶体管，故在本公开实施例中的工作电平信号(工作电平状态)则是指高电平信号(高电平状态)，非工作电平信号为低电平信号(低电平状态)；相应的工作电平端为高电平信号端，非工作电平端为低电平信号端。
通常显示面板包括多条栅线和多条数据线，栅线和数据线交叉设置限定出多个像素区，每个像素区均设置有薄膜晶体管。其中，以各栅线的延伸方向为行方向，各数据线的延伸方向为列方向为例对显示面板的结构进行说明。在驱动显示面板进行显示时，可以根据待显示画面，逐行给栅线写入扫描信号，同时给各数据线写入源极电压信号，以使显示面板中的像素区逐行被点亮。其中，扫描信号由栅极驱动电路提供，源极电压信号由源极驱动电路提供，其中，源极电压信号是对时序控制器提供的数据信号进行数模转换、电平转换等一系列处理后生成的，源极驱动电路输出源极电压信号的时序与时序控制器输出的数据使能(Source Output Enable，SOE)信号有关，其中，源极电压信号的起始时刻与SOE信号的下降沿时间相同。在相关技术中可以将栅极驱动电路集成在栅极驱动芯片中，将源极驱动电路集成在源极驱动芯片中；而目前为了较少芯片数量，以及实现窄边框或者无边框，提供了一种将栅极驱动电路集成在阵列基板上(Gate On Array；GOA)的技术；其中，栅极驱动电路包括集成在阵列基板上、多个级联的移位寄存器单元，移位寄存器单元与栅线一一对应连接，用于为与之连接的栅线提供扫描信号。
在驱动显示面板进行显示时，时序控制器通过时钟信号线向多个移位寄存器单元提供时钟信号，其中，在每个移位寄存器单元的输出阶段，其接收到的时钟信号处于高电平状态。但是，由于每条时钟信号线的电阻R较大，而且每条时钟信号线与其相邻的金属、介质等结构之间会形成一定的电容C(nF级)；R和C的存在会造成信号的衰减、延迟、形变，导致不同时钟信号线上所传输的时钟信号的脉宽可能产生差异，从而导致不同时钟信号线所连接的移位寄存器单元所接收到的时钟信号的脉宽可能出现差 异，进而导致不同行的像素之间的充电时间不同，引起横纹不良。
另外，由于R和C的存在会造成信号的衰减、延迟、形变，导致时钟信号并不是理想的方波信号，而是具有一定的上升时间和下降时间，从而会导致像素的充电时间不够。在一些示例中，会通过电阻电感联调(Resistance Inductor Tuning，RLT)技术，在时序控制器1与时钟信号线(CK1～CK2)之间串联电阻R0和电感L(如图1所示)，通过电感L储能，产生瞬间反向电动势，从而减小时钟信号的下降时间，但是，在时序控制器1与时钟信号线(CK1～CK2)之间串联的电阻R0和电感L均具有一定的精度范围，从而导致不同时钟信号线上的时钟信号的差异放大，当不同时钟信号线上串联的电阻R0和电感L的差异较大时，显示面板所显示的画面将出现明显的横纹不良。为了解决显示面板的横纹不良问题，本公开实施例提供一种显示面板的驱动方法和驱动电路、显示装置，下面将结合附图对本公开提供的显示面板的驱动方法和驱动电路、显示装置作进一步详细描述。
图2为本公开的一些实施例中提供的显示面板的驱动方法的示意图，该驱动方法用于驱动显示面板进行显示，其中，显示面板包括多条栅线和多条数据线，多条栅线和多条数据线交叉设置，从而限定出多个子像素，多个子像素排成多行多列，每行子像素可以对应一条栅线，每列子像素可以对应一条数据线。具体地，每个子像素中设置有薄膜晶体管，薄膜晶体管的栅极连接相应的栅线，薄膜晶体管的源极连接相应的数据线。
如图2所示，显示面板的驱动方法包括显示过程，所述显示过程包括：
S1、根据待显示的图像信息生成每行子像素的初始驱动信号。
其中，初始驱动信号可以由时序控制器生成，每行子像素的初始驱动信号是指，每行中的每个子像素的初始驱动信号，初始驱动信号可以包括初始时钟信号、初始数据信号和SOE信号。可以理解的是，同一行中各子像素的初始时钟信号是相同的，初始数据信号可以为数字信号，各子像素 的初始数据信号的大小与子像素待显示的灰阶相关，因此，同一行中不同子像素的初始数据信号的电压可能不同。
在一些示例中，时序控制器可以根据预设时序以及待显示图像的原始灰阶，生成初始驱动信号。不同行子像素对应的初始时钟信号的脉宽相同，同一列中不同的子像素的SOE信号的脉宽相同。每个子像素的初始数据信号的大小是根据待显示图像的原始灰阶确定的。在另一些实施例中，时序控制器可以根据预设时序、待显示图像的原始灰阶，生成每行子像素的原始时钟信号和原始数据信号，之后，根据mura补偿表，来确定待显示图像的中间灰阶，并根据待显示图像的中间灰阶确定每个子像素的初始驱动信号。其中，待显示图像的原始灰阶是利用亮度偏差消除技术(De-Mura)进行补偿前的灰阶，中间灰阶是利用De-Mura补偿技术对待显示图像的显示亮度进行补偿，以使其达到目标亮度所对应的灰阶。不同行子像素对应的初始时钟信号的脉宽相同，同一列中不同的子像素的SOE信号的脉宽相同。每个子像素的初始数据信号的大小是根据待显示图像的中间灰阶确定的。
S2、根据预设的补偿增益表中存储的每行子像素的补偿增益(gain)，对每行子像素的初始驱动信号进行调节，得到目标驱动信号。其中，每行子像素的补偿增益为：显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度增益。
其中，补偿增益表是在显示阶段之前的测试阶段获取到的，并可以存储在时序控制器中的存储模块中。基准行子像素可以为显示面板中的其中一行子像素。
目标驱动信号可以包括目标时钟信号、目标数据信号和目标SOE信号，上述利用补偿增益对初始驱动信号进行调节，具体可以为：利用补偿增益对初始时钟信号进行调节，得到目标驱动信号中的目标时钟信号；也可以为：利用补偿增益对初始数据信号进行调节，得到目标驱动信号中的目标数据信号；也可以为利用补偿增益对初始SOE信号进行调节，从而得到目 标驱动信号中的目标SOE信号。
S3、根据每行子像素的目标驱动信号驱动相应行的子像素进行显示，以使每行子像素达到目标亮度。
在本公开实施例中，预设的补偿增益表中包括每行子像素的补偿增益，每行子像素的补偿增益为显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度增益；根据补偿增益表来对每行子像素的初始驱动信号进行调节，可以对显示面板各行子像素的亮度进行补偿，以使各行子像素最终均能达到目标亮度，减少横纹不良的产生。
在一些实施例中，还包括测试过程，在测试过程中可以生成补偿增益表，图3为本公开的一些实施例中提供的测试过程的示意图，如图3所示，测试过程包括S01～S05：
S01、驱动显示面板显示测试灰阶的图像。
在一个示例中，测试灰阶大于200，可选地，测试灰阶在220～255之间，例如测试灰阶为223、230、233、240、250或255。
在一些实施例中，驱动显示面板显示的测试灰阶的图像，是经过De-mura技术对亮度进行补偿后的图像，因此，显示画面中不会出现mura不良。但是，De-mura技术无法对高灰阶图像中的横纹不良进行改善，即，步骤S01中，显示面板所显示的图像可能会因为上文中所述的时钟信号线上的时钟信号的差异，产生横纹不良。
S02、对显示面板所显示画面进行图像采集。
S03、根据采集到的图像，确定显示面板中每行子像素的实际亮度。
S04、根据每行子像素的实际亮度和基准行子像素的实际亮度，确定每行子像素的补偿增益，并生成补偿增益表。
在一些实施例中，基准行子像素为显示面板中亮度最低的一行子像素。表1为本公开的一些实施例中提供的每行子像素的实际亮度表，表2为本公开实施例中提供的补偿增益表，如表1和表2所示，第3行、第9行的 亮度最低，将其中一行作为基准行子像素，第i行子像素的实际亮度记作Li，基准行子像素的亮度记作L0，第i行子像素的补偿增益记作Gain_i，则Gain_i＝Li/L0，从而得到表2所示的补偿增益表。
表1
  实际亮度
第1行子像素 200
第2行子像素 200
第3行子像素 180
第4行子像素 199
第5行子像素 197
第6行子像素 198
第7行子像素 200
第8行子像素 200
第9行子像素 180
第10行子像素 201
第11行子像素 202
第12行子像素 198
…… ……
表2
  补偿增益
第1行子像素 1.111
第2行子像素 1.111
第3行子像素 1
第4行子像素 1.106
第5行子像素 1.1
第6行子像素 1.094
第7行子像素 1.111
第8行子像素 1.111
第9行子像素 1
第10行子像素 1.106
第11行子像素 1.1
第12行子像素 1.094
…… ……
S05、对补偿增益表进行存储。
下面对利用补偿增益表对初始驱动信号的几种调节方式进行具体介绍。其中，以时序控制器通过六条时钟信号线为多级移位寄存器单元提供时钟信号为例，进行说明。具体地，第(1+6n)级移位寄存器单元与第一时钟信号线连接，第(2+6n)级移位寄存器单元与第二时钟信号线连接，第(3+6n)级移位寄存器单元与第三时钟信号线连接，第(4+6n)级移位寄存器单元与第四时钟信号线连接，第(5+6n)级移位寄存器单元与第五时钟信号线连接，第(6+6n)级移位寄存器单元与第六时钟信号线连接，n为整数，n≥0。同一条时钟信号线所连接的移位寄存器单元所对应的各行子像素的初始时钟信号是相同的，同一条时钟信号线所连接的移位寄存器单元所对应的各行子像素的目标时钟信号也是相同的，且目标时钟信号由时序控制器提供至时钟信号线。
在第一种调节方式中，具体可以对初始时钟信号进行调节。上述步骤S2具体可以包括：根据每行子像素的补偿增益，调节每行子像素的初始时钟信号的下降沿时间，以调整每行子像素的栅极输出使能时间(GOE)，其中，在对初始时钟信号进行调节之前，各行子像素的GOE时间可以相同。每行子像素的调整后的栅极输出使能时间与子像素对应的补偿增益正相关。
需要说明的是，每行子像素的栅极输出使能信号(GOE)是指，每行子像素的时钟信号的下降沿，与下一行子像素的源极电压信号的起始时刻之间的间隔时间；也即，每行子像素的时钟信号的下降沿，与下一行子像素的SOE信号的下降沿之间的间隔时间。j为正整数，且j不大于子像素的总行数。设置GOE时间的目的在于防止错充，具体地，在每行子像素的扫描阶段结束后，本行子像素中的薄膜晶体管不会瞬间关掉，如果不设置GOE时间，那么，一旦本行的薄膜晶体管还未完全关闭，而下一行子像素的源极电压信号已输出至各条数据线，那么就有可能出现错充现象。某行子像素的扫描阶段是指，该行子像素对应的移位寄存器单元的输出阶段。
图4为本公开的一些实施例中提供的对初始时钟信号的调节过程示意图，图4中，仅以六行子像素的初始时钟信号的调节过程为例进行说明，其余行的调节原理相同。其中，CLK1至CLK6分别为第一行至第六行子像素的初始时钟信号，CLK1’至CLK6’分别为第一行至第六行子像素的目标时钟信号。Source2至Source7分别为第二行至第七行子像素的源极电压信号。T1至T6分别为第一行至第六行子像素的调节前的GOE时间，T1’至T6’分别是第一行至第六行子像素的调节后的GOE时间。在对初始时钟信号调节前后，各行子像素的源极电压信号未发生变化。
需要说明的是，每行子像素的初始时钟信号和目标时钟信号均为在高电平状态与低电平状态之间切换的时钟信号，图4中在对每行子像素的初始时钟信号/源极电压信号进行示意时，仅示出了其中一个高电平状态。
对于上文表2所示的补偿增益表，即，显示面板的第三行子像素出现暗纹，这种情况下，可以增加CLK3的脉宽，即，将CLK3下降沿相对于CLK1后移，从而减小第三行子像素的GOE时间(从T3减小至T3’)，这样有利于提高第三行子像素的充电时间，从而提高第三行子像素的亮度。
可选地，第i行子像素的调节后的GOE时间满足以下关系：Ti’＝T0*Gain_i*A，其中，Ti’为第i行子像素的调节后的GOE时间，T0为基 准行子像素的调节后的GOE时间，在图4中，T3’即为T0；A为与显示面板的充电率相关的比例系数，充电率等于显示面板的实际亮度与理论亮度之比。
在第一种调节方式中，可以仅对初始驱动信号中的初始时钟信号调节，不对初始数据信号调节。调节后的初始时钟信号即为目标时钟信号，而目标数据信号与初始数据信号相同，目标SOE信号与初始SOE信号相同。
在第二种调节方式中，具体可以对初始SOE信号进行调节。上述步骤S2具体可以包括：根据每行子像素的补偿增益，调节每行子像素的初始SOE信号的下降沿时间，以调节源极驱动芯片输出源极电压信号的起始时间，从而调整每行子像素的有效充电时间，其中，每行子像素的调整后的有效充电时间与所述子像素对应的补偿增益正相关。
其中，SOE信号用于控制源极驱动芯片输出源极电压信号的时间，图5为本公开的一些实施例中提供的源极驱动芯片的结构示意图，如图5所示，源极驱动芯片包括：第一缓存单元Latch1、选通开关K1、第二缓存单元Latch2、电平转换器LS、数模转换器DAC、极性控制单元21、放大器OP、输出控制单元22。其中，时序控制器输出的目标数据信号先存储在第一缓存单元Latch1中，当选通开关K1响应于选通信号而导通时，将目标数据信号传输至第二缓存单元Latch2，之后，目标数据信号经电平转换器LS进行电平转换，再经数模转换器DAC进行数模转换，生成模拟信号。极性控制单元22对模拟信号进行极性控制，从而根据需要对模拟信号的极性进行控制，例如，在一个示例中，源极驱动芯片的第N个输出端需要输出正极性的电压信号，第N+1个输出端需要输出负极性的电压信号，则极性控制单元21通过其内部的多个开关的控制，使第N个输出端对应的模数转换器DAC输出的模拟信号的极性为正，并将其传输至相应的放大器OP，使第N+1个输出端对应的模数转换器DAC输出的模拟信号的极性为负，并将其传输至相应的放大器OP。输出控制单元22响应于SOE信号的下降沿，将 每个放大器OP输出的电压信号传输至源极驱动电路的相应输出端。
其中，每行子像素的有效充电时间为该行子像素的时钟信号的高电平阶段与源极电压信号的有效阶段的重叠时间。需要说明的是，源极电压信号的“有效阶段”并不包括无效阶段与有效阶段之间的过度阶段。对于本公开实施例，每行子像素调节前的有效充电时间即为，初始时钟信号的高电平阶段与调节前的源极电压信号的有效阶段的重叠时间；调节后的有效充电时间即为，目标时钟信号的高电平阶段与调节后的源极电压信号的有效阶段的重叠时间。由于源极电压信号是源极驱动芯片响应于SOE信号的下降沿而输出的，因此，通过调节SOE信号的下降沿时间，可以调节子像素的有效充电时间。
图6为本公开的一些实施例中提供的对各行子像素的初始驱动信号的调节示意图，图6中仅以三行子像素为例进行说明，如图6所示，CLK1～CLK3分别为前三行子像素的初始时钟信号，CLK1’～CLK3’分别为前三行的目标时钟信号，其中，各行子像素的目标时钟信号可以与初始时钟信号相同。SOE1～SOE3分别为前三行子像素的初始SOE信号，SOE1’～SOE3’分别为前三行子像素的目标SOE信号。Source1～Source3分别为第一行至第三行子像素的调节前的源极电压信号，Source1’～Source3’分别为第一行至第三行子像素的调节后的源极电压信号。各行子像素的调节前的有效充电时间可以相等。
对于上文表2中所示的补偿增益表，由于第三行子像素的补偿增益较小，因此可以对SOE3的下降沿进行前移，从而使得SOE3’的下降沿提前于SOE1’和SOE2’，从而增大第三行子像素的有效充电时间，进而提高第三行子像素的亮度。另外，在调节初始SOE信号时，可以不对其上升沿做调整。
在第三种调节方式中，可以对初始数据信号的大小进行调节。具体地，可以根据每行子像素的补偿增益，调节每行子像素的初始数据信号的大小，其中，所述初始数据信号调节后的大小与所述子像素对应的补偿增益正相 关。在第三种调节方式中，调节后的初始数据信号即为目标驱动信号中的目标数据信号，而目标时钟信号、目标SOE信号可以分别与初始时钟信号、初始SOE信号相同。
其中，可以根据预设的对应关系表来确定目标数据信号的大小。
图7为本公开的一些实施例中提供的显示面板的驱动电路的示意图，如图7所示，驱动电路包括：初始信号生成模块10、补偿模块20、驱动模块30。
其中，初始信号生成模块10被配置为，根据待显示图像的图像信息生成每行子像素的初始驱动信号。初始驱动信号具体可以包括初始时钟信号、初始数据信号和初始SOE信号。
补偿模块20被配置为，根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行子像素的初始驱动信号进行调节，得到目标驱动信号；其中，每行子像素的补偿增益为：显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度系数。
驱动模块30被配置为，根据每行子像素的目标驱动信号驱动相应行的子像素进行显示，以使每行子像素达到目标亮度。
其中，初始信号生成模块10和补偿模块20可以集成在时序控制器中，驱动模块30可以包括栅极驱动电路和源极驱动电路。
在一些实施例中，所述补偿模块20具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始时钟信号的下降沿时间，以调整每行子像素的栅极输出使能时间，其中，每行子像素的调整后的栅极输出使能时间与所述子像素对应的补偿增益正相关。
对初始时钟信号的具体调节过程参见上文说明，这里不再赘述。
在另一些实施例中，补偿模块20具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始SOE信号的下降沿时间，以调整每行子像素的有效充电时间，其中，每行子像素的调整后的有效充电时间与所述子 像素对应的补偿增益正相关。
对初始SOE信号的调节过程参见上文说明，这里不再赘述。
在再一些实施例中，补偿模块20具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始数据信号的大小，其中，所述初始数据信号调节后的大小与所述子像素对应的补偿增益正相关。
对初始数据信号的调节过程参见上文说明，这里不再赘述。
在一些实施例中，补偿增益表根据以下步骤生成：驱动所述显示面板显示测试灰阶的图像；对所述显示面板所显示画面进行图像采集；根据采集到的图像，确定所述显示面板中每行子像素的实际亮度；根据每行子像素的实际亮度和基准行子像素的实际亮度，确定每行子像素的补偿增益，并生成所述补偿增益表。可选地，基准子像素行为所述显示面板在显示所述测试灰阶的图像时，亮度最低的子像素行。可选地，测试灰阶大于200。
其中，所述驱动电路还包括存储模块，被配置为对所述补偿增益表进行存储。补偿增益表可以在显示过程之前的测试过程中生成，在显示过程中进行图像显示时，时序控制器可以调用存储模块中存储的补偿增益表来对初始驱动信号进行调节，从而生成目标驱动信号。通过对初始驱动信号的调节，可以对由于时钟信号线的电阻差异等原因的导致的不同行的像素充电差异进行补偿，从而减少横纹不良，提高显示效果。
本公开实施例还提供一种显示装置，包括显示面板和上述实施例中的驱动电路。该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (16)

  1. 一种显示面板的驱动方法，所述显示面板包括多行子像素，所述驱动方法包括显示过程，所述显示过程包括：
    根据待显示图像的图像信息生成每行所述子像素的初始驱动信号；
    根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，得到目标驱动信号；其中，每行子像素的补偿增益为：所述显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度系数；
    根据每行所述子像素的所述目标驱动信号驱动相应行的子像素进行显示，以使每行所述子像素达到目标亮度。
  2. 根据权利要求1所述的驱动方法，其中，所述初始驱动信号包括初始时钟信号，
    根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，具体包括：
    根据每行子像素的补偿增益，调节每行子像素的初始时钟信号的下降沿时间，以调整每行子像素的栅极输出使能时间，其中，每行子像素的调整后的栅极输出使能时间与所述子像素对应的补偿增益正相关。
  3. 根据权利要求1所述的驱动方法，其中，所述初始驱动信号包括初始数据输出使能信号；根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，具体包括：
    根据每行子像素的补偿增益，调节每行子像素的初始数据输出使能信号的下降沿时间，以调整每行子像素的有效充电时间，其中，每行子像素的调整后的有效充电时间与所述子像素对应的补偿增益正相关。
  4. 根据权利要求1所述的驱动方法，其中，所述初始驱动信号包括初始数据信号；根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，具体包括：
    根据每行子像素的补偿增益，调节每行子像素的初始数据信号的大小，其中，所述初始数据信号调节后的大小与所述子像素对应的补偿增益正相关。
  5. 根据权利要求1至4中任意一项所述的驱动方法，其中，所述驱动方法还包括在所述显示过程之前进行的测试过程，所述测试过程包括：
    驱动所述显示面板显示测试灰阶的图像；
    对所述显示面板所显示画面进行图像采集；
    根据采集到的图像，确定所述显示面板中每行子像素的实际亮度；
    根据每行子像素的实际亮度和基准行子像素的实际亮度，确定每行子像素的补偿增益，并生成所述补偿增益表；
    对所述补偿增益表进行存储。
  6. 根据权利要求1至4中任意一项所述的驱动方法，其中，所述基准子像素行为所述显示面板在显示所述测试灰阶的图像时，亮度最低的子像素行。
  7. 根据权利要求1至4中任意一项所述的驱动方法，其中，所述测试灰阶大于200。
  8. 一种显示面板的驱动电路，所述显示面板包括多行子像素，所述驱动电路包括：
    初始信号生成模块，被配置为根据待显示的图像信息生成每行所述子 像素的初始驱动信号；
    补偿模块，被配置为根据预设的补偿增益表中存储的每行子像素的补偿增益，对每行所述子像素的所述初始驱动信号进行调节，得到目标驱动信号；其中，每行子像素的补偿增益为：所述显示面板在显示测试灰阶的图像时，该行子像素相对于基准行子像素的实际亮度系数；
    驱动模块，被配置为根据每行所述子像素的所述目标驱动信号驱动相应行的子像素进行显示，以使每行所述子像素达到目标亮度。
  9. 根据权利要求8所述的驱动电路，其中，所述初始驱动信号包括初始时钟信号；所述补偿模块具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始时钟信号的下降沿时间，以调整每行子像素的栅极输出使能时间，其中，每行子像素的调整后的栅极输出使能时间与所述子像素对应的补偿增益正相关。
  10. 根据权利要求8所述的驱动电路，其中，所述初始驱动信号包括初始数据输出使能信号；所述补偿模块具体被配置为，根据每行子像素的补偿增益，调节每行子像素的初始数据输出使能信号的下降沿时间，以调整每行子像素的有效充电时间，其中，每行子像素的调整后的有效充电时间与所述子像素对应的补偿增益正相关。
  11. 根据权利要求8所述的驱动电路，其中，所述初始驱动信号包括初始数据信号；所述补偿模块具体被配置为，
    根据每行子像素的补偿增益，调节每行子像素的初始数据信号的大小，其中，所述初始数据信号调节后的大小与所述子像素对应的补偿增益正相关。
  12. 根据权利要求8至11中任一项所述的驱动电路，其中，所述补偿增益表根据以下步骤生成：
    驱动所述显示面板显示测试灰阶的图像；
    对所述显示面板所显示画面进行图像采集；
    根据采集到的图像，确定所述显示面板中每行子像素的实际亮度；
    根据每行子像素的实际亮度和基准行子像素的实际亮度，确定每行子像素的补偿增益，并生成所述补偿增益表。
  13. 根据权利要求8至11中任一项所述的驱动电路，其中，所述驱动电路还包括存储模块，被配置为对所述补偿增益表进行存储。
  14. 根据权利要求8至11中任一项所述的驱动电路，其中，所述基准子像素行为所述显示面板在显示所述测试灰阶的图像时，亮度最低的子像素行。
  15. 根据权利要求8至11中任一项所述的驱动电路，其中，所述测试灰阶大于200。
  16. 一种显示装置，包括显示面板和权利要求8至15中任一项所述的驱动电路。
PCT/CN2022/078252 2022-02-28 2022-02-28 显示面板的驱动方法、驱动电路、显示装置 WO2023159557A1 (zh)

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