WO2023155263A1 - Shallow trench isolation structure, preparation method therefor, and semiconductor structure - Google Patents

Shallow trench isolation structure, preparation method therefor, and semiconductor structure Download PDF

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Publication number
WO2023155263A1
WO2023155263A1 PCT/CN2022/081487 CN2022081487W WO2023155263A1 WO 2023155263 A1 WO2023155263 A1 WO 2023155263A1 CN 2022081487 W CN2022081487 W CN 2022081487W WO 2023155263 A1 WO2023155263 A1 WO 2023155263A1
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layer
substrate
oxide layer
hard mask
oxide
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PCT/CN2022/081487
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French (fr)
Chinese (zh)
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高远皓
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Definitions

  • the present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a shallow trench isolation structure, a preparation method thereof, and a semiconductor structure.
  • the feature size of devices in integrated circuits is getting smaller and smaller.
  • the isolation and planarization process becomes more and more important.
  • the Shallow Trench Isolation (STI) process has excellent isolation performance and has gradually become one of the mainstream isolation technologies for device active area isolation.
  • Defects such as divots, holes, or sharp corners appear on local edges of the isolation structure.
  • the isolation performance of the shallow trench isolation structure is affected, thereby affecting the electrical performance of the semiconductor structure, such as leakage current, narrow channel effect and other defects.
  • a shallow trench isolation structure a manufacturing method thereof, and a semiconductor structure are provided.
  • a substrate is provided, and an oxygen pad layer and a hard mask layer are sequentially stacked on the surface of the substrate.
  • the pad oxide layer and the substrate are etched using the patterned hard mask layer as a mask to form openings in the pad oxide layer and grooves in the substrate.
  • a substrate oxide layer is formed within the trench.
  • a first barrier layer is formed, and the first barrier layer covers the hard mask layer and the substrate oxide layer.
  • a first oxide layer is formed, and the first oxide layer covers the first barrier layer.
  • the first barrier layer and the first oxide layer on the upper surface of the hard mask layer are removed.
  • the oxygen pad layer and the hard mask layer on the upper surface of the substrate are removed to form a second barrier layer.
  • the preparation method further includes the following steps.
  • forming a substrate oxide layer in the trench includes the following steps.
  • Oxide within the pattern of openings and hard mask layer is removed such that the oxide remaining within the trench constitutes a substrate oxide layer.
  • removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer, and removing the pad oxide layer and the hard mask layer on the upper surface of the substrate to form the second barrier layer include the following steps.
  • the oxygen pad layer and the middle oxide layer are removed so that the middle barrier layer forms a second barrier layer.
  • a wet etching process is used to remove the pad oxide layer and the intermediate oxide layer.
  • the materials of the oxygen pad layer and the first oxide layer are the same.
  • the material of the first barrier layer includes polysilicon.
  • the thickness of the first barrier layer ranges from 1 nm to 3 nm.
  • another aspect of the present disclosure provides a shallow trench isolation structure, which is prepared by using the preparation method described in some embodiments above.
  • another aspect of the present disclosure provides a semiconductor structure, including: a substrate, a plurality of transistors, and the shallow trench isolation structure as described in some embodiments above.
  • the substrate has grooves.
  • the shallow trench isolation structure is arranged in the trench and isolates a plurality of active regions in the substrate.
  • the transistors are disposed in the corresponding active regions.
  • the transistor includes: a Metal Oxide Semiconductor Field Effect Transistor.
  • the gate length of metal-oxide-semiconductor field-effect transistors is less than 50nm.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the second barrier layer may be formed based on the first barrier layer.
  • the first oxide layer on the upper surface of the oxide layer of the substrate and the oxygen layer can be removed synchronously, so that the first barrier layer on the upper surface of the oxide layer of the substrate forms a second barrier layer.
  • the substrate oxide layer can be protected and isolated by using the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer.
  • the second barrier layer covers the substrate oxide layer, which can effectively avoid over-etching at the edge of the substrate oxide layer due to accumulation of etching solution. Therefore, defects such as divots, holes or sharp corners in the shallow trench isolation structure formed by the oxide layer of the substrate can be avoided. In this way, a shallow trench isolation structure with high molding surface quality can be obtained, so as to ensure the integrity of the edge of the shallow trench isolation structure.
  • the second barrier layer covers the exposed surface of the oxide layer of the substrate, that is, the second barrier layer protrudes from the upper surface of the substrate. Therefore, the second barrier layer can be oxidized so that part of the surface of the second barrier layer and the substrate can be oxidized and transformed into a second oxide layer, and then removed by cleaning the oxidized surface to ensure that a flat upper surface is obtained. the substrate. Therefore, the preparation process of the shallow trench isolation structure is simplified, and the shallow trench isolation structure has a higher surface quality.
  • FIG. 1 is a schematic flowchart of a method for preparing a shallow trench isolation structure provided in an embodiment
  • FIG. 2 is a schematic cross-sectional view of the structure obtained after forming an oxygen pad layer and a hard mask layer provided in an embodiment
  • FIG. 3 is a schematic cross-sectional view of a structure obtained after forming a photoresist layer provided in an embodiment
  • FIG. 4 is a schematic cross-sectional view of a structure obtained after forming a patterned hard mask layer provided in an embodiment
  • FIG. 6 is a schematic flowchart of step S300 provided in an embodiment
  • FIG. 7 is a schematic cross-sectional view of a structure obtained after depositing an oxide in the pattern of trenches, openings, and a hard mask layer provided in an embodiment
  • FIG. 9 is a schematic flowchart of step S300 provided in another embodiment.
  • FIG. 10 is a schematic cross-sectional view of a structure obtained after forming a first barrier layer provided in an embodiment
  • FIG. 11 is a schematic cross-sectional view of a structure obtained after forming a first oxide layer provided in an embodiment
  • FIG. 12 is a schematic flowchart of step S600 provided in an embodiment
  • FIG. 13 is a schematic cross-sectional view of a structure obtained after forming an intermediate barrier layer and a first intermediate oxide layer provided in an embodiment
  • FIG. 14 is a schematic cross-sectional view of a structure obtained after forming a second barrier layer and a second intermediate oxide layer provided in an embodiment
  • Fig. 15 is a schematic cross-sectional view of the structure obtained after removing the oxygen pad layer provided in an embodiment
  • FIG. 16 is a schematic flowchart of a method for manufacturing a shallow trench isolation structure provided in another embodiment
  • 17 is a schematic cross-sectional view of a structure obtained after forming a second oxide layer provided in an embodiment
  • FIG. 18 is a schematic cross-sectional view of a structure obtained after forming a shallow trench isolation structure provided in an embodiment
  • FIG. 19 is a schematic diagram of a semiconductor structure provided in an embodiment.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • the regions shown in the figures are schematic in nature and their shapes are not indicative of the actual shape of a region of a device and are not intended to limit the scope of the disclosure.
  • some embodiments of the present disclosure provide a method for fabricating a shallow trench isolation structure, including the following steps.
  • a substrate is provided, and an oxygen pad layer and a hard mask layer are sequentially stacked on the surface of the substrate.
  • the patterned hard mask layer is used as a mask to etch the oxygen pad layer and the substrate to form an opening in the oxygen pad layer
  • a trench is formed in the substrate.
  • a substrate oxide layer is formed in the trench
  • a first barrier layer is formed on the substrate oxide layer and the hard mask layer
  • a first oxide layer is formed on the first barrier layer, so that the upper surface of the hard mask layer can be removed.
  • the first barrier layer and the first oxide layer so as to retain the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer.
  • the second barrier layer may be formed based on the first barrier layer.
  • the substrate oxide layer can be protected and isolated by using the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer.
  • the second barrier layer formed on the substrate oxide layer covers the substrate oxide layer, which can effectively avoid excessive corrosion caused by accumulation of etching solution at the edge of the substrate oxide layer. carve. Therefore, defects such as divots, holes or sharp corners in the shallow trench isolation structure formed by the oxide layer of the substrate can be avoided. In this way, a shallow trench isolation structure with high molding surface quality can be obtained, so as to ensure the integrity of the edge of the shallow trench isolation structure.
  • the second barrier layer covers the exposed surface of the oxide layer of the substrate, that is, the second barrier layer protrudes from the upper surface of the substrate. This facilitates the oxidation treatment of the second barrier layer, so that part of the surface of the second barrier layer and the substrate is oxidized and transformed into a second oxide layer, and then removed by cleaning the oxidized surface to ensure that a flat upper surface is obtained. substrate. Therefore, the preparation process of the shallow trench isolation structure is simplified, and the shallow trench isolation structure has a higher surface quality.
  • the embodiments of the present disclosure can ensure the surface quality of the shallow trench isolation structure after forming, so as to improve the isolation performance of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor structure, and improving the reliability and yield of the semiconductor structure .
  • the substrate 10 may be made of semiconductor material, insulating material, conductive material or any combination thereof.
  • the substrate 10 can be a single-layer structure or a multi-layer structure.
  • the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic An indium (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the substrate 10 may be a layered substrate including, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
  • the substrate 10 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
  • the pad oxide layer (Pad Oxide) 11 includes but not limited to a silicon dioxide (SiO 2 ) layer.
  • the oxygen pad layer 11 is used as a transitional buffer layer between the hard mask layer 12 and the substrate 10, and low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD) or atomic layer chemical vapor deposition can be used. Deposition (ALCVD) and other processes are formed.
  • LPCVD low-pressure chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • ACVD atomic layer chemical vapor deposition
  • hard mask layer 12 includes, but is not limited to, a silicon nitride layer.
  • the hard mask layer 12 may also be a silicon oxynitride layer.
  • the hard mask layer 12 is used as a mask for trenches on the subsequent substrate 10, and can be formed by processes such as high-density plasma chemical vapor deposition (HDPCVD) or plasma-enhanced chemical vapor deposition (PECVD), and Patterned by patterning process.
  • HDPCVD high-density plasma chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • a photoresist material is coated on the surface of the hard mask layer 12 and photolithography processes such as exposure and development are performed to form a photoresist pattern 20 that can define trench positions and have openings.
  • the hard mask layer 12 can be etched based on the photoresist pattern 20 , for example, by reactive ion etching or plasma etching, to form a patterned hard mask layer 12 , such as shown in FIG. 4 .
  • step S200 referring to S200 in FIG. 1 and FIG. 4 and FIG. 5 , the patterned hard mask layer 12 is used as a mask to etch the pad oxide layer 11 and the substrate 10, so that the pad oxide layer 11 An opening K is formed, and a trench G is formed in the substrate 10 .
  • the etching of the oxygen pad layer 11 and the substrate 10 in step S200 includes wet etching or dry etching, wherein the dry etching includes at least reactive ion etching (RIE), inductively coupled plasma etching Either one of (ICP) or high-density plasma etching (HDP).
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • HDP high-density plasma etching
  • the etching methods of the oxygen pad layer 11 and the substrate 10 may be the same or different.
  • the number and formation positions of the above-mentioned openings K and trenches G can be selected and set according to the corresponding active regions to be isolated. Embodiments of the present disclosure do not limit this.
  • step S300 referring to S300 in FIG. 1 and FIGS. 6 to 9 , a substrate oxide layer 13 is formed in the trench G. Referring to FIG.
  • step S300 includes the following steps.
  • oxide 130 includes, but is not limited to, silicon dioxide (SiO 2 ).
  • the oxide 130 may be deposited by high density plasma chemical vapor deposition (HDP-CVD) or other processes.
  • HDP-CVD high density plasma chemical vapor deposition
  • the oxide 130 is first deposited in the pattern of the trench G, the opening K and the hard mask layer 12, and then the oxide 130 located in the pattern of the opening K and the hard mask layer 12 is removed.
  • a substrate oxide layer 13 is formed. In this way, the material density of the substrate oxide layer 13 can be improved, and it is beneficial to ensure that the formation surface of the substrate oxide layer 13 is flush with the upper surface of the substrate 10 .
  • step S300 after depositing the oxide 130 in the pattern of the trench G, the opening K and the hard mask layer 12 , after removing the Before the oxide 130 in the pattern, step S300 further includes the following steps.
  • the exposed surfaces of the hard mask layer 12 and the oxide 130 can be guaranteed to be even and planar, so as to facilitate the subsequent precise etching of the oxide 130 , for example, to be etched to be flush with the upper surface of the substrate 10 .
  • step S400 referring to S400 in FIG. 1 and FIG. 10 , a first barrier layer 14 is formed, and the first barrier layer 14 covers the hard mask layer 12 and the substrate oxide layer 13 .
  • the upper surface of the substrate oxide layer 13 and the upper surface of the substrate 10 may be located on the same plane.
  • the portion of the first barrier layer 14 covering the substrate oxide layer 13 is located within the pattern of the opening K of the oxygen pad layer 11 and the hard mask layer 12 .
  • the material of the first barrier layer 14 includes polysilicon. In this way, after the subsequent formation of the second barrier layer 16 based on the first barrier layer 14, it is convenient to perform oxidation treatment on the second barrier layer 16 and remove it by removing the oxidized surface, thereby simplifying the preparation process of the shallow trench isolation structure, And ensure the surface quality of the shallow trench isolation structure after molding.
  • the thickness of the first barrier layer 14 can be set according to actual needs.
  • the thickness of the first barrier layer 14 ranges from 1 nm to 3 nm, such as 1 nm, 2 nm or 3 nm. But it doesn't stop there.
  • the thickness of the first barrier layer 14 is relatively thin, the structure of the first barrier layer 14 is likely to be unstable, for example, it is difficult to form stably, which is not conducive to the formation of the first barrier layer 14 after multiple etchings.
  • the shape of the second barrier layer 16 is set.
  • the thickness of the first barrier layer 14 is relatively thick, it will take more time to oxidize the second barrier layer 16 formed based on the first barrier layer 14 later, which is not conducive to improving production efficiency.
  • setting the value range of the thickness of the first barrier layer 14 at 1 nm to 3 nm can make the forming surface of the first barrier layer 14 exist due to the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12
  • the resulting concave surface that is, the first barrier layer 14 has a depression caused by the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12
  • step S500 referring to S500 in FIG. 1 and FIG. 11 , a first oxide layer 15 is formed, and the first oxide layer 15 covers the first barrier layer 14 .
  • part of the material of the first oxide layer 15 can be used to fill up the depression formed by the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12 in the first barrier layer 14 .
  • the first oxide layer 15 and the oxygen pad layer 11 are made of the same material, such as silicon dioxide. In this way, it is convenient to use the same process to remove the pad oxide layer 11 and the first oxide layer 15, so as to simplify the manufacturing process of the shallow trench isolation structure.
  • step S600 referring to S600 in FIG. 1 and FIGS. 12 to 15, the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12 are removed, and the oxygen pad layer on the upper surface of the substrate 10 is removed. 11 and hard mask layer 12 to form a second barrier layer 16 .
  • step S600 includes the following steps.
  • a chemical mechanical polishing process can be used to remove the parts of the first barrier layer 14 and the first oxide layer 15 located on the upper surface of the hard mask layer 12, so as to form the intermediate barrier layer 14' and the intermediate oxide layer 15. ', and ensure that the upper surfaces of the middle barrier layer 14' and the middle oxide layer 15' are on the same plane.
  • polishing liquid and the polishing time used in the chemical mechanical polishing process can be selected and set according to actual needs, which is not limited in the embodiments of the present disclosure.
  • the hard mask layer 12 is removed by a wet etching process.
  • the hard mask layer 12 is wet-etched using a hot phosphoric acid solution, and the temperature of the hot phosphoric acid solution may be 150° C. ⁇ 170° C.
  • a first pure water cleaning process may also be performed to remove residual hot phosphoric acid. Since the temperature of hot phosphoric acid is too high, if the substrate 10 is directly placed in a normal temperature water tank for cleaning, there is a risk of fragmentation. Therefore, the temperature of the first pure water cleaning process may be 50°C-70°C.
  • a wet etching process is used to remove the pad oxide layer 11 and the middle oxide layer 15 ′.
  • hydrofluoric acid is used to etch the pad oxide layer 11 and the middle oxide layer 15 ′.
  • part of the material of the first oxide layer 15 can be used to fill up the depression formed by the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12 in the first barrier layer 14 .
  • the intermediate barrier layer 14' has a U-shaped thin-walled structure, and the intermediate oxide layer 15' fills up the intermediate barrier layer.
  • the layer 14' can support the intermediate barrier layer 14', so as to ensure the stability of the structure of the intermediate barrier layer 14' during the subsequent removal of the hard mask layer 12, the oxygen pad layer 11 and the intermediate oxide layer 15'.
  • the second barrier layer 16 can also be formed in other ways. For example, first remove the first barrier layer 14 and the first oxide layer 15 both on the upper surface of the hard mask layer 12, to form the intermediate barrier layer 14' and the first intermediate oxide layer 15'; then, remove the hard mask Layer 12, and the part of the intermediate barrier layer 14' and the first intermediate oxide layer 15' protruding from the upper surface of the oxygen pad layer 11 to form the second barrier layer 16 and the second intermediate oxide layer; finally remove the oxygen pad layer layer 11 and the second intermediate oxide layer. But it is not limited thereto, as long as the formed second barrier layer 16 can effectively isolate the substrate oxide layer 13 .
  • the removal of the above-mentioned layer structures may also be implemented by a dry etching process.
  • the manufacturing method of the shallow trench isolation structure further includes the following steps.
  • the first oxide layer on the upper surface of the oxide layer of the substrate and the oxygen pad layer can be removed synchronously, so that the first barrier layer on the upper surface of the oxide layer of the substrate forms the first barrier layer.
  • Two barrier layers Based on this, after oxidizing the surface of the second barrier layer and part of the substrate, the surface of the second barrier layer and part of the substrate is oxidized and transformed into a second oxide layer, so that the second oxide layer can be removed by cleaning the oxidized surface.
  • the oxide layer thereby simplifying the preparation process of the shallow trench isolation structure, and further ensuring that the shallow trench isolation structure has a higher surface quality.
  • the isolation performance of the shallow trench isolation structure can be further improved, so as to further improve the electrical performance of the semiconductor structure, and effectively improve the reliability and yield of the semiconductor structure.
  • step S700 referring to S700 in FIG. 16 and FIG. 17 , the second barrier layer 16 and part of the surface of the substrate 10 are oxidized to form a second oxide layer 17 .
  • the resulting structure after forming the second barrier layer 16 is placed in an oxidizing environment, for example, an oxidant gas flow is passed through the resulting structure after forming the second barrier layer 16, and the resulting structure is placed in a high-temperature environment, So that the material of the second barrier layer 16 and part of the surface of the substrate 10 is converted from polysilicon or silicon to silicon oxide.
  • the temperature of the high-temperature environment can be selected and set according to actual needs, and the thickness of the oxidized material of the substrate 10 can be selected and set according to actual needs. The embodiments of the present disclosure do not limit this.
  • an SC1 cleaning process may be performed to remove impurities on the substrate.
  • the cleaning solution of the SC1 cleaning process includes ammonia water, hydrogen peroxide and water, and the volume ratio of ammonia water: hydrogen peroxide water: water is, for example, 1:2:100 ⁇ 1:2:10.
  • the concentration of ammonia water is, for example, 27%
  • the concentration of hydrogen peroxide is, for example, 30%.
  • the temperature of the SC1 cleaning solution is, for example, 20°C to 50°C.
  • the cleaning time of the SC1 cleaning solution is, for example, 0.5 min to 10 min.
  • a second pure water cleaning process may also be performed as appropriate to remove the remaining SC1 solution on the substrate 10 .
  • the temperature of the second pure water cleaning process is, for example, 20°C ⁇ 30°C.
  • removing the second oxide layer 17 and part of the substrate oxide layer 13 includes: cleaning the structure obtained after the formation of the second oxide layer 17 with a dilute hydrofluoric acid solution to remove the second oxide layer 17 and Part of the substrate oxide layer 13.
  • the volume ratio of hydrofluoric acid to water is, for example, 1:100 to 1:500.
  • the temperature of the diluted hydrofluoric acid solution is, for example, 15°C to 30°C.
  • some embodiments of the present disclosure also provide a shallow trench isolation structure 18 , which is prepared by using the preparation method described in some embodiments above.
  • some embodiments of the present disclosure further provide a semiconductor structure, including: a substrate 10 , a plurality of transistors 20 , and the shallow trench isolation structure 18 as described in some embodiments above.
  • the substrate 10 has a groove G.
  • the shallow trench isolation structure 18 is disposed in the trench G and isolates a plurality of active regions S in the substrate 10 .
  • the transistor 20 is disposed in the corresponding active region S.
  • a plurality of active regions S may be arranged in an array.
  • the active area includes a source area and a drain area.
  • the material of the active region is, for example, polysilicon (poly), and the source region and the drain region of the active region are respectively different doped regions of the polysilicon.
  • a transistor generally includes a gate, a source, and a drain; wherein, the source may be connected to the source region of the active region, and the drain may be connected to the drain region of the active region.
  • the transistor 20 includes: a Metal Oxide Semiconductor Field Effect Transistor (MOSFET for short), such as an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), or a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Semiconductor Field Effect Transistor (PMOSFET).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • NMOSFET N-type Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET P-type Metal Oxide Semiconductor Field Effect Transistor
  • the gate length of the metal oxide semiconductor field effect transistor is less than 50 nm.
  • the gate length of the metal oxide semiconductor field effect transistor refers to the length of the conductive channel that the gate can control, that is, the distance between the drain and the source.
  • the edge of the shallow trench isolation structure is complete, which can effectively isolate different active regions when the size of the semiconductor structure is small, so as to avoid the reverse narrow channel of the metal oxide semiconductor field effect transistor. effect, thereby effectively improving the electrical performance of the metal oxide semiconductor field effect transistor, for example, effectively improving the switching response speed of the metal oxide semiconductor field effect transistor.

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Abstract

The present disclosure relates to a shallow trench isolation structure, a preparation method therefor, and a semiconductor structure. The preparation method comprises: providing a substrate, and sequentially forming a pad oxide layer and a hard mask layer on the surface of the substrate in a laminated way; etching the pad oxide layer and the substrate by using a patterned hard mask layer as a mask, so as to form openings in the pad oxide layer and form trenches in the substrate; forming a substrate oxide layer in the trenches; forming a first barrier layer, the first barrier layer covering the hard mask layer and the substrate oxide layer; forming a first oxide layer, the first oxide layer covering the first barrier layer; removing the first barrier layer and the first oxide layer from the upper surface of the hard mask layer; and removing the pad oxide layer and the hard mask layer from the upper surface of the substrate to form a second barrier layer. The present disclosure can improve the isolation performance of a shallow trench isolation structure, so that the use reliability and yield of a semiconductor structure are improved.

Description

浅沟槽隔离结构及其制备方法、半导体结构Shallow trench isolation structure and its preparation method, semiconductor structure
相关申请的交叉引用Cross References to Related Applications
本公开要求于2022年02月18日提交中国专利局、申请号为202210153623.7的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开中。This disclosure claims the priority of a Chinese patent with application number 202210153623.7 filed with China Patent Office on February 18, 2022, the entire content of which is incorporated by reference in this disclosure.
技术领域technical field
本公开涉及半导体集成电路制造技术领域，特别是涉及一种浅沟槽隔离结构及其制备方法、半导体结构。The present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a shallow trench isolation structure, a preparation method thereof, and a semiconductor structure.
背景技术Background technique
随着半导体技术的发展，集成电路中器件的特征尺寸越来越小。在半导体工艺进入深亚微米阶段后，为了实现高密度及高性能的器件及半导体结构，隔离与平坦化工艺变得越来越重要。With the development of semiconductor technology, the feature size of devices in integrated circuits is getting smaller and smaller. After the semiconductor process enters the deep submicron stage, in order to realize high-density and high-performance devices and semiconductor structures, the isolation and planarization process becomes more and more important.
目前，浅沟槽隔离(Shallow Trench Isolation，简称STI)工艺具有优异的隔离性能，已逐渐成为器件有源区隔离的主流隔离技术之一。At present, the Shallow Trench Isolation (STI) process has excellent isolation performance and has gradually become one of the mainstream isolation technologies for device active area isolation.
然而，相关技术中，浅沟槽隔离结构的形成往往离不开硬掩膜层和垫氧层的使用。例如，先在衬底的表面依次层叠形成垫氧层和硬掩膜层；然后依次刻蚀硬掩膜层、垫氧层和衬底，以在衬底中形成沟槽；之后在沟槽中填充氧化物，以形成浅沟槽隔离结构；最后去除硬掩膜层和垫氧层。由于垫氧层与浅沟槽隔离结构的材料均包含氧化物，因此在去除垫氧层的过程中，浅沟槽隔离结构的拐角或边界处也容易出现被刻蚀的情况，导致浅沟槽隔离结构的局部边缘出现凹陷(divot)、孔洞或尖角等缺陷。从而影响浅沟槽隔离结构的隔离性能，进而影响半导体结构的电学性能，例如出现漏电流、窄沟道效应等不良。However, in the related art, the formation of the shallow trench isolation structure is often inseparable from the use of a hard mask layer and an oxygen pad layer. For example, an oxygen pad layer and a hard mask layer are sequentially stacked on the surface of the substrate; then the hard mask layer, the oxygen pad layer, and the substrate are sequentially etched to form a trench in the substrate; Oxide is filled to form a shallow trench isolation structure; finally, the hard mask layer and the pad oxygen layer are removed. Since the materials of the oxygen pad layer and the shallow trench isolation structure both contain oxide, during the process of removing the oxygen pad layer, the corners or boundaries of the shallow trench isolation structure are also prone to be etched, resulting in shallow trench isolation. Defects such as divots, holes, or sharp corners appear on local edges of the isolation structure. As a result, the isolation performance of the shallow trench isolation structure is affected, thereby affecting the electrical performance of the semiconductor structure, such as leakage current, narrow channel effect and other defects.
发明内容Contents of the invention
根据本公开的各种实施例，提供一种浅沟槽隔离结构及其制备方法、半导体结构。According to various embodiments of the present disclosure, a shallow trench isolation structure, a manufacturing method thereof, and a semiconductor structure are provided.
根据一些实施例，本公开一方面提供一种浅沟槽隔离结构的制备方法，包括如下步骤。According to some embodiments, the present disclosure provides a method for fabricating a shallow trench isolation structure, including the following steps.
提供衬底，在衬底的表面依次层叠形成垫氧层和硬掩膜层。A substrate is provided, and an oxygen pad layer and a hard mask layer are sequentially stacked on the surface of the substrate.
以图案化后的硬掩膜层为掩膜刻蚀垫氧层及衬底，以在垫氧层中形成开口，在衬底中形成沟槽。The pad oxide layer and the substrate are etched using the patterned hard mask layer as a mask to form openings in the pad oxide layer and grooves in the substrate.
在沟槽内形成衬底氧化层。A substrate oxide layer is formed within the trench.
形成第一阻挡层，第一阻挡层覆盖硬掩膜层和衬底氧化层。A first barrier layer is formed, and the first barrier layer covers the hard mask layer and the substrate oxide layer.
形成第一氧化层，第一氧化层覆盖第一阻挡层。A first oxide layer is formed, and the first oxide layer covers the first barrier layer.
去除硬掩膜层上表面的第一阻挡层和第一氧化层。The first barrier layer and the first oxide layer on the upper surface of the hard mask layer are removed.
去除衬底上表面的垫氧层和硬掩膜层以形成第二阻挡层。The oxygen pad layer and the hard mask layer on the upper surface of the substrate are removed to form a second barrier layer.
在一些实施例中，所述制备方法还包括如下步骤。In some embodiments, the preparation method further includes the following steps.
氧化第二阻挡层及衬底的部分表面以形成第二氧化层。Oxidizing the second barrier layer and part of the surface of the substrate to form a second oxide layer.
去除第二氧化层及部分衬底氧化层，以使保留于沟槽内的衬底氧化层形成浅沟槽隔离 结构。The second oxide layer and part of the substrate oxide layer are removed, so that the substrate oxide layer remaining in the trench forms a shallow trench isolation structure.
根据一些实施例，去除第二氧化层及部分衬底氧化层，包括：使用氢氟酸稀释溶液对形成第二氧化层后所得的结构进行清洗，以去除第二氧化层及部分衬底氧化层。According to some embodiments, removing the second oxide layer and part of the substrate oxide layer includes: cleaning the structure obtained after forming the second oxide layer with a dilute solution of hydrofluoric acid, so as to remove the second oxide layer and part of the substrate oxide layer .
根据一些实施例，在沟槽内形成衬底氧化层，包括如下步骤。According to some embodiments, forming a substrate oxide layer in the trench includes the following steps.
在沟槽、开口和硬掩膜层的图案内沉积氧化物。Oxide is deposited within the pattern of trenches, openings and hard mask layer.
去除位于开口和硬掩膜层的图案内的氧化物，以使保留于沟槽内的氧化物构成衬底氧化层。Oxide within the pattern of openings and hard mask layer is removed such that the oxide remaining within the trench constitutes a substrate oxide layer.
根据一些实施例，在沟槽内形成衬底氧化层，还包括：在沟槽、开口和硬掩膜层的图案内沉积氧化物之后，在去除位于开口和硬掩膜层的图案内的氧化物之前，采用化学机械研磨工艺抛光硬掩膜层及氧化物的裸露表面。According to some embodiments, forming the substrate oxide layer in the trench further includes: after depositing the oxide in the pattern of the trench, the opening and the hard mask layer, removing the oxide located in the pattern of the opening and the hard mask layer Before processing, the exposed surface of the hard mask layer and oxide is polished by a chemical mechanical polishing process.
根据一些实施例，去除硬掩膜层上表面的第一阻挡层和第一氧化层，去除衬底上表面的垫氧层和硬掩膜层以形成第二阻挡层，包括如下步骤。According to some embodiments, removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer, and removing the pad oxide layer and the hard mask layer on the upper surface of the substrate to form the second barrier layer include the following steps.
去除第一阻挡层和第一氧化层二者位于硬掩膜层上表面的部分，以形成中间阻挡层和中间氧化层。Portions of both the first barrier layer and the first oxide layer located on the upper surface of the hard mask layer are removed to form an intermediate barrier layer and an intermediate oxide layer.
去除硬掩膜层。Remove the hard mask layer.
去除垫氧层和中间氧化层，以使中间阻挡层形成第二阻挡层。The oxygen pad layer and the middle oxide layer are removed so that the middle barrier layer forms a second barrier layer.
根据一些实施例，采用化学机械研磨工艺，去除第一阻挡层和第一氧化层二者位于硬掩膜层上表面的部分，以形成中间阻挡层和中间氧化层。According to some embodiments, a chemical mechanical polishing process is used to remove portions of the first barrier layer and the first oxide layer located on the upper surface of the hard mask layer, so as to form the intermediate barrier layer and the intermediate oxide layer.
根据一些实施例，采用湿法刻蚀工艺，去除硬掩膜层。According to some embodiments, the hard mask layer is removed using a wet etching process.
根据一些实施例，采用湿法刻蚀工艺，去除垫氧层和中间氧化层。According to some embodiments, a wet etching process is used to remove the pad oxide layer and the intermediate oxide layer.
根据一些实施例，垫氧层和第一氧化层的材料相同。According to some embodiments, the materials of the oxygen pad layer and the first oxide layer are the same.
根据一些实施例，第一阻挡层的材料包括多晶硅。According to some embodiments, the material of the first barrier layer includes polysilicon.
根据一些实施例，第一阻挡层的厚度范围为1nm～3nm。According to some embodiments, the thickness of the first barrier layer ranges from 1 nm to 3 nm.
根据一些实施例，本公开另一方面提供了一种浅沟槽隔离结构，采用如上一些实施例所述的制备方法制备获得。According to some embodiments, another aspect of the present disclosure provides a shallow trench isolation structure, which is prepared by using the preparation method described in some embodiments above.
根据一些实施例，本公开又一方面提供了一种半导体结构，包括：衬底、多个晶体管以及如上一些实施例所述的浅沟槽隔离结构。其中，衬底具有沟槽。浅沟槽隔离结构设置于所述沟槽内，并在衬底内隔离出多个有源区。晶体管设置于对应的有源区内。According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, including: a substrate, a plurality of transistors, and the shallow trench isolation structure as described in some embodiments above. Wherein, the substrate has grooves. The shallow trench isolation structure is arranged in the trench and isolates a plurality of active regions in the substrate. The transistors are disposed in the corresponding active regions.
根据一些实施例，晶体管包括：金属氧化物半导体场效应晶体管。金属氧化物半导体场效应晶体管的栅极长度小于50nm。According to some embodiments, the transistor includes: a Metal Oxide Semiconductor Field Effect Transistor. The gate length of metal-oxide-semiconductor field-effect transistors is less than 50nm.
本公开实施例可以/至少具有以下优点：Embodiments of the present disclosure may/at least have the following advantages:
本公开实施例中，在形成垫氧层和硬掩膜层之后，以图案化后的硬掩膜层为掩膜对垫氧层及衬底进行刻蚀，可以在垫氧层中形成开口，在衬底中形成沟槽。之后，在沟槽内形成衬底氧化层，在衬底氧化层和硬掩膜层上形成第一阻挡层，在第一阻挡层上形成第一氧化层，便可以去除硬掩膜层上表面的第一阻挡层和第一氧化层，以保留衬底氧化层上表面 的第一阻挡层和第一氧化层。基于此，在后续去除衬底上表面的垫氧层和硬掩膜层之后，可以基于第一阻挡层形成第二阻挡层。例如，在去除垫氧层的过程中，可以将衬底氧化层上表面的第一氧化层与垫氧层同步去除，以使衬底氧化层上表面的第一阻挡层形成第二阻挡层。In the embodiment of the present disclosure, after forming the oxygen pad layer and the hard mask layer, the patterned hard mask layer is used as a mask to etch the oxygen pad layer and the substrate to form an opening in the oxygen pad layer, A trench is formed in the substrate. After that, a substrate oxide layer is formed in the trench, a first barrier layer is formed on the substrate oxide layer and the hard mask layer, and a first oxide layer is formed on the first barrier layer, so that the upper surface of the hard mask layer can be removed. the first barrier layer and the first oxide layer, so as to retain the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer. Based on this, after subsequent removal of the oxygen pad layer and the hard mask layer on the upper surface of the substrate, the second barrier layer may be formed based on the first barrier layer. For example, in the process of removing the oxide layer, the first oxide layer on the upper surface of the oxide layer of the substrate and the oxygen layer can be removed synchronously, so that the first barrier layer on the upper surface of the oxide layer of the substrate forms a second barrier layer.
可见，在去除垫氧层和硬掩膜层的过程中，可以利用衬底氧化层上表面的第一阻挡层和第一氧化层对衬底氧化层进行保护隔离。并且，在去除垫氧层和硬掩膜层之后，第二阻挡层覆盖衬底氧化层，可以有效避免衬底氧化层的边缘处因刻蚀液堆积而出现过刻的现象。从而能够避免由衬底氧化层形成的浅沟槽隔离结构出现凹陷(divot)、孔洞或尖角等缺陷。如此，可以获得成型表面质量较高的浅沟槽隔离结构，以确保浅沟槽隔离结构的边缘完整。It can be seen that in the process of removing the pad oxide layer and the hard mask layer, the substrate oxide layer can be protected and isolated by using the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer. Moreover, after removing the oxygen pad layer and the hard mask layer, the second barrier layer covers the substrate oxide layer, which can effectively avoid over-etching at the edge of the substrate oxide layer due to accumulation of etching solution. Therefore, defects such as divots, holes or sharp corners in the shallow trench isolation structure formed by the oxide layer of the substrate can be avoided. In this way, a shallow trench isolation structure with high molding surface quality can be obtained, so as to ensure the integrity of the edge of the shallow trench isolation structure.
此外，由于第二阻挡层覆盖于衬底氧化层的裸露表面，也即第二阻挡层会凸出于衬底的上表面。因此，可以对第二阻挡层进行氧化处理，以使得第二阻挡层及衬底的部分表面可以氧化转变为第二氧化层，然后再通过清洗氧化表面的方式去除，以确保获得具有平坦上表面的衬底。从而简化浅沟槽隔离结构的制备工艺，并进一步确保浅沟槽隔离结构具有较高的表面质量。In addition, since the second barrier layer covers the exposed surface of the oxide layer of the substrate, that is, the second barrier layer protrudes from the upper surface of the substrate. Therefore, the second barrier layer can be oxidized so that part of the surface of the second barrier layer and the substrate can be oxidized and transformed into a second oxide layer, and then removed by cleaning the oxidized surface to ensure that a flat upper surface is obtained. the substrate. Therefore, the preparation process of the shallow trench isolation structure is simplified, and the shallow trench isolation structure has a higher surface quality.
由上，本公开实施例可以确保浅沟槽隔离结构成型后的表面质量，以提高浅沟槽隔离结构的隔离性能，从而改善半导体结构的电学性能，以提高半导体结构的使用可靠性及良率。From the above, the embodiments of the present disclosure can ensure the surface quality of the shallow trench isolation structure after forming, so as to improve the isolation performance of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor structure, and improving the reliability and yield of the semiconductor structure .
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, drawings, and claims.
附图说明Description of drawings
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. Those of ordinary skill in the art can also obtain the drawings of other embodiments according to these drawings without any creative effort.
图1为一实施例中提供的一种浅沟槽隔离结构的制备方法的流程示意图；FIG. 1 is a schematic flowchart of a method for preparing a shallow trench isolation structure provided in an embodiment;
图2为一实施例中提供的形成垫氧层和硬掩膜层后所得结构的剖面示意图；2 is a schematic cross-sectional view of the structure obtained after forming an oxygen pad layer and a hard mask layer provided in an embodiment;
图3为一实施例中提供的形成光刻胶层后所得结构的剖面示意图；3 is a schematic cross-sectional view of a structure obtained after forming a photoresist layer provided in an embodiment;
图4为一实施例中提供的形成图案化的硬掩膜层后所得结构的剖面示意图；4 is a schematic cross-sectional view of a structure obtained after forming a patterned hard mask layer provided in an embodiment;
图5为一实施例中提供的形成沟槽后所得结构的剖面示意图；FIG. 5 is a schematic cross-sectional view of a structure obtained after forming trenches provided in an embodiment;
图6为一实施例中提供的步骤S300的流程示意图；FIG. 6 is a schematic flowchart of step S300 provided in an embodiment;
图7为一实施例中提供的在沟槽、开口及硬掩膜层的图案内沉积氧化物后所得结构的剖面示意图；7 is a schematic cross-sectional view of a structure obtained after depositing an oxide in the pattern of trenches, openings, and a hard mask layer provided in an embodiment;
图8为一实施例中提供的形成衬底氧化层后所得结构的剖面示意图；8 is a schematic cross-sectional view of a structure obtained after forming a substrate oxide layer provided in an embodiment;
图9为另一实施例中提供的步骤S300的流程示意图；FIG. 9 is a schematic flowchart of step S300 provided in another embodiment;
图10为一实施例中提供的形成第一阻挡层后所得结构的剖面示意图；FIG. 10 is a schematic cross-sectional view of a structure obtained after forming a first barrier layer provided in an embodiment;
图11为一实施例中提供的形成第一氧化层后所得结构的剖面示意图；11 is a schematic cross-sectional view of a structure obtained after forming a first oxide layer provided in an embodiment;
图12为一实施例中提供的步骤S600的流程示意图；FIG. 12 is a schematic flowchart of step S600 provided in an embodiment;
图13为一实施例中提供的形成中间阻挡层及第一中间氧化层后所得结构的剖面示意图；13 is a schematic cross-sectional view of a structure obtained after forming an intermediate barrier layer and a first intermediate oxide layer provided in an embodiment;
图14为一实施例中提供的形成第二阻挡层及第二中间氧化层后所得结构的剖面示意图；14 is a schematic cross-sectional view of a structure obtained after forming a second barrier layer and a second intermediate oxide layer provided in an embodiment;
图15为一实施例中提供的去除垫氧层后所得结构的剖面示意图；Fig. 15 is a schematic cross-sectional view of the structure obtained after removing the oxygen pad layer provided in an embodiment;
图16为另一实施例中提供的一种浅沟槽隔离结构的制备方法的流程示意图；FIG. 16 is a schematic flowchart of a method for manufacturing a shallow trench isolation structure provided in another embodiment;
图17为一实施例中提供的形成第二氧化层后所得结构的剖面示意图；17 is a schematic cross-sectional view of a structure obtained after forming a second oxide layer provided in an embodiment;
图18为一实施例中提供的形成浅沟槽隔离结构后所得结构的剖面示意图；FIG. 18 is a schematic cross-sectional view of a structure obtained after forming a shallow trench isolation structure provided in an embodiment;
图19为一实施例中提供的一种半导体结构的示意图。FIG. 19 is a schematic diagram of a semiconductor structure provided in an embodiment.
具体实施方式Detailed ways
为了便于理解本公开，下面将参考相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the description of the present disclosure are for the purpose of describing specific embodiments only, and are not intended to limit the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
应当明白，当元件或层被称为“在...上”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer. or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not indicative of the actual shape of a region of a device and are not intended to limit the scope of the disclosure.
请参阅图1，本公开一些实施例提供了一种浅沟槽隔离结构的制备方法，包括如下步骤。Referring to FIG. 1 , some embodiments of the present disclosure provide a method for fabricating a shallow trench isolation structure, including the following steps.
S100，提供衬底，在衬底的表面依次层叠形成垫氧层和硬掩膜层。S100, a substrate is provided, and an oxygen pad layer and a hard mask layer are sequentially stacked on the surface of the substrate.
S200，以图案化后的硬掩膜层为掩膜刻蚀垫氧层及衬底，以在垫氧层中形成开口，在衬底中形成沟槽。S200, using the patterned hard mask layer as a mask to etch the pad oxide layer and the substrate, so as to form openings in the pad oxide layer and form trenches in the substrate.
S300，在沟槽内形成衬底氧化层。S300, forming a substrate oxide layer in the trench.
S400，形成第一阻挡层，第一阻挡层覆盖硬掩膜层和衬底氧化层。S400, forming a first barrier layer, where the first barrier layer covers the hard mask layer and the substrate oxide layer.
S500，形成第一氧化层，第一氧化层覆盖第一阻挡层。S500, forming a first oxide layer, where the first oxide layer covers the first barrier layer.
S600，去除硬掩膜层上表面的第一阻挡层和第一氧化层，去除衬底上表面的垫氧层和硬掩膜层以形成第二阻挡层。S600, removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer, and removing the pad oxide layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer.
本公开实施例中，在形成垫氧层和硬掩膜层之后，以图案化后的硬掩膜层为掩膜对垫氧层及衬底进行刻蚀，可以在垫氧层中形成开口，在衬底中形成沟槽。之后，在沟槽内形成衬底氧化层，在衬底氧化层和硬掩膜层上形成第一阻挡层，在第一阻挡层上形成第一氧化层，便可以去除硬掩膜层上表面的第一阻挡层和第一氧化层，以保留衬底氧化层上表面的第一阻挡层和第一氧化层。基于此，在后续去除衬底上表面的垫氧层和硬掩膜层之后，可以基于第一阻挡层形成第二阻挡层。In the embodiment of the present disclosure, after forming the oxygen pad layer and the hard mask layer, the patterned hard mask layer is used as a mask to etch the oxygen pad layer and the substrate to form an opening in the oxygen pad layer, A trench is formed in the substrate. After that, a substrate oxide layer is formed in the trench, a first barrier layer is formed on the substrate oxide layer and the hard mask layer, and a first oxide layer is formed on the first barrier layer, so that the upper surface of the hard mask layer can be removed. the first barrier layer and the first oxide layer, so as to retain the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer. Based on this, after subsequent removal of the oxygen pad layer and the hard mask layer on the upper surface of the substrate, the second barrier layer may be formed based on the first barrier layer.
可见，在去除垫氧层和硬掩膜层的过程中，可以利用衬底氧化层上表面的第一阻挡层和第一氧化层对衬底氧化层进行保护隔离。并且，在去除垫氧层和硬掩膜层之后，形成于衬底氧化层上的第二阻挡层覆盖衬底氧化层，可以有效避免衬底氧化层的边缘处因刻蚀液堆积而造成过刻。从而能够避免由衬底氧化层形成的浅沟槽隔离结构出现凹陷(divot)、孔洞或尖角等缺陷。如此，可以获得成型表面质量较高的浅沟槽隔离结构，以确保浅沟槽隔离结构的边缘完整。It can be seen that in the process of removing the pad oxide layer and the hard mask layer, the substrate oxide layer can be protected and isolated by using the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer. Moreover, after removing the pad oxide layer and the hard mask layer, the second barrier layer formed on the substrate oxide layer covers the substrate oxide layer, which can effectively avoid excessive corrosion caused by accumulation of etching solution at the edge of the substrate oxide layer. carve. Therefore, defects such as divots, holes or sharp corners in the shallow trench isolation structure formed by the oxide layer of the substrate can be avoided. In this way, a shallow trench isolation structure with high molding surface quality can be obtained, so as to ensure the integrity of the edge of the shallow trench isolation structure.
此外，第二阻挡层覆盖于衬底氧化层的裸露表面，也即第二阻挡层会凸出于衬底的上表面。这样方便于对第二阻挡层进行氧化处理，以使得第二阻挡层及衬底的部分表面氧化 转变为第二氧化层，然后再通过清洗氧化表面的方式去除，以确保获得具有平坦上表面的衬底。从而简化浅沟槽隔离结构的制备工艺，并进一步确保浅沟槽隔离结构具有较高的表面质量。In addition, the second barrier layer covers the exposed surface of the oxide layer of the substrate, that is, the second barrier layer protrudes from the upper surface of the substrate. This facilitates the oxidation treatment of the second barrier layer, so that part of the surface of the second barrier layer and the substrate is oxidized and transformed into a second oxide layer, and then removed by cleaning the oxidized surface to ensure that a flat upper surface is obtained. substrate. Therefore, the preparation process of the shallow trench isolation structure is simplified, and the shallow trench isolation structure has a higher surface quality.
由上，本公开实施例可以确保浅沟槽隔离结构成型后的表面质量，以提高浅沟槽隔离结构的隔离性能，从而改善半导体结构的电学性能，以提高半导体结构的使用可靠性及良率。From the above, the embodiments of the present disclosure can ensure the surface quality of the shallow trench isolation structure after forming, so as to improve the isolation performance of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor structure, and improving the reliability and yield of the semiconductor structure .
在步骤S100中，请参阅图1中的S100及图2，提供衬底10，在衬底10的表面依次层叠形成垫氧层11和硬掩膜层12。In step S100 , referring to S100 in FIG. 1 and FIG. 2 , a substrate 10 is provided, and an oxygen pad layer 11 and a hard mask layer 12 are sequentially stacked on the surface of the substrate 10 .
在一些实施例中，衬底10可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底10可以为单层结构，也可以为多层结构。例如，衬底10可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底10可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。In some embodiments, the substrate 10 may be made of semiconductor material, insulating material, conductive material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic An indium (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrates or II/VI semiconductor substrates. Alternatively, also for example, the substrate 10 may be a layered substrate including, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
在一个示例中，衬底10包括但不限于硅衬底或硅基衬底。In one example, the substrate 10 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
在一个示例中，垫氧层(Pad Oxide)11包括但不限于二氧化硅(SiO 2)层。 In one example, the pad oxide layer (Pad Oxide) 11 includes but not limited to a silicon dioxide (SiO 2 ) layer.
在一些实施例中，垫氧层11作为硬掩膜层12和衬底10之间的过渡缓冲层，可以采用低压化学气相沉积(LPCVD)、等离子增强化学气相沉积(PECVD)或原子层化学气相沉积(ALCVD)等工艺形成。In some embodiments, the oxygen pad layer 11 is used as a transitional buffer layer between the hard mask layer 12 and the substrate 10, and low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD) or atomic layer chemical vapor deposition can be used. Deposition (ALCVD) and other processes are formed.
在一个示例中，硬掩膜层12包括但不限于氮化硅层。例如硬掩膜层12也可以为氮氧化硅层。In one example, hard mask layer 12 includes, but is not limited to, a silicon nitride layer. For example, the hard mask layer 12 may also be a silicon oxynitride layer.
在一些实施例中，硬掩膜层12作为后续衬底10上沟槽的掩膜，可以采用高密度等离子体化学气相淀积(HDPCVD)或等离子增强化学气相沉积(PECVD)等工艺形成，并通过构图工艺图案化。In some embodiments, the hard mask layer 12 is used as a mask for trenches on the subsequent substrate 10, and can be formed by processes such as high-density plasma chemical vapor deposition (HDPCVD) or plasma-enhanced chemical vapor deposition (PECVD), and Patterned by patterning process.
示例的，如图3所示，在硬掩膜层12上表面涂覆光刻胶材料并进行曝光、显影等光刻工艺，以形成可以定义沟槽位置且具有开口的光刻胶图形20。如此，可以基于光刻胶图形20，例如采用反应离子刻蚀或等离子刻蚀硬掩膜层12，以形成图案化的硬掩膜层12，例如图4中所示。Exemplarily, as shown in FIG. 3 , a photoresist material is coated on the surface of the hard mask layer 12 and photolithography processes such as exposure and development are performed to form a photoresist pattern 20 that can define trench positions and have openings. In this way, the hard mask layer 12 can be etched based on the photoresist pattern 20 , for example, by reactive ion etching or plasma etching, to form a patterned hard mask layer 12 , such as shown in FIG. 4 .
在步骤S200中，请参阅图1中的S200及图4、图5，以图案化后的硬掩膜层12为掩膜刻蚀垫氧层11及衬底10，以在垫氧层11中形成开口K，在衬底10中形成沟槽G。In step S200, referring to S200 in FIG. 1 and FIG. 4 and FIG. 5 , the patterned hard mask layer 12 is used as a mask to etch the pad oxide layer 11 and the substrate 10, so that the pad oxide layer 11 An opening K is formed, and a trench G is formed in the substrate 10 .
可以理解，步骤S200中垫氧层11及衬底10的刻蚀包括湿法刻蚀或干法刻蚀，其中，干法刻蚀至少包括反应离子刻蚀(RIE)、感应耦合等离子体刻蚀(ICP)或高浓度等离子体刻蚀(HDP)中的任意一种。本公开实施例中，垫氧层11及衬底10的刻蚀方法可以相同，也可以不同。It can be understood that the etching of the oxygen pad layer 11 and the substrate 10 in step S200 includes wet etching or dry etching, wherein the dry etching includes at least reactive ion etching (RIE), inductively coupled plasma etching Either one of (ICP) or high-density plasma etching (HDP). In the embodiments of the present disclosure, the etching methods of the oxygen pad layer 11 and the substrate 10 may be the same or different.
在一些实施例中，垫氧层11可以采用反应离子刻蚀或等离子刻蚀。In some embodiments, the oxygen pad layer 11 can be etched by reactive ion etching or plasma etching.
在一些实施例中，衬底10可以采用含氟刻蚀气体刻蚀，或采用氢氟酸溶液进行湿法刻蚀。In some embodiments, the substrate 10 can be etched with fluorine-containing etching gas, or wet-etched with hydrofluoric acid solution.
此外，上述开口K及沟槽G的数量及形成位置，可以根据对应待隔离的有源区选择设置。本公开实施例对此不做限定。In addition, the number and formation positions of the above-mentioned openings K and trenches G can be selected and set according to the corresponding active regions to be isolated. Embodiments of the present disclosure do not limit this.
在步骤S300中，请参阅图1中的S300以及图6～图9，在沟槽G内形成衬底氧化层13。In step S300 , referring to S300 in FIG. 1 and FIGS. 6 to 9 , a substrate oxide layer 13 is formed in the trench G. Referring to FIG.
示例的，如图6和图7、图8所示，步骤S300包括如下步骤。Exemplarily, as shown in FIG. 6 , FIG. 7 , and FIG. 8 , step S300 includes the following steps.
S310，在沟槽G、开口K和硬掩膜层12的图案内沉积氧化物130。S310 , deposit an oxide 130 in the pattern of the trench G, the opening K and the hard mask layer 12 .
在一个示例中，氧化物130包括但不限于二氧化硅(SiO 2)。 In one example, oxide 130 includes, but is not limited to, silicon dioxide (SiO 2 ).
在一些实施例中，氧化物130可以采用高密度等离子体化学气相淀积(HDP-CVD)等工艺沉积。In some embodiments, the oxide 130 may be deposited by high density plasma chemical vapor deposition (HDP-CVD) or other processes.
S320，去除位于开口K和硬掩膜层12的图案内的氧化物130，以使保留于沟槽G内的氧化物130构成衬底氧化层(Liner Oxide)13。S320, removing the oxide 130 located in the pattern of the opening K and the hard mask layer 12, so that the oxide 130 remaining in the trench G forms a substrate oxide layer (Liner Oxide) 13.
本公开实施例中，采取在沟槽G、开口K和硬掩膜层12的图案内先沉积氧化物130，再去除位于开口K和硬掩膜层12的图案内的氧化物130的方式，形成衬底氧化层13。如此，可以提升衬底氧化层13的材料致密性，并有利于确保衬底氧化层13的形成表面与衬底10上表面平齐。In the embodiment of the present disclosure, the oxide 130 is first deposited in the pattern of the trench G, the opening K and the hard mask layer 12, and then the oxide 130 located in the pattern of the opening K and the hard mask layer 12 is removed. A substrate oxide layer 13 is formed. In this way, the material density of the substrate oxide layer 13 can be improved, and it is beneficial to ensure that the formation surface of the substrate oxide layer 13 is flush with the upper surface of the substrate 10 .
在一些实施例中，请参阅图7、图8和图9，在沟槽G、开口K和硬掩膜层12的图案内沉积氧化物130之后，在去除位于开口K和硬掩膜层12的图案内的氧化物130之前，步骤S300还包括如下步骤。In some embodiments, referring to FIG. 7 , FIG. 8 and FIG. 9 , after depositing the oxide 130 in the pattern of the trench G, the opening K and the hard mask layer 12 , after removing the Before the oxide 130 in the pattern, step S300 further includes the following steps.
S315，采用化学机械研磨工艺，抛光硬掩膜层12及氧化物130的裸露表面。S315 , polishing the exposed surfaces of the hard mask layer 12 and the oxide 130 by using a chemical mechanical polishing process.
如此，可以确保硬掩膜层12及氧化物130的裸露表面平齐且平坦，以利于实现后续氧化物130的精确刻蚀，例如刻蚀至与衬底10上表面平齐。In this way, the exposed surfaces of the hard mask layer 12 and the oxide 130 can be guaranteed to be even and planar, so as to facilitate the subsequent precise etching of the oxide 130 , for example, to be etched to be flush with the upper surface of the substrate 10 .
在步骤S400中，请参阅图1中的S400及图10，形成第一阻挡层14，第一阻挡层14覆盖硬掩膜层12和衬底氧化层13。In step S400 , referring to S400 in FIG. 1 and FIG. 10 , a first barrier layer 14 is formed, and the first barrier layer 14 covers the hard mask layer 12 and the substrate oxide layer 13 .
可以理解，在形成衬底氧化层13后，衬底氧化层13上表面与衬底10上表面可以位于同一平面。如此，在形成第一阻挡层14后，第一阻挡层14覆盖衬底氧化层13的部分位于垫氧层11的开口K及硬掩膜层12的图案内。It can be understood that after the substrate oxide layer 13 is formed, the upper surface of the substrate oxide layer 13 and the upper surface of the substrate 10 may be located on the same plane. In this way, after the first barrier layer 14 is formed, the portion of the first barrier layer 14 covering the substrate oxide layer 13 is located within the pattern of the opening K of the oxygen pad layer 11 and the hard mask layer 12 .
在一些实施例中，第一阻挡层14的材料包括多晶硅。如此，方便于在后续基于第一阻挡层14形成第二阻挡层16后，对第二阻挡层16执行氧化处理，并通过去除氧化表面的方式去除，从而简化浅沟槽隔离结构的制备工艺，并确保浅沟槽隔离结构成型后的表面质量。In some embodiments, the material of the first barrier layer 14 includes polysilicon. In this way, after the subsequent formation of the second barrier layer 16 based on the first barrier layer 14, it is convenient to perform oxidation treatment on the second barrier layer 16 and remove it by removing the oxidized surface, thereby simplifying the preparation process of the shallow trench isolation structure, And ensure the surface quality of the shallow trench isolation structure after molding.
在一些实施例中，第一阻挡层14的厚度可以实际需求选择设置。例如，第一阻挡层14的厚度的取值范围为1nm～3nm，例如可以为1nm、2nm或3nm。但并不仅限于此。In some embodiments, the thickness of the first barrier layer 14 can be set according to actual needs. For example, the thickness of the first barrier layer 14 ranges from 1 nm to 3 nm, such as 1 nm, 2 nm or 3 nm. But it doesn't stop there.
此处，若第一阻挡层14的厚度较薄，则容易导致第一阻挡层14的结构不稳定，例如 难以稳定成型，不利于在经由多次刻蚀后基于第一阻挡层14形成具有预设形状的第二阻挡层16。并且，若第一阻挡层14的厚度较厚，则后期基于第一阻挡层14所形成的第二阻挡层16在进行氧化处理时，需要耗费较多的时间，不利于提高生产效率。Here, if the thickness of the first barrier layer 14 is relatively thin, the structure of the first barrier layer 14 is likely to be unstable, for example, it is difficult to form stably, which is not conducive to the formation of the first barrier layer 14 after multiple etchings. The shape of the second barrier layer 16 is set. Moreover, if the thickness of the first barrier layer 14 is relatively thick, it will take more time to oxidize the second barrier layer 16 formed based on the first barrier layer 14 later, which is not conducive to improving production efficiency.
因此，本公开实施例中，将第一阻挡层14厚度的取值范围设置在1nm～3nm，可以使第一阻挡层14的成型表面存在因垫氧层11开口K及硬掩膜层12图案造成的凹面(即第一阻挡层14具有因垫氧层11开口K及硬掩膜层12图案造成的凹陷)，以便于后续可以形成具有U形结构的第二阻挡层16。并且，还方便于对第一阻挡层14进行部分去除以形成第二阻挡层16，以及对第二阻挡层16进行氧化处理，从而有利于提高生产效率。Therefore, in the embodiment of the present disclosure, setting the value range of the thickness of the first barrier layer 14 at 1 nm to 3 nm can make the forming surface of the first barrier layer 14 exist due to the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12 The resulting concave surface (that is, the first barrier layer 14 has a depression caused by the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12 ) facilitates subsequent formation of the second barrier layer 16 with a U-shaped structure. Moreover, it is also convenient to partially remove the first barrier layer 14 to form the second barrier layer 16, and to perform oxidation treatment on the second barrier layer 16, which is beneficial to improve production efficiency.
在步骤S500中，请参阅图1中的S500及图11，形成第一氧化层15，第一氧化层15覆盖第一阻挡层14。In step S500 , referring to S500 in FIG. 1 and FIG. 11 , a first oxide layer 15 is formed, and the first oxide layer 15 covers the first barrier layer 14 .
此处，在形成第一氧化层15之后，可以利用第一氧化层15的部分材料填平第一阻挡层14因垫氧层11开口K及硬掩膜层12图案形成的凹陷。Here, after the formation of the first oxide layer 15 , part of the material of the first oxide layer 15 can be used to fill up the depression formed by the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12 in the first barrier layer 14 .
在一些实施例中，第一氧化层15和垫氧层11的材料相同，例如均为二氧化硅。如此，方便于采用相同工艺去除垫氧层11和第一氧化层15，以简化浅沟槽隔离结构的制备工艺。In some embodiments, the first oxide layer 15 and the oxygen pad layer 11 are made of the same material, such as silicon dioxide. In this way, it is convenient to use the same process to remove the pad oxide layer 11 and the first oxide layer 15, so as to simplify the manufacturing process of the shallow trench isolation structure.
在步骤S600中，请参阅图1中的S600及图12～图15，去除硬掩膜层12上表面的第一阻挡层14和第一氧化层15，去除衬底10上表面的垫氧层11和硬掩膜层12以形成第二阻挡层16。In step S600, referring to S600 in FIG. 1 and FIGS. 12 to 15, the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12 are removed, and the oxygen pad layer on the upper surface of the substrate 10 is removed. 11 and hard mask layer 12 to form a second barrier layer 16 .
示例的，请参阅图12～图15，步骤S600包括如下步骤。For example, please refer to FIG. 12 to FIG. 15 , step S600 includes the following steps.
S610，如图13中所示，去除第一阻挡层14和第一氧化层15二者位于硬掩膜层12上表面的部分，以形成中间阻挡层14'和中间氧化层15'。S610 , as shown in FIG. 13 , removing portions of the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12 to form an intermediate barrier layer 14 ′ and an intermediate oxide layer 15 ′.
在一些实施例中，可以采用化学机械研磨工艺，去除第一阻挡层14和第一氧化层15二者位于硬掩膜层12上表面的部分，以形成中间阻挡层14'和中间氧化层15'，并确保中间阻挡层14'和中间氧化层15'的上表面位于同一平面。In some embodiments, a chemical mechanical polishing process can be used to remove the parts of the first barrier layer 14 and the first oxide layer 15 located on the upper surface of the hard mask layer 12, so as to form the intermediate barrier layer 14' and the intermediate oxide layer 15. ', and ensure that the upper surfaces of the middle barrier layer 14' and the middle oxide layer 15' are on the same plane.
此处，化学机械研磨工艺所使用的研磨液及研磨时间，均可以根据实际需求选择设置，本公开实施例对此不做限定。Here, the polishing liquid and the polishing time used in the chemical mechanical polishing process can be selected and set according to actual needs, which is not limited in the embodiments of the present disclosure.
S620，如图14中所示，去除硬掩膜层12。S620, as shown in FIG. 14 , removing the hard mask layer 12 .
在一些实施例中，采用湿法刻蚀工艺去除硬掩膜层12。In some embodiments, the hard mask layer 12 is removed by a wet etching process.
例如，采用热磷酸溶液对硬掩膜层12进行湿法刻蚀，热磷酸溶液的温度可以为150℃～170℃。For example, the hard mask layer 12 is wet-etched using a hot phosphoric acid solution, and the temperature of the hot phosphoric acid solution may be 150° C.˜170° C.
可以理解，在去除硬掩膜层12之后，还可以执行第一纯水清洗工艺，以去除残留的热磷酸。由于热磷酸的温度太高，若将衬底10直接放入常温水槽清洗，容易存在破片的风险。因此，该第一纯水清洗工艺的温度可以为50℃～70℃。It can be understood that after removing the hard mask layer 12 , a first pure water cleaning process may also be performed to remove residual hot phosphoric acid. Since the temperature of hot phosphoric acid is too high, if the substrate 10 is directly placed in a normal temperature water tank for cleaning, there is a risk of fragmentation. Therefore, the temperature of the first pure water cleaning process may be 50°C-70°C.
S630，如图15中所示，去除垫氧层11和中间氧化层15'，以使中间阻挡层14'形成第二阻挡层16。S630, as shown in FIG. 15 , removing the oxygen pad layer 11 and the intermediate oxide layer 15 ′, so that the intermediate barrier layer 14 ′ forms the second barrier layer 16 .
在一些实施例中，采用湿法刻蚀工艺，去除垫氧层11和中间氧化层15'。In some embodiments, a wet etching process is used to remove the pad oxide layer 11 and the middle oxide layer 15 ′.
例如，采用氢氟酸对垫氧层11和中间氧化层15'进行刻蚀。For example, hydrofluoric acid is used to etch the pad oxide layer 11 and the middle oxide layer 15 ′.
本公开实施例中，在形成第一氧化层15之后，可以利用第一氧化层15的部分材料填平第一阻挡层14中因垫氧层11开口K及硬掩膜层12图案形成的凹陷。如此，在去除第一阻挡层14和第一氧化层15二者位于硬掩膜层12上表面的部分之后，中间阻挡层14'呈U型薄壁结构，中间氧化层15'填平中间阻挡层14'，可以对中间阻挡层14'进行支撑，从而有利于在后续去除硬掩膜层12、垫氧层11及中间氧化层15'的过程中，确保中间阻挡层14'的结构稳定。In the embodiment of the present disclosure, after the first oxide layer 15 is formed, part of the material of the first oxide layer 15 can be used to fill up the depression formed by the opening K of the oxygen pad layer 11 and the pattern of the hard mask layer 12 in the first barrier layer 14 . In this way, after the parts of the first barrier layer 14 and the first oxide layer 15 located on the upper surface of the hard mask layer 12 are removed, the intermediate barrier layer 14' has a U-shaped thin-walled structure, and the intermediate oxide layer 15' fills up the intermediate barrier layer. The layer 14' can support the intermediate barrier layer 14', so as to ensure the stability of the structure of the intermediate barrier layer 14' during the subsequent removal of the hard mask layer 12, the oxygen pad layer 11 and the intermediate oxide layer 15'.
需要说明的是，第二阻挡层16还可以采用其他的方式形成。例如，首先去除第一阻挡层14和第一氧化层15二者位于硬掩膜层12上表面的部分，以形成中间阻挡层14'和第一中间氧化层15'；然后，去除硬掩膜层12，以及中间阻挡层14'和第一中间氧化层15'二者凸出于垫氧层11上表面的部分，以形成第二阻挡层16和第二中间氧化层；最后再去除垫氧层11和第二中间氧化层。但并不仅限于此，以形成的第二阻挡层16能够有效隔离衬底氧化层13为限。It should be noted that the second barrier layer 16 can also be formed in other ways. For example, first remove the first barrier layer 14 and the first oxide layer 15 both on the upper surface of the hard mask layer 12, to form the intermediate barrier layer 14' and the first intermediate oxide layer 15'; then, remove the hard mask Layer 12, and the part of the intermediate barrier layer 14' and the first intermediate oxide layer 15' protruding from the upper surface of the oxygen pad layer 11 to form the second barrier layer 16 and the second intermediate oxide layer; finally remove the oxygen pad layer layer 11 and the second intermediate oxide layer. But it is not limited thereto, as long as the formed second barrier layer 16 can effectively isolate the substrate oxide layer 13 .
此外，在一些实施例中，上述各层结构的去除也可以采用干法刻蚀工艺实现。In addition, in some embodiments, the removal of the above-mentioned layer structures may also be implemented by a dry etching process.
值得一提的是，在一些实施例中，请参阅图16，浅沟槽隔离结构的制备方法还包括如下步骤。It is worth mentioning that, in some embodiments, please refer to FIG. 16 , the manufacturing method of the shallow trench isolation structure further includes the following steps.
S700，氧化第二阻挡层及衬底的部分表面以形成第二氧化层。S700, oxidize the second barrier layer and part of the surface of the substrate to form a second oxide layer.
S800，去除第二氧化层及部分衬底氧化层，以使保留于沟槽内的衬底氧化层形成浅沟槽隔离结构。S800, removing the second oxide layer and part of the substrate oxide layer, so that the substrate oxide layer remaining in the trench forms a shallow trench isolation structure.
本公开实施例中，在去除垫氧层的过程中，可以将衬底氧化层上表面的第一氧化层与垫氧层同步去除，以使衬底氧化层上表面的第一阻挡层形成第二阻挡层。基于此，在对第二阻挡层及衬底的部分表面进行氧化处理后，第二阻挡层及衬底的部分表面氧化转变为第二氧化层，这样便可以通过清洗氧化表面的方式去除第二氧化层，从而简化浅沟槽隔离结构的制备工艺，并进一步确保浅沟槽隔离结构具有较高的表面质量。进而能够进一步提高浅沟槽隔离结构的隔离性能，以进一步改善半导体结构的电学性能，有效提升半导体结构的使用可靠性及良率。In the embodiment of the present disclosure, in the process of removing the oxygen pad layer, the first oxide layer on the upper surface of the oxide layer of the substrate and the oxygen pad layer can be removed synchronously, so that the first barrier layer on the upper surface of the oxide layer of the substrate forms the first barrier layer. Two barrier layers. Based on this, after oxidizing the surface of the second barrier layer and part of the substrate, the surface of the second barrier layer and part of the substrate is oxidized and transformed into a second oxide layer, so that the second oxide layer can be removed by cleaning the oxidized surface. The oxide layer, thereby simplifying the preparation process of the shallow trench isolation structure, and further ensuring that the shallow trench isolation structure has a higher surface quality. Furthermore, the isolation performance of the shallow trench isolation structure can be further improved, so as to further improve the electrical performance of the semiconductor structure, and effectively improve the reliability and yield of the semiconductor structure.
在步骤S700中，请参阅图16中的S700及图17，氧化第二阻挡层16及衬底10的部分表面，以形成第二氧化层17。In step S700 , referring to S700 in FIG. 16 and FIG. 17 , the second barrier layer 16 and part of the surface of the substrate 10 are oxidized to form a second oxide layer 17 .
在一些实施例中，将形成第二阻挡层16后的所得结构放置于氧化环境中，例如向形成第二阻挡层16后的所得结构通入氧化剂气流，并将所得结构放置于高温环境中，以使得第二阻挡层16及衬底10部分表面的材料由多晶硅或硅转化为氧化硅。高温环境的温度可以根据实际需求选择设置，衬底10被氧化材料的厚度可以根据实际需求选择设置。本公开实施例对此均不做限定。In some embodiments, the resulting structure after forming the second barrier layer 16 is placed in an oxidizing environment, for example, an oxidant gas flow is passed through the resulting structure after forming the second barrier layer 16, and the resulting structure is placed in a high-temperature environment, So that the material of the second barrier layer 16 and part of the surface of the substrate 10 is converted from polysilicon or silicon to silicon oxide. The temperature of the high-temperature environment can be selected and set according to actual needs, and the thickness of the oxidized material of the substrate 10 can be selected and set according to actual needs. The embodiments of the present disclosure do not limit this.
此外，可以理解，在氧化第二阻挡层16及衬底10的部分表面，以形成第二氧化层17之前，还可以执行SC1清洗工艺，以去除衬底上的杂质。其中，SC1清洗工艺的清洗 液包括氨水、双氧水和水，且氨水：双氧水：水的体积比例如为1:2:100～1:2:10。示例地，氨水浓度例如是27％，双氧水例如是30％。SC1清洗液的温度例如为20℃～50℃。SC1清洗液的清洗时间例如为0.5min～10min。并且，在执行SC1清洗工艺之后，还可以视情况执行第二纯水清洗工艺，以去除衬底10上残留的SC1溶液。该第二纯水清洗工艺的温度例如为20℃～30℃。In addition, it can be understood that before oxidizing the second barrier layer 16 and part of the surface of the substrate 10 to form the second oxide layer 17 , an SC1 cleaning process may be performed to remove impurities on the substrate. Wherein, the cleaning solution of the SC1 cleaning process includes ammonia water, hydrogen peroxide and water, and the volume ratio of ammonia water: hydrogen peroxide water: water is, for example, 1:2:100˜1:2:10. Exemplarily, the concentration of ammonia water is, for example, 27%, and the concentration of hydrogen peroxide is, for example, 30%. The temperature of the SC1 cleaning solution is, for example, 20°C to 50°C. The cleaning time of the SC1 cleaning solution is, for example, 0.5 min to 10 min. Moreover, after performing the SC1 cleaning process, a second pure water cleaning process may also be performed as appropriate to remove the remaining SC1 solution on the substrate 10 . The temperature of the second pure water cleaning process is, for example, 20°C˜30°C.
在步骤S800中，请参阅图16中的S800及图18，去除第二氧化层17及部分衬底氧化层13，以使保留于沟槽G内的衬底氧化层形成浅沟槽隔离结构18。In step S800, referring to S800 in FIG. 16 and FIG. 18, the second oxide layer 17 and part of the substrate oxide layer 13 are removed, so that the substrate oxide layer remaining in the trench G forms a shallow trench isolation structure 18. .
在一些实施例中，去除第二氧化层17及部分衬底氧化层13，包括：使用氢氟酸稀释溶液对形成第二氧化层17后所得的结构进行清洗，以去除第二氧化层17及部分衬底氧化层13。In some embodiments, removing the second oxide layer 17 and part of the substrate oxide layer 13 includes: cleaning the structure obtained after the formation of the second oxide layer 17 with a dilute hydrofluoric acid solution to remove the second oxide layer 17 and Part of the substrate oxide layer 13.
此处，氢氟酸稀释溶液中，氢氟酸和水的体积比例如为1:100至1:500。氢氟酸稀释溶液的温度例如为15℃～30℃。使用氢氟酸稀释溶液对形成第二氧化层17后所得的结构进行清洗，可以视为是采用湿法刻蚀工艺去除第二氧化层17及部分衬底氧化层13。Here, in the diluted hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water is, for example, 1:100 to 1:500. The temperature of the diluted hydrofluoric acid solution is, for example, 15°C to 30°C. Using a diluted solution of hydrofluoric acid to clean the structure obtained after forming the second oxide layer 17 can be regarded as removing the second oxide layer 17 and part of the substrate oxide layer 13 by using a wet etching process.
请参阅图18，本公开一些实施例还提供了一种浅沟槽隔离结构18，采用如上一些实施例所述的制备方法制备获得。Please refer to FIG. 18 , some embodiments of the present disclosure also provide a shallow trench isolation structure 18 , which is prepared by using the preparation method described in some embodiments above.
请参阅图19，本公开一些实施例还提供了一种半导体结构，包括：衬底10、多个晶体管20以及如上一些实施例所述的浅沟槽隔离结构18。其中，衬底10具有沟槽G。浅沟槽隔离结构18设置于所述沟槽G内，并在衬底10内隔离出多个有源区S。晶体管20设置于对应的有源区S内。Referring to FIG. 19 , some embodiments of the present disclosure further provide a semiconductor structure, including: a substrate 10 , a plurality of transistors 20 , and the shallow trench isolation structure 18 as described in some embodiments above. Wherein, the substrate 10 has a groove G. The shallow trench isolation structure 18 is disposed in the trench G and isolates a plurality of active regions S in the substrate 10 . The transistor 20 is disposed in the corresponding active region S.
在一些实施例中，多个有源区S可以呈阵列状排布。有源区包括源区和漏区。有源区的材料例如为多晶硅(poly)，有源区的源区和漏区分别为多晶硅的不同掺杂区。晶体管通常包括栅极、源极和漏极；其中，源极可以与有源区的源区连接，漏极可以与有源区的漏区连接。In some embodiments, a plurality of active regions S may be arranged in an array. The active area includes a source area and a drain area. The material of the active region is, for example, polysilicon (poly), and the source region and the drain region of the active region are respectively different doped regions of the polysilicon. A transistor generally includes a gate, a source, and a drain; wherein, the source may be connected to the source region of the active region, and the drain may be connected to the drain region of the active region.
在一些实施例中，晶体管20包括：金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，简称MOSFET)，例如为N型金属氧化物半导体场效应晶体管(NMOSFET)，或P型金属氧化物半导体场效应晶体管(PMOSFET)。In some embodiments, the transistor 20 includes: a Metal Oxide Semiconductor Field Effect Transistor (MOSFET for short), such as an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), or a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Semiconductor Field Effect Transistor (PMOSFET).
示例的，金属氧化物半导体场效应晶体管的栅极长度小于50nm。Exemplarily, the gate length of the metal oxide semiconductor field effect transistor is less than 50 nm.
此处，金属氧化物半导体场效应晶体管的栅极长度是指栅极所能控制的导电沟道长度，即其漏极与源极之间的距离。Here, the gate length of the metal oxide semiconductor field effect transistor refers to the length of the conductive channel that the gate can control, that is, the distance between the drain and the source.
本公开实施例中，浅沟槽隔离结构的边缘完整，可以在半导体结构尺寸规模较小的情况下，有效隔离不同的有源区，以避免金属氧化物半导体场效应晶体管出现反向窄沟道效应，从而有效提升金属氧化物半导体场效应晶体管的电学性能，例如能够有效提升金属氧化物半导体场效应晶体管的开关响应速度。In the embodiment of the present disclosure, the edge of the shallow trench isolation structure is complete, which can effectively isolate different active regions when the size of the semiconductor structure is small, so as to avoid the reverse narrow channel of the metal oxide semiconductor field effect transistor. effect, thereby effectively improving the electrical performance of the metal oxide semiconductor field effect transistor, for example, effectively improving the switching response speed of the metal oxide semiconductor field effect transistor.
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛 盾，都应当认为是本说明书记载的范围。The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the present disclosure, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the scope of protection of the disclosed patent should be based on the appended claims.

Claims (15)

  1. 一种浅沟槽隔离结构的制备方法，包括：A method for preparing a shallow trench isolation structure, comprising:
    提供衬底，在所述衬底的表面依次层叠形成垫氧层和硬掩膜层；A substrate is provided, and an oxygen pad layer and a hard mask layer are sequentially stacked on the surface of the substrate;
    以图案化后的所述硬掩膜层为掩膜刻蚀所述垫氧层及所述衬底，以在所述垫氧层中形成开口，在所述衬底中形成沟槽；Etching the pad oxide layer and the substrate by using the patterned hard mask layer as a mask to form openings in the pad oxide layer and form trenches in the substrate;
    在所述沟槽内形成衬底氧化层；forming a substrate oxide layer within the trench;
    形成第一阻挡层，所述第一阻挡层覆盖所述硬掩膜层和所述衬底氧化层；forming a first barrier layer covering the hard mask layer and the substrate oxide layer;
    形成第一氧化层，所述第一氧化层覆盖所述第一阻挡层；forming a first oxide layer covering the first barrier layer;
    去除所述硬掩膜层上表面的所述第一阻挡层和所述第一氧化层；removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer;
    去除所述衬底上表面的所述垫氧层和所述硬掩膜层以形成第二阻挡层。The oxygen pad layer and the hard mask layer on the upper surface of the substrate are removed to form a second barrier layer.
  2. 根据权利要求1所述的浅沟槽隔离结构的制备方法，其中，所述制备方法还包括：The preparation method of the shallow trench isolation structure according to claim 1, wherein the preparation method further comprises:
    氧化所述第二阻挡层及所述衬底的部分表面以形成第二氧化层；oxidizing the second barrier layer and a portion of the surface of the substrate to form a second oxide layer;
    去除所述第二氧化层及部分所述衬底氧化层，以使保留于所述沟槽内的所述衬底氧化层形成浅沟槽隔离结构。The second oxide layer and part of the substrate oxide layer are removed, so that the substrate oxide layer remaining in the trench forms a shallow trench isolation structure.
  3. 根据权利要求2所述的浅沟槽隔离结构的制备方法，其中，所述去除所述第二氧化层及部分所述衬底氧化层，包括：The method for preparing a shallow trench isolation structure according to claim 2, wherein said removing said second oxide layer and part of said substrate oxide layer comprises:
    使用氢氟酸稀释溶液对形成所述第二氧化层后所得的结构进行清洗，以去除所述第二氧化层及部分所述衬底氧化层。The structure obtained after forming the second oxide layer is cleaned by using a dilute hydrofluoric acid solution to remove the second oxide layer and part of the substrate oxide layer.
  4. 根据权利要求1所述的浅沟槽隔离结构的制备方法，其中，所述在所述沟槽内形成衬底氧化层，包括：The method for preparing a shallow trench isolation structure according to claim 1, wherein said forming a substrate oxide layer in said trench comprises:
    在所述沟槽、所述开口和所述硬掩膜层的图案内沉积氧化物；depositing an oxide within the pattern of the trenches, the openings, and the hard mask layer;
    去除位于所述开口和所述硬掩膜层的图案内的所述氧化物，以使保留于所述沟槽内的所述氧化物构成所述衬底氧化层。The oxide within the pattern of the opening and the hard mask layer is removed such that the oxide remaining within the trench constitutes the substrate oxide layer.
  5. 根据权利要求4所述的浅沟槽隔离结构的制备方法，其中，所述在所述沟槽内形成衬底氧化层，还包括：The method for preparing a shallow trench isolation structure according to claim 4, wherein said forming a substrate oxide layer in said trench further comprises:
    在所述沟槽、所述开口和所述硬掩膜层的图案内沉积氧化物之后，在去除位于所述开口和所述硬掩膜层的图案内的所述氧化物之前，采用化学机械研磨工艺抛光所述硬掩膜层及所述氧化物的裸露表面。After depositing oxide within the trenches, openings and pattern of the hard mask layer, prior to removing the oxide located within the pattern of openings and the hard mask layer, chemical mechanical A lapping process polishes the exposed surface of the hard mask layer and the oxide.
  6. 根据权利要求1所述的浅沟槽隔离结构的制备方法，其中，所述去除所述硬掩膜层上表面的所述第一阻挡层和所述第一氧化层，去除所述衬底上表面的所述垫氧层和所述硬掩膜层以形成第二阻挡层，包括：The method for preparing a shallow trench isolation structure according to claim 1, wherein the removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer removes the The oxygen pad layer and the hard mask layer on the surface to form a second barrier layer, including:
    去除所述第一阻挡层和所述第一氧化层二者位于所述硬掩膜层上表面的部分，以形成中间阻挡层和中间氧化层；removing portions of both the first barrier layer and the first oxide layer located on the upper surface of the hard mask layer to form an intermediate barrier layer and an intermediate oxide layer;
    去除所述硬掩膜层；removing the hard mask layer;
    去除所述垫氧层和所述中间氧化层，以使所述中间阻挡层形成所述第二阻挡层。The oxygen pad layer and the middle oxide layer are removed, so that the middle barrier layer forms the second barrier layer.
  7. 根据权利要求6所述的浅沟槽隔离结构的制备方法，其中，采用化学机械研磨工艺，去除所述第一阻挡层和所述第一氧化层二者位于所述硬掩膜层上表面的部分，以形成中间阻挡层和中间氧化层。The method for preparing a shallow trench isolation structure according to claim 6, wherein a chemical mechanical polishing process is used to remove both the first barrier layer and the first oxide layer on the upper surface of the hard mask layer part to form an intermediate barrier layer and an intermediate oxide layer.
  8. 根据权利要求6所述的浅沟槽隔离结构的制备方法，其中，采用湿法刻蚀工艺，去除所述硬掩膜层。The manufacturing method of the shallow trench isolation structure according to claim 6, wherein the hard mask layer is removed by using a wet etching process.
  9. 根据权利要求6所述的浅沟槽隔离结构的制备方法，其中，采用湿法刻蚀工艺，去除所述垫氧层和所述中间氧化层。The manufacturing method of the shallow trench isolation structure according to claim 6, wherein the pad oxide layer and the intermediate oxide layer are removed by using a wet etching process.
  10. 根据权利要求9所述的浅沟槽隔离结构的制备方法，其中，所述垫氧层和所述第一氧化层的材料相同。The manufacturing method of the shallow trench isolation structure according to claim 9, wherein the material of the pad oxygen layer and the first oxide layer are the same.
  11. 根据权利要求1～10中任一项所述的浅沟槽隔离结构的制备方法，其中，所述第一阻挡层的材料包括多晶硅。The manufacturing method of the shallow trench isolation structure according to any one of claims 1-10, wherein the material of the first barrier layer comprises polysilicon.
  12. 根据权利要求1～10中任一项所述的浅沟槽隔离结构的制备方法，其中，所述第一阻挡层的厚度范围为1nm～3nm。The method for preparing a shallow trench isolation structure according to any one of claims 1 to 10, wherein the thickness of the first barrier layer ranges from 1 nm to 3 nm.
  13. 一种浅沟槽隔离结构，采用如权利要求1～12中任一项所述的制备方法制备获得。A shallow trench isolation structure, prepared by the preparation method according to any one of claims 1-12.
  14. 一种半导体结构，包括：A semiconductor structure comprising:
    衬底，具有沟槽；a substrate having grooves;
    如权利要求13中所述的浅沟槽隔离结构，设置于所述沟槽内；所述浅沟槽隔离结构在所述衬底内隔离出多个有源区；The shallow trench isolation structure as claimed in claim 13, disposed in the trench; the shallow trench isolation structure isolates a plurality of active regions in the substrate;
    以及，多个晶体管；所述晶体管设置于对应的所述有源区内。And, a plurality of transistors; the transistors are arranged in the corresponding active regions.
  15. 根据权利要求14所述的半导体结构，其中，所述晶体管包括：金属氧化物半导体场效应晶体管；所述金属氧化物半导体场效应晶体管的栅极长度小于50nm。The semiconductor structure according to claim 14, wherein the transistor comprises: a metal oxide semiconductor field effect transistor; and the gate length of the metal oxide semiconductor field effect transistor is less than 50 nm.
PCT/CN2022/081487 2022-02-18 2022-03-17 Shallow trench isolation structure, preparation method therefor, and semiconductor structure WO2023155263A1 (en)

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