WO2023151987A1 - Method and semiconductor module - Google Patents

Method and semiconductor module Download PDF

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Publication number
WO2023151987A1
WO2023151987A1 PCT/EP2023/052315 EP2023052315W WO2023151987A1 WO 2023151987 A1 WO2023151987 A1 WO 2023151987A1 EP 2023052315 W EP2023052315 W EP 2023052315W WO 2023151987 A1 WO2023151987 A1 WO 2023151987A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal disk
semiconductor component
clip body
main side
bottom metal
Prior art date
Application number
PCT/EP2023/052315
Other languages
French (fr)
Inventor
Jagoda Dobrzynska
Jan Vobecky
Umamaheswara Vemulapati
Thomas Bernhard Gradinger
Thomas Stiasny
Original Assignee
Hitachi Energy Switzerland Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Energy Switzerland Ag filed Critical Hitachi Energy Switzerland Ag
Publication of WO2023151987A1 publication Critical patent/WO2023151987A1/en

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    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
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    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • a method is provided by means of which a semiconductor module is produced .
  • a semiconductor module produced by such a method is also provided .
  • a problem to be solved is to provide a semiconductor module that has improved reliability .
  • a semiconductor component is pressed on a bottom metal disk with a pressure profile that has a circumferential maximum of a pressure profile that is between a local minimum in a central region and a circumferential minimum of the pressure profile , seen along a radial direction .
  • a pressure profile also referred to as pressure distribution
  • an improved contact between the semiconductor component and the bottom metal disk can be obtained, and thus enhanced cooling and/or higher currents can be achieved .
  • the manufacturing method comprises the following steps :
  • - providing a semiconductor component configured for voltages of at least 0 . 6 kV and having a bottom main side and an opposite top main side ,
  • the pressure profile can be predefined .
  • the top main side faces a top metal disk and the semiconductor component is located directly between the bottom metal disk and the top main side
  • the method further comprises forming a clip body which surrounds the semiconductor component in a lateral direction which is in parallel with the bottom main side and which partially covers the top main side , the clip body is in direct contact with the bottom metal disk, the clip body is made of plastics , the clip body and the top metal disk press the semiconductor component onto the bottom metal disk, and the pressure profile is present in the finished semiconductor module when being operated .
  • a semiconductor module is additionally provided .
  • a semiconductor module as indicated below in connection with at least one of the following embodiments can be produced .
  • Features of the semiconductor module are therefore also disclosed for the method and vice versa .
  • the semiconductor module comprises one or a plurality of semiconductor components configured for voltages of at least 0 . 6 kV having a bottom main side and an opposite top main side , and a bottom metal disk onto which the semiconductor component is pressed with a pressure profile , the bottom main side faces the bottom metal disk .
  • the pressure profile has a local minimum in a central region of the semiconductor component which is surrounded by a circumferential maximum of the pressure profile, and said circumferential maximum is surrounded by a circumferential minimum of the pressure profile.
  • the pressure in the local minimum in the central region is lower than in the circumferential maximum of the pressure profile, but it is also possible that there is the same pressure in said circumferential maximum and in said local minimum.
  • FRD fast recovery diode
  • the at least one semiconductor component is, for example, a wafer. It is possible that the semiconductor component is an injection enhanced gate transistor, IEGT, an integrated gate- commutated thyristor, IGCT, a metal-oxide-semiconductor field-effect transistor, MOSFET, a metal-insulator- semiconductor field-effect transistor, MISFET, an insulated- gate bipolar transistor, IGBT, a bipolar junction transistor, BJT, a gate turn-off thyristor, GTO, a gate commutated thyristor, GCT, a junction gate field-effect transistor, JFET, a phase controlled thyristor, PCT, or also a diode.
  • the semiconductor component is of silicon, Si.
  • the semiconductor component can alternatively be based on a wide-bandgap semiconductor material like SiC, GagOg or GaN.
  • the semiconductor component is a power device.
  • the semiconductor component is configured for a maximum voltage of at least 0.6 kV or of at least 1.2 kV or of at least 2.8 kV.
  • the semiconductor component can be configured for a maximum current of at least 10 A or of at least 0 . 1 kA or of at least 1 kA.
  • the semiconductor module is , for example , a power module to convert direct current from a battery to alternating current for an electric motor, for example , in vehicles like hybrid vehicles or plug-in electric vehicles or also in railways , like commuter trains .
  • I f there is more than one semiconductor component in the semiconductor module all the semiconductor components can be of the same type and may be connected electrically in series , or di f ferent types of semiconductor components can be combined with each other .
  • the semiconductor module could be an FRD with a novel design of an attachment of the semiconductor component which is , for example , a silicon wafer to the bottom metal disk, which is , for example , a molybdenum disk, wherein a strain buf fer is introduced .
  • the semiconductor component is attached to the bottom metal disk in a way to control a pressure distribution, resulting in a wafer bow, in three dimensions .
  • One option is the attachment of the semiconductor component to the bottom metal disk by a clip body which is , for example , a molded ring serving at the same time as an insulation to increase a striking distance , instead of , for example , silicone rubber, SR .
  • a second option is the attachment of the semiconductor component to the bottom metal disk by a low temperature bonding, LTB, process , where a bond line is structured in two dimensions . Further options are also possible to achieve the desired pressure profile . Both options increase the reverse bias safety operating area, RBSOA, demonstrated by increased ruggedness in frequency operation in a power converter with an IGCT.
  • FRDs Components like FRDs are inevitable for operation of power converters with diode-less IGBT modules, lEGTs or IGCTs.
  • the demand on continuously growing current capability of power converters results in growing area of discrete FRDs.
  • discrete FRDs In the 4.5 kV class, for example, discrete FRDs with diameters of, for example, a silicon wafer ranging from 30 mm to 120 mm can be found. With growing device area beyond 1 cm ⁇ chips, it is more difficult for FRDs to pass without failure the fast reverse recovery process from a high ON-state current in the unit kA range and direct current, DC, link voltages at 2.8 kV and above, that is, the 4.5 kV class.
  • a failure current depends primarily on the design of FRD.
  • An appropriate doping profile of an anode semiconductor side can minimize dynamic avalanche leading to current filaments caused by entering the negative differential resistance, NDR, region of operation and subsequent failure by melting a hole through the semiconductor component.
  • the failure current also depends on a thermal resistance of a junction to a case, Rfh j-c-
  • the LTB process is known to reduce this Rpp j_ c and to provide higher ratings.
  • the semiconductor component is bonded at a single side to the bottom metal disk.
  • the bottom metal disk consists of one or a plurality of metals.
  • the bottom metal disk is a disk made of molybdenum or a molybdenum alloy.
  • 'Disk' may mean that a thickness of the respective component is at most 10% of a diameter, or mean diameter, of said component.
  • Mean diameter means twice a mean radius which is the square root of the area content of the respective component divided by %.
  • the bottom metal disk has a radius rO, and a position of the circumferential maximum M of the pressure profile P is between 0.5 rO and 0.9 rO.
  • the bottom metal disk and/or the semiconductor component can be of rotational symmetric shape, that is, of circular shape, seen in top view.
  • a radius r of the bottom metal disk it applies that 0 ⁇ r ⁇ rO.
  • a zero position may be located at a center of gravity, and r may run from 0 to a maximum distance of the center of gravity to an edge of the bottom metal disk.
  • a radius rS of the semiconductor component is between 0.8 rO and rO or is between 0.9 rO and rO or is between 0.92 rO and 0.99 rO. That is, the semiconductor component could be slightly smaller than the bottom metal disk or can have the same size as the bottom metal disk.
  • a pressure pM of the circumferential maximum and a pressure pN2 of the circumferential minimum the following applies: 0 ⁇ pN2 ⁇ 0.5 pM ⁇ pNl ⁇ pM or 0,1 pM ⁇ pN2 ⁇ 0.4 pM ⁇ pNl ⁇ 0,9 pM o r 0,1 pM ⁇ pN2 ⁇ 0.6 pM ⁇ pNl ⁇ 0,9 pM.
  • pN2 ⁇ pNl for example, pNl - pN2 > 0.1 pM or pNl - pN2 > 0.2 pM.
  • r is a unitless variable representing a distance to the local minimum and/or a center of the bottom metal disk and/or the semiconductor component.
  • A/pM and at least one of C, D, E and F/pM are positive numbers.
  • B is a negative number.
  • P(r) A / (l + B + F is true from -rS to rS, that is, r is between ⁇ -rS ⁇ and ⁇ rS ⁇ , and ⁇ ⁇ indicates a numeric value of the respective quantity value, with a tolerance of at most 0.1 pM or of at most 0.05 pM or of at most 0.02 pM. For example, 0.25 pM ⁇ A ⁇ pM and -
  • 'tolerance of' means ' ⁇ ' , that is, for example, 'with a tolerance of at most 0.1 pM' means ⁇ 0.1 pM .
  • pNl ⁇ pM pNl ⁇ pM.
  • the semiconductor module further comprises one or a plurality of clip bodies .
  • the at least one clip body may surround the semiconductor component completely or partially in a lateral direction which is in parallel with the bottom main side . Further, the at least one clip body partially covers the top main side .
  • the clip body is in direct contact with the bottom metal disk and/or with the semiconductor component .
  • side faces of the semiconductor component are completely and directly covered with the clip body .
  • Side faces of the bottom metal disk can completely or partially be covered with the clip body in a direct manner .
  • a bottom metal disk top side can partially and directly be covered with the clip body .
  • the clip body is made of at least one plastics .
  • Said plastics can include one or a plurality of additives , for example , to adj ust the thermal and/or mechanical properties of the plastics .
  • the plastics is an epoxide .
  • the clip body is electrically insulating .
  • the clip body In operation of the semiconductor module , no current is intended to be led through the clip body, but the clip body may provide electric insulation between pole pieces and/or the metal disks .
  • the clip body is configured to press the semiconductor component onto the bottom metal disk . This is achieved, for example , by a geometric shape of the clip body . For example, when the semiconductor component has a bow relative to the bottom metal disk, a part of the clip body at the lateral faces of the semiconductor component can be stresses so that a part of the clip body atop the top main side can press the semiconductor component in the direction towards the bottom metal disk .
  • the circumferential maximum of the pressure profile is located within an opening in the clip body so that the circumferential maximum is not covered by the clip body . Otherwise , the circumferential maximum can be covered by the clip body .
  • the semiconductor component between the semiconductor component and the bottom metal disk there is at least in places at least one free floating region in which the semiconductor component is free floating relative to the bottom metal disk .
  • there is a so-called dry contact in said regions the semiconductor component may be in direct contact with the bottom metal disk and/or there is no component of condensed matter between the bottom metal disk and the semiconductor component in said regions .
  • the semiconductor module further comprises at least one bond material located at least in places between the semiconductor component and the bottom metal disk .
  • the semiconductor component is fixedly connected to the bottom metal disk by means of the at least one bond material .
  • Fixedly connected' may mean that in the intended use the semiconductor component cannot move relative to the bottom metal disk in the at least one connection region.
  • the at least one free floating region there is both the at least one free floating region and the at least one connection region. Hence, only at places relative movement of the bottom metal disk with respect to the semiconductor component is inhibited.
  • the at least one bond material is present both in the at least one free floating region and in the at least one connection region.
  • the at least one bond material has a constant thickness throughout the bottom main side.
  • a thickness of the at least one bond material is at least 10 pm and/or is at most 100 pm.
  • the at least one bond material can be comparably thick.
  • the at least one connection region is located at at least one of the circumferential maximum and the circumferential minimum of the pressure profile.
  • the central region is free of the connection region.
  • the at least one bond material is selected from the following group: soldering paste, silver paste, silver sheet, sinter body.
  • the at least one bond material comprises or consists of one or a plurality of the following metals: Ag, Al, Bi, Cu, In, Mo, Ni, Pb, Sb, Ti, W.
  • the bond material is of silver or a silver alloy.
  • the semiconductor module further comprises a top metal disk which is arranged at the top main side . A diameter of the top metal disk is smaller than a diameter of the semiconductor component .
  • the circumferential maximum of the pressure profile is covered by the top metal disk, or alternatively the circumferential maximum is located outside the top metal disk .
  • the top metal disk can be a molybdenum disk, too .
  • At least one of the bottom metal disk and the top metal disk, i f present comprises a bow configured to provide the pressure profile .
  • at least one of the metal disks intentionally does not have a plane side facing the assigned semiconductor component .
  • the semiconductor component is bent , and seen in cross-section perpendicular to the bottom main side , a bending profile has a maximum in the central region between two adj acent inflection points and a flat region along a rim of the semiconductor component .
  • a di f ferential bending that is , a distance between the semiconductor component and the bottom metal disk .
  • a maximum relative bending of the semiconductor component is at most 3 x 10- ⁇ or is at most 1 x 10- ⁇
  • the maximum relative bending is a maximum absolute bending divided by a diameter of the semiconductor component .
  • the maximum absolute bending is at most 0 . 3 mm or at most 0 . 1 mm or at most 40 gm .
  • a width of the semiconductor component is at least 25 mm or is at least 5 cm and alternatively or additionally is at most 25 cm .
  • the semiconductor component can be comparably large .
  • Figure 1 is a schematic sectional view of an exemplary embodiment of a semiconductor module described herein,
  • Figure 2 is a schematic pressure profile of the semiconductor module of Figure 1 .
  • Figure 3 is a schematic sectional view of an exemplary embodiment of a semiconductor module described herein,
  • Figure 4 is a schematic top view of the semiconductor module of Figure 3
  • Figures 5 and 6 are schematic sectional views of an exemplary embodiment of a semiconductor module described herein,
  • Figure 7 is a schematic representation of a displacement of a semiconductor component and of a bottom metal disk of an exemplary embodiment of a semiconductor module described herein,
  • Figures 8 to 10 are schematic representations of electric and thermal properties of exemplary embodiments of semiconductor modules described herein compared with reference devices ,
  • Figure 11 are schematic perspective representations of a semiconductor modules described herein and of a reference device .
  • Figures 12 and 13 are schematic sectional views of semiconductor components of semiconductor modules described herein,
  • Figure 14 is a schematic sectional views of a semiconductor component of a reference device .
  • Figure 15 are schematic top views of pressure sensitive papers used in semiconductor modules described herein.
  • Figure 16 is a schematic top view and a schematic sectional view of a reference device
  • Figures 17 to 20 are schematic top views and respective schematic sectional views of exemplary embodiments of semiconductor modules described herein,
  • Figures 21 to 24 are schematic top views of exemplary embodiments of semiconductor modules described herein,
  • Figure 25 is a schematic sectional view of an exemplary embodiment of a semiconductor module described herein,
  • Figure 26 is a schematic representation of manufacturing parameters of a method for producing exemplary embodiments of semiconductor modules described herein,
  • Figure 27 is a schematic representation of a pressure profile of an exemplary embodiment of a semiconductor module described herein.
  • Figure 28 is a schematic block diagram of an exemplary embodiment of a method for producing of semiconductor modules described herein .
  • the semiconductor module 1 comprises a semiconductor component 2 which is , for example , a silicon wafer configured as an IEGT , IGCT , IGBT , GTO, PCT , FRD or GCT .
  • the semiconductor component 2 is mounted on a bottom metal disk 3 .
  • the bottom metal disk 3 is a molybdenum disk . It is possible that a bottom main side 23 of the semiconductor component 2 is at least in places in direct contact with a bottom metal disk top side 30 . A top main side 24 of the semiconductor component 2 is remote from the bottom metal disk 3 .
  • the semiconductor component 2 is pressed onto the bottom metal disk top side 30 with a pressure profile P, see Figure 2 .
  • the pressure profile P may be rotational symmetric .
  • the bottom metal disk 3 has a radius rO
  • a radius of the semiconductor component 2 is also rO or slightly smaller .
  • the sketch in Figure 2 starts from a center of the bottom metal disk 3 and the semiconductor component 2 .
  • the pressure profile P has a local minimum N1 .
  • Nl there is a pressure pNl .
  • M there is a circumferential maximum M of the pressure profile P in which there is a global maximum pressure pM at a radius rM .
  • the pressure decreases , for example , in a monotonic and/or di f ferentiable manner .
  • an outer third region A3 there is a circumferential minimum N2 with a pressure pN2 .
  • the pressure pN2 is present at an edge of the semiconductor component 2 or near said edge . Accordingly, the pressure profile P has the maximum N in the second region A2 .
  • the first and second regions Al , A2 and/or the second and third regions A2 , A3 are delimited by inflexion points of the pressure profile P .
  • the local minimum Nl in the maximum M and optionally also in the circumferential minimum N2 there can be zeros of a derivation of the pressure profile P .
  • the first region Al it applies that
  • a boundary between the first and second region Al, A2 may be at an r for which it applies 0.3 ⁇ r ⁇ 0, 6 rO or 0.4 ⁇ r ⁇ 0, 6 rO.
  • a boundary between the second and third region A2, A3 may be at an r for which it applies 0.7 ⁇ r ⁇ rO or at 0.8 ⁇ r ⁇ 0,9 rO.
  • FIGS 3 and 4 illustrate another embodiment of the semiconductor module 1.
  • the pressure profile P is obtained by using a clip body 5,
  • the clip body 5 is of an epoxide.
  • Exemplary materials for the clip body 5 are epoxy mold compounds, EMC. It is possible that coefficients of thermal expansions, CTEs, of said EMCs for the clip body 5 are at least 3 ppm/ °C and/or at most 50 ppm/°C.
  • glass transmission temperatures, Tg, of EMCs for the clip body 5 are at least 120 °C and/or at most 300 °C.
  • a Young's modulus, E, and/or a flexural modulus of EMCs for the clip body 5 are at least 10 GPa and/or at least 40 GPa.
  • the clip body 5 partially directly covers the top main side 24 as well as the bottom metal disk top side 30. Side faces of the semiconductor component 2 are completely directly covered by the clip body 5. Side faces of the bottom metal disk 3 are completely or also partially directly covered by the clip body 5 . Other than shown, the semiconductor component 2 and the bottom metal disk 3 can have the same radius .
  • the clip body 5 laterally protrudes from the bottom metal disk 3 and/or from the semiconductor component 2 by at least 2 mm and/or by at most 2 cm .
  • said lateral protrusion is at least 2 % and/or at most 20% of rO .
  • a thickness of the clip body 5 atop the top main side 24 is at least 1 mm and/or at most 1 cm .
  • said thickness is at least 1 % and/or at most 10% of rO , or is at least 50% and/or is at most 300% of a thickness of the semiconductor component 2 .
  • a covering width L of the clip body 5 on the top main side 24 is at least 1 mm and/or at most 1 cm .
  • said covering width L is at least 2 % and/or at most 20% of rO .
  • the semiconductor module 1 is , seen in top view, of rotational symmetric design .
  • the sectional views illustrated herein refer to a cross-section along one of the dash-dotted lines through the center of the semiconductor module 1 , compare Figure 4 . The same can apply for all other embodiments .
  • the semiconductor module 1 includes a top metal disk 4 which is , for example , a molybdenum disk .
  • the bottom metal disk 3 can be arranged on a bottom pole piece 71 which is , for example , a copper plate .
  • An additional top pole piece can correspondingly be present at the top metal disk 4.
  • the metal disks 3, 4 may have an adjustment structure 73 in the center.
  • the components 71, 3, 2, 4 may be pressed together with a clamping force of, for example, 1 kN to 0.1 MN. In case of r « 90 mm, said force may be about 0.04 MN. For example, a pressure resulting from the clamping force is between 2 MPa and 20 MPa.
  • void 25 between the semiconductor component 2 and the bottom metal disk 3 .
  • This void 25 is located, for example , in the second and/or in the third region .
  • the circumferential maximum M of the pressure profile P is located where the void 25 has been in the case of no clamping force .
  • the clip body 5 is produced as follows :
  • the semiconductor component 2 is applied directly on the bottom metal disk 3 , for example , at room temperature .
  • the semiconductor component 2 and bottom metal disk 3 may be flat when the clip body 5 is formed .
  • the clip body 5 is created by clamping the semiconductor component 2 and the bottom metal disk 3 together at a high temperature when a material for the clip body 5 is in a liquid state .
  • Clamping may be achieved by a mold for the clip body, an interior of the mold has the shape of the clip body 5 to be formed .
  • the material for the clip body 5 is inj ected into the mold . After some time , the liquid material for the clip body 5 solidi fies . After solidi fication, the resulting arrangement of the semiconductor component 2 , the bottom metal disk 3 and the clip body 5 is unclamped and cooled down in a fourth step . Because of this cooling down, the bending of the semiconductor component 2 and optionally also of the bottom metal disk 3 occurs .
  • the material for the clip body 5 is , for example , a thermosetting plastics , like a thermosetting resin .
  • the clip body 5 is manufactured at a temperature of at least 130 ° C and/or of at most 260 ° C . Hence , when clamped together, the semiconductor component 2 and the bottom metal disk 3 can have such a high temperature .
  • a part of the clip body 5 on the top main side 24 acts as a lever that presses the semiconductor component 2 onto the bottom metal disk 3 .
  • This pressure by the lever is possible , for example , because the semiconductor component 2 and/or the bottom metal disk 3 is/are bent at said temperature .
  • at room temperature there can be a gap between the semiconductor component 2 and the bottom metal disk 3 in the area the clip body 5 is applied, seen in top view, and without the top metal disk 4 being applied, compare Figure 6 .
  • Room temperature may mean 23 ° C ; the operating temperature of the finished semiconductor module 1 is , for example , at least -40 ° C and/or at most 160 ° C .
  • the operating temperature may be below the glass transition temperature of the clip body 5 .
  • the pressure profile P may then form in a fi fth step when the top metal disk 4 and the bottom metal disk 3 are pressed onto the semiconductor component 2 after the clip body 5 has been formed .
  • This pressing is done , for example , by means of the pole pieces 71 , 72 .
  • the pressure profile P may only be present after pressing the top metal disk 4 inside a housing, but the bent wafer shape of the semiconductor component 2 is present immediately after cooling down the semiconductor component 2 and the bottom metal disk 3 with finishing the molding process of the clip body 5 .
  • reference devices 9 are compared with embodiments of the semiconductor module 1 which is , for example , a FRD .
  • Figure 8 shows the capability of a 4 . 5 kV FRD when tested in continuous regime in a power converter, further called frequency test , F-test .
  • the lowest ruggedness shows the free floating, FF, design concept with no clip body 5 as illustrated above .
  • a ruggedness of the FF concept can be increased by increasing a clamping force from 40 kN to 50 kN . However, this represents an extra cost a customer, and it is not always possible.
  • the capability of the FF concept without increasing the clamping force can be improved if the semiconductor component 2, which is, for example, a silicon wafer, is attached to the bottom metal disk using the clip body 5 as a mold compound.
  • a contact between the bottom main side 23 and the bottom metal disk 3 is still dry, but the pressure distribution from a wafer center to an edge is different.
  • the EMC KI has a higher CTE, a higher Tg and a lower E than the EMC K2.
  • FIG 8 a last pass current Ip in an F-test of 4.5 kV FRDs with an area of 55 cm ⁇ in a converter comprising an IGCT is illustrated.
  • Figure 9 illustrates a last pass current Ip of a diode in an F-test of 4.5 kV FRDs with an area of 55 cm ⁇ in a converter comprising an IGCT.
  • FIG. 10 illustrates a thermal stability test of 4 . 5 kV FRDs with area of 55 cm ⁇ .
  • the performance is improvement by 5 ° C for the semiconductor module 1 described herein compared with a corresponding LTB design, equal for both types of mold compound KI , K2 , resulting from di f ferent pressure distribution due to di f ferent bow .
  • the semiconductor module 1 described herein uses a controlled device warpage and/or bow to achieve the advantageous pressure distribution giving the best device ruggedness .
  • Figure 11 shows the di f ferences between wafer bows after attachment of a silicon wafer 2 with a diameter of 91 mm to a molybdenum disk 3 for LTB, right side , and the clip body 5 design, left side .
  • the latter shows a distinct flattened region at the proximity of a wafer edge .
  • the silicon wafer 2 is pressed to the molybdenum disk 3 in a wide region at the edge towards the center of the wafer 2 .
  • there is more current flowing outside the wafer edge through a wider region with a lower resistance and lower Rfh j -c due to the higher pressure .
  • the wafer edge of the design comprising the clip body 5 is less overheated and the module 1 does not fail in reverse blocking mode due to thermal runaway . It most likely might fail at reverse recovery, what happens at higher currents .
  • Figure 15 shows pressure sensitive papers used in semiconductor modules 1 described herein and in reference devices 9 .
  • a tighter hatching pattern represents a higher pressure .
  • the pressure profile P shows a higher pressure at the edge of the wafer than the semiconductor module 1 described herein and than the LTB reference device 9 shown in Figure 15 , right part .
  • the wafers with a higher pressure at periphery may fail along the wafer edge typically during reverse blocking between switching events .
  • the semiconductor module 1 described herein may fail mostly in switching mode during reverse recovery and a failure pattern may starts in the bulk as a result of current f ilamentation due to the NDR .
  • a failure current may be close to that of the LTB design, which has a lower Rpp j _ c over the whole wafer surface due to the bonding of the silicon wafer to the molybdenum disk .
  • the concept of FRD back-end design described herein has a higher robustness during hard switching without using the conventional LTB technique to reduce cost and increase production yield .
  • the methods to achieve the flat wide region along the wafer edge in the pressure profile P various methods can be used, for example , the clip body 5 described above ; further methods are described below .
  • the locali zed reduction of the contact thermal resistance and electrical resistance at the desired location on the wafer surface may be achieved by a designed- in warpage of the wafer achieved from, for example :
  • bent metal disks and/or
  • a reference device 9 using LTB is shown in Figure 16 .
  • the conventional LTB concept involves deposition of a bond material 6 in-between the silicon wafer and the molybdenum disk and homogenous all-over the surface of the two parts being bonded . This results , due to thermal stress and coef ficient of thermal expansion, GTE , mismatch of the parts , in a dome shaped bow, as presented in Figure 14 .
  • Structuring of the bond-line may be achieved by deposition of the bond material 6 at selective areas . This can be achieved, for example , by stencil printing or screen printing of a soldering or silver paste , or a trans fer of a silver sheet with a pre-defined shape .
  • Structuring of the bond-interface may be achieved, for example , by structured coating of the wafer with a thin ( compared to the bond line ) bonding or non-bonding metal layer, or structuring of the bond material 6 before the bond process , for example , by structured hot stamp pressing on the bond material 6 before the wafer-to-Mo bonding process , that sinters the bond material 6 in the respectively selected areas and prevents to sinter wafer-to-Mo in the following process ) .
  • a bonding material 6 is present only in the area of the bond between the semiconductor component 2 and the bottom metal disk 3 .
  • the bond material 6 is present all over the surface of the semiconductor component 2 and the bottom metal disk 3 , so that there is the bond material 6 and would mechanically, electrically and/or thermally support the structure , however, but there is no bond in the selected areas .
  • the bond material 6 is limited to an outer region, and the central region C is free of the bond material 6.
  • the bond material 6 may run to an edge of the semiconductor component 2.
  • a width of the bond material 6 is between 0.1 rO and 0.5 rO or between 0.15 rO and 0.3 rO, wherein rO is the radius of the bottom metal disk 3 and/or of the semiconductor component 2.
  • the bond material 6 is limited to the central region C, and the outer region is free of the bond material 6.
  • the bond material 6 may thus cover the center of the semiconductor component 2.
  • the bond material 6 runs towards the edge up to at most 0.8 rO or up to at most 0.5 rO or up to at most 0.3 rO.
  • the bond material 6 is applied all over the semiconductor component 2. However, only at the outer region, there is a connection region 60 in which bonding between the semiconductor component 2 and the bottom metal disk 3 is achieved. In the center region C, there is a free floating region 62 in which no bonding is achieved between the semiconductor component 2 and the bottom metal disk 3 by means of the bond material 6.
  • a width of the connection region 60 is between 0.1 rO and 0.5 rO or between 0.15 rO and 0.3 rO.
  • the bond material 6 is also applied all over the semiconductor component 2, however, the outer region corresponds to the free floating region 62 and the center region C is the connection region 60.
  • the connection region 60 runs towards the edge of the semiconductor component 2 up to at most 0.8 rO or up to at most 0.5 rO or up to at most 0.3 rO.
  • the outer ring starts at the edge of the semiconductor component 2.
  • the center region C can be free of the bond material 6.
  • widths of the rings are between 0.05 rO and 0.4 rO or between 0.15 rO and 0.35 rO.
  • the inner ring of the bond material 6 is located, for example, between 0.2 rO and
  • a radius of the inner dot is at least 0.2 rO or at least 0.3 rO and/or is at most 0.8 rO or is at most 0.6 rO.
  • the bond material 6 corresponds to an outer ring starting, for example, at the edge of the semiconductor component 2.
  • a width of the ring of the bond material 6 is between 0.1 rO and 0.5 rO or between 0.2 rO and 0.4 rO.
  • said ring comprises a plurality of recesses 64.
  • a depth of the recesses 64 into the ring is, for example, at least 10% or at least 30% and/or at most 90% or at most 60% of the width of the ring. For example, there are at least five and/or at most 32 of the recesses 64.
  • the recesses 64 may be arranged in an equidistant manner.
  • the bond material 6 is applied as a dot in the center region C.
  • a radius of the dot is at least 0.2 rO or at least 0.3 rO and/or is at most 0.8 rO or is at most 0.6 rO.
  • said central dot comprises a plurality of dents 63.
  • a radial extent of the dents 63 towards the edge of the semiconductor component 2 is, for example, at least 10% or at least 30% and/or at most 90% or at most 60% of the diameter of the dot. For example, there are at least five and/or at most 32 of the dents 63.
  • the dents 63 may be arranged in an equidistant manner.
  • the bond material 6 corresponds to the connection region 60, like in Figures 18 and 19. However, there can also be free floating regions 62 of the bond material in Figures 22 to 25 analogous to Figures 20 and 21.
  • the pressure profile P is achieved by the bottom pole piece 71 and/or by the top pole piece 72. In-between the pole pieces 71, 72, there is a space 74 for the metal disks 3, 4 and for the semiconductor component 2. Seen in cross-section, the pole pieces 71, 72 can be of hump fashion or double-hump fashion so that one or two thickness maxima can be present . Other than shown in Figure 25 it is not necessary that the thickness maxima exactly face one another, but that the thickness maxima are laterally displaced, for example , for at least 0 . 02 rO and/or for at most 0 . 2 rO .
  • Such non-planar pole pieces 71 , 72 can be combined with the clip body 5 and with the bond material 6 .
  • the pressure profile P can be achieved by having di f ferent bonding conditions during, for example , applying the connection between the semiconductor component 2 and the bottom metal disk 3 by means of the bond material 6 .
  • a bonding pressure p and/or a bonding temperature T applied to the semiconductor component 2 and the bottom metal disk 3 and the bond material 6 during bonding increase towards an edge of the semiconductor component 2 .
  • the pressure p and/or the temperature T may be nearly constant so that a rapid change in pressure and/or temperature T may occur in the second region A2 .
  • Such varied process parameters can also be combined with non- planar pole pieces 71 , 72 , with the clip body 5 and/or with the bond material 6 .
  • Figure 27 a further exemplary pressure profile P is shown.
  • the pressure profile P can be approximated by the formula
  • P(r) A / (l + B + F, for example, with a tolerance of at most 0.1 pM or of at most 0.05 pM.
  • Such a pressure profile P as approximated by the above formula may apply to all embodiments of the semiconductor module 1.
  • a first method step SI the semiconductor component 2 and the bottom metal disk 3 are provided.
  • a second method step S2 the semiconductor component 2 is pressed onto the bottom metal disk 3 with a pressure profile.
  • This step S2 may directly follow method step SI or may be done during installation of the semiconductor module 1 or occurs in the intended use of the semiconductor module 1, that is, under operation conditions. For example, directly after assembling the semiconductor component 2 onto the bottom metal disk 3 , there may be no such pressure profile P, but the desired pressure profile P may result later from operating the semiconductor module 1 as intended . Otherwise , the desired pressure profile P may be present immediately when assembling the semiconductor component 2 onto the bottom metal disk 3 .
  • step S2 can include substeps S21 , S22 or S23 , wherein steps S21 , S22 and S23 can be used in any combination .
  • the clip body 5 is applied, for example , to result in the semiconductor module 1 of Figures 1 to 15 , see especially Figures 5 and 6 .
  • the bond material 6 is applied, for example , to result in the semiconductor module 1 of Figures 17 to 24 .
  • Step S22 may include providing method parameters in treating the bond material 6 as illustrated in connection with Figure 26 .
  • the pole pieces 71 , 72 are provided, for example , to result in the semiconductor module 1 of Figure 25 .
  • the semiconductor module 1 described herein may be an FRD with a defined profile of a bow and a respective pressure distribution over the wafer interface between the silicon wafer and molybdenum strain buf fer .
  • an FRD with high robustness in hard switching conditions without using the conventional LTB technique can be achieved .
  • Usage of silver contaminant can be eliminated and reduced cost of the process can be obtained .
  • the LTB process with spatial adj ustment of the pressure distribution along the wafer when structuring the bond material 6 can be used, too .
  • a new generation of FRDs with high robustness in hard switching condition is provided . There is the possibility to utili ze the new design on new FRDs with larger areas than exist today .
  • the semiconductor module 1 described herein has a defined spatial distribution of pressure at the silicon wafer 2 - molybdenum disk 3 interface .
  • the silicon wafer 2 and the molybdenum disk 3 are attached together by a clip body, forming a desired three-dimensional deformation, warpage or bow of a resulting package .
  • the silicon wafer 2 and the molybdenum disk 3 are bonded together, by a bond material 6 , present at the interface with a speci fic pattern and thus forming a desired three- dimensional deformation, warpage or bow of the package , or by using any bonding technique , such as low temperature bonding, sintering, soldering or brazing .
  • the bond material 6 between the silicon wafer 2 and the molybdenum disk 3 may be a silver- , lead- , copper- , tin- , bismuth- , indium- , zinc- , antimony- , aluminum- , nickel-containing material .
  • the semiconductor module described here is not restricted by the description on the basis of the exemplary embodiments . Rather, the semiconductor module encompasses any new feature and also any combination of features , which includes in particular any combination of features in the patent claims , even i f this feature or this combination itsel f is not explicitly speci fied in the patent claims or exemplary embodiments .
  • Ip last pass current in A or kA
  • Tp last pass temperature in ° C z displacement zM maximum absolute bending zN relative minimum bending

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Abstract

In one embodiment, the method is for producing a semiconductor module (1), the method comprises: - providing a semiconductor component (2) configured for voltages of at least 0.6 kV and having a bottom main side (23) and an opposite top main side (24), - providing a bottom metal disk (3), and - pressing the semiconductor component (2) onto the bottom metal disk (3) with a preconfigured inhomogeneous pressure profile (P), wherein the bottom main side (23) faces the bottom metal disk (3), seen in top view of the bottom main side (23), the pressure profile (P) has a local minimum (Nl) in a central region (C) of the semiconductor component (2) which is surrounded by a circumferential maximum (M) of the pressure profile (P), and the circumferential maximum (M) is surrounded by a circumferential minimum (N2) of the pressure profile (P).

Description

Description
METHOD AND SEMICONDUCTOR MODULE
A method is provided by means of which a semiconductor module is produced . A semiconductor module produced by such a method is also provided .
Document WO 2020/ 078816 Al discloses a semiconductor module .
A problem to be solved is to provide a semiconductor module that has improved reliability .
This obj ect is achieved, inter alia, by a method and by a semiconductor module as defined in the independent patent claims . Exemplary further developments constitute the sub ect-matter of the dependent claims .
For example , in the semiconductor module a semiconductor component is pressed on a bottom metal disk with a pressure profile that has a circumferential maximum of a pressure profile that is between a local minimum in a central region and a circumferential minimum of the pressure profile , seen along a radial direction . With such a pressure profile , also referred to as pressure distribution, an improved contact between the semiconductor component and the bottom metal disk can be obtained, and thus enhanced cooling and/or higher currents can be achieved .
In at least one embodiment , the manufacturing method comprises the following steps :
- providing a semiconductor component configured for voltages of at least 0 . 6 kV and having a bottom main side and an opposite top main side ,
- providing a bottom metal disk, and then
- pressing the semiconductor component onto the bottom metal disk intentionally with an inhomogeneous pressure profile , or creating said pressure profile between the semiconductor component onto the bottom metal disk . Accordingly, the pressure profile can be predefined . For example , the top main side faces a top metal disk and the semiconductor component is located directly between the bottom metal disk and the top main side , and the method further comprises forming a clip body which surrounds the semiconductor component in a lateral direction which is in parallel with the bottom main side and which partially covers the top main side , the clip body is in direct contact with the bottom metal disk, the clip body is made of plastics , the clip body and the top metal disk press the semiconductor component onto the bottom metal disk, and the pressure profile is present in the finished semiconductor module when being operated .
A semiconductor module is additionally provided . By means of the aforementioned method, a semiconductor module as indicated below in connection with at least one of the following embodiments can be produced . Features of the semiconductor module are therefore also disclosed for the method and vice versa .
In at least one embodiment , the semiconductor module comprises one or a plurality of semiconductor components configured for voltages of at least 0 . 6 kV having a bottom main side and an opposite top main side , and a bottom metal disk onto which the semiconductor component is pressed with a pressure profile , the bottom main side faces the bottom metal disk . Seen in top view of the bottom main side , for example , the pressure profile has a local minimum in a central region of the semiconductor component which is surrounded by a circumferential maximum of the pressure profile, and said circumferential maximum is surrounded by a circumferential minimum of the pressure profile. Preferably, the pressure in the local minimum in the central region is lower than in the circumferential maximum of the pressure profile, but it is also possible that there is the same pressure in said circumferential maximum and in said local minimum.
For example, a fast recovery diode, FRD, with an optimized wafer attachment for enhanced electrical performance is provided .
The at least one semiconductor component is, for example, a wafer. It is possible that the semiconductor component is an injection enhanced gate transistor, IEGT, an integrated gate- commutated thyristor, IGCT, a metal-oxide-semiconductor field-effect transistor, MOSFET, a metal-insulator- semiconductor field-effect transistor, MISFET, an insulated- gate bipolar transistor, IGBT, a bipolar junction transistor, BJT, a gate turn-off thyristor, GTO, a gate commutated thyristor, GCT, a junction gate field-effect transistor, JFET, a phase controlled thyristor, PCT, or also a diode. For example, the semiconductor component is of silicon, Si. However, the semiconductor component can alternatively be based on a wide-bandgap semiconductor material like SiC, GagOg or GaN.
For example, the semiconductor component is a power device. This means, for example, that the semiconductor component is configured for a maximum voltage of at least 0.6 kV or of at least 1.2 kV or of at least 2.8 kV. Alternatively or additionally, the semiconductor component can be configured for a maximum current of at least 10 A or of at least 0 . 1 kA or of at least 1 kA.
The semiconductor module is , for example , a power module to convert direct current from a battery to alternating current for an electric motor, for example , in vehicles like hybrid vehicles or plug-in electric vehicles or also in railways , like commuter trains .
I f there is more than one semiconductor component in the semiconductor module , all the semiconductor components can be of the same type and may be connected electrically in series , or di f ferent types of semiconductor components can be combined with each other .
Thus , the semiconductor module could be an FRD with a novel design of an attachment of the semiconductor component which is , for example , a silicon wafer to the bottom metal disk, which is , for example , a molybdenum disk, wherein a strain buf fer is introduced . The semiconductor component is attached to the bottom metal disk in a way to control a pressure distribution, resulting in a wafer bow, in three dimensions . One option is the attachment of the semiconductor component to the bottom metal disk by a clip body which is , for example , a molded ring serving at the same time as an insulation to increase a striking distance , instead of , for example , silicone rubber, SR . A second option is the attachment of the semiconductor component to the bottom metal disk by a low temperature bonding, LTB, process , where a bond line is structured in two dimensions . Further options are also possible to achieve the desired pressure profile . Both options increase the reverse bias safety operating area, RBSOA, demonstrated by increased ruggedness in frequency operation in a power converter with an IGCT.
Components like FRDs are inevitable for operation of power converters with diode-less IGBT modules, lEGTs or IGCTs. The demand on continuously growing current capability of power converters results in growing area of discrete FRDs. In the 4.5 kV class, for example, discrete FRDs with diameters of, for example, a silicon wafer ranging from 30 mm to 120 mm can be found. With growing device area beyond 1 cm^ chips, it is more difficult for FRDs to pass without failure the fast reverse recovery process from a high ON-state current in the unit kA range and direct current, DC, link voltages at 2.8 kV and above, that is, the 4.5 kV class.
A failure current depends primarily on the design of FRD. An appropriate doping profile of an anode semiconductor side can minimize dynamic avalanche leading to current filaments caused by entering the negative differential resistance, NDR, region of operation and subsequent failure by melting a hole through the semiconductor component. The failure current also depends on a thermal resistance of a junction to a case, Rfh j-c- The LTB process is known to reduce this Rpp j_c and to provide higher ratings.
Typically, the semiconductor component is bonded at a single side to the bottom metal disk. As a result, there is an about 10 pm to 50 pm thick bond line from thermally and electrically well conducting silver or copper between the semiconductor component and the bottom metal disk. This gives much lower Rpp j_c than a free floating, FF, packaging option, where a not bonded silicon wafer is directly pressed between two molybdenum disks and a so-called dry contact is created .
According to at least one embodiment, the bottom metal disk consists of one or a plurality of metals. For example, the bottom metal disk is a disk made of molybdenum or a molybdenum alloy. 'Disk' may mean that a thickness of the respective component is at most 10% of a diameter, or mean diameter, of said component. Mean diameter means twice a mean radius which is the square root of the area content of the respective component divided by %.
According to at least one embodiment, the bottom metal disk has a radius rO, and a position of the circumferential maximum M of the pressure profile P is between 0.5 rO and 0.9 rO. In this case, the bottom metal disk and/or the semiconductor component can be of rotational symmetric shape, that is, of circular shape, seen in top view. Thus, for a radius r of the bottom metal disk it applies that 0 < r < rO. In case of a non-rotational symmetric geometry, a zero position may be located at a center of gravity, and r may run from 0 to a maximum distance of the center of gravity to an edge of the bottom metal disk.
According to at least one embodiment, a radius rS of the semiconductor component is between 0.8 rO and rO or is between 0.9 rO and rO or is between 0.92 rO and 0.99 rO. That is, the semiconductor component could be slightly smaller than the bottom metal disk or can have the same size as the bottom metal disk.
According to at least one embodiment, for a pressure pNl of the local minimum in the central region, a pressure pM of the circumferential maximum and a pressure pN2 of the circumferential minimum the following applies: 0 < pN2 < 0.5 pM < pNl < pM or 0,1 pM < pN2 < 0.4 pM < pNl < 0,9 pM o r 0,1 pM < pN2 < 0.6 pM < pNl < 0,9 pM. Further, it may apply that pN2 < pNl, for example, pNl - pN2 > 0.1 pM or pNl - pN2 > 0.2 pM.
According to at least one embodiment, seen in cross-section through the local minimum and through the semiconductor component, the pressure profile P can be approximated as follows: P(r) = A / (l + B
Figure imgf000009_0001
+ F, wherein r is a unitless variable representing a distance to the local minimum and/or a center of the bottom metal disk and/or the semiconductor component. For example, A/pM and at least one of C, D, E and F/pM are positive numbers. B is a negative number.
According to at least one embodiment,
P(r) = A / (l + B
Figure imgf000009_0002
+ F is true from -rS to rS, that is, r is between {-rS} and {rS}, and { } indicates a numeric value of the respective quantity value, with a tolerance of at most 0.1 pM or of at most 0.05 pM or of at most 0.02 pM. For example, 0.25 pM < A < pM and -
2 < B < -0.5 and 0 < C < 2 and 0 < D < 6 and 0 < E < 10 and 0 < F < 0.3 pM. Alternatively, 0.1 pM < A < pM and
-6 < B < -0.1 and 0 < C < 10 and 0 < D < 25 and 0 < E < 30 and 0 < F < 0.6 pM. The term 'tolerance of' means '±' , that is, for example, 'with a tolerance of at most 0.1 pM' means ± 0.1 pM .
According to at least one embodiment, pNl < pM.
Alternatively, pNl = pM applies. According to at least one embodiment , the semiconductor module further comprises one or a plurality of clip bodies . The at least one clip body may surround the semiconductor component completely or partially in a lateral direction which is in parallel with the bottom main side . Further, the at least one clip body partially covers the top main side .
According to at least one embodiment , the clip body is in direct contact with the bottom metal disk and/or with the semiconductor component . For example , side faces of the semiconductor component are completely and directly covered with the clip body . Side faces of the bottom metal disk can completely or partially be covered with the clip body in a direct manner . Also a bottom metal disk top side can partially and directly be covered with the clip body .
According to at least one embodiment , the clip body is made of at least one plastics . Said plastics can include one or a plurality of additives , for example , to adj ust the thermal and/or mechanical properties of the plastics . For example , the plastics is an epoxide .
According to at least one embodiment , the clip body is electrically insulating . In operation of the semiconductor module , no current is intended to be led through the clip body, but the clip body may provide electric insulation between pole pieces and/or the metal disks .
According to at least one embodiment , the clip body is configured to press the semiconductor component onto the bottom metal disk . This is achieved, for example , by a geometric shape of the clip body . For example , when the semiconductor component has a bow relative to the bottom metal disk, a part of the clip body at the lateral faces of the semiconductor component can be stresses so that a part of the clip body atop the top main side can press the semiconductor component in the direction towards the bottom metal disk .
According to at least one embodiment , seen in top view of the bottom main side , the circumferential maximum of the pressure profile is located within an opening in the clip body so that the circumferential maximum is not covered by the clip body . Otherwise , the circumferential maximum can be covered by the clip body .
According to at least one embodiment , between the semiconductor component and the bottom metal disk there is at least in places at least one free floating region in which the semiconductor component is free floating relative to the bottom metal disk . In other words , in the respective regions there is a so-called dry contact . Accordingly, in said regions the semiconductor component may be in direct contact with the bottom metal disk and/or there is no component of condensed matter between the bottom metal disk and the semiconductor component in said regions .
According to at least one embodiment , the semiconductor module further comprises at least one bond material located at least in places between the semiconductor component and the bottom metal disk . In at least one connection region, the semiconductor component is fixedly connected to the bottom metal disk by means of the at least one bond material . ' Fixedly connected' may mean that in the intended use the semiconductor component cannot move relative to the bottom metal disk in the at least one connection region.
According to at least one embodiment, there is both the at least one free floating region and the at least one connection region. Hence, only at places relative movement of the bottom metal disk with respect to the semiconductor component is inhibited.
According to at least one embodiment, the at least one bond material is present both in the at least one free floating region and in the at least one connection region. For example, the at least one bond material has a constant thickness throughout the bottom main side.
According to at least one embodiment, a thickness of the at least one bond material is at least 10 pm and/or is at most 100 pm. Thus, the at least one bond material can be comparably thick.
According to at least one embodiment, the at least one connection region is located at at least one of the circumferential maximum and the circumferential minimum of the pressure profile. Alternatively or additionally, the central region is free of the connection region.
According to at least one embodiment, the at least one bond material is selected from the following group: soldering paste, silver paste, silver sheet, sinter body. For example, the at least one bond material comprises or consists of one or a plurality of the following metals: Ag, Al, Bi, Cu, In, Mo, Ni, Pb, Sb, Ti, W. For example, the bond material is of silver or a silver alloy. According to at least one embodiment , the semiconductor module further comprises a top metal disk which is arranged at the top main side . A diameter of the top metal disk is smaller than a diameter of the semiconductor component . Seen in top view of the top main side , the circumferential maximum of the pressure profile is covered by the top metal disk, or alternatively the circumferential maximum is located outside the top metal disk . The top metal disk can be a molybdenum disk, too .
According to at least one embodiment , at least one of the bottom metal disk and the top metal disk, i f present , comprises a bow configured to provide the pressure profile . Thus , at least one of the metal disks intentionally does not have a plane side facing the assigned semiconductor component .
According to at least one embodiment , the semiconductor component is bent , and seen in cross-section perpendicular to the bottom main side , a bending profile has a maximum in the central region between two adj acent inflection points and a flat region along a rim of the semiconductor component . Alternatively or additionally, the same may apply for a di f ferential bending, that is , a distance between the semiconductor component and the bottom metal disk .
According to at least one embodiment , a maximum relative bending of the semiconductor component is at most 3 x 10-^ or is at most 1 x 10-^ , the maximum relative bending is a maximum absolute bending divided by a diameter of the semiconductor component . For example , the maximum absolute bending is at most 0 . 3 mm or at most 0 . 1 mm or at most 40 gm .
The same may apply for the di f ferential bending .
According to at least one embodiment , a width of the semiconductor component is at least 25 mm or is at least 5 cm and alternatively or additionally is at most 25 cm . Thus , the semiconductor component can be comparably large .
A method and a semiconductor module described herein are explained in greater detail below by way of exemplary embodiments with reference to the drawings . Elements which are the same in the individual figures are indicated with the same reference numerals . The relationships between the elements are not shown to scale , however, but rather individual elements may be shown exaggeratedly large to assist in understanding .
In the figures :
Figure 1 is a schematic sectional view of an exemplary embodiment of a semiconductor module described herein,
Figure 2 is a schematic pressure profile of the semiconductor module of Figure 1 ,
Figure 3 is a schematic sectional view of an exemplary embodiment of a semiconductor module described herein,
Figure 4 is a schematic top view of the semiconductor module of Figure 3 , Figures 5 and 6 are schematic sectional views of an exemplary embodiment of a semiconductor module described herein,
Figure 7 is a schematic representation of a displacement of a semiconductor component and of a bottom metal disk of an exemplary embodiment of a semiconductor module described herein,
Figures 8 to 10 are schematic representations of electric and thermal properties of exemplary embodiments of semiconductor modules described herein compared with reference devices ,
Figure 11 are schematic perspective representations of a semiconductor modules described herein and of a reference device ,
Figures 12 and 13 are schematic sectional views of semiconductor components of semiconductor modules described herein,
Figure 14 is a schematic sectional views of a semiconductor component of a reference device ,
Figure 15 are schematic top views of pressure sensitive papers used in semiconductor modules described herein,
Figure 16 is a schematic top view and a schematic sectional view of a reference device , Figures 17 to 20 are schematic top views and respective schematic sectional views of exemplary embodiments of semiconductor modules described herein,
Figures 21 to 24 are schematic top views of exemplary embodiments of semiconductor modules described herein,
Figure 25 is a schematic sectional view of an exemplary embodiment of a semiconductor module described herein,
Figure 26 is a schematic representation of manufacturing parameters of a method for producing exemplary embodiments of semiconductor modules described herein,
Figure 27 is a schematic representation of a pressure profile of an exemplary embodiment of a semiconductor module described herein, and
Figure 28 is a schematic block diagram of an exemplary embodiment of a method for producing of semiconductor modules described herein .
In Figure 1 , an embodiment of a semiconductor module 1 is shown . The semiconductor module 1 comprises a semiconductor component 2 which is , for example , a silicon wafer configured as an IEGT , IGCT , IGBT , GTO, PCT , FRD or GCT . The semiconductor component 2 is mounted on a bottom metal disk 3 . For example , the bottom metal disk 3 is a molybdenum disk . It is possible that a bottom main side 23 of the semiconductor component 2 is at least in places in direct contact with a bottom metal disk top side 30 . A top main side 24 of the semiconductor component 2 is remote from the bottom metal disk 3 .
The semiconductor component 2 is pressed onto the bottom metal disk top side 30 with a pressure profile P, see Figure 2 . Like the semiconductor component 2 and the bottom metal disk 3 , the pressure profile P may be rotational symmetric . Thus , the bottom metal disk 3 has a radius rO , and a radius of the semiconductor component 2 is also rO or slightly smaller . The sketch in Figure 2 starts from a center of the bottom metal disk 3 and the semiconductor component 2 .
In a central first region C, Al the pressure profile P has a local minimum N1 . At the local minimum Nl , there is a pressure pNl . Then, in a middle second region A2 , there is a circumferential maximum M of the pressure profile P in which there is a global maximum pressure pM at a radius rM . Then, with increasing radius r, the pressure decreases , for example , in a monotonic and/or di f ferentiable manner . In an outer third region A3 , there is a circumferential minimum N2 with a pressure pN2 . For example , the pressure pN2 is present at an edge of the semiconductor component 2 or near said edge . Accordingly, the pressure profile P has the maximum N in the second region A2 .
For example , the first and second regions Al , A2 and/or the second and third regions A2 , A3 are delimited by inflexion points of the pressure profile P . In the local minimum Nl , in the maximum M and optionally also in the circumferential minimum N2 there can be zeros of a derivation of the pressure profile P . For example, for the first region Al it applies that
0 < r < 0,5 rO. Alternatively or additionally, for the third region A3 it applies that 0.9 < r < rO.
That is, a boundary between the first and second region Al, A2 may be at an r for which it applies 0.3 < r < 0, 6 rO or 0.4 < r < 0, 6 rO. Likewise, a boundary between the second and third region A2, A3 may be at an r for which it applies 0.7 < r < rO or at 0.8 < r < 0,9 rO.
For example, 0 < (pM - pNl) < (pM - pN2) , and pNl < mF or alternatively pNl = pM.
Figures 3 and 4 illustrate another embodiment of the semiconductor module 1. In this embodiment, the pressure profile P is obtained by using a clip body 5, For example, the clip body 5 is of an epoxide. Exemplary materials for the clip body 5 are epoxy mold compounds, EMC. It is possible that coefficients of thermal expansions, CTEs, of said EMCs for the clip body 5 are at least 3 ppm/ °C and/or at most 50 ppm/°C. Alternatively or additionally, glass transmission temperatures, Tg, of EMCs for the clip body 5 are at least 120 °C and/or at most 300 °C. Alternatively or additionally, a Young's modulus, E, and/or a flexural modulus of EMCs for the clip body 5 are at least 10 GPa and/or at least 40 GPa.
In the embodiment of Figures 3 and 4, the clip body 5 partially directly covers the top main side 24 as well as the bottom metal disk top side 30. Side faces of the semiconductor component 2 are completely directly covered by the clip body 5. Side faces of the bottom metal disk 3 are completely or also partially directly covered by the clip body 5 . Other than shown, the semiconductor component 2 and the bottom metal disk 3 can have the same radius .
For example , the clip body 5 laterally protrudes from the bottom metal disk 3 and/or from the semiconductor component 2 by at least 2 mm and/or by at most 2 cm . Alternatively or additionally, said lateral protrusion is at least 2 % and/or at most 20% of rO .
For example , a thickness of the clip body 5 atop the top main side 24 is at least 1 mm and/or at most 1 cm . Alternatively or additionally, said thickness is at least 1 % and/or at most 10% of rO , or is at least 50% and/or is at most 300% of a thickness of the semiconductor component 2 .
For example , a covering width L of the clip body 5 on the top main side 24 is at least 1 mm and/or at most 1 cm . Alternatively or additionally, said covering width L is at least 2 % and/or at most 20% of rO .
As can be seen from Figure 4 , the semiconductor module 1 is , seen in top view, of rotational symmetric design . The sectional views illustrated herein refer to a cross-section along one of the dash-dotted lines through the center of the semiconductor module 1 , compare Figure 4 . The same can apply for all other embodiments .
In Figures 5 and 6 , the working principle of the clip body 5 is illustrated . As an option, the semiconductor module 1 includes a top metal disk 4 which is , for example , a molybdenum disk . The bottom metal disk 3 can be arranged on a bottom pole piece 71 which is , for example , a copper plate . An additional top pole piece , not shown in Figures 5 and 6 , can correspondingly be present at the top metal disk 4. On a side of the top metal disk 4 remote from the semiconductor component 2, there is a top pole piece 72 which is, for example, a copper plate, too. Optionally, the metal disks 3, 4 may have an adjustment structure 73 in the center.
According to Figure 5, all the components 71, 3, 2, 4 are of planar shape so that there is no or no significant displacement z perpendicular to the bottom pole piece 71. However, this state is only idealized. In reality, compare Figure 6, there is a significant displacement z at least of the semiconductor component 2 and possibly also of the bottom metal disk 3. This displacement z results, for example, from temperature differences between assembling and use of the semiconductor module 1 and/or from high currents in the kA range through the semiconductor component 2. It is noted that in Figure 6 a situation is shown in which no clamping pressure is applied to the top metal disk 4 and to the bottom pole piece 71 so that a pressure is effectively just 1 bar.
In the intended use of the semiconductor module 1, by such a displacement, a contact area in particular between the bottom main side 23 and the bottom metal disk top side 30 is reduced and, thus, the performance of the semiconductor module 1 may likewise be limited. In use of the semiconductor module 1, the components 71, 3, 2, 4 may be pressed together with a clamping force of, for example, 1 kN to 0.1 MN. In case of r « 90 mm, said force may be about 0.04 MN. For example, a pressure resulting from the clamping force is between 2 MPa and 20 MPa.
With the exaggerated displacement z illustrated in Figure 6 it can be seen that a top part 52 of the clip body 5 at the top main side 24 is bent relative to a lateral part 53 at the lateral faces . For example , by such a bending, an additional force is applied on the semiconductor component 2 resulting in the desired pressure profile P, compare Figure 2 .
When no clamping force is applied, there may be a void 25 between the semiconductor component 2 and the bottom metal disk 3 . This void 25 is located, for example , in the second and/or in the third region . For example , when the clamping force is applied, the circumferential maximum M of the pressure profile P is located where the void 25 has been in the case of no clamping force .
For example , the clip body 5 is produced as follows :
In a first step, the semiconductor component 2 is applied directly on the bottom metal disk 3 , for example , at room temperature . The semiconductor component 2 and bottom metal disk 3 may be flat when the clip body 5 is formed .
In a second step, for example , the clip body 5 is created by clamping the semiconductor component 2 and the bottom metal disk 3 together at a high temperature when a material for the clip body 5 is in a liquid state . Clamping may be achieved by a mold for the clip body, an interior of the mold has the shape of the clip body 5 to be formed .
Then, in a third step, the material for the clip body 5 is inj ected into the mold . After some time , the liquid material for the clip body 5 solidi fies . After solidi fication, the resulting arrangement of the semiconductor component 2 , the bottom metal disk 3 and the clip body 5 is unclamped and cooled down in a fourth step . Because of this cooling down, the bending of the semiconductor component 2 and optionally also of the bottom metal disk 3 occurs . The material for the clip body 5 is , for example , a thermosetting plastics , like a thermosetting resin .
For example , the clip body 5 is manufactured at a temperature of at least 130 ° C and/or of at most 260 ° C . Hence , when clamped together, the semiconductor component 2 and the bottom metal disk 3 can have such a high temperature .
For example , below a glass transition temperature of the clip body 5 , like room temperature or an operating temperature of the module 1 , a part of the clip body 5 on the top main side 24 acts as a lever that presses the semiconductor component 2 onto the bottom metal disk 3 . This pressure by the lever is possible , for example , because the semiconductor component 2 and/or the bottom metal disk 3 is/are bent at said temperature . Especially, at room temperature there can be a gap between the semiconductor component 2 and the bottom metal disk 3 in the area the clip body 5 is applied, seen in top view, and without the top metal disk 4 being applied, compare Figure 6 .
Room temperature may mean 23 ° C ; the operating temperature of the finished semiconductor module 1 is , for example , at least -40 ° C and/or at most 160 ° C . The operating temperature may be below the glass transition temperature of the clip body 5 .
The pressure profile P may then form in a fi fth step when the top metal disk 4 and the bottom metal disk 3 are pressed onto the semiconductor component 2 after the clip body 5 has been formed . This pressing is done , for example , by means of the pole pieces 71 , 72 . Accordingly, the pressure profile P may only be present after pressing the top metal disk 4 inside a housing, but the bent wafer shape of the semiconductor component 2 is present immediately after cooling down the semiconductor component 2 and the bottom metal disk 3 with finishing the molding process of the clip body 5 .
In Figure 7 , the displacement z in the case of Figure 6 when no force is applied on the components 71 , 4 is illustrated; this may apply in the case of no clamping force . At r = 0 , there is a maximum displacement z3 of the bottom metal disk 3 and a maximum displacement of the semiconductor component 2 . In the second region A2 , near rM with the circumferential maximum M, there is a relative minimum zN in the displacement of the semiconductor component 2 .
For example , 300 pm > z3 > zM > zN > 0 .
Otherwise , the same as to Figures 1 and 2 may also apply to Figures 3 to 7 , and vice versa .
In Figures 8 to 10 reference devices 9 are compared with embodiments of the semiconductor module 1 which is , for example , a FRD .
Figure 8 shows the capability of a 4 . 5 kV FRD when tested in continuous regime in a power converter, further called frequency test , F-test . The lowest ruggedness shows the free floating, FF, design concept with no clip body 5 as illustrated above . A ruggedness of the FF concept can be increased by increasing a clamping force from 40 kN to 50 kN . However, this represents an extra cost a customer, and it is not always possible.
The capability of the FF concept without increasing the clamping force can be improved if the semiconductor component 2, which is, for example, a silicon wafer, is attached to the bottom metal disk using the clip body 5 as a mold compound. A contact between the bottom main side 23 and the bottom metal disk 3 is still dry, but the pressure distribution from a wafer center to an edge is different. Its performance in the F-test is about equal at f = 300 Hz and about equal at f = 100 Hz compared with a reference device 9 in which the semiconductor component 2 and the bottom metal disk 3 are connected by means of LTB, if a proper EMC mold compound is used for the clip body 5, Figure 9. For example, the EMC KI has a higher CTE, a higher Tg and a lower E than the EMC K2.
Thus, in Figure 8, a last pass current Ip in an F-test of 4.5 kV FRDs with an area of 55 cm^ in a converter comprising an IGCT is illustrated. A DC link voltage is 2.85 kV, f = 100 Hz. Figure 9 illustrates a last pass current Ip of a diode in an F-test of 4.5 kV FRDs with an area of 55 cm^ in a converter comprising an IGCT. A DC link voltage is again 2.85 kV, f = 300 Hz. In this frequency, the EMC KI gives performance equal to that of the LTB design.
Similar improvement of the performance is observed during an AC blocking test, at 4.5 kV, 50 Hz, 5 s. A temperature range of stable blocking can be increased by +5 °C, that is, thermal stability can be increased, when using the design concept having the clip body 5 resulting in a different pressure distribution than in the standard LTB design. Thus , Figure 10 illustrates a thermal stability test of 4 . 5 kV FRDs with area of 55 cm^ . A voltage waveform is AC hal f sine at 4 . 5kV and f = 50 Hz , duration of the test is 5 s . The performance is improvement by 5 ° C for the semiconductor module 1 described herein compared with a corresponding LTB design, equal for both types of mold compound KI , K2 , resulting from di f ferent pressure distribution due to di f ferent bow .
Hence , the semiconductor module 1 described herein uses a controlled device warpage and/or bow to achieve the advantageous pressure distribution giving the best device ruggedness .
Figure 11 shows the di f ferences between wafer bows after attachment of a silicon wafer 2 with a diameter of 91 mm to a molybdenum disk 3 for LTB, right side , and the clip body 5 design, left side . The latter shows a distinct flattened region at the proximity of a wafer edge . In this case , the silicon wafer 2 is pressed to the molybdenum disk 3 in a wide region at the edge towards the center of the wafer 2 . As a result , there is more current flowing outside the wafer edge through a wider region with a lower resistance and lower Rfh j -c due to the higher pressure . The wafer edge of the design comprising the clip body 5 is less overheated and the module 1 does not fail in reverse blocking mode due to thermal runaway . It most likely might fail at reverse recovery, what happens at higher currents .
This is also illustrated in Figures 12 to 14 . While the FF design gives random shapes , the semiconductor module 1 described herein shows the relatively wide flattened region at wafer periphery and a lower bow of about 20 pm, see Figures 12 and 13 . The massive dome shaped bow of the LTB is the result of bonding two di f ferent materials together, and the resulting bow is about 60 pm, see Figure 14 .
Figure 15 shows pressure sensitive papers used in semiconductor modules 1 described herein and in reference devices 9 . A tighter hatching pattern represents a higher pressure . As can be seen from Figure 15 , left part , the pressure profile P in which the pressure p is low at the edge as well as in the center region C but its high in between .
Contrary to that , in the FF design without clip body 5 , see Figure 15 , middle part , the pressure profile P shows a higher pressure at the edge of the wafer than the semiconductor module 1 described herein and than the LTB reference device 9 shown in Figure 15 , right part .
Otherwise , the same as to Figures 1 to 7 may also apply to Figures 8 to 15 , and vice versa .
In the F-test , the wafers with a higher pressure at periphery may fail along the wafer edge typically during reverse blocking between switching events . The semiconductor module 1 described herein may fail mostly in switching mode during reverse recovery and a failure pattern may starts in the bulk as a result of current f ilamentation due to the NDR . A failure current may be close to that of the LTB design, which has a lower Rpp j _c over the whole wafer surface due to the bonding of the silicon wafer to the molybdenum disk .
Based on these findings , the concept of FRD back-end design described herein has a higher robustness during hard switching without using the conventional LTB technique to reduce cost and increase production yield . The methods to achieve the flat wide region along the wafer edge in the pressure profile P various methods can be used, for example , the clip body 5 described above ; further methods are described below . Thus , the locali zed reduction of the contact thermal resistance and electrical resistance at the desired location on the wafer surface may be achieved by a designed- in warpage of the wafer achieved from, for example :
- using a clip body 5 as discussed above ,
- using a waf er-to-molybdenum bonding at speci fic surface areas ,
- using bent metal disks , and/or
- using speci fic manufacturing parameters .
A reference device 9 using LTB is shown in Figure 16 . The conventional LTB concept involves deposition of a bond material 6 in-between the silicon wafer and the molybdenum disk and homogenous all-over the surface of the two parts being bonded . This results , due to thermal stress and coef ficient of thermal expansion, GTE , mismatch of the parts , in a dome shaped bow, as presented in Figure 14 .
On the contrary to this homogenous surface bonding, depositing the bond material 6 in-between the semiconductor component 2 and the bottom metal disk 3 only in speci fic and preferential areas is targeted, see Figures 17 to 23 , and a locali zed bond-line or a locali zed bond-interface is achieved . By doing so , a desired warpage of the wafer-moly package can be obtained . One should imagine a plurality of shapes and patterns formed by the bond material 6 , resulting in various three-dimensional deformations of the semiconductor component 2 and the bottom metal disk 3 . Various bond materials 6 may be used, like soldering pastes , silver pastes or silver sheets , resulting in a typical bond line thickness between 10 pm and 100 pm . Various bonding techniques may be used, such as LTB, brazing, sintering or soldering .
Structuring of the bond-line may be achieved by deposition of the bond material 6 at selective areas . This can be achieved, for example , by stencil printing or screen printing of a soldering or silver paste , or a trans fer of a silver sheet with a pre-defined shape .
Structuring of the bond-interface may be achieved, for example , by structured coating of the wafer with a thin ( compared to the bond line ) bonding or non-bonding metal layer, or structuring of the bond material 6 before the bond process , for example , by structured hot stamp pressing on the bond material 6 before the wafer-to-Mo bonding process , that sinters the bond material 6 in the respectively selected areas and prevents to sinter wafer-to-Mo in the following process ) .
By structuring a bond-line , a bonding material 6 is present only in the area of the bond between the semiconductor component 2 and the bottom metal disk 3 . By structuring a bond-interface , the bond material 6 is present all over the surface of the semiconductor component 2 and the bottom metal disk 3 , so that there is the bond material 6 and would mechanically, electrically and/or thermally support the structure , however, but there is no bond in the selected areas . According to the embodiment of Figure 17, the bond material 6 is limited to an outer region, and the central region C is free of the bond material 6. The bond material 6 may run to an edge of the semiconductor component 2. For example, a width of the bond material 6 is between 0.1 rO and 0.5 rO or between 0.15 rO and 0.3 rO, wherein rO is the radius of the bottom metal disk 3 and/or of the semiconductor component 2.
According to the embodiment of Figure 18, the bond material 6 is limited to the central region C, and the outer region is free of the bond material 6. The bond material 6 may thus cover the center of the semiconductor component 2. For example, the bond material 6 runs towards the edge up to at most 0.8 rO or up to at most 0.5 rO or up to at most 0.3 rO.
According to the embodiment of Figure 19, the bond material 6 is applied all over the semiconductor component 2. However, only at the outer region, there is a connection region 60 in which bonding between the semiconductor component 2 and the bottom metal disk 3 is achieved. In the center region C, there is a free floating region 62 in which no bonding is achieved between the semiconductor component 2 and the bottom metal disk 3 by means of the bond material 6. For example, in this case a width of the connection region 60 is between 0.1 rO and 0.5 rO or between 0.15 rO and 0.3 rO.
According to the embodiment of Figure 20, the bond material 6 is also applied all over the semiconductor component 2, however, the outer region corresponds to the free floating region 62 and the center region C is the connection region 60. For example, the connection region 60 runs towards the edge of the semiconductor component 2 up to at most 0.8 rO or up to at most 0.5 rO or up to at most 0.3 rO. In Figure 21 it is shown that there are two rings, like circles, of the bond material 6. For example, the outer ring starts at the edge of the semiconductor component 2. The center region C can be free of the bond material 6. For example, widths of the rings are between 0.05 rO and 0.4 rO or between 0.15 rO and 0.35 rO. The inner ring of the bond material 6 is located, for example, between 0.2 rO and
0.7 rO. Other than shown, as an option there can be an inner dot of the bond material 6 covering the center of the semiconductor component 2 and having, for example, a radius of at most 0.3 rO or of at most 0.15 rO.
According to Figure 22, there is the outer ring, like a circle, of the bond material, for example, analogous to
Figure 22. Further, there is a comparably large inner dot of the bond material. For example, a radius of the inner dot is at least 0.2 rO or at least 0.3 rO and/or is at most 0.8 rO or is at most 0.6 rO.
In Figure 23 it is illustrated that the bond material 6 corresponds to an outer ring starting, for example, at the edge of the semiconductor component 2. For example, a width of the ring of the bond material 6 is between 0.1 rO and 0.5 rO or between 0.2 rO and 0.4 rO.
As an option, said ring comprises a plurality of recesses 64.
A depth of the recesses 64 into the ring is, for example, at least 10% or at least 30% and/or at most 90% or at most 60% of the width of the ring. For example, there are at least five and/or at most 32 of the recesses 64. The recesses 64 may be arranged in an equidistant manner. According to Figure 24, the bond material 6 is applied as a dot in the center region C. For example, a radius of the dot is at least 0.2 rO or at least 0.3 rO and/or is at most 0.8 rO or is at most 0.6 rO.
As an option, said central dot comprises a plurality of dents 63. A radial extent of the dents 63 towards the edge of the semiconductor component 2 is, for example, at least 10% or at least 30% and/or at most 90% or at most 60% of the diameter of the dot. For example, there are at least five and/or at most 32 of the dents 63. The dents 63 may be arranged in an equidistant manner.
Also in the embodiments of Figures 23 and 24 there can be further rings or dots of the bond material 6.
According to Figures 21 to 24, the bond material 6 corresponds to the connection region 60, like in Figures 18 and 19. However, there can also be free floating regions 62 of the bond material in Figures 22 to 25 analogous to Figures 20 and 21.
In the embodiments of Figures 17 to 24 it is possible that the clip body 5 is additionally present.
Otherwise, the same as to Figures 1 to 15 may also apply to Figures 17 to 24, and vice versa.
In Figure 25 it is illustrated that the pressure profile P is achieved by the bottom pole piece 71 and/or by the top pole piece 72. In-between the pole pieces 71, 72, there is a space 74 for the metal disks 3, 4 and for the semiconductor component 2. Seen in cross-section, the pole pieces 71, 72 can be of hump fashion or double-hump fashion so that one or two thickness maxima can be present . Other than shown in Figure 25 it is not necessary that the thickness maxima exactly face one another, but that the thickness maxima are laterally displaced, for example , for at least 0 . 02 rO and/or for at most 0 . 2 rO .
Such non-planar pole pieces 71 , 72 can be combined with the clip body 5 and with the bond material 6 .
Hence , the same as to Figures 1 to 24 may also apply to Figure 25 , and vice versa .
In Figure 26 it is illustrated that the pressure profile P can be achieved by having di f ferent bonding conditions during, for example , applying the connection between the semiconductor component 2 and the bottom metal disk 3 by means of the bond material 6 . For example , a bonding pressure p and/or a bonding temperature T applied to the semiconductor component 2 and the bottom metal disk 3 and the bond material 6 during bonding increase towards an edge of the semiconductor component 2 . In the center region C and in the third region A3 , the pressure p and/or the temperature T may be nearly constant so that a rapid change in pressure and/or temperature T may occur in the second region A2 .
Such varied process parameters can also be combined with non- planar pole pieces 71 , 72 , with the clip body 5 and/or with the bond material 6 .
Otherwise , the same as to Figures 1 to 25 may also apply to Figure 26 , and vice versa . In Figure 27, a further exemplary pressure profile P is shown. For example, the pressure profile P can be approximated by the formula
P(r) = A / (l + B
Figure imgf000033_0001
+ F, for example, with a tolerance of at most 0.1 pM or of at most 0.05 pM.
In the specific embodiment of Figure 28, {A} = 0, 64, and B = -1, E = 5, and C = D = F = 0, wherein { } indicates a numeric value of the respective quantity value, and r is a unitless variable representing a distance to the local minimum and/or a center of the bottom metal disk 3 and/or the semiconductor component 2.
Such a pressure profile P as approximated by the above formula may apply to all embodiments of the semiconductor module 1.
Otherwise, the same as to Figures 1 to 26 may also apply to Figure 27, and vice versa.
In Figure 28, a manufacturing method for producing the semiconductor module 1 is schematically illustrated.
In a first method step SI, the semiconductor component 2 and the bottom metal disk 3 are provided.
In a second method step S2, the semiconductor component 2 is pressed onto the bottom metal disk 3 with a pressure profile. This step S2 may directly follow method step SI or may be done during installation of the semiconductor module 1 or occurs in the intended use of the semiconductor module 1, that is, under operation conditions. For example, directly after assembling the semiconductor component 2 onto the bottom metal disk 3 , there may be no such pressure profile P, but the desired pressure profile P may result later from operating the semiconductor module 1 as intended . Otherwise , the desired pressure profile P may be present immediately when assembling the semiconductor component 2 onto the bottom metal disk 3 .
In Figure 28 it is illustrated that step S2 can include substeps S21 , S22 or S23 , wherein steps S21 , S22 and S23 can be used in any combination . In step S21 , the clip body 5 is applied, for example , to result in the semiconductor module 1 of Figures 1 to 15 , see especially Figures 5 and 6 . In step S22 , the bond material 6 is applied, for example , to result in the semiconductor module 1 of Figures 17 to 24 . Step S22 may include providing method parameters in treating the bond material 6 as illustrated in connection with Figure 26 . In step S23 , the pole pieces 71 , 72 are provided, for example , to result in the semiconductor module 1 of Figure 25 .
Otherwise , the same as to Figures 1 to 27 may also apply to Figure 28 , and vice versa .
Thus , the semiconductor module 1 described herein may be an FRD with a defined profile of a bow and a respective pressure distribution over the wafer interface between the silicon wafer and molybdenum strain buf fer . Hence , an FRD with high robustness in hard switching conditions without using the conventional LTB technique can be achieved . Usage of silver contaminant can be eliminated and reduced cost of the process can be obtained . Optionally, the LTB process with spatial adj ustment of the pressure distribution along the wafer when structuring the bond material 6 can be used, too . Thus , a new generation of FRDs with high robustness in hard switching condition is provided . There is the possibility to utili ze the new design on new FRDs with larger areas than exist today .
Hence , the semiconductor module 1 described herein has a defined spatial distribution of pressure at the silicon wafer 2 - molybdenum disk 3 interface . Optionally, the silicon wafer 2 and the molybdenum disk 3 are attached together by a clip body, forming a desired three-dimensional deformation, warpage or bow of a resulting package . Optionally, the silicon wafer 2 and the molybdenum disk 3 are bonded together, by a bond material 6 , present at the interface with a speci fic pattern and thus forming a desired three- dimensional deformation, warpage or bow of the package , or by using any bonding technique , such as low temperature bonding, sintering, soldering or brazing . The bond material 6 between the silicon wafer 2 and the molybdenum disk 3 may be a silver- , lead- , copper- , tin- , bismuth- , indium- , zinc- , antimony- , aluminum- , nickel-containing material .
The components shown in the figures follow, unless indicated otherwise , exemplarily in the speci fied sequence directly one on top of the other . Components which are not in contact in the figures are exemplarily spaced apart from one another . I f lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another . Likewise , unless indicated otherwise , the positions of the drawn components relative to one another are correctly reproduced in the figures .
The semiconductor module described here is not restricted by the description on the basis of the exemplary embodiments . Rather, the semiconductor module encompasses any new feature and also any combination of features , which includes in particular any combination of features in the patent claims , even i f this feature or this combination itsel f is not explicitly speci fied in the patent claims or exemplary embodiments .
Reference Signs
1 semiconductor module
2 semiconductor component
23 bottom main side
24 top main side
25 void
3 bottom metal disk
30 bottom metal disk top side
4 top metal disk
5 clip body
52 top part
53 lateral part
6 bond material
60 connection region
62 free floating region
63 dent
64 recess
71 bottom pole piece
72 top pole piece
73 adj ustment structure
74 space for semiconductor component and metal disks
8 pressure sensitive paper
9 reference device
A. . region
C central region
FF free floating device
Ip last pass current in A or kA
K . . plastics material
L covering width
LTB low-temperature bonding device
M circumferential maximum of the pressure profile N1 local minimum in the central region of the pressure profile
N2 circumferential minimum of the pressure profile
P pressure profile p pressure r radius rO radius of the bottom metal disk
SR silicone rubber
Tp last pass temperature in ° C z displacement zM maximum absolute bending zN relative minimum bending

Claims

Patent Claims
1. A method for producing a semiconductor module (1) comprising the following steps:
- providing a semiconductor component (2) configured for voltages of at least 0.6 kV and having a bottom main side (23) and an opposite top main side (24) ,
- providing a bottom metal disk (3) and a top metal disk (4) , and
- pressing the semiconductor component (2) onto the bottom metal disk (3) with a preconfigured inhomogeneous pressure profile (P) , wherein
- the bottom main side (23) faces the bottom metal disk (3) and the top main side (24) faces the top metal disk (4) and the semiconductor component (2) is located directly between the bottom metal disk (3) and the top main side (24) ,
- the method further comprises forming a clip body (5) which surrounds the semiconductor component (2) in a lateral direction which is in parallel with the bottom main side (23) and which partially covers the top main side (24) ,
- the clip body (5) is in direct contact with the bottom metal disk ( 3 ) ,
- the clip body (5) is made of plastics,
- the clip body (5) and the top metal disk (4) press the semiconductor component (2) onto the bottom metal disk (3) , and,
- seen in top view of the bottom main side (23) , the pressure profile (P) has a local minimum (Nl) in a central region (C) of the semiconductor component (2) which is surrounded by a circumferential maximum (M) of the pressure profile (P) , and the circumferential maximum (M) is surrounded by a circumferential minimum (N2) of the pressure profile (P) , the pressure profile (P) is present in the finished semiconductor module (1) when being operated.
2. The method according to the preceding claim, wherein the bottom metal disk (3) has a radius rO, and a position rM of the circumferential maximum (M) of the pressure profile (P) is between 0.5 rO and 0.9 rO, wherein a radius rS of the semiconductor component is between 0.8 rO and rO and rM is smaller than rS, and wherein for a pressure pNl of the local minimum (Nl) in the central region (C) , a pressure pM of the circumferential maximum (M) and a pressure pN2 of the circumferential minimum
(N2) the following applies:
0,1 pM < pN2 < 0.4 pM < pNl < 0,9 pM.
3. The method according to the preceding claim, wherein, seen in cross-section through the local minimum (Nl) and through the semiconductor component (2) , the pressure profile (P) can be approximated as follows: P(r) = A / (1 + B r2 + C r4 + D r6 + E r8) + F, wherein r is a numeric value of a distance to the local minimum (Nl) , wherein A/pM and F/pM as well as at least one of C, D and E are positive numbers, and wherein B is a negative number.
4. The method according to the two preceding claims, wherein P(r) = A / ( 1 + B r2 + C r4 + D r 8 + E r8) + F is true for {-rS} < r < {rS} with a tolerance of at most 0.1 pM, wherein 0.25 pM < A < pM and -2 < B < -0.5 and 0 < C d 2 and 0 < D < 6 and 0 < E < 10 and 0 < F < 0.3 pM.
5. The method according to any one of the preceding claims, wherein the clip body (5) is manufactured at a temperature between 130 °C and 260 °C when a material the clip body (5) is made from is initially in a liquid state.
6. The method according to any one of the preceding claims, wherein, seen in top view of the bottom main side (23) , the circumferential maximum (M) of the pressure profile (P) is located within an opening in the clip body (5) so that the circumferential maximum (M) is not covered by the clip body (5) , wherein a part of the clip body (5) on the top main side (24) acts as a lever that presses the semiconductor component (2) onto the bottom metal disk (3) , and wherein the clip body (5) terminates distant from the top metal disk (4) so that the clip body (5) and the top metal disk (4) do not touch.
7. The method according to any one of the preceding claims, wherein the semiconductor component (2) is bent when the arrangement including the clip body (5) , the semiconductor component (2) and the bottom metal disk (3) is cooled down from a manufacturing temperature of the clip body (5) back to room temperature, that is, 23 °C.
8. The method according to any one of the preceding claims, wherein the pressure profile (P) forms when the top metal disk (4) and the bottom metal disk (3) are pressed onto the semiconductor component (2) after the clip body (5) has been formed .
9. The method according to any one of the preceding claims, wherein an operating temperature of the finished semiconductor module (1) is between -40 °C and 160 °C inclusive, wherein the clip body (5) is a solid body at the operating temperature.
10. The method according to the preceding claim, wherein the semiconductor component (2) is bent at at least one of room temperature, that is, at 23 °C, or the operating temperature, and seen in cross-section perpendicular to the bottom main side (23) , a bending profile has a maximum in the central region (C) between two adjacent inflection points and a flat region along a rim of the semiconductor component (2) , wherein a maximum relative bending of the semiconductor component (2) is at most 3 x 10-^, the maximum relative bending is a maximum absolute bending divided by a diameter of the semiconductor component (2) .
11. A semiconductor module (1) comprising:
- a semiconductor component (2) configured for voltages of at least 0.6 kV and having a bottom main side (23) and an opposite top main side (24) ,
- a clip body (5) made of a plastics,
- a top metal disk (4) facing the top main side (24) , and
- a bottom metal disk (3) onto which the semiconductor component (2) is pressed with a pressure profile (P) , the bottom main side (23) faces the bottom metal disk (3) , wherein, seen in top view of the bottom main side (23) , the pressure profile (P) has a local minimum (Nl) in a central region (C) of the semiconductor component (2) which is surrounded by a circumferential maximum (M) of the pressure profile (P) , and the circumferential maximum (M) is surrounded by a circumferential minimum (N2) of the pressure profile (P) , wherein the semiconductor component (2) is located directly between the bottom metal disk (3) and the top main side (24) ,
- the clip body (5) partially covers the top main side (24) ,
- the clip body (5) is in direct contact with the bottom metal disk (3) , and
- the clip body (5) and the top metal disk (4) press the semiconductor component (2) onto the bottom metal disk (3) .
12. The semiconductor module (1) according to the preceding claim, wherein between the semiconductor component (2) and the bottom metal disk (3) there is at least in places at least one free floating region (62) in which the semiconductor component (2) is free floating relative to the bottom metal disk ( 3 ) .
13. The semiconductor module (1) according to any one of the two preceding claims, wherein a diameter of the top metal disk (4) is smaller than a diameter of the semiconductor component (2) , wherein, seen in top view of the top main side (24) , the circumferential maximum (M) of the pressure profile (P) is covered by the top metal disk (4) .
14. The semiconductor module (1) according to the preceding claim, wherein at least one of the bottom metal disk (3) and the top metal disk (4) comprises a bow configured to provide the pressure profile (P) .
15. The semiconductor module (1) according to any one of the four preceding claims, wherein the semiconductor component (2) is selected from the following group: an injection enhanced gate transistor, a metal-oxide-semiconductor field-effect transistor, a metalinsulator-semiconductor field-effect transistor, an insulated-gate bipolar transistor, a bipolar junction transistor, a thyristor, a junction gate field-effect transistor, wherein a width of the semiconductor component (2) is at least 25 mm and is at most 25 cm.
PCT/EP2023/052315 2022-02-14 2023-01-31 Method and semiconductor module WO2023151987A1 (en)

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EP22156536 2022-02-14

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2115549A5 (en) * 1970-11-24 1972-07-07 Silec Semi Conducteurs
US4358785A (en) * 1979-03-13 1982-11-09 Tokyo Shibaura Denki Kabushiki Kaisha Compression type semiconductor device
WO2020078816A1 (en) 2018-10-19 2020-04-23 Abb Schweiz Ag Power semiconductor device with free-floating packaging concept

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2115549A5 (en) * 1970-11-24 1972-07-07 Silec Semi Conducteurs
US4358785A (en) * 1979-03-13 1982-11-09 Tokyo Shibaura Denki Kabushiki Kaisha Compression type semiconductor device
WO2020078816A1 (en) 2018-10-19 2020-04-23 Abb Schweiz Ag Power semiconductor device with free-floating packaging concept

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