WO2023145558A1 - Substrate-processing device and substrate-processing method - Google Patents
Substrate-processing device and substrate-processing method Download PDFInfo
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- WO2023145558A1 WO2023145558A1 PCT/JP2023/001289 JP2023001289W WO2023145558A1 WO 2023145558 A1 WO2023145558 A1 WO 2023145558A1 JP 2023001289 W JP2023001289 W JP 2023001289W WO 2023145558 A1 WO2023145558 A1 WO 2023145558A1
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- protective film
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
Definitions
- the present disclosure relates to a substrate processing apparatus and a substrate processing method.
- the chip mounting system described in Patent Document 1 includes a chip supply device, a bonding device, a surface treatment device, a loading/unloading section, and a transport section (paragraph [0225] of Patent Document 1).
- the chip supply device holds a plurality of chips and individually supplies the chips to be joined.
- the bonding device attaches the chips supplied from the chip supply device onto the substrate.
- the surface treatment apparatus performs surface activation treatment and hydrophilization treatment on the bonding surfaces of the plurality of chips and the substrate.
- the loading/unloading section loads a chip and a substrate to be bonded from the outside of the chip mounting system into the inside thereof, and carries out the substrate on which the chip is attached (the structure including the chip and the substrate) to the outside.
- the transport unit transports a plurality of chips, substrates, and a structure including chips and substrates between the loading/unloading unit, the chip supply device, the bonding device, and the surface treatment device.
- a dicing process is performed to generate a plurality of chips (paragraph [0248] of Patent Document 1).
- a plurality of diced chips are placed on a dicing tape (paragraph [0250] of Patent Document 1).
- One aspect of the present disclosure provides a technique for improving the quality of substrates with chips.
- a substrate processing apparatus includes a pickup section, a removal section, and a mount section.
- the pickup part separates the chips from the tape in a state in which a plurality of chips are attached to the frame via a tape and a protective film is formed on the first main surface of the chips opposite to the tape.
- the removal unit removes the protective film from the chip after the chip is separated from the tape by the pickup unit.
- the mounting section mounts the chip on the substrate with the first main surface of the chip facing the substrate after the protective film is removed by the removing portion.
- FIG. 1 is a plan view showing a substrate processing apparatus according to one embodiment.
- 2A is a cross-sectional view showing an example of a substrate
- FIG. 2B is a cross-sectional view showing an example of a chip
- FIG. 2C is a cross-sectional view showing an example of chip pick-up
- FIG. 2D is a cross-sectional view showing an example of a substrate with a chip.
- FIG. 3 is a flowchart illustrating a substrate processing method according to one embodiment.
- 4A is a plan view showing an example of the motion of the first frame transfer arm
- FIG. 4B is a plan view showing an example of the motion of the first frame transfer arm following FIG. 4A. be.
- FIG. 4A is a plan view showing an example of the motion of the first frame transfer arm following FIG. 4A. be.
- FIG. 5 is a cross-sectional view showing an example of the tip cleaning section.
- FIG. 6 is a cross-sectional view showing an example of an expanded portion.
- FIG. 7 is a cross-sectional view showing an example of a second processing station.
- FIG. 8 is a cross-sectional view showing an example of lamination of dummy chips.
- FIG. 9 is a cross-sectional view showing an example of an inspection unit.
- FIG. 10 is a cross-sectional view showing an example of the chip peeling portion.
- FIG. 11A is a cross-sectional view showing an example of a blade
- FIG. 11B is a cross-sectional view showing an example of a heater and a cooler.
- FIG. 12(A) is a cross-sectional view showing an example of a seal and a nozzle
- FIG. 12(B) is a cross-sectional view showing an example of a push-up pin
- FIG. 13 is a cross-sectional view showing an example of a rework portion.
- FIG. 14 is a plan view showing a substrate processing apparatus according to the first modified example.
- FIG. 15 is a plan view showing a substrate processing apparatus according to a second modified example.
- 16A is a cross-sectional view showing a modification of the substrate shown in FIG. 2A
- FIG. 16B is a cross-sectional view showing an example of the second chip
- FIG. FIG. 16D is a cross-sectional view showing an example of picking up a chip
- FIG. 16D is a cross-sectional view showing a modification of the chip-attached substrate shown in FIG. 2D.
- FIG. 17A is a cross-sectional view showing another modification of the substrate with chips shown in FIG. 2D
- FIG. 17C is a cross-sectional view showing an example of post-processing following FIG. 17B
- FIG. 17D is a cross-sectional view showing an example of post-processing following FIG. It is a sectional view showing.
- FIG. 18 is a plan view showing a substrate processing apparatus according to a third modified example.
- 19A is a cross-sectional view showing an example of a chip protected by a protective film
- FIG. 19B is a cross-sectional view showing an example of pickup of the chip shown in FIG. 19A.
- FIG. 19C is a cross-sectional view showing an example of mounting the chip shown in FIG. 19B;
- FIG. 20 is a cross-sectional view showing an example of the second processing station shown in FIG. 18.
- FIG. 21A is a cross-sectional view showing an example of particles
- FIG. 21B is a cross-sectional view showing an example of supply of stripping solution
- FIG. 21C is a cross-sectional view showing an example of stripping of a protective film.
- FIG. 21D is a cross-sectional view showing an example of dissolution of the protective film.
- FIG. 22 is a cross-sectional view showing an example of the application section.
- the X-axis direction, the Y-axis direction, and the Z-axis direction are directions perpendicular to each other.
- the X-axis direction and Y-axis direction are horizontal directions, and the Z-axis direction is vertical direction.
- a substrate processing apparatus 1 will be described with reference to FIGS. As shown in FIGS. 2A to 2D, the substrate processing apparatus 1 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1, thereby forming a substrate CW1 with chips. manufacture.
- the pasting area is set in advance.
- a substrate CW1 with chips includes a substrate W1 and a plurality of chips CP1 bonded to the substrate W1. Although not shown, another chip may be stacked on each chip CP1.
- a substrate W1 shown in FIG. 2(A) is loaded into the substrate processing apparatus 1.
- the substrate W1 has an underlying substrate W1a and a plurality of devices W1b formed on the underlying substrate W1a.
- the underlying substrate W1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate.
- Device W1b includes a semiconductor element, a circuit, a terminal, or the like.
- the device W1b is formed on the main surface W1c.
- a plurality of chips CP1 are adhered to a tape TP1, and the outer circumference of the tape TP1 is attached to the frame FR1.
- a plurality of chips CP1 are arranged in the opening of the frame FR1.
- the plurality of chips CP1 can be obtained, for example, by dicing the substrate while the substrate is adhered to the tape TP1.
- the chip CP1 has a base substrate CP1a and a device CP1b formed on the base substrate CP1a.
- the underlying substrate CP1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate.
- Device CP1b includes a semiconductor element, a circuit, a terminal, or the like.
- the device CP1b is arranged on the side opposite to the tape TP1 with respect to the base substrate CP1a.
- the pickup unit 53 separates the plurality of chips CP1 individually from the tape TP1. After that, the chip CP1 is turned upside down and then bonded to the substrate W1 as shown in FIG. 2(D). The device W1b on the substrate W1 and the device CP1b on the chip CP1 are electrically connected. Thus, a chip-equipped substrate CW1 is obtained.
- the substrate W1 that constitutes the chip-equipped substrate CW1 may not have the device W1b. That is, the substrate W1 does not have to have an electric circuit.
- the substrate W1 consists of only a silicon wafer, a compound semiconductor wafer, or a glass substrate.
- the substrate W1 and the substrate W2 are bonded with the plurality of chips CP1 interposed therebetween.
- FIG. 17C the plurality of chips CP1 and substrate W1 are separated, and finally, as shown in FIG. spliced.
- the substrate W3 has an underlying substrate W3a and a plurality of devices W3b formed on the underlying substrate W3a.
- the device W3b on the substrate W3 and the device CP1b on the chip CP1 are electrically connected.
- the substrate processing apparatus 1 includes a loading/unloading station 2, a first processing station 3, an interface block 4, a second processing station 5, and a controller 9.
- the loading/unloading station 2, the first processing station 3, the interface block 4, and the second processing station 5 are arranged in this order from the X-axis negative direction side to the X-axis positive direction side.
- the loading/unloading station 2 includes a mounting table 20 .
- Cassettes C1 to C4 are mounted on the mounting table 20.
- the cassette C1 accommodates the substrate W1 shown in FIG. 2(A).
- the cassette C2 accommodates the chip-attached substrate CW1 shown in FIG. 2(D).
- the cassette C3 accommodates a plurality of chips CP1 together with the frame FR1 shown in FIG. 2(B).
- a cassette C4 accommodates a used frame FR1 (not shown).
- the used frame FR1 is the frame FR1 remaining after the plurality of chips CP1 are separated from the tape TP1.
- a chip CP1 may remain in the used frame FR1.
- the loading/unloading station 2 includes a transport area 21 , a third substrate transport arm 22 and a third frame transport arm 23 .
- the transport area 21 is adjacent to the mounting table 20 .
- the third substrate transport arm 22 holds and transports the substrate W1 in the transport area 21 .
- the third frame transport arm 23 holds and transports the frame FR1 in the transport area 21 .
- the third substrate transfer arm 22 and the third frame transfer arm 23 are each capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.
- the loading/unloading station 2 has a drive section (not shown) that moves or rotates the third substrate transfer arm 22 and the third frame transfer arm 23 .
- the third substrate transfer arm 22 and the third frame transfer arm 23 may be mounted on the same Y-axis slider and moved in the Y-axis direction at the same time, or may be mounted on different Y-axis sliders and moved in the Y-axis direction independently. may be The third substrate transfer arm 22 and the third frame transfer arm 23 are stacked in the Z-axis direction when mounted on the same Y-axis slider. When the third substrate transfer arm 22 and the third frame transfer arm 23 are mounted on different Y-axis sliders, the Y-axis sliders are shifted in the Z-axis direction.
- the third substrate transport arm 22 takes out the substrate W1 before bonding the chip CP1 from the cassette C1 and transports it to the substrate platform 24 . Further, the third substrate transport arm 22 takes out the substrate CW1 with chips from the substrate mounting portion 24 and stores it in the cassette C2.
- the third substrate transfer arm 22 that transfers the substrate W1 before bonding the chip CP1 thereto and the third substrate transfer arm 22 that transfers the substrate CW1 with the chip may be provided separately.
- the third frame transport arm 23 takes out the plurality of chips CP1 together with the frame FR1 from the cassette C3 and transports them to the frame mounting section 25. Also, the third frame transfer arm 23 takes out the used frame FR1 from the frame placing portion 25 and stores it in the cassette C4.
- the third frame transfer arm 23 that transfers the plurality of chips CP1 together with the frame FR1 and the third frame transfer arm 23 that transfers the used frame FR1 may be provided separately.
- the loading/unloading station 2 includes a substrate loading section 24 and a frame loading section 25 .
- the substrate rest 24 and the frame rest 25 are arranged between the transport area 21 of the loading/unloading station 2 and the transport area 30 of the first processing station 3 and are adjacent to both transport areas 21 , 30 .
- the substrate rest 24 and the frame rest 25 may be vertically stacked to reduce the footprint of the loading/unloading station 2 .
- the substrate W1 before bonding the chip CP1 is mounted on the substrate mounting portion 24.
- a substrate CW ⁇ b>1 with a chip may be placed on the substrate placement part 24 .
- the substrate mounting portion 24 on which the substrate W1 before bonding the chip CP1 is mounted and the substrate mounting portion 24 on which the substrate CW1 with chips is mounted may be provided separately, or a plurality of each may be provided. may be
- a plurality of chips CP1 are mounted on the frame mounting portion 25 together with the frame FR1.
- a used frame FR ⁇ b>1 may be placed on the frame placement portion 25 .
- the frame mounting portion 25 on which the plurality of chips CP1 are mounted together with the frame FR1 and the frame mounting portion 25 on which the used frames FR1 are mounted may be provided separately, or a plurality of each may be provided. good too.
- the first processing station 3 includes a transfer area 30 , a first substrate transfer arm 31 and a first frame transfer arm 32 .
- the transport area 30 extends in the X-axis direction.
- the first substrate transport arm 31 holds and transports the substrate W ⁇ b>1 in the transport area 30 .
- the first frame transport arm 32 holds and transports the frame FR1 in the transport area 30 .
- the first substrate transfer arm 31 and the first frame transfer arm 32 are each capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.
- the first processing station 3 has a drive section (not shown) that moves or rotates the first substrate transfer arm 31 and the first frame transfer arm 32 .
- the first substrate transfer arm 31 and the first frame transfer arm 32 may be mounted on the same X-axis slider and moved in the X-axis direction at the same time, or may be mounted on different X-axis sliders and moved in the X-axis direction independently. may be The first substrate transfer arm 31 and the first frame transfer arm 32 are stacked in the Z-axis direction when mounted on the same X-axis slider. When the first substrate transfer arm 31 and the first frame transfer arm 32 are mounted on different X-axis sliders, the plurality of X-axis sliders are shifted in the Z-axis direction.
- the first substrate transport arm 31 takes out the substrate W1 before bonding the chip CP1 from the substrate mounting part 24, passes through the surface modification part 34 and the substrate cleaning part 35, and transfers it to the first buffer part of the interface block 4. Transport to 41.
- the first substrate transport arm 31 also takes out the substrate CW1 with chips from the first buffer unit 41 and places it on the substrate placement unit 24 of the loading/unloading station 2 via the inspection unit 36 and the like.
- the first substrate transfer arm 31 that transfers the substrate W1 before bonding the chip CP1 thereto and the first substrate transfer arm 31 that transfers the substrate CW1 with the chip may be provided separately.
- the first frame transport arm 32 takes out the plurality of chips CP1 together with the frame FR1 from the frame mounting part 25 and transports them to the second buffer part 42 of the interface block 4 via the chip cleaning part 33 . Also, the first frame transfer arm 32 takes out the used frame FR1 from the second buffer section 42 and places it on the frame placement section 25 of the loading/unloading station 2 .
- the first frame transfer arm 32 that transfers the plurality of chips CP1 together with the frame FR1 and the first frame transfer arm 32 that transfers the used frame FR1 may be provided separately.
- the first processing station 3 includes a chip cleaning section 33 , a surface modification section 34 , a substrate cleaning section 35 , an inspection section 36 , a chip peeling section 37 , a rework section 38 and an annealing section 39 .
- the chip cleaning section 33, the surface modification section 34, the substrate cleaning section 35, the inspection section 36, the chip peeling section 37, the rework section 38, and the annealing section 39 are adjacent to the transfer area 30, It is arranged on the Y-axis positive direction side or the Y-axis negative direction side of the transport area 30 .
- the chip cleaning unit 33 cleans the plurality of chips CP1 in a state in which the plurality of chips CP1 are adhered to the tape TP1 and the outer periphery of the tape TP1 is attached to the frame FR1. By bonding the chip CP1 to the substrate W1 after cleaning the chip CP1, it is possible to prevent foreign matter from entering.
- the details of the chip cleaning unit 33 will be described later.
- the surface modification unit 34 plasma-processes the main surface W1c of the substrate W1.
- the oxygen gas which is the processing gas
- the processing gas is excited under reduced pressure to be plasmatized and ionized.
- the processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.
- the substrate cleaning section 35 cleans the main surface W1c of the substrate W1.
- the substrate cleaning unit 35 supplies pure water (for example, deionized water) onto the substrate W1 while rotating the substrate W1 held by the spin chuck.
- the pure water spreads over the entire main surface W1c due to centrifugal force and washes the main surface W1c.
- Pure water imparts OH groups to the main surface W1c that has been modified in advance.
- the substrate W1 and the chip CP1 can be bonded using hydrogen bonding between OH groups.
- the inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad.
- the inspection items include at least one of presence/absence of foreign matter such as air bubbles and presence/absence of misalignment. For example, if a bubble exists at the interface between the substrate W1 and the chip CP1, the bubble bursts when the chip-attached substrate CW1 is vacuum-processed. Due to the bursting of the air bubbles, even the chip CP1, which is in a good state of bonding, may cause problems, or the vacuum chamber may be contaminated.
- the chip peeling unit 37 peels off the chip CP1, which was found to be in a defective bonding state in the inspection by the inspection unit 36, from the substrate W1. By peeling off the chip CP1, which is in a poorly bonded state, from the substrate W1, the problem caused when air bubbles or particles are present at the interface between the substrate W1 and the chip CP1 can be solved, and the quality of the substrate CW1 with the chip can be improved.
- the chip CP1 separated from the substrate W1 may be reused or discarded. Details of the chip peeling portion 37 will be described later.
- the rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off by the chip peeling unit 37 on the main surface W1c of the substrate W1. This process is a process of returning the bonding region from which the chip CP1 has been peeled off to the state immediately before bonding the chip CP1.
- the rework unit 38 selectively supplies at least one of plasma and water to the bonding region from which the chip CP1 has been removed. Details of the rework unit 38 will be described later.
- the annealing section 39 heats the chip-equipped substrate CW1.
- the chip CP1 and the substrate W1 are bonded by hydrogen bonding between OH groups.
- the heat treatment causes a dehydration-condensation reaction and a covalent bond, thereby improving the bonding strength between the chip CP1 and the substrate W1.
- the chip CP ⁇ b>1 is peeled off by the chip peeling unit 37 before the chip-attached substrate CW ⁇ b>1 is heat-treated by the annealing unit 39 .
- the interface block 4 is adjacent to the transport area 30 of the first processing station 3 .
- the interface block 4 includes a first buffer section 41 , a second buffer section 42 , a second substrate transfer arm 43 and a second frame transfer arm 44 .
- the first buffer section 41 and the second buffer section 42 are adjacent to the transport area 30 of the first processing station 3 .
- the first buffer section 41 and the second buffer section 42 may be vertically stacked to reduce the footprint of the interface block 4 .
- the first buffer unit 41 stores the substrate W1 before bonding the chip CP1.
- the first buffer section 41 may store the chip-equipped substrate CW1.
- the first buffer section 41 that stores the substrate W1 before bonding the chip CP1 thereto and the first buffer section 41 that stores the substrate CW1 with the chip may be provided separately, or a plurality of each may be provided. .
- the second buffer unit 42 stores a plurality of chips CP1 together with the frame FR1.
- the second buffer section 42 may store the used frame FR1.
- the second buffer section 42 that stores the plurality of chips CP1 together with the frame FR1 and the second buffer section 42 that stores the used frame FR1 may be provided separately, or a plurality of each may be provided.
- the second substrate transport arm 43 takes out the substrate W1 before bonding the chip CP1 from the first buffer unit 41 and transports it to the substrate holding unit 51 of the second processing station 5 .
- the second substrate transport arm 43 may transport the substrate CW1 with chips from the substrate holding section 51 to the first buffer section 41 .
- the second substrate transfer arm 43 is capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.
- the second substrate transport arm 43 that transports the substrate W1 before bonding the chip CP1 thereto and the second substrate transport arm 43 that transports the substrate CW1 with the chip may be provided separately.
- the second frame transport arm 44 takes out the plurality of chips CP1 together with the frame FR1 from the second buffer section 42 and transports them to the chip holding section 52 of the second processing station 5 .
- the second frame transport arm 44 may transport the used frame FR1 from the chip holding section 52 to the second buffer section 42 .
- the second frame transfer arm 44 is capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.
- the second frame transfer arm 44 that transfers the plurality of chips CP1 together with the frame FR1 and the second frame transfer arm 44 that transfers the used frame FR1 may be provided separately.
- the interface block 4 has a drive section (not shown) that moves or rotates the second substrate transfer arm 43 and the second frame transfer arm 44 .
- the second substrate transfer arm 43 and the second frame transfer arm 44 may be moved simultaneously in a predetermined direction, or may be moved independently in a predetermined direction.
- the second substrate transfer arm 43 and the second frame transfer arm 44 are not stacked in the Z-axis direction in FIGS. 1 and 2, they may be stacked in the Z-axis direction.
- the interface block 4 stores a substrate W1 that has undergone pretreatment (for example, surface modification and cleaning) and a plurality of chips CP1 that have undergone pretreatment (for example, cleaning).
- pretreatment for example, surface modification and cleaning
- chips CP1 that have undergone pretreatment
- the interface block 4 may be omitted, and the first processing station 3 and the second processing station 5 may be adjacent to each other.
- the first substrate transport arm 31 of the first processing station 3 transports the substrate W1 before bonding the chip CP1 to the substrate holding unit 51 of the second processing station 5, and the substrate CW1 with chips is transferred to the substrate holding unit.
- the first frame transport arm 32 of the first processing station 3 transports the plurality of chips CP1 together with the frame FR1 to the chip holding section 52 of the second processing station 5, and transfers the used frame FR1 to the chip holding section. Received from 52.
- the second processing station 5 is arranged on the opposite side of the transfer area 30 of the first processing station 3 with respect to the interface block 4 .
- the second processing station 5 includes a substrate holding section 51 , a chip holding section 52 , a pickup section 53 and a mounting section 54 .
- the substrate holding part 51 holds the substrate W1.
- the chip holding unit 52 holds the plurality of chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1.
- the substrate holding part 51 and the chip holding part 52 are each capable of horizontal movement (both the X-axis direction and the Y-axis direction) and rotation about the vertical axis.
- the pickup unit 53 separates the chip CP1 held by the chip holding unit 52 from the tape TP1.
- the mounting unit 54 mounts the chip CP1 separated from the tape TP1 by the pickup unit 53 onto the main surface W1c of the substrate W1. Details of the second processing station 5 will be described later.
- a chip bonding section 6 is composed of the interface block 4 and the second processing station 5 .
- the chip bonding section 6 is adjacent to the transfer area 30 of the first processing station 3 .
- the interface block 4 may be omitted, and the chip bonding section 6 may be composed of only the second processing station 5 .
- the control unit 9 is, for example, a computer, and includes a CPU (Central Processing Unit) 91 and a storage medium 92 such as a memory.
- the storage medium 92 stores programs for controlling various processes executed in the substrate processing apparatus 1 .
- the control unit 9 controls the operation of the substrate processing apparatus 1 by causing the CPU 91 to execute programs stored in the storage medium 92 .
- a unit controller for controlling the operation of each unit constituting the substrate processing apparatus 1 may be provided, and a system controller for integrally controlling a plurality of unit controllers may be provided.
- the control section 9 may be configured by the unit control section and the system control section.
- FIG. 3 The processing in FIG. 3 is performed under the control of the control unit 9 .
- the third substrate transfer arm 22 of the loading/unloading station 2 takes out the substrate W1 from the cassette C1 and transfers it to the substrate platform 24 .
- the first substrate transport arm 31 of the first processing station 3 takes out the substrate W1 from the substrate platform 24 and transports it to the surface modification unit 34 .
- the surface modification unit 34 plasma-processes the main surface W1c of the substrate W1 (step S101).
- the first substrate transfer arm 31 takes out the substrate W ⁇ b>1 from the surface modification section 34 and transfers it to the substrate cleaning section 35 .
- the substrate cleaning section 35 cleans the main surface W1c of the substrate W1 (step S102).
- the first substrate transport arm 31 takes out the substrate W1 from the substrate cleaning section 35 and transports it to the first buffer section 41 of the interface block 4 .
- the second substrate transfer arm 43 takes out the substrate W1 from the first buffer section 41 and transfers it to the substrate holding section 51 of the second processing station 5 .
- the third frame transfer arm 23 of the loading/unloading station 2 takes out a plurality of chips CP1 together with the frame FR1 from the cassette C3, and transfers them to the frame mounting section 25.
- the first frame transfer arm 32 of the first processing station 3 takes out the plurality of chips CP1 together with the frame FR1 from the frame mounting section 25 and transfers them to the chip cleaning section 33 .
- the chip cleaning unit 33 cleans the multiple chips CP1 (step S103).
- the first frame transport arm 32 takes out the plurality of chips CP1 together with the frame FR1 from the chip cleaning section 33 and transports them to the second buffer section 42 of the interface block 4 .
- the second frame transport arm 44 takes out the plurality of chips CP1 together with the frame FR1 from the second buffer section 42 and transports them to the chip holding section 52 of the second processing station 5 .
- the chip bonding section 6 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1 (step S104).
- a chip-equipped substrate CW1 is obtained.
- the second substrate transport arm 43 takes out the substrate CW1 with chips from the substrate holding section 51 and transports it to the first buffer section 41 .
- the first substrate transfer arm 31 of the first processing station 3 takes out the chip-attached substrate CW1 from the first buffer section 41 and transfers it to the inspection section 36 .
- the inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad (step S105).
- the inspection unit 36 transmits inspection results to the control unit 9 .
- the control unit 9 checks whether there is a defect (step S106).
- the control unit 9 performs control to sort the transfer destination of the substrate CW1 with chips between the annealing unit 39 and the chip peeling unit 37 according to the inspection result by the inspection unit 36 .
- the destination of the chip-attached substrate CW1 is the chip peeling section 37.
- the first substrate transport arm 31 takes out the substrate CW1 with chips from the inspection section 36 and transports it to the chip peeling section 37 .
- the chip peeling unit 37 peels off the chip CP1, which was in a defective bonding state, from the substrate W1 (step S107).
- the first substrate transport arm 31 takes out the substrate CW1 with chips from the chip peeling section 37 and transports it to the rework section 38 .
- the rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off (step S108).
- the first substrate transfer arm 31 takes out the chip-attached substrate CW1 from the rework section 38 and transfers it to the chip bonding section 6 .
- the chip bonding unit 6 either bonds the chip CP1 again to the bonding region where the chip CP1 has been peeled off, or the dummy chip DC1 prepared separately from the chip CP1 without bonding the chip CP1 again. (see FIG. 8) are pasted together (step S109).
- dummy chip DC1 does not have a device, that is, an electric circuit.
- the dummy chip DC1 consists of only a silicon wafer, a compound semiconductor wafer, or a glass substrate.
- the chip bonding unit 6 may bond neither the chip CP1 nor the dummy chip DC1, or bond anything on the bonding region from which the chip CP1 has been peeled off.
- the device W1b on the substrate W1 may be damaged. Bonding the chip CP1 again to the damaged device W1b is a waste of the chip CP1. Waste of the chip CP1 can be prevented by not bonding the chip CP1 to the damaged device W1b. This effect is obtained even when nothing is attached to the damaged device W1b.
- the substrate W1 does not have the device W1b as shown in FIG. 17A, it is preferable to bond the chip CP1 again to the bonding region from which the chip CP1 has been peeled off. This is because if the chip CP1 is not bonded again (including the case that the dummy chip DC1 is bonded again without bonding the chip CP1 again), the device W3b on the substrate W3 shown in FIG. 17D is wasted. .
- the chip bonding unit 6 bonds the chip CP1 again or bonds the dummy chip DC1 to the bonding region from which the chip CP1 has been peeled off (step S109).
- the substrate CW1 with the chip from being subjected to post-processing while leaving a space for mounting the chip CP1.
- the quality of post-processing can be improved. Uniform processing is possible, for example when grinding or polishing.
- step S ⁇ b>109 the first substrate transfer arm 31 of the first processing station 3 takes out the chip-attached substrate CW ⁇ b>1 from the chip bonding section 6 and transfers it to the inspection section 36 . After that, the processing after step S105 is performed again. After step S ⁇ b>109 , the first substrate transfer arm 31 may take out the chip-attached substrate CW ⁇ b>1 from the chip bonding section 6 and transfer it to the annealing section 39 . After that, the processing after step S110 is performed.
- the annealing unit 39 is the transfer destination of the substrate CW1 with chips.
- the first substrate transfer arm 31 takes out the chip-attached substrate CW1 from the inspection section 36 and transfers it to the annealing section 39 .
- the annealing section 39 heats the substrate CW1 with chips (step S110). The heat treatment improves the bonding strength between the chip CP1 and the substrate W1.
- the first substrate transfer arm 31 takes out the substrate CW1 with chips from the annealing section 39 and places it on the substrate mounting section 24 of the loading/unloading station 2 .
- the third substrate transfer arm 22 of the loading/unloading station 2 takes out the substrate CW1 with chips from the substrate mounting section 24 and stores it in the cassette C2.
- the chip-equipped substrate CW1 is unloaded from the substrate processing apparatus 1 while being accommodated in the cassette C2.
- step S104 the first frame transfer arm 32 of the first processing station 3 takes out the used frame FR1 from the chip bonding section 6 and places it on the frame mounting section 25 of the loading/unloading station 2.
- the third frame transfer arm 23 of the loading/unloading station 2 takes out the used frame FR1 from the frame mounting section 25 and stores it in the cassette C4.
- the first frame transport arm 32 has a pair of guide rails 321 on which the frame FR1 is placed, a gripping portion 322 that grips the frame FR1, and a driving portion 323 that moves the gripping portion 322 in the longitudinal direction of the pair of guide rails 321. .
- the third frame transfer arm 23 of the loading/unloading station 2 and the second frame transfer arm 44 of the interface block 4 may be configured similarly to the first frame transfer arm 32 of the first processing station 3. a pair of guide rails on which the frame FR1 is placed, a gripping portion that grips the frame FR1, and a driving portion that moves the gripping portion in the longitudinal direction of the pair of guide rails.
- Each of the pair of guide rails 321 has an L-shaped cross section and includes a horizontal plate 321a and a vertical plate 321b.
- a pair of vertical plates 321b are arranged to sandwich the frame FR1, and restrict movement of the frame FR1 in a direction perpendicular to the vertical plates 321b.
- the frame FR1 is placed on a pair of horizontal plates 321a.
- the first frame transfer arm 32 has a pair of guide rails 321 in addition to the grip portion 322, so that the frame FR1 can be stably supported. Further, the driving section 323 moves the gripping section 322 in the longitudinal direction of the pair of guide rails 321, so that the frame FR1 can be smoothly transferred to and from a desired device (for example, the tip cleaning section 33).
- the tip cleaning section 33 may have a pair of guide rails 338 .
- the pair of guide rails 338 may be horizontally and vertically movable.
- Each of the pair of guide rails 338 has an L-shaped cross section and includes a horizontal plate 338a and a vertical plate 338b.
- a pair of vertical plates 338b are arranged to sandwich the frame FR1 and restrict movement of the frame FR1 in a direction perpendicular to the vertical plates 338b.
- the frame FR1 is placed on a pair of horizontal plates 338a.
- the tip cleaning section 33 may have an internal transport section 339 . As shown in FIG. 4B, inside the chip cleaning section 33, the internal transport section 339 holds and transports the frame FR1 from above. The internal transport section 339 transports the frame FR1 between the pair of guide rails 338 and the frame holding section 332, which will be described later.
- the internal transport section 339 has, for example, a plurality of arms 339a. When viewed from above, each of the plurality of arms 339a traverses the opening of the frame FR1, and both ends in the longitudinal direction attract and transport the frame FR1 from above.
- the internal transport section 339 is capable of horizontal (both X-axis and Y-axis) and vertical movement.
- the chip cleaning section 33 has, for example, a chip holding section 331 and a frame holding section 332 .
- the chip holding part 331 horizontally holds the plurality of chips CP1 from below via the tape TP1.
- the chip holding section 331 slidably mounts the tape TP1.
- the chip holding portion 331 may have a vacuum chuck mechanism to fix the tape TP1.
- the frame holding portion 332 horizontally holds the frame FR1 from below.
- the frame holder 332 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1.
- a rotation drive unit 334 which will be described later, rotates the frame holding unit 332, thereby rotating the plurality of chips CP1 together with the frame FR1.
- the tip cleaning section 33 may have an expanding section 333 .
- the expanding section 333 widens the interval between the adjacent chips CP1 by radially expanding the tape TP1.
- the expanding section 333 radially expands the tape TP1 by raising the chip holding section 331 relative to the frame holding section 332 . By widening the interval between the adjacent chips CP1, the side surfaces of the chips CP1 can be efficiently cleaned.
- the tip cleaning section 33 may have a rotary drive section 334 , a nozzle 335 and a cup 336 .
- the rotation driving unit 334 rotates the frame holding unit 332 to rotate the plurality of chips CP1 together with the frame FR1.
- the rotation driving section 334 rotates the chip holding section 331 together with the frame holding section 332 .
- the nozzle 335 supplies cleaning liquid to the multiple chips CP1.
- the cleaning liquid is a chemical liquid, a rinse liquid, or the like.
- the rinse liquid is pure water such as DIW (deionized water).
- the nozzle 335 may move in a direction perpendicular to the rotation centerline of the tip holder 331 or the like.
- a cup 336 collects the cleaning fluid.
- the tip cleaning section 33 may have a cleaning head 337 .
- the cleaning head 337 is a brush, sponge, or the like, and scrubs and cleans the chips CP1.
- the cleaning head 337 may apply ultrasonic waves to the liquid film formed between the plurality of chips CP1.
- the liquid film is formed by supplying the cleaning liquid from the nozzle 335 .
- the second processing station 5 includes a substrate holding section 51, a chip holding section 52, a pickup section 53, and a mounting section 54, as described above.
- the substrate holding part 51 holds the substrate W1.
- the substrate holding unit 51 holds the substrate W1 horizontally, for example, with the main surface W1c of the substrate W1 facing upward.
- the main surface W1c of the substrate W1 may have a device W1b for each bonding region, and the substrate holding section 51 may hold the substrate W1 horizontally with the device W1b facing upward.
- the chip holding unit 52 holds the plurality of chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1.
- the chip holding unit 52 horizontally holds the plurality of chips CP1, for example, with the devices CP1b of the plurality of chips CP1 facing upward.
- the pickup unit 53 separates the plurality of chips CP1 individually from the tape TP1.
- the pickup section 53 has a first suction head 531 .
- the first suction head 531 sucks the chip CP1 from the side opposite to the tape TP1.
- the first suction head 531 sucks the chip CP1 from above.
- the first suction head 531 removes the chip CP1 from the tape TP1 by moving upward while sucking the chip CP1.
- the first suction head 531 may be upside down. By turning the chip CP1 upside down, the chip CP1 can be mounted on the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1.
- the tip holding part 52 may have a push-up pin 532 .
- the push-up pin 532 pushes up the chip CP1 from below via the tape TP1.
- the first suction head 531 sucks the chip CP ⁇ b>1 pushed up by the push-up pin 532 . Thereby, it is possible to prevent the adjacent chips CP1 from rubbing against each other.
- the pick-up section 53 may have an expanding section similar to the tip cleaning section 33 .
- the expanding section widens the interval between adjacent chips CP1 by radially expanding the tape TP1. Thereby, it is possible to prevent the adjacent chips CP1 from rubbing against each other.
- the mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1.
- the mount section 54 has a second suction head 541 .
- the second suction head 541 sucks the upside-down chip CP1 from above and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1.
- the second suction head 541 of the mount section 54 directly receives the chip CP1 from the first suction head 531 of the pickup section 53, but it may be received via a transport section (not shown).
- the transport unit transports the chip CP ⁇ b>1 from the pickup unit 53 to the mount unit 54 .
- the transport section may turn the chip CP1 upside down.
- the control section 9 may have an information acquisition section 93.
- the information acquisition unit 93 acquires information indicating whether the state of the device W1b is good or bad for each bonding region. Whether the device W1b is in good condition or not is inspected by an external inspection device.
- the inspection device performs, for example, an appearance inspection or an operation inspection of the device W1b, and transmits the inspection result to the control unit 9.
- the chip bonding unit 6 bonds the chip CP1 to the device W1b in good condition, and bonds the dummy chip DC1 (see FIG. 8) to the device W1b in poor condition. match. Note that the chip bonding unit 6 may bond neither the chip CP1 nor the dummy chip DC1, or bond anything on the device W1b in the defective state.
- Bonding the chip CP1 to the device W1b in a bad state is a waste of the chip CP1. Waste of the chip CP1 can be prevented by not bonding the chip CP1 to the device W1b in a defective state. This effect can be obtained even when nothing is attached to the device W1b which is in a bad state.
- the space for mounting the chip CP1 remains empty.
- the attached substrate CW1 can be prevented from being subjected to post-processing, and the quality of the post-processing can be improved.
- the inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad.
- the inspection items include at least one of presence/absence of foreign matter such as air bubbles and presence/absence of misalignment.
- the inspection unit 36 has, for example, a substrate holding unit 361 and an inspection head 362 .
- the substrate holding part 361 holds the chip-equipped substrate CW1.
- the substrate holder 361 can move in the horizontal direction (both the X-axis direction and the Y-axis direction).
- the substrate holder 361 may be rotatable around the vertical axis.
- the inspection position can be changed by moving or rotating the substrate holder 361 .
- the substrate holder 361 may be vertically movable.
- the inspection head 362 has, for example, a CT scanner, an infrared scanner, a confocal laser scanner, an ultrasonic scanner, or the like, acquires an image of the interface between the chip CP1 and the substrate W1, and detects the presence or absence of air bubbles.
- the inspection head 362 may have a height measuring device such as a laser displacement gauge and detect the presence or absence of air bubbles by detecting the height of the chip CP1. If there is a bubble, the height of the chip CP1 increases by the thickness of the bubble.
- the inspection unit 36 determines whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. It may have a determination unit (not shown). The determination unit is composed of a computer. The determination unit may be part of the control unit 9 .
- the chip peeling unit 37 peels off the chip CP1, which was found to be poorly bonded in the inspection by the inspection unit 36, from the substrate W1.
- the chip peeling section 37 has, for example, a substrate holding section 371 , a peeling head 372 , and a recovery box 373 .
- the substrate holding part 371 holds the chip-equipped substrate CW1.
- the substrate holding part 371 can move in the horizontal direction (both the X-axis direction and the Y-axis direction).
- the substrate holder 371 may be rotatable around the vertical axis. The peeling position can be changed by moving or rotating the substrate holder 371 .
- the substrate holder 371 may be vertically movable.
- the stripping head 372 includes, for example, a suction head 372a.
- the suction head 372a sucks the chip CP1 from above and moves upward in this state to separate the chip CP1 from the substrate W1.
- the first suction head 531 may be movable not only in the vertical direction but also in the horizontal direction.
- the suction head 372 a drops the chips CP ⁇ b>1 separated from the substrate W ⁇ b>1 into the recovery box 373 .
- the separation head 372 may include a blade 372b in addition to the suction head 372a.
- the blade 372b separates the chip CP1 from the substrate W1 by being inserted into the interface between the chip CP1 and the substrate W1.
- the separation head 372 may include a heater 372c and a cooler 372d in addition to the suction head 372a.
- the heater 372c and the cooler 372d are provided inside the suction head 372a, form a temperature gradient in the chip CP1, and separate the chip CP1 from the substrate W1 by thermal stress.
- the cooler 372d is arranged to surround the heater 372c. This can suppress lateral leakage of heat from the heater 372c, and can suppress heating of the chip CP1, which is not to be peeled off. Note that even if the arrangement of the cooler 372d and the heater 372c is reversed, it is possible to separate the chip CP1 from the substrate W1 by thermal stress. Note that the cooler 372d may be provided in the substrate holder 371 (see FIG. 10) instead of being provided inside the suction head 372a.
- the stripping head 372 may include a tubular seal 372e and a nozzle 372f in addition to the suction head 372a.
- the seal 372e collects a peeling liquid that reduces the bonding strength between the chip CP1 and the substrate W1 around the chip CP1 to be peeled.
- the nozzle 372f discharges the stripping liquid inside the seal 372e.
- the stripper penetrates into the interface between the chip CP1 and the substrate W1 to be stripped, and reduces the bonding strength between the chip CP1 and the substrate W1.
- the stripping liquid contains, for example, pure water such as DIW. Pure water reduces the bonding strength between the chip CP1 and the substrate W1 by hydrolysis.
- the stripping solution may contain pure water and components other than pure water.
- the seal 372e is pressed against the main surface W1c of the substrate W1.
- the material of the seal 372e is, for example, resin or rubber.
- the inner peripheral surface of the seal 372e may be a tapered surface that tapers downward. The stripping liquid can be guided inward by the tapered surface.
- the nozzle 372f may suck up the stripping liquid accumulated inside the seal 372e before separating the seal 372e from the substrate W1.
- the nozzle 372f for discharging the stripping liquid and the nozzle 372f for sucking the stripping liquid may be provided separately.
- the chip peeling section 37 may have a plurality of push-up pins 374 inside the substrate holding section 371 .
- the plurality of push-up pins 374 are raised and lowered individually. With the substrate holding part 371 sucking the substrate CW1 with chips, the push-up pins 374 locally push up the substrate W1, so that the substrate W1 is locally bent and deformed, and the chips CP1 are separated from the substrate W1.
- the rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off by the chip peeling unit 37 on the main surface W1c of the substrate W1.
- the rework section 38 has, for example, a substrate holding section 381 and a processing head 382 .
- the substrate holding part 381 holds the chip-equipped substrate CW1.
- the substrate holder 381 can move in the horizontal direction (both the X-axis direction and the Y-axis direction).
- the substrate holder 381 may be rotatable around the vertical axis.
- the processing position can be changed by moving or rotating the substrate holder 381 .
- the substrate holder 381 may be vertically movable.
- the processing head 382 has, for example, a plasma head, and selectively supplies plasma to the bonding area where the chip CP1 is separated from the plasma head.
- the processing head 382 may have a cover surrounding the plasma head in order to narrow the plasma supply area, and the pressure inside the cover may be reduced.
- the processing head 382 may have a cleaning head, and selectively supplies water to the bonding region where the chip CP1 is separated from the cleaning head.
- the cleaning head may supply water in either liquid or gaseous form, preferably in gaseous form.
- the treatment head 382 may have a cover surrounding the cleaning head to restrict the water supply area and may also have a vacuum inside the cover.
- the processing head 382 may be movable in the horizontal direction (both the X-axis direction and the Y-axis direction). By moving the processing head 382, the processing position can be changed.
- the processing head 382 may be vertically movable.
- the substrate processing apparatus 1 according to the first modified example will be described mainly about the differences from the above-described embodiment.
- the second processing station 5 has an inspection section 36 instead of the first processing station 3 . It is also possible to simultaneously perform the bonding of the substrate W1 and the chip CP1 (step S104) and the inspection of the bonding state (step S105).
- the second processing station 5 may also include a chip peeling section 37 in addition to the inspection section 36 instead of the first processing station 3 .
- the substrate processing apparatus 1 attaches a second chip different from the chip CP1 to a second bonding region different from the bonding region of the main surface W1c of the substrate W1.
- a substrate CW1 with a chip is manufactured by laminating CP2.
- the substrate with chips CW1 includes a substrate W1, a plurality of chips CP1 bonded to the substrate W1, and a plurality of second chips CP2 bonded to the substrate W1.
- a plurality of second chips CP2 shown in FIG. 16(B) are loaded into the substrate processing apparatus 1 .
- a plurality of second chips CP2 are adhered to a second tape TP2, and the outer periphery of the second tape TP2 is attached to the second frame FR2.
- a plurality of second chips CP2 are arranged in the opening of the second frame FR2. The plurality of second chips CP2 can be obtained, for example, by dicing the substrate while the substrate is adhered to the second tape TP2.
- the second chip CP2 has a base substrate CP2a and a device CP2b formed on the base substrate CP2a.
- the underlying substrate CP2a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate.
- the device CP2b includes semiconductor elements, circuits, terminals, or the like.
- the device CP2b is arranged on the side opposite to the second tape TP2 with respect to the base substrate CP2a.
- the pickup unit 53 separates the plurality of second chips CP2 individually from the second tape TP2. After that, the second chip CP2 is turned upside down and then bonded to the substrate W1 as shown in FIG. 16(D).
- the device W1b of the substrate W1, the device CP1b of the chip CP1, and the device CP2b of the second chip CP2 are electrically connected.
- a chip-equipped substrate CW1 is obtained.
- the interface block 4 may include a third buffer section 45.
- the third buffer section 45 is adjacent to the transport area 30 of the first processing station 3 .
- the first buffer section 41 , the second buffer section 42 and the third buffer section 45 may be vertically stacked to reduce the footprint of the interface block 4 .
- the third buffer unit 45 stores a plurality of second chips CP2 together with the second frame FR2.
- the third buffer unit 45 stores a plurality of second chips CP2 that have undergone pretreatment (for example, cleaning). As a result, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrates CW1 with chips can be improved.
- the transportation and cleaning of the second chip CP2 are performed in the same manner as the transportation and cleaning of the chip CP1, so description thereof will be omitted.
- the device used for transporting and cleaning the second chip CP2 and the device used for transporting and cleaning the chip CP1 may be a common device or may be separate devices.
- the device used to pick up and mount the second chip CP2 and the device used to pick up and mount the chip CP1 may be a common device or may be separate devices.
- the substrate processing apparatus 1 peels off the chip CP1 protected by the protective film PF1 from the tape TP1, and then mounts the chip CP1 on the substrate W1. On the way, the substrate processing apparatus 1 removes the protective film PF1 from the chip CP1.
- the second processing station 5 includes a substrate holding section 51, a chip holding section 52, a pickup section 53, and a mounting section .
- the second processing station 5 also comprises a remover 55 (see FIG. 18).
- the pickup section 53, the mounting section 54, and the removing section 55 will be described in this order.
- the pickup unit 53 picks up the chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1 and the protective film PF1 is formed on the first main surface CP1c of the chips CP1 opposite to the tape TP1. Peel off from tape TP1.
- the protective film PF1 covers the first main surface CP1c of the chip CP1.
- the pickup section 53 has a first suction head 531 .
- the first suction head 531 suctions the chip CP1 via the protective film PF1.
- the protective film PF1 suppresses damage to the device CP1b by preventing contact between the first suction head 531 and the device CP1b of the chip CP1.
- the first suction head 531 separates the chip CP1 from the tape TP1 by moving upward while sucking the chip CP1. At this time, the protective film PF1 is torn off and divided. Note that the protective film PF1 may be divided in advance by laser processing, blade processing, or the like.
- the first suction head 531 may be capable of being turned upside down.
- the chip CP1 can be turned upside down, and the first main surface CP1c of the chip CP1 can face the substrate W1.
- a transporting unit (not shown) may transport the chip CP1 from the pickup unit 53 to the mounting unit 54, and the transporting unit may turn the chip CP1 upside down on the way.
- the mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1.
- the mount section 54 has a second suction head 541 .
- the second suction head 541 suctions the second main surface CP1d of the chip CP1.
- the second main surface CP1d is a surface opposite to the first main surface CP1c and is a surface separated from the tape TP1.
- the second suction head 541 picks up the chip CP1 from above and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1.
- the protective film PF1 is removed in advance so that the chip CP1 and the substrate W1 are in contact with each other.
- the device CP1b of the chip CP1 and the device W1b of the substrate W1 are electrically connected.
- the pickup unit 53 peels off the chip CP1 from the tape TP1 while the protective film PF1 covers the first main surface CP1c of the chip CP1. Therefore, contact between the pickup portion 53 and the chip CP1 can be prevented, and damage to the chip CP1 can be suppressed. This is particularly effective when the first main surface CP1c of the chip CP1 has the device CP1b.
- the chip CP1 is bonded to the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1.
- the chip CP1 can be brought into contact with the substrate W1, and the device CP1b of the chip CP1 and the device W1b of the substrate W1 can be electrically connected.
- the protective film PF1 may cover not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1.
- the protective film PF1 is formed by coating and solidifying a liquid material for the protective film PF1 on a plurality of chips CP1 divided in advance by dicing, and is also formed in the gaps between the adjacent chips CP1. It is formed.
- the removal section 55 may have a first supply section 551 .
- the first supply unit 551 supplies the stripping liquid L1 for stripping the protective film PF1 from the chip CP1 to the protective film PF1.
- the peeling liquid L1 peels the protective film PF1 from the chip CP1, for example, without dissolving the protective film PF1.
- the protective film PF1 is peeled off from the chip CP1 in the form of a film.
- the first supply unit 551 has a storage tank for storing the stripping liquid L1, and the protective film PF1 is immersed in the stripping liquid L1 stored in the storage tank together with the chip CP1.
- the second suction head 541 of the mount section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the stripping liquid L1.
- the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mount section 54 .
- the peeling liquid L1 permeates into the protective film PF1 and reaches the interface between the protective film PF1 and the chip CP1, thereby peeling the protective film PF1 from the chip CP1.
- the particles PC attached to the chip CP1 before the protective film PF1 is formed are separated from the chip CP1 together with the protective film PF1.
- the protective film PF1 preferably covers not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1 in order to improve the removal efficiency of the particles PC. Particles PC adhering to side surface CP1e of chip CP1 can also be peeled off from chip CP1.
- the stripping liquid L1 is appropriately selected according to the material of the protective film PF1, and is, for example, pure water such as DIW.
- the protective film PF1 is, for example, an organic film. Pure water can permeate the interior of the organic film.
- the material of the organic film is not particularly limited, it is, for example, an acrylic resin or an epoxy resin, preferably an acrylic resin.
- the pure water may be heated to improve the peelability between the protective film PF1 and the chip CP1.
- the removal section 55 may have a second supply section 552 .
- the second supply unit 552 supplies the stripping liquid L1 to the protective film PF1 by the first supply unit 551, and then supplies the dissolving liquid L2 for dissolving the protective film PF1.
- the second supply unit 552 has a reservoir for storing the solution L2, and the protective film PF1 is immersed in the solution L2 stored in the reservoir together with the chip CP1.
- the second suction head 541 of the mount section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the solution L2.
- the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mount section 54 .
- an alkaline developer is used as the dissolving liquid L2.
- an alkaline developer is used, the zeta potential of the same polarity can be generated in the chips CP1 and the particles PC, and the reattachment of the particles PC to the chips CP1 can be suppressed.
- an alkaline developer is used as the dissolving liquid L2
- an alkaline developing liquid having a concentration lower than that of the dissolving liquid L2 may be used as the stripping liquid L1.
- the storage tank for storing the dissolving liquid L2 and the storage tank for storing the stripping liquid L1 may be common.
- the removal unit 55 may have both the first supply unit 551 and the second supply unit 552 , it may have only the first supply unit 551 or only the second supply unit 552 .
- the removal unit 55 may have a drying unit that dries the chip CP1. If the removing unit 55 does not use liquid such as the stripping liquid L1 or the dissolving liquid L2, the drying unit is unnecessary.
- FIG. The coating section 70 is provided in the first processing station 3 as shown in FIG.
- the coating section 70 is adjacent to the transport area 30 .
- the plurality of chips CP ⁇ b>1 are cleaned by the chip cleaning section 33 , processed by the coating section 70 , and then transported to the chip bonding section 6 by the first frame transport arm 32 .
- the application unit 70 and the tip cleaning unit 33 are provided separately in this modification, the application unit 70 may have the function of the tip cleaning unit 33 .
- the application section 70 has, for example, a tip holding section 701 and a frame holding section 702.
- the chip holding unit 701 horizontally holds the plurality of chips CP1 from below via the tape TP1.
- the chip holding portion 701 slidably mounts the tape TP1.
- the tip holding unit 701 may have a vacuum chuck mechanism to fix the tape TP1.
- the frame holding portion 702 horizontally holds the frame FR1 from below.
- the frame holder 702 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1.
- a rotation drive unit 704 which will be described later, rotates the frame holding unit 702, thereby rotating the plurality of chips CP1 together with the frame FR1.
- the application unit 70 has a rotary drive unit 704 , a nozzle 705 and a cup 706 .
- the rotation driving unit 704 rotates the frame holding unit 702 to rotate the plurality of chips CP1 together with the frame FR1.
- the rotation driving section 704 rotates the tip holding section 701 as well as the frame holding section 702 .
- the nozzle 705 supplies the liquid material L3 of the protective film PF1 to the plurality of chips CP1.
- Cup 706 collects liquid material L3.
- the applicator 70 forms the protective film PF1 by applying and solidifying the liquid material of the protective film PF1 on the plurality of chips CP1 divided in advance by dicing.
- the protective film PF1 can also be formed in the gap between the adjacent chips CP1, and the protective film PF1 can also be formed on the side surface CP1e of the chip CP1.
- “hardening” includes “hardening.” “Curing” means that molecules are linked together to form a polymer (for example, cross-linking or polymerization).
- the coating unit 70 applies the liquid material L3 of the protective film PF1 to the chips CP1 from the opposite side of the tape TP1 with respect to the chips CP1. Then, the protective film PF1 is formed. Since the plurality of chips CP1 are adhered to the tape TP1, it is easy to handle.
- the liquid material L3 is supplied near the rotation center line of the plurality of chips CP1, spreads radially in a direction away from the rotation center line due to centrifugal force, and forms a liquid film.
- the protective film PF1 is formed by solidifying the liquid film of the liquid material L3. After forming the liquid film, the rotation of the chip CP1 may be stopped before the liquid film is solidified.
- the liquid material L3 contains, for example, a volatile component, and is solidified by volatilization of the volatile component.
- the particles PC can be peeled off from the chip CP1 by utilizing the volume shrinkage associated with volatilization of the volatile components.
- the liquid material L3 may contain acrylic resin.
- the particles PC can also be separated from the chip CP1 by curing shrinkage of the acrylic resin.
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Abstract
This substrate-processing device comprises: a pick-up unit; a removal unit; and a mounting unit. The pick-up unit separates a chip from a tape in a state where a plurality of the chips are fitted to a frame via the tape and a protective film is formed on a first main surface of each of the chips on the side that is opposite from the tape. After the chip is separated from the tape by the pick-up unit, the removal unit removes the protective film from the chip. After the removal unit has removed the protective film, the mounting unit mounts the chip on a substrate with the first main surface of the chip facing the substrate.
Description
本開示は、基板処理装置、及び基板処理方法に関する。
The present disclosure relates to a substrate processing apparatus and a substrate processing method.
特許文献1に記載のチップ実装システムは、チップ供給装置と、ボンディング装置と、表面処理装置と、搬出入部と、搬送部と、を備える(特許文献1の段落[0225])。チップ供給装置は、複数のチップを保持して接合すべきチップを個別に供給する。ボンディング装置は、チップ供給装置から供給されたチップを基板上に取り付ける。表面処理装置は、複数のチップ及び基板の接合面に表面活性化処理と親水化処理を行う。搬入出部は、チップ実装システムの外部から接合すべきチップ及び基板をその内部に搬入し、チップが取り付けられた基板(チップと基板とを含む構造体)をその外部へ搬出する。搬送部は、複数のチップ、基板及びチップと基板とを含む構造体を搬出入部、チップ供給装置、ボンディング装置及び表面処理装置の間において搬送する。チップ供給装置の内部では、ダイシング処理が行われて複数のチップが生成される(特許文献1の段落[0248])。また、チップ供給装置の内部では、ダイシングされた複数のチップがダイシングテープ上に載置される(特許文献1の段落[0250])。
The chip mounting system described in Patent Document 1 includes a chip supply device, a bonding device, a surface treatment device, a loading/unloading section, and a transport section (paragraph [0225] of Patent Document 1). The chip supply device holds a plurality of chips and individually supplies the chips to be joined. The bonding device attaches the chips supplied from the chip supply device onto the substrate. The surface treatment apparatus performs surface activation treatment and hydrophilization treatment on the bonding surfaces of the plurality of chips and the substrate. The loading/unloading section loads a chip and a substrate to be bonded from the outside of the chip mounting system into the inside thereof, and carries out the substrate on which the chip is attached (the structure including the chip and the substrate) to the outside. The transport unit transports a plurality of chips, substrates, and a structure including chips and substrates between the loading/unloading unit, the chip supply device, the bonding device, and the surface treatment device. Inside the chip feeder, a dicing process is performed to generate a plurality of chips (paragraph [0248] of Patent Document 1). Also, inside the chip supply device, a plurality of diced chips are placed on a dicing tape (paragraph [0250] of Patent Document 1).
本開示の一態様は、チップ付き基板の品質を向上する、技術を提供する。
One aspect of the present disclosure provides a technique for improving the quality of substrates with chips.
本開示の一態様に係る基板処理装置は、ピックアップ部と、除去部と、マウント部と、を備える。前記ピックアップ部は、複数のチップがテープを介してフレームに装着され且つ前記チップの前記テープとは反対側の第1主面に保護膜が形成された状態で前記チップを前記テープから剥離する。前記除去部は、前記ピックアップ部によって前記チップを前記テープから剥離した後、前記チップから前記保護膜を除去する。前記マウント部は、前記除去部によって前記保護膜を除去した後、前記チップの前記第1主面を基板に向けて前記チップを前記基板に実装する。
A substrate processing apparatus according to one aspect of the present disclosure includes a pickup section, a removal section, and a mount section. The pickup part separates the chips from the tape in a state in which a plurality of chips are attached to the frame via a tape and a protective film is formed on the first main surface of the chips opposite to the tape. The removal unit removes the protective film from the chip after the chip is separated from the tape by the pickup unit. The mounting section mounts the chip on the substrate with the first main surface of the chip facing the substrate after the protective film is removed by the removing portion.
本開示の一態様によれば、チップ付き基板の品質を向上することができる。
According to one aspect of the present disclosure, it is possible to improve the quality of the chip-equipped substrate.
以下、本開示の実施形態について図面を参照して説明する。なお、各図面において同一の又は対応する構成には同一の符号を付し、説明を省略することがある。本明細書において、X軸方向、Y軸方向、Z軸方向は互いに垂直な方向である。X軸方向及びY軸方向は水平方向、Z軸方向は鉛直方向である。
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In addition, in each drawing, the same reference numerals are given to the same or corresponding configurations, and explanations thereof may be omitted. In this specification, the X-axis direction, the Y-axis direction, and the Z-axis direction are directions perpendicular to each other. The X-axis direction and Y-axis direction are horizontal directions, and the Z-axis direction is vertical direction.
図1~図2を参照して、一実施形態に係る基板処理装置1について説明する。基板処理装置1は、図2(A)~図2(D)に示すように、基板W1の主面W1cの異なる貼合領域に複数のチップCP1を貼合することで、チップ付き基板CW1を製造する。貼合領域は、予め設定されている。
A substrate processing apparatus 1 according to one embodiment will be described with reference to FIGS. As shown in FIGS. 2A to 2D, the substrate processing apparatus 1 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1, thereby forming a substrate CW1 with chips. manufacture. The pasting area is set in advance.
チップ付き基板CW1は、基板W1と、基板W1に貼合された複数のチップCP1と、を含む。図示しないが、各チップCP1の上には、さらに別のチップが積層されてもよい。
A substrate CW1 with chips includes a substrate W1 and a plurality of chips CP1 bonded to the substrate W1. Although not shown, another chip may be stacked on each chip CP1.
基板処理装置1には、図2(A)に示す基板W1が搬入される。基板W1は、下地基板W1aと、下地基板W1aの上に形成された複数のデバイスW1bと、を有する。下地基板W1aは、例えば、シリコンウェハ、化合物半導体ウェハ、又はガラス基板である。デバイスW1bは、半導体素子、回路、又は端子などを含む。デバイスW1bは、主面W1cに形成されている。
A substrate W1 shown in FIG. 2(A) is loaded into the substrate processing apparatus 1. The substrate W1 has an underlying substrate W1a and a plurality of devices W1b formed on the underlying substrate W1a. The underlying substrate W1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. Device W1b includes a semiconductor element, a circuit, a terminal, or the like. The device W1b is formed on the main surface W1c.
また、基板処理装置1には、図2(B)に示す複数のチップCP1が搬入される。複数のチップCP1はテープTP1に接着されており、テープTP1の外周がフレームFR1に装着されている。フレームFR1の開口部に、複数のチップCP1が配列されている。複数のチップCP1は、例えば基板をテープTP1に接着した状態で基板をダイシングすることで得られる。
Also, a plurality of chips CP1 shown in FIG. A plurality of chips CP1 are adhered to a tape TP1, and the outer circumference of the tape TP1 is attached to the frame FR1. A plurality of chips CP1 are arranged in the opening of the frame FR1. The plurality of chips CP1 can be obtained, for example, by dicing the substrate while the substrate is adhered to the tape TP1.
チップCP1は、下地基板CP1aと、下地基板CP1aの上に形成されたデバイスCP1bと、を有する。下地基板CP1aは、例えば、シリコンウェハ、化合物半導体ウェハ、又はガラス基板である。デバイスCP1bは、半導体素子、回路、又は端子などを含む。デバイスCP1bは、下地基板CP1aを基準として、テープTP1とは反対側に配置される。
The chip CP1 has a base substrate CP1a and a device CP1b formed on the base substrate CP1a. The underlying substrate CP1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. Device CP1b includes a semiconductor element, a circuit, a terminal, or the like. The device CP1b is arranged on the side opposite to the tape TP1 with respect to the base substrate CP1a.
図2(C)に示すように、ピックアップ部53は、複数のチップCP1を個別にテープTP1から剥離する。その後、チップCP1は、上下反転された上で、図2(D)に示すように、基板W1に貼合される。基板W1のデバイスW1bと、チップCP1のデバイスCP1bとが電気的に接続される。これにより、チップ付き基板CW1が得られる。
As shown in FIG. 2(C), the pickup unit 53 separates the plurality of chips CP1 individually from the tape TP1. After that, the chip CP1 is turned upside down and then bonded to the substrate W1 as shown in FIG. 2(D). The device W1b on the substrate W1 and the device CP1b on the chip CP1 are electrically connected. Thus, a chip-equipped substrate CW1 is obtained.
なお、図17(A)に示すように、チップ付き基板CW1を構成する基板W1は、デバイスW1bを有しなくてもよい。つまり、基板W1は、電気回路を有しなくてもよい。例えば、基板W1は、シリコンウェハ、化合物半導体ウェハ、又はガラス基板のみからなる。基板W1がデバイスW1bを有しない場合、図17(B)に示すように、複数のチップCP1を挟んで基板W1と基板W2とが接合される。次に、図17(C)に示すように、複数のチップCP1と基板W1が剥離され、最後に、図17(D)に示すように複数のチップCP1を挟んで基板W2と基板W3とが接合される。基板W3は、下地基板W3aと、下地基板W3aの上に形成された複数のデバイスW3bと、を有する。基板W3のデバイスW3bと、チップCP1のデバイスCP1bとが電気的に接続される。
It should be noted that, as shown in FIG. 17A, the substrate W1 that constitutes the chip-equipped substrate CW1 may not have the device W1b. That is, the substrate W1 does not have to have an electric circuit. For example, the substrate W1 consists of only a silicon wafer, a compound semiconductor wafer, or a glass substrate. When the substrate W1 does not have the device W1b, as shown in FIG. 17B, the substrate W1 and the substrate W2 are bonded with the plurality of chips CP1 interposed therebetween. Next, as shown in FIG. 17C, the plurality of chips CP1 and substrate W1 are separated, and finally, as shown in FIG. spliced. The substrate W3 has an underlying substrate W3a and a plurality of devices W3b formed on the underlying substrate W3a. The device W3b on the substrate W3 and the device CP1b on the chip CP1 are electrically connected.
図1に示すように、基板処理装置1は、搬入出ステーション2と、第1処理ステーション3と、インターフェースブロック4と、第2処理ステーション5と、制御部9と、を備える。搬入出ステーション2と、第1処理ステーション3と、インターフェースブロック4と、第2処理ステーション5とは、この順番で、X軸負方向側からX軸正方向側に並ぶ。
As shown in FIG. 1, the substrate processing apparatus 1 includes a loading/unloading station 2, a first processing station 3, an interface block 4, a second processing station 5, and a controller 9. The loading/unloading station 2, the first processing station 3, the interface block 4, and the second processing station 5 are arranged in this order from the X-axis negative direction side to the X-axis positive direction side.
搬入出ステーション2は、載置台20を備える。載置台20には、カセットC1~C4が載置される。カセットC1は、図2(A)に示す基板W1を収容する。カセットC2は、図2(D)に示すチップ付き基板CW1を収容する。カセットC3は、図2(B)に示すフレームFR1と共に複数のチップCP1を収容する。カセットC4は、図示しない使用済みのフレームFR1を収容する。使用済みのフレームFR1とは、複数のチップCP1をテープTP1から剥離した後に残るフレームFR1のことである。使用済みのフレームFR1には、チップCP1が残っていてもよい。
The loading/unloading station 2 includes a mounting table 20 . Cassettes C1 to C4 are mounted on the mounting table 20. As shown in FIG. The cassette C1 accommodates the substrate W1 shown in FIG. 2(A). The cassette C2 accommodates the chip-attached substrate CW1 shown in FIG. 2(D). The cassette C3 accommodates a plurality of chips CP1 together with the frame FR1 shown in FIG. 2(B). A cassette C4 accommodates a used frame FR1 (not shown). The used frame FR1 is the frame FR1 remaining after the plurality of chips CP1 are separated from the tape TP1. A chip CP1 may remain in the used frame FR1.
搬入出ステーション2は、搬送領域21と、第3基板搬送アーム22と、第3フレーム搬送アーム23と、を備える。搬送領域21は、載置台20に隣接する。第3基板搬送アーム22は、搬送領域21にて基板W1を保持して搬送する。第3フレーム搬送アーム23は、搬送領域21にてフレームFR1を保持して搬送する。第3基板搬送アーム22と第3フレーム搬送アーム23は、それぞれ、水平方向(X軸方向及びY軸方向の両方向)及び鉛直方向の移動と、鉛直軸を中心とする回転とが可能である。
The loading/unloading station 2 includes a transport area 21 , a third substrate transport arm 22 and a third frame transport arm 23 . The transport area 21 is adjacent to the mounting table 20 . The third substrate transport arm 22 holds and transports the substrate W1 in the transport area 21 . The third frame transport arm 23 holds and transports the frame FR1 in the transport area 21 . The third substrate transfer arm 22 and the third frame transfer arm 23 are each capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.
搬入出ステーション2は、第3基板搬送アーム22と第3フレーム搬送アーム23を移動または回転させる図示しない駆動部を有する。第3基板搬送アーム22と第3フレーム搬送アーム23は、同じY軸スライダに搭載され同時にY軸方向に移動させられてもよいし、異なるY軸スライダに搭載され独立にY軸方向に移動させられてもよい。第3基板搬送アーム22と第3フレーム搬送アーム23は、同じY軸スライダに搭載される場合、Z軸方向に積層される。第3基板搬送アーム22と第3フレーム搬送アーム23が異なるY軸スライダに搭載される場合、複数のY軸スライダはZ軸方向にずらして配置される。
The loading/unloading station 2 has a drive section (not shown) that moves or rotates the third substrate transfer arm 22 and the third frame transfer arm 23 . The third substrate transfer arm 22 and the third frame transfer arm 23 may be mounted on the same Y-axis slider and moved in the Y-axis direction at the same time, or may be mounted on different Y-axis sliders and moved in the Y-axis direction independently. may be The third substrate transfer arm 22 and the third frame transfer arm 23 are stacked in the Z-axis direction when mounted on the same Y-axis slider. When the third substrate transfer arm 22 and the third frame transfer arm 23 are mounted on different Y-axis sliders, the Y-axis sliders are shifted in the Z-axis direction.
第3基板搬送アーム22は、チップCP1を貼合する前の基板W1をカセットC1から取り出し、基板載置部24に搬送する。また、第3基板搬送アーム22は、基板載置部24からチップ付き基板CW1を取り出し、カセットC2に収納する。チップCP1を貼合する前の基板W1を搬送する第3基板搬送アーム22と、チップ付き基板CW1を搬送する第3基板搬送アーム22とは、別々に設けられてもよい。
The third substrate transport arm 22 takes out the substrate W1 before bonding the chip CP1 from the cassette C1 and transports it to the substrate platform 24 . Further, the third substrate transport arm 22 takes out the substrate CW1 with chips from the substrate mounting portion 24 and stores it in the cassette C2. The third substrate transfer arm 22 that transfers the substrate W1 before bonding the chip CP1 thereto and the third substrate transfer arm 22 that transfers the substrate CW1 with the chip may be provided separately.
第3フレーム搬送アーム23は、フレームFR1と共に複数のチップCP1をカセットC3から取り出し、フレーム載置部25に搬送する。また、第3フレーム搬送アーム23は、フレーム載置部25から使用済みのフレームFR1を取り出し、カセットC4に収納する。フレームFR1と共に複数のチップCP1を搬送する第3フレーム搬送アーム23と、使用済みのフレームFR1を搬送する第3フレーム搬送アーム23とは、別々に設けられてもよい。
The third frame transport arm 23 takes out the plurality of chips CP1 together with the frame FR1 from the cassette C3 and transports them to the frame mounting section 25. Also, the third frame transfer arm 23 takes out the used frame FR1 from the frame placing portion 25 and stores it in the cassette C4. The third frame transfer arm 23 that transfers the plurality of chips CP1 together with the frame FR1 and the third frame transfer arm 23 that transfers the used frame FR1 may be provided separately.
搬入出ステーション2は、基板載置部24と、フレーム載置部25と、を備える。基板載置部24とフレーム載置部25は、搬入出ステーション2の搬送領域21と、第1処理ステーション3の搬送領域30との間に配置され、両方の搬送領域21、30に隣接する。基板載置部24とフレーム載置部25とは、搬入出ステーション2のフットプリントを小さくすべく、鉛直方向に積層されてもよい。
The loading/unloading station 2 includes a substrate loading section 24 and a frame loading section 25 . The substrate rest 24 and the frame rest 25 are arranged between the transport area 21 of the loading/unloading station 2 and the transport area 30 of the first processing station 3 and are adjacent to both transport areas 21 , 30 . The substrate rest 24 and the frame rest 25 may be vertically stacked to reduce the footprint of the loading/unloading station 2 .
基板載置部24には、チップCP1を貼合する前の基板W1が載置される。基板載置部24には、チップ付き基板CW1が載置されてもよい。チップCP1を貼合する前の基板W1が載置される基板載置部24と、チップ付き基板CW1が載置される基板載置部24とは、別々に設けられてもよく、それぞれ複数設けられてもよい。
The substrate W1 before bonding the chip CP1 is mounted on the substrate mounting portion 24. A substrate CW<b>1 with a chip may be placed on the substrate placement part 24 . The substrate mounting portion 24 on which the substrate W1 before bonding the chip CP1 is mounted and the substrate mounting portion 24 on which the substrate CW1 with chips is mounted may be provided separately, or a plurality of each may be provided. may be
フレーム載置部25には、フレームFR1と共に複数のチップCP1が載置される。フレーム載置部25には、使用済みのフレームFR1が載置されてもよい。フレームFR1と共に複数のチップCP1が載置されるフレーム載置部25と、使用済みのフレームFR1が載置されるフレーム載置部25とは、別々に設けられてもよく、それぞれ複数設けられてもよい。
A plurality of chips CP1 are mounted on the frame mounting portion 25 together with the frame FR1. A used frame FR<b>1 may be placed on the frame placement portion 25 . The frame mounting portion 25 on which the plurality of chips CP1 are mounted together with the frame FR1 and the frame mounting portion 25 on which the used frames FR1 are mounted may be provided separately, or a plurality of each may be provided. good too.
第1処理ステーション3は、搬送領域30と、第1基板搬送アーム31と、第1フレーム搬送アーム32と、を備える。搬送領域30は、X軸方向に延びている。第1基板搬送アーム31は、搬送領域30にて基板W1を保持して搬送する。第1フレーム搬送アーム32は、搬送領域30にてフレームFR1を保持して搬送する。第1基板搬送アーム31と第1フレーム搬送アーム32は、それぞれ、水平方向(X軸方向及びY軸方向の両方向)及び鉛直方向の移動と、鉛直軸を中心とする回転とが可能である。
The first processing station 3 includes a transfer area 30 , a first substrate transfer arm 31 and a first frame transfer arm 32 . The transport area 30 extends in the X-axis direction. The first substrate transport arm 31 holds and transports the substrate W<b>1 in the transport area 30 . The first frame transport arm 32 holds and transports the frame FR1 in the transport area 30 . The first substrate transfer arm 31 and the first frame transfer arm 32 are each capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.
第1処理ステーション3は、第1基板搬送アーム31と第1フレーム搬送アーム32を移動または回転させる図示しない駆動部を有する。第1基板搬送アーム31と第1フレーム搬送アーム32は、同じX軸スライダに搭載され同時にX軸方向に移動させられてもよいし、異なるX軸スライダに搭載され独立にX軸方向に移動させられてもよい。第1基板搬送アーム31と第1フレーム搬送アーム32は、同じX軸スライダに搭載される場合、Z軸方向に積層される。第1基板搬送アーム31と第1フレーム搬送アーム32が異なるX軸スライダに搭載される場合、複数のX軸スライダはZ軸方向にずらして配置される。
The first processing station 3 has a drive section (not shown) that moves or rotates the first substrate transfer arm 31 and the first frame transfer arm 32 . The first substrate transfer arm 31 and the first frame transfer arm 32 may be mounted on the same X-axis slider and moved in the X-axis direction at the same time, or may be mounted on different X-axis sliders and moved in the X-axis direction independently. may be The first substrate transfer arm 31 and the first frame transfer arm 32 are stacked in the Z-axis direction when mounted on the same X-axis slider. When the first substrate transfer arm 31 and the first frame transfer arm 32 are mounted on different X-axis sliders, the plurality of X-axis sliders are shifted in the Z-axis direction.
第1基板搬送アーム31は、チップCP1を貼合する前の基板W1を基板載置部24から取り出し、表面改質部34と基板洗浄部35を経由して、インターフェースブロック4の第1バッファ部41に搬送する。また、第1基板搬送アーム31は、第1バッファ部41からチップ付き基板CW1を取り出し、検査部36などを経由して、搬入出ステーション2の基板載置部24に載置する。チップCP1を貼合する前の基板W1を搬送する第1基板搬送アーム31と、チップ付き基板CW1を搬送する第1基板搬送アーム31とは、別々に設けられてもよい。
The first substrate transport arm 31 takes out the substrate W1 before bonding the chip CP1 from the substrate mounting part 24, passes through the surface modification part 34 and the substrate cleaning part 35, and transfers it to the first buffer part of the interface block 4. Transport to 41. The first substrate transport arm 31 also takes out the substrate CW1 with chips from the first buffer unit 41 and places it on the substrate placement unit 24 of the loading/unloading station 2 via the inspection unit 36 and the like. The first substrate transfer arm 31 that transfers the substrate W1 before bonding the chip CP1 thereto and the first substrate transfer arm 31 that transfers the substrate CW1 with the chip may be provided separately.
第1フレーム搬送アーム32は、フレーム載置部25からフレームFR1と共に複数のチップCP1を取り出し、チップ洗浄部33を経由して、インターフェースブロック4の第2バッファ部42に搬送する。また、第1フレーム搬送アーム32は、第2バッファ部42から使用済みのフレームFR1を取り出し、搬入出ステーション2のフレーム載置部25に載置する。フレームFR1と共に複数のチップCP1を搬送する第1フレーム搬送アーム32と、使用済みのフレームFR1を搬送する第1フレーム搬送アーム32とは、別々に設けられてもよい。
The first frame transport arm 32 takes out the plurality of chips CP1 together with the frame FR1 from the frame mounting part 25 and transports them to the second buffer part 42 of the interface block 4 via the chip cleaning part 33 . Also, the first frame transfer arm 32 takes out the used frame FR1 from the second buffer section 42 and places it on the frame placement section 25 of the loading/unloading station 2 . The first frame transfer arm 32 that transfers the plurality of chips CP1 together with the frame FR1 and the first frame transfer arm 32 that transfers the used frame FR1 may be provided separately.
第1処理ステーション3は、チップ洗浄部33と、表面改質部34と、基板洗浄部35と、検査部36と、チップ剥離部37と、リワーク部38と、アニール部39と、を備える。チップ洗浄部33と、表面改質部34と、基板洗浄部35と、検査部36と、チップ剥離部37と、リワーク部38と、アニール部39とは、搬送領域30に隣接しており、搬送領域30のY軸正方向側またはY軸負方向側に配置される。
The first processing station 3 includes a chip cleaning section 33 , a surface modification section 34 , a substrate cleaning section 35 , an inspection section 36 , a chip peeling section 37 , a rework section 38 and an annealing section 39 . The chip cleaning section 33, the surface modification section 34, the substrate cleaning section 35, the inspection section 36, the chip peeling section 37, the rework section 38, and the annealing section 39 are adjacent to the transfer area 30, It is arranged on the Y-axis positive direction side or the Y-axis negative direction side of the transport area 30 .
チップ洗浄部33は、複数のチップCP1がテープTP1に接着され且つテープTP1の外周がフレームFR1に装着された状態で、複数のチップCP1を洗浄する。チップCP1を洗浄した後で、チップCP1を基板W1に貼合することで、異物の噛み込みを抑制できる。チップ洗浄部33の詳細は後述する。
The chip cleaning unit 33 cleans the plurality of chips CP1 in a state in which the plurality of chips CP1 are adhered to the tape TP1 and the outer periphery of the tape TP1 is attached to the frame FR1. By bonding the chip CP1 to the substrate W1 after cleaning the chip CP1, it is possible to prevent foreign matter from entering. The details of the chip cleaning unit 33 will be described later.
表面改質部34は、基板W1の主面W1cをプラズマ処理する。表面改質部34では、例えば減圧下において処理ガスである酸素ガスが励起されてプラズマ化され、イオン化される。酸素イオンが基板W1の主面W1cに照射されることにより、主面W1cが改質される。処理ガスは、酸素ガスには限定されず、例えば窒素ガスなどでもよい。
The surface modification unit 34 plasma-processes the main surface W1c of the substrate W1. In the surface modification section 34, for example, the oxygen gas, which is the processing gas, is excited under reduced pressure to be plasmatized and ionized. By irradiating the main surface W1c of the substrate W1 with oxygen ions, the main surface W1c is modified. The processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.
基板洗浄部35は、基板W1の主面W1cを洗浄する。例えば、基板洗浄部35は、スピンチャックに保持されている基板W1を回転させながら、基板W1の上に純水(例えば脱イオン水)を供給する。純水は、遠心力によって主面W1c全体に広がり、主面W1cを洗浄する。純水は、予め改質された主面W1cにOH基を付与する。OH基同士の水素結合を利用して、基板W1とチップCP1を貼合できる。
The substrate cleaning section 35 cleans the main surface W1c of the substrate W1. For example, the substrate cleaning unit 35 supplies pure water (for example, deionized water) onto the substrate W1 while rotating the substrate W1 held by the spin chuck. The pure water spreads over the entire main surface W1c due to centrifugal force and washes the main surface W1c. Pure water imparts OH groups to the main surface W1c that has been modified in advance. The substrate W1 and the chip CP1 can be bonded using hydrogen bonding between OH groups.
検査部36は、基板W1の主面W1cの異なる貼合領域に貼合された複数のチップCP1のそれぞれの貼合状態が良好か不良かを検査する。検査項目は、気泡などの異物の有無と、位置ずれの有無と、の少なくとも1つを含む。例えば気泡が基板W1とチップCP1の界面に有ると、チップ付き基板CW1が真空処理される際に、気泡が破裂する。気泡の破裂によって、貼合状態が良好なチップCP1まで問題が生じたり、真空チャンバーが汚染されたりする。あるいは、気泡または粒子が基板W1とチップCP1の界面に有ると、チップCP1の高さが高くなり、研削または研磨時にチッピングが生じ、その衝撃で貼合状態が良好なチップCP1まで問題が生じる。検査部36の詳細は後述する。
The inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. The inspection items include at least one of presence/absence of foreign matter such as air bubbles and presence/absence of misalignment. For example, if a bubble exists at the interface between the substrate W1 and the chip CP1, the bubble bursts when the chip-attached substrate CW1 is vacuum-processed. Due to the bursting of the air bubbles, even the chip CP1, which is in a good state of bonding, may cause problems, or the vacuum chamber may be contaminated. Alternatively, if air bubbles or particles exist at the interface between the substrate W1 and the chip CP1, the height of the chip CP1 increases, chipping occurs during grinding or polishing, and the resulting impact causes problems even for the chip CP1, which is in a good state of bonding. Details of the inspection unit 36 will be described later.
チップ剥離部37は、検査部36による検査で貼合状態が不良であったチップCP1を、基板W1から剥離する。貼合状態が不良であったチップCP1を基板W1から剥離することで、気泡または粒子が基板W1とチップCP1の界面にある場合に生じる問題を解決でき、チップ付き基板CW1の品質を向上できる。基板W1から剥離したチップCP1は、再利用されてもよいし、廃棄されてもよい。チップ剥離部37の詳細は後述する。
The chip peeling unit 37 peels off the chip CP1, which was found to be in a defective bonding state in the inspection by the inspection unit 36, from the substrate W1. By peeling off the chip CP1, which is in a poorly bonded state, from the substrate W1, the problem caused when air bubbles or particles are present at the interface between the substrate W1 and the chip CP1 can be solved, and the quality of the substrate CW1 with the chip can be improved. The chip CP1 separated from the substrate W1 may be reused or discarded. Details of the chip peeling portion 37 will be described later.
リワーク部38は、基板W1の主面W1cのうち、チップ剥離部37によってチップCP1を剥離した貼合領域を選択的に処理する。その処理は、チップCP1を剥離した貼合領域を、チップCP1を貼合する直前の状態に戻す処理である。例えば、リワーク部38は、チップCP1を剥離した貼合領域に対して選択的に、プラズマと水の少なくとも1つを供給する。リワーク部38の詳細は、後述する。
The rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off by the chip peeling unit 37 on the main surface W1c of the substrate W1. This process is a process of returning the bonding region from which the chip CP1 has been peeled off to the state immediately before bonding the chip CP1. For example, the rework unit 38 selectively supplies at least one of plasma and water to the bonding region from which the chip CP1 has been removed. Details of the rework unit 38 will be described later.
アニール部39は、チップ付き基板CW1を加熱処理する。加熱処理前に、チップCP1と基板W1は、OH基同士の水素結合によって結合されている。加熱処理によって、脱水縮合反応が生じ、共有結合が生じ、チップCP1と基板W1の接合強度が向上する。なお、チップ剥離部37によるチップCP1の剥離は、アニール部39によるチップ付き基板CW1の加熱処理前に行われる。
The annealing section 39 heats the chip-equipped substrate CW1. Before heat treatment, the chip CP1 and the substrate W1 are bonded by hydrogen bonding between OH groups. The heat treatment causes a dehydration-condensation reaction and a covalent bond, thereby improving the bonding strength between the chip CP1 and the substrate W1. Note that the chip CP<b>1 is peeled off by the chip peeling unit 37 before the chip-attached substrate CW<b>1 is heat-treated by the annealing unit 39 .
インターフェースブロック4は、第1処理ステーション3の搬送領域30に隣接する。インターフェースブロック4は、第1バッファ部41と、第2バッファ部42と、第2基板搬送アーム43と、第2フレーム搬送アーム44と、を備える。第1バッファ部41と第2バッファ部42は、第1処理ステーション3の搬送領域30に隣接している。第1バッファ部41と第2バッファ部42は、インターフェースブロック4のフットプリントを小さくすべく、鉛直方向に積層されてもよい。
The interface block 4 is adjacent to the transport area 30 of the first processing station 3 . The interface block 4 includes a first buffer section 41 , a second buffer section 42 , a second substrate transfer arm 43 and a second frame transfer arm 44 . The first buffer section 41 and the second buffer section 42 are adjacent to the transport area 30 of the first processing station 3 . The first buffer section 41 and the second buffer section 42 may be vertically stacked to reduce the footprint of the interface block 4 .
第1バッファ部41は、チップCP1を貼合する前の基板W1を保管する。第1バッファ部41は、チップ付き基板CW1を保管してもよい。チップCP1を貼合する前の基板W1を保管する第1バッファ部41と、チップ付き基板CW1を保管する第1バッファ部41とは、別々に設けられてもよく、それぞれ複数設けられてもよい。
The first buffer unit 41 stores the substrate W1 before bonding the chip CP1. The first buffer section 41 may store the chip-equipped substrate CW1. The first buffer section 41 that stores the substrate W1 before bonding the chip CP1 thereto and the first buffer section 41 that stores the substrate CW1 with the chip may be provided separately, or a plurality of each may be provided. .
第2バッファ部42は、フレームFR1と共に複数のチップCP1を保管する。第2バッファ部42は、使用済みのフレームFR1を保管してもよい。フレームFR1と共に複数のチップCP1を保管する第2バッファ部42と、使用済みのフレームFR1を保管する第2バッファ部42とは、別々に設けられてもよく、それぞれ複数設けられてもよい。
The second buffer unit 42 stores a plurality of chips CP1 together with the frame FR1. The second buffer section 42 may store the used frame FR1. The second buffer section 42 that stores the plurality of chips CP1 together with the frame FR1 and the second buffer section 42 that stores the used frame FR1 may be provided separately, or a plurality of each may be provided.
第2基板搬送アーム43は、チップCP1を貼合する前の基板W1を第1バッファ部41から取り出し、第2処理ステーション5の基板保持部51に搬送する。第2基板搬送アーム43は、チップ付き基板CW1を基板保持部51から第1バッファ部41に搬送してもよい。第2基板搬送アーム43は、水平方向(X軸方向及びY軸方向の両方向)及び鉛直方向の移動と、鉛直軸を中心とする回転とが可能である。チップCP1を貼合する前の基板W1を搬送する第2基板搬送アーム43と、チップ付き基板CW1を搬送する第2基板搬送アーム43とは、別々に設けられてもよい。
The second substrate transport arm 43 takes out the substrate W1 before bonding the chip CP1 from the first buffer unit 41 and transports it to the substrate holding unit 51 of the second processing station 5 . The second substrate transport arm 43 may transport the substrate CW1 with chips from the substrate holding section 51 to the first buffer section 41 . The second substrate transfer arm 43 is capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis. The second substrate transport arm 43 that transports the substrate W1 before bonding the chip CP1 thereto and the second substrate transport arm 43 that transports the substrate CW1 with the chip may be provided separately.
第2フレーム搬送アーム44は、フレームFR1と共に複数のチップCP1を第2バッファ部42から取り出し、第2処理ステーション5のチップ保持部52に搬送する。第2フレーム搬送アーム44は、使用済みのフレームFR1をチップ保持部52から第2バッファ部42に搬送してもよい。第2フレーム搬送アーム44は、水平方向(X軸方向及びY軸方向の両方向)及び鉛直方向の移動と、鉛直軸を中心とする回転とが可能である。フレームFR1と共に複数のチップCP1を搬送する第2フレーム搬送アーム44と、使用済みのフレームFR1を搬送する第2フレーム搬送アーム44とは、別々に設けられてもよい。
The second frame transport arm 44 takes out the plurality of chips CP1 together with the frame FR1 from the second buffer section 42 and transports them to the chip holding section 52 of the second processing station 5 . The second frame transport arm 44 may transport the used frame FR1 from the chip holding section 52 to the second buffer section 42 . The second frame transfer arm 44 is capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis. The second frame transfer arm 44 that transfers the plurality of chips CP1 together with the frame FR1 and the second frame transfer arm 44 that transfers the used frame FR1 may be provided separately.
インターフェースブロック4は、第2基板搬送アーム43と第2フレーム搬送アーム44を移動または回転させる図示しない駆動部を有する。第2基板搬送アーム43と第2フレーム搬送アーム44は、所定方向に同時に移動させられてもよいし、所定方向に独立に移動させられてもよい。第2基板搬送アーム43と第2フレーム搬送アーム44は、図1及び図2ではZ軸方向に積層されていないが、Z軸方向に積層されてもよい。
The interface block 4 has a drive section (not shown) that moves or rotates the second substrate transfer arm 43 and the second frame transfer arm 44 . The second substrate transfer arm 43 and the second frame transfer arm 44 may be moved simultaneously in a predetermined direction, or may be moved independently in a predetermined direction. Although the second substrate transfer arm 43 and the second frame transfer arm 44 are not stacked in the Z-axis direction in FIGS. 1 and 2, they may be stacked in the Z-axis direction.
インターフェースブロック4は、前処理(例えば表面改質と洗浄)を実施済みの基板W1と、前処理(例えば洗浄)を実施済みの複数のチップCP1とを保管する。これにより、第2処理ステーション5の稼働率を向上でき、チップ付き基板CW1の生産効率を向上できる。
The interface block 4 stores a substrate W1 that has undergone pretreatment (for example, surface modification and cleaning) and a plurality of chips CP1 that have undergone pretreatment (for example, cleaning). As a result, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrates CW1 with chips can be improved.
なお、インターフェースブロック4は無くてもよく、第1処理ステーション3と第2処理ステーション5とが隣接していてもよい。この場合、第1処理ステーション3の第1基板搬送アーム31が、チップCP1を貼合する前の基板W1を第2処理ステーション5の基板保持部51に搬送し、チップ付き基板CW1を基板保持部51から受け取る。また、この場合、第1処理ステーション3の第1フレーム搬送アーム32が、フレームFR1と共に複数のチップCP1を第2処理ステーション5のチップ保持部52に搬送し、使用済みのフレームFR1をチップ保持部52から受け取る。
The interface block 4 may be omitted, and the first processing station 3 and the second processing station 5 may be adjacent to each other. In this case, the first substrate transport arm 31 of the first processing station 3 transports the substrate W1 before bonding the chip CP1 to the substrate holding unit 51 of the second processing station 5, and the substrate CW1 with chips is transferred to the substrate holding unit. Received from 51. Also, in this case, the first frame transport arm 32 of the first processing station 3 transports the plurality of chips CP1 together with the frame FR1 to the chip holding section 52 of the second processing station 5, and transfers the used frame FR1 to the chip holding section. Received from 52.
第2処理ステーション5は、インターフェースブロック4を基準として第1処理ステーション3の搬送領域30とは反対側に配置される。第2処理ステーション5は、基板保持部51と、チップ保持部52と、ピックアップ部53と、マウント部54と、を備える。基板保持部51は、基板W1を保持する。チップ保持部52は、複数のチップCP1がテープTP1を介してフレームFR1に装着された状態で、複数のチップCP1を保持する。基板保持部51とチップ保持部52は、それぞれ、水平方向(X軸方向及びY軸方向の両方向)の移動と、鉛直軸を中心とする回転とが可能である。ピックアップ部53は、チップ保持部52で保持されているチップCP1をテープTP1から剥離する。マウント部54は、ピックアップ部53でテープTP1から剥離したチップCP1を基板W1の主面W1cに実装する。第2処理ステーション5の詳細は後述する。
The second processing station 5 is arranged on the opposite side of the transfer area 30 of the first processing station 3 with respect to the interface block 4 . The second processing station 5 includes a substrate holding section 51 , a chip holding section 52 , a pickup section 53 and a mounting section 54 . The substrate holding part 51 holds the substrate W1. The chip holding unit 52 holds the plurality of chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1. The substrate holding part 51 and the chip holding part 52 are each capable of horizontal movement (both the X-axis direction and the Y-axis direction) and rotation about the vertical axis. The pickup unit 53 separates the chip CP1 held by the chip holding unit 52 from the tape TP1. The mounting unit 54 mounts the chip CP1 separated from the tape TP1 by the pickup unit 53 onto the main surface W1c of the substrate W1. Details of the second processing station 5 will be described later.
インターフェースブロック4と、第2処理ステーション5とで、チップ貼合部6が構成される。チップ貼合部6は、第1処理ステーション3の搬送領域30に隣接している。なお、既述の通り、インターフェースブロック4は無くてもよく、第2処理ステーション5のみでチップ貼合部6が構成されてもよい。
A chip bonding section 6 is composed of the interface block 4 and the second processing station 5 . The chip bonding section 6 is adjacent to the transfer area 30 of the first processing station 3 . As described above, the interface block 4 may be omitted, and the chip bonding section 6 may be composed of only the second processing station 5 .
制御部9は、例えばコンピュータであり、CPU(Central Processing Unit)91と、メモリなどの記憶媒体92と、を備える。記憶媒体92には、基板処理装置1において実行される各種の処理を制御するプログラムが格納される。制御部9は、記憶媒体92に記憶されたプログラムをCPU91に実行させることにより、基板処理装置1の動作を制御する。基板処理装置1を構成するユニットごとにユニットの動作を制御するユニット制御部が設けられ、複数のユニット制御部を統括制御するシステム制御部が設けられてもよい。ユニット制御部とシステム制御部とで制御部9が構成されてもよい。
The control unit 9 is, for example, a computer, and includes a CPU (Central Processing Unit) 91 and a storage medium 92 such as a memory. The storage medium 92 stores programs for controlling various processes executed in the substrate processing apparatus 1 . The control unit 9 controls the operation of the substrate processing apparatus 1 by causing the CPU 91 to execute programs stored in the storage medium 92 . A unit controller for controlling the operation of each unit constituting the substrate processing apparatus 1 may be provided, and a system controller for integrally controlling a plurality of unit controllers may be provided. The control section 9 may be configured by the unit control section and the system control section.
次に、図3を参照して、一実施形態に係る基板処理方法について説明する。図3の処理は、制御部9による制御下で実施される。
Next, a substrate processing method according to one embodiment will be described with reference to FIG. The processing in FIG. 3 is performed under the control of the control unit 9 .
先ず、搬入出ステーション2の第3基板搬送アーム22が、カセットC1から基板W1を取り出し、基板載置部24に搬送する。次に、第1処理ステーション3の第1基板搬送アーム31が、基板載置部24から基板W1を取り出し、表面改質部34に搬送する。次に、表面改質部34が、基板W1の主面W1cをプラズマ処理する(ステップS101)。その後、第1基板搬送アーム31が、表面改質部34から基板W1を取り出し、基板洗浄部35に搬送する。次に、基板洗浄部35が、基板W1の主面W1cを洗浄する(ステップS102)。その後、第1基板搬送アーム31が、基板洗浄部35から基板W1を取り出し、インターフェースブロック4の第1バッファ部41に搬送する。次に、第2基板搬送アーム43が、第1バッファ部41から基板W1を取り出し、第2処理ステーション5の基板保持部51に搬送する。
First, the third substrate transfer arm 22 of the loading/unloading station 2 takes out the substrate W1 from the cassette C1 and transfers it to the substrate platform 24 . Next, the first substrate transport arm 31 of the first processing station 3 takes out the substrate W1 from the substrate platform 24 and transports it to the surface modification unit 34 . Next, the surface modification unit 34 plasma-processes the main surface W1c of the substrate W1 (step S101). After that, the first substrate transfer arm 31 takes out the substrate W<b>1 from the surface modification section 34 and transfers it to the substrate cleaning section 35 . Next, the substrate cleaning section 35 cleans the main surface W1c of the substrate W1 (step S102). After that, the first substrate transport arm 31 takes out the substrate W1 from the substrate cleaning section 35 and transports it to the first buffer section 41 of the interface block 4 . Next, the second substrate transfer arm 43 takes out the substrate W1 from the first buffer section 41 and transfers it to the substrate holding section 51 of the second processing station 5 .
上記の処理と並行して、下記の処理が行われる。先ず、搬入出ステーション2の第3フレーム搬送アーム23が、カセットC3からフレームFR1と共に複数のチップCP1を取り出し、フレーム載置部25に搬送する。次に、第1処理ステーション3の第1フレーム搬送アーム32が、フレーム載置部25からフレームFR1と共に複数のチップCP1を取り出し、チップ洗浄部33に搬送する。次に、チップ洗浄部33が、複数のチップCP1を洗浄する(ステップS103)。その後、第1フレーム搬送アーム32が、チップ洗浄部33からフレームFR1と共に複数のチップCP1を取り出し、インターフェースブロック4の第2バッファ部42に搬送する。次に、第2フレーム搬送アーム44が、第2バッファ部42からフレームFR1と共に複数のチップCP1を取り出し、第2処理ステーション5のチップ保持部52に搬送する。
In parallel with the above processing, the following processing is performed. First, the third frame transfer arm 23 of the loading/unloading station 2 takes out a plurality of chips CP1 together with the frame FR1 from the cassette C3, and transfers them to the frame mounting section 25. As shown in FIG. Next, the first frame transfer arm 32 of the first processing station 3 takes out the plurality of chips CP1 together with the frame FR1 from the frame mounting section 25 and transfers them to the chip cleaning section 33 . Next, the chip cleaning unit 33 cleans the multiple chips CP1 (step S103). After that, the first frame transport arm 32 takes out the plurality of chips CP1 together with the frame FR1 from the chip cleaning section 33 and transports them to the second buffer section 42 of the interface block 4 . Next, the second frame transport arm 44 takes out the plurality of chips CP1 together with the frame FR1 from the second buffer section 42 and transports them to the chip holding section 52 of the second processing station 5 .
次に、チップ貼合部6が、基板W1の主面W1cの異なる貼合領域に、複数のチップCP1を貼合する(ステップS104)。これにより、チップ付き基板CW1が得られる。その後、第2基板搬送アーム43が、基板保持部51からチップ付き基板CW1を取り出し、第1バッファ部41に搬送する。次に、第1処理ステーション3の第1基板搬送アーム31が、第1バッファ部41からチップ付き基板CW1を取り出し、検査部36に搬送する。
Next, the chip bonding section 6 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1 (step S104). Thus, a chip-equipped substrate CW1 is obtained. After that, the second substrate transport arm 43 takes out the substrate CW1 with chips from the substrate holding section 51 and transports it to the first buffer section 41 . Next, the first substrate transfer arm 31 of the first processing station 3 takes out the chip-attached substrate CW1 from the first buffer section 41 and transfers it to the inspection section 36 .
次に、検査部36が、基板W1の主面W1cの異なる貼合領域に貼合された複数のチップCP1のそれぞれの貼合状態が良好か不良かを検査する(ステップS105)。検査部36は、検査結果を制御部9に送信する。制御部9は、不良の有無をチェックする(ステップS106)。制御部9は、検査部36による検査結果に応じて、チップ付き基板CW1の搬送先を、アニール部39とチップ剥離部37とに振り分ける制御を行う。
Next, the inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad (step S105). The inspection unit 36 transmits inspection results to the control unit 9 . The control unit 9 checks whether there is a defect (step S106). The control unit 9 performs control to sort the transfer destination of the substrate CW1 with chips between the annealing unit 39 and the chip peeling unit 37 according to the inspection result by the inspection unit 36 .
チップCP1の貼合状態に不良が有る場合(ステップS106、NO)、チップ付き基板CW1の搬送先は、チップ剥離部37になる。第1基板搬送アーム31が、検査部36からチップ付き基板CW1を取り出し、チップ剥離部37に搬送する。次に、チップ剥離部37が、貼合状態が不良であったチップCP1を、基板W1から剥離する(ステップS107)。その後、第1基板搬送アーム31が、チップ剥離部37からチップ付き基板CW1を取り出し、リワーク部38に搬送する。次に、リワーク部38が、チップCP1を剥離した貼合領域を選択的に処理する(ステップS108)。その後、第1基板搬送アーム31が、リワーク部38からチップ付き基板CW1取り出し、チップ貼合部6に搬送する。
When there is a defect in the bonding state of the chip CP1 (step S106, NO), the destination of the chip-attached substrate CW1 is the chip peeling section 37. The first substrate transport arm 31 takes out the substrate CW1 with chips from the inspection section 36 and transports it to the chip peeling section 37 . Next, the chip peeling unit 37 peels off the chip CP1, which was in a defective bonding state, from the substrate W1 (step S107). After that, the first substrate transport arm 31 takes out the substrate CW1 with chips from the chip peeling section 37 and transports it to the rework section 38 . Next, the rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off (step S108). After that, the first substrate transfer arm 31 takes out the chip-attached substrate CW1 from the rework section 38 and transfers it to the chip bonding section 6 .
次に、チップ貼合部6が、チップCP1を剥離した貼合領域に、チップCP1を再度貼合するか、またはチップCP1を再度貼合することなくチップCP1とは別に用意されたダミーチップDC1(図8参照)を貼合する(ステップS109)。ダミーチップDC1は、チップCP1とは異なり、デバイス、つまり電気回路を有しない。例えば、ダミーチップDC1は、シリコンウェハ、化合物半導体ウェハ、又はガラス基板のみからなる。なお、チップ貼合部6は、チップCP1を剥離した貼合領域に、チップCP1もダミーチップDC1も貼合しなくてもよく、何も貼合しなくてもよい。
Next, the chip bonding unit 6 either bonds the chip CP1 again to the bonding region where the chip CP1 has been peeled off, or the dummy chip DC1 prepared separately from the chip CP1 without bonding the chip CP1 again. (see FIG. 8) are pasted together (step S109). Unlike chip CP1, dummy chip DC1 does not have a device, that is, an electric circuit. For example, the dummy chip DC1 consists of only a silicon wafer, a compound semiconductor wafer, or a glass substrate. Note that the chip bonding unit 6 may bond neither the chip CP1 nor the dummy chip DC1, or bond anything on the bonding region from which the chip CP1 has been peeled off.
チップCP1を基板W1から剥離した時に、基板W1のデバイスW1bが損傷してしまうことがある。損傷したデバイスW1bにチップCP1を再度貼合することは、チップCP1の無駄である。損傷したデバイスW1bにチップCP1を貼合しなければ、チップCP1の無駄を防止できる。この効果は、損傷したデバイスW1bに何も貼合しない場合にも得られる。
When the chip CP1 is separated from the substrate W1, the device W1b on the substrate W1 may be damaged. Bonding the chip CP1 again to the damaged device W1b is a waste of the chip CP1. Waste of the chip CP1 can be prevented by not bonding the chip CP1 to the damaged device W1b. This effect is obtained even when nothing is attached to the damaged device W1b.
なお、図17(A)に示すように基板W1がデバイスW1bを有しない場合、チップCP1を剥離した貼合領域にチップCP1を再度貼合することが好ましい。チップCP1を再度貼合しない場合(チップCP1を再度貼合することなくダミーチップDC1を再度貼合する場合を含む)、図17(D)に示す基板W3のデバイスW3bが無駄になるからである。
Note that when the substrate W1 does not have the device W1b as shown in FIG. 17A, it is preferable to bond the chip CP1 again to the bonding region from which the chip CP1 has been peeled off. This is because if the chip CP1 is not bonded again (including the case that the dummy chip DC1 is bonded again without bonding the chip CP1 again), the device W3b on the substrate W3 shown in FIG. 17D is wasted. .
チップ貼合部6は、既述の通り、チップCP1を剥離した貼合領域に、チップCP1を再度貼合するか、またはダミーチップDC1を貼合する(ステップS109)。この場合、チップCP1を剥離した貼合領域に何も貼合しない場合とは異なり、チップCP1が実装されるスペースが空いたまま、チップ付き基板CW1が後処理に供されるのを防止でき、後処理の品質を向上できる。例えば研削または研磨時に、均一な処理が可能である。
As described above, the chip bonding unit 6 bonds the chip CP1 again or bonds the dummy chip DC1 to the bonding region from which the chip CP1 has been peeled off (step S109). In this case, unlike the case where nothing is bonded to the bonding area from which the chip CP1 has been peeled off, it is possible to prevent the substrate CW1 with the chip from being subjected to post-processing while leaving a space for mounting the chip CP1. The quality of post-processing can be improved. Uniform processing is possible, for example when grinding or polishing.
ステップS109の後、第1処理ステーション3の第1基板搬送アーム31が、チップ貼合部6からチップ付き基板CW1を取り出し、検査部36に搬送する。その後、ステップS105以降の処理が再度行われる。なお、ステップS109の後、第1基板搬送アーム31が、チップ貼合部6からチップ付き基板CW1を取り出し、アニール部39に搬送してもよい。その後、ステップS110以降の処理が行われる。
After step S<b>109 , the first substrate transfer arm 31 of the first processing station 3 takes out the chip-attached substrate CW<b>1 from the chip bonding section 6 and transfers it to the inspection section 36 . After that, the processing after step S105 is performed again. After step S<b>109 , the first substrate transfer arm 31 may take out the chip-attached substrate CW<b>1 from the chip bonding section 6 and transfer it to the annealing section 39 . After that, the processing after step S110 is performed.
一方、全てのチップCP1の貼合状態に不良が無い場合(ステップS106、YES)、チップ付き基板CW1の搬送先は、アニール部39になる。第1基板搬送アーム31が、検査部36からチップ付き基板CW1を取り出し、アニール部39に搬送する。次に、アニール部39が、チップ付き基板CW1を加熱処理する(ステップS110)。加熱処理によって、チップCP1と基板W1の接合強度が向上する。
On the other hand, if there is no defect in the bonded state of all the chips CP1 (step S106, YES), the annealing unit 39 is the transfer destination of the substrate CW1 with chips. The first substrate transfer arm 31 takes out the chip-attached substrate CW1 from the inspection section 36 and transfers it to the annealing section 39 . Next, the annealing section 39 heats the substrate CW1 with chips (step S110). The heat treatment improves the bonding strength between the chip CP1 and the substrate W1.
その後、第1基板搬送アーム31が、アニール部39からチップ付き基板CW1を取り出し、搬入出ステーション2の基板載置部24に載置する。最後に、搬入出ステーション2の第3基板搬送アーム22が、基板載置部24からチップ付き基板CW1を取り出し、カセットC2に収納する。チップ付き基板CW1は、カセットC2に収納された状態で、基板処理装置1から搬出される。
After that, the first substrate transfer arm 31 takes out the substrate CW1 with chips from the annealing section 39 and places it on the substrate mounting section 24 of the loading/unloading station 2 . Finally, the third substrate transfer arm 22 of the loading/unloading station 2 takes out the substrate CW1 with chips from the substrate mounting section 24 and stores it in the cassette C2. The chip-equipped substrate CW1 is unloaded from the substrate processing apparatus 1 while being accommodated in the cassette C2.
なお、ステップS104の後、第1処理ステーション3の第1フレーム搬送アーム32が、チップ貼合部6から使用済みのフレームFR1を取り出し、搬入出ステーション2のフレーム載置部25に載置する。次に、搬入出ステーション2の第3フレーム搬送アーム23が、フレーム載置部25から使用済みのフレームFR1を取り出し、カセットC4に収納する。
After step S104, the first frame transfer arm 32 of the first processing station 3 takes out the used frame FR1 from the chip bonding section 6 and places it on the frame mounting section 25 of the loading/unloading station 2. Next, the third frame transfer arm 23 of the loading/unloading station 2 takes out the used frame FR1 from the frame mounting section 25 and stores it in the cassette C4.
次に、図4を参照して、第1処理ステーション3の第1フレーム搬送アーム32の一例について説明する。第1フレーム搬送アーム32は、フレームFR1を載せる一対のガイドレール321と、フレームFR1を掴む把持部322と、一対のガイドレール321の長手方向に把持部322を移動させる駆動部323と、を有する。
Next, an example of the first frame transfer arm 32 of the first processing station 3 will be described with reference to FIG. The first frame transport arm 32 has a pair of guide rails 321 on which the frame FR1 is placed, a gripping portion 322 that grips the frame FR1, and a driving portion 323 that moves the gripping portion 322 in the longitudinal direction of the pair of guide rails 321. .
なお、搬入出ステーション2の第3フレーム搬送アーム23と、インターフェースブロック4の第2フレーム搬送アーム44も、第1処理ステーション3の第1フレーム搬送アーム32と同様に構成されてもよく、フレームFR1を載せる一対のガイドレールと、フレームFR1を掴む把持部と、一対のガイドレールの長手方向に把持部を移動させる駆動部と、を有してもよい。
The third frame transfer arm 23 of the loading/unloading station 2 and the second frame transfer arm 44 of the interface block 4 may be configured similarly to the first frame transfer arm 32 of the first processing station 3. a pair of guide rails on which the frame FR1 is placed, a gripping portion that grips the frame FR1, and a driving portion that moves the gripping portion in the longitudinal direction of the pair of guide rails.
一対のガイドレール321は、それぞれ、断面L字形状を有し、水平板321aと鉛直板321bとを含む。上方から見たときに、一対の鉛直板321bが、フレームFR1を挟んで配置され、鉛直板321bと直交する方向へのフレームFR1の移動を規制する。フレームFR1は、一対の水平板321aの上に載置される。
Each of the pair of guide rails 321 has an L-shaped cross section and includes a horizontal plate 321a and a vertical plate 321b. When viewed from above, a pair of vertical plates 321b are arranged to sandwich the frame FR1, and restrict movement of the frame FR1 in a direction perpendicular to the vertical plates 321b. The frame FR1 is placed on a pair of horizontal plates 321a.
第1フレーム搬送アーム32が、把持部322に加えて、一対のガイドレール321を有することで、フレームFR1を安定的に支持できる。また、駆動部323が、一対のガイドレール321の長手方向に把持部322を移動させることで、所望の装置(例えばチップ洗浄部33)との間でフレームFR1を円滑に受け渡すことができる。
The first frame transfer arm 32 has a pair of guide rails 321 in addition to the grip portion 322, so that the frame FR1 can be stably supported. Further, the driving section 323 moves the gripping section 322 in the longitudinal direction of the pair of guide rails 321, so that the frame FR1 can be smoothly transferred to and from a desired device (for example, the tip cleaning section 33).
図4に示すように、チップ洗浄部33は、一対のガイドレール338を有してもよい。一対のガイドレール338と、一対のガイドレール321とを連続的に並べることで、フレームFR1を円滑に受け渡すことができる。一対のガイドレール338は、水平方向及び鉛直方向に移動可能であってもよい。
As shown in FIG. 4, the tip cleaning section 33 may have a pair of guide rails 338 . By continuously arranging the pair of guide rails 338 and the pair of guide rails 321, the frame FR1 can be transferred smoothly. The pair of guide rails 338 may be horizontally and vertically movable.
一対のガイドレール338は、それぞれ、断面L字形状を有し、水平板338aと鉛直板338bとを含む。上方から見たときに、一対の鉛直板338bが、フレームFR1を挟んで配置され、鉛直板338bと直交する方向へのフレームFR1の移動を規制する。フレームFR1は、一対の水平板338aの上に載置される。
Each of the pair of guide rails 338 has an L-shaped cross section and includes a horizontal plate 338a and a vertical plate 338b. When viewed from above, a pair of vertical plates 338b are arranged to sandwich the frame FR1 and restrict movement of the frame FR1 in a direction perpendicular to the vertical plates 338b. The frame FR1 is placed on a pair of horizontal plates 338a.
チップ洗浄部33は、内部搬送部339を有してもよい。図4(B)に示すように、内部搬送部339は、チップ洗浄部33の内部で、フレームFR1を上方から保持して搬送する。内部搬送部339は、一対のガイドレール338と、後述するフレーム保持部332との間で、フレームFR1を搬送する。
The tip cleaning section 33 may have an internal transport section 339 . As shown in FIG. 4B, inside the chip cleaning section 33, the internal transport section 339 holds and transports the frame FR1 from above. The internal transport section 339 transports the frame FR1 between the pair of guide rails 338 and the frame holding section 332, which will be described later.
内部搬送部339は、例えば複数本のアーム339aを有する。上方から見たときに、複数本のアーム339aは、それぞれ、フレームFR1の開口部を横切っており、長手方向両端でフレームFR1を上方から吸着して搬送する。内部搬送部339は、水平方向(X軸方向及びY軸方向の両方向)及び鉛直方向の移動が可能である。
The internal transport section 339 has, for example, a plurality of arms 339a. When viewed from above, each of the plurality of arms 339a traverses the opening of the frame FR1, and both ends in the longitudinal direction attract and transport the frame FR1 from above. The internal transport section 339 is capable of horizontal (both X-axis and Y-axis) and vertical movement.
次に、図5と図6を参照して、チップ洗浄部33の一例について説明する。チップ洗浄部33は、例えば、チップ保持部331と、フレーム保持部332と、を有する。チップ保持部331は、テープTP1を介して複数のチップCP1を下方から水平に保持する。後述するエキスパンド部333がテープTP1を放射状に拡張する場合、チップ保持部331はテープTP1を摺動自在に載せる。なお、チップ保持部331は、真空チャック機構を有し、テープTP1を固定してもよい。
Next, an example of the tip cleaning section 33 will be described with reference to FIGS. 5 and 6. FIG. The chip cleaning section 33 has, for example, a chip holding section 331 and a frame holding section 332 . The chip holding part 331 horizontally holds the plurality of chips CP1 from below via the tape TP1. When the later-described expanding section 333 expands the tape TP1 radially, the chip holding section 331 slidably mounts the tape TP1. Note that the chip holding portion 331 may have a vacuum chuck mechanism to fix the tape TP1.
フレーム保持部332は、フレームFR1を下方から水平に保持する。フレーム保持部332は、真空チャック機構またはメカニカルチャック機構を有し、フレームFR1を固定する。後述する回転駆動部334がフレーム保持部332を回転駆動させることで、フレームFR1と共に複数のチップCP1が回転する。
The frame holding portion 332 horizontally holds the frame FR1 from below. The frame holder 332 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1. A rotation drive unit 334, which will be described later, rotates the frame holding unit 332, thereby rotating the plurality of chips CP1 together with the frame FR1.
チップ洗浄部33は、エキスパンド部333を有してもよい。エキスパンド部333は、図6に示すように、テープTP1を放射状に拡張することで、隣り合うチップCP1同士の間隔を広げる。例えば、エキスパンド部333は、フレーム保持部332に対してチップ保持部331を相対的に上昇させることで、テープTP1を放射状に拡張する。隣り合うチップCP1同士の間隔を広げることで、チップCP1の側面を効率よく洗浄できる。
The tip cleaning section 33 may have an expanding section 333 . As shown in FIG. 6, the expanding section 333 widens the interval between the adjacent chips CP1 by radially expanding the tape TP1. For example, the expanding section 333 radially expands the tape TP1 by raising the chip holding section 331 relative to the frame holding section 332 . By widening the interval between the adjacent chips CP1, the side surfaces of the chips CP1 can be efficiently cleaned.
チップ洗浄部33は、回転駆動部334と、ノズル335と、カップ336と、を有してもよい。回転駆動部334は、フレーム保持部332を回転駆動させることで、フレームFR1と共に複数のチップCP1を回転させる。回転駆動部334は、フレーム保持部332と共にチップ保持部331も回転駆動させる。ノズル335は、複数のチップCP1に対して洗浄液を供給する。洗浄液は、薬液またはリンス液などである。リンス液は、DIW(脱イオン水)などの純水である。ノズル335は、チップ保持部331などの回転中心線と直交する方向に移動してもよい。カップ336は、洗浄液を回収する。
The tip cleaning section 33 may have a rotary drive section 334 , a nozzle 335 and a cup 336 . The rotation driving unit 334 rotates the frame holding unit 332 to rotate the plurality of chips CP1 together with the frame FR1. The rotation driving section 334 rotates the chip holding section 331 together with the frame holding section 332 . The nozzle 335 supplies cleaning liquid to the multiple chips CP1. The cleaning liquid is a chemical liquid, a rinse liquid, or the like. The rinse liquid is pure water such as DIW (deionized water). The nozzle 335 may move in a direction perpendicular to the rotation centerline of the tip holder 331 or the like. A cup 336 collects the cleaning fluid.
チップ洗浄部33は、洗浄ヘッド337を有してもよい。洗浄ヘッド337は、ブラシまたはスポンジなどであり、複数のチップCP1をスクラブ洗浄する。洗浄ヘッド337は、複数のチップCP1との間に形成される液膜に対して超音波を付与するものであってもよい。液膜は、ノズル335が洗浄液を供給することで形成される。
The tip cleaning section 33 may have a cleaning head 337 . The cleaning head 337 is a brush, sponge, or the like, and scrubs and cleans the chips CP1. The cleaning head 337 may apply ultrasonic waves to the liquid film formed between the plurality of chips CP1. The liquid film is formed by supplying the cleaning liquid from the nozzle 335 .
次に、図7を参照して、第2処理ステーション5の一例について説明する。第2処理ステーション5は、既述の通り、基板保持部51と、チップ保持部52と、ピックアップ部53と、マウント部54と、を備える。
Next, an example of the second processing station 5 will be described with reference to FIG. The second processing station 5 includes a substrate holding section 51, a chip holding section 52, a pickup section 53, and a mounting section 54, as described above.
基板保持部51は、基板W1を保持する。基板保持部51は、例えば基板W1の主面W1cを上に向けて、基板W1を水平に保持する。基板W1の主面W1cが貼合領域ごとにデバイスW1bを有してもよく、基板保持部51はデバイスW1bを上に向けて基板W1を水平に保持してもよい。
The substrate holding part 51 holds the substrate W1. The substrate holding unit 51 holds the substrate W1 horizontally, for example, with the main surface W1c of the substrate W1 facing upward. The main surface W1c of the substrate W1 may have a device W1b for each bonding region, and the substrate holding section 51 may hold the substrate W1 horizontally with the device W1b facing upward.
チップ保持部52は、複数のチップCP1がテープTP1を介してフレームFR1に装着された状態で、複数のチップCP1を保持する。チップ保持部52は、例えば複数のチップCP1のそれぞれのデバイスCP1bを上に向けて、複数のチップCP1を水平に保持する。
The chip holding unit 52 holds the plurality of chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1. The chip holding unit 52 horizontally holds the plurality of chips CP1, for example, with the devices CP1b of the plurality of chips CP1 facing upward.
ピックアップ部53は、複数のチップCP1を個別にテープTP1から剥離する。ピックアップ部53は、第1吸着ヘッド531を有する。第1吸着ヘッド531は、チップCP1をテープTP1とは反対側から吸着する。例えば、第1吸着ヘッド531は、チップCP1を上方から吸着する。
The pickup unit 53 separates the plurality of chips CP1 individually from the tape TP1. The pickup section 53 has a first suction head 531 . The first suction head 531 sucks the chip CP1 from the side opposite to the tape TP1. For example, the first suction head 531 sucks the chip CP1 from above.
第1吸着ヘッド531は、チップCP1を吸着した状態で、上方に移動することで、チップCP1をテープTP1から剥離する。第1吸着ヘッド531は、上下反転可能であってもよい。チップCP1を上下反転することで、チップCP1のデバイスCP1bを基板W1に向けた状態でチップCP1を基板W1に実装できる。
The first suction head 531 removes the chip CP1 from the tape TP1 by moving upward while sucking the chip CP1. The first suction head 531 may be upside down. By turning the chip CP1 upside down, the chip CP1 can be mounted on the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1.
チップ保持部52は、突き上げピン532を有してもよい。突き上げピン532は、テープTP1を介してチップCP1を下方から突き上げる。第1吸着ヘッド531は、突き上げピン532で突き上げたチップCP1を吸着する。これにより、隣り合うチップCP1同士が擦れ合うことを抑制できる。
The tip holding part 52 may have a push-up pin 532 . The push-up pin 532 pushes up the chip CP1 from below via the tape TP1. The first suction head 531 sucks the chip CP<b>1 pushed up by the push-up pin 532 . Thereby, it is possible to prevent the adjacent chips CP1 from rubbing against each other.
図示しないが、ピックアップ部53は、チップ洗浄部33と同様に、エキスパンド部を有してもよい。エキスパンド部は、テープTP1を放射状に拡張することで、隣り合うチップCP1同士の間隔を広げる。これにより、隣り合うチップCP1同士が擦れ合うことを抑制できる。
Although not shown, the pick-up section 53 may have an expanding section similar to the tip cleaning section 33 . The expanding section widens the interval between adjacent chips CP1 by radially expanding the tape TP1. Thereby, it is possible to prevent the adjacent chips CP1 from rubbing against each other.
マウント部54は、チップCP1のデバイスCP1bを基板W1に向けた状態で、チップCP1を基板W1の主面W1cに実装する。マウント部54は、第2吸着ヘッド541を有する。第2吸着ヘッド541は、上下反転したチップCP1を上方から吸着し、その状態で下方に移動することで、チップCP1を基板W1の主面W1cに実装する。
The mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1. The mount section 54 has a second suction head 541 . The second suction head 541 sucks the upside-down chip CP1 from above and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1.
なお、本実施形態ではマウント部54の第2吸着ヘッド541がピックアップ部53の第1吸着ヘッド531からチップCP1を直接受け取るが、図示しない搬送部を介して受け取ってもよい。搬送部は、ピックアップ部53からマウント部54にチップCP1を搬送する。搬送部が、チップCP1を上下反転してもよい。
In this embodiment, the second suction head 541 of the mount section 54 directly receives the chip CP1 from the first suction head 531 of the pickup section 53, but it may be received via a transport section (not shown). The transport unit transports the chip CP<b>1 from the pickup unit 53 to the mount unit 54 . The transport section may turn the chip CP1 upside down.
図7に示すように、基板W1の主面W1cが貼合領域ごとにデバイスW1bを有する場合、制御部9が情報取得部93を有してもよい。情報取得部93は、貼合領域ごとにデバイスW1bの状態が良好か不良かを示す情報を取得する。デバイスW1bの状態が良好か不良かは、外部の検査装置で検査される。検査装置は、例えばデバイスW1bの外観検査または動作検査を行い、その検査結果を制御部9に送信する。
As shown in FIG. 7, when the main surface W1c of the substrate W1 has a device W1b for each bonding region, the control section 9 may have an information acquisition section 93. The information acquisition unit 93 acquires information indicating whether the state of the device W1b is good or bad for each bonding region. Whether the device W1b is in good condition or not is inspected by an external inspection device. The inspection device performs, for example, an appearance inspection or an operation inspection of the device W1b, and transmits the inspection result to the control unit 9. FIG.
チップ貼合部6は、制御部9による制御下で、状態が良好であるデバイスW1bにはチップCP1を貼合し、状態が不良であるデバイスW1bにはダミーチップDC1(図8参照)を貼合する。なお、チップ貼合部6は、状態が不良であるデバイスW1bには、チップCP1もダミーチップDC1も貼合しなくてもよく、何も貼合しなくてもよい。
Under the control of the control unit 9, the chip bonding unit 6 bonds the chip CP1 to the device W1b in good condition, and bonds the dummy chip DC1 (see FIG. 8) to the device W1b in poor condition. match. Note that the chip bonding unit 6 may bond neither the chip CP1 nor the dummy chip DC1, or bond anything on the device W1b in the defective state.
状態が不良であるデバイスW1bにチップCP1を貼合することは、チップCP1の無駄である。状態が不良であるデバイスW1bにチップCP1を貼合しないことで、チップCP1の無駄を防止できる。この効果は、状態が不良であるデバイスW1bに何も貼合しない場合にも得られる。
Bonding the chip CP1 to the device W1b in a bad state is a waste of the chip CP1. Waste of the chip CP1 can be prevented by not bonding the chip CP1 to the device W1b in a defective state. This effect can be obtained even when nothing is attached to the device W1b which is in a bad state.
また、状態が不良であるデバイスW1bにチップCP1を貼合することなくダミーチップDC1を貼合すれば、何も貼合しない場合とは異なり、チップCP1が実装されるスペースが空いたまま、チップ付き基板CW1が後処理に供されるのを防止でき、後処理の品質を向上できる。
Also, if the dummy chip DC1 is bonded without bonding the chip CP1 to the device W1b that is in a defective state, unlike the case where nothing is bonded, the space for mounting the chip CP1 remains empty. The attached substrate CW1 can be prevented from being subjected to post-processing, and the quality of the post-processing can be improved.
次に、図9を参照して、検査部36の一例について説明する。検査部36は、基板W1の主面W1cの異なる貼合領域に貼合された複数のチップCP1のそれぞれの貼合状態が良好か不良かを検査する。検査項目は、気泡などの異物の有無と、位置ずれの有無と、の少なくとも1つを含む。検査部36は、例えば、基板保持部361と、検査ヘッド362と、を有する。
Next, an example of the inspection unit 36 will be described with reference to FIG. The inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. The inspection items include at least one of presence/absence of foreign matter such as air bubbles and presence/absence of misalignment. The inspection unit 36 has, for example, a substrate holding unit 361 and an inspection head 362 .
基板保持部361は、チップ付き基板CW1を保持する。基板保持部361は、水平方向(X軸方向及びY軸方向の両方向)の移動が可能である。基板保持部361は、鉛直軸を中心とする回転が可能であってもよい。基板保持部361の移動または回転によって、検査位置を変更できる。基板保持部361は、鉛直方向の移動が可能であってもよい。
The substrate holding part 361 holds the chip-equipped substrate CW1. The substrate holder 361 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holder 361 may be rotatable around the vertical axis. The inspection position can be changed by moving or rotating the substrate holder 361 . The substrate holder 361 may be vertically movable.
検査ヘッド362は、例えばCTスキャナ、赤外線スキャナ、共焦点レーザースキャナ、または超音波スキャナなどを有し、チップCP1と基板W1の界面の画像を取得し、気泡の有無を検出する。あるいは、検査ヘッド362は、レーザー変位計などの高さ計測器を有し、チップCP1の高さを検出することで、気泡の有無を検出してもよい。気泡が有れば、気泡の厚みの分、チップCP1の高さが高くなる。
The inspection head 362 has, for example, a CT scanner, an infrared scanner, a confocal laser scanner, an ultrasonic scanner, or the like, acquires an image of the interface between the chip CP1 and the substrate W1, and detects the presence or absence of air bubbles. Alternatively, the inspection head 362 may have a height measuring device such as a laser displacement gauge and detect the presence or absence of air bubbles by detecting the height of the chip CP1. If there is a bubble, the height of the chip CP1 increases by the thickness of the bubble.
検査部36は、検査ヘッド362によって取得した情報を基に、基板W1の主面W1cの異なる貼合領域に貼合された複数のチップCP1のそれぞれの貼合状態が良好か不良かを判断する図示しない判断部を有してもよい。判断部は、コンピュータで構成される。判断部は、制御部9の一部であってもよい。
Based on the information acquired by the inspection head 362, the inspection unit 36 determines whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. It may have a determination unit (not shown). The determination unit is composed of a computer. The determination unit may be part of the control unit 9 .
次に、図10を参照して、チップ剥離部37の一例について説明する。チップ剥離部37は、検査部36による検査で貼合状態が不良であったチップCP1を、基板W1から剥離する。チップ剥離部37は、例えば、基板保持部371と、剥離ヘッド372と、回収ボックス373と、を有する。
Next, an example of the chip peeling portion 37 will be described with reference to FIG. The chip peeling unit 37 peels off the chip CP1, which was found to be poorly bonded in the inspection by the inspection unit 36, from the substrate W1. The chip peeling section 37 has, for example, a substrate holding section 371 , a peeling head 372 , and a recovery box 373 .
基板保持部371は、チップ付き基板CW1を保持する。基板保持部371は、水平方向(X軸方向及びY軸方向の両方向)の移動が可能である。基板保持部371は、鉛直軸を中心とする回転が可能であってもよい。基板保持部371の移動または回転によって、剥離位置を変更できる。基板保持部371は、鉛直方向の移動が可能であってもよい。
The substrate holding part 371 holds the chip-equipped substrate CW1. The substrate holding part 371 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holder 371 may be rotatable around the vertical axis. The peeling position can be changed by moving or rotating the substrate holder 371 . The substrate holder 371 may be vertically movable.
剥離ヘッド372は、例えば吸着ヘッド372aを含む。吸着ヘッド372aは、チップCP1を上方から吸着し、その状態で上方に移動することで、チップCP1を基板W1から剥離する。第1吸着ヘッド531は、鉛直方向だけではなく、水平方向の移動が可能であってよい。吸着ヘッド372aは、基板W1から剥離したチップCP1を回収ボックス373に投下する。
The stripping head 372 includes, for example, a suction head 372a. The suction head 372a sucks the chip CP1 from above and moves upward in this state to separate the chip CP1 from the substrate W1. The first suction head 531 may be movable not only in the vertical direction but also in the horizontal direction. The suction head 372 a drops the chips CP<b>1 separated from the substrate W<b>1 into the recovery box 373 .
次に、図11と図12を参照して、チップ剥離部37の変形例について説明する。図11(A)に示すように、剥離ヘッド372は、吸着ヘッド372aに加えて、ブレード372bを含んでもよい。ブレード372bは、チップCP1と基板W1の界面に挿入されることで、チップCP1を基板W1から剥離する。
Next, with reference to FIGS. 11 and 12, a modified example of the chip peeling portion 37 will be described. As shown in FIG. 11A, the separation head 372 may include a blade 372b in addition to the suction head 372a. The blade 372b separates the chip CP1 from the substrate W1 by being inserted into the interface between the chip CP1 and the substrate W1.
図11(B)に示すように、剥離ヘッド372は、吸着ヘッド372aに加えて、加熱器372cと冷却器372dを含んでもよい。加熱器372cと冷却器372dは、吸着ヘッド372aの内部に設けられ、チップCP1に温度勾配を形成し、熱応力によってチップCP1を基板W1から剥離する。
As shown in FIG. 11(B), the separation head 372 may include a heater 372c and a cooler 372d in addition to the suction head 372a. The heater 372c and the cooler 372d are provided inside the suction head 372a, form a temperature gradient in the chip CP1, and separate the chip CP1 from the substrate W1 by thermal stress.
冷却器372dは、加熱器372cを囲むように配置される。これにより、加熱器372cの熱が横に漏れるのを抑制でき、剥離対象ではないチップCP1が加熱されるのを抑制できる。なお、冷却器372dと加熱器372cの配置が逆であっても、熱応力によってチップCP1を基板W1から剥離することは可能である。なお、冷却器372dは、吸着ヘッド372aの内部に設けられる代わりに、基板保持部371(図10参照)に設けられてもよい。
The cooler 372d is arranged to surround the heater 372c. This can suppress lateral leakage of heat from the heater 372c, and can suppress heating of the chip CP1, which is not to be peeled off. Note that even if the arrangement of the cooler 372d and the heater 372c is reversed, it is possible to separate the chip CP1 from the substrate W1 by thermal stress. Note that the cooler 372d may be provided in the substrate holder 371 (see FIG. 10) instead of being provided inside the suction head 372a.
図12(A)に示すように、剥離ヘッド372は、吸着ヘッド372aに加えて、チューブ状のシール372eとノズル372fとを含んでもよい。シール372eは、剥離対象であるチップCP1の周囲に、チップCP1と基板W1の接合強度を低下させる剥離液を溜める。ノズル372fは、シール372eの内部に剥離液を吐出する。
As shown in FIG. 12(A), the stripping head 372 may include a tubular seal 372e and a nozzle 372f in addition to the suction head 372a. The seal 372e collects a peeling liquid that reduces the bonding strength between the chip CP1 and the substrate W1 around the chip CP1 to be peeled. The nozzle 372f discharges the stripping liquid inside the seal 372e.
剥離液は、剥離対象であるチップCP1と基板W1の界面に浸入し、チップCP1と基板W1の接合強度を低下させる。剥離液は、例えば、DIWなどの純水を含む。純水は、加水分解によってチップCP1と基板W1の接合強度を低下させる。剥離液は、純水と、純水以外の成分とを含んでもよい。
The stripper penetrates into the interface between the chip CP1 and the substrate W1 to be stripped, and reduces the bonding strength between the chip CP1 and the substrate W1. The stripping liquid contains, for example, pure water such as DIW. Pure water reduces the bonding strength between the chip CP1 and the substrate W1 by hydrolysis. The stripping solution may contain pure water and components other than pure water.
シール372eは、基板W1の主面W1cに押し付けられる。シール372eの材質は、例えば樹脂またはゴムである。シール372eの内周面は、下方に向けて先細り状のテーパー面であってもよい。テーパー面によって剥離液を内側に導くことができる。
The seal 372e is pressed against the main surface W1c of the substrate W1. The material of the seal 372e is, for example, resin or rubber. The inner peripheral surface of the seal 372e may be a tapered surface that tapers downward. The stripping liquid can be guided inward by the tapered surface.
ノズル372fは、シール372eを基板W1から離す前に、シール372eの内部に溜めた剥離液を吸い上げてもよい。剥離液を吐出するノズル372fと、剥離液を吸い上げるノズル372fとは、別々に設けられてもよい。
The nozzle 372f may suck up the stripping liquid accumulated inside the seal 372e before separating the seal 372e from the substrate W1. The nozzle 372f for discharging the stripping liquid and the nozzle 372f for sucking the stripping liquid may be provided separately.
図12(B)に示すように、チップ剥離部37は、基板保持部371の内部に複数の突き上げピン374を有してもよい。複数の突き上げピン374は、個別に昇降させられる。基板保持部371がチップ付き基板CW1を吸着した状態で、突き上げピン374が基板W1を局所的に付き上げることで、基板W1が局所的に曲げ変形させられ、チップCP1が基板W1から剥離する。
As shown in FIG. 12(B), the chip peeling section 37 may have a plurality of push-up pins 374 inside the substrate holding section 371 . The plurality of push-up pins 374 are raised and lowered individually. With the substrate holding part 371 sucking the substrate CW1 with chips, the push-up pins 374 locally push up the substrate W1, so that the substrate W1 is locally bent and deformed, and the chips CP1 are separated from the substrate W1.
次に、図13を参照して、リワーク部38の一例について説明する。リワーク部38は、基板W1の主面W1cのうち、チップ剥離部37によってチップCP1を剥離した貼合領域を選択的に処理する。リワーク部38は、例えば、基板保持部381と、処理ヘッド382と、を有する。
Next, an example of the rework section 38 will be described with reference to FIG. The rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off by the chip peeling unit 37 on the main surface W1c of the substrate W1. The rework section 38 has, for example, a substrate holding section 381 and a processing head 382 .
基板保持部381は、チップ付き基板CW1を保持する。基板保持部381は、水平方向(X軸方向及びY軸方向の両方向)の移動が可能である。基板保持部381は、鉛直軸を中心とする回転が可能であってもよい。基板保持部381の移動または回転によって、処理位置を変更できる。基板保持部381は、鉛直方向の移動が可能であってもよい。
The substrate holding part 381 holds the chip-equipped substrate CW1. The substrate holder 381 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holder 381 may be rotatable around the vertical axis. The processing position can be changed by moving or rotating the substrate holder 381 . The substrate holder 381 may be vertically movable.
処理ヘッド382は、例えばプラズマヘッドを有し、プラズマヘッドからチップCP1を剥離した貼合領域に選択的にプラズマを供給する。処理ヘッド382は、プラズマの供給領域を絞るべく、プラズマヘッドを囲むカバーを有してもよく、さらにカバーの内部を減圧してもよい。
The processing head 382 has, for example, a plasma head, and selectively supplies plasma to the bonding area where the chip CP1 is separated from the plasma head. The processing head 382 may have a cover surrounding the plasma head in order to narrow the plasma supply area, and the pressure inside the cover may be reduced.
処理ヘッド382は、洗浄ヘッドを有してもよく、洗浄ヘッドからチップCP1を剥離した貼合領域に選択的に水を供給する。洗浄ヘッドは、水を液体と気体のどちらの状態で供給してもよいが、好ましくは気体の状態で供給する。処理ヘッド382は、水の供給領域を絞るべく、洗浄ヘッドを囲むカバーを有してもよく、さらにカバーの内部を減圧してもよい。
The processing head 382 may have a cleaning head, and selectively supplies water to the bonding region where the chip CP1 is separated from the cleaning head. The cleaning head may supply water in either liquid or gaseous form, preferably in gaseous form. The treatment head 382 may have a cover surrounding the cleaning head to restrict the water supply area and may also have a vacuum inside the cover.
処理ヘッド382は、水平方向(X軸方向及びY軸方向の両方向)の移動が可能であってもよい。処理ヘッド382の移動によって、処理位置を変更できる。処理ヘッド382は、鉛直方向の移動が可能であってもよい。
The processing head 382 may be movable in the horizontal direction (both the X-axis direction and the Y-axis direction). By moving the processing head 382, the processing position can be changed. The processing head 382 may be vertically movable.
次に、図14を参照して、第1変形例に係る基板処理装置1について、上記実施形態との相違点を主に説明する。基板処理装置1は、第1処理ステーション3の代わりに、第2処理ステーション5が検査部36を備える。基板W1とチップCP1の貼合(ステップS104)と、貼合状態の検査(ステップS105)とを同時に実施することも可能である。第2処理ステーション5は、第1処理ステーション3の代わりに、検査部36に加えて、チップ剥離部37も備えてもよい。
Next, with reference to FIG. 14, the substrate processing apparatus 1 according to the first modified example will be described mainly about the differences from the above-described embodiment. In the substrate processing apparatus 1 , the second processing station 5 has an inspection section 36 instead of the first processing station 3 . It is also possible to simultaneously perform the bonding of the substrate W1 and the chip CP1 (step S104) and the inspection of the bonding state (step S105). The second processing station 5 may also include a chip peeling section 37 in addition to the inspection section 36 instead of the first processing station 3 .
次に、図15と図16を参照して、第2変形例に係る基板処理装置1について、上記実施形態及び上記第1変形例との相違点を主に説明する。基板処理装置1は、図16(A)~図16(D)に示すように、基板W1の主面W1cの貼合領域とは異なる第2貼合領域に、チップCP1とは異なる第2チップCP2を貼合することで、チップ付き基板CW1を製造する。チップ付き基板CW1は、基板W1と、基板W1に貼合された複数のチップCP1と、基板W1に貼合された複数の第2チップCP2を含む。
Next, with reference to FIGS. 15 and 16, the substrate processing apparatus 1 according to the second modified example will be described mainly with respect to differences from the above embodiment and the first modified example. As shown in FIGS. 16A to 16D, the substrate processing apparatus 1 attaches a second chip different from the chip CP1 to a second bonding region different from the bonding region of the main surface W1c of the substrate W1. A substrate CW1 with a chip is manufactured by laminating CP2. The substrate with chips CW1 includes a substrate W1, a plurality of chips CP1 bonded to the substrate W1, and a plurality of second chips CP2 bonded to the substrate W1.
基板処理装置1には、図16(B)に示す複数の第2チップCP2が搬入される。複数の第2チップCP2は第2テープTP2に接着されており、第2テープTP2の外周が第2フレームFR2に装着されている。第2フレームFR2の開口部に、複数の第2チップCP2が配列されている。複数の第2チップCP2は、例えば基板を第2テープTP2に接着した状態で基板をダイシングすることで得られる。
A plurality of second chips CP2 shown in FIG. 16(B) are loaded into the substrate processing apparatus 1 . A plurality of second chips CP2 are adhered to a second tape TP2, and the outer periphery of the second tape TP2 is attached to the second frame FR2. A plurality of second chips CP2 are arranged in the opening of the second frame FR2. The plurality of second chips CP2 can be obtained, for example, by dicing the substrate while the substrate is adhered to the second tape TP2.
第2チップCP2は、下地基板CP2aと、下地基板CP2aの上に形成されたデバイスCP2bと、を有する。下地基板CP2aは、例えば、シリコンウェハ、化合物半導体ウェハ、又はガラス基板である。デバイスCP2bは、半導体素子、回路、又は端子などを含む。デバイスCP2bは、下地基板CP2aを基準として、第2テープTP2とは反対側に配置される。
The second chip CP2 has a base substrate CP2a and a device CP2b formed on the base substrate CP2a. The underlying substrate CP2a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The device CP2b includes semiconductor elements, circuits, terminals, or the like. The device CP2b is arranged on the side opposite to the second tape TP2 with respect to the base substrate CP2a.
図16(C)に示すように、ピックアップ部53は、複数の第2チップCP2を個別に第2テープTP2から剥離する。その後、第2チップCP2は、上下反転された上で、図16(D)に示すように、基板W1に貼合される。基板W1のデバイスW1bと、チップCP1のデバイスCP1bと、第2チップCP2のデバイスCP2bとが電気的に接続される。これにより、チップ付き基板CW1が得られる。
As shown in FIG. 16(C), the pickup unit 53 separates the plurality of second chips CP2 individually from the second tape TP2. After that, the second chip CP2 is turned upside down and then bonded to the substrate W1 as shown in FIG. 16(D). The device W1b of the substrate W1, the device CP1b of the chip CP1, and the device CP2b of the second chip CP2 are electrically connected. Thus, a chip-equipped substrate CW1 is obtained.
図15に示すように、インターフェースブロック4は、第3バッファ部45を備えてもよい。第3バッファ部45は、第1処理ステーション3の搬送領域30に隣接している。第1バッファ部41と第2バッファ部42と第3バッファ部45は、インターフェースブロック4のフットプリントを小さくすべく、鉛直方向に積層されてもよい。
As shown in FIG. 15, the interface block 4 may include a third buffer section 45. The third buffer section 45 is adjacent to the transport area 30 of the first processing station 3 . The first buffer section 41 , the second buffer section 42 and the third buffer section 45 may be vertically stacked to reduce the footprint of the interface block 4 .
第3バッファ部45は、第2フレームFR2と共に複数の第2チップCP2を保管する。第3バッファ部45は、前処理(例えば洗浄)を実施済みの複数の第2チップCP2を保管する。これにより、第2処理ステーション5の稼働率を向上でき、チップ付き基板CW1の生産効率を向上できる。
The third buffer unit 45 stores a plurality of second chips CP2 together with the second frame FR2. The third buffer unit 45 stores a plurality of second chips CP2 that have undergone pretreatment (for example, cleaning). As a result, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrates CW1 with chips can be improved.
なお、第2チップCP2の搬送と洗浄は、チップCP1の搬送と洗浄と同様に行われるので、説明を省略する。第2チップCP2の搬送と洗浄に用いられる装置と、チップCP1の搬送と洗浄に用いられる装置とは、共通の装置であってもよいし、別々に設けた装置であってもよい。
The transportation and cleaning of the second chip CP2 are performed in the same manner as the transportation and cleaning of the chip CP1, so description thereof will be omitted. The device used for transporting and cleaning the second chip CP2 and the device used for transporting and cleaning the chip CP1 may be a common device or may be separate devices.
また、第2チップCP2のピックアップと実装は、チップCP1のピックアップと実装と同様に行われるので、説明を省略する。第2チップCP2のピックアップと実装に用いられる装置と、チップCP1のピックアップと実装に用いられる装置とは、共通の装置であってもよいし、別々に設けた装置であってもよい。
Also, since the pickup and mounting of the second chip CP2 are performed in the same manner as the pickup and mounting of the chip CP1, the description thereof will be omitted. The device used to pick up and mount the second chip CP2 and the device used to pick up and mount the chip CP1 may be a common device or may be separate devices.
次に、図18~図22を参照して、第3変形例に係る基板処理装置1について、上記実施形態、上記第1変形例および上記第2変形例との相違点を主に説明する。基板処理装置1は、図19(A)~図19(C)に示すように、保護膜PF1によって保護されているチップCP1をテープTP1から剥離し、その後、チップCP1を基板W1に実装する。その途中で、基板処理装置1は、保護膜PF1をチップCP1から除去する。
Next, with reference to FIGS. 18 to 22, the substrate processing apparatus 1 according to the third modified example will be described mainly with respect to differences from the above embodiment, the first modified example, and the second modified example. As shown in FIGS. 19A to 19C, the substrate processing apparatus 1 peels off the chip CP1 protected by the protective film PF1 from the tape TP1, and then mounts the chip CP1 on the substrate W1. On the way, the substrate processing apparatus 1 removes the protective film PF1 from the chip CP1.
図20に示すように、第2処理ステーション5は、基板保持部51と、チップ保持部52と、ピックアップ部53と、マウント部54と、を備える。また、第2処理ステーション5は、除去部55(図18参照)も備える。以下、ピックアップ部53と、マウント部54と、除去部55について、この順番で説明する。
As shown in FIG. 20, the second processing station 5 includes a substrate holding section 51, a chip holding section 52, a pickup section 53, and a mounting section . The second processing station 5 also comprises a remover 55 (see FIG. 18). Hereinafter, the pickup section 53, the mounting section 54, and the removing section 55 will be described in this order.
ピックアップ部53は、複数のチップCP1がテープTP1を介してフレームFR1に装着され且つチップCP1のテープTP1とは反対側の第1主面CP1cに保護膜PF1が形成された状態で、チップCP1をテープTP1から剥離する。保護膜PF1は、チップCP1の第1主面CP1cを覆う。
The pickup unit 53 picks up the chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1 and the protective film PF1 is formed on the first main surface CP1c of the chips CP1 opposite to the tape TP1. Peel off from tape TP1. The protective film PF1 covers the first main surface CP1c of the chip CP1.
ピックアップ部53は、第1吸着ヘッド531を有する。第1吸着ヘッド531は、保護膜PF1を介してチップCP1を吸着する。保護膜PF1は、第1吸着ヘッド531とチップCP1のデバイスCP1bとの接触を防止することで、デバイスCP1bの損傷を抑制する。
The pickup section 53 has a first suction head 531 . The first suction head 531 suctions the chip CP1 via the protective film PF1. The protective film PF1 suppresses damage to the device CP1b by preventing contact between the first suction head 531 and the device CP1b of the chip CP1.
第1吸着ヘッド531は、チップCP1を吸着した状態で上方に移動することで、チップCP1をテープTP1から剥離する。このとき、保護膜PF1が引きちぎられ、分割される。なお、保護膜PF1は、レーザー加工またはブレード加工などによって、予め分割されていてもよい。
The first suction head 531 separates the chip CP1 from the tape TP1 by moving upward while sucking the chip CP1. At this time, the protective film PF1 is torn off and divided. Note that the protective film PF1 may be divided in advance by laser processing, blade processing, or the like.
第1吸着ヘッド531は、上下反転可能であってもよい。チップCP1を上下反転でき、チップCP1の第1主面CP1cを基板W1に向けることができる。なお、既述の通り、図示しない搬送部がピックアップ部53からマウント部54にチップCP1を搬送してもよく、その途中で搬送部がチップCP1を上下反転してもよい。
The first suction head 531 may be capable of being turned upside down. The chip CP1 can be turned upside down, and the first main surface CP1c of the chip CP1 can face the substrate W1. Note that, as described above, a transporting unit (not shown) may transport the chip CP1 from the pickup unit 53 to the mounting unit 54, and the transporting unit may turn the chip CP1 upside down on the way.
マウント部54は、チップCP1の第1主面CP1cを基板W1に向けて、チップCP1を基板W1の主面W1cに実装する。マウント部54は、第2吸着ヘッド541を有する。第2吸着ヘッド541は、チップCP1の第2主面CP1dを吸着する。第2主面CP1dは、第1主面CP1cとは反対向きの面であって、テープTP1から剥離された面である。
The mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1. The mount section 54 has a second suction head 541 . The second suction head 541 suctions the second main surface CP1d of the chip CP1. The second main surface CP1d is a surface opposite to the first main surface CP1c and is a surface separated from the tape TP1.
第2吸着ヘッド541は、チップCP1を上方から吸着し、その状態で下方に移動することで、チップCP1を基板W1の主面W1cに実装する。チップCP1と基板W1が接触するように、予め保護膜PF1が除去される。チップCP1のデバイスCP1bと、基板W1のデバイスW1bとが、電気的に接続される。
The second suction head 541 picks up the chip CP1 from above and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1. The protective film PF1 is removed in advance so that the chip CP1 and the substrate W1 are in contact with each other. The device CP1b of the chip CP1 and the device W1b of the substrate W1 are electrically connected.
本変形例によれば、保護膜PF1がチップCP1の第1主面CP1cを被覆した状態で、ピックアップ部53がチップCP1をテープTP1から剥離する。よって、ピックアップ部53とチップCP1との接触を防止でき、チップCP1の損傷を抑制できる。チップCP1の第1主面CP1cがデバイスCP1bを有する場合に、特に有効である。
According to this modification, the pickup unit 53 peels off the chip CP1 from the tape TP1 while the protective film PF1 covers the first main surface CP1c of the chip CP1. Therefore, contact between the pickup portion 53 and the chip CP1 can be prevented, and damage to the chip CP1 can be suppressed. This is particularly effective when the first main surface CP1c of the chip CP1 has the device CP1b.
その後、保護膜PF1を除去したうえで、チップCP1の第1主面CP1cを基板W1に向けてチップCP1を基板W1に貼合する。予め保護膜PF1を除去することで、チップCP1を基板W1に接触でき、チップCP1のデバイスCP1bと、基板W1のデバイスW1bとを電気的に接続できる。
After that, after removing the protective film PF1, the chip CP1 is bonded to the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1. By removing the protective film PF1 in advance, the chip CP1 can be brought into contact with the substrate W1, and the device CP1b of the chip CP1 and the device W1b of the substrate W1 can be electrically connected.
次に、図21を参照して、除去部55の一例について説明する。図21(A)に示すように、保護膜PF1は、チップCP1の第1主面CP1cだけではなく、チップCP1の側面CP1eも被覆していてもよい。保護膜PF1は、詳しくは後述するが、予めダイシングによって分割された複数のチップCP1の上に保護膜PF1の液状材料を塗布して固化することで形成され、隣り合うチップCP1同士の隙間にも形成される。
Next, an example of the removal unit 55 will be described with reference to FIG. As shown in FIG. 21A, the protective film PF1 may cover not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1. Although the details will be described later, the protective film PF1 is formed by coating and solidifying a liquid material for the protective film PF1 on a plurality of chips CP1 divided in advance by dicing, and is also formed in the gaps between the adjacent chips CP1. It is formed.
図21(B)に示すように、除去部55は、第1供給部551を有してもよい。第1供給部551は、保護膜PF1に対して、保護膜PF1をチップCP1から剥離させる剥離液L1を供給する。剥離液L1は、例えば保護膜PF1を溶解することなく、保護膜PF1をチップCP1から剥離させる。保護膜PF1は、膜の形態のまま、チップCP1から剥離させられる。
As shown in FIG. 21(B), the removal section 55 may have a first supply section 551 . The first supply unit 551 supplies the stripping liquid L1 for stripping the protective film PF1 from the chip CP1 to the protective film PF1. The peeling liquid L1 peels the protective film PF1 from the chip CP1, for example, without dissolving the protective film PF1. The protective film PF1 is peeled off from the chip CP1 in the form of a film.
例えば、第1供給部551は剥離液L1を溜める貯留槽を有し、保護膜PF1はチップCP1と共に、貯留槽に溜めた剥離液L1に浸漬される。このとき、保護膜PF1が剥離液L1に浸漬されやすいように、例えばマウント部54の第2吸着ヘッド541がチップCP1の第1主面CP1cを下に向けてチップCP1を保持する。なお、チップCP1を保持する吸着ヘッドは、マウント部54の第2吸着ヘッド541には限定されない。
For example, the first supply unit 551 has a storage tank for storing the stripping liquid L1, and the protective film PF1 is immersed in the stripping liquid L1 stored in the storage tank together with the chip CP1. At this time, for example, the second suction head 541 of the mount section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the stripping liquid L1. Note that the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mount section 54 .
図21(C)に示すように、剥離液L1が保護膜PF1の内部に浸透し、保護膜PF1とチップCP1の界面に到達することで、保護膜PF1がチップCP1から剥離される。これにより、保護膜PF1を形成する前からチップCP1に付着していたパーティクルPCが、保護膜PF1と共にチップCP1から剥離される。
As shown in FIG. 21(C), the peeling liquid L1 permeates into the protective film PF1 and reaches the interface between the protective film PF1 and the chip CP1, thereby peeling the protective film PF1 from the chip CP1. As a result, the particles PC attached to the chip CP1 before the protective film PF1 is formed are separated from the chip CP1 together with the protective film PF1.
保護膜PF1は、パーティクルPCの除去効率を向上すべく、チップCP1の第1主面CP1cだけではなく、チップCP1の側面CP1eをも被覆していることが好ましい。チップCP1の側面CP1eに付着していたパーティクルPCも、チップCP1から剥離できる。
The protective film PF1 preferably covers not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1 in order to improve the removal efficiency of the particles PC. Particles PC adhering to side surface CP1e of chip CP1 can also be peeled off from chip CP1.
剥離液L1は、保護膜PF1の材質に応じて適宜選択されるが、例えばDIWなどの純水である。保護膜PF1は、例えば有機膜である。純水は、有機膜の内部に浸透することができる。有機膜の材質は、特に限定されないが、例えばアクリル樹脂またはエポキシ樹脂であり、好ましくはアクリル樹脂である。純水は、保護膜PF1とチップCP1の剥離性を向上すべく、加熱されてもよい。
The stripping liquid L1 is appropriately selected according to the material of the protective film PF1, and is, for example, pure water such as DIW. The protective film PF1 is, for example, an organic film. Pure water can permeate the interior of the organic film. Although the material of the organic film is not particularly limited, it is, for example, an acrylic resin or an epoxy resin, preferably an acrylic resin. The pure water may be heated to improve the peelability between the protective film PF1 and the chip CP1.
図21(D)に示すように、除去部55は、第2供給部552を有してもよい。第2供給部552は、保護膜PF1に対して、第1供給部551によって剥離液L1を供給した後、保護膜PF1を溶解させる溶解液L2を供給する。
As shown in FIG. 21(D), the removal section 55 may have a second supply section 552 . The second supply unit 552 supplies the stripping liquid L1 to the protective film PF1 by the first supply unit 551, and then supplies the dissolving liquid L2 for dissolving the protective film PF1.
例えば、第2供給部552は溶解液L2を溜める貯留槽を有し、保護膜PF1はチップCP1と共に、貯留槽に溜めた溶解液L2に浸漬される。このとき、保護膜PF1が溶解液L2に浸漬されやすいように、例えばマウント部54の第2吸着ヘッド541がチップCP1の第1主面CP1cを下に向けてチップCP1を保持する。なお、チップCP1を保持する吸着ヘッドは、マウント部54の第2吸着ヘッド541には限定されない。
For example, the second supply unit 552 has a reservoir for storing the solution L2, and the protective film PF1 is immersed in the solution L2 stored in the reservoir together with the chip CP1. At this time, for example, the second suction head 541 of the mount section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the solution L2. Note that the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mount section 54 .
溶解液L2としては、例えばアルカリ現像液が用いられる。アルカリ現像液を用いた場合、チップCP1とパーティクルPCに同一極性のゼータ電位を生じさせることでき、パーティクルPCがチップCP1に再付着するのを抑制できる。なお、溶解液L2としてアルカリ現像液が用いられる場合に、剥離液L1として溶解液L2よりも低い濃度のアルカリ現像液が用いられてもよい。
For example, an alkaline developer is used as the dissolving liquid L2. When an alkaline developer is used, the zeta potential of the same polarity can be generated in the chips CP1 and the particles PC, and the reattachment of the particles PC to the chips CP1 can be suppressed. Note that when an alkaline developer is used as the dissolving liquid L2, an alkaline developing liquid having a concentration lower than that of the dissolving liquid L2 may be used as the stripping liquid L1.
なお、溶解液L2を溜める貯留槽と、剥離液L1を溜める貯留槽とは、共通であってもよい。また、除去部55は、第1供給部551と第2供給部552の両方を有するが、第1供給部551のみ有してもよいし、第2供給部552のみ有してもよい。除去部55は、チップCP1を乾燥させる乾燥部を有してもよい。除去部55が剥離液L1または溶解液L2などの液体を使用しない場合、乾燥部は不要である。
The storage tank for storing the dissolving liquid L2 and the storage tank for storing the stripping liquid L1 may be common. Moreover, although the removal unit 55 has both the first supply unit 551 and the second supply unit 552 , it may have only the first supply unit 551 or only the second supply unit 552 . The removal unit 55 may have a drying unit that dries the chip CP1. If the removing unit 55 does not use liquid such as the stripping liquid L1 or the dissolving liquid L2, the drying unit is unnecessary.
次に、図18と図22を参照して、塗布部70の一例について説明する。塗布部70は、図18に示すように第1処理ステーション3に備えられる。塗布部70は、搬送領域30に隣接している。複数のチップCP1は、チップ洗浄部33で洗浄された後、塗布部70で処理され、その後、第1フレーム搬送アーム32によってチップ貼合部6に搬送される。なお、本変形例では塗布部70とチップ洗浄部33とが別々に設けられるが、塗布部70がチップ洗浄部33の機能を有してもよい。
Next, an example of the application unit 70 will be described with reference to FIGS. 18 and 22. FIG. The coating section 70 is provided in the first processing station 3 as shown in FIG. The coating section 70 is adjacent to the transport area 30 . The plurality of chips CP<b>1 are cleaned by the chip cleaning section 33 , processed by the coating section 70 , and then transported to the chip bonding section 6 by the first frame transport arm 32 . Although the application unit 70 and the tip cleaning unit 33 are provided separately in this modification, the application unit 70 may have the function of the tip cleaning unit 33 .
図22に示すように、塗布部70は、例えば、チップ保持部701と、フレーム保持部702と、を有する。チップ保持部701は、テープTP1を介して複数のチップCP1を下方から水平に保持する。チップ保持部701はテープTP1を摺動自在に載せる。なお、チップ保持部701は、真空チャック機構を有し、テープTP1を固定してもよい。
As shown in FIG. 22, the application section 70 has, for example, a tip holding section 701 and a frame holding section 702. The chip holding unit 701 horizontally holds the plurality of chips CP1 from below via the tape TP1. The chip holding portion 701 slidably mounts the tape TP1. Note that the tip holding unit 701 may have a vacuum chuck mechanism to fix the tape TP1.
フレーム保持部702は、フレームFR1を下方から水平に保持する。フレーム保持部702は、真空チャック機構またはメカニカルチャック機構を有し、フレームFR1を固定する。後述する回転駆動部704がフレーム保持部702を回転駆動させることで、フレームFR1と共に複数のチップCP1が回転する。
The frame holding portion 702 horizontally holds the frame FR1 from below. The frame holder 702 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1. A rotation drive unit 704, which will be described later, rotates the frame holding unit 702, thereby rotating the plurality of chips CP1 together with the frame FR1.
塗布部70は、回転駆動部704と、ノズル705と、カップ706と、を有する。回転駆動部704は、フレーム保持部702を回転駆動させることで、フレームFR1と共に複数のチップCP1を回転させる。回転駆動部704は、フレーム保持部702と共にチップ保持部701も回転駆動させる。ノズル705は、複数のチップCP1に対して保護膜PF1の液状材料L3を供給する。カップ706は、液状材料L3を回収する。
The application unit 70 has a rotary drive unit 704 , a nozzle 705 and a cup 706 . The rotation driving unit 704 rotates the frame holding unit 702 to rotate the plurality of chips CP1 together with the frame FR1. The rotation driving section 704 rotates the tip holding section 701 as well as the frame holding section 702 . The nozzle 705 supplies the liquid material L3 of the protective film PF1 to the plurality of chips CP1. Cup 706 collects liquid material L3.
塗布部70は、予めダイシングによって分割された複数のチップCP1の上に保護膜PF1の液状材料を塗布して固化することで、保護膜PF1を形成する。隣り合うチップCP1同士の隙間にも保護膜PF1を形成でき、チップCP1の側面CP1eにも保護膜PF1を形成できる。なお、本明細書において、「固化」は、「硬化」を含む。「硬化」とは、分子同士が連結して高分子化すること(例えば架橋または重合など)を意味する。
The applicator 70 forms the protective film PF1 by applying and solidifying the liquid material of the protective film PF1 on the plurality of chips CP1 divided in advance by dicing. The protective film PF1 can also be formed in the gap between the adjacent chips CP1, and the protective film PF1 can also be formed on the side surface CP1e of the chip CP1. In addition, in this specification, "hardening" includes "hardening." “Curing” means that molecules are linked together to form a polymer (for example, cross-linking or polymerization).
塗布部70は、複数のチップCP1がテープTP1を介してフレームFR1に装着された状態で、チップCP1を基準としてテープTP1とは反対側から、保護膜PF1の液状材料L3をチップCP1に塗布して固化することで、保護膜PF1を形成する。複数のチップCP1がテープTP1に接着されているので、ハンドリング性が良い。
With the plurality of chips CP1 attached to the frame FR1 via the tape TP1, the coating unit 70 applies the liquid material L3 of the protective film PF1 to the chips CP1 from the opposite side of the tape TP1 with respect to the chips CP1. Then, the protective film PF1 is formed. Since the plurality of chips CP1 are adhered to the tape TP1, it is easy to handle.
液状材料L3は、複数のチップCP1の回転中心線付近に供給され、遠心力によって回転中心線から遠ざかる方向に放射状に広がり、液膜を形成する。液状材料L3の液膜を固化することで、保護膜PF1が形成される。液膜の形成後、液膜の固化前に、チップCP1の回転を停止してもよい。
The liquid material L3 is supplied near the rotation center line of the plurality of chips CP1, spreads radially in a direction away from the rotation center line due to centrifugal force, and forms a liquid film. The protective film PF1 is formed by solidifying the liquid film of the liquid material L3. After forming the liquid film, the rotation of the chip CP1 may be stopped before the liquid film is solidified.
液状材料L3は、例えば揮発成分を含み、揮発成分の揮発によって固化する。揮発成分の揮発に伴う体積収縮を利用して、パーティクルPCをチップCP1から剥離できる。液状材料L3は、アクリル樹脂を含んでもよい。アクリル樹脂の硬化収縮によっても、パーティクルPCをチップCP1から剥離できる。
The liquid material L3 contains, for example, a volatile component, and is solidified by volatilization of the volatile component. The particles PC can be peeled off from the chip CP1 by utilizing the volume shrinkage associated with volatilization of the volatile components. The liquid material L3 may contain acrylic resin. The particles PC can also be separated from the chip CP1 by curing shrinkage of the acrylic resin.
以上、本開示に係る基板処理装置、及び基板処理方法の実施形態等について説明したが、本開示は上記実施形態等に限定されない。特許請求の範囲に記載された範疇内において、各種の変更、修正、置換、付加、削除、及び組み合わせが可能である。それらについても当然に本開示の技術的範囲に属する。
Although the embodiments and the like of the substrate processing apparatus and the substrate processing method according to the present disclosure have been described above, the present disclosure is not limited to the above embodiments and the like. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These also naturally belong to the technical scope of the present disclosure.
本出願は、2022年1月27日に日本国特許庁に出願した特願2022-011239号に基づく優先権を主張するものであり、特願2022-011239号の全内容を本出願に援用する。
This application claims priority based on Japanese Patent Application No. 2022-011239 filed with the Japan Patent Office on January 27, 2022, and the entire contents of Japanese Patent Application No. 2022-011239 are incorporated into this application. .
1 基板処理装置
6 チップ貼合部
53 ピックアップ部
54 マウント部
55 除去部
CP1 チップ
CP1c 第1主面
FR1 フレーム
TP1 テープ
PF1 保護膜
W1 基板
W1c 主面 1Substrate Processing Apparatus 6 Chip Bonding Part 53 Pickup Part 54 Mounting Part 55 Removal Part CP1 Chip CP1c First Main Surface FR1 Frame TP1 Tape PF1 Protective Film W1 Substrate W1c Main Surface
6 チップ貼合部
53 ピックアップ部
54 マウント部
55 除去部
CP1 チップ
CP1c 第1主面
FR1 フレーム
TP1 テープ
PF1 保護膜
W1 基板
W1c 主面 1
Claims (17)
- 複数のチップがテープを介してフレームに装着され且つ前記チップの前記テープとは反対側の第1主面に保護膜が形成された状態で前記チップを前記テープから剥離するピックアップ部と、
前記ピックアップ部によって前記チップを前記テープから剥離した後、前記チップから前記保護膜を除去する除去部と、
前記除去部によって前記保護膜を除去した後、前記チップの前記第1主面を基板に向けて前記チップを前記基板に実装するマウント部と、
を備える、基板処理装置。 a pick-up unit that removes the chips from the tape in a state in which a plurality of chips are attached to a frame via a tape and a protective film is formed on a first main surface of the chips opposite to the tape;
a removal unit that removes the protective film from the chip after the chip is separated from the tape by the pickup unit;
a mounting unit that mounts the chip on the substrate with the first main surface of the chip facing the substrate after the protective film is removed by the removing unit;
A substrate processing apparatus comprising: - 前記ピックアップ部は前記保護膜を介して前記チップを吸着する第1吸着ヘッドを含み、前記マウント部は前記チップの前記テープから剥離された第2主面を吸着する第2吸着ヘッドを含む、請求項1に記載の基板処理装置。 wherein said pickup section includes a first suction head that suctions said chip via said protective film, and said mounting section includes a second suction head that suctions a second main surface of said chip separated from said tape. Item 1. The substrate processing apparatus according to item 1.
- 前記除去部は、前記保護膜に対して、前記保護膜を前記チップから剥離させる剥離液を供給する第1供給部を含む、請求項1または2に記載の基板処理装置。 3. The substrate processing apparatus according to claim 1, wherein said removal section includes a first supply section that supplies a stripping liquid for stripping said protective film from said chip to said protective film.
- 前記剥離液は純水である、請求項3に記載の基板処理装置。 The substrate processing apparatus according to claim 3, wherein the stripping liquid is pure water.
- 前記除去部は、前記保護膜に対して、前記第1供給部によって前記剥離液を供給した後、前記保護膜を溶解させる溶解液を供給する第2供給部を含む、請求項3に記載の基板処理装置。 4. The removing section according to claim 3, wherein the removal section includes a second supply section that supplies a dissolving liquid for dissolving the protective film after supplying the stripping liquid from the first supply section to the protective film. Substrate processing equipment.
- 予めダイシングによって分割された複数の前記チップの上に前記保護膜の液状材料を塗布して固化することで、前記保護膜を形成する塗布部を備える、請求項1または2に記載の基板処理装置。 3. The substrate processing apparatus according to claim 1, further comprising a coating unit that forms the protective film by coating and solidifying the liquid material for the protective film on the plurality of chips divided in advance by dicing. .
- 前記塗布部は、複数の前記チップが前記テープを介して前記フレームに装着された状態で、前記チップを基準として前記テープとは反対側から、前記保護膜の前記液状材料を前記チップに塗布して固化することで、前記保護膜を形成する、請求項6に記載の基板処理装置。 The application unit applies the liquid material of the protective film to the chips from the side opposite to the tape with respect to the chips in a state where the chips are attached to the frame via the tape. 7. The substrate processing apparatus according to claim 6, wherein said protective film is formed by solidifying said protective film.
- 前記ピックアップ部と前記除去部と前記マウント部とを有するチップ貼合部を備え、
前記塗布部と前記チップ貼合部に隣接する搬送領域と、前記搬送領域で前記フレームを保持して前記フレームと共に複数の前記チップを搬送する第1フレーム搬送アームと、を備え、
前記第1フレーム搬送アームは、前記フレームと共に複数の前記チップを前記塗布部から前記チップ貼合部に搬送する、請求項6に記載の基板処理装置。 a chip bonding section having the pickup section, the removing section, and the mounting section;
a transport area adjacent to the coating unit and the chip bonding unit; and a first frame transport arm that holds the frame in the transport area and transports the plurality of chips together with the frame,
7. The substrate processing apparatus according to claim 6, wherein said first frame transport arm transports said plurality of chips together with said frame from said coating section to said chip bonding section. - 前記チップ貼合部は、前記搬送領域に隣接するインターフェース部と、前記インターフェース部を基準として前記搬送領域とは反対側に配置される第2処理ステーションと、を備え、
前記第2処理ステーションは、前記基板を保持する基板保持部と、複数の前記チップが前記テープを介して前記フレームに装着された状態で複数の前記チップを保持するチップ保持部と、前記ピックアップ部と、前記除去部と、前記マウント部と、を備え、
前記インターフェース部は、前記基板を保管する第1バッファ部と、前記第1バッファ部から前記基板保持部に前記基板を搬送する第2基板搬送アームと、前記第1フレーム搬送アームによって前記フレームと共に搬送された複数の前記チップを保管する第2バッファ部と、前記第2バッファ部から前記チップ保持部に前記フレームと共に複数の前記チップを搬送する第2フレーム搬送アームと、を備える、請求項8に記載の基板処理装置。 The chip bonding section includes an interface section adjacent to the transfer area, and a second processing station disposed on the opposite side of the interface section to the transfer area,
The second processing station includes a substrate holding section that holds the substrate, a chip holding section that holds the plurality of chips while the plurality of chips are mounted on the frame via the tape, and the pickup section. , the removing section, and the mounting section,
The interface section includes a first buffer section that stores the substrate, a second substrate transfer arm that transfers the substrate from the first buffer section to the substrate holding section, and a first frame transfer arm that transfers the substrate together with the frame. and a second frame transport arm for transporting the plurality of chips together with the frame from the second buffer to the chip holding part. A substrate processing apparatus as described. - 前記第2処理ステーションは、前記基板の主面の異なる貼合領域に貼合された複数の前記チップのそれぞれの貼合状態が良好か不良かを検査する検査部と、前記検査部による検査で前記貼合状態が不良であった前記チップを前記基板から剥離するチップ剥離部と、を備える、請求項9に記載の基板処理装置。 The second processing station includes an inspection unit for inspecting whether the bonding state of each of the plurality of chips bonded to different bonding regions on the main surface of the substrate is good or bad, and an inspection by the inspection unit. 10. The substrate processing apparatus according to claim 9, further comprising a chip peeling unit for peeling said chip whose bonding state is defective from said substrate.
- 前記基板の主面の異なる貼合領域に貼合された複数の前記チップのそれぞれの貼合状態が良好か不良かを検査する検査部と、前記検査部による検査で前記貼合状態が不良であった前記チップを前記基板から剥離するチップ剥離部と、を備え、
前記検査部と前記チップ剥離部は、前記搬送領域に隣接する、請求項8に記載の基板処理装置。 an inspection unit that inspects whether the bonding state of each of the plurality of chips bonded to different bonding regions on the main surface of the substrate is good or bad; a chip peeling unit for peeling the chip from the substrate,
9. The substrate processing apparatus according to claim 8, wherein said inspection section and said chip peeling section are adjacent to said transfer area. - 複数のチップがテープを介してフレームに装着され且つ前記チップの前記テープとは反対側の第1主面に保護膜が形成された状態で前記チップを前記テープから剥離することと、
前記チップを前記テープから剥離した後、前記チップから前記保護膜を除去することと、
前記保護膜を除去した後、前記チップの前記第1主面を基板に向けて前記チップを前記基板に実装することと、
を有する、基板処理方法。 removing the chips from the tape in a state in which a plurality of chips are attached to a frame via tape and a protective film is formed on a first main surface of the chips opposite to the tape;
removing the protective film from the chip after peeling the chip from the tape;
After removing the protective film, mounting the chip on the substrate with the first main surface of the chip facing the substrate;
A substrate processing method comprising: - 前記保護膜を除去することは、前記保護膜に対して、前記保護膜を前記チップから剥離させる剥離液を供給することを含む、請求項12に記載の基板処理方法。 13. The substrate processing method according to claim 12, wherein removing the protective film includes supplying a peeling liquid for peeling the protective film from the chip to the protective film.
- 前記剥離液は純水である、請求項13に記載の基板処理方法。 The substrate processing method according to claim 13, wherein the stripping liquid is pure water.
- 前記保護膜を除去することは、前記保護膜に対して前記剥離液を供給した後、前記保護膜に対して前記保護膜を溶解させる溶解液を供給することを含む、請求項13または14に記載の基板処理方法。 15. The method according to claim 13 or 14, wherein removing the protective film includes supplying the stripping solution to the protective film and then supplying the protective film with a dissolving solution for dissolving the protective film. The substrate processing method described.
- 予めダイシングによって分割された複数の前記チップの上に前記保護膜の液状材料を塗布して固化することで、前記保護膜を形成することを含む、請求項12~14のいずれか1項に記載の基板処理方法。 15. The method according to any one of claims 12 to 14, comprising forming the protective film by coating and solidifying the liquid material of the protective film on the plurality of chips divided in advance by dicing. substrate processing method.
- 前記保護膜を形成することは、複数の前記チップが前記テープを介して前記フレームに装着された状態で、前記チップを基準として前記テープとは反対側から、前記保護膜の前記液状材料を前記チップに塗布して固化することで、前記保護膜を形成することを含む、請求項16に記載の基板処理方法。 Forming the protective film is performed by applying the liquid material of the protective film from the side opposite to the tape with respect to the chips in a state in which the plurality of chips are attached to the frame via the tape. 17. The substrate processing method according to claim 16, comprising forming the protective film by coating the chip and solidifying it.
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PCT/JP2023/001289 WO2023145558A1 (en) | 2022-01-27 | 2023-01-18 | Substrate-processing device and substrate-processing method |
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TW (1) | TW202335115A (en) |
WO (1) | WO2023145558A1 (en) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007299966A (en) * | 2006-05-01 | 2007-11-15 | Matsushita Electric Ind Co Ltd | Electronic component mounting apparatus |
WO2008146744A1 (en) * | 2007-05-25 | 2008-12-04 | Hamamatsu Photonics K.K. | Working method for cutting |
JP2014029921A (en) * | 2012-07-31 | 2014-02-13 | Sony Corp | Semiconductor device processing method and semiconductor substrate processed article |
WO2014141514A1 (en) * | 2013-03-12 | 2014-09-18 | 株式会社新川 | Flip chip bonder and flip chip bonding method |
JP2020031174A (en) * | 2018-08-24 | 2020-02-27 | パナソニックIpマネジメント株式会社 | Manufacturing method of element chip |
JP2021190557A (en) * | 2020-05-29 | 2021-12-13 | 株式会社ディスコ | Wafer processing method |
-
2023
- 2023-01-13 TW TW112101477A patent/TW202335115A/en unknown
- 2023-01-18 WO PCT/JP2023/001289 patent/WO2023145558A1/en unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007299966A (en) * | 2006-05-01 | 2007-11-15 | Matsushita Electric Ind Co Ltd | Electronic component mounting apparatus |
WO2008146744A1 (en) * | 2007-05-25 | 2008-12-04 | Hamamatsu Photonics K.K. | Working method for cutting |
JP2014029921A (en) * | 2012-07-31 | 2014-02-13 | Sony Corp | Semiconductor device processing method and semiconductor substrate processed article |
WO2014141514A1 (en) * | 2013-03-12 | 2014-09-18 | 株式会社新川 | Flip chip bonder and flip chip bonding method |
JP2020031174A (en) * | 2018-08-24 | 2020-02-27 | パナソニックIpマネジメント株式会社 | Manufacturing method of element chip |
JP2021190557A (en) * | 2020-05-29 | 2021-12-13 | 株式会社ディスコ | Wafer processing method |
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