WO2023142820A1 - 一种开关电容电路sc及电子设备 - Google Patents

一种开关电容电路sc及电子设备 Download PDF

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Publication number
WO2023142820A1
WO2023142820A1 PCT/CN2022/141582 CN2022141582W WO2023142820A1 WO 2023142820 A1 WO2023142820 A1 WO 2023142820A1 CN 2022141582 W CN2022141582 W CN 2022141582W WO 2023142820 A1 WO2023142820 A1 WO 2023142820A1
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WIPO (PCT)
Prior art keywords
switch
capacitor
terminal
switch circuit
state
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PCT/CN2022/141582
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English (en)
French (fr)
Inventor
阮新波
叶刚
姚凯
邵蕃光
侯庆慧
Original Assignee
华为技术有限公司
南京航空航天大学
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Publication of WO2023142820A1 publication Critical patent/WO2023142820A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

Definitions

  • the embodiments of the present application relate to the field of electronic technology, and in particular to a switched capacitor circuit SC and electronic equipment.
  • Terminal equipment such as mobile phones, watches, and tablet computers achieve wired or wireless fast charging through a power adapter or a wireless charging circuit that outputs a high voltage that is twice (or four times) the battery voltage, and then passes through a switched capacitor circuit in the terminal equipment ( switched capacitor converter, SC) reduces the high voltage to 1/2 (or 1/4) voltage to charge the battery.
  • SC switched capacitor converter
  • SC has the characteristics of open loop and high efficiency. Combined with the charging protocol to control the adapter or the wireless charging circuit to adjust the voltage or current, it can make the charging system of the entire terminal device efficient and reduce heat consumption, thereby achieving super fast charging.
  • the charging protocol controls the adapter or the wireless charging circuit to realize fast charging of the battery with a higher charging power (for example, 60W).
  • the charging protocol controls the adapter or the wireless charger to output a higher The voltage (such as 20V)
  • the SC works in the 4:1 step-down mode at this time, and converts the voltage of 20V to 5V to charge the battery.
  • the adapter or wireless charger needs to be controlled to switch to a lower charging power (for example, 40W), and the output voltage of the adapter or wireless charger to the SC will decrease.
  • the charging protocol will control the SC to reduce the input 10V voltage to around 5V in a 2:1 step-down mode to continue charging the battery; of course, the charging protocol
  • the SC When controlling the adapter or wireless charger to further reduce the voltage, it is necessary to control the SC to further switch the step-down mode to ensure that the output voltage is maintained at around 5V, so as to ensure the effect of fast charging. Therefore, it is necessary to provide an SC capable of freely switching between various step-down ratios.
  • Embodiments of the present application provide a switched capacitor circuit SC and an electronic device capable of freely switching between various step-down ratios.
  • a switched capacitor circuit SC including: a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, and a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; Wherein, the first end of the first switch circuit is connected to the power supply end; the second end of the first switch circuit is connected to the first end of the third capacitor, and the third end of the first switch circuit is connected to the first end of the second switch circuit.
  • the fourth end of the first switch circuit is connected to the first end of the second capacitor, the fifth end of the first switch circuit is connected to the third The first end of the switch circuit, the first end of the fourth switch circuit, and the first end of the fourth capacitor; the second end of the third capacitor is connected to the second end of the second switch circuit, so The third end of the second switch circuit is connected to the ground; the second end of the second capacitor is connected to the second end of the third switch circuit, the third end of the third switch circuit is connected to the ground, and the first The second end of the capacitor is connected to the second end of the fourth switch circuit, the third end of the fourth switch circuit is connected to the ground, and the second end of the fourth capacitor is connected to the ground; In voltage mode, the first switch circuit is configured to connect the power supply terminal to the first terminal of the third capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor.
  • the second switch circuit is configured to conduct the second terminal of the third capacitor with the first terminal of the first capacitor; the third switch circuit is configured to connect the second capacitor The second terminal of the first capacitor is conducted with the ground; the fourth switch circuit is configured to conduct the second terminal of the first capacitor with the first terminal of the fourth capacitor; or, the first switch The circuit is configured to conduct conduction between the first end of the third capacitor and the first end of the second capacitor, and conduct conduction between the first end of the first capacitor and the first end of the fourth capacitor; The second switch circuit is configured to connect the second end of the third capacitor to the ground; the third switch circuit is configured to connect the second end of the second capacitor to the fourth The first end of the capacitor is turned on; the fourth switch circuit is configured to conduct the second end of the first capacitor to the ground; in the second step-down mode, the first switch circuit is configured To conduct conduction between the power supply terminal and the first end of the first capacitor, and conduct conduction between the first end of the second capacitor and the first end of the fourth capacitor; the third switch circuit is configured To conduct conduction between the
  • the third switch circuit is configured to conduct the second end of the second capacitor with the first end of the fourth capacitor; the fourth switch circuit is configured to connect the first end of the first capacitor The second end is connected to the ground; in the third step-down mode, the first switch circuit is configured to connect the power supply end to the first end of the fourth capacitor.
  • the first switch circuit conducts the power supply terminal with the first terminal of the third capacitor Cfly3, and connects the first terminal of the second capacitor Cfly2 with the first terminal of the second capacitor Cfly2.
  • the first end of the fourth capacitor Co is turned on; the second switch circuit connects the second end of the third capacitor Cfly3 to the first end of the first capacitor Cfly1; the third switch circuit connects the second end of the second capacitor Cfly2 to the first end of the first capacitor Cfly1.
  • the ground GND is turned on; the fourth switch circuit conducts the second end of the first capacitor Cfly1 and the first end of the fourth capacitor Co, wherein the third capacitor Cfly3, the first capacitor Cfly1 and the fourth capacitor Co form a series structure, And the two ends of the series structure are respectively connected to the power terminal and the ground terminal GND; the second capacitor Cfly2 is connected in parallel with the fourth capacitor Co.
  • the first switch circuit 31 conducts the first end of the third capacitor Cfly3 with the first end of the second capacitor Cfly2, and connects the first end of the first capacitor Cfly1 with the first end of the fourth capacitor Co
  • the first end is turned on
  • the second switch circuit 32 conducts the second end of the third capacitor Cfly3 to the ground GND
  • the third switch circuit 33 conducts the second end of the second capacitor Cfly2 to the first end of the fourth capacitor Co
  • the fourth switch circuit conducts the second terminal of the first capacitor Cfly1 with the ground GND, wherein the first capacitor Cfly1 is connected in parallel with the fourth capacitor Co, and the series structure of the second capacitor Cfly2 and the third capacitor Cfly3 is connected with the fourth capacitor Co in parallel.
  • Vcfly3 Vcfly2+Vo
  • Vcfly2 is the voltage across the second capacitor Cfly2.
  • the first switch circuit 31 When implementing the 2:1 step-down mode, in the first time period of a cycle, the first switch circuit 31 conducts the power supply end with the first end of the first capacitor Cfly1, and connects the first end of the second capacitor Cfly2 with the first end of the second capacitor Cfly2.
  • the first end of the four capacitors Co is turned on;
  • the third switch circuit connects the second end of the second capacitor Cfly2 to the ground GND;
  • the fourth switch circuit 34 connects the second end of the first capacitor Cfly1 to the first end of the fourth capacitor Co One end conduction.
  • the first capacitor Cfly1 and the fourth capacitor Co are connected in series between the power terminal and the ground GND, and the second capacitor Cfly2 is connected in parallel with the fourth capacitor Co.
  • the first switch circuit conducts the power supply end with the first end of the second capacitor Cfly2, and conducts the first end of the first capacitor Cfly1 with the first end of the fourth capacitor Co, and the second The three switch circuits connect the second end of the second capacitor Cfly2 with the first end of the fourth capacitor Co, and the fourth switch circuit connects the second end of the first capacitor Cfly1 with the ground GND.
  • the second capacitor Cfly2 and the fourth capacitor Co are connected in series between the power terminal and the ground GND, the first capacitor Cfly1 and the fourth capacitor Co are connected in parallel, and the current flows in the direction shown by the dotted arrow in the figure.
  • Vin Vcfly1+Vo
  • Vo Cfly2.
  • the voltage at the input terminal is respectively stepped down to output at both ends of the fourth capacitor Co in the manner of 4:1, 2:1, and 1:1, so that Realized the switching of various step-down ratios.
  • the first switch circuit includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; wherein, the first end of the first switch is connected to the the first end of the first switch circuit, the second end of the first switch is connected to the second end of the first switch circuit, the first end of the second switch is connected to the second end of the first switch circuit , the second end of the second switch is connected to the fourth end of the first switch circuit, the first end of the fourth switch is connected to the second end of the first switch circuit, and the first end of the fourth switch
  • the two terminals are connected to the third terminal of the first switch circuit, the first terminal of the third switch is connected to the fourth terminal of the first switch circuit, and the second terminal of the third switch is connected to the first switch.
  • the fifth terminal of the circuit, the first terminal of the fifth switch is connected to the third terminal of the first switch circuit, and the second terminal of the fifth switch is connected to the fifth terminal of the first switch circuit.
  • the first step-down mode in the first period of time within one cycle, the first switch and the third switch are in the on state, and the second switch and the fifth switch are in the off state state; in the second period of time within one cycle, the first switch and the third switch are in an off state, and the second switch and the fifth switch are in an on state; within one cycle, the first switch The four switches are in the off state; in the second step-down mode, in the first period of time within one cycle, the third switch and the fourth switch are in the on state, and the second switch and the first switch are in the on state.
  • the fifth switch is in the off state; in the second period of time within one cycle, the third switch and the fourth switch are in the off state, and the second switch and the fifth switch are in the on state;
  • the fourth switch is in an off state within a period; the first switch is in an on state within a period; in the third step-down mode, the first switch, the second switch, the third The switch, the fourth switch, and the fifth switch are in a conducting state.
  • the second switch circuit includes: a sixth switch and a seventh switch; wherein, the first end of the sixth switch is connected to the first end of the second switch circuit, and the The second end of the sixth switch is connected to the second end of the second switch circuit, the first end of the seventh switch is connected to the second end of the second switch circuit, and the second end of the seventh switch connected to the third end of the second switch circuit; in the first step-down mode, during a first period of time within one cycle, the sixth switch is in an on state, and the seventh switch is in an off state; In the second period of time within one cycle, the sixth switch is in the off state, and the seventh switch is in the on state; in the second step-down mode, within one cycle, the sixth switch and the The seventh switch is in an off state; in the third step-down mode, the sixth switch and the seventh switch are in an off state.
  • the third switch circuit includes: an eighth switch and a ninth switch; wherein, the first end of the eighth switch is connected to the first end of the third switch circuit, and the first end of the eighth switch is connected to the first end of the third switch circuit.
  • the second end of the eighth switch is connected to the second end of the third switch circuit, the first end of the ninth switch is connected to the second end of the third switch circuit, and the second end of the ninth switch is connected to the third switch
  • the third terminal of the circuit in the first step-down mode, during the first time period within one cycle, the ninth switch is in the on state, and the eighth switch is in the off state; during the second time period within one cycle time period, the ninth switch is in the off state, and the eighth switch is in the on state; in the second step-down mode, in the first time period within one cycle, the ninth switch is in the on state , the eighth switch is in an off state; in a second period of time within one cycle, the ninth switch is in an off state, and the eighth switch is in an on state; in the third step-down mode, the The eighth switch and the ninth switch are in an off state.
  • the fourth switch circuit includes: a tenth switch and an eleventh switch, wherein the first end of the tenth switch is connected to the first end of the fourth switch circuit, and the first end of the tenth switch is connected to the first end of the fourth switch circuit.
  • the second end of the tenth switch is connected to the second end of the fourth switch circuit, the first end of the eleventh switch is connected to the second end of the fourth switch circuit, and the second end of the eleventh switch is connected to the The third end of the fourth switch circuit.
  • the tenth switch In the first step-down mode, during the first time period within one cycle, the tenth switch is in the on state, and the eleventh switch is in the off state; during the second time period within one cycle, the The tenth switch is in an off state, and the eleventh switch is in an on state; in the second step-down mode, in a first period of time within one cycle, the tenth switch is in an on state, and the eleventh switch is in an on state. Eleven is in the off state; in the second period of time within one cycle, the tenth switch is in the off state, and the eleventh switch is in the on state; in the third step-down mode, the tenth switch The switch and the eleventh switch are in an off state.
  • the first switch, the sixth switch, and the tenth switch are in the conduction state during the first period of time in one cycle, and the third capacitor, the first capacitor, and the fourth capacitor are sequentially connected
  • a current path is formed in a series relationship
  • the third switch and the ninth switch are in a conducting state, and the second capacitor and the fourth capacitor are connected in a series relationship to form another current path, and the other switches are disconnected
  • the fifth switch and the Nine switches are in a conducting state to connect the first capacitor and the fourth capacitor in series to form another current path, and the other switches are disconnected.
  • the first switch, the fourth switch, and the tenth switch are in a conducting state during the first period of time in one cycle, and the first capacitor and the fourth capacitor are sequentially connected in a series relationship, A current path is formed; the third switch and the ninth switch are in the on state, and the second capacitor and the fourth capacitor are connected in series to form another current path, and the other switches are turned off; during the second period of time in one cycle Inside, the first switch, the second switch, and the eighth switch are in the conduction state, and the second capacitor and the fourth capacitor are connected in series to form a current path; the fifth switch and the eleventh switch are in the conduction state, and the The first capacitor and the fourth capacitor are connected in parallel to form another current path, and the other switches are disconnected.
  • the first capacitor in the first time period, the first capacitor is connected in series with the fourth capacitor, and in the second time period, the first capacitor is connected in series with the second capacitor to form an interleaved parallel structure, which provides More current paths are created, which can effectively reduce power consumption.
  • the first switch, the second switch, and the third switch are in a conducting state, and the fourth capacitor is directly connected to the power supply terminal to form a current path; the first switch, the fourth switch, and the second The fifth switch is in the conduction state, and the fourth capacitor is directly connected to the power supply terminal to form another current path; thus, the current path formed by the first switch, the second switch, and the third switch is connected to the first switch, the fourth switch, and the fifth switch.
  • the current paths formed by the switches are connected in parallel, thus reducing the resistance on the charging path of the fourth circuit, effectively reducing power consumption and improving the efficiency of the SC.
  • each switch includes one switch transistor, or each switch includes two or more switch transistors connected in parallel.
  • Each switch can also use two or more switch transistors connected in parallel to reduce the resistance when the switch is turned on, thereby improving the system efficiency.
  • a chip including: a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit; wherein, the first end of the first switch circuit is connected to a power supply end; the first switch circuit The second end of a switch circuit is used to connect the first end of the third capacitor, the third end of the first switch circuit is connected to the first end of the second switch circuit, the third end of the first switch circuit It is also used to connect the first terminal of the first capacitor, the fourth terminal of the first switch circuit is used to connect the first terminal of the second capacitor, and the fifth terminal of the first switch circuit is connected to the third switch circuit The first terminal of the first switch circuit, the first terminal of the fourth switch circuit, the fifth terminal of the first switch circuit is also used to connect the first terminal of the fourth capacitor; the second terminal of the second switch circuit is used for Connect the second end of the third capacitor, the third end of the second switch circuit is connected to the ground; the second end of the third switch circuit is used to connect the second end of the second capacitor, the
  • the second terminal of the fourth capacitor is connected to the ground; in the first step-down mode, the first switch circuit is configured to conduct the power supply terminal with the first terminal of the third capacitor, and connect the The first end of the second capacitor conducts with the first end of the fourth capacitor; the second switch circuit is configured to conduct the second end of the third capacitor with the first end of the first capacitor ; the third switch circuit is configured to connect the second end of the second capacitor to the ground; the fourth switch circuit is configured to connect the second end of the first capacitor to the first The first end of the four capacitors is turned on; or, the first switch circuit is configured to conduct the first end of the third capacitor and the first end of the second capacitor, and turn on the first end of the first capacitor The first end conducts with the first end of the fourth capacitor; the second switch circuit is configured to conduct the second end of the third capacitor with the ground; the third switch circuit is configured To conduct conduction between the second end of the second capacitor and the first end of the fourth capacitor; the fourth switch circuit is configured to conduct conduction between the second end of the first capacitor and the ground
  • the first switch circuit includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; wherein, the first end of the first switch is connected to The first end of the first switch circuit, the second end of the first switch is connected to the second end of the first switch circuit, the first end of the second switch is connected to the second end of the first switch circuit Two terminals, the second terminal of the second switch is connected to the fourth terminal of the first switch circuit, the first terminal of the fourth switch is connected to the second terminal of the first switch circuit, and the fourth switch The second terminal of the third switch is connected to the third terminal of the first switch circuit, the first terminal of the third switch is connected to the fourth terminal of the first switch circuit, and the second terminal of the third switch is connected to the first switch circuit.
  • the first terminal of the fifth switch is connected to the third terminal of the first switch circuit, and the second terminal of the fifth switch is connected to the fifth terminal of the first switch circuit;
  • the first step-down mode in the first period of time within one cycle, the first switch and the third switch are in the on state, and the second switch and the fifth switch are in the off state state; in the second period of time within one cycle, the first switch and the third switch are in an off state, and the second switch and the fifth switch are in an on state; within one cycle, the first switch The four switches are in the off state; in the second step-down mode, in the first period of time within one cycle, the third switch and the fourth switch are in the on state, and the second switch and the first switch are in the on state.
  • the fifth switch is in the off state; in the second period of time within one cycle, the third switch and the fourth switch are in the off state, and the second switch and the fifth switch are in the on state;
  • the fourth switch is in an off state in a cycle; the first switch is in an on state in one cycle; in the third step-down mode, the first switch, the second switch, and the third switch , the fourth switch, and the fifth switch are in a conducting state.
  • the second switch circuit includes: a sixth switch and a seventh switch; wherein, the first end of the sixth switch is connected to the first end of the second switch circuit, and the The second end of the sixth switch is connected to the second end of the second switch circuit, the first end of the seventh switch is connected to the second end of the second switch circuit, and the second end of the seventh switch connected to the third end of the second switch circuit; in the first step-down mode, during a first period of time within one cycle, the sixth switch is in an on state, and the seventh switch is in an off state; In the second period of time within one cycle, the sixth switch is in the off state, and the seventh switch is in the on state; in the second step-down mode, the sixth switch and the seventh switch are in the Off state; in the third step-down mode, the sixth switch and the seventh switch are in an off state.
  • the third switch circuit includes: an eighth switch and a ninth switch; wherein, the first end of the eighth switch is connected to the first end of the third switch circuit, and the first end of the eighth switch is connected to the first end of the third switch circuit.
  • the second end of the eighth switch is connected to the second end of the third switch circuit, the first end of the ninth switch is connected to the second end of the third switch circuit, and the second end of the ninth switch is connected to the third switch
  • the third terminal of the circuit in the first step-down mode, during the first time period within one cycle, the ninth switch is in the on state, and the eighth switch is in the off state; during the second time period within one cycle time period, the ninth switch is in the off state, and the eighth switch is in the on state; in the second step-down mode, in the first time period within one cycle, the ninth switch is in the on state , the eighth switch is in an off state; in a second period of time within one cycle, the ninth switch is in an off state, and the eighth switch is in an on state; in the third step-down mode, the The eighth switch and the ninth switch are in an off state.
  • the fourth switch circuit includes: a tenth switch and an eleventh switch, wherein the first end of the tenth switch is connected to the first end of the fourth switch circuit, and the tenth switch The second end of the switch is connected to the second end of the fourth switch circuit, the first end of the eleventh switch is connected to the second end of the fourth switch circuit, and the second end of the eleventh switch is connected to the The third terminal of the fourth switch circuit; in the first step-down mode, during the first period of time within one cycle, the tenth switch is in the on state, and the eleventh switch is in the off state; in one cycle In the second period of time, the tenth switch is in the off state, and the eleventh switch is in the on state; in the second step-down mode, in the first time period of one cycle, the tenth switch The switch is in the on state, and the eleventh switch is in the off state; in the second period of time within one cycle, the tenth switch is in the off state, and the eleventh switch is in the eleventh switch is in
  • each switch includes one switch transistor, or each switch includes two or more switch transistors connected in parallel.
  • an electronic device including the SC as described in the first aspect or any possible implementation thereof, or including the chip as described in the second aspect or any possible implementation thereof .
  • it also includes a wireless charging coil, a receiving circuit, and a battery; the wireless charging coil is connected to the receiving circuit, the receiving circuit is connected to the power supply terminal of the SC or the chip, and the battery connected in parallel with the fourth capacitor. This realizes the wireless charging method.
  • the USB interface is connected to a power supply terminal of the SC or the chip, and the battery is connected in parallel with the fourth capacitor. This realizes the wired charging method.
  • an overvoltage protection protection circuit is also provided between the USB interface and the power supply terminal of the SC or the chip, wherein the overvoltage protection protection circuit is used to detect When the voltage of the interface exceeds the threshold voltage, the connection between the power terminal of the SC or the chip and the USB interface is cut off. In this way, it is avoided that the SC circuit or the chip and the battery are damaged when the voltage received by the USB interface is too high.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a SC connection relationship provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an SC provided by an embodiment of the present application.
  • FIG. 4 is an equivalent circuit 1 of a SC provided by an embodiment of the present application.
  • FIG. 5 is an equivalent circuit 2 of a SC provided by an embodiment of the present application.
  • FIG. 6 is an equivalent circuit 3 of a SC provided by an embodiment of the present application.
  • FIG. 7 is an equivalent circuit 4 of a SC provided by an embodiment of the present application.
  • FIG. 8 is an equivalent circuit five of a SC provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an SC provided by another embodiment of the present application.
  • FIG. 10 is a schematic diagram of the control signals of each switch of a SC provided by the embodiment of the present application:
  • FIG. 11 is a schematic diagram of a current flow of a SC provided by an embodiment of the present application.
  • Figure 12 is a second schematic diagram of the current flow of a SC provided by the embodiment of the present application.
  • Fig. 13 is a schematic structural diagram of an SC provided by another embodiment of the present application.
  • Figure 14 is a second schematic diagram of the control signals of the switches of a SC provided by the embodiment of the present application:
  • Figure 15 is a schematic diagram of the current flow of a SC provided by the embodiment of the present application III;
  • FIG. 16 is an equivalent circuit six of an SC provided by an embodiment of the present application.
  • Figure 17 is a schematic diagram 4 of the current flow of a SC provided by the embodiment of the present application.
  • Fig. 18 is an equivalent circuit 7 of a SC provided by the embodiment of the present application.
  • Fig. 19 is a schematic structural diagram of an SC provided by another embodiment of the present application.
  • Figure 20 is a schematic diagram of the control signals of each switch of a SC provided by the embodiment of the present application III:
  • Figure 21 is a schematic diagram of the current flow of a SC provided by the embodiment of the present application.
  • Figure 22 is an equivalent circuit eight of a SC provided by the embodiment of the present application.
  • Figure 23 is a schematic diagram of the current flow of a SC provided by the embodiment of the present application VI;
  • FIG. 24 is an equivalent circuit nine of an SC provided by an embodiment of the present application.
  • Figure 25 is a fourth schematic diagram of the control signals of each switch of a SC provided by the embodiment of the present application:
  • Figure 26 is a schematic diagram of the current flow of a SC provided by the embodiment of the present application VII;
  • Fig. 27 is a schematic diagram eight of the current flow of a SC provided by the embodiment of the present application.
  • FIG. 28 is a schematic diagram of the control signals of each switch of a SC provided by the embodiment of the present application V:
  • Figure 29 is a schematic diagram of the current flow of a SC provided by the embodiment of the present application.
  • FIG. 30 is an equivalent circuit 10 of an SC provided by an embodiment of the present application.
  • Fig. 31 is a schematic diagram of the current trend of a SC provided by the embodiment of the present application.
  • Fig. 32 is an equivalent circuit eleven of an SC provided by the embodiment of the present application.
  • Figure 33 is a six schematic diagram of the control signals of each switch of a SC provided by the embodiment of the present application:
  • Fig. 34 is a schematic diagram eleven of the current flow of a SC provided by the embodiment of the present application.
  • FIG. 35 is an equivalent circuit twelve of an SC provided by an embodiment of the present application.
  • Fig. 36 is a schematic diagram of the current trend of a SC provided by the embodiment of the present application.
  • FIG. 37 is an equivalent circuit thirteen of an SC provided by an embodiment of the present application.
  • Fig. 38 is a schematic diagram of the current trend of a SC provided by the embodiment of the present application.
  • Figure 39 is a fourteenth schematic diagram of the current flow of a SC provided by the embodiment of the present application.
  • Figure 40 is a schematic diagram of the current flow of a SC provided by the embodiment of the present application.
  • FIG. 41 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more. Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action that is “based on” one or more stated conditions or values may in practice be based on additional conditions or beyond stated values.
  • the SC provided by the embodiment of the present application can be applied to mobile phones, tablet computers, notebook computers, ultra-mobile personal computers (ultra-mobile personal computer, UMPC), handheld computers, netbooks, personal digital assistants (personal digital assistant, PDA),
  • UMPC ultra-mobile personal computer
  • PDA personal digital assistant
  • the embodiment of the present application does not impose any limitation on this.
  • FIG. 1 shows a schematic structural diagram of an electronic device 100 .
  • the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, and an antenna 2 , mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 193 and display screen 194, etc.
  • a processor 110 an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, and an antenna 2 , mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 193 and display screen 194, etc.
  • USB universal serial bus
  • the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processing unit
  • GPU graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • baseband processor baseband processor
  • neural network processor neural-network processing unit
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is a cache memory.
  • the memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be called directly from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thereby improving the efficiency of the system.
  • processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input and output (general-purpose input/output, GPIO) interface, subscriber identity module (subscriber identity module, SIM) interface, and /or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input and output
  • subscriber identity module subscriber identity module
  • SIM subscriber identity module
  • USB universal serial bus
  • the charging management module 140 is configured to receive a charging input from a charger.
  • the charger may be a wireless charger or a wired charger (or an adapter).
  • the charging management module 140 can receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 may receive a wireless charging input through a wireless charging coil of the electronic device 100 . While the charging management module 140 is charging the battery 142 , it can also supply power to the electronic device through the power management module 141 . Specifically, as shown in FIG.
  • the charging management module 140 can be connected to the USB interface 130 through an overvoltage protection (over voltage protection, OVP) protection circuit 131, wherein, when the OVP protection circuit 131 detects that the voltage connected to the USB interface 130 When the voltage is too high (over the threshold voltage), the connection between the charging management module 140 and the USB interface 130 can be cut off actively.
  • OVP over voltage protection
  • the charging management module 140 is specifically connected to the wireless charging coil 132 through a receiving circuit (receive integrated circuit, Rx IC) 133.
  • Rx IC receiving integrated circuit
  • SC and BUCK are connected to the USB interface 130 through the OVP protection circuit 131, and connected to the wireless charging coil 132 through the Rx IC133.
  • the processor 110 or the charging management module 140 can detect BUCK or SC to charge the battery according to the charging protocol.
  • SC and BUCK are step-down conversion circuits with a fixed step-down ratio. For example, according to the charging protocol, it is detected that the voltage on the input side of SC and BUCK is 5V.
  • control BUCK to convert the voltage of 5V to 2V, which is slightly higher than the battery voltage, and then charge the battery, or, when the voltage at the input side of SC and BUCK is detected to be 20V according to the charging protocol, it is determined that this is a fast charging scene, then Control the SC to charge the battery after converting the 20V voltage to a voltage close to the battery voltage.
  • a lower charging power for example, 40W
  • the charging protocol will control the SC to reduce the input 10V voltage to around 5V in a 2:1 step-down mode to continue charging the battery; of course, When the charging protocol controls the adapter or wireless charger to further reduce the voltage, it is necessary to control the SC to further switch the step-down mode to ensure that the output voltage is continuously maintained at about 5V, so as to ensure the effect of fast charging.
  • the specific structure of the SC is mainly described.
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the power management module 141 receives the input from the battery 142 and/or the charging management module 140 to provide power for the processor 110 , the internal memory 121 , the display screen 194 , the camera 193 , and the wireless communication module 160 .
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, and battery health status (leakage, impedance).
  • the power management module 141 may also be disposed in the processor 110 .
  • the power management module 141 and the charging management module 140 may also be set in the same device.
  • the wireless communication function of the electronic device 100 can be realized by the antenna 1 , the antenna 2 , the mobile communication module 150 , the wireless communication module 160 , a modem processor, a baseband processor, and the like.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 100 may be used to cover single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas.
  • Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network.
  • the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the electronic device 100 .
  • the mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (low noise amplifier, LNA) and the like.
  • the mobile communication module 150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and send them to the modem processor for demodulation.
  • the mobile communication module 150 can also amplify the signals modulated by the modem processor, and convert them into electromagnetic waves and radiate them through the antenna 1 .
  • at least part of the functional modules of the mobile communication module 150 may be set in the processor 110 .
  • at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be set in the same device.
  • a modem processor may include a modulator and a demodulator.
  • the modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator sends the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low-frequency baseband signal is passed to the application processor after being processed by the baseband processor.
  • the application processor outputs sound signals through audio equipment (not limited to speaker 170A, receiver 170B, etc.), or displays images or videos through display screen 194 .
  • the modem processor may be a stand-alone device.
  • the modem processor may be independent from the processor 110, and be set in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide wireless local area networks (wireless local area networks, WLAN) (such as wireless fidelity (Wireless fidelity, Wi-Fi) network), bluetooth (Bluetooth, BT), global navigation satellite, etc. System (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions.
  • the wireless communication module 160 may be one or more devices integrating one or more communication processing modules.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency-modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110 , frequency-modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.
  • the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), broadband Code division multiple access (wideband code division multiple access, WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (long term eVolution, LTE), BT, GNSS, WLAN, NFC , FM, and/or IR techniques, etc.
  • the GNSS may include a global positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a Beidou navigation satellite system (beidou navigation satellite system, BDS), a quasi-zenith satellite system (quasi -zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).
  • GPS global positioning system
  • GLONASS global navigation satellite system
  • Beidou navigation satellite system beidou navigation satellite system
  • BDS Beidou navigation satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite based augmentation systems
  • the electronic device 100 realizes the display function through the GPU, the display screen 194 , and the application processor.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 194 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.
  • the display screen 194 is used to display images, videos and the like.
  • the display screen 194 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED), etc.
  • the electronic device 100 may include 1 or N display screens 194 , where N is a positive integer greater than 1.
  • the electronic device 100 can realize the shooting function through the ISP, the camera 193 , the video codec, the GPU, the display screen 194 and the application processor.
  • the ISP is used for processing the data fed back by the camera 193 .
  • the light is transmitted to the photosensitive element of the camera through the lens, and the light signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness, and skin color.
  • ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be located in the camera 193 .
  • Camera 193 is used to capture still images or video.
  • the object generates an optical image through the lens and projects it to the photosensitive element.
  • the photosensitive element may be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor.
  • CMOS complementary metal-oxide-semiconductor
  • the photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal.
  • the ISP outputs the digital image signal to the DSP for processing.
  • DSP converts digital image signals into standard RGB, YUV and other image signals.
  • the electronic device 100 may include 1 or N cameras 193 , where N is a positive integer greater than 1.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, so as to expand the storage capacity of the electronic device 100.
  • the external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. Such as saving music, video and other files in the external memory card.
  • the internal memory 121 may be used to store one or more computer programs including instructions.
  • the processor 110 may execute the above-mentioned instructions stored in the internal memory 121, so that the electronic device 100 executes the methods provided in some embodiments of the present application, as well as various functional applications and data processing.
  • the internal memory 121 may include an area for storing programs and an area for storing data.
  • the stored program area can store an operating system; the stored program area can also store one or more application programs (such as a gallery, contacts, etc.) and the like.
  • the storage data area can store data (such as photos, contacts, etc.) created during the use of the electronic device 101 .
  • the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (universal flash storage, UFS) and the like.
  • the processor 110 causes the electronic device 100 to execute the method provided in the embodiment of the present application by executing the instructions stored in the internal memory 121 and/or the instructions stored in the memory provided in the processor, And various functional applications and data processing.
  • the electronic device 100 can implement audio functions through the audio module 170 , the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor. Such as music playback, recording, etc.
  • the audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signal.
  • the audio module 170 may also be used to encode and decode audio signals.
  • the audio module 170 can be set in the processor 110, or some functional modules of the audio module 170 can be set in the processor 110.
  • Speaker 170A also referred to as a "horn" is used to convert audio electrical signals into sound signals.
  • Electronic device 100 can listen to music through speaker 170A, or listen to hands-free calls.
  • Receiver 170B also called “earpiece” is used to convert audio electrical signals into sound signals.
  • the receiver 170B can be placed close to the human ear to receive the voice.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can put his mouth close to the microphone 170C to make a sound, and input the sound signal to the microphone 170C.
  • the electronic device 100 may be provided with one or more microphones 170C. In some other embodiments, the electronic device 100 may be provided with two microphones 170C, which may also implement a noise reduction function in addition to collecting sound signals. In some other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify sound sources, and realize directional recording functions, etc.
  • the earphone interface 170D is used for connecting wired earphones.
  • the earphone interface 170D can be a USB interface 130, or a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.
  • OMTP open mobile terminal platform
  • CTIA cellular telecommunications industry association of the USA
  • the sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.
  • the above-mentioned electronic device may also include one or more components such as a key 190, a motor 191, an indicator 192, and a subscriber identification module (subscriber identification module, SIM) card interface 195, which is not limited in this embodiment of the present application. .
  • a key 190 a motor 191, an indicator 192, and a subscriber identification module (subscriber identification module, SIM) card interface 195, which is not limited in this embodiment of the present application. .
  • SIM subscriber identification module
  • an embodiment of the present application provides an SC, as shown in FIG.
  • the first terminal of the first switch circuit 31 is connected to the power supply terminal, and the power supply terminal is connected to the power adapter through the USB interface, or connected to the wireless charging circuit, so as to provide the input voltage Vin to the Sc;
  • the second terminal of the first switch circuit 31 is connected to The first terminal of the third capacitor Cfly3, the third terminal of the first switch circuit 31 is connected to the first terminal of the second switch circuit 32 and the first terminal of the first capacitor fly1, and the fourth terminal of the first switch circuit 31 is connected to the first terminal of the first switch circuit 31.
  • the first end of the second capacitor Cfly, the fifth end of the first switch circuit 31 is connected to the first end of the third switch circuit 33, the first end of the fourth switch circuit 33 and the first end of the fourth capacitor Co;
  • the third capacitor The second end of Cfly3 is connected to the second end of the second switch circuit 32, and the third end of the second switch circuit 32 is connected to the ground GND;
  • the second end of the second capacitor Cfly2 is connected to the second end of the third switch circuit 33, and the third The third end of the switch circuit 33 is connected to the ground GND
  • the second end of the first capacitor Cfly1 is connected to the second end of the fourth switch circuit 34
  • the third end of the fourth switch circuit 34 is connected to the ground GND, and the second end of the fourth capacitor Co Terminal connected to GND.
  • the first capacitor Cfly1, the second capacitor Cfly2, and the third capacitor Cfly3 are flying capacitors, and the fourth capacitor Co is used as an output capacitor (output capacitance), and the voltage at both ends of the capacitor is supplied to the load RL (wherein the mobile phone scene Next, the load refers to the battery) to provide a stable supply voltage.
  • the first switch circuit 31 is configured to conduct the power supply terminal and the first terminal of the third capacitor Cfly3, and connect the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co.
  • the second switch circuit 32 is configured to conduct the second end of the third capacitor Cfly3 with the first end of the first capacitor Cfly1;
  • the third switch circuit 33 is configured to connect the second end of the second capacitor Cfly2 conduction with the ground GND;
  • the fourth switch circuit 34 is configured to conduct conduction between the second terminal of the first capacitor Cfly1 and the first terminal of the fourth capacitor Co.
  • the first switch circuit 31 is configured to connect the first end of the third capacitor Cfly3 to the first end of the second capacitor Cfly2, and connect the first end of the first capacitor Cfly1 to the first end of the fourth capacitor Co.
  • the second switch circuit 32 is configured to connect the second terminal of the third capacitor Cfly3 to the ground GND; the third switch circuit 33 is configured to connect the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co The end is turned on; the fourth switch circuit 34 is configured to turn on the second end of the first capacitor Cfly1 to the ground GND.
  • the first switch circuit 31 is configured to conduct the power supply terminal with the first terminal of the first capacitor Cfly1, and conduct the first terminal of the second capacitor Cfly2 with the first terminal of the fourth capacitor Co.
  • the third switch circuit 33 is configured to connect the second terminal of the second capacitor Cfly2 to the ground GND; the fourth switch circuit 34 is configured to connect the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co terminal conduction.
  • the first switch circuit 31 is configured to conduct the first terminal of the second capacitor Cfly2 with the power supply terminal, and conduct the first terminal of the first capacitor Cfly1 with the first terminal of the fourth capacitor Co;
  • the third switch circuit 33 is configured to connect the second end of the second capacitor Cfly2 to the first end of the fourth capacitor Co, and the fourth switch circuit 34 is configured to connect the second end of the first capacitor Cfly1 to the ground GND.
  • the first switch circuit 31 is configured to conduct the power supply terminal with the first terminal of the fourth capacitor Co.
  • the first switch circuit 31 conducts the power supply end with the first end of the third capacitor Cfly3, and connects the first end of the second capacitor Cfly2 conduction with the first end of the fourth capacitor Co;
  • the second switch circuit 32 conducts the second end of the third capacitor Cfly3 with the first end of the first capacitor Cfly1;
  • the third switch circuit 33 connects the second end of the second capacitor Cfly2 The two terminals are connected to the ground GND;
  • the fourth switch circuit 34 conducts the second terminal of the first capacitor Cfly1 with the first terminal of the fourth capacitor Co, thereby connecting each capacitor into an equivalent circuit as shown in FIG.
  • the third capacitor Cfly3, the first capacitor Cfly1 and the fourth capacitor Co form a series structure, and the two ends of the series structure are respectively connected to the power terminal and the ground terminal GND; the second capacitor Cfly2 is connected in parallel with the fourth capacitor Co, and the current flows as The direction indicated by the dotted arrow in the figure.
  • the first switch circuit 31 conducts the first end of the third capacitor Cfly3 with the first end of the second capacitor Cfly2, and connects the first end of the first capacitor Cfly1 with the first end of the fourth capacitor Co
  • the first end is turned on
  • the second switch circuit 32 conducts the second end of the third capacitor Cfly3 to the ground GND
  • the third switch circuit 33 conducts the second end of the second capacitor Cfly2 to the first end of the fourth capacitor Co
  • the fourth switch circuit conducts the second end of the first capacitor Cfly1 with the ground GND, thereby connecting each capacitor into an equivalent circuit as shown in FIG.
  • the first switch circuit 31 When implementing the 2:1 step-down mode, in the first time period of a cycle, the first switch circuit 31 conducts the power supply end with the first end of the first capacitor Cfly1, and connects the first end of the second capacitor Cfly2 with the first end of the second capacitor Cfly2. The first end of the four capacitors Co is turned on; the third switch circuit 33 connects the second end of the second capacitor Cfly2 to the ground GND; the fourth switch circuit 34 connects the second end of the first capacitor Cfly1 to the fourth capacitor Co The first end is turned on. Therefore, each capacitor is connected into an equivalent circuit as shown in FIG.
  • the first switch circuit 31 conducts the power supply end with the first end of the second capacitor Cfly2, and conducts the first end of the first capacitor Cfly1 with the first end of the fourth capacitor Co
  • the third switch circuit 33 conducts the second terminal of the second capacitor Cfly2 with the first terminal of the fourth capacitor Co
  • the fourth switch circuit 34 conducts the second terminal of the first capacitor Cfly1 with the ground GND. Therefore, each capacitor is connected into an equivalent circuit as shown in FIG. 7, wherein the second capacitor Cfly2 and the fourth capacitor Co are connected in series between the power supply terminal and the ground GND, the first capacitor Cfly1 is connected in parallel with the fourth capacitor Co, and the current flows to The direction indicated by the dotted arrow in the figure.
  • Vin Vcfly2+Vo
  • Vo Cfly1.
  • the voltage at the input terminal is respectively stepped down to output at both ends of the fourth capacitor Co in the manner of 4:1, 2:1, and 1:1, so that Realized the switching of various step-down ratios.
  • the first switch circuit 31 includes switches Q1, Q2, Q3, Qadd, and Q8; wherein, the first end of the switch Q1 is connected to the first end of the first switch circuit 31, and the second end of the switch Q1 is connected to the second end of the switch Q1.
  • the second end of a switch circuit 31 the first end of the switch Q2 is connected to the second end of the first switch circuit 31, the second end of the switch Q2 is connected to the fourth end of the first switch circuit 31, and the first end of the switch Qadd is connected to The second end of the first switch circuit 31, the second end of the switch Qadd is connected to the third end of the first switch circuit 31, the first end of the switch Q3 is connected to the fourth end of the first switch circuit 31, the second end of the switch Q3 connected to the fifth terminal of the first switch circuit 31 , the first terminal of the switch Q8 is connected to the third terminal of the first switch circuit 31 , and the second terminal of the switch Q8 is connected to the fifth terminal of the first switch circuit 31 .
  • the second switch circuit 32 includes switches Q6 and Q7, wherein the first end of the switch Q6 is connected to the first end of the second switch circuit 32, the second end of the switch Q6 is connected to the second end of the second switch circuit 32, and the second end of the switch Q7 is connected to the second end of the second switch circuit 32.
  • One end is connected to the second end of the second switch circuit 32 , and the second end of the switch Q7 is connected to the third end of the second switch circuit 32 .
  • the third switch circuit 33 includes switches Q4 and Q5, wherein the first end of the switch Q4 is connected to the first end of the third switch circuit 33, the second end of the switch Q4 is connected to the second end of the third switch circuit 33, and the first end of the switch Q5 is connected to the second end of the third switch circuit 33.
  • One end is connected to the second end of the third switch circuit 33 , and the second end of the switch Q5 is connected to the third end of the third switch circuit 33 .
  • the fourth switch circuit 34 includes switches Q9 and Q10, wherein the first end of the switch Q9 is connected to the first end of the fourth switch circuit 34, the second end of the switch Q9 is connected to the second end of the fourth switch circuit 34, and the first end of the switch Q10 is connected to the second end of the fourth switch circuit 34.
  • One end is connected to the second end of the fourth switch circuit 34 , and the second end of the switch Q10 is connected to the third end of the fourth switch circuit 34 .
  • the above-mentioned switches Q1-Q10 and Qadd all include a control terminal, and under the control of the control terminal, the switch can switch its two ends between on and off states.
  • the switch may use a switch transistor (referred to as a switch tube or transistor), and in the embodiment of the present application, the switch transistor may use a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • each switch is implemented with a switch transistor. It can be understood that in order to reduce the resistance when the switch is turned on, each switch may also use two or more switch transistors connected in parallel.
  • the switching transistors are classified into two types: N (negative, negative) type transistors and P (positive, positive) type transistors.
  • the switching transistor includes a source (source), a drain (drain) and a gate (gate). By controlling the level input to the gate of the switching transistor, the switching transistor can be controlled to be turned on (on) or off (off, cut off, open circuit ).
  • the switching transistor is turned on, the source and drain are turned on to generate a turn-on current, and when the gate level of the transistor is different, the magnitude of the turn-on current generated between the source and the drain is also different; the switch transistor is turned off When , the source and drain will not conduct and no current will flow.
  • the gate of the switching transistor is also called the control terminal, the source is called the first terminal, and the drain is called the second terminal; or, the gate is called the control terminal, and the drain is called the second terminal. is called the first terminal and the source is called the second terminal.
  • the N-type transistor is turned on when the level of the control terminal is high, the first terminal and the second terminal are turned on, and a turn-on current is generated between the first terminal and the second terminal; the level of the N-type transistor is low at the control terminal. Normally closed, the first terminal and the second terminal are not conducted, and no current is generated.
  • the P-type transistor is turned on when the level of the control terminal is low, and the first terminal and the second terminal are turned on to generate a turn-on current; the P-type transistor is turned off when the level of the control terminal is high, and the first terminal and the second terminal are not connected. conduction, no current flow.
  • FIG. 10 provides a time sequence diagram of the control signals of each switch in FIG. 9 in a time period T in the 4:1 step-down mode.
  • the switch Qadd under the control of S3
  • the switch Qadd is in the off state during the entire time period T.
  • the switches Q1, Q3, Q5, Q6 and Q9 are under the control of S1.
  • the switches Q2, Q4, Q7, Q8, and Q10 are in the on state under the control of S2, and each capacitor is connected to form an equivalent circuit as shown in Figure 5; thus, a 4:1 voltage ratio conversion can be realized.
  • the control signal is in the on state when the logic level is high (H), and the control signal is in the off state when the logic level is low (L) as an example for illustration.
  • a typical Dickson-based SC which includes Q1-Q8, eight switches, and four capacitors Cfly1, Cfly1, Cfly3 and Co.
  • the switches Q1, Q2, Q3, Q4 and the capacitor Co are serially connected between the power supply terminal (providing the power supply voltage Vin) and the ground GND in sequence, the series structure of the switches Q5 and Q6 is connected in parallel with the capacitor Co, and the series structure of the switches Q8 and Q7 is connected with Capacitor Co is connected in parallel, the series structure of switches Q2, Q3, Q4, Q5 is connected in parallel with capacitor Cfly3, the series structure of switches Q4 and Q5 is connected in parallel with capacitor Cfly1, the series structure of switches Q3, Q4, Q8 is connected in parallel with capacitor Cfly2, the two ends of capacitor Co The output voltage supplies power to the load RL.
  • FIG. 14 provides a timing diagram of the control signals of each switch in FIG. 13 in a time period T in the 4:1 step-down mode. Wherein, taking each switch is turned on at high level and turned off at low level as an example, then in the first period t1 of a time period T, as shown in FIG.
  • the switches Q1, Q3, Q5, and Q7 are in the OFF state under the control of S1 and the switches Q2, Q4, Q7, and Q8 are in the ON state under the control of S2.
  • Capacitors are connected to form an equivalent circuit shown in Figure 18; wherein, the first capacitor Cfly1 and the fourth capacitor CO form a series structure, the second capacitor Cfly2 and the fourth capacitor CO form a series structure and the third capacitor Cfly3 in parallel, and the current flows as The direction indicated by the dotted arrow in the figure.
  • FIG. 19 another typical Dickson-based SC is provided, which includes Q1-Q10, ten switches, and four capacitors Cfly1, Cfly1, Cfly3 and Co.
  • switches Q1, Q2, Q3 and capacitor Co are serially connected between the power supply terminal (providing power supply voltage Vin) and ground GND in sequence
  • the series structure of switches Q4 and Q5 is connected in parallel with capacitor Co
  • the series structure of switches Q8, Q6 and Q7 is connected with Capacitor Co is connected in parallel
  • the series structure of switches Q9 and Q10 is connected in parallel with capacitor Co
  • the series structure of switches Q2, Q3, Q8, Q6 is connected in parallel with capacitor Cfly3
  • the series structure of switches Q3 and Q4 is connected in parallel with capacitor Cfly2
  • the series structure of switches Q8 and Q9 The structure is connected in parallel with the capacitor Cfly1, and the voltage output from both ends of the capacitor Co supplies power to the load RL.
  • FIG. 20 provides a timing diagram of the control signals of each switch in FIG. 19 in a time period T in the 4:1 step-down mode.
  • the switches Q1, Q3, Q5, Q6, and Q9 are Under the control of S1, it is in an on state, and the switches Q2, Q4, Q7, Q8, and Q10 are in an off state under the control of S2, and the respective capacitors are connected to form an equivalent circuit shown in FIG.
  • the third capacitor Cfly3 The first capacitor Cfly1 and the fourth capacitor Co form a series structure, and the two ends of the series structure are respectively connected to the power supply terminal and the ground terminal GND; the second capacitor Cfly2 is connected in parallel with the fourth capacitor Co, and the current flows as shown by the dotted arrow in the figure direction.
  • Vcfly3 Vcfly2+Vo
  • Vcfly2 is the voltage at both ends of the capacitor Cfly2
  • Vin 4Vo
  • Vcfly3 2Vo
  • Vcfly2 Vo
  • Vcfly1 Vo
  • FIG. 25 provides a timing diagram of the control signals of each switch in FIG. 9 in a time period T in the 2:1 step-down mode.
  • switches Q6 and Q7 under the control of S3 are in the off state during the entire time period T
  • Q1 under the control of S4
  • the switches Qadd, Q3, Q5 and Q9 are in the conduction state under the control of S1
  • the switches Q2, Q4, Q8 and Q10 are in the ON state under the control of S2.
  • each capacitor is connected to form the equivalent circuit shown in Figure 6; in the second time period t2, referring to Figure 27, the switches Qadd, Q3, Q5, and Q9 are in the disconnected state under the control of S1, and the switch Q2 , Q4, Q8, and Q10 are in the conduction state under the control of S2, and each capacitor is connected to form an equivalent circuit as shown in FIG. 7; thus, a voltage ratio conversion of 2:1 can be realized.
  • FIG. 28 provides a timing diagram of the control signals of each switch in FIG. 13 in a time period T in the 2:1 step-down mode.
  • the switches Q2 and Q3 are in the on state during the entire time period T.
  • the switches Q1, Q5, and Q8 are in the on state under the control of S1
  • the switches Q4, Q6, and Q7 are in the off state under the control of S2. Connect each capacitor to form an equivalent circuit shown in FIG.
  • the third capacitor Cfly3 and the fourth capacitor Co form a series structure, and the two ends of the series structure are respectively connected to the power supply terminal and the ground terminal GND; the second capacitor Cfly2 and the fourth capacitor Co
  • the fourth capacitor Co forms a series structure, and the two ends of the series structure are respectively connected to the power terminal and the ground terminal GND, the first capacitor Cfly1 and the fourth capacitor Co form a series structure, and the two ends of the series structure are respectively connected to the power terminal and the ground Terminal GND.
  • the switches Q1, Q5, and Q8 are in the OFF state under the control of S1
  • the switches Q4, Q6, and Q7 are in the ON state under the control of S2.
  • FIG. 33 provides a timing diagram of the control signals of each switch in FIG. 19 in a time period T in the 2:1 step-down mode.
  • taking each switch is turned on at high level and disconnected at low level as an example, where Q6-Q10 (under the control of S3) are in the off state during the entire time period T, Q1 (under the control of S4 ) is in the conduction state during the entire time period T.
  • Q6-Q10 under the control of S3
  • Q1 under the control of S4
  • the switches Q2 and Q4 are in the on state under the control of S1, and the switches Q3 and Q5 are in the off state under the control of S2, and each capacitor is connected to Form the equivalent circuit shown in Figure 35; wherein, the third capacitor Cfly3 and the first capacitor Cfly1 are disconnected from the circuit; the second capacitor Cfly2 and the fourth capacitor Co form a series structure, and the two ends of the series structure are respectively connected to the power supply terminal and the ground terminal GND, the current flows in the direction indicated by the dotted arrow in the figure.
  • step-down mode by adding a switch Qadd, more flying capacitors (Cfly1 and Cfly2) can be used, wherein in the t1 time period, the capacitor Cfly1 is connected in series with the capacitor Co, and in the t2 time period, the capacitor Cfly1 is connected in parallel with the capacitor Co , forming a staggered parallel structure. More current paths are provided for the power supply terminal, which can effectively reduce power consumption compared with the solution provided in FIG. 19 .
  • the switches Q1, Q2, Q3, Qadd, and Q8 are controlled to be turned on during the entire time period, and the other switches Q4-Q7, Q9, and Q10 are controlled to be turned off, as shown in the figure 38; in this way, each capacitor is connected to form the equivalent circuit shown in Figure 8; thus a 1:1 voltage ratio conversion can be realized.
  • the control switches Q1, Q2, Q3, and Q4 are turned on during the entire time period, and the other switches Q5-Q8 are turned off, as shown in Figure 39; The equivalent circuit; thus a 1:1 voltage ratio conversion can be realized.
  • the SC provided in Figure 9 can implement multiple step-down modes of 4:1, 2:1 and 1:1, and compared with the existing two SCs based on the Dickson architecture ( Figure 13 and Figure 19 provided SC) with higher efficiency.
  • a chip 30 is provided, wherein the chip 30 includes: a first switch circuit 31 , a second switch circuit 32 , a third switch circuit 33 , and a fourth switch circuit 34 .
  • the difference from the SC circuit provided in FIG. 3 is that since the capacitor needs to be implemented through a large-sized plate, it is not conducive to integration on the chip. Therefore, the SC provided in FIG. 3 can be formed by the chip 30 provided in FIG. Specifically, the packaging structure of the chip 30 provided with reference to FIG. 41 includes: a first switch circuit 31, a second switch circuit 32, a third switch circuit 33, and a fourth switch circuit 34, wherein the chip 30 also includes P1-P10 A total of 10 chip pins (pin).
  • the first end of the first switch circuit 31 is connected to the power supply terminal Vin through P1; the second end of the first switch circuit 31 is used to connect the first end of the third capacitor Cfly3 through P2, and the third end of the first switch circuit 31 is connected to the first end of the first switch circuit 31.
  • the first end of the second switch circuit 31, the third end of the first switch circuit 31 is also used to connect the first end of the first capacitor Cfly1 through P7, and the fourth end of the first switch circuit 31 is used to connect the second capacitor through P5
  • the first end of Cfly2, the fifth end of the first switch circuit 31 connects the first end of the third switch circuit 33, the first end of the fourth switch circuit 34, and the fifth end of the first switch circuit 31 is also used for passing through P9 Connect the first end of the fourth capacitor Co;
  • the second end of the second switch circuit 32 is used to connect the second end of the third capacitor Cfly3 through P3, and the third end of the second switch circuit 32 is connected to the ground GND through P10;
  • the third The second end of the switch circuit 33 is used to connect the second end of the second capacitor Cfly2 through P6, the third end of the third switch circuit 33 is connected to the ground GND through P10, and the second end of the fourth switch circuit 34 is used to connect to the second end of the second capacitor Cfly2 through
  • the second terminal of the first capacitor Cfly1 and the third terminal of the fourth switch circuit 34 are connected to the ground GND through P10, and the second terminal of the fourth capacitor Co is connected to the ground GND.
  • the internal structures and working principles of the first switch circuit 31, the second switch circuit 32, the third switch circuit 33, and the fourth switch circuit 34 in this chip can refer to the detailed descriptions in the above-mentioned embodiments, and will not be repeated here. repeat.

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Abstract

本申请实施例提供一种开关电容电路SC及电子设备，涉及电子技术领域，能够自由切换多种降压比例。该SC，第一开关电路的第一端连接电源端，第二端连接第三电容的第一端，第一开关电路的第三端连接第二开关电路的第一端、以及第一电容的第一端，第一开关电路的第四端连接第二电容的第一端，第一开关电路的第五端所述第三开关电路的第一端、第四开关电路的第一端以及第四电容的第一端；第三电容的第二端连接第二开关电路的第二端，第二开关电路的第三端连接地；第二电容的第二端连接第三开关电路的第二端，第三开关电路的第三端连接地，第一电容的第二端连接第四开关电路的第二端，第四开关电路的第三端连接地，第四电容的第二端连接地。

Description

一种开关电容电路SC及电子设备
本申请要求于2022年01月30日提交国家知识产权局、申请号为202210114727.7、申请名称为“一种开关电容电路SC及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及电子技术领域，尤其涉及一种开关电容电路SC及电子设备。
背景技术
手机、手表、平板电脑等终端设备实现有线或无线快速充电都是通过电源适配器或者无线充电电路输出电池电压的2倍(或4倍)的高电压后，再通过终端设备内的开关电容电路(switched capacitor converter，SC)将该高电压降至1/2(或1/4)电压给电池充电。这样，在同等功率下采用高电压传输电能可以减小传输电流，降低线损。此外，SC具有开环高效的特性，结合充电协议控制适配器或者无线充电电路调压或者调流，可以使整个终端设备的充电***高效，降低热耗，从而实现超级快速充电。
通常，在快速充电的起始阶段，充电协议控制适配器或者无线充电电路以较高的充电功率(例如60W)实现对电池的快速充电，此时充电协议控制适配器或者无线充电器向SC输出较高的电压(例如20V)，SC此时工作在4:1的降压模式下，将20V的电压转换为5V为电池充电。当电池电压或者容量上升至一定阶段，或热耗过大充电功率时，需要控制适配器或者无线充电器下降切换至较低的充电功率(例如40W)，适配器或者无线充电器向SC输出的电压会降至10V附近，此时为了维持原先的充电电流，以保持快速充电，充电协议会控制SC以2:1的降压模式将输入的10V电压降至5V附近继续给电池充电；当然，充电协议控制适配器或者无线充电器进一步降低电压时，需要控制SC进一步切换降压模式，以保证输出的电压持续维持在5V左右，以此确保快速充电的效果。那么便需要相应的提供一种能够自由切换多种降压比例的SC。
发明内容
本申请的实施例提供一种开关电容电路SC及电子设备，能够自由切换多种降压比例。
第一方面，提供一种开关电容电路SC，包括：第一开关电路、第二开关电路、第三开关电路、第四开关电路以及第一电容、第二电容、第三电容以及第四电容；其中，第一开关电路的第一端连接电源端；第一开关电路的第二端连接第三电容的第一端，所述第一开关电路的第三端连接所述第二开关电路的第一端、以及所述第一电容的第一端，所述第一开关电路的第四端连接所述第二电容的第一端，所述第一开关电路的第五端连接所述第三开关电路的第一端、所述第四开关电路的第一端以及所述第四电容的第一端；所述第三电容的第二端连接所述第二开关电路的第二端，所述第二开关电路的第三端连接地；所述第二电容的第二端连接所述第三开关电路的第二端，所述第三开关电路的第三端连接地，所述第一电容的第二端连接所述第四开关电路的第二端，所述第四开关电路的第三端连接所述地，所述第四电容的第二端连接所述地；在 第一降压模式下，所述第一开关电路被配置为将所述电源端与所述第三电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置将所述第三电容的第二端与所述第一电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第三电容的第一端与所述第二电容的第一端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置为将所述第三电容的第二端与所述地导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；在第二降压模式下，所述第一开关电路被配置为将所述电源端与所述第一电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第二电容的第一端与所述电源端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；在第三降压模式下，所述第一开关电路被配置为将所述电源端与所述第四电容的第一端导通。
这样在实现4:1降压模式时，在一个时间周期的第一时间段，第一开关电路将电源端与第三电容Cfly3的第一端导通，将第二电容Cfly2的第一端与第四电容Co的第一端导通；第二开关电路将第三电容Cfly3的第二端与第一电容Cfly1的第一端导通；第三开关电路将第二电容Cfly2的第二端与地GND导通；第四开关电路将第一电容Cfly1的第二端与第四电容Co的第一端导通，其中，第三电容Cfly3、第一电容Cfly1以及第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND；第二电容Cfly2与第四电容Co并联。这样，当***稳定时：Vin＝Vcfly3+Vcfly1+Vo，Vcfly2＝Vo；其中Vcfly3为第三电容Cfly3两端的电压，Vcfly1为第一电容Cfly1两端的电压，V0为第四电容Co两端的电压。在一个周期的第二时间段，第一开关电路31将第三电容Cfly3的第一端与第二电容Cfly2的第一端导通，将第一电容Cfly1的第一端与第四电容Co的第一端导通，第二开关电路32将第三电容Cfly3的第二端与地GND导通，第三开关电路33将第二电容Cfly2的第二端与第四电容Co的第一端导通，第四开关电路将第一电容Cfly1的第二端与地GND导通，其中第一电容Cfly1与第四电容Co并联，第二电容Cfly2与第三电容Cfly3的串联结构与第四电容Co并联。这样，当***稳定时：Vcfly3＝Vcfly2+Vo，Vcfly2为第二电容Cfly2两端的电压。综上，可得Vin＝4Vo，Vcfly3＝2Vo，Vcfly2＝Vo，Vcfly1＝Vo，由此可以实现4:1的电压比例变换。
在实现2:1降压模式时，在一个周期的第一时间段，第一开关电路31将电源端与第一电容Cfly1的第一端导通，将第二电容Cfly2的第一端与第四电容Co的第一端导通；第三开关电路将第二电容Cfly2的第二端与地GND导通；第四开关电路34将第一电容Cfly1的第二端与第四电容Co的第一端导通。其中，第一电容Cfly1与第四电容Co串联在电源端与地GND之间，第二电容Cfly2与第四电容Co并联。这样，当*** 稳定时：Vin＝Vcfly1+Vo，Vo＝Cfly2。在一个周期的第二时间段，第一开关电路将电源端与第二电容Cfly2的第一端导通，将第一电容Cfly1的第一端与第四电容Co的第一端导通，第三开关电路将第二电容Cfly2的第二端与第四电容Co的第一端导通，第四开关电路将第一电容Cfly1的第二端与地GND导通。其中，第二电容Cfly2与第四电容Co串联在电源端与地GND之间，第一电容Cfly1与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly1+Vo，Vo＝Cfly2。综上，可得Vin＝2Vo，Vcfly2＝Vo，Vcfly1＝Vo，由此可以实现2:1的电压比例变换。
在实现1:1降压模式时，第一开关电路31将电源端与第四电容Co的第一端导通，其中，第四电容Co串联在电源端与地GND之间。这样，当***稳定时：Vin＝Vo。由此可以实现1:1的电压比例变换。
综上，该SC电路工作在不同的降压模式时，分别实现了将输入端的电压分别以4:1、2:1、1:1的方式降压在第四电容Co的两端输出，从而实现了多种降压比例的切换。
在一种可能的实现方式中，第一开关电路，包括：第一开关、第二开关、第三开关、第四开关以及第五开关；其中，所述第一开关的第一端连接所述第一开关电路的第一端，所述第一开关的第二端连接所述第一开关电路的第二端，所述第二开关的第一端连接所述第一开关电路的第二端，所述第二开关的第二端连接所述第一开关电路的第四端，所述第四开关的第一端连接所述第一开关电路的第二端，所述第四开关的第二端连接所述第一开关电路的第三端，所述第三开关的第一端连接所述第一开关电路的第四端，所述第三开关的第二端连接所述第一开关电路的第五端，所述第五开关的第一端连接所述第一开关电路的第三端，所述第五开关的第二端连接所述第一开关电路的第五端。其中，在第一降压模式下，在一个周期内的第一时间段，所述第一开关、所述第三开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第一开关、所述第三开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期内所述第四开关处于断开状态；在第二降压模式下，在一个周期内的第一时间段，所述第三开关、所述第四开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第三开关、所述第四开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期内所述第四开关处于断开状态；在一个周期内所述第一开关处于导通状态；在第三降压模式下，所述第一开关、所述第二开关、所述第三开关、所述第四开关、以及第五开关处于导通状态。
在一种可能的实现方式中，所述第二开关电路，包括：第六开关和第七开关；其中，所述第六开关的第一端连接所述第二开关电路的第一端，所述第六开关的第二端连接所述第二开关电路的第二端，所述第七开关的第一端连接所述第二开关电路的第二端，所述第七开关的第二端连接所述第二开关电路的第三端；在第一降压模式下，在一个周期内的第一时间段，所述第六开关处于导通状态，所述第七开关处于断开状态；在一个周期内的第二时间段，所述第六开关处于断开状态，所述第七开关处于导通状态；在第二降压模式下，在一个周期内，所述第六开关和所述第七开关处于断开状态；在第三降压模式下，所述第六开关和所述第七开关处于断开状态。
在一种可能的实现方式中，所述第三开关电路，包括：第八开关和第九开关；其中，第八开关的第一端连接所述第三开关电路的第一端，所述第八开关的第二端连接第三开关电路的第二端，所述第九开关的第一端连接第三开关电路的第二端，所述第九开关的第二端连接所述第三开关电路的第三端；在第一降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；在第二降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；在第三降压模式下，所述第八开关和所述第九开关处于断开状态。
在一种可能的实现方式中，所述第四开关电路，包括：包括第十开关和第十一开关，其中，所述第十开关的第一端连接第四开关电路的第一端，第十开关的第二端连接第四开关电路的第二端，所述第十一开关的第一端连接所述第四开关电路的第二端，所述第十一开关的第二端连接所述第四开关电路的第三端。在第一降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；在第二降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；在第三降压模式下，所述第十开关和所述第十一开关处于断开状态。
这样，在4:1降压模式下，在一个周期内的第一时间段第一开关、第六开关、第十开关处于导通状态，将第三电容、第一电容以及第四电容依次连接为串联关系，形成一条电流路径；第三开关、第九开关处于导通状态，将第二电容和第四电容连接为串联关系，形成另一条电流路径，其他开关断开；在一个周期内的第二时间段内，第二开关、第七开关和第八开关处于导通状态，将第三电容、第二电容以及第四电容依次连接为串联关系，形成一条电流路径；第五开关和第九开关处于导通状态将第一电容和第四电容连接为串联关系，形成另一条电流路径，其他开关断开。则在两个时间段中，均形成了两条电流路径，这样在每个处于导通状态的开关上都只有一条电流流经的电流路径，因此电流在各个开关上的损耗分布均匀，能够有效的提高SC整体的***效率。
而，在2:1降压模式下，在一个周期内的第一时间段第一开关、第四开关、第十开关处于导通状态，将第一电容以及第四电容依次连接为串联关系，形成一条电流路径；第三开关、第九开关处于导通状态，将第二电容和第四电容连接为串联关系，形成另一条电流路径，其他开关断开；在一个周期内的第二时间段内，第一开关、第二开关、第八开关处于导通状态，将第二电容以及第四电容依次连接为串联关系，形成一条电流路径；第五开关和第十一开关处于导通状态将第一电容和第四电容连接为并联关系，形成另一条电流路径，其他开关断开。则在两个时间段中，均形成了两条电流路径，这样在每个处于导通状态的开关上都只有一条电流流经的电流路径，因此电流在各个开关上的损耗分布均匀，能够有效的提高SC整体的***效率。此外，在2:1降压模式下，其中在第一时间段，第一电容与第四电容串联，在第二时间段第一电容 与第二电容串联，构成交错并联结构，为电源端提供了更多的电流路径，能够有效降低功耗。
而，在1:1降压模式下，第一开关、第二开关和第三开关处于导通状态，将第四电容直接与电源端连接形成一条电流路径；第一开关、第四开关和第五开关处于导通状态，将第四电容直接与电源端连接形成另一条电流路径；这样由于第一开关、第二开关和第三开关形成的电流路径与第一开关、第四开关和第五开关形成的电流路径并联在一起，因此降低了第四电路充电路径上的电阻，能够有效降低功耗，提高SC的效率。
在一种可能的实现方式中，各个开关包括一个开关晶体管，或者，各个开关包括并联的两个或多个开关晶体管。其中每个开关也可以采用并联的两个或多个开关晶体管可以降低开关导通时的电阻，进而提高***效率。
第二方面，提供一种芯片，包括：第一开关电路、第二开关电路、第三开关电路、第四开关电路；其中，所述第一开关电路的第一端连接电源端；所述第一开关电路的第二端用于连接第三电容的第一端，所述第一开关电路的第三端连接所述第二开关电路的第一端，所述第一开关电路的第三端还用于连接第一电容的第一端，所述第一开关电路的第四端用于连接第二电容的第一端，所述第一开关电路的第五端连接所述第三开关电路的第一端、所述第四开关电路的第一端，所述第一开关电路的第五端还用于连接第四电容的第一端；所述第二开关电路的第二端用于连接所述第三电容的第二端，所述第二开关电路的第三端连接地；所述第三开关电路的第二端用于连接所述第二电容的第二端，所述第三开关电路的第三端连接地，所述第四开关电路的第二端用于连接所述第一电容的第二端，所述第四开关电路的第三端连接所述地，所述第四电容的第二端连接所述地；在第一降压模式下，所述第一开关电路被配置为将所述电源端与所述第三电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置将所述第三电容的第二端与所述第一电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第三电容的第一端与所述第二电容的第一端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置为将所述第三电容的第二端与所述地导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；在第二降压模式下，所述第一开关电路被配置为将所述电源端与所述第一电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第二电容的第一端与所述电源端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；在第三降压模式下，所述第一开关电路被配置为将所述电源端与所述第四电容的第一端导通。
在一种可能的实现方式中，所述第一开关电路，包括：第一开关、第二开关、第三开关、第四开关以及第五开关；其中，所述第一开关的第一端连接所述第一开关电路的第一端，所述第一开关的第二端连接所述第一开关电路的第二端，所述第二开关的第一端连接所述第一开关电路的第二端，所述第二开关的第二端连接所述第一开关电路的第四端，所述第四开关的第一端连接所述第一开关电路的第二端，所述第四开关的第二端连接所述第一开关电路的第三端，所述第三开关的第一端连接所述第一开关电路的第四端，所述第三开关的第二端连接所述第一开关电路的第五端，所述第五开关的第一端连接所述第一开关电路的第三端，所述第五开关的第二端连接所述第一开关电路的第五端；其中，在第一降压模式下，在一个周期内的第一时间段，所述第一开关、所述第三开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第一开关、所述第三开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期内所述第四开关处于断开状态；在第二降压模式下，在一个周期内的第一时间段，所述第三开关、所述第四开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第三开关、所述第四开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期所述第四开关处于断开状态；在一个周期内所述第一开关处于导通状态；在第三降压模式下，所述第一开关、所述第二开关、所述第三开关、所述第四开关、以及第五开关处于导通状态。
在一种可能的实现方式中，所述第二开关电路，包括：第六开关和第七开关；其中，所述第六开关的第一端连接所述第二开关电路的第一端，所述第六开关的第二端连接所述第二开关电路的第二端，所述第七开关的第一端连接所述第二开关电路的第二端，所述第七开关的第二端连接所述第二开关电路的第三端；在第一降压模式下，在一个周期内的第一时间段，所述第六开关处于导通状态，所述第七开关处于断开状态；在一个周期内的第二时间段，所述第六开关处于断开状态，所述第七开关处于导通状态；在第二降压模式下，所述第六开关和所述第七开关处于断开状态；在第三降压模式下，所述第六开关和所述第七开关处于断开状态。
在一种可能的实现方式中，所述第三开关电路，包括：第八开关和第九开关；其中，第八开关的第一端连接所述第三开关电路的第一端，所述第八开关的第二端连接第三开关电路的第二端，所述第九开关的第一端连接第三开关电路的第二端，所述第九开关的第二端连接所述第三开关电路的第三端；在第一降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；在第二降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；在第三降压模式下，所述第八开关和所述第九开关处于断开状态。
在一种可能的实现方式中，所述第四开关电路，包括：第十开关和第十一开关，其中，所述第十开关的第一端连接第四开关电路的第一端，第十开关的第二端连接第四开关电路的第二端，所述第十一开关的第一端连接所述第四开关电路的第二端，所述第十一开关的第二端连接所述第四开关电路的第三端；在第一降压模式下，在一个 周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；在第二降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；在第三降压模式下，所述第十开关和所述第十一开关处于断开状态。
在一种可能的实现方式中，各个开关包括一个开关晶体管，或者，各个开关包括并联的两个或多个开关晶体管。
其中，第二方面实现的技术效果可以参考第一方面或任意一种可能的实现方式中的描述，此处不再赘述。
第三方面，提供一种电子设备，包括如第一方面或其任意一种可能的实现方式中所述的SC，或者包括如第二方面或其任意一种可能的实现方式中所述的芯片。
其中，第三方面实现的技术效果可以参考第一方面或任意一种可能的实现方式中的描述，此处不再赘述。
在一种可能的实现方式中，还包括无线充电线圈、接收电路以及电池；所述无线充电线圈连接所述接收电路，所述接收电路连接所述SC或所述芯片的电源端，所述电池与所述第四电容并联。这样实现了无线充电方式。
在一种可能的实现方式中，还包括USB接口以及电池；所述USB接口连接所述SC或所述芯片的电源端，所述电池与所述第四电容并联。这样实现了有线充电方式。
在一种可能的实现方式中，所述USB接口与所述SC或所述芯片的电源端之间还设置有过压保护防护电路，其中所述过压保护防护电路用于检测到接入USB接口的电压超过阈值电压时，将所述SC或所述芯片的电源端与所述USB接口的连接切断。这样，避免了USB接口接收的电压过高时对SC电路或所述芯片以及电池造成损坏。
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图1为本申请的实施例提供的一种电子设备的结构示意图；
图2为本申请的实施例提供的一种SC的连接关系示意图；
图3为本申请的实施例提供的一种SC的结构示意图；
图4为本申请的实施例提供的一种SC的等效电路一；
图5为本申请的实施例提供的一种SC的等效电路二；
图6为本申请的实施例提供的一种SC的等效电路三；
图7为本申请的实施例提供的一种SC的等效电路四；
图8为本申请的实施例提供的一种SC的等效电路五；
图9为本申请的另一实施例提供的一种SC的结构示意图；
图10为本申请的实施例提供的一种SC的各个开关的控制信号示意图一：
图11为本申请的实施例提供的一种SC的电流走向示意图一；
图12为本申请的实施例提供的一种SC的电流走向示意图二；
图13为本申请的另一实施例提供的一种SC的结构示意图；
图14为本申请的实施例提供的一种SC的各个开关的控制信号示意图二：
图15为本申请的实施例提供的一种SC的电流走向示意图三；
图16为本申请的实施例提供的一种SC的等效电路六；
图17为本申请的实施例提供的一种SC的电流走向示意图四；
图18为本申请的实施例提供的一种SC的等效电路七；
图19为本申请的又一实施例提供的一种SC的结构示意图；
图20为本申请的实施例提供的一种SC的各个开关的控制信号示意图三：
图21为本申请的实施例提供的一种SC的电流走向示意图五；
图22为本申请的实施例提供的一种SC的等效电路八；
图23为本申请的实施例提供的一种SC的电流走向示意图六；
图24为本申请的实施例提供的一种SC的等效电路九；
图25为本申请的实施例提供的一种SC的各个开关的控制信号示意图四：
图26为本申请的实施例提供的一种SC的电流走向示意图七；
图27为本申请的实施例提供的一种SC的电流走向示意图八；
图28为本申请的实施例提供的一种SC的各个开关的控制信号示意图五：
图29为本申请的实施例提供的一种SC的电流走向示意图九；
图30为本申请的实施例提供的一种SC的等效电路十；
图31为本申请的实施例提供的一种SC的电流走向示意图十；
图32为本申请的实施例提供的一种SC的等效电路十一；
图33为本申请的实施例提供的一种SC的各个开关的控制信号示意图六：
图34为本申请的实施例提供的一种SC的电流走向示意图十一；
图35为本申请的实施例提供的一种SC的等效电路十二；
图36为本申请的实施例提供的一种SC的电流走向示意图十二；
图37为本申请的实施例提供的一种SC的等效电路十三；
图38为本申请的实施例提供的一种SC的电流走向示意图十三；
图39为本申请的实施例提供的一种SC的电流走向示意图十四；
图40为本申请的实施例提供的一种SC的电流走向示意图十五；
图41为本申请的实施例提供的一种芯片的结构示意图。
具体实施方式
下面将结合附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括
(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、
“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、 材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例提供的一种SC可应用于手机、平板电脑、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、手持计算机、上网本、个人数字助理(personal digital assistant，PDA)、可穿戴电子设备、虚拟现实设备等电子设备中，本申请实施例对此不做任何限制。
示例性的，图1示出了电子设备100的结构示意图。
电子设备100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，摄像头193以及显示屏194等。
可以理解的是，本发明实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了***的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器(或者适配器)。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过电子设备100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为电子设备供电。具体的，参照图2所示，充电管理模块140具体可以通过过压保护(over voltage protection，OVP)防护电路131连接USB接口130，其中，当OVP防护电路131检测到接入USB接口130的电压过高(超过阈值电压)时，可以主动将充电管理模块140与USB接口130的连接切断。又例如，参照图2所示，充电管理模块140具体通过接收电路(receive integrated circuit，Rx IC)133连接无线充电线圈132。此外为了实现对电池的普通充电或快速充电，参照图2所示，充电管理模块140可以包括用于为电池进行快速充电的SC以及用于为电池进行普通正常充电的降压转换电路(例如BUCK)，SC以及BUCK通过OVP防护电路131连接USB接口130，并且通过Rx IC133连接无线充电线圈132。处理器110或者充电管理模块140可以根据充电协议检测BUCK或者SC为电池充电，通常SC以及BUCK为固定降压比例的降压转换电路，例如根据充电协议检测到SC以及BUCK输入侧的电压为5V时，控制BUCK将5V的电压转换为比电池电压稍高的电压2V后为电池充电，或者，根据充电协议检测到SC以及BUCK输入侧的电压为20V时，确定此时为快速充电场景，则控制SC将20V的电压转换为电池电压附近的电压后为电池充电。当然，当电池电压或者容量上升至一定阶段，或热耗过大充电功率时，需要控制适配器或者无线充电器下降切换至较低的充电功率(例如40W)，适配器或者无线充电器向SC输出的电压会降至10V附近，此时为了维持原先的充电电流，以保持快速充电，充电协议会控制SC以2:1的降压模式将输入的10V电压降至5V附近继续给电池充电；当然，充电协议控制适配器或者无线充电器进一步降低电压时，需要控制SC进一步切换降压模式，以保证输出的电压持续维持在5V左右，以此确保快速充电的效果。在下述的示例中主要对SC的具体结构展开说明。
电源管理模块141用于连接电池142，充电管理模块140与处理器110。电源管理模块141接收电池142和/或充电管理模块140的输入，为处理器110，内部存储器121，显示屏194，摄像头193，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于处理器110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
电子设备100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。电子设备100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括一个或多个滤波器，开关，功率放大器， 低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于处理器110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与处理器110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A，受话器170B等)输出声音信号，或通过显示屏194显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(Bluetooth，BT)，全球导航卫星***(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成一个或多个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，电子设备100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。所述无线通信技术可以包括全球移动通讯***(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term eVolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。所述GNSS可以包括全球卫星定位***(global positioning system，GPS)，全球导航卫星***(global navigation satellite system，GLONASS)，北斗卫星导航***(beidou navigation satellite system，BDS)，准天顶卫星***(quasi-zenith satellite system，QZSS)和/或星基增强***(satellite based augmentation systems，SBAS)。
电子设备100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏194用于显示图像，视频等。显示屏194包括显示面板。显示面板可以采 用液晶显示屏(liquid crystal display，LCD)，有机发光二极管(organic light-emitting diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode的，AMOLED)，柔性发光二极管(flex light-emitting diode，FLED)，Miniled，MicroLed，Micro-oLed，量子点发光二极管(quantum dot light emitting diodes，QLED)等。在一些实施例中，电子设备100可以包括1个或N个显示屏194，N为大于1的正整数。
电子设备100可以通过ISP，摄像头193，视频编解码器，GPU，显示屏194以及应用处理器等实现拍摄功能。
ISP用于处理摄像头193反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将所述电信号传递给ISP处理，转化为肉眼可见的图像。ISP还可以对图像的噪点，亮度，肤色进行算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头193中。
摄像头193用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(charge coupled device，CCD)或互补金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像信号。ISP将数字图像信号输出到DSP加工处理。DSP将数字图像信号转换成标准的RGB，YUV等格式的图像信号。在一些实施例中，电子设备100可以包括1个或N个摄像头193，N为大于1的正整数。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备100的存储能力。外部存储卡通过外部存储器接口120与处理器110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储一个或多个计算机程序，该一个或多个计算机程序包括指令。处理器110可以通过运行存储在内部存储器121的上述指令，从而使得电子设备100执行本申请一些实施例中所提供的方法，以及各种功能应用和数据处理等。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作***；该存储程序区还可以存储一个或多个应用程序(比如图库、联系人等)等。存储数据区可存储电子设备101使用过程中所创建的数据(比如照片，联系人等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如一个或多个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。在另一些实施例中，处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，来使得电子设备100执行本申请实施例中提供的方法，以及各种功能应用和数据处理。
电子设备100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。在一些实施例中，音频模块170可以设置于处理器110中，或将音频模块170的部分功能模 块设置于处理器110中。
扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。电子设备100可以通过扬声器170A收听音乐，或收听免提通话。
受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。当电子设备100接听电话或语音信息时，可以通过将受话器170B靠近人耳接听语音。
麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风170C发声，将声音信号输入到麦克风170C。电子设备100可以设置一个或多个麦克风170C。在另一些实施例中，电子设备100可以设置两个麦克风170C，除了采集声音信号，还可以实现降噪功能。在另一些实施例中，电子设备100还可以设置三个，四个或更多麦克风170C，实现采集声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口170D用于连接有线耳机。耳机接口170D可以是USB接口130，也可以是3.5mm的开放移动电子设备平台(open mobile terminal platform，OMTP)标准接口，美国蜂窝电信工业协会(cellular telecommunications industry association of the USA，CTIA)标准接口。
传感器模块180可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器，加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感器，环境光传感器，骨传导传感器等。
另外，上述电子设备中还可以包括按键190、马达191、指示器192以及用户标识模块(subscriber identification module，SIM)卡接口195等一种或多种部件，本申请实施例对此不做任何限制。
基于上述的电子设备，本申请的实施例提供一种SC，参照图3所示，包括：第一开关电路31、第二开关电路32、第三开关电路33、第四开关电路34以及第一电容Cfly1、第二电容Cfly2、第三电容Cfly3以及第四电容Co。其中，第一开关电路31的第一端连接电源端，该电源端通过USB接口连接电源适配器，或者连接无线充电电路，以向该Sc提供输入电压Vin；第一开关电路31的第二端连接第三电容Cfly3的第一端，第一开关电路31的第三端连接第二开关电路32的第一端、以及第一电容fly1的第一端，第一开关电路31的第四端连接第二电容Cfly的第一端，第一开关电路31的第五端连接第三开关电路33的第一端、第四开关电路33的第一端以及第四电容Co的第一端；第三电容Cfly3的第二端连接第二开关电路32的第二端，第二开关电路32的第三端连接地GND；第二电容Cfly2的第二端连接第三开关电路33的第二端，第三开关电路33的第三端连接地GND，第一电容Cfly1的第二端连接第四开关电路34的第二端，第四开关电路34的第三端连接地GND，第四电容Co的第二端连接地GND。其中，在该方案中，第一电容Cfly1、第二电容Cfly2以及电三电容Cfly3是飞跨电容，第四电容Co作为输出电容(output capacitance)，其两端的电压向负载RL(其中在手机场景下，负载指电池)提供稳定的供电电压。
其中，在第一降压模式下，第一开关电路31被配置为将电源端与第三电容Cfly3的第一端导通，将第二电容Cfly2的第一端与第四电容Co的第一端导通；第二开关电路32被配置为将第三电容Cfly3的第二端与第一电容Cfly1的第一端导通；第三开 关电路33被配置为将第二电容Cfly2的第二端与地GND导通；第四开关电路34被配置为将第一电容Cfly1的第二端与第四电容Co的第一端导通。或者，第一开关电路31被配置为将第三电容Cfly3的第一端与第二电容Cfly2的第一端导通，将第一电容Cfly1的第一端与第四电容Co的第一端导通；第二开关电路32被配置为将第三电容Cfly3的第二端与地GND导通；第三开关电路33被配置为将第二电容Cfly2的第二端与第四电容Co的第一端导通；第四开关电路34被配置为将第一电容Cfly1的第二端与地GND导通。
在第二降压模式下，第一开关电路31被配置为将电源端与第一电容Cfly1的第一端导通，将第二电容Cfly2的第一端与第四电容Co的第一端导通；第三开关电路33被配置为将第二电容Cfly2的第二端与地GND导通；第四开关电路34被配置为将第一电容Cfly1的第二端与第四电容Co的第一端导通。或者，第一开关电路31被配置为将第二电容Cfly2的第一端与电源端导通，将第一电容Cfly1的第一端与第四电容Co的第一端导通；第三开关电路33被配置为将第二电容Cfly2的第二端与第四电容Co的第一端导通，第四开关电路34被配置为将第一电容Cfly1的第二端与地GND导通。
在第三降压模式下，第一开关电路31被配置为将电源端与第四电容Co的第一端导通。
这样在实现4:1降压模式时，在一个时间周期的第一时间段，第一开关电路31将电源端与第三电容Cfly3的第一端导通，将第二电容Cfly2的第一端与第四电容Co的第一端导通；第二开关电路32将第三电容Cfly3的第二端与第一电容Cfly1的第一端导通；第三开关电路33将第二电容Cfly2的第二端与地GND导通；第四开关电路34将第一电容Cfly1的第二端与第四电容Co的第一端导通，从而将各个电容连接成如图4所示的等效电路，其中，第三电容Cfly3、第一电容Cfly1以及第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND；第二电容Cfly2与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly3+Vcfly1+Vo，Vcfly2＝Vo；其中Vcfly3为第三电容Cfly3两端的电压，Vcfly1为第一电容Cfly1两端的电压，V0为第四电容Co两端的电压。在一个周期的第二时间段，第一开关电路31将第三电容Cfly3的第一端与第二电容Cfly2的第一端导通，将第一电容Cfly1的第一端与第四电容Co的第一端导通，第二开关电路32将第三电容Cfly3的第二端与地GND导通，第三开关电路33将第二电容Cfly2的第二端与第四电容Co的第一端导通，第四开关电路将第一电容Cfly1的第二端与地GND导通，从而将各个电容连接成如图5所示的等效电路，其中第一电容Cfly1与第四电容Co并联，第二电容Cfly2与第三电容Cfly3的串联结构与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vcfly3＝Vcfly2+Vo，Vcfly2为第二电容Cfly2两端的电压。综上，可得Vin＝4Vo，Vcfly3＝2Vo，Vcfly2＝Vo，Vcfly1＝Vo，由此可以实现4:1的电压比例变换。
在实现2:1降压模式时，在一个周期的第一时间段，第一开关电路31将电源端与第一电容Cfly1的第一端导通，将第二电容Cfly2的第一端与第四电容Co的第一端导通；第三开关电路33将第二电容Cfly2的第二端与地GND导通；第四开关电路34将第一电容Cfly1的第二端与第四电容Co的第一端导通。从而将各个电容连接成如图6 所示的等效电路，其中，第一电容Cfly1与第四电容Co串联在电源端与地GND之间，第二电容Cfly2与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly1+Vo，Vo＝Cfly2。在一个周期的第二时间段，第一开关电路31将电源端与第二电容Cfly2的第一端导通，将第一电容Cfly1的第一端与第四电容Co的第一端导通，第三开关电路33将第二电容Cfly2的第二端与第四电容Co的第一端导通，第四开关电路34将第一电容Cfly1的第二端与地GND导通。从而将各个电容连接成如图7所示的等效电路，其中，第二电容Cfly2与第四电容Co串联在电源端与地GND之间，第一电容Cfly1与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly2+Vo，Vo＝Cfly1。综上，可得Vin＝2Vo，Vcfly2＝Vo，Vcfly1＝Vo，由此可以实现2:1的电压比例变换。
在实现1:1降压模式时，第一开关电路31将电源端与第四电容Co的第一端导通，从而将各个电容连接成如图8所示的等效电路，其中，第四电容Co串联在电源端与地GND之间，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vo。由此可以实现1:1的电压比例变换。
综上，该SC电路工作在不同的降压模式时，分别实现了将输入端的电压分别以4:1、2:1、1:1的方式降压在第四电容Co的两端输出，从而实现了多种降压比例的切换。
结合图9所示，第一开关电路31包括开关Q1、Q2、Q3、Qadd以及Q8；其中，开关Q1的第一端连接第一开关电路31的第一端，开关Q1的第二端连接第一开关电路31的第二端，开关Q2的第一端连接第一开关电路31的第二端，开关Q2的第二端连接第一开关电路31的第四端，开关Qadd的第一端连接第一开关电路31的第二端，开关Qadd的第二端连接第一开关电路31的第三端，开关Q3的第一端连接第一开关电路31的第四端，开关Q3的第二端连接第一开关电路31的第五端，开关Q8的第一端连接第一开关电路31的第三端，开关Q8的第二端连接第一开关电路31的第五端。
第二开关电路32包括开关Q6和Q7，其中开关Q6的第一端连接第二开关电路32的第一端，开关Q6的第二端连接第二开关电路32的第二端，开关Q7的第一端连接第二开关电路32的第二端，开关Q7的第二端连接第二开关电路32的第三端。
第三开关电路33包括开关Q4和Q5，其中开关Q4的第一端连接第三开关电路33的第一端，开关Q4的第二端连接第三开关电路33的第二端，开关Q5的第一端连接第三开关电路33的第二端，开关Q5的第二端连接第三开关电路33的第三端。
第四开关电路34包括开关Q9和Q10，其中开关Q9的第一端连接第四开关电路34的第一端，开关Q9的第二端连接第四开关电路34的第二端，开关Q10的第一端连接第四开关电路34的第二端，开关Q10的第二端连接第四开关电路34的第三端。
其中，上述的开关Q1-Q10以及Qadd均包括控制端，在其控制端的控制之下，开关可以将其两端在导通或断开状态之间切换。通常，开关可以采用开关晶体管(简称开关管或晶体管)，在本申请的实施例中开关晶体管可以采用金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。此外，在图9示出的示例中，每个开关用一个开关晶体管实现，可以理解的是为了降低开关导通时的电阻，每个开关也可以采用并联的两个或多个开关晶体管。在本申请的实施例中， 开关晶体管分为N(negative，负)型晶体管和P(positive，正)型晶体管两种类型。开关晶体管包括源极(source)、漏极(drain)以及栅极(gate)，通过控制输入开关晶体管栅极的电平可以控制开关晶体管的导通(开启)或断开(关闭、截止、断路)。开关晶体管在开启时，源极和漏极导通，产生开启电流，并且，在晶体管的栅极电平不同时，源极与漏极之间产生的开启电流的大小也不同；开关晶体管在关闭时，源极和漏极不会导通，不会产生电流。在本申请的实施例中，开关晶体管的栅极也被称为控制端，源极被称为第一端，漏极被称为第二端；或者，栅极被称为控制端，漏极被称为第一端，源极被称为第二端。此外，N型晶体管在控制端的电平为高电平时开启，第一端和第二端导通，第一端和第二端之间产生开启电流；N型晶体管在控制端的电平为低电平时关闭，第一端和第二端不导通，不产生电流。P型晶体管在控制端的电平为低电平时开启，第一端和第二端导通，产生开启电流；P型晶体管在控制端的电平为高电平时关闭，第一端和第二端不导通，不产生电流。以下方案中的开关所采用的开关晶体管均可以参照此处的描述。
此外，图10提供了在4：1降压模式下，一个时间周期T中，图9中各个开关的控制信号的时序图。其中，以各个开关在高电平时导通，低电平时断开为例，开关Qadd(在S3的控制下)在整个时间周期T内都处于断开状态。在一个时间周期T的第一时间段t1，参照图11所示，开关Q1、Q3、Q5、Q6以及Q9在S1的控制下处于导通状态，开关Q2、Q4、Q7、Q8以及Q10在S2的控制下处于断开状态，将各个电容连接形成图4所示的等效电路；第二时间段t2，参照图12所示，开关Q1、Q3、Q5、Q6以及Q9在S1的控制下处于断开状态，开关Q2、Q4、Q7、Q8以及Q10在S2的控制下处于导通状态，将各个电容连接形成图5所示的等效电路；由此可以实现4:1的电压比例变换。其中，本申请的各个实施例中以控制信号为逻辑高电平(H)时处于导通状态，以控制信号为逻辑低电平(L)时处于断开状态为例进行说明。
参照图13所示，还提供了一种典型的基于迪克森(Dickson)架构的SC，其包括Q1-Q8，八个开关，以及四个电容Cfly1、Cfly1、Cfly3以及Co。其中，开关Q1、Q2、Q3、Q4以及电容Co依次串联于电源端(提供供电电压Vin)与地GND之间，开关Q5、Q6的串联结构与电容Co并联，开关Q8与Q7的串联结构与电容Co并联，开关Q2、Q3、Q4、Q5的串联结构与电容Cfly3并联，开关Q4与Q5的串联结构与电容Cfly1并联，开关Q3、Q4、Q8的串联结构与电容Cfly2并联，电容Co两端输出的电压向负载RL供电。
此外，图14提供了在4：1降压模式下，一个时间周期T中，图13中各个开关的控制信号的时序图。其中，以各个开关在高电平时导通，低电平时断开为例，则在一个时间周期T的第一时间段t1，参照图15所示，开关Q1、Q3、Q5、Q7在S1的控制下处于导通状态，开关Q2、Q4、Q6、Q8在S2的控制下处于断开状态，将各个电容连接形成图16所示的等效电路；其中，第三电容Cfly3与第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND；第一电容Cfly1与第四电容Co形成的串联结构与第二电容Cfly2并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly3+Vo，Vcfly2＝Vcfly1+Vo。第二时间段t2，参照图17所示，开关Q1、Q3、Q5、Q7在S1的控制下处于断开状态，开关Q2、Q4、Q7、Q8在 S2的控制下处于导通状态，将各个电容连接形成图18所示的等效电路；其中，第一电容Cfly1与第四电容CO形成串联结构，第二电容Cfly2与第四电容CO形成的串联结构与第三电容Cfly3并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vcfly3＝Vcfly2+Vo，Vcfly1＝Vo；综上可得Vin＝4Vo，Vcfly3＝3Vo，Vcfly2＝2Vo，Vcfly1＝Vo，由此可以实现4:1的电压比例变换。
其中，结合图10-图12中对图9提供的SC在4:1降压模式下的电路分析，以及图14-图18对图13提供的SC在4：1降压模式下的电路分析，可以看出，两者在4:1降压模式下，由于图13提供的SC在t1时间段所有电流都要通过开关Q5(参照图15所示)、并且在t2时间段所有电流流经的路径都要通过开关Q6(参照图17所示)，因此导致Q5与Q6具有更大的电流损耗，尤其在大电流场景下会产生大量的热量，造成效率低下，而图9提供的SC中每个开关都只通过一条电流流经的路径，因此电流在各个开关上的损耗分布均匀，相对于图13提供的SC有效的提高了整体的***效率。此外，图13提供的SC在4:1降压模式下Cfly3需要满足具有Vcfly3＝3Vo的耐压值，而图9提供的SC对Cfly3的耐压值要求在Vcfly3＝2Vo。而Cfly3需使用的耐压越高，电容单位体积能量密度越低，降低了转换的功率密度。
参照图19所示，还提供了另一种典型的基于迪克森(Dickson)架构的SC，其包括Q1-Q10，十个开关，以及四个电容Cfly1、Cfly1、Cfly3以及Co。其中，开关Q1、Q2、Q3以及电容Co依次串联于电源端(提供供电电压Vin)与地GND之间，开关Q4、Q5的串联结构与电容Co并联，开关Q8、Q6以及Q7的串联结构与电容Co并联，开关Q9、Q10的串联结构与电容Co并联，开关Q2、Q3、Q8、Q6的串联结构与电容Cfly3并联，开关Q3、Q4的串联结构与电容Cfly2并联，开关Q8与Q9的串联结构与电容Cfly1并联，电容Co两端输出的电压向负载RL供电。
此外，图20提供了在4：1降压模式下，一个时间周期T中，图19中各个开关的控制信号的时序图。其中，以各个开关在高电平时导通，低电平时断开为例，则在一个时间周期T的第一时间段t1，参照图21所示，开关Q1、Q3、Q5、Q6、Q9在S1的控制下处于导通状态，开关Q2、Q4、Q7、Q8、Q10在S2的控制下处于断开状态，将各个电容连接形成图22所示的等效电路；其中，第三电容Cfly3、第一电容Cfly1以及第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND；第二电容Cfly2与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly3+Vcfly1+Vo，Vcfly2＝Vo；第二时间段t2，参照图23所示，开关Q1、Q3、Q5、Q6、Q9在S1的控制下处于断开状态，开关Q2、Q4、Q7、Q8、Q10在S2的控制下处于导通状态，将各个电容连接形成图24所示的等效电路；其中第一电容Cfly1与第四电容Co并联，第二电容Cfly2与第三电容Cfly3的串联结构与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vcfly3＝Vcfly2+Vo，Vcfly2为电容Cfly2两端的电压，综上，可得Vin＝4Vo，Vcfly3＝2Vo，Vcfly2＝Vo，Vcfly1＝Vo，由此可以实现4:1的电压比例变换。
其中，结合图10-图12中对图9提供的SC在4:1降压模式下的电路分析，以及图20-图24对图19提供的SC在4：1降压模式下的电路分析，可以看出本申请的实施例中图9提供的SC在4：1降压模式下至少可以取得等同于图19提供的SC的效果。
图25提供了在2：1降压模式下，一个时间周期T中，图9中各个开关的控制信号的时序图。其中，以各个开关在高电平时导通，低电平时断开为例，开关Q6、Q7(在S3的控制下)在整个时间周期T内都处于断开状态，Q1(在S4的控制下)在整个时间周期T内都处于导通状态。在一个时间周期T的第一时间段t1，参照图26所示，开关Qadd、Q3、Q5以及Q9在S1的控制下处于导通状态，开关Q2、Q4、Q8以及Q10在S2的控制下处于断开状态，将各个电容连接形成图6所示的等效电路；第二时间段t2，参照图27所示，开关Qadd、Q3、Q5以及Q9在S1的控制下处于断开状态，开关Q2、Q4、Q8以及Q10在S2的控制下处于导通状态，将各个电容连接形成图7所示的等效电路；由此可以实现2:1的电压比例变换。
此外，图28提供了在2：1降压模式下，一个时间周期T中，图13中各个开关的控制信号的时序图。其中，以各个开关在高电平时导通，低电平时断开为例，其中开关Q2和Q3(在S3的控制下)在整个时间周期T内均处于导通状态。在一个时间周期T的第一时间段t1，参照图29所示，开关Q1、Q5、Q8在S1的控制下处于导通状态，开关Q4、Q6、Q7在S2的控制下处于断开状态，将各个电容连接形成图30所示的等效电路；其中，第三电容Cfly3与第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND；第二电容Cfly2与第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND，第一电容Cfly1与第四电容Co形成串联结构，并且该串联结构的两端分别连接电源端以及接地端GND。电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly1+Vo，Vcfly1＝Vcfly2＝Vcfly3。第二时间段t2，参照图31所示，开关Q1、Q5、Q8在S1的控制下处于断开状态，开关Q4、Q6、Q7在S2的控制下处于导通状态，将各个电容连接形成图32所示的等效电路；其中，第一电容Cfly1、第二电容Cfly2以及第三电容Cfly3均与与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vcfly3＝Vcfly2＝cfly1＝Vo；综上可得Vin＝2Vo，Vcfly3＝Vo，Vcfly2＝Vo，Vcfly1＝Vo，由此可以实现2:1的电压比例变换。
其中，结合图25-图27中对图9提供的SC在2:1降压模式下的电路分析，以及图28-图32对图13提供的SC在2：1降压模式下的电路分析，可以看出，两者在2:1降压模式下，由于图13提供的SC在t1时间段所有电流都要通过开关Q5(参照图29所示)、并且在t2时间段所有电流流经的路径都要通过开关Q6(参照图31所示)，因此导致Q5与Q6具有更大的电流损耗，尤其在大电流场景下会产生大量的热量，造成效率低下，而图9提供的SC中每个开关都只通过一条电流流经的路径，因此电流在各个开关上的损耗分布均匀，相对于图13提供的SC有效的提高了整体的***效率。
此外，图33提供了在2：1降压模式下，一个时间周期T中，图19中各个开关的控制信号的时序图。其中，以各个开关在高电平时导通，低电平时断开为例，其中Q6-Q10(在S3的控制下)在整个时间周期T内都处于断开状态，Q1(在S4的控制下)在整个时间周期T内都处于导通状态。在一个时间周期T的第一时间段t1，参照图34所示，开关Q2、Q4在S1的控制下处于导通状态，开关Q3、Q5在S2的控制下处于断开状态，将各个电容连接形成图35所示的等效电路；其中，第三电容Cfly3、第一电容Cfly1从电路中断开；第二电容Cfly2以及第四电容Co形成串联结构，并且该串联 结构的两端分别连接电源端以及接地端GND，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vin＝Vcfly2+Vo；第二时间段t2，参照图36所示，开关Q2、Q4在S1的控制下处于断开状态，开关Q3、Q5在S2的控制下处于导通状态，将各个电容连接形成图37所示的等效电路；其中第三电容Cfly3、第一电容Cfly1从电路中断开；第二电容Cfly2与第四电容Co并联，电流流向如图中虚线箭头示出的方向。这样，当***稳定时：Vcfly2＝Vo，综上，可得Vin＝2Vo，Vcfly2＝Vo，由此可以实现2:1的电压比例变换。
其中，结合图25-图27中对图9提供的SC在2:1降压模式下的电路分析，以及图33-图37对图19提供的SC在2：1降压模式下的电路分析，图19提供的SC在2:1降压模式下只用到了一个飞跨电容Cfly2，在该结构中，电源端提供的所有电流都只有一条电流路径；而在图9提供的SC在2:1降压模式下，通过增加一个开关Qadd后，可以利用更多的飞跨电容(Cfly1和Cfly2)，其中在t1时间段，电容Cfly1与电容Co串联，在t2时间段电容Cfly1与电容Co并联，构成交错并联结构。为电源端提供了更多的电流路径，这样相对于图19提供的方案能够有效降低功耗。
在1：1降压模式下，对于图9示出的SC，在整个时间周期控制开关Q1、Q2、Q3、Qadd以及Q8导通，控制其他开关Q4-Q7、Q9、Q10断开，如图38所示；这样，将各个电容连接形成图8所示的等效电路；由此可以实现1:1的电压比例变换。对于图13示出的SC，在整个时间周期控制开关Q1、Q2、Q3以及Q4导通，其他开关Q5-Q8关断，如图39所示；这样，可以将各个电容连接形成图8所示的等效电路；由此可以实现1:1的电压比例变换。对于图19示出的SC，在整个时间周期控制开关Q1、Q2、Q3导通，其他开关Q4-Q10以及Qadd关断，如图40所示；这样，可以将各个电容连接形成图8所示的等效电路；由此可以实现1:1的电压比例变换。虽然上述图9、图13以及图19提供的SC在1:1降压模式下的形成的电容连接的等效电路相同，但是参照图38-图40可以看出，在图38中，由于增加了Qadd，在Q2、Q3、Qadd以及Q8导通时，Q2与Q3的串联结构以及Qadd与Q8的串联结构并联在一起可以降低电流路径上的电阻；而图39的电流路径上开关Q1、Q2、Q3以及Q4直接与电容Co串联，图40的电流路径上开关Q1、Q2、Q3直接与电容Co串联，因此存在较大的电阻，因此，图9提供的SC具有更高的效率。
综上，图9提供的SC可以实现4:1、2:1以及1:1多种降压模式，并且相对于现有的两种基于迪克森(Dickson)架构的SC(图13以及图19提供的SC)具有更高的效率。
此外，结合图41所示，提供一种芯片30，其中该芯片30，包括：第一开关电路31、第二开关电路32、第三开关电路33、第四开关电路34。与图3提供的SC电路的区别在于，由于电容需要通过大尺寸的极板实现，不利于集成到芯片上。因此，图3提供的SC可以通过图41提供的芯片30以及设置于芯片30***的PCB上的电容连接形成。具体的，参照图41提供的该芯片30的封装结构中，包括：第一开关电路31、第二开关电路32、第三开关电路33、第四开关电路34，其中芯片30还包括P1-P10一共10个芯片引脚(pin)。第一开关电路31的第一端通过P1连接电源端Vin；第一开关电路31的第二端用于通过P2连接第三电容Cfly3的第一端，第一开关电路31 的第三端连接第二开关电路31的第一端，第一开关电路31的第三端还用于通过P7连接第一电容Cfly1的第一端，第一开关电路31的第四端用于通过P5连接第二电容Cfly2的第一端，第一开关电路31的第五端连接第三开关电路33的第一端、第四开关电路34的第一端，第一开关电路31的第五端还用于通过P9连接第四电容Co的第一端；第二开关电路32的第二端用于通过P3连接第三电容Cfly3的第二端，第二开关电路32的第三端通过P10连接地GND；第三开关电路33的第二端用于通过P6连接第二电容Cfly2的第二端，第三开关电路33的第三端通过P10连接地GND，第四开关电路34的第二端用于通过P8连接第一电容Cfly1的第二端，第四开关电路34的第三端通过P10连接地GND，第四电容Co的第二端连接地GND。此外，在该芯片中第一开关电路31、第二开关电路32、第三开关电路33、第四开关电路34的内部结构及工作原理可以参照上述各个实施例中的详细描述，此处不再赘述。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看附图、公开内容、以及所附权利要求书，可理解并实现所公开实施例的其它变化。在权利要求中，“包括”一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
以上已经描述了本申请的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (16)

  1. 一种开关电容电路SC，其特征在于，包括：第一开关电路、第二开关电路、第三开关电路、第四开关电路以及第一电容、第二电容、第三电容以及第四电容；
    其中，所述第一开关电路的第一端连接电源端；所述第一开关电路的第二端连接所述第三电容的第一端，所述第一开关电路的第三端连接所述第二开关电路的第一端、以及所述第一电容的第一端，所述第一开关电路的第四端连接所述第二电容的第一端，所述第一开关电路的第五端连接所述第三开关电路的第一端、所述第四开关电路的第一端以及所述第四电容的第一端；所述第三电容的第二端连接所述第二开关电路的第二端，所述第二开关电路的第三端连接地；所述第二电容的第二端连接所述第三开关电路的第二端，所述第三开关电路的第三端连接地，所述第一电容的第二端连接所述第四开关电路的第二端，所述第四开关电路的第三端连接所述地，所述第四电容的第二端连接所述地；
    在第一降压模式下，所述第一开关电路被配置为将所述电源端与所述第三电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置将所述第三电容的第二端与所述第一电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第三电容的第一端与所述第二电容的第一端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置为将所述第三电容的第二端与所述地导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；
    在第二降压模式下，所述第一开关电路被配置为将所述电源端与所述第一电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第二电容的第一端与所述电源端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；
    在第三降压模式下，所述第一开关电路被配置为将所述电源端与所述第四电容的第一端导通。
  2. 根据权利要求1所述的SC，其特征在于，所述第一开关电路，包括：第一开关、第二开关、第三开关、第四开关以及第五开关；其中，所述第一开关的第一端连接所述第一开关电路的第一端，所述第一开关的第二端连接所述第一开关电路的第二端，所述第二开关的第一端连接所述第一开关电路的第二端，所述第二开关的第二端连接所述第一开关电路的第四端，所述第四开关的第一端连接所述第一开关电路的第二端，所述第四开关的第二端连接所述第一开关电路的第三端，所述第三开关的第一端连接所述第一开关电路的第四端，所述第三开关的第二端连接所述第一开关电路的第五端，所述第五开关的第一端连接所述第一开关电路的第三端，所述第五开关的第二端连接 所述第一开关电路的第五端；
    其中，在第一降压模式下，在一个周期内的第一时间段，所述第一开关、所述第三开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第一开关、所述第三开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期内所述第四开关处于断开状态；
    在第二降压模式下，在一个周期内的第一时间段，所述第三开关、所述第四开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第三开关、所述第四开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期内所述第四开关处于断开状态；在一个周期内所述第一开关处于导通状态；
    在第三降压模式下，所述第一开关、所述第二开关、所述第三开关、所述第四开关、以及第五开关处于导通状态。
  3. 根据权利要求1或2所述的SC，其特征在于，所述第二开关电路，包括：第六开关和第七开关；其中，所述第六开关的第一端连接所述第二开关电路的第一端，所述第六开关的第二端连接所述第二开关电路的第二端，所述第七开关的第一端连接所述第二开关电路的第二端，所述第七开关的第二端连接所述第二开关电路的第三端；
    在第一降压模式下，在一个周期内的第一时间段，所述第六开关处于导通状态，所述第七开关处于断开状态；在一个周期内的第二时间段，所述第六开关处于断开状态，所述第七开关处于导通状态；
    在第二降压模式下，所述第六开关和所述第七开关处于断开状态；
    在第三降压模式下，所述第六开关和所述第七开关处于断开状态。
  4. 根据权利要求1-3任一项所述的SC，其特征在于，所述第三开关电路，包括：第八开关和第九开关；
    其中，第八开关的第一端连接所述第三开关电路的第一端，所述第八开关的第二端连接第三开关电路的第二端，所述第九开关的第一端连接第三开关电路的第二端，所述第九开关的第二端连接所述第三开关电路的第三端；
    在第一降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；
    在第二降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；
    在第三降压模式下，所述第八开关和所述第九开关处于断开状态。
  5. 根据权利要求1-4任一项所述的SC，其特征在于，所述第四开关电路，包括：第十开关和第十一开关，其中，所述第十开关的第一端连接第四开关电路的第一端，第十开关的第二端连接第四开关电路的第二端，所述第十一开关的第一端连接所述第四开关电路的第二端，所述第十一开关的第二端连接所述第四开关电路的第三端；
    在第一降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态， 所述第十一开关处于导通状态；
    在第二降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；
    在第三降压模式下，所述第十开关和所述第十一开关处于断开状态。
  6. 根据权利要求2-5任一项所述的SC，其特征在于，各个开关包括一个开关晶体管，或者，各个开关包括并联的两个或多个开关晶体管。
  7. 一种芯片，其特征在于，包括：第一开关电路、第二开关电路、第三开关电路、第四开关电路；
    其中，所述第一开关电路的第一端连接电源端；所述第一开关电路的第二端用于连接第三电容的第一端，所述第一开关电路的第三端连接所述第二开关电路的第一端，所述第一开关电路的第三端还用于连接第一电容的第一端，所述第一开关电路的第四端用于连接第二电容的第一端，所述第一开关电路的第五端连接所述第三开关电路的第一端、所述第四开关电路的第一端，所述第一开关电路的第五端还用于连接第四电容的第一端；所述第二开关电路的第二端用于连接所述第三电容的第二端，所述第二开关电路的第三端连接地；所述第三开关电路的第二端用于连接所述第二电容的第二端，所述第三开关电路的第三端连接地，所述第四开关电路的第二端用于连接所述第一电容的第二端，所述第四开关电路的第三端连接所述地，所述第四电容的第二端连接所述地；
    在第一降压模式下，所述第一开关电路被配置为将所述电源端与所述第三电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置将所述第三电容的第二端与所述第一电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第三电容的第一端与所述第二电容的第一端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第二开关电路被配置为将所述第三电容的第二端与所述地导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；
    在第二降压模式下，所述第一开关电路被配置为将所述电源端与所述第一电容的第一端导通，将所述第二电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述地导通；所述第四开关电路被配置为将所述第一电容的第二端与所述第四电容的第一端导通；或者，所述第一开关电路被配置为将所述第二电容的第一端与所述电源端导通，将所述第一电容的第一端与所述第四电容的第一端导通；所述第三开关电路被配置为将所述第二电容的第二端与所述第四电容的第一端导通；所述第四开关电路被配置为将所述第一电容的第二端与所述地导通；
    在第三降压模式下，所述第一开关电路被配置为将所述电源端与所述第四电容的第一端导通。
  8. 根据权利要求7所述的芯片，其特征在于，所述第一开关电路，包括：第一开 关、第二开关、第三开关、第四开关以及第五开关；其中，所述第一开关的第一端连接所述第一开关电路的第一端，所述第一开关的第二端连接所述第一开关电路的第二端，所述第二开关的第一端连接所述第一开关电路的第二端，所述第二开关的第二端连接所述第一开关电路的第四端，所述第四开关的第一端连接所述第一开关电路的第二端，所述第四开关的第二端连接所述第一开关电路的第三端，所述第三开关的第一端连接所述第一开关电路的第四端，所述第三开关的第二端连接所述第一开关电路的第五端，所述第五开关的第一端连接所述第一开关电路的第三端，所述第五开关的第二端连接所述第一开关电路的第五端；
    其中，在第一降压模式下，在一个周期内的第一时间段，所述第一开关、所述第三开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第一开关、所述第三开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期内所述第四开关处于断开状态；
    在第二降压模式下，在一个周期内的第一时间段，所述第三开关、所述第四开关处于导通状态，所述第二开关、所述第五开关处于断开状态；在一个周期内的第二时间段，所述第三开关、所述第四开关断开状态，所述第二开关、所述第五开关处于导通状态；在一个周期所述第四开关处于断开状态；在一个周期内所述第一开关处于导通状态；
    在第三降压模式下，所述第一开关、所述第二开关、所述第三开关、所述第四开关、以及第五开关处于导通状态。
  9. 根据权利要求7或8所述的芯片，其特征在于，所述第二开关电路，包括：第六开关和第七开关；其中，所述第六开关的第一端连接所述第二开关电路的第一端，所述第六开关的第二端连接所述第二开关电路的第二端，所述第七开关的第一端连接所述第二开关电路的第二端，所述第七开关的第二端连接所述第二开关电路的第三端；
    在第一降压模式下，在一个周期内的第一时间段，所述第六开关处于导通状态，所述第七开关处于断开状态；在一个周期内的第二时间段，所述第六开关处于断开状态，所述第七开关处于导通状态；
    在第二降压模式下，所述第六开关和所述第七开关处于断开状态；
    在第三降压模式下，所述第六开关和所述第七开关处于断开状态。
  10. 根据权利要求7-9任一项所述的芯片，其特征在于，所述第三开关电路，包括：第八开关和第九开关；
    其中，第八开关的第一端连接所述第三开关电路的第一端，所述第八开关的第二端连接第三开关电路的第二端，所述第九开关的第一端连接第三开关电路的第二端，所述第九开关的第二端连接所述第三开关电路的第三端；
    在第一降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；
    在第二降压模式下，在一个周期内的第一时间段，所述第九开关处于导通状态，所述第八开关断开状态；在一个周期内的第二时间段，所述第九开关处于断开状态，所述第八开关处于导通状态；
    在第三降压模式下，所述第八开关和所述第九开关处于断开状态。
  11. 根据权利要求7-10任一项所述的芯片，其特征在于，所述第四开关电路，包括：第十开关和第十一开关，其中，所述第十开关的第一端连接第四开关电路的第一端，第十开关的第二端连接第四开关电路的第二端，所述第十一开关的第一端连接所述第四开关电路的第二端，所述第十一开关的第二端连接所述第四开关电路的第三端；
    在第一降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；
    在第二降压模式下，在一个周期内的第一时间段，所述第十开关处于导通状态，所述第十一处于断开状态；在一个周期内的第二时间段，所述第十开关处于断开状态，所述第十一开关处于导通状态；
    在第三降压模式下，所述第十开关和所述第十一开关处于断开状态。
  12. 根据权利要求7-11任一项所述的芯片，其特征在于，各个开关包括一个开关晶体管，或者，各个开关包括并联的两个或多个开关晶体管。
  13. 一种电子设备，其特征在于，包括如权利要求1-6任一项所述的SC或权利要求7-12所述的芯片。
  14. 根据权利要求13所述的电子设备，其特征在于，还包括无线充电线圈、接收电路以及电池；所述无线充电线圈连接所述接收电路，所述接收电路连接所述SC或所述芯片的电源端，所述电池与所述第四电容并联。
  15. 根据权利要求13所述的电子设备，其特征在于，还包括USB接口以及电池；所述USB接口连接所述SC或所述芯片的电源端，所述电池与所述第四电容并联。
  16. 根据权利要求15所述的电子设备，其特征在于，所述USB接口与所述SC或所述芯片的电源端之间还设置有过压保护防护电路，其中所述过压保护防护电路用于检测到接入USB接口的电压超过阈值电压时，将所述SC或所述芯片的电源端与所述USB接口的连接切断。
PCT/CN2022/141582 2022-01-30 2022-12-23 一种开关电容电路sc及电子设备 WO2023142820A1 (zh)

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JP2004040884A (ja) * 2002-07-02 2004-02-05 Fumio Ueno スイッチトキャパシタ電源回路
JP2009055722A (ja) * 2007-08-28 2009-03-12 Seiko Npc Corp チャージポンプ方式電源回路
JP2013059240A (ja) * 2011-09-09 2013-03-28 Rohm Co Ltd チャージポンプ回路およびその制御回路、オーディオ信号処理回路、電子機器
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