WO2023137855A1 - 存储芯片的测试方法及设备 - Google Patents

存储芯片的测试方法及设备 Download PDF

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Publication number
WO2023137855A1
WO2023137855A1 PCT/CN2022/081819 CN2022081819W WO2023137855A1 WO 2023137855 A1 WO2023137855 A1 WO 2023137855A1 CN 2022081819 W CN2022081819 W CN 2022081819W WO 2023137855 A1 WO2023137855 A1 WO 2023137855A1
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Prior art keywords
memory chip
tested
memory
data
test data
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PCT/CN2022/081819
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English (en)
French (fr)
Inventor
刘�东
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长鑫存储技术有限公司
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Priority to US17/808,701 priority Critical patent/US20230230649A1/en
Publication of WO2023137855A1 publication Critical patent/WO2023137855A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a method and device for testing a memory chip.
  • DRAM Dynamic Random Access Memory
  • DRAM is composed of a plurality of storage units, each of which usually includes a capacitor structure and a transistor.
  • the gate of the transistor is connected to the word line (WL), the drain is connected to the bit line (BL), and the source is connected to the above-mentioned capacitor structure; the voltage signal on WL can control the opening or closing of the above-mentioned transistor, and then read the data signal stored in the above-mentioned capacitor structure through BL, or write the data signal into the above-mentioned capacitor structure through BL for storage.
  • Embodiments of the present application provide a memory chip testing method and equipment, which can accurately detect whether a memory chip has a failed memory unit, thereby improving the yield rate of the memory chip.
  • a method for testing a memory chip comprising:
  • the current bit line precharge voltage of the memory chip to be tested is less than the standard bit line precharge voltage of the memory chip to be tested, and/or, the current sensing delay time of the memory chip to be tested is less than the standard sensing delay time of the memory chip to be tested.
  • a memory chip testing device comprising:
  • write module for writing test data in the storage unit of the memory chip to be tested
  • a reading module configured to read stored data from the storage unit
  • a processing module configured to generate a test result of the memory chip to be tested according to the test data and the stored data
  • the current bit line precharge voltage of the memory chip to be tested is less than the standard bit line precharge voltage of the memory chip to be tested, and/or, the current sensing delay time of the memory chip to be tested is less than the standard sensing delay time of the memory chip to be tested.
  • an electronic device comprising: at least one processor and a memory;
  • the memory stores computer-executable instructions
  • the at least one processor executes the computer-executed instructions stored in the memory, so that the at least one processor executes the memory chip testing method provided in the above-mentioned embodiments.
  • a computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the memory chip testing method provided in the above-mentioned embodiments is realized.
  • the memory chip testing method and equipment provided in the embodiments of the present application can realize: writing test data in the storage unit of the storage chip to be tested; reading storage data from the storage unit; generating a test result of the storage chip to be tested according to the test data and the storage data.
  • the current bit line precharge voltage of the memory chip to be tested is less than the standard bit line precharge voltage of the memory chip to be tested, and/or, the current sensing delay time of the memory chip to be tested is less than the standard sensing delay time of the memory chip to be tested, that is, the memory chip is in a poor working environment, so the failed memory cells existing in the memory chip can be exposed more easily, thereby accurately detecting whether there is a failed memory cell in the memory chip, thereby improving the yield rate of the memory chip.
  • FIG. 1 is a schematic layout diagram of a memory chip provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a memory unit of a memory chip provided by an embodiment of the present application
  • FIG. 3 is a schematic flowchart of a method for testing a memory chip provided in an embodiment of the present application
  • FIG. 4 is a schematic diagram of multiple data topologies in the test data provided in the embodiments of the present application.
  • FIG. 5 is a schematic flowchart of a method for testing a memory chip provided in an embodiment of the present application
  • FIG. 6 is a first schematic diagram of a data writing process of a memory chip testing method provided in an embodiment of the present application
  • FIG. 7 is a second schematic diagram of a data writing process of a memory chip testing method provided in an embodiment of the present application.
  • FIG. 8 is a third schematic diagram of a data writing process of a memory chip testing method provided in an embodiment of the present application.
  • FIG. 9 is a schematic diagram 4 of a data writing process of a memory chip testing method provided in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of program modules of a memory chip testing device provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application.
  • module refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic or combination of hardware and/or software codes capable of performing the functions associated with that element.
  • the embodiment of the present application provides a method for testing a memory chip.
  • the memory chip By adjusting the memory chip to be in a poor working environment, the failed memory cells in the memory chip are more likely to be exposed, thereby helping to accurately detect whether there are failed memory cells in the memory chip, thereby improving the yield rate of the memory chip.
  • the memory chip includes a plurality of bit lines (Bit Line, referred to as BL), a plurality of word lines (Word Line, referred to as WL) and a plurality of memory cells, wherein each memory cell is connected to a corresponding word line WL and a bit line BL.
  • Bit Line referred to as BL
  • Word Line referred to as WL
  • FIG. 1 is a schematic layout diagram of a memory chip provided by an embodiment of the present application.
  • multiple bit lines can be divided into 128 bit line groups, and each bit line group has 8 bit lines.
  • bit lines in each bit line group are marked as BL0, BL1, BL2...BL7.
  • multiple word lines can be divided into 8192 word line groups, each word line group has 8 word lines, for the convenience of description below, the bit lines in each bit line group are marked as WL0, WL1, WL2...WL7.
  • a plurality of memory cells P11-P88 are distributed in a matrix, wherein the memory cells in the first column are all connected to the word line WL0, the memory cells in the second column are all connected to the word line WL1, and so on, and the memory cells in the eighth column are all connected to the word line WL7; the memory cells in the first row are all connected to the bit line BL0, and the memory cells in the second row are all connected to the bit line BL1, and so on.
  • the memory cells in the eighth row are all connected to the bit line BL7, so that each memory cell is connected to a word line WL and a bit line BL connect.
  • FIG. 2 is a schematic structural diagram of a memory unit of a memory chip provided by an embodiment of the present application.
  • each memory cell 10 includes a transistor 12 and a capacitor 11.
  • the gate of the transistor 12 is connected to the word line WL
  • the source of the transistor 12 is connected to the bit line BL
  • the drain of the transistor 12 is connected to the capacitor 11.
  • the source of the transistor 12 can also be connected to the capacitor 11.
  • the drain of the transistor 12 is connected to the bit line BL.
  • the data line BL when the signal on the word line WL turns on the switching transistor T, the data line BL can write a high-level signal "1" to the storage capacitor C, and when the signal on the word line WL turns off the switching transistor T, the charge on the storage capacitor C slowly leaks over time.
  • the time between the leakage of the storage capacitor C from the high-level signal "1" to the low-level signal “0" is the data storage time of the storage capacitor C.
  • the data storage time of the storage capacitor C needs to be longer than the preset time to realize the dynamic storage function of the DRAM.
  • FIG. 3 is a schematic flowchart of a method for testing a memory chip provided in an embodiment of the present application.
  • the testing method of the memory chip includes:
  • the current bit line precharge voltage of the memory chip to be tested is less than the standard bit line precharge voltage of the memory chip to be tested, and/or, the current sensing delay time of the memory chip to be tested is less than the standard sensing delay time of the memory chip to be tested.
  • the above-mentioned memory chip to be tested takes DRAM as an example, lowering the bit line precharge voltage (VBLP) to be lower than the standard bit line precharge voltage of DRAM can create poor working conditions for DRAM, reduce the signal margin (Signal Margin), and make the failed memory cells in DRAM more easily exposed.
  • VBLP bit line precharge voltage
  • sensing Delay Time (Sensing Delay Time, referred to as SDT) to less than the standard sensing delay time of DRAM can also create poor working conditions for DRAM, reducing charge sharing ( ⁇ V), and making failed memory cells in DRAM more easily exposed.
  • bit line precharge voltage can be adjusted down to P% of the standard bit line precharge voltage, where 0 ⁇ P ⁇ 1.
  • the sensing delay time can be adjusted down to Q% of the standard sensing delay time, where 0 ⁇ Q ⁇ 1.
  • the current sensing delay time of the memory chip to be tested is less than the standard sensing delay time of the memory chip to be tested.
  • the current bit line precharge voltage of the memory chip to be tested can be adjusted to be less than the standard bit line precharge voltage of the memory chip to be tested, and the current sensing delay time of the memory chip to be tested can also be adjusted to be less than the standard sensing delay time of the memory chip to be tested.
  • test data is written into the storage unit of the memory chip to be tested, and then the stored data in each storage unit is read.
  • the above test data By comparing the above test data with the stored data, it can be determined whether there is a failed storage unit in each storage unit of the above-mentioned tested memory chip, which can be applied to the detection of failed storage units in the memory chip due to failure to store low-level "0".
  • the current write timing parameter of the memory chip to be tested is also possible to adjust the current write timing parameter of the memory chip to be tested to be smaller than the standard write timing parameter of the memory chip to be tested, and/or adjust the current read timing parameter of the memory chip to be tested to be smaller than the standard read timing parameter of the memory chip to be tested.
  • the above-mentioned write timing parameter may be the write recovery time (Write Recovery Time, referred to as TWR) of the memory chip to be tested; the above-mentioned read timing parameter is the row precharge effective period (Row Precharge Time, referred to as TRP) of the memory chip to be tested.
  • TWR Write Recovery Time
  • TRP Row Precharge Time
  • TWR time to write the data into each storage unit of the DRAM
  • This time is defined as TWR.
  • TWR time to write the data into each storage unit of the DRAM
  • This value specifies how many clock cycles must wait before a valid write operation and precharge are completed in an active bank. This necessary clock cycle is used to ensure that the data in the write buffer can be written to the memory cell before the precharge occurs.
  • TRP is the time between the precharge command (PRE) and the activation command (ACT) of the next word line in DRAM, which is used to characterize the speed at which the DRAM array returns to the precharge state, especially the time required for the bit line in the array to charge from a high level or a low level to an intermediate potential.
  • shortening the write recovery time of the memory chip to be tested is equivalent to creating an insufficient writing condition for the memory chip to be tested.
  • Shortening the effective period of row precharging of the memory chip to be tested is equivalent to creating an insufficient read-in condition for the memory chip to be tested.
  • the write recovery time may be adjusted down to R% of the standard write recovery time, where 0 ⁇ R ⁇ 1.
  • the effective period of the row precharging can be adjusted down to S% of the standard row precharging effective period, where 0 ⁇ S ⁇ 1.
  • only the write recovery time of the memory chip under test can be shortened, or only the effective period of row precharging of the memory chip under test can be shortened.
  • the write recovery time of the memory chip under test and the effective period of row precharging of the memory chip under test can be shortened simultaneously.
  • the write recovery time of the memory chip to be tested and/or the row precharge effective period of the memory chip to be tested can be shortened.
  • the current bit line precharge voltage of the memory chip to be tested can be adjusted to be less than the standard bit line precharge voltage of the memory chip to be tested, and the current sensing delay time of the memory chip to be tested can be adjusted to be less than the standard sensing delay time of the memory chip to be tested, so as to create a poor working condition for the memory chip to be tested; at the same time, under the premise of shortening the write recovery time of the memory chip to be tested, test data is written in the storage unit of the memory chip to be tested to create an insufficient condition for writing; then shorten the row precharge of the memory chip to be tested On the premise of valid period, the stored data is read from the above-mentioned storage unit to create an insufficient read condition. Compare whether the read storage data is consistent with the written test data. If they are consistent, it means that the memory chip to be tested does not have a failed memory unit; if they are inconsistent, it means that the memory chip to be tested has a failed memory unit.
  • any one, or any two, or any three of the above-mentioned bit line precharge voltage, sensing delay time, write timing parameters, and read timing parameters can be reduced, and the embodiments of the present application will not repeat the various combinations.
  • the memory chip testing method provided in the embodiment of the present application creates a poor working condition for the memory chip to be tested, then writes the stored data while shortening the write recovery time, and reads the stored data from the above-mentioned storage unit while shortening the effective period of row precharging, which can create double bad conditions for detecting the failed storage unit due to the failure to store a low-level “0”, making it easier to expose the failed storage unit due to the failure to store a low-level “0”, thereby effectively prompting the accuracy of the detection result.
  • the memory chip to be tested includes multiple columns of storage units, and each column of storage units adopts one or more detection cycles.
  • the test data can be written in the storage cells in the same detection cycle.
  • the stored data is also read from the storage cells in the same detection cycle.
  • each column of memory cells of the above-mentioned memory chip to be tested may be tested in a traversal manner along the X-axis direction.
  • the above-mentioned memory chip to be tested includes multiple rows of storage units, and each row of memory cells adopts one or more detection cycles; when writing test data in the storage cells of the memory chip to be tested, the test data can be written in the storage cells in the same detection cycle; similarly, when reading the storage data from the storage unit, the storage data is also read from the storage cells in the same detection cycle.
  • each column of memory cells of the above-mentioned memory chip to be tested may be tested in a traversal manner along the Y-axis direction.
  • the test data is a plurality of binary sequences with equal data bits, and each binary sequence has a different data topology.
  • test data can be determined as follows:
  • any one or more data bits in the above test data as conversion bits perform traversal access to the above test data, and flip the data of the conversion bits accessed through traversal until each binary sequence in the above test data is traversed.
  • the number of bits of the memory cells in each row or the memory cells in each column of the memory chip to be tested is greater than the number of bits of the test data.
  • the number of bits of the memory cells in each row or column of the memory chip to be tested is an integer multiple of the number of bits in the test data.
  • the test data includes multiple binary sequences, and only one data bit in each binary sequence is 0.
  • FIG. 4 is a schematic diagram of multiple data topologies in the test data provided in the embodiment of the present application.
  • the number of bits of the above test data is 8 bits, and there is only one data bit in each binary sequence that is 0.
  • the memory chip testing method provided in the embodiment of the present application uses the binary sequence in the above format as test data, and can effectively detect failed memory cells in the memory chip.
  • data 1 before writing the test data in the storage unit of the storage chip to be tested, data 1 is written into each storage unit of the storage chip to be tested, and after the test is completed, data 1 is stored back to each storage unit of the storage chip to be tested.
  • FIG. 5 is a schematic flowchart of a method for testing a memory chip provided in an embodiment of the present application.
  • the testing method of above-mentioned memory chip comprises:
  • Step 1 traverse the memory cells of the memory chip to be tested along the Y axis direction, and write 1 into the traversed memory cells.
  • Step 2 Traverse the memory cells of the memory chip to be tested along the Y-axis direction, and read the data stored in the traversed memory cells.
  • Step 3 Determine whether the data read in step 2 are all 1; if the read data are all 1, proceed to step 4, if there is 0 in the read data, then determine that there is a failed storage unit in the memory chip to be tested, and the failed storage unit is a storage unit whose read data is 0.
  • Step 4 Shorten the current bit line precharge voltage of the memory chip to be tested, and/or, the sensing delay time.
  • Step 5 On the premise of shortening the write timing parameters, traverse a column of memory cells of the memory chip to be tested along the X-axis direction, and write a binary sequence in the traversed column of memory cells.
  • Step 6 On the premise of shortening the reading timing parameters, traverse a column of memory cells of the memory chip to be tested along the X-axis direction, and read the binary sequence stored in the traversed column of memory cells.
  • Steps 5 to 6 are repeated to traverse each row of memory cells of the memory chip to be tested.
  • Step 7 traverse other remaining binary sequences, and repeatedly execute steps 1 to 6.
  • a test result of the memory chip to be tested is generated according to the written test data and the read stored data.
  • the test data and the stored data can be compared, and it is determined according to the comparison result whether a read/write error occurs in the storage unit of the memory chip to be tested; wherein, if a read/write error occurs in the storage unit of the memory chip to be tested, the number of digits in which the read/write error occurs is determined according to the comparison result; and the test result of the memory chip to be tested is generated according to the determination result of whether a read/write error occurs in the storage unit of the memory chip to be tested.
  • FIG. 6 is a first schematic flow diagram of a data writing process of a memory chip testing method provided in the embodiment of the present application.
  • bit lines in FIG. 6 taking a bank in the DRAM memory as an example, multiple bit lines can be divided into 128 bit line groups, and each bit line group has 8 bit lines.
  • bit lines in each bit line group are recorded as BL0, BL1, BL2...BL7.
  • Multiple word lines can be divided into 8192 word line groups, and each word line group has 8 word lines.
  • the bit lines in each bit line group are marked as WL0, WL1, WL2...WL7.
  • a plurality of memory cells are distributed in a matrix, wherein, the memory cells in the first column are all connected to the word line WL0, the memory cells in the second column are all connected to the word line WL1, and so on, the memory cells in the eighth column are all connected to the word line WL7; the memory cells in the first row are all connected to the bit line BL0, the memory cells in the second row are all connected to the bit line BL1, and so on.
  • the memory cells in the eighth row are all connected to the bit line BL7, so that each memory cell is connected to a word line WL and a bit line BL.
  • the current bit line precharge voltage of the memory chip to be tested is adjusted in advance to be less than the standard bit line precharge voltage of the memory chip to be tested, and the current sensing delay time of the memory chip to be tested is adjusted to be less than the standard sensing delay time of the memory chip to be tested, so as to create poor working conditions for the memory chip to be tested; under this working condition, after adjusting the current write timing parameters of the memory chip to be tested to be less than the standard write timing parameters of the memory chip to be tested, traverse each word line (WL0, WL1, WL2) of the memory chip to be tested along the X-axis direction ...WL7), write a binary sequence (example topology 0): 01111111 in a column of memory cells corresponding to a group of bit lines (BL0, BL1, BL2...BL7) of each word line. Afterwards, adjust the current read timing parameter of the memory chip to be tested to be smaller than the standard read timing parameter of the memory chip to be tested, and read the data stored in
  • FIG. 7 is a second schematic diagram of a data writing process of a memory chip testing method provided in an embodiment of the present application.
  • FIG. 8 is a third schematic diagram of a data writing process of a memory chip testing method provided in an embodiment of the present application.
  • each word line (WL0, WL1, WL2...WL7) of the memory chip to be tested along the X-axis direction and write a binary sequence (example topology 1): 10111111 in a column of memory cells corresponding to a group of bit lines (BL0, BL1, BL2... BL7) of each word line.
  • adjust the current read timing parameter of the memory chip to be tested to be smaller than the standard read timing parameter of the memory chip to be tested, and read the data stored in the traversed row of memory cells.
  • FIG. 9 is a schematic diagram 4 of a data writing process of a memory chip testing method provided in an embodiment of the present application.
  • the test result of the memory chip to be tested can be obtained.
  • the memory chip testing method provided in the embodiment of the present application, by adjusting the current bit line precharge voltage of the memory chip to be tested to be smaller than the standard bit line precharge voltage of the memory chip to be tested, and/or, the current sensing delay time of the memory chip to be tested is shorter than the standard sensing delay time of the memory chip to be tested, so that the memory chip can be placed in a poor working environment; Under the condition that the reading timing parameters of the memory chip are smaller than the standard reading timing parameters, reading the stored data from the memory unit can make the failed memory units in the memory chip more easily exposed. According to the above test data and the read stored data, it can be accurately detected whether there is a failed memory unit in the memory chip, thereby improving the yield rate of the memory chip.
  • FIG. 10 is a schematic diagram of program modules of a memory chip testing device provided in an embodiment of the present application.
  • the memory chip testing device includes:
  • the writing module 1001 is used for writing test data in the storage unit of the memory chip to be tested.
  • a reading module 1002 configured to read stored data from the storage unit.
  • the processing module 1003 is configured to generate a test result of the memory chip to be tested according to the test data and the stored data.
  • the current bit line precharge voltage of the memory chip to be tested is less than the standard bit line precharge voltage of the memory chip to be tested, and/or, the current sensing delay time of the memory chip to be tested is less than the standard sensing delay time of the memory chip to be tested.
  • the memory chip testing device since the current bit line precharge voltage of the memory chip to be tested is lower than the standard bit line precharge voltage of the memory chip to be tested, and/or the current sensing delay time of the memory chip to be tested is shorter than the standard sensing delay time of the memory chip to be tested, the memory chip is in a poor working environment, so that the abnormality existing in the memory chip can be exposed more easily, thereby accurately detecting whether the memory chip has an abnormality, thereby improving the yield rate of the memory chip.
  • the current write timing parameter of the memory chip to be tested is smaller than the standard write timing parameter of the memory chip to be tested, and/or, the current read timing parameter of the memory chip to be tested is smaller than the standard read timing parameter of the memory chip to be tested.
  • the above-mentioned write timing parameter is the write recovery time of the memory chip to be tested;
  • the above-mentioned read timing parameter is an effective period of row precharging of the memory chip to be tested.
  • the memory chip to be tested includes multiple columns of memory cells, and one or more detection cycles are used for each column of memory cells.
  • the writing module 1001 is used for: writing test data in the storage units in the same detection period.
  • the reading module 1002 is configured to: read storage data from storage units in the same detection period.
  • each row of memory cells of the memory chip to be tested is tested in a traversal manner; wherein, the traversal direction is the X-axis direction.
  • the memory chip to be tested includes multiple rows of memory cells, and one or more detection cycles are used for each row of memory cells.
  • the writing module 1001 is used for: writing test data in the storage units in the same testing period.
  • the reading module 1002 is configured to: read storage data from storage units in the same detection period.
  • each row of memory cells of the memory chip to be tested is tested in a traversal manner; wherein, the traversal direction is the Y-axis direction.
  • the above-mentioned test data is a plurality of binary sequences with equal data bits, and each of the above-mentioned binary sequences has a different data topology.
  • test data generation module configured to determine the test data in the following manner:
  • any one or more data bits in the above test data as conversion bits perform traversal access to the above test data, and flip the data of the conversion bits accessed through traversal until each binary sequence in the above test data is traversed.
  • the number of bits of the memory cells in each row or the memory cells in each column is greater than that of the test data.
  • the number of bits of the memory cells in each row or the memory cells in each column is an integer multiple of the number of bits in the test data.
  • the above test data includes multiple binary sequences, and only one data bit in each binary sequence is 0.
  • the processing module 1003 is used to:
  • the writing module 1001 is also used for:
  • test data 1 is written into each memory cell of the memory chip to be tested.
  • the reading module 1002 is further configured to: after generating the test result of the memory chip to be tested according to the test data and the stored data, store 1 back into each storage unit of the memory chip to be tested.
  • the writing module 1001, the reading module 1002, and the processing module can refer to the relevant content in the embodiments shown in FIG. 1 to FIG.
  • the embodiments of the present application also provide an electronic device, the electronic device includes at least one processor and a memory; wherein, the memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory, so as to implement each step in the method for testing a memory chip as described in the above-mentioned embodiments, and this embodiment will not repeat them here.
  • FIG. 11 is a schematic diagram of a hardware structure of an electronic device provided in the embodiment of the present application.
  • the electronic device 110 of this embodiment includes: a processor 1101 and a memory 1102; wherein:
  • memory 1102 for storing computer-executable instructions
  • the processor 1101 is configured to execute the computer-executable instructions stored in the memory, so as to implement each step in the memory chip testing method described in the above-mentioned embodiments, which will not be repeated here in this embodiment.
  • the memory 1102 can be independent or integrated with the processor 1101 .
  • the device When the memory 1102 is set independently, the device further includes a bus 1103 for connecting the memory 1102 and the processor 1101 .
  • the embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, each step in the method for testing a memory chip as described in the above-mentioned embodiments is implemented, and details are not repeated here in this embodiment.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules can be combined or integrated into another system, or some features can be ignored or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or modules may be in electrical, mechanical or other forms.
  • modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in each embodiment of the present application may be integrated into one processing unit, each module may exist separately physically, or two or more modules may be integrated into one unit.
  • the integrated units of the above modules can be implemented in the form of hardware, or in the form of hardware plus software functional units.
  • the above-mentioned integrated modules implemented in the form of software function modules can be stored in a computer-readable storage medium.
  • the above-mentioned software function modules are stored in a storage medium, and include several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) or a processor (English: processor) to execute some steps of the methods described in various embodiments of the present application.
  • processor may be a central processing unit (English: Central Processing Unit, referred to as: CPU), and may also be other general-purpose processors, digital signal processors (English: Digital Signal Processor, referred to as: DSP), application specific integrated circuits (English: Application Specific Integrated Circuit, referred to as: ASIC), etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in conjunction with the application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
  • the storage may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk storage, and may also be a U disk, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disk.
  • NVM non-volatile storage
  • the bus can be an Industry Standard Architecture (Industry Standard Architecture, ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the buses in the drawings of the present application are not limited to only one bus or one type of bus.
  • the above-mentioned storage medium can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • EPROM erasable programmable read-only memory
  • PROM programmable read-only memory
  • ROM read-only memory
  • magnetic memory flash memory
  • flash memory magnetic disk or optical disk.
  • a storage media may be any available media that can be accessed by a general purpose or special purpose computer.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and the storage medium may be located in Application Specific Integrated Circuits (ASIC for short).
  • ASIC Application Specific Integrated Circuits
  • the processor and the storage medium can also exist in the electronic device or the main control device as discrete components.
  • the aforementioned program can be stored in a computer-readable storage medium.
  • the program executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

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Abstract

本申请实施例提供一种存储芯片的测试方法及设备，包括：在待测存储芯片的存储单元中写入测试数据；从存储单元中读取存储数据；根据测试数据与存储数据，生成待测存储芯片的测试结果；其中，待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，和/或，待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间。本申请实施例提供的存储芯片的测试方法及设备，可以准确检测出存储芯片是否存在失效的存储单元，进而提升存储芯片的良率。

Description

存储芯片的测试方法及设备
本申请要求于2022年01月19日提交中国专利局、申请号为202210059291.6、申请名称为“存储芯片的测试方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种存储芯片的测试方法及设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种常见的存储芯片，已被广泛地应用到各种电子设备中。
DRAM由多个存储单元组成，每个存储单元通常包括电容结构和晶体管，晶体管的栅极与字线(Word Line，简称WL)相连、漏极与位线(Bit Line，简称BL)相连、源极与上述电容结构相连；WL上的电压信号能够控制上述晶体管的打开或关闭，进而通过BL读取存储在上述电容结构中的数据信号，或者通过BL将数据信号写入到上述电容结构中进行存储。
在现代集成电路制造工艺中，器件缺陷造成的损失代价极为高昂，因此，亟需提供一种测试方法来测试存储芯片是否存在失效的存储单元，以便于提升存储芯片的良率。
发明内容
本申请实施例提供一种存储芯片的测试方法及设备，可以准确检测出存储芯片是否存在失效的存储单元，进而提升存储芯片的良率。
在一些实施例中，提供了一种存储芯片的测试方法，该方法包括：
在待测存储芯片的存储单元中写入测试数据；
从所述存储单元中读取存储数据；
根据所述测试数据与所述存储数据，生成所述待测存储芯片的测试结果；
其中，所述待测存储芯片当前的位线预充电电压小于所述待测存储芯片的标准位线预充电电压，和/或，所述待测存储芯片当前的感测延迟时间小于所述待测存储芯片的标准感测延迟时间。
在一些实施例中，提供了一种存储芯片的测试装置，该装置包括：
写入模块，用于在待测存储芯片的存储单元中写入测试数据；
读取模块，用于从所述存储单元中读取存储数据；
处理模块，用于根据所述测试数据与所述存储数据，生成所述待测存储芯片的测试结果；
其中，所述待测存储芯片当前的位线预充电电压小于所述待测存储芯片的标准位线预充电电压，和/或，所述待测存储芯片当前的感测延迟时间小于所述待测存储芯片的标准感测延迟时间。
在一些实施例中，提供了一种电子设备，包括：至少一个处理器和存储器；
所述存储器存储计算机执行指令；
所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如上述实施例中提供的存储芯片的测试方法。
在一些实施例中，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如上述实施例中提供的存储芯片的测试方法。
本申请实施例中所提供的存储芯片的测试方法及设备，可以实现：在待测存储芯片的存储单元中写入测试数据；从存储单元中读取存储数据；根据测试数据与所述存储数据，生成待测存储芯片的测试结果。其中，由于待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，和/或，待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间，即将存储芯片处于较差的工作环境下，因此可以使存储芯片中存在的失效存储单元更容易暴露，从而准确检测出存储芯片是否存在失效的存储单元，进而提升存储芯片的良率。
附图说明
图1为本申请实施例提供的一种存储芯片的布局示意图；
图2为本申请实施例提供的一种存储芯片的存储单元的结构示意图；
图3为本申请实施例中提供的一种存储芯片的测试方法的流程示意图；
图4为本申请实施例中提供的测试数据中多个数据拓扑示意图；
图5为本申请实施例中提供的一种存储芯片的测试方法的流程示意图；
图6为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图一；
图7为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图二；
图8为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图三；
图9为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图四；
图10为本申请实施例中提供的一种存储芯片的测试装置的程序模块示意图；
图11为本申请实施例提供的一种电子设备的硬件结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，虽然本申请中公开内容按照示范性一个或几个实例来介绍，但应理解，可以就这些公开内容的各个方面也可以单独构成一个完整实施方式。
需要说明的是，本申请中对于术语的简要说明，仅是为了方便理解接下来描述的实施方式，而不是意图限定本申请的实施方式。除非另有说明，这些术语应当按照其普通和通常的含义理解。
本申请中说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似或同类的对象或实体，而不必然意味着限定特定的顺序或先后次序，除非另外注明。应该理解这样使用的用语在适当情况下可以互换，例如能够根据本申请实施例图示或描述中给出那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖但不 排他的包含，例如，包含了一系列组件的产品或设备不必限于清楚地列出的那些组件，而是可包括没有清楚地列出的或对于这些产品或设备固有的其它组件。
本申请中使用的术语“模块”，是指任何已知或后来开发的硬件、软件、固件、人工智能、模糊逻辑或硬件或/和软件代码的组合，能够执行与该元件相关的功能。
在现代集成电路制造工艺中，器件缺陷造成的损失代价极为高昂，因此，如何测试存储芯片是否存在失效的存储单元显得非常重要。
针对上述技术问题，本申请实施例中提供了一种存储芯片的测试方法，通过调节使存储芯片处于较差的工作环境中，使存储芯片中失效的存储单元更容易暴露，从而有助于准确检测出存储芯片是否存在失效的存储单元，进而提升存储芯片的良率。
在一些实施例中，存储芯片包括多条位线(Bit Line，简称BL)、多条字线(Word Line，简称WL)以及多个存储单元，其中，每个存储单元与相对应的一条字线WL连接和一条位线BL连接。
参照图1，图1为本申请实施例提供的一种存储芯片的布局示意图。
在一些实施例中，以DRAM存储器中的一个Bank为例，多条位线可以划分为128个位线组，每个位线组中具有8条位线，为了方便下文的描述，将每个位线组中的位线记为BL0、BL1、BL2……BL7。，多条字线可以划分为8192个字线组，每个字线组中具有8条字线，为了方便下文的描述，将每个位线组中的位线记为WL0、WL1、WL2……WL7。
多个存储单元P11～P88呈矩阵分布，其中，第一列的存储单元均与字线WL0连接，第二列的存储单元均与字线WL1连接，依次类推，第八列的存储单元均与字线WL7连接；第一行的存储单元均与位线BL0连接，第二行的存储单元均与位线BL1连接，以此类推，第八行的存储单元均与位线BL7连接，使得每个存储单元均与一条字线WL和一条位线BL连接。
参照图2，图2为本申请实施例提供的一种存储芯片的存储单元的结构示意图。
在一些实施例中，每个存储单元10均包括一个晶体管12和一个电容器11，晶体管12的栅极与字线WL连接，晶体管12的源极与位线BL连接，晶体管12的漏极与电容器11连接，需要说明的是，晶体管12的源极也可以与电容器11连接，相应地，晶体管12的漏极与位线BL连接。
在一些实施例中，当字线WL上的信号导通开关晶体管T时，数据线BL可以向存储电容C写入高电平信号“1”，当字线WL上的信号关断开关晶体管T后，存储电容C上的电荷随时间慢慢泄漏。存储电容C从高电平信号“1”漏电到低电平信号“0”之间的时间即为存储电容C的数据存储时间。其中，存储电容C的数据存储时间需要大于预设的时间，才能实现动态随机存取存储器的动态存储功能。
参照图3，图3为本申请实施例中提供的一种存储芯片的测试方法的流程示意图。在一种可行的实施方式中，该存储芯片的测试方法包括：
S301、在待测存储芯片的存储单元中写入测试数据。
其中，待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，和/或，待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间。
S302、从上述存储单元中读取存储数据。
S303、根据上述测试数据与存储数据，生成待测存储芯片的测试结果。
在一些实施例中，上述待测存储芯片以DRAM为例，将位线预充电电压(VBLP)调低至小于DRAM的标准位线预充电电压，可以为DRAM创造较差的工作条件，减小了信号裕量(Signal Margin)，让DRAM中失效的存储单元更容易暴露。
将感测延迟时间(Sensing Delay Time，简称SDT)调低至小于DRAM的标准感测延迟时间，同样可以为DRAM创造较差的工作条件，减小了电荷分享(ΔV)，让DRAM中失效的存储单元更容易暴露。
在一种可行的实施方式中，可以将位线预充电电压调低至标准位线预充电电压的P％，其中0<P<1。
在一种可行的实施方式中，可以将感测延迟时间调低至标准感测延迟时间的Q％，其中0<Q<1。
在一些实施例中，可以只调节待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压。
在一些实施例中，可以只调节待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间。
在一些实施例中，可以调节待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，同时也调节待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间。
本申请实施例中所提供的存储芯片的测试方法，在将位线预充电电压调低，和/或，将感测延迟时间调低的前提下，对待测存储芯片的存储单元中写入测试数据，然后读取各存储单元中的存储数据，通过比较上述测试数据与存储数据，即可确定出上述测存储芯片的各存储单元中是否存在失效的存储单元，可以应用于检测存储芯片中因存储低电平“0”失效而造成失效的存储单元。
基于上述实施例中描述的内容，在一些实施例中，还可以调节待测存储芯片当前的写入时序参数小于待测存储芯片的标准写入时序参数，和/或，调节待测存储芯片当前的读取时序参数小于待测存储芯片的标准读取时序参数。
在一些实施例中，上述写入时序参数可以为待测存储芯片的写入恢复时间(Write Recovery Time，简称TWR)；上述读取时序参数为待测存储芯片的行预充电有效周期(Row Precharge Time，简称TRP)。
其中，DRAM接收完数据后，需要一定的时间将数据写入到DRAM各存储单元中，这个时间定义为TWR。该值说明在一个激活的存储阵列(bank)中完成有效的写操作及预充电前，必须等待多少个时钟周期。这段必须的时钟周期用来确保在预充电发生前，写缓冲中的数据可以被写进内存单元中。
其中，TRP是DRAM中从预充电命令(PRE)到下一条字线的激活命令(ACT)之间的时间，用于表征了DRAM阵列恢复到预充电状态的速度，尤其是阵列中位线从高电平或低电平充电至中间电位所需要的时间。
其中，缩短待测存储芯片的写入恢复时间，相当于是为待测存储芯片制造了写入不充分的条件。缩短待测存储芯片的行预充电有效周期，相当于是为待测存储芯片制造了读入不足的条件。
在一种可行的实施方式中，可以将写入恢复时间调低至标准写入恢复时间的R％，其中0<R<1。
在一种可行的实施方式中，可以将行预充电有效周期调低至标准行预充电有效周期的S％，其中0<S<1。
在一些实施例中，可以只缩短待测存储芯片的写入恢复时间，或者只缩短待测存储芯片的行预充电有效周期。
在一些实施例中，可以同时缩短待测存储芯片的写入恢复时间与待测存储芯片的行预充电有效周期。
在一些实施例中，可以在调节待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，和/或调节待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间的前提下，缩短待测存储芯片的写入恢复时间和/或待测存储芯片的行预充电有效周期。
示例性的，在一种可行的实施方式中，可以调节待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，以及调节待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间，为待测存储芯片创造较差的工作条件；同时，缩短待测存储芯片的写入恢复时间的前提下，在待测存储芯片的存储单元中写入测试数据，制造出写入不充分的条件；然后在缩短待测存储芯片的行预充电有效周期的前提下，从上述存储单元中读取存储数据，制造出读取不足的条件。比较读取存储数据与写入的测试数据是否一致，如果一致，则表示待测存储芯片不存在失效的存储单元；如果不一致，则表示待测存储芯片存在失效的存储单元。
可以理解的是，在一些实施例中，可以降低上述位线预充电电压、感测延迟时间、写入时序参数、读取时序参数中的任意一种，或者任意两种、任意三种等，本申请实施例对各种组合不再赘述。
本申请实施例中所提供的存储芯片的测试方法，为待测存储芯片创造较差的工作条件后，在缩短写入恢复时间的情况下去写入存储数据，在缩短行预充电有效周期的情况下，从上述存储单元中读取存储数据，可以为检测出因存储低电平“0”失效而造成失效的存储单元创造双重恶劣的条件，使因存储低电平“0”失效而造成失效的存储单元更容易暴露，从而能够有效提示检测结果的准确性。
基于上述实施例中所描述的内容，在一些实施例中，上述待测存储芯片包括多列存储单元，每一列存储单元采用一个或者多个检测周期，在待测存储芯片的存储单元中写入测试数据时，可以在处于同一个检测周期内的存储单元中写入测试数据，同理，在从存储单元中读取存储数据时，也从处于同一个检测周期内的存储单元中读取存储数据。
可选地，上述待测存储芯片的各列存储单元可以沿X轴方向，按照遍历的形式进行测试。
在一些实施例中，上述待测存储芯片包括多行存储单元，每一行存储单元采用一个或者多个检测周期；在待测存储芯片的存储单元中写入测试数据时，可以在处于同一个检测周期内的存储单元中写入测试数据；同理， 在从存储单元中读取存储数据时，也从处于同一个检测周期内的存储单元中读取存储数据。
可选地，上述待测存储芯片的各列存储单元可以沿Y轴方向，按照遍历的形式进行测试。
在一些实施例中，上述测试数据为具有相等数据位的多个二进制序列，且每个二进制序列具有不同的数据拓扑。
可选地，可以按照以下方式确定上述测试数据：
以上述测试数据中的任意一个或多个数据位为转换位，对上述测试数据进行遍历访问，并将遍历访问到的转换位的数据进行翻转，直至遍历完上述测试数据中的每个二进制序列。
在一些实施例中，上述待测存储芯片各行上述存储单元或者各列上述存储单元的位数大于上述测试数据的位数。
在一些实施例中，上述待测存储芯片各行上述存储单元或者各列上述存储单元的位数为上述测试数据的位数的整数倍。
在一些实施例中，上述测试数据包括多个二进制序列，且每个二进制序列中有且只有一个数据位为0。
为了更好的理解，参照图4，图4为本申请实施例中提供的测试数据中多个数据拓扑示意图。
在图4，上述测试数据的位数均为8位，每个二进制序列中有且只有一个数据位为0。
本申请实施例中所提供的存储芯片的测试方法，采用以上形式的二进制序列作为测试数据，可以有效的检测出存储芯片中失效的存储单元。
在一些实施例中，在待测存储芯片的存储单元中写入测试数据之前，向待测存储芯片的每个存储单元写入数据1，且在测试完之后，向待测存储芯片的每个存储单元回存1。
在一种可行的实施方式中，参照图5，图5为本申请实施例中提供的一种存储芯片的测试方法的流程示意图。上述存储芯片的测试方法包括：
步骤1：沿Y轴方向遍历待测存储芯片的存储单元，并向遍历到的存储单元中写入1。
步骤2：沿Y轴方向遍历待测存储芯片的存储单元，并读取遍历到的存储单元中存储的数据。
步骤3：确定步骤2中读取到的数据是否均为1；若读取到的数据均为 1，则继续执行步骤4，若读取到的数据中存在0，则确定待测存储芯片中存在失效的存储单元，且该失效的存储单元为读取到的数据为0的存储单元。
步骤4：缩短待测存储芯片当前的位线预充电电压，和/或，感测延迟时间。
步骤5：在缩短写入时序参数的前提下，沿X轴方向遍历待测存储芯片的一列存储单元，并在遍历到的一列存储单元中写入一个二进制序列。
步骤6：在缩短读取时序参数的前提下，沿X轴方向遍历待测存储芯片的一列存储单元，并读取遍历到的一列存储单元中存储的二进制序列。
其中，在读取遍历到的一列存储单元中存储的二进制序列之后，在当前遍历到的一列存储单元中写入1。
重复步骤5～步骤6，遍历待测存储芯片的每一列存储单元。
步骤7：遍历其它剩余的二进制序列，重复执行步骤1～步骤6。
本实施例中，在遍历完所有的二进制序列之后，根据写入的测试数据与读取到的存储数据，生成待测存储芯片的测试结果。
在一种可行的实施方式中，可以对比测试数据与存储数据，并根据对比结果确定待测存储芯片的存储单元是否发生读写错误；其中，若待测存储芯片的存储单元发生读写错误，则根据对比结果确定发生读写错误的位数；根据待测存储芯片的存储单元是否发生读写错误的确定结果，生成待测存储芯片的测试结果。
为了更好的理解本申请实施例，参照图6，图6为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图一。
在图6中，以DRAM存储器中的一个Bank为例，多条位线可以划分为128个位线组，每个位线组中具有8条位线，为了方便下文的描述，将每个位线组中的位线记为BL0、BL1、BL2……BL7。
多条字线可以划分为8192个字线组，每个字线组中具有8条字线，为了方便下文的描述，将每个位线组中的位线记为WL0、WL1、WL2……WL7。
多个存储单元呈矩阵分布，其中，第一列的存储单元均与字线WL0连接，第二列的存储单元均与字线WL1连接，依次类推，第八列的存储单元均与字线WL7连接；第一行的存储单元均与位线BL0连接，第二行的存储单元均与位线BL1连接，以此类推，第八行的存储单元均与位线BL7连接，使得每个存储单元均与一条字线WL和一条位线BL连接。
在一些实施例中，预先调节待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，以及调节待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间，为待测存储芯片创造较差的工作条件；在此工作条件下，调节待测存储芯片当前的写入时序参数小于待测存储芯片的标准写入时序参数后，沿X轴方向遍历待测存储芯片每个字线(WL0、WL1、WL2……WL7)，在每个字线的一组位线(BL0、BL1、BL2……BL7)对应的一列存储单元中写入一个二进制序列(举例拓扑0)：01111111。之后，调节待测存储芯片当前的读取时序参数小于待测存储芯片的标准读取时序参数，读取遍历到的一列存储单元中存储的数据。
参照图7，图7为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图二。
在图7中，在沿X轴方向遍历完一行位线组之后，按照同样的操作方式，开始遍历第二行位线组，在第二行位线组的每一列存储单元中写入上述二进制序列(拓扑0)：01111111，直至最后一行位线组中的最后一列存储单元。
参照图8，图8为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图三。
在遍历完所有的位线组之后，按照同样的操作方式，沿X轴方向遍历待测存储芯片每个字线(WL0、WL1、WL2……WL7)，在每个字线的一组位线(BL0、BL1、BL2……BL7)对应的一列存储单元中写入一个二进制序列(举例拓扑1)：10111111。之后，调节待测存储芯片当前的读取时序参数小于待测存储芯片的标准读取时序参数，读取遍历到的一列存储单元中存储的数据。
参照图9，图9为本申请实施例中提供的一种存储芯片的测试方法的数据写入流程示意图四。
在图9中，在沿X轴方向遍历完一行位线组之后，按照同样的操作方式，开始遍历第二行位线组，在第二行位线组的每一列存储单元中写入上述二进制序列(举例拓扑1)：10111111，直至最后一行位线组中的最后一列存储单元。
按照以上方式，遍历完测试数据中的所有二进制序列之后，对比上述测试数据与从待测存储芯片中读取到的存储数据，可以得到待测存储芯片 的测试结果。
本申请实施例中所提供的存储芯片的测试方法，通过调节待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，和/或，待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间，可以使存储芯片处于较差的工作环境下；进一步的，通过在待测存储芯片当前的写入时序参数小于标准写入时序参数的条件下，在待测存储芯片的存储单元中写入测试数据，在待测存储芯片当前的读取时序参数小于标准读取时序参数的条件下，从存储单元中读取存储数据，可以使存储芯片中存在的失效存储单元更容易暴露，根据上述测试数据与读取到的存储数据，可以准确检测出存储芯片是否存在失效的存储单元，进而提升存储芯片的良率。
基于上述实施例中所描述的内容，本申请实施例中还提供一种存储芯片的测试装置。参照图10，图10为本申请实施例中提供的一种存储芯片的测试装置的程序模块示意图，该存储芯片的测试装置包括：
写入模块1001，用于在待测存储芯片的存储单元中写入测试数据。
读取模块1002，用于从上述存储单元中读取存储数据。
处理模块1003，用于根据上述测试数据与上述存储数据，生成待测存储芯片的测试结果。
其中，上述待测存储芯片当前的位线预充电电压小于上述待测存储芯片的标准位线预充电电压，和/或，上述待测存储芯片当前的感测延迟时间小于上述待测存储芯片的标准感测延迟时间。
本申请实施例中所提供的存储芯片的测试装置，由于待测存储芯片当前的位线预充电电压小于待测存储芯片的标准位线预充电电压，和/或，待测存储芯片当前的感测延迟时间小于待测存储芯片的标准感测延迟时间，使存储芯片处于较差的工作环境下，因此可以使存储芯片中存在的异常更容易暴露，从而准确检测出存储芯片是否存在异常，进而提升存储芯片的良率。
在一种可行的实施方式中，上述待测存储芯片当前的写入时序参数小于待测存储芯片的标准写入时序参数，和/或，上述待测存储芯片当前的读取时序参数小于待测存储芯片的标准读取时序参数。
在一种可行的实施方式中，上述写入时序参数为所述待测存储芯片的写入恢复时间；上述读取时序参数为待测存储芯片的行预充电有效周期。
在一种可行的实施方式中，上述待测存储芯片包括多列存储单元，每一列存储单元采用一个或者多个检测周期。
写入模块1001用于：在处于同一个检测周期内的存储单元中写入测试数据。
读取模块1002用于：从处于同一个检测周期内的存储单元中读取存储数据。
在一种可行的实施方式中，上述待测存储芯片的各列存储单元按照遍历的形式进行测试；其中，上述遍历的方向为X轴方向。
在一种可行的实施方式中，上述待测存储芯片包括多行存储单元，每一行存储单元采用一个或者多个检测周期。
写入模块1001用于：在处于同一个检测周期内的存储单元中写入测试数据。
读取模块1002用于：从处于同一个检测周期内的存储单元中读取存储数据。
在一种可行的实施方式中，上述待测存储芯片的各行存储单元按照遍历的形式进行测试；其中，上述遍历的方向为Y轴方向。
在一种可行的实施方式中，上述测试数据为具有相等数据位的多个二进制序列，且每个上述二进制序列具有不同的数据拓扑。
在一种可行的实施方式中，还包括测试数据生成模块，用于按照以下方式确定所述测试数据：
以上述测试数据中的任意一个或多个数据位为转换位，对上述测试数据进行遍历访问，并将遍历访问到的转换位的数据进行翻转，直至遍历完上述测试数据中的每个二进制序列。
在一种可行的实施方式中，各行上述存储单元或者各列存储单元的位数大于所述测试数据的位数。
在一种可行的实施方式中，各行上述存储单元或者各列存储单元的位数为上述测试数据的位数的整数倍。
在一种可行的实施方式中，上述测试数据包括多个二进制序列，且每个二进制序列中有且只有一个数据位为0。
在一种可行的实施方式中，处理模块1003用于：
对比所述测试数据与存储数据，并根据对比结果确定所述待测存储芯片的存储单元是否发生读写错误；其中，若待测存储芯片的存储单元发生 读写错误，则根据所述对比结果确定发生读写错误的位数；根据所述待测存储芯片的存储单元是否发生读写错误的确定结果，生成所述待测存储芯片的测试结果。
在一种可行的实施方式中，写入模块1001还用于：
在待测存储芯片的存储单元中写入测试数据之前，向待测存储芯片的每个存储单元写入数据1。
在一种可行的实施方式中，读取模块1002还用于：在根据测试数据与存储数据，生成待测存储芯片的测试结果之后，向待测存储芯片的每个存储单元回存1。
需要说明的是，本申请实施例中写入模块1001、读取模块1002、处理模块，具体执行的内容可以参阅图1至图9所示实施例中相关内容，此处不做赘述。
进一步的，基于上述实施例中所描述的内容，本申请实施例中还提供了一种电子设备，该电子设备包括至少一个处理器和存储器；其中，存储器存储计算机执行指令；上述至少一个处理器执行存储器存储的计算机执行指令，以实现如上述实施例中描述的存储芯片的测试方法中的各个步骤，本实施例此处不再赘述。
为了更好的理解本申请实施例，参照图11，图11为本申请实施例提供的一种电子设备的硬件结构示意图。
如图11所示，本实施例的电子设备110包括：处理器1101以及存储器1102；其中：
存储器1102，用于存储计算机执行指令；
处理器1101，用于执行存储器存储的计算机执行指令，以实现上述实施例中描述的存储芯片的测试方法中的各个步骤，本实施例此处不再赘述。
可选地，存储器1102既可以是独立的，也可以跟处理器1101集成在一起。
当存储器1102独立设置时，该设备还包括总线1103，用于连接所述存储器1102和处理器1101。
进一步的，基于上述实施例中所描述的内容，本申请实施例中还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，以实现如上述实施例中描述的存储芯片的测试方法中的各个步骤，本实施例此处不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述模块集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(英文：processor)执行本申请各个实施例所述方法的部分步骤。
应理解，上述处理器可以是中央处理单元(英文：Central Processing Unit，简称：CPU)，还可以是其他通用处理器、数字信号处理器(英文：Digital Signal Processor，简称：DSP)、专用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合申请所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
存储器可能包含高速RAM存储器，也可能还包括非易失性存储NVM，例如至少一个磁盘存储器，还可以为U盘、移动硬盘、只读存储器、磁盘或光盘等。
总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外部设备互连(Peripheral Component，PCI)总线或扩展工业标准 体系结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，本申请附图中的总线并不限定仅有一根总线或一种类型的总线。
上述存储介质可以是由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。存储介质可以是通用或专用计算机能够存取的任何可用介质。
一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于专用集成电路(Application Specific Integrated Circuits，简称：ASIC)中。当然，处理器和存储介质也可以作为分立组件存在于电子设备或主控设备中。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (18)

  1. 一种存储芯片的测试方法，所述方法包括：
    在待测存储芯片的存储单元中写入测试数据；
    从所述存储单元中读取存储数据；
    根据所述测试数据与所述存储数据，生成所述待测存储芯片的测试结果；
    其中，所述待测存储芯片当前的位线预充电电压小于所述待测存储芯片的标准位线预充电电压，和/或，所述待测存储芯片当前的感测延迟时间小于所述待测存储芯片的标准感测延迟时间。
  2. 根据权利要求1所述的方法，其中，所述待测存储芯片当前的写入时序参数小于所述待测存储芯片的标准写入时序参数，和/或，所述待测存储芯片当前的读取时序参数小于所述待测存储芯片的标准读取时序参数。
  3. 根据权利要求2所述的方法，其中，所述写入时序参数为所述待测存储芯片的写入恢复时间；所述读取时序参数为所述待测存储芯片的行预充电有效周期。
  4. 根据权利要求1所述的方法，其中，所述待测存储芯片包括多列存储单元，每一列存储单元采用一个或者多个检测周期；
    所述在待测存储芯片的存储单元中写入测试数据，包括：
    在处于同一个检测周期内的存储单元中写入测试数据；
    所述从所述存储单元中读取存储数据，包括：
    从处于同一个检测周期内的存储单元中读取存储数据。
  5. 根据权利要求4所述的方法，其中，所述待测存储芯片的各列存储单元按照遍历的形式进行测试；其中，所述遍历的方向为X轴方向。
  6. 根据权利要求1所述的方法，其中，所述待测存储芯片包括多行存储单元，每一行存储单元采用一个或者多个检测周期；
    所述在待测存储芯片的存储单元中写入测试数据，包括：
    在处于同一个检测周期内的存储单元中写入测试数据；
    所述从所述存储单元中读取存储数据，包括：
    从处于同一个检测周期内的存储单元中读取存储数据。
  7. 根据权利要求6所述的方法，其中，所述待测存储芯片的各行存储单元按照遍历的形式进行测试；其中，所述遍历的方向为Y轴方向。
  8. 根据权利要求1所述的方法，其中，所述测试数据为具有相等数据位的多个二进制序列，且每个所述二进制序列具有不同的数据拓扑。
  9. 根据权利要求8所述的方法，其中，还包括：
    按照以下方式确定所述测试数据：
    以所述测试数据中的任意一个或多个数据位为转换位，对所述测试数据进行遍历访问，并将遍历访问到的转换位的数据进行翻转，直至遍历完所述测试数据中的每个二进制序列。
  10. 根据权利要求8所述的方法，其中，各行所述存储单元或者各列所述存储单元的位数大于所述测试数据的位数。
  11. 根据权利要求8所述的方法，其中，各行所述存储单元或者各列所述存储单元的位数为所述测试数据的位数的整数倍。
  12. 根据权利要求1所述的方法，其中，所述测试数据包括多个二进制序列，且每个所述二进制序列中有且只有一个数据位为0。
  13. 根据权利要求1所述的方法，其中，所述根据所述测试数据与所述存储数据，生成所述待测存储芯片的测试结果，包括：
    对比所述测试数据与所述存储数据，并根据对比结果确定所述待测存储芯片的存储单元是否发生读写错误；其中，若所述待测存储芯片的存储单元发生读写错误，则根据所述对比结果确定发生读写错误的位数；
    根据所述待测存储芯片的存储单元是否发生读写错误的确定结果，生成所述待测存储芯片的测试结果。
  14. 根据权利要求1所述的方法，其中，所述在待测存储芯片的存储单元中写入测试数据之前，还包括：
    将所述待测存储芯片的每个存储单元写入数据1。
  15. 根据权利要求1所述的方法，其中，所述根据所述测试数据与所述存储数据，生成所述待测存储芯片的测试结果之后，还包括：
    将所述待测存储芯片的每个存储单元回存1。
  16. 一种存储芯片的测试装置，所述装置包括：
    写入模块，用于在待测存储芯片的存储单元中写入测试数据；
    读取模块，用于从所述存储单元中读取存储数据；
    处理模块，用于根据所述测试数据与所述存储数据，生成所述待测存储芯片的测试结果；
    其中，所述待测存储芯片当前的位线预充电电压小于所述待测存储芯 片的标准位线预充电电压，和/或，所述待测存储芯片当前的感测延迟时间小于所述待测存储芯片的标准感测延迟时间。
  17. 一种电子设备，包括：至少一个处理器和存储器；
    所述存储器存储计算机执行指令；
    所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如权利要求1至15任一项所述的存储芯片的测试方法。
  18. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如权利要求1至15任一项所述的存储芯片的测试方法。
PCT/CN2022/081819 2022-01-19 2022-03-18 存储芯片的测试方法及设备 WO2023137855A1 (zh)

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CN1551223A (zh) * 2003-04-30 2004-12-01 海力士半导体有限公司 具有用于控制位线感测界限时间的存储装置
CN104810062A (zh) * 2015-05-12 2015-07-29 东南大学 一种sram芯片的puf特性测试方法及装置
CN112542199A (zh) * 2020-12-30 2021-03-23 深圳市芯天下技术有限公司 检测flash存储出错的方法、电路、存储介质和终端

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Publication number Priority date Publication date Assignee Title
CN1551223A (zh) * 2003-04-30 2004-12-01 海力士半导体有限公司 具有用于控制位线感测界限时间的存储装置
CN104810062A (zh) * 2015-05-12 2015-07-29 东南大学 一种sram芯片的puf特性测试方法及装置
CN112542199A (zh) * 2020-12-30 2021-03-23 深圳市芯天下技术有限公司 检测flash存储出错的方法、电路、存储介质和终端

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