WO2023135929A1 - Package - Google Patents

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Publication number
WO2023135929A1
WO2023135929A1 PCT/JP2022/042698 JP2022042698W WO2023135929A1 WO 2023135929 A1 WO2023135929 A1 WO 2023135929A1 JP 2022042698 W JP2022042698 W JP 2022042698W WO 2023135929 A1 WO2023135929 A1 WO 2023135929A1
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WO
WIPO (PCT)
Prior art keywords
optical
chips
substrate
chip
package according
Prior art date
Application number
PCT/JP2022/042698
Other languages
French (fr)
Japanese (ja)
Inventor
修一 岡
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Publication date
Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Publication of WO2023135929A1 publication Critical patent/WO2023135929A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management

Definitions

  • This technology is related to packaging. Specifically, the present technology relates to a package capable of mounting multiple chips.
  • multiple optical chips mounted on a package are sometimes installed so as to satisfy relative positional relationships. For example, two side portions of the ceramic package are brought into contact with two contact portions of a manufacturing jig, respectively, and a plurality of light emitting/receiving elements are installed in predetermined regions of the ceramic package based on the contact portions of the manufacturing jig. A method for doing so has been proposed (see, for example, Patent Document 1).
  • This technology was created in view of this situation, and aims to make it possible to design the heat dissipation properties of multiple chips mounted in a single package separately.
  • the present technology has been made to solve the above-described problems.
  • the package includes a plurality of plate members respectively provided at positions where the openings are closed, and a plurality of chips mounted on the plurality of plate members, at least a part of which is located in each of the openings. This brings about an effect that the heat dissipation properties of the plurality of chips are individually set while aligning the reference surfaces of the plurality of chips.
  • the plate material may be made of metal or resin mixed with filler. This brings about an effect that the thermal conductivity of the plate material is higher than that of the substrate.
  • the plate material may have a coefficient of thermal expansion closer to that of the chip than that of the substrate.
  • At least one of the plurality of plate members may differ from the other plate members in at least one of plate thickness and material.
  • a Peltier element may be provided between at least one of the plurality of chips and the plate on which the chip is mounted. This provides an effect of cooling the chip according to the chip type.
  • the first side surface may further include a heat sink provided on the back side of at least one of the plurality of plate members. This brings about an effect that the heat dissipation of the chip is improved according to the type of the chip.
  • first side surface may further include a connector provided upright on the back surface of the substrate. This brings about the effect that the package is electrically connected without increasing the installation area of the package.
  • the chip may include an optical chip on which an optical element is formed. This brings about an effect that the heat dissipation properties of the plurality of optical chips are individually set while aligning the optical reference planes of the plurality of optical chips.
  • At least one of the plurality of optical chips may be of a different type from the other optical chips. This brings about the effect of providing multiple optical functions while using a single package.
  • a lens that converges light onto the optical chip and a housing that is fastened to the substrate and supports the lens on the optical chip may be further provided. This brings about the effect that the lens and the optical chip are integrated.
  • the second side surface includes a substrate provided with a plurality of openings, a plurality of chips at least partially positioned within the openings, and the plurality of chips mounted separately from each other. and a plate material having high thermal conductivity, having gaps between respective mounting regions of the plurality of chips, and provided at positions where the plurality of openings are blocked. This brings about an effect that the heat dissipation properties of the plurality of chips are individually set while aligning the reference surfaces of the plurality of chips.
  • the material of the plate material may be metal or resin mixed with filler. This brings about an effect that the thermal conductivity of the plate material is higher than that of the substrate.
  • the plate material may have a coefficient of thermal expansion closer to that of the chip than that of the substrate.
  • the thickness of the plate material at at least one position of the plurality of openings may be different from the thickness of the plate material at other opening positions.
  • the device may further include a Peltier element provided between at least one of the plurality of chips and a plate material at the mounting position of the chip. This provides an effect of cooling the chip according to the chip type.
  • a heat sink may be provided on the rear surface side of the plate member at at least one position of the plurality of openings. This brings about an effect that the heat dissipation of the chip is improved according to the type of the chip.
  • the second side surface may further include a connector provided upright on the back surface of the substrate. This brings about the effect that the package is electrically connected without increasing the installation area of the package.
  • the chip may include an optical chip on which an optical element is formed. This brings about an effect that the heat dissipation properties of the plurality of optical chips are individually set while aligning the optical reference planes of the plurality of optical chips.
  • At least one of the plurality of optical chips may be of a different type from the other optical chips. This brings about the effect of providing multiple optical functions while using a single package.
  • a lens that condenses light onto the optical chip and a housing that is fastened to the substrate and supports the lens on the optical chip may be further provided. This brings about the effect that the lens and the optical chip are integrated.
  • FIG. 1 is a diagram showing a configuration example of a package according to a first embodiment
  • FIG. 4A to 4C are cross-sectional views showing an example of a method for manufacturing the package according to the first embodiment
  • FIG. 11 is a cross-sectional view showing a configuration example of a package according to a second embodiment
  • FIG. 11 is a cross-sectional view showing a configuration example of a package according to a third embodiment
  • FIG. 11 is a cross-sectional view showing a configuration example of a package according to a fourth embodiment
  • FIG. 11 is a cross-sectional view showing a configuration example of a package according to a fifth embodiment
  • FIG. 11 is a cross-sectional view showing a configuration example of a package according to a sixth embodiment
  • FIG. 21 is a diagram illustrating a configuration example of a package according to a seventh embodiment
  • FIG. 21 is a diagram illustrating a configuration example of a package according to a seventh embodiment
  • First Embodiment Example in which a plurality of optical chips are individually mounted on a plurality of heat sinks provided in a single package
  • Second Embodiment Example in which a plurality of heat sinks provided in a single package have mutually different plate thicknesses
  • Third Embodiment Example of providing a common lens for a plurality of optical chips mounted in a single package
  • Fourth embodiment an example in which a lens is individually provided for each of a plurality of optical chips mounted in a single package
  • FIG. 1 is a cross-sectional view showing a configuration example of a package according to the first embodiment.
  • a is a cross-sectional view showing a configuration example of the package 100 cut in the vertical direction
  • b is a plan view showing a configuration example of the heat sinks 111 and 112
  • c is the package 100.
  • 1 is a plan view showing a configuration example of FIG. A in the same figure is cut along the A1-A2 line of c in the same figure.
  • the package 100 includes a substrate 101 and heat sinks 111 and 112 .
  • Substrate 101 is provided with a plurality of openings 181 and 182 .
  • Radiator plates 111 and 112 are provided on the back side of substrate 101 at positions where openings 181 and 182 are blocked.
  • An optical chip 121 is mounted on the heat sink 111 and an optical chip 122 is mounted on the heat sink 112 . At this time, at least portions of the optical chips 121 and 122 are positioned within the openings 181 and 182, respectively.
  • the periphery of optical chips 121 and 122 may be surrounded by openings 181 and 182, respectively.
  • solder may be used, metal paste may be used, or diffusion bonding using a metal such as Cu may be used.
  • Components other than the optical chips 121 and 122 may be mounted on the heat sinks 111 and 112, respectively. At this time, the back surface of the substrate 101 can be used as an optical reference plane for the optical chips 121 and 122 .
  • the optical device may be a solid-state imaging device such as a CCD (Charged Coupled Device) or CMOS (Complementary Metal-Oxide Semiconductor).
  • the light received by the solid-state imaging device may be visible light, near-infrared light (NIR: Near InfraRed), short-wave infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, X-rays, or the like.
  • NIR Near InfraRed
  • SWIR Short Wavelength InfraRed
  • the optical element may be a light receiving element such as PD (Photo Diode), or a light emitting element such as LD (Laser Diode), LED (Light Emitting Diode) or VCSEL (Vertical Cavity Surface Emitting Laser).
  • the optical elements may be MEMS (Micro Electro Mechanical Systems) elements such as optical switches and mirror devices.
  • the optical elements formed on the optical chips 121 and 122 may be of the same type, or may be of different types. Examples of different types of optical elements formed on the optical chips 121 and 122 include, for example, a solid-state imaging device in which the optical element formed in the optical chip 121 is sensitive to visible light, and an optical element formed in the optical chip 122. may be a solid-state imaging device sensitive to near-infrared light.
  • the material used for the base material of the optical chips 121 and 122 may be a semiconductor such as Si, GaAs or InGaAsP, or a dielectric such as LiNbO 3 , glass or transparent resin.
  • a Si substrate is used for the optical chip 121
  • a solid-state imaging device sensitive to near-infrared light is formed on the optical chip 122.
  • An InGaAs substrate can be used for the chip 122 .
  • the substrate 101 for example, an organic substrate or a ceramic substrate can be used. Wiring and pad electrodes can be formed on the substrate 101 .
  • the substrate 101 may be an interposer substrate, a printed substrate, or a buildup substrate. Also, a terminal electrically connected to the connector 102 may be formed on the substrate 101 .
  • the width W1 of each of the heat sinks 111 and 112 can be made equal to the width W2 of the substrate 101. At this time, the widthwise end positions of the heat sinks 111 and 112 and the widthwise end position of the substrate 101 can be aligned with each other.
  • the radiator plates 111 and 112 can be attached to the back side of the substrate 101 via an adhesive, for example.
  • an adhesive for example, insulating resin such as epoxy resin can be used.
  • Heat sinks 111 and 112 can be made of a material with higher thermal conductivity than substrate 101 . Moreover, it is preferable that the thermal expansion coefficients of the heat sinks 111 and 112 be closer to those of the optical chips 121 and 122 than that of the substrate 101 .
  • the thermal expansion coefficient may be a linear expansion coefficient or a volume expansion coefficient.
  • the material of heat sinks 111 and 112 may be metal or resin mixed with filler. Depending on the types of optical chips 121 and 122, the materials of heat sinks 111 and 112 may be different from each other. For example, if Si substrates are used for the optical chips 121 and 122, CuW or Invar can be used as the metal forming the radiator plates 111 and 112. FIG. Alternatively, CFRP (Carbon Fiber Reinforced Plastics) can be used as the filler-mixed resin.
  • the thermal expansion coefficients of the heat sinks 111 and 112 can be adjusted to those of the optical chips 121 and 122 by adjusting the content of carbon fiber mixed in CFRP.
  • the coefficient of thermal expansion can be approximated.
  • the radiator plates 111 and 112 are an example of the plate material described in the claims.
  • a connector 102 is provided on the back side of the substrate 101 .
  • Connector 102 may be positioned between heat sinks 111 and 112 or adjacent to each heat sink 111 and 112 .
  • the connector 102 can be fixed to the substrate 101 upright on the back surface of the substrate 101 .
  • the connector 102 may be adhered to the back surface of the substrate 101 via an adhesive.
  • the terminals of connector 102 may be electrically connected to substrate 101, for example, based on soldering.
  • the height of the connector 102 in the normal direction from the back surface of the substrate 101 can be higher than the height of the heat sinks 111 and 112 in the normal direction from the back surface of the substrate 101 .
  • a projecting electrode such as a bump electrode or a pillar electrode may be used instead of the connector 102 .
  • each of the optical chips 121 and 122 has color filters 131 and 132 and on-chip lenses 141 and 142 as indicated by a in FIG. may be provided for each pixel.
  • Each of the color filters 131 and 132 may form, for example, a Bayer array.
  • Each optical chip 121 and 122 is electrically connected to the substrate 101 via bonding wires 151 and 152, respectively.
  • the material of the bonding wires 151 and 152 may be Au or Al, for example.
  • a cover glass 171 and 172 is provided on each optical chip 121 and 122 .
  • Each cover glass 171 and 172 can be supported on substrate 101 via spacers 161 and 162 .
  • Materials for the cover glasses 171 and 172 may be different from each other according to the types of the optical chips 121 and 122 .
  • the cover Quartz may be used as the material of the glass 171 .
  • Resin for example, can be used as the material of each spacer 161 and 162 .
  • a filler may be mixed into the resin to increase the strength of each spacer 161 and 162 .
  • the height of each spacer 161 and 162 can be set so that cover glasses 171 and 172 do not contact bonding wires 151 and 152 .
  • insulating resin such as epoxy resin can be used for bonding the cover glasses 171 and 172 to the spacers 161 and 162 and bonding the spacers 161 and 162 to the substrate 101.
  • insulating resin such as epoxy resin can be used for bonding the cover glasses 171 and 172 to the spacers 161 and 162 and bonding the spacers 161 and 162 to the substrate 101 .
  • each cover glass 171 and 172 may be removable from the substrate 101 .
  • a pressure-sensitive adhesive whose adhesive force is rapidly reduced by ultraviolet irradiation may be used for adhesion between the cover glasses 171 and 172 and the spacers 161
  • the heat sinks 111 and 112 and the substrate 101 are provided with fastening holes 191 to 193, respectively.
  • the fastening holes 191 to 193 can be provided at both ends in the width direction of each of the radiator plates 111 and 112 and the substrate 101 .
  • Fastening holes 191 to 193 can be used to fasten a lens-supporting housing to the substrate 101 .
  • optical chips 121 and 122 are CMOS image sensors.
  • Such optical chips 121 and 122 can be used, for example, in fields such as appreciation, transportation, home appliances, medicine, healthcare, security, beauty, sports, and agriculture.
  • the optical chips 121 and 122 can be applied to devices that take images for viewing, such as digital cameras, smart phones, and mobile phones with camera functions. can.
  • the optical chips 121 and 122 are used as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, recognition of the driver's state, and the like. It can be applied to a device that captures an image for use in transportation. Alternatively, in the field of transportation, the optical chips 121 and 122 may be applied to devices used for transportation, such as surveillance cameras that monitor running vehicles and roads, and ranging sensors that measure distances between vehicles. good.
  • the optical chips 121 and 122 are devices provided in home appliances such as television receivers, refrigerators, and air conditioners, for example, to capture user gestures and operate devices according to the gestures. can be applied to
  • the optical chips 121 and 122 can be applied to medical and health care devices such as endoscopes and devices for imaging blood vessels by receiving infrared light. can.
  • the optical chips 121 and 122 can be applied, for example, to security devices such as surveillance cameras for crime prevention and cameras for person authentication.
  • the optical chips 121 and 122 can be applied, for example, to devices used for beauty care, such as skin measuring instruments that take images of the skin and microscopes that take images of the scalp.
  • the optical chips 121 and 122 can be applied, for example, to devices used for sports such as action cameras and wearable cameras for sports.
  • the optical chips 121 and 122 can be applied to devices used for agriculture, such as cameras for monitoring the conditions of fields and crops, and the conditions of livestock. can.
  • optical chips 121 and 122 monitor the entry and exit of people into a building, for example, to turn lights on and off or open and close blinds in response to people entering and leaving the building. It can be applied to a device used for illumination and daylighting such as a camera that does the work.
  • the optical chips 121 and 122 are used in the manufacturing industry, for example, as cameras for monitoring the status of products, intermediates or parts on the manufacturing line, or for checking the position of robot arms and the like. It can be applied to the equipment provided.
  • the optical chips 121 and 122 can be applied to devices used in the steel and chemical industries, such as cameras that monitor the temperature, color, and state of reacting substances. .
  • FIG. 2 is a cross-sectional view showing an example of the method of manufacturing the package according to the first embodiment.
  • a plurality of openings 181 and 182 are formed in the substrate 101 as shown in a in the figure. At this time, wirings, electrodes, and the like may be formed on the substrate 101 in regions other than the positions of the openings 181 and 182 .
  • the openings 181 and 182 may be formed by, for example, punching the substrate 101 or cutting the substrate 101 along the contours of the openings 181 and 182 using a blade or laser.
  • heat sinks 111 and 112 are attached to the rear surface of the substrate 101 so that the openings 181 and 182 are closed.
  • An adhesive may be used to attach heat sinks 111 and 112 to the back surface of substrate 101 .
  • the connector 102 is mounted upright on the back surface of the substrate 101 . Soldering may be used to mount connector 102 on the back side of substrate 101 .
  • optical chips 121 and 122 are die-bonded onto the heat sinks 111 and 112, respectively.
  • the respective optical chips 121 and 122 and the substrate 101 are electrically connected with bonding wires 151 and 152 by using wire bonding.
  • each cover glass 171 and 172 is adhered onto the substrate 101 via each spacer 161 and 162 .
  • An adhesive may be used for this adhesion.
  • an adhesive is applied to the tips of the spacers 161 and 162 while the spacers 161 and 162 are adhered to the respective cover glasses 171 and 172, and the spacers 161 and 162 are adhered onto the substrate 101 via the adhesive.
  • the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 that close the openings 181 and 182 provided in the substrate 101, respectively. Accordingly, by installing a single package 100, it is possible to set the heat dissipation properties of the optical chips 121 and 122 separately while aligning the optical reference planes of the optical chips 121 and 122. FIG. Therefore, it is not necessary to install the optical chips 121 and 122 one by one using jigs and measuring instruments for aligning the optical reference planes, and the load for aligning the optical reference planes can be reduced. In addition, it is possible to suppress heat interference between the optical chips 121 and 122 and individually control the temperature of the optical chips 121 and 122, thereby improving the performance of the optical chips 121 and 122 and increasing their reliability. can be improved.
  • the heat sinks 111 and 112 are made of a material whose thermal expansion coefficient is closer to that of the optical chips 121 and 122 than that of the substrate 101 .
  • the stress applied to the optical chips 121 and 122 can be suppressed while separately setting the heat dissipation properties of the optical chips 121 and 122.
  • and 122 can be improved.
  • the performance of the optical chips 121 and 122 is, for example, the resolution of resolution, sensitivity and signal-to-noise ratio (S/N ratio) in a solid-state imaging device.
  • the optical chips 121 and 122 are surrounded by the heat sinks 111 and 112 so as to be surrounded by the substrate 101. can be implemented on Therefore, compared to the case where the optical chips 121 and 122 are mounted on the substrate 101, the mounting positions of the optical chips 121 and 122 can be lowered, and the package 100 can be thinned.
  • the package 100 can be electrically connected to the outside without increasing the installation area of the package 100. connection can be secured.
  • the materials of the heat sinks 111 and 112 are changed according to the types of the optical chips 121 and 122, thereby improving the heat dissipation of the respective optical chips 121 and 122. , the stress applied to each of the optical chips 121 and 122 can be suppressed.
  • Second Embodiment> In the first embodiment described above, the plurality of heat sinks 111 and 112 have the same plate thickness, but in the second embodiment, the plurality of heat sinks have different plate thicknesses.
  • FIG. 3 is a cross-sectional view showing a configuration example of a package according to the second embodiment.
  • the package 200 includes a heat sink 212 instead of the heat sink 112 of the first embodiment.
  • Other configurations of the package 200 of the second embodiment are the same as those of the package 100 of the first embodiment described above.
  • the radiator plate 212 is adhered to the back side of the substrate 101 so as to close the opening 182 .
  • An optical chip 122 is mounted on the heat sink 212 .
  • the plate thickness of the heat sink 212 is different from the plate thickness of the heat sink 111 . That is, the plate thicknesses of the heat sinks 111 and 212 can be set separately in consideration of the heat dissipation properties of the optical chips 121 and 122, respectively.
  • the heat dissipation can be set separately for each of the optical chips 121 and 122. can.
  • the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101, respectively.
  • a lens 321 common to the optical chips 121 and 122 is provided on the optical chips 121 and 122 .
  • FIG. 4 is a cross-sectional view showing a configuration example of a package according to the third embodiment.
  • a in the same figure shows a configuration example corresponding to a position cut along the A1-A2 line of c in FIG. 1
  • b in the same figure is a cut along the B1-B2 line of c in FIG.
  • the package 300 includes a housing 311 and a lens 321 in addition to the package 100 of the first embodiment described above.
  • Other configurations of the package 300 of the third embodiment are the same as those of the package 100 of the first embodiment described above.
  • the lens 321 is provided commonly to the optical chips 121 and 122 .
  • Lens 321 collects the light incident on each of optical chips 121 and 122 .
  • Lens 321 is supported on optical chips 121 and 122 via housing 311 .
  • the housing 311 is fixed on the substrate 101 by being fastened with the substrate 101, for example. At this time, housing 311 can be screwed to substrate 101 by inserting bolts 313 into the bottom surface of housing 311 through fastening holes 191, 193 and fastening holes 192, 193, respectively.
  • the material of the housing 311 may be, for example, stainless steel or aluminum die-cast.
  • the heat sink 111 and the A housing 311 can be used as a heat dissipation path from 112 .
  • the cover glasses 171 and 172 may be removed from the substrate 101 before fastening the housing 311 to the substrate 101.
  • the lens 321 common to the optical chips 121 and 122 is provided on the optical chips 121 and 122 .
  • the optical chips 121 and 122 and the lens 321 can be integrally installed while maintaining the relative positional relationship between the optical chips 121 and 122 and the lens 321. It is possible to reduce the load on installation of packages that satisfy a proper positional relationship. Also, the distance between the optical chips 121 and 122 can be reduced, and the package 300 can be miniaturized.
  • the lenses 321 common to the optical chips 121 and 122 are provided on the optical chips 121 and 122.
  • individual lenses are provided for the optical chips 121 and 122. Provided on each optical chip 121 and 122 .
  • FIG. 5 is a cross-sectional view showing a configuration example of a package according to the fourth embodiment.
  • a package 400 includes a housing 411 and lenses 421 and 422 instead of the housing 311 and lens 321 of the third embodiment described above.
  • Other configurations of the package 400 of the fourth embodiment are the same as those of the package 300 of the above-described third embodiment.
  • the lenses 421 and 422 are individually provided for each of the optical chips 121 and 122. Each lens 421 and 422 collects the light incident on each optical chip 121 and 122 . Each lens 421 and 422 is supported on each optical chip 121 and 122 via housing 411 . The types of lenses 421 and 422 may be different for each optical chip 121 and 122 . If the optical elements formed in the optical chips 121 and 122 are solid-state imaging elements, the lens 421 may be a telephoto lens, and the lens 422 may be a standard or wide-angle lens.
  • each optical chip 121 and 122 for each optical chip 121 and 122 . Accordingly, by installing a single package 400, it is possible to expand the applications of the optical chips 121 and 122 while aligning the optical reference planes of the optical chips 121 and 122. FIG.
  • the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101, respectively.
  • heat sinks are provided which are connected to radiator plates 111 and 112 respectively closing openings 181 and 182 provided in substrate 101 .
  • FIG. 6 is a cross-sectional view showing a configuration example of a package according to the fifth embodiment.
  • a package 500 includes heat sinks 511 and 512 in addition to the package 100 of the first embodiment described above.
  • Other configurations of the package 500 of the fifth embodiment are the same as those of the package 100 of the first embodiment described above.
  • the package 500 is installed on the motherboard 501 .
  • a connector 502 is provided on the motherboard 501 . Plugging connector 102 into connector 502 electrically connects connectors 102 and 502 together.
  • heat sinks 511 and 512 are installed on the motherboard 501 .
  • the material of the heat sinks 511 and 512 is Cu or Al, for example.
  • the heat sink 512 is provided with fins 513 .
  • the heat sink 511 is arranged at a position where it comes into contact with the radiator plate 111 when the connectors 102 and 502 are connected to each other.
  • the heat sink 512 is arranged at a position in contact with the heat sink 112 when the connectors 102 and 502 are connected to each other.
  • the fins 513 of the heat sink 512 are pulled out to the back side of the motherboard 501 .
  • An opening 182 can be provided in the motherboard 501 to pull out the fins 513 of the heat sink 512 to the back side of the motherboard 501 . At this time, the tip surface of the heat sink 512 can be brought into contact with the heat sink 111 through the opening 182 .
  • the heat sinks 511 and 512 connected to the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101 are provided. This makes it possible to improve the heat dissipation of the optical chips 121 and 122 while suppressing an increase in mounting area.
  • the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101, respectively.
  • a Peltier element 123 is provided between the heat sink 112 of the plurality of heat sinks 111 and 112 provided in the package 600 and the optical chip 122 .
  • FIG. 7 is a cross-sectional view showing a configuration example of a package according to the sixth embodiment.
  • a package 600 includes a Peltier element 123 in addition to the package 100 of the first embodiment described above.
  • Other configurations of the package 600 of the sixth embodiment are the same as those of the package 100 of the first embodiment described above.
  • the Peltier element 123 can cool the optical chip 122 .
  • the Peltier element 123 can be provided between the optical chip 122 and the heat sink 112 .
  • the semiconductor element formed on the optical chip 122 may be a solid-state imaging element sensitive to near-infrared light.
  • a solid-state imaging device sensitive to near-infrared light does not need the color filter 132 .
  • the optical chip 122 can be mounted without increasing the installation area of the package 600. Allow to cool.
  • FIG. 8 is a diagram showing a configuration example of a package according to the seventh embodiment.
  • a is a cross-sectional view showing a configuration example of the package 700 cut in the vertical direction
  • b is a plan view showing a configuration example of the heat sink 711
  • c is the configuration of the package 700. It is a top view showing an example. A in the same figure is cut along the A1-A2 line of c in the same figure.
  • a package 700 includes a heat sink 711 instead of the heat sinks 111 and 112 of the first embodiment.
  • Other configurations of the package 700 of the seventh embodiment are the same as those of the package 100 of the first embodiment described above.
  • the heat sink 711 has a mounting area 721 for the optical chip 121 , a mounting area 722 for the optical chip 122 , and a gap 712 . Gap 712 may be located between mounting area 721 and mounting area 722 .
  • a heat sink 711 can be provided on the back side of the substrate 101 so as to close the openings 181 and 182 .
  • Optical chips 121 and 122 are mounted separately on the heat sink 711 . Each optical chip 121 and 122 is at least partially located within openings 181 and 182, respectively.
  • the optical chip 121 is mounted on the mounting area 721 of the heat sink 711 so as to be surrounded by the opening 181
  • the optical chip 122 is mounted on the mounting area 722 of the heat sink 711 so as to be surrounded by the opening 182 .
  • the plate thickness of heat sink 711 may differ at the positions of openings 181 and 182 .
  • a fastening hole 792 is provided in the radiator plate 711 .
  • the fastening holes 792 can be provided at both ends of the heat sink 711 in the width direction.
  • the radiator plate 711 is an example of a plate material described in the claims.
  • the openings 181 and 182 provided in the substrate 101 are closed, and the gap between the mounting area 721 of the optical chip 121 and the mounting area 722 of the optical chip 122 is formed.
  • a plurality of optical chips 121 and 122 are mounted on a single heat sink 711 on which 712 is formed. Accordingly, by installing a single package 700, it is possible to set the heat dissipation properties of the optical chips 121 and 122 separately while aligning the optical reference planes of the optical chips 121 and 122.
  • the gap 712 between the mounting area 721 of the optical chip 121 and the mounting area 722 of the optical chip 122 suppresses heat interference between the optical chips 121 and 122 and controls the temperature of the optical chips 121 and 122. Can be done individually. Therefore, reliability can be improved while improving the performance of the optical chips 121 and 122 .
  • the openings 181 and 182 can be closed by attaching one heat sink 711 to the substrate 101 . Therefore, compared to the method of attaching the plurality of heat sinks 111 and 112 to the substrate 101 of the first embodiment, the number of steps required for attaching the heat sink 711 can be reduced.
  • the plurality of openings provided in the substrate may be arranged in a line or in a matrix.
  • an optical chip package in which an optical element is formed is taken as an example, but a semiconductor chip package in which a semiconductor element other than an optical element is formed may also be used.
  • Semiconductor elements other than optical elements may be, for example, processors, memories, logic circuits or power elements.
  • the optical chip may have, for example, a structure in which an optical chip having a solid-state imaging device is stacked on a semiconductor chip having a logic circuit.
  • the present technology can also have the following configuration.
  • a substrate provided with a plurality of openings; a plurality of plate members each having a higher thermal conductivity than the substrate and provided at a position where the opening is blocked; and a plurality of chips at least partially positioned in the openings and respectively mounted on the plurality of plate members.
  • the material of the plate material is metal or resin mixed with filler.
  • the plate material has a coefficient of thermal expansion closer to that of the chip than that of the substrate.
  • a lens for condensing light onto the optical chip The package according to (8), further comprising a housing that is fastened to the substrate and supports the lens on the optical chip.
  • a substrate provided with a plurality of openings; a plurality of chips each having at least a portion located within the opening; The plurality of chips are mounted separately, have higher thermal conductivity than the substrate, have gaps between respective mounting regions of the plurality of chips, and are located at positions where the plurality of openings are closed.
  • a package comprising a provided plate.
  • a heat sink provided on the back side of the plate member at a position of at least one of the plurality of openings.

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Abstract

The present invention is to enable individual design of heat dissipation properties of a plurality of chips mounted in a single package.　A package (100) comprises: a substrate (101); a plurality of plate members (111, 112); and a plurality of chips (121, 122). The substrate (101) is provided with a plurality of openings (181, 182). The plurality of plate members (111, 112) have higher thermal conductivity than the substrate (101) and are provided at positions where the openings (181, 182) are blocked. The plurality of chips (121, 122) are located at least partially in the openings (181, 182), respectively, and mounted on the plurality of plate members (111, 112), respectively. The chips (121, 122) may include optical chips having optical elements formed thereon. The plates (111, 112) may have a coefficient of thermal expansion closer to the chips (121, 122) than the substrate (101). The material of the plate members (111, 112) may be metal, or resin mixed with a filler.

Description

パッケージpackage
　本技術は、パッケージに関する。詳しくは、本技術は、複数のチップを実装可能なパッケージに関する。 This technology is related to packaging. Specifically, the present technology relates to a package capable of mounting multiple chips.
　光学装置では、パッケージに実装された複数の光学チップが相対的な位置関係を満たすように設置されることがある。例えば、セラミックパッケージの２つの側面部分を製造用の治具の２つの接触部分に各々接触させ、製造用の治具の接触部分を基準にセラミックパッケージの所定の領域に複数の受発光素子を設置する方法が提案されている（例えば、特許文献１参照）。 In an optical device, multiple optical chips mounted on a package are sometimes installed so as to satisfy relative positional relationships. For example, two side portions of the ceramic package are brought into contact with two contact portions of a manufacturing jig, respectively, and a plurality of light emitting/receiving elements are installed in predetermined regions of the ceramic package based on the contact portions of the manufacturing jig. A method for doing so has been proposed (see, for example, Patent Document 1).
特開２０１３－１３１５０９号公報JP 2013-131509 A
　しかしながら、上述の従来技術では、複数の受発光素子がセラミックパッケージのセラミック面上に実装され、各受発光素子の放熱性を別個に設計するのが困難であった。一方、複数の光学チップを別個のパッケージにそれぞれ実装すると、それらの複数の光学チップの相対的な位置関係を満たすようにパッケージを設置する負荷が大きくなるおそれがあった。 However, in the conventional technology described above, a plurality of light emitting/receiving elements are mounted on the ceramic surface of the ceramic package, making it difficult to design the heat dissipation of each light emitting/receiving element separately. On the other hand, if a plurality of optical chips are mounted in separate packages, there is a risk that the load of installing the packages so as to satisfy the relative positional relationship of the plurality of optical chips will increase.
　本技術はこのような状況に鑑みて生み出されたものであり、単一のパッケージに実装された複数のチップの放熱性を別個に設計可能とすることを目的とする。 This technology was created in view of this situation, and aims to make it possible to design the heat dissipation properties of multiple chips mounted in a single package separately.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、複数の開口部が設けられた基板と、上記基板と比べて熱伝導率が高く、上記開口部が塞がれる位置にそれぞれ設けられた複数の板材と、少なくとも一部が上記開口部内にそれぞれ位置し、複数の板材上にそれぞれ実装された複数のチップと、を具備するパッケージである。これにより、複数のチップの基準面を揃えつつ、複数のチップの放熱性が別個に設定されるという作用をもたらす。 The present technology has been made to solve the above-described problems. The package includes a plurality of plate members respectively provided at positions where the openings are closed, and a plurality of chips mounted on the plurality of plate members, at least a part of which is located in each of the openings. This brings about an effect that the heat dissipation properties of the plurality of chips are individually set while aligning the reference surfaces of the plurality of chips.
　また、第１の側面において、上記板材に材料は、金属またはフィラーが混入された樹脂でもよい。これにより、基板と比べて板材の熱伝導率が高くなるという作用をもたらす。 In addition, in the first aspect, the plate material may be made of metal or resin mixed with filler. This brings about an effect that the thermal conductivity of the plate material is higher than that of the substrate.
　また、第１の側面において、上記板材は、上記基板と比べて熱膨張率が上記チップに近くてもよい。これにより、複数のチップの放熱性を別個に設定しつつ、チップにかかる応力が抑制されるという作用をもたらす。 Further, in the first aspect, the plate material may have a coefficient of thermal expansion closer to that of the chip than that of the substrate. As a result, the heat dissipation properties of a plurality of chips can be individually set, and the stress applied to the chips can be suppressed.
　また、第１の側面において、上記複数の板材のうちの少なくとも１つは、板厚および材料の少なくとも１つが他の板材と異なってもよい。これにより、チップの種類が異なる場合においても、各チップの放熱性を向上させつつ、各チップにかかる応力が抑制されるという作用をもたらす。 Further, in the first aspect, at least one of the plurality of plate members may differ from the other plate members in at least one of plate thickness and material. As a result, even when the types of chips are different, the effect of suppressing the stress applied to each chip while improving the heat dissipation of each chip is brought about.
　また、第１の側面において、上記複数のチップのうちの少なくとも１つと、上記チップが実装された板材との間に設けられたペルチェ素子をさらに備えてもよい。これにより、チップの種類に応じてチップが冷却されるという作用をもたらす。 Also, in the first aspect, a Peltier element may be provided between at least one of the plurality of chips and the plate on which the chip is mounted. This provides an effect of cooling the chip according to the chip type.
　また、第１の側面において、上記複数の板材のうちの少なくとも１つの裏面側に設けられたヒートシンクをさらに備えてもよい。これにより、チップの種類に応じてチップの放熱性が向上されるという作用をもたらす。 Further, the first side surface may further include a heat sink provided on the back side of at least one of the plurality of plate members. This brings about an effect that the heat dissipation of the chip is improved according to the type of the chip.
　また、第１の側面において、上記基板の裏面上に直立して設けられたコネクタをさらに備えてもよい。これにより、パッケージの設置面積を増大させることなく、パッケージが電気的に接続されるという作用をもたらす。 Further, the first side surface may further include a connector provided upright on the back surface of the substrate. This brings about the effect that the package is electrically connected without increasing the installation area of the package.
　また、第１の側面において、上記チップは、光学素子が形成された光学チップを含んでもよい。これにより、複数の光学チップの光学基準面を揃えつつ、複数の光学チップの放熱性が別個に設定されるという作用をもたらす。 Also, in the first aspect, the chip may include an optical chip on which an optical element is formed. This brings about an effect that the heat dissipation properties of the plurality of optical chips are individually set while aligning the optical reference planes of the plurality of optical chips.
　また、第１の側面において、上記複数の光学チップのうちの少なくとも１つは、他の光学チップと種類が異なってもよい。これにより、単一のパッケージを用いつつ、複数の光学的な機能が提供されるという作用をもたらす。 Also, in the first aspect, at least one of the plurality of optical chips may be of a different type from the other optical chips. This brings about the effect of providing multiple optical functions while using a single package.
　また、第１の側面において、上記光学チップに光を集光するレンズと、上記基板に締結され、上記レンズを上記光学チップ上で支持する筐体とをさらに備えてもよい。これにより、レンズと光学チップが一体化されるという作用をもたらす。 Further, in the first aspect, a lens that converges light onto the optical chip and a housing that is fastened to the substrate and supports the lens on the optical chip may be further provided. This brings about the effect that the lens and the optical chip are integrated.
　また、第２の側面は、複数の開口部が設けられた基板と、少なくとも一部が上記開口部内にそれぞれ位置する複数のチップと、上記複数のチップが離間して実装され、上記基板と比べて熱伝導率が高く、上記複数のチップのそれぞれの実装領域の間に間隙を有し、上記複数の開口部が塞がれる位置に設けられた板材とを具備するパッケージである。これにより、複数のチップの基準面を揃えつつ、複数のチップの放熱性が別個に設定されるという作用をもたらす。 The second side surface includes a substrate provided with a plurality of openings, a plurality of chips at least partially positioned within the openings, and the plurality of chips mounted separately from each other. and a plate material having high thermal conductivity, having gaps between respective mounting regions of the plurality of chips, and provided at positions where the plurality of openings are blocked. This brings about an effect that the heat dissipation properties of the plurality of chips are individually set while aligning the reference surfaces of the plurality of chips.
　また、第２の側面において、上記板材の材料は、金属またはフィラーが混入された樹脂でもよい。これにより、基板と比べて板材の熱伝導率が高くなるという作用をもたらす。 In addition, in the second aspect, the material of the plate material may be metal or resin mixed with filler. This brings about an effect that the thermal conductivity of the plate material is higher than that of the substrate.
　また、第２の側面において、上記板材は、上記基板と比べて熱膨張率が上記チップに近くてもよい。これにより、複数のチップの放熱性を別個に設定しつつ、チップにかかる応力が抑制されるという作用をもたらす。 Further, in the second aspect, the plate material may have a coefficient of thermal expansion closer to that of the chip than that of the substrate. As a result, the heat dissipation properties of a plurality of chips can be individually set, and the stress applied to the chips can be suppressed.
　また、第２の側面において、上記複数の開口部の少なくとも１つの位置において上記板材の板厚が他の開口部の位置の上記板材の板厚と異なってもよい。これにより、チップの種類が異なる場合においても、各チップの放熱性を向上されるという作用をもたらす。 Further, in the second aspect, the thickness of the plate material at at least one position of the plurality of openings may be different from the thickness of the plate material at other opening positions. As a result, even if the types of chips are different, the effect of improving the heat dissipation of each chip is brought about.
　また、第２の側面において、上記複数のチップのうちの少なくとも１つと、上記チップの実装位置における板材との間に設けられたペルチェ素子をさらに備えてもよい。これにより、チップの種類に応じてチップが冷却されるという作用をもたらす。 Also, in the second aspect, the device may further include a Peltier element provided between at least one of the plurality of chips and a plate material at the mounting position of the chip. This provides an effect of cooling the chip according to the chip type.
　また、第２の側面において、上記複数の開口部の少なくとも１つの位置において上記板材の裏面側に設けられたヒートシンクをさらに備えてもよい。これにより、チップの種類に応じてチップの放熱性が向上されるという作用をもたらす。 Further, on the second side surface, a heat sink may be provided on the rear surface side of the plate member at at least one position of the plurality of openings. This brings about an effect that the heat dissipation of the chip is improved according to the type of the chip.
　また、第２の側面において、上記基板の裏面上に直立して設けられたコネクタをさらに備えてもよい。これにより、パッケージの設置面積を増大させることなく、パッケージが電気的に接続されるという作用をもたらす。 Further, the second side surface may further include a connector provided upright on the back surface of the substrate. This brings about the effect that the package is electrically connected without increasing the installation area of the package.
　また、第２の側面において、上記チップは、光学素子が形成された光学チップを含んでもよい。これにより、複数の光学チップの光学基準面を揃えつつ、複数の光学チップの放熱性が別個に設定されるという作用をもたらす。 Also, in the second aspect, the chip may include an optical chip on which an optical element is formed. This brings about an effect that the heat dissipation properties of the plurality of optical chips are individually set while aligning the optical reference planes of the plurality of optical chips.
　また、第２の側面において、上記複数の光学チップのうちの少なくとも１つは、他の光学チップと種類が異なってもよい。これにより、単一のパッケージを用いつつ、複数の光学的な機能が提供されるという作用をもたらす。 Also, in the second aspect, at least one of the plurality of optical chips may be of a different type from the other optical chips. This brings about the effect of providing multiple optical functions while using a single package.
　また、第２の側面において、上記光学チップに光を集光するレンズと、上記基板に締結され、上記レンズを上記光学チップ上で支持する筐体とをさらに備えてもよい。これにより、レンズと光学チップが一体化されるという作用をもたらす。 Further, in the second aspect, a lens that condenses light onto the optical chip and a housing that is fastened to the substrate and supports the lens on the optical chip may be further provided. This brings about the effect that the lens and the optical chip are integrated.
第１の実施の形態に係るパッケージの構成例を示す図である。1 is a diagram showing a configuration example of a package according to a first embodiment; FIG. 第１の実施の形態に係るパッケージの製造方法の一例を示す断面図である。4A to 4C are cross-sectional views showing an example of a method for manufacturing the package according to the first embodiment; 第２の実施の形態に係るパッケージの構成例を示す断面図である。FIG. 11 is a cross-sectional view showing a configuration example of a package according to a second embodiment; 第３の実施の形態に係るパッケージの構成例を示す断面図である。FIG. 11 is a cross-sectional view showing a configuration example of a package according to a third embodiment; 第４の実施の形態に係るパッケージの構成例を示す断面図である。FIG. 11 is a cross-sectional view showing a configuration example of a package according to a fourth embodiment; 第５の実施の形態に係るパッケージの構成例を示す断面図である。FIG. 11 is a cross-sectional view showing a configuration example of a package according to a fifth embodiment; 第６の実施の形態に係るパッケージの構成例を示す断面図である。FIG. 11 is a cross-sectional view showing a configuration example of a package according to a sixth embodiment; 第７の実施の形態に係るパッケージの構成例を示す図である。FIG. 21 is a diagram illustrating a configuration example of a package according to a seventh embodiment; FIG.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（単一のパッケージに設けられた複数の放熱板に複数の光学チップを個別に実装した例）
　２．第２の実施の形態（単一のパッケージに設けられた複数の放熱板の板厚を互いに異ならせた例）
　３．第３の実施の形態（単一のパッケージに実装された複数の光学チップに共通のレンズを設けた例）
　４．第４の実施の形態（単一のパッケージに実装された複数の光学チップごとに個別にレンズを設けた例）
　５．第５の実施の形態（複数の光学チップが個別に実装された複数の放熱板にヒートシンクを設けた例）
　６．第６の実施の形態（単一のパッケージに設けられた複数の放熱板のうちの１つと光学チップとの間にペルチェ素子を設けた例）
　７．第７の実施の形態（光学チップの実装領域の間に位置する間隙を単一の放熱板に設けた例） Hereinafter, a form for carrying out the present technology (hereinafter referred to as an embodiment) will be described. Explanation will be given in the following order.
1. First Embodiment (Example in which a plurality of optical chips are individually mounted on a plurality of heat sinks provided in a single package)
2. Second Embodiment (Example in which a plurality of heat sinks provided in a single package have mutually different plate thicknesses)
3. Third Embodiment (Example of providing a common lens for a plurality of optical chips mounted in a single package)
4. Fourth embodiment (an example in which a lens is individually provided for each of a plurality of optical chips mounted in a single package)
5. Fifth embodiment (example in which a heat sink is provided on a plurality of radiator plates on which a plurality of optical chips are individually mounted)
6. Sixth Embodiment (Example in which a Peltier element is provided between one of a plurality of heat sinks provided in a single package and an optical chip)
7. Seventh embodiment (an example in which a gap positioned between mounting regions of optical chips is provided in a single heat sink)
　＜１．第１の実施の形態＞
　図１は、第１の実施の形態に係るパッケージの構成例を示す断面図である。なお、同図におけるａは、パッケージ１００を垂直方向に切断した構成例を示す断面図、同図におけるｂは、放熱板１１１および１１２の構成例を示す平面図、同図におけるｃは、パッケージ１００の構成例を示す平面図である。同図におけるａは、同図におけるｃのＡ１－Ａ２線に沿って切断した。 <1. First Embodiment>
FIG. 1 is a cross-sectional view showing a configuration example of a package according to the first embodiment. In the figure, a is a cross-sectional view showing a configuration example of the package 100 cut in the vertical direction, b is a plan view showing a configuration example of the heat sinks 111 and 112, and c is the package 100. 1 is a plan view showing a configuration example of FIG. A in the same figure is cut along the A1-A2 line of c in the same figure.
　同図において、パッケージ１００は、基板１０１と、放熱板１１１および１１２とを備える。基板１０１には、複数の開口部１８１および１８２が設けられている。基板１０１の裏面側には、開口部１８１および１８２が塞がる位置に放熱板１１１および１１２が設けられている。放熱板１１１上には光学チップ１２１が実装され、放熱板１１２上には光学チップ１２２が実装される。このとき、光学チップ１２１および１２２は、その少なくとも一部が開口部１８１および１８２内にそれぞれ位置する。光学チップ１２１および１２２の周囲は、開口部１８１および１８２でそれぞれ囲まれてもよい。各放熱板１１１および１１２上への光学チップ１２１および１２２の実装には、ハンダを用いてもよいし、金属ペーストを用いてもよいし、Ｃｕなどの金属を用いた拡散接合を用いてもよい。各放熱板１１１および１１２上には、光学チップ１２１および１２２以外の他の部品が実装されてもよい。このとき、基板１０１の裏面を光学チップ１２１および１２２の光学基準面とすることができる。 In the figure, the package 100 includes a substrate 101 and heat sinks 111 and 112 . Substrate 101 is provided with a plurality of openings 181 and 182 . Radiator plates 111 and 112 are provided on the back side of substrate 101 at positions where openings 181 and 182 are blocked. An optical chip 121 is mounted on the heat sink 111 and an optical chip 122 is mounted on the heat sink 112 . At this time, at least portions of the optical chips 121 and 122 are positioned within the openings 181 and 182, respectively. The periphery of optical chips 121 and 122 may be surrounded by openings 181 and 182, respectively. For mounting the optical chips 121 and 122 on the respective heat sinks 111 and 112, solder may be used, metal paste may be used, or diffusion bonding using a metal such as Cu may be used. . Components other than the optical chips 121 and 122 may be mounted on the heat sinks 111 and 112, respectively. At this time, the back surface of the substrate 101 can be used as an optical reference plane for the optical chips 121 and 122 .
　光学チップ１２１および１２２には、光学素子が形成される。光学素子は、ＣＣＤ（Charged Coupled Device）またはＣＭＯＳ（Complementary Metal-Oxide Semiconductor）などの固体撮像素子でもよい。固体撮像素子で受光される光は、可視光であってもよいし、近赤外光（ＮＩＲ：Near InfraRed）、短波赤外光（ＳＷＩＲ：Short Wavelength InfraRed）、紫外光またはＸ線などでもよい。光学素子は、ＰＤ（Photo Diode）などの受光素子でもよいし、ＬＤ（Laser Diode）やＬＥＤ（Light Emitting Diode）やＶＣＳＥＬ（Vertical Cavity Surface Emitting Laser）などの発光素子でもよい。光学素子は、光スイッチやミラーデバイスなどのＭＥＭＳ（Micro Electro Mechanical Systems）素子でもよい。光学チップ１２１および１２２に形成される光学素子は、種類が互いに同一でもよいし、種類が互いに異なっていてもよい。光学チップ１２１および１２２に形成される光学素子の種類が互い異なる例として、例えば、光学チップ１２１に形成される光学素子が可視光に感度を有する固体撮像素子、光学チップ１２２に形成される光学素子が近赤外光に感度を有する固体撮像素子でもよい。 Optical elements are formed on the optical chips 121 and 122 . The optical device may be a solid-state imaging device such as a CCD (Charged Coupled Device) or CMOS (Complementary Metal-Oxide Semiconductor). The light received by the solid-state imaging device may be visible light, near-infrared light (NIR: Near InfraRed), short-wave infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, X-rays, or the like. . The optical element may be a light receiving element such as PD (Photo Diode), or a light emitting element such as LD (Laser Diode), LED (Light Emitting Diode) or VCSEL (Vertical Cavity Surface Emitting Laser). The optical elements may be MEMS (Micro Electro Mechanical Systems) elements such as optical switches and mirror devices. The optical elements formed on the optical chips 121 and 122 may be of the same type, or may be of different types. Examples of different types of optical elements formed on the optical chips 121 and 122 include, for example, a solid-state imaging device in which the optical element formed in the optical chip 121 is sensitive to visible light, and an optical element formed in the optical chip 122. may be a solid-state imaging device sensitive to near-infrared light.
　このとき、光学チップ１２１および１２２の基材に用いられる材料は、Ｓｉ、ＧａＡＳまたはＩｎＧａＡｓＰなどの半導体であってもよいし、ＬｉＮｂＯ３、ガラスまたは透明樹脂などの誘電体であってもよい。例えば、可視光に感度を有する固体撮像素子を光学チップ１２１に形成する場合、光学チップ１２１にＳｉ基板を用い、近赤外光に感度を有する固体撮像素子を光学チップ１２２に形成する場合、光学チップ１２２にＩｎＧａＡｓ基板を用いることができる。近赤外光に感度を有する固体撮像素子を光学チップ１２２に形成する場合、感度を維持しつつ、ノイズを低減するために、光学チップ１２２を冷却するのが好ましい。 At this time, the material used for the base material of the optical chips 121 and 122 may be a semiconductor such as Si, GaAs or InGaAsP, or a dielectric such as LiNbO 3 , glass or transparent resin. For example, when forming a solid-state imaging device sensitive to visible light on the optical chip 121, a Si substrate is used for the optical chip 121, and a solid-state imaging device sensitive to near-infrared light is formed on the optical chip 122. An InGaAs substrate can be used for the chip 122 . When a solid-state imaging device sensitive to near-infrared light is formed on the optical chip 122, it is preferable to cool the optical chip 122 in order to reduce noise while maintaining sensitivity.
　基板１０１は、例えば、有機系基板やセラミック基板を用いることができる。基板１０１には、配線およびパッド電極を形成することができる。基板１０１は、インターポーザ基板でもよいし、プリント基板でもよいし、ビルドアップ基板でもよい。また、コネクタ１０２と電気的に接続される端子を基板１０１に形成してもよい。 For the substrate 101, for example, an organic substrate or a ceramic substrate can be used. Wiring and pad electrodes can be formed on the substrate 101 . The substrate 101 may be an interposer substrate, a printed substrate, or a buildup substrate. Also, a terminal electrically connected to the connector 102 may be formed on the substrate 101 .
　各放熱板１１１および１１２の幅Ｗ１は、基板１０１の幅Ｗ２と等しくすることができる。このとき、放熱板１１１および１１２の幅方向の端部の位置と、基板１０１の幅方向の端部の位置は、互いに一致させることができる。放熱板１１１および１１２は、例えば、接着剤を介して基板１０１の裏面側に貼り付けることができる。この接着剤は、例えば、エポキシ樹脂などの絶縁性樹脂を用いることができる。放熱板１１１および１１２は、基板１０１と比べて熱伝導率が高い材料で構成することができる。また、放熱板１１１および１１２は、基板１０１と比べて熱膨張率が光学チップ１２１および１２２に近いことが好ましい。熱膨張率は、線膨張率でもよいし、体積膨張率でもよい。放熱板１１１および１１２の材料は、金属でもよいし、フィラーが混入された樹脂でもよい。光学チップ１２１および１２２の種類に応じて、放熱板１１１および１１２の材料は互いに異なっていてもよい。例えば、光学チップ１２１および１２２にＳｉ基板が用いられるものとすると、放熱板１１１および１１２を構成する金属として、ＣｕＷまたはインバーを用いることができる。あるいは、フィラーが混入された樹脂として、ＣＦＲＰ（Carbon Fiber Reinforced Plastics）を用いることができる。光学チップ１２１および１２２にＳｉ基板以外の基板が用いられる場合においても、ＣＦＲＰに混入される炭素繊維の含有量を調整することにより、放熱板１１１および１１２の熱膨張率を光学チップ１２１および１２２の熱膨張率に近づけることができる。なお、放熱板１１１および１１２は、特許請求の範囲に記載の板材の一例である。 The width W1 of each of the heat sinks 111 and 112 can be made equal to the width W2 of the substrate 101. At this time, the widthwise end positions of the heat sinks 111 and 112 and the widthwise end position of the substrate 101 can be aligned with each other. The radiator plates 111 and 112 can be attached to the back side of the substrate 101 via an adhesive, for example. For this adhesive, for example, insulating resin such as epoxy resin can be used. Heat sinks 111 and 112 can be made of a material with higher thermal conductivity than substrate 101 . Moreover, it is preferable that the thermal expansion coefficients of the heat sinks 111 and 112 be closer to those of the optical chips 121 and 122 than that of the substrate 101 . The thermal expansion coefficient may be a linear expansion coefficient or a volume expansion coefficient. The material of heat sinks 111 and 112 may be metal or resin mixed with filler. Depending on the types of optical chips 121 and 122, the materials of heat sinks 111 and 112 may be different from each other. For example, if Si substrates are used for the optical chips 121 and 122, CuW or Invar can be used as the metal forming the radiator plates 111 and 112. FIG. Alternatively, CFRP (Carbon Fiber Reinforced Plastics) can be used as the filler-mixed resin. Even when substrates other than Si substrates are used for the optical chips 121 and 122, the thermal expansion coefficients of the heat sinks 111 and 112 can be adjusted to those of the optical chips 121 and 122 by adjusting the content of carbon fiber mixed in CFRP. The coefficient of thermal expansion can be approximated. The radiator plates 111 and 112 are an example of the plate material described in the claims.
　基板１０１の裏面側には、コネクタ１０２が設けられている。コネクタ１０２は、放熱板１１１および１１２の間または各放熱板１１１および１１２に隣接して配置することができる。コネクタ１０２は、基板１０１の裏面上に直立して基板１０１に固定することができる。コネクタ１０２は、接着剤を介して基板１０１の裏面に接着してもよい。コネクタ１０２の端子は、例えば、ハンダ付けに基づいて基板１０１と電気的に接続してもよい。基板１０１の裏面からの法線方向のコネクタ１０２の高さは、基板１０１の裏面からの法線方向の放熱板１１１および１１２の高さより高くすることができる。なお、コネクタ１０２に代えて、バンプ電極やピラー電極などの突出電極を用いてもよい。 A connector 102 is provided on the back side of the substrate 101 . Connector 102 may be positioned between heat sinks 111 and 112 or adjacent to each heat sink 111 and 112 . The connector 102 can be fixed to the substrate 101 upright on the back surface of the substrate 101 . The connector 102 may be adhered to the back surface of the substrate 101 via an adhesive. The terminals of connector 102 may be electrically connected to substrate 101, for example, based on soldering. The height of the connector 102 in the normal direction from the back surface of the substrate 101 can be higher than the height of the heat sinks 111 and 112 in the normal direction from the back surface of the substrate 101 . A projecting electrode such as a bump electrode or a pillar electrode may be used instead of the connector 102 .
　可視光に感度を有する固体撮像素子を光学チップ１２１および１２２に形成する場合、各光学チップ１２１および１２２には、同図におけるａに示すように、カラーフィルタ１３１、１３２およびオンチップレンズ１４１、１４２を画素ごとに設けてもよい。各カラーフィルタ１３１、１３２は、例えば、ベイヤ配列を構成してもよい。 When solid-state imaging devices sensitive to visible light are formed on the optical chips 121 and 122, each of the optical chips 121 and 122 has color filters 131 and 132 and on- chip lenses 141 and 142 as indicated by a in FIG. may be provided for each pixel. Each of the color filters 131 and 132 may form, for example, a Bayer array.
　各光学チップ１２１および１２２は、ボンディングワイヤ１５１および１５２をそれぞれ介して基板１０１に電気的に接続される。ボンディングワイヤ１５１および１５２の材料は、例えば、Ａｕでもよいし、Ａｌでもよい。 Each optical chip 121 and 122 is electrically connected to the substrate 101 via bonding wires 151 and 152, respectively. The material of the bonding wires 151 and 152 may be Au or Al, for example.
　各光学チップ１２１および１２２上には、カバーガラス１７１および１７２が設けられる。各カバーガラス１７１および１７２は、スペーサ１６１および１６２を介して基板１０１上に支持することができる。カバーガラス１７１および１７２の材料は、光学チップ１２１および１２２の種類に応じて互いに異ならせてもよい。例えば、可視光に感度を有する固体撮像素子を光学チップ１２１に形成する場合、カバーガラス１７１の材料にホウケイ酸ガラスを用い、紫外線に感度を有する固体撮像素子を光学チップ１２２に形成する場合、カバーガラス１７１の材料に石英を用いてもよい。 A cover glass 171 and 172 is provided on each optical chip 121 and 122 . Each cover glass 171 and 172 can be supported on substrate 101 via spacers 161 and 162 . Materials for the cover glasses 171 and 172 may be different from each other according to the types of the optical chips 121 and 122 . For example, when forming a solid-state imaging device sensitive to visible light on the optical chip 121, borosilicate glass is used as the material of the cover glass 171, and when forming a solid-state imaging device sensitive to ultraviolet rays on the optical chip 122, the cover Quartz may be used as the material of the glass 171 .
　各スペーサ１６１および１６２の材料は、例えば、樹脂を用いることができる。各スペーサ１６１および１６２の強度を上げるために、フィラーが樹脂に混入されてもよい。各スペーサ１６１および１６２の高さは、カバーガラス１７１および１７２がボンディングワイヤ１５１および１５２に接触しないように設定することができる。各カバーガラス１７１および１７２と各スペーサ１６１および１６２との接着および各スペーサ１６１および１６２と基板１０１との接着には、例えば、エポキシ樹脂などの絶縁性樹脂を用いることができる。なお、各カバーガラス１７１および１７２は、基板１０１から取り外し可能であってもよい。このとき、各カバーガラス１７１および１７２と各スペーサ１６１および１６２との接着には、例えば、紫外線照射に基づいて粘着力が急激に低下する粘着剤を用いてもよい。 Resin, for example, can be used as the material of each spacer 161 and 162 . A filler may be mixed into the resin to increase the strength of each spacer 161 and 162 . The height of each spacer 161 and 162 can be set so that cover glasses 171 and 172 do not contact bonding wires 151 and 152 . For bonding the cover glasses 171 and 172 to the spacers 161 and 162 and bonding the spacers 161 and 162 to the substrate 101, for example, insulating resin such as epoxy resin can be used. Note that each cover glass 171 and 172 may be removable from the substrate 101 . At this time, for adhesion between the cover glasses 171 and 172 and the spacers 161 and 162, for example, a pressure-sensitive adhesive whose adhesive force is rapidly reduced by ultraviolet irradiation may be used.
　各放熱板１１１および１１２および基板１０１には、締結穴１９１乃至１９３がそれぞれ設けられている。各締結穴１９１乃至１９３は、各放熱板１１１および１１２および基板１０１のそれぞれの幅方向の両端に設けることができる。締結穴１９１乃至１９３は、レンズを支持する筐体を基板１０１に締結するために用いることができる。 The heat sinks 111 and 112 and the substrate 101 are provided with fastening holes 191 to 193, respectively. The fastening holes 191 to 193 can be provided at both ends in the width direction of each of the radiator plates 111 and 112 and the substrate 101 . Fastening holes 191 to 193 can be used to fasten a lens-supporting housing to the substrate 101 .
　以下、光学チップ１２１および１２２に形成された光学素子がＣＭＯＳイメージセンサである場合の適用分野の例について説明する。このような光学チップ１２１および１２２は、例えば、鑑賞、交通、家電、医療、ヘルスケア、セキュリティ、美容、スポーツ、農業などの分野で用いることができる。 An example of an application field in which the optical elements formed on the optical chips 121 and 122 are CMOS image sensors will be described below. Such optical chips 121 and 122 can be used, for example, in fields such as appreciation, transportation, home appliances, medicine, healthcare, security, beauty, sports, and agriculture.
　具体的には、鑑賞の分野においては、光学チップ１２１および１２２は、例えば、デジタルカメラ、スマートフォンまたはカメラ機能付きの携帯電話機などの鑑賞の用に供される画像を撮像する装置に適用することができる。 Specifically, in the field of viewing, the optical chips 121 and 122 can be applied to devices that take images for viewing, such as digital cameras, smart phones, and mobile phones with camera functions. can.
　交通の分野では、光学チップ１２１および１２２は、例えば、自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮像する車載用センサなどの交通の用に供される画像を撮像する装置に適用することができる。あるいは、交通の分野では、光学チップ１２１および１２２は、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサなどの交通の用に供される装置に適用してもよい。 In the field of transportation, the optical chips 121 and 122 are used as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, recognition of the driver's state, and the like. It can be applied to a device that captures an image for use in transportation. Alternatively, in the field of transportation, the optical chips 121 and 122 may be applied to devices used for transportation, such as surveillance cameras that monitor running vehicles and roads, and ranging sensors that measure distances between vehicles. good.
　家電の分野では、光学チップ１２１および１２２は、例えば、ユーザのジェスチャを撮像し、そのジェスチャに従った機器操作を行うために、テレビ受像機、冷蔵庫またはエアーコンディショナなどの家電に供される装置に適用することができる。 In the field of home appliances, the optical chips 121 and 122 are devices provided in home appliances such as television receivers, refrigerators, and air conditioners, for example, to capture user gestures and operate devices according to the gestures. can be applied to
　医療・ヘルスケアの分野では、光学チップ１２１および１２２は、例えば、内視鏡や赤外光の受光による血管撮像を行う装置などの医療やヘルスケアの用に供される装置に適用することができる。 In the field of medical care and health care, the optical chips 121 and 122 can be applied to medical and health care devices such as endoscopes and devices for imaging blood vessels by receiving infrared light. can.
　セキュリティの分野では、光学チップ１２１および１２２は、例えば、防犯用途の監視カメラや人物認証用途のカメラなどのセキュリティの用に供される装置に適用することができる。 In the field of security, the optical chips 121 and 122 can be applied, for example, to security devices such as surveillance cameras for crime prevention and cameras for person authentication.
　美容の分野では、光学チップ１２１および１２２は、例えば、肌を撮像する肌測定器や頭皮を撮像するマイクロスコープなどの美容の用に供される装置に適用することができる。 In the field of beauty care, the optical chips 121 and 122 can be applied, for example, to devices used for beauty care, such as skin measuring instruments that take images of the skin and microscopes that take images of the scalp.
　スポーツの分野では、光学チップ１２１および１２２は、例えば、スポーツ用途等向けのアクションカメラやウェアラブルカメラなどのスポーツの用に供される装置に適用することができる。 In the field of sports, the optical chips 121 and 122 can be applied, for example, to devices used for sports such as action cameras and wearable cameras for sports.
　農業・牧畜の分野では、光学チップ１２１および１２２は、例えば、畑や作物の状態を監視したり、家畜の状態を監視したりするカメラなどの農業の用に供される装置に適用することができる。 In the fields of agriculture and livestock, the optical chips 121 and 122 can be applied to devices used for agriculture, such as cameras for monitoring the conditions of fields and crops, and the conditions of livestock. can.
　照明・採光の分野では、光学チップ１２１および１２２は、例えば、建物内への人物の出入りに応じて照明のオン／オフやブラインドの開閉を実施するために、建物内への人物の出入りを監視するカメラなどの照明・採光の用に供される装置に適用することができる。 In the field of lighting and daylighting, optical chips 121 and 122 monitor the entry and exit of people into a building, for example, to turn lights on and off or open and close blinds in response to people entering and leaving the building. It can be applied to a device used for illumination and daylighting such as a camera that does the work.
　製造業の分野では、光学チップ１２１および１２２は、例えば、製造ライン上の製品、中間体または部品の状態を監視したり、ロボットアームなどの位置を確認したりするカメラなどの製造業の用に供される装置に適用することができる。 In the field of manufacturing, the optical chips 121 and 122 are used in the manufacturing industry, for example, as cameras for monitoring the status of products, intermediates or parts on the manufacturing line, or for checking the position of robot arms and the like. It can be applied to the equipment provided.
　製鉄・化学工業の分野では、光学チップ１２１および１２２は、例えば、反応中の物質の温度や色や状態を監視するカメラなどの製鉄・化学工業の用に供される装置に適用することができる。 In the field of the steel and chemical industries, the optical chips 121 and 122 can be applied to devices used in the steel and chemical industries, such as cameras that monitor the temperature, color, and state of reacting substances. .
　図２は、第１の実施の形態に係るパッケージの製造方法の一例を示す断面図である。 FIG. 2 is a cross-sectional view showing an example of the method of manufacturing the package according to the first embodiment.
　同図におけるａに示すように、複数の開口部１８１および１８２を基板１０１に形成する。このとき、基板１０１には、開口部１８１および１８２の位置以外の領域に配線および電極などが形成されてもよい。開口部１８１および１８２の形成方法は、例えば、基板１０１の打ち抜きでもよいし、ブレードまたはレーザなどを用いて開口部１８１および１８２に輪郭に沿って基板１０１を切断してもよい。 A plurality of openings 181 and 182 are formed in the substrate 101 as shown in a in the figure. At this time, wirings, electrodes, and the like may be formed on the substrate 101 in regions other than the positions of the openings 181 and 182 . The openings 181 and 182 may be formed by, for example, punching the substrate 101 or cutting the substrate 101 along the contours of the openings 181 and 182 using a blade or laser.
　次に、同図におけるｂに示すように、各開口部１８１および１８２が塞がれるように基板１０１の裏面に放熱板１１１および１１２を貼り付ける。基板１０１の裏面に放熱板１１１および１１２を貼り付けるために、接着剤を用いてもよい。 Next, as shown in b in the figure, heat sinks 111 and 112 are attached to the rear surface of the substrate 101 so that the openings 181 and 182 are closed. An adhesive may be used to attach heat sinks 111 and 112 to the back surface of substrate 101 .
　次に、同図におけるｃに示すように、基板１０１の裏面上にコネクタ１０２を直立させて実装する。基板１０１の裏面上にコネクタ１０２を実装するために、ハンダ付けを用いてもよい。 Next, as shown in c in the figure, the connector 102 is mounted upright on the back surface of the substrate 101 . Soldering may be used to mount connector 102 on the back side of substrate 101 .
　次に、同図におけるｄに示すように、各放熱板１１１および１１２上に光学チップ１２１および１２２をそれぞれダイボンドする。 Next, as indicated by d in the figure, optical chips 121 and 122 are die-bonded onto the heat sinks 111 and 112, respectively.
　次に、同図におけるｅに示すように、ワイヤボンディングを用いることにより、各光学チップ１２１および１２２と基板１０１とをボンディングワイヤ１５１および１５２にて電気的に接続する。 Next, as shown by e in the figure, the respective optical chips 121 and 122 and the substrate 101 are electrically connected with bonding wires 151 and 152 by using wire bonding.
　次に、図１に示すように、各スペーサ１６１および１６２を介して各カバーガラス１７１および１７２を基板１０１上に接着する。この接着には、接着剤を用いてもよい。このとき、各カバーガラス１７１および１７２にスペーサ１６１および１６２をそれぞれ接着した状態でスペーサ１６１および１６２を先端に接着剤を塗布し、その接着剤を介してスペーサ１６１および１６２を基板１０１上に接着してもよい。 Next, as shown in FIG. 1, each cover glass 171 and 172 is adhered onto the substrate 101 via each spacer 161 and 162 . An adhesive may be used for this adhesion. At this time, an adhesive is applied to the tips of the spacers 161 and 162 while the spacers 161 and 162 are adhered to the respective cover glasses 171 and 172, and the spacers 161 and 162 are adhered onto the substrate 101 via the adhesive. may
　このように、上述の第１の実施の形態では、基板１０１に設けられた各開口部１８１および１８２を塞ぐ放熱板１１１および１１２上にそれぞれ光学チップ１２１および１２２が実装される。これにより、単一のパッケージ１００を設置することで、光学チップ１２１および１２２の光学基準面を揃えつつ、光学チップ１２１および１２２の放熱性を別個に設定することが可能となる。このため、光学基準面を揃えるための治具や計測器を用いて光学チップ１２１および１２２をひとつずつ設置する必要がなくなり、光学基準面を揃えるのにかかる負荷を低減することが可能となる。また、光学チップ１２１および１２２間での熱の干渉を抑制したり、光学チップ１２１および１２２の温度制御を個別に行うことが可能となり、光学チップ１２１および１２２の性能を向上させつつ、信頼性を向上させることができる。 Thus, in the first embodiment described above, the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 that close the openings 181 and 182 provided in the substrate 101, respectively. Accordingly, by installing a single package 100, it is possible to set the heat dissipation properties of the optical chips 121 and 122 separately while aligning the optical reference planes of the optical chips 121 and 122. FIG. Therefore, it is not necessary to install the optical chips 121 and 122 one by one using jigs and measuring instruments for aligning the optical reference planes, and the load for aligning the optical reference planes can be reduced. In addition, it is possible to suppress heat interference between the optical chips 121 and 122 and individually control the temperature of the optical chips 121 and 122, thereby improving the performance of the optical chips 121 and 122 and increasing their reliability. can be improved.
　また、上述の第１の実施の形態では、基板１０１と比べて熱膨張率が光学チップ１２１および１２２に近い材料で放熱板１１１および１１２を構成する。これにより、光学チップ１２１および１２２の放熱性を別個に設定しつつ、光学チップ１２１および１２２にかかる応力を抑制することができ、光学チップ１２１および１２２の性能の低下を抑制しつつ、光学チップ１２１および１２２の信頼性を向上させることができる。例えば、光学チップ１２１および１２２にかかる応力を抑制することにより、光学チップ１２１および１２２の反りを抑制することができ、光学チップ１２１および１２２の反りに起因する光学チップ１２１および１２２の性能の低下を抑制することができる。光学チップ１２１および１２２の性能は、例えば、固体撮像素子では、分解解像度、感度およびＳ／Ｎ比（Signal-to-Noise ratio）である。 In addition, in the first embodiment described above, the heat sinks 111 and 112 are made of a material whose thermal expansion coefficient is closer to that of the optical chips 121 and 122 than that of the substrate 101 . As a result, the stress applied to the optical chips 121 and 122 can be suppressed while separately setting the heat dissipation properties of the optical chips 121 and 122. , and 122 can be improved. For example, by suppressing the stress applied to the optical chips 121 and 122, the warping of the optical chips 121 and 122 can be suppressed, and the deterioration of the performance of the optical chips 121 and 122 caused by the warping of the optical chips 121 and 122 can be prevented. can be suppressed. The performance of the optical chips 121 and 122 is, for example, the resolution of resolution, sensitivity and signal-to-noise ratio (S/N ratio) in a solid-state imaging device.
　また、上述の第１の実施の形態によれば、放熱板１１１および１１２を基板１０１の裏面側に設けることにより、基板１０１で周囲が囲まれるように光学チップ１２１および１２２を放熱板１１１および１１２上に実装することができる。このため、光学チップ１２１および１２２を基板１０１上に実装した場合に比べて、光学チップ１２１および１２２の実装位置を低くすることができ、パッケージ１００を薄型化することができる。 Further, according to the first embodiment described above, by providing the heat sinks 111 and 112 on the back side of the substrate 101, the optical chips 121 and 122 are surrounded by the heat sinks 111 and 112 so as to be surrounded by the substrate 101. can be implemented on Therefore, compared to the case where the optical chips 121 and 122 are mounted on the substrate 101, the mounting positions of the optical chips 121 and 122 can be lowered, and the package 100 can be thinned.
　また、上述の第１の実施の形態によれば、基板１０１の裏面上にコネクタ１０２を直立させて設けることにより、パッケージ１００の設置面積を増大させることなく、パッケージ１００と外部との電気的な接続を確保することができる。 Further, according to the above-described first embodiment, by providing the connector 102 upright on the back surface of the substrate 101, the package 100 can be electrically connected to the outside without increasing the installation area of the package 100. connection can be secured.
　また、上述の第１の実施の形態によれば、光学チップ１２１および１２２の種類に応じて放熱板１１１および１１２の材料を異ならせることにより、各光学チップ１２１および１２２の放熱性を向上させつつ、各光学チップ１２１および１２２にかかる応力を抑制することができる。 Further, according to the above-described first embodiment, the materials of the heat sinks 111 and 112 are changed according to the types of the optical chips 121 and 122, thereby improving the heat dissipation of the respective optical chips 121 and 122. , the stress applied to each of the optical chips 121 and 122 can be suppressed.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態では複数の放熱板１１１および１１２の板厚を同一としたが、この第２の実施の形態では複数の放熱板の板厚を互いに異ならせる。 <2. Second Embodiment>
In the first embodiment described above, the plurality of heat sinks 111 and 112 have the same plate thickness, but in the second embodiment, the plurality of heat sinks have different plate thicknesses.
　図３は、第２の実施の形態に係るパッケージの構成例を示す断面図である。 FIG. 3 is a cross-sectional view showing a configuration example of a package according to the second embodiment.
　同図において、パッケージ２００は、上述の第１の実施の形態の放熱板１１２に代えて、放熱板２１２を備える。第２の実施の形態のパッケージ２００のそれ以外の構成は、上述の第１の実施の形態のパッケージ１００の構成と同様である。 In the figure, the package 200 includes a heat sink 212 instead of the heat sink 112 of the first embodiment. Other configurations of the package 200 of the second embodiment are the same as those of the package 100 of the first embodiment described above.
　放熱板２１２は、開口部１８２を塞ぐように基板１０１の裏面側に接着される。放熱板２１２上には、光学チップ１２２が実装される。放熱板２１２の板厚は、放熱板１１１の板厚と異なる。すなわち、放熱板１１１および２１２の板厚は、光学チップ１２１および１２２のそれぞれの熱放散性を考慮して別個に設定され得る。 The radiator plate 212 is adhered to the back side of the substrate 101 so as to close the opening 182 . An optical chip 122 is mounted on the heat sink 212 . The plate thickness of the heat sink 212 is different from the plate thickness of the heat sink 111 . That is, the plate thicknesses of the heat sinks 111 and 212 can be set separately in consideration of the heat dissipation properties of the optical chips 121 and 122, respectively.
　このように、上述の第２の実施の形態によれば、複数の放熱板１１１および２１２の板厚を互いに異ならせることにより、光学チップ１２１および１２２ごとに熱放散性を別個に設定することができる。 Thus, according to the second embodiment described above, by making the plate thicknesses of the plurality of heat sinks 111 and 212 different from each other, the heat dissipation can be set separately for each of the optical chips 121 and 122. can.
　＜３．第３の実施の形態＞
　上述の第１の実施の形態では基板１０１に設けられた各開口部１８１および１８２を塞ぐ放熱板１１１および１１２上にそれぞれ光学チップ１２１および１２２を実装した。この第３の実施の形態では光学チップ１２１および１２２に共通のレンズ３２１を光学チップ１２１および１２２上に設ける。 <3. Third Embodiment>
In the first embodiment described above, the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101, respectively. In this third embodiment, a lens 321 common to the optical chips 121 and 122 is provided on the optical chips 121 and 122 .
　図４は、第３の実施の形態に係るパッケージの構成例を示す断面図である。なお、同図におけるａは、図１におけるｃのＡ１－Ａ２線に沿って切断した位置に対応した構成例を示し、同図におけるｂは、図１におけるｃのＢ１－Ｂ２線に沿って切断した位置に対応した構成例を示す。 FIG. 4 is a cross-sectional view showing a configuration example of a package according to the third embodiment. In addition, a in the same figure shows a configuration example corresponding to a position cut along the A1-A2 line of c in FIG. 1, and b in the same figure is a cut along the B1-B2 line of c in FIG. A configuration example corresponding to the position where the
　同図において、パッケージ３００は、上述の第１の実施の形態のパッケージ１００に加えて、筐体３１１およびレンズ３２１を備える。第３の実施の形態のパッケージ３００のそれ以外の構成は、上述の第１の実施の形態のパッケージ１００の構成と同様である。 In the figure, the package 300 includes a housing 311 and a lens 321 in addition to the package 100 of the first embodiment described above. Other configurations of the package 300 of the third embodiment are the same as those of the package 100 of the first embodiment described above.
　レンズ３２１は、光学チップ１２１および１２２に共通に設けられている。レンズ３２１は、各光学チップ１２１および１２２に入射する光を集光する。レンズ３２１は、筐体３１１を介して光学チップ１２１および１２２上に支持される。筐体３１１は、例えば、基板１０１と締結されることで、基板１０１上に固定される。このとき、締結穴１９１、１９３および締結穴１９２、１９３をそれぞれ介してボルト３１３を筐体３１１の底面に侵入させることにより、筐体３１１を基板１０１にネジ止めすることができる。 The lens 321 is provided commonly to the optical chips 121 and 122 . Lens 321 collects the light incident on each of optical chips 121 and 122 . Lens 321 is supported on optical chips 121 and 122 via housing 311 . The housing 311 is fixed on the substrate 101 by being fastened with the substrate 101, for example. At this time, housing 311 can be screwed to substrate 101 by inserting bolts 313 into the bottom surface of housing 311 through fastening holes 191, 193 and fastening holes 192, 193, respectively.
　筐体３１１の材料は、例えば、ステンレス鋼でもよいし、アルミダイキャストでもよい。ここで、図１におけるｂおよびｃに示すように、放熱板１１１および１１２の幅方向の端部の位置と、基板１０１の幅方向の端部の位置を互いに一致させることにより、放熱板１１１および１１２からの放熱経路として筐体３１１を用いることができる。 The material of the housing 311 may be, for example, stainless steel or aluminum die-cast. Here, as shown in b and c in FIG. 1, by aligning the positions of the ends of the heat sinks 111 and 112 in the width direction with the positions of the ends of the substrate 101 in the width direction, the heat sink 111 and the A housing 311 can be used as a heat dissipation path from 112 .
　なお、各カバーガラス１７１および１７２に起因するゴーストの発生を防止するために、筐体３１１を基板１０１に締結する前に、各カバーガラス１７１および１７２を基板１０１から取り外してもよい。 In order to prevent ghosts caused by the cover glasses 171 and 172, the cover glasses 171 and 172 may be removed from the substrate 101 before fastening the housing 311 to the substrate 101.
　このように、上述の第３の実施の形態では、光学チップ１２１および１２２に共通のレンズ３２１を光学チップ１２１および１２２上に設ける。これにより、光学チップ１２１および１２２とレンズ３２１との間の相対的な位置関係を保ちつつ、光学チップ１２１および１２２とレンズ３２１とを一体的に設置することができ、複数の光学部品の相対的な位置関係を満たしたパッケージの設置にかかる負荷を低減できる。また、光学チップ１２１および１２２の間の間隔を小さくすることができ、パッケージ３００を小型化することができる。 Thus, in the third embodiment described above, the lens 321 common to the optical chips 121 and 122 is provided on the optical chips 121 and 122 . As a result, the optical chips 121 and 122 and the lens 321 can be integrally installed while maintaining the relative positional relationship between the optical chips 121 and 122 and the lens 321. It is possible to reduce the load on installation of packages that satisfy a proper positional relationship. Also, the distance between the optical chips 121 and 122 can be reduced, and the package 300 can be miniaturized.
　＜４．第４の実施の形態＞
　上述の第３の実施の形態では光学チップ１２１および１２２に共通のレンズ３２１を光学チップ１２１および１２２上に設けたが、この第４の実施の形態では光学チップ１２１および１２２ごとに個別のレンズを各光学チップ１２１および１２２上に設ける。 <4. Fourth Embodiment>
In the third embodiment described above, the lenses 321 common to the optical chips 121 and 122 are provided on the optical chips 121 and 122. In this fourth embodiment, individual lenses are provided for the optical chips 121 and 122. Provided on each optical chip 121 and 122 .
　図５は、第４の実施の形態に係るパッケージの構成例を示す断面図である。 FIG. 5 is a cross-sectional view showing a configuration example of a package according to the fourth embodiment.
　同図において、パッケージ４００は、上述の第３の実施の形態の筐体３１１およびレンズ３２１に代えて、筐体４１１と、レンズ４２１および４２２とを備える。第４の実施の形態のパッケージ４００のそれ以外の構成は、上述の第３の実施の形態のパッケージ３００の構成と同様である。 In the figure, a package 400 includes a housing 411 and lenses 421 and 422 instead of the housing 311 and lens 321 of the third embodiment described above. Other configurations of the package 400 of the fourth embodiment are the same as those of the package 300 of the above-described third embodiment.
　レンズ４２１および４２２は、光学チップ１２１および１２２ごとに個別に設けられている。各レンズ４２１および４２２は、各光学チップ１２１および１２２に入射する光を集光する。各レンズ４２１および４２２は、筐体４１１を介して各光学チップ１２１および１２２上に支持される。レンズ４２１および４２２の種類は、光学チップ１２１および１２２ごとに異なってもよい。光学チップ１２１および１２２に形成される光学素子が固体撮像素子である場合、レンズ４２１は望遠レンズ、レンズ４２２は標準レンズまたは広角レンズでもよい。 The lenses 421 and 422 are individually provided for each of the optical chips 121 and 122. Each lens 421 and 422 collects the light incident on each optical chip 121 and 122 . Each lens 421 and 422 is supported on each optical chip 121 and 122 via housing 411 . The types of lenses 421 and 422 may be different for each optical chip 121 and 122 . If the optical elements formed in the optical chips 121 and 122 are solid-state imaging elements, the lens 421 may be a telephoto lens, and the lens 422 may be a standard or wide-angle lens.
　このように、上述の第４の実施の形態では、光学チップ１２１および１２２ごとに個別のレンズ４２１および４２２を各光学チップ１２１および１２２上に設ける。これにより、単一のパッケージ４００を設置することにより、光学チップ１２１および１２２の光学基準面を揃えつつ、光学チップ１２１および１２２の用途を拡大することが可能となる。 Thus, in the fourth embodiment described above, individual lenses 421 and 422 are provided on each optical chip 121 and 122 for each optical chip 121 and 122 . Accordingly, by installing a single package 400, it is possible to expand the applications of the optical chips 121 and 122 while aligning the optical reference planes of the optical chips 121 and 122. FIG.
　＜５．第５の実施の形態＞
　上述の第１の実施の形態では基板１０１に設けられた各開口部１８１および１８２を塞ぐ放熱板１１１および１１２上にそれぞれ光学チップ１２１および１２２を実装した。この第５の実施の形態では基板１０１に設けられた各開口部１８１および１８２を塞ぐ放熱板１１１および１１２にそれぞれ接続されたヒートシンクをそれぞれ設ける。 <5. Fifth Embodiment>
In the first embodiment described above, the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101, respectively. In the fifth embodiment, heat sinks are provided which are connected to radiator plates 111 and 112 respectively closing openings 181 and 182 provided in substrate 101 .
　図６は、第５の実施の形態に係るパッケージの構成例を示す断面図である。 FIG. 6 is a cross-sectional view showing a configuration example of a package according to the fifth embodiment.
　同図において、パッケージ５００は、上述の第１の実施の形態のパッケージ１００に加えて、ヒートシンク５１１および５１２を備える。第５の実施の形態のパッケージ５００のそれ以外の構成は、上述の第１の実施の形態のパッケージ１００の構成と同様である。 In the figure, a package 500 includes heat sinks 511 and 512 in addition to the package 100 of the first embodiment described above. Other configurations of the package 500 of the fifth embodiment are the same as those of the package 100 of the first embodiment described above.
　パッケージ５００は、マザーボード５０１上に設置される。マザーボード５０１上には、コネクタ５０２が設けられている。コネクタ１０２をコネクタ５０２に差し込むことにより、コネクタ１０２、５０２が互いに電気的に接続される。 The package 500 is installed on the motherboard 501 . A connector 502 is provided on the motherboard 501 . Plugging connector 102 into connector 502 electrically connects connectors 102 and 502 together.
　また、マザーボード５０１には、ヒートシンク５１１および５１２が設置される。ヒートシンク５１１および５１２の材料は、例えば、ＣｕまたはＡｌである。ヒートシンク５１２には、フィン５１３が設けられている。ヒートシンク５１１は、コネクタ１０２、５０２同士が接続されたときに、放熱板１１１と接触する位置に配置される。ヒートシンク５１２は、コネクタ１０２、５０２同士が接続されたときに、放熱板１１２と接触する位置に配置される。ヒートシンク５１２のフィン５１３は、マザーボード５０１の裏面側に引き出される。ヒートシンク５１２のフィン５１３をマザーボード５０１の裏面側に引き出すために、マザーボード５０１には開口部１８２を設けることができる。このとき、開口部１８２を介してヒートシンク５１２の先端面を放熱板１１１に接触させることができる。 Also, heat sinks 511 and 512 are installed on the motherboard 501 . The material of the heat sinks 511 and 512 is Cu or Al, for example. The heat sink 512 is provided with fins 513 . The heat sink 511 is arranged at a position where it comes into contact with the radiator plate 111 when the connectors 102 and 502 are connected to each other. The heat sink 512 is arranged at a position in contact with the heat sink 112 when the connectors 102 and 502 are connected to each other. The fins 513 of the heat sink 512 are pulled out to the back side of the motherboard 501 . An opening 182 can be provided in the motherboard 501 to pull out the fins 513 of the heat sink 512 to the back side of the motherboard 501 . At this time, the tip surface of the heat sink 512 can be brought into contact with the heat sink 111 through the opening 182 .
　このように、上述の第５の実施の形態によれば、基板１０１に設けられた各開口部１８１および１８２を塞ぐ放熱板１１１および１１２にそれぞれ接続されたヒートシンク５１１および５１２を設ける。これにより、実装面積の増大を抑制しつつ、光学チップ１２１および１２２の放熱性を向上させることが可能となる。 Thus, according to the fifth embodiment described above, the heat sinks 511 and 512 connected to the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101 are provided. This makes it possible to improve the heat dissipation of the optical chips 121 and 122 while suppressing an increase in mounting area.
　なお、上述の第５の実施の形態において、上述の第２の実施の形態乃至第４の実施の形態のいずれかと同様の構成を適用してもよい。また、上述の第５の実施の形態において、上述の第２の実施の形態乃至第４の実施の形態のいずれかを組み合わせて適用してもよい。 In addition, in the above-described fifth embodiment, the same configuration as that of any one of the above-described second to fourth embodiments may be applied. Further, in the fifth embodiment described above, any one of the second to fourth embodiments described above may be combined and applied.
　＜６．第６の実施の形態＞
　上述の第１の実施の形態では基板１０１に設けられた各開口部１８１および１８２を塞ぐ放熱板１１１および１１２上にそれぞれ光学チップ１２１および１２２を実装した。この第６の実施の形態ではパッケージ６００に設けられた複数の放熱板１１１および１１２のうちの放熱板１１２と光学チップ１２２との間にペルチェ素子１２３を設ける。 <6. Sixth Embodiment>
In the first embodiment described above, the optical chips 121 and 122 are mounted on the heat sinks 111 and 112 closing the openings 181 and 182 provided in the substrate 101, respectively. In this sixth embodiment, a Peltier element 123 is provided between the heat sink 112 of the plurality of heat sinks 111 and 112 provided in the package 600 and the optical chip 122 .
　図７は、第６の実施の形態に係るパッケージの構成例を示す断面図である。 FIG. 7 is a cross-sectional view showing a configuration example of a package according to the sixth embodiment.
　同図において、パッケージ６００は、上述の第１の実施の形態のパッケージ１００に加えて、ペルチェ素子１２３を備える。第６の実施の形態のパッケージ６００のそれ以外の構成は、上述の第１の実施の形態のパッケージ１００の構成と同様である。 In the figure, a package 600 includes a Peltier element 123 in addition to the package 100 of the first embodiment described above. Other configurations of the package 600 of the sixth embodiment are the same as those of the package 100 of the first embodiment described above.
　ペルチェ素子１２３は、光学チップ１２２を冷却することができる。ペルチェ素子１２３は、光学チップ１２２と放熱板１１２との間に設けることができる。このとき、光学チップ１２２に形成される半導体素子は、近赤外光に感度を有する固体撮像素子でもよい。近赤外光に感度を有する固体撮像素子では、カラーフィルタ１３２はなくてもよい。 The Peltier element 123 can cool the optical chip 122 . The Peltier element 123 can be provided between the optical chip 122 and the heat sink 112 . At this time, the semiconductor element formed on the optical chip 122 may be a solid-state imaging element sensitive to near-infrared light. A solid-state imaging device sensitive to near-infrared light does not need the color filter 132 .
　このように、上述の第６の実施の形態によれば、放熱板１１２と光学チップ１２２との間にペルチェ素子１２３を設けることにより、パッケージ６００の設置面積を増大させることなく、光学チップ１２２を冷却することができる。 Thus, according to the sixth embodiment described above, by providing the Peltier element 123 between the heat sink 112 and the optical chip 122, the optical chip 122 can be mounted without increasing the installation area of the package 600. Allow to cool.
　なお、上述の第６の実施の形態において、上述の第２の実施の形態乃至第５の実施の形態のいずれかと同様の構成を適用してもよい。また、上述の第６の実施の形態において、上述の第２の実施の形態乃至第５の実施の形態のいずれかを組み合わせて適用してもよい。 It should be noted that, in the sixth embodiment described above, a configuration similar to that of any one of the second to fifth embodiments described above may be applied. Further, in the sixth embodiment described above, any one of the second to fifth embodiments described above may be combined and applied.
　＜７．第７の実施の形態＞
　上述の第１の実施の形態では光学チップ１２１および１２２の放熱性を別個に設定するために、光学チップ１２１および１２２ごとに別個の放熱板１１１および１１２を設けた。この第７の実施の形態では光学チップ１２１および１２２の放熱性を別個に設定するために、各光学チップ１２１および１２２の実装領域間に位置する間隙を単一の放熱板に設ける。 <7. Seventh Embodiment>
In the first embodiment described above, separate heat sinks 111 and 112 are provided for the optical chips 121 and 122 in order to set the heat dissipation of the optical chips 121 and 122 separately. In this seventh embodiment, in order to separately set the heat dissipation properties of the optical chips 121 and 122, a gap positioned between the mounting areas of the respective optical chips 121 and 122 is provided in a single heat sink.
　図８は、第７の実施の形態に係るパッケージの構成例を示す図である。なお、同図におけるａは、パッケージ７００を垂直方向に切断した構成例を示す断面図、同図におけるｂは、放熱板７１１の構成例を示す平面図、同図におけるｃは、パッケージ７００の構成例を示す平面図である。同図におけるａは、同図におけるｃのＡ１－Ａ２線に沿って切断した。 FIG. 8 is a diagram showing a configuration example of a package according to the seventh embodiment. In FIG. 7, a is a cross-sectional view showing a configuration example of the package 700 cut in the vertical direction, b is a plan view showing a configuration example of the heat sink 711, and c is the configuration of the package 700. It is a top view showing an example. A in the same figure is cut along the A1-A2 line of c in the same figure.
　同図において、パッケージ７００は、上述の第１の実施の形態の放熱板１１１および１１２に代えて、放熱板７１１を備える。第７の実施の形態のパッケージ７００のそれ以外の構成は、上述の第１の実施の形態のパッケージ１００の構成と同様である。 In the figure, a package 700 includes a heat sink 711 instead of the heat sinks 111 and 112 of the first embodiment. Other configurations of the package 700 of the seventh embodiment are the same as those of the package 100 of the first embodiment described above.
　放熱板７１１は、光学チップ１２１の実装領域７２１と、光学チップ１２２の実装領域７２２と、間隙７１２とを備える。間隙７１２は、実装領域７２１と、実装領域７２２との間に位置することができる。放熱板７１１は、開口部１８１および１８２を塞ぐように基板１０１の裏面側に設けることができる。放熱板７１１には、光学チップ１２１および１２２が離間して実装される。各光学チップ１２１および１２２は、その少なくとも一部が開口部１８１および１８２内にそれぞれ位置する。このとき、光学チップ１２１は、開口部１８１で囲まれるように放熱板７１１の実装領域７２１上に実装され、光学チップ１２２は、開口部１８２で囲まれるように放熱板７１１の実装領域７２２上に実装される。放熱板７１１の板厚は、開口部１８１および１８２の位置で互いに異なってもよい。また、放熱板７１１には、締結穴７９２が設けられている。締結穴７９２は、放熱板７１１の幅方向の両端に設けることができる。なお、放熱板７１１は、特許請求の範囲に記載の板材の一例である。 The heat sink 711 has a mounting area 721 for the optical chip 121 , a mounting area 722 for the optical chip 122 , and a gap 712 . Gap 712 may be located between mounting area 721 and mounting area 722 . A heat sink 711 can be provided on the back side of the substrate 101 so as to close the openings 181 and 182 . Optical chips 121 and 122 are mounted separately on the heat sink 711 . Each optical chip 121 and 122 is at least partially located within openings 181 and 182, respectively. At this time, the optical chip 121 is mounted on the mounting area 721 of the heat sink 711 so as to be surrounded by the opening 181 , and the optical chip 122 is mounted on the mounting area 722 of the heat sink 711 so as to be surrounded by the opening 182 . Implemented. The plate thickness of heat sink 711 may differ at the positions of openings 181 and 182 . Further, a fastening hole 792 is provided in the radiator plate 711 . The fastening holes 792 can be provided at both ends of the heat sink 711 in the width direction. The radiator plate 711 is an example of a plate material described in the claims.
　このように、上述の第７の実施の形態では、基板１０１に設けられた各開口部１８１および１８２を塞ぐとともに、光学チップ１２１の実装領域７２１と光学チップ１２２の実装領域７２２との間に間隙７１２が形成された単一の放熱板７１１上に複数の光学チップ１２１および１２２が実装される。これにより、単一のパッケージ７００を設置することで、光学チップ１２１および１２２の光学基準面を揃えつつ、光学チップ１２１および１２２の放熱性を別個に設定することが可能となる。 Thus, in the seventh embodiment described above, the openings 181 and 182 provided in the substrate 101 are closed, and the gap between the mounting area 721 of the optical chip 121 and the mounting area 722 of the optical chip 122 is formed. A plurality of optical chips 121 and 122 are mounted on a single heat sink 711 on which 712 is formed. Accordingly, by installing a single package 700, it is possible to set the heat dissipation properties of the optical chips 121 and 122 separately while aligning the optical reference planes of the optical chips 121 and 122. FIG.
　また、光学チップ１２１の実装領域７２１と光学チップ１２２の実装領域７２２との間の間隙７１２により、光学チップ１２１および１２２間での熱の干渉を抑制したり、光学チップ１２１および１２２の温度制御を個別に行うことができる。このため、光学チップ１２１および１２２の性能を向上させつつ、信頼性を向上させることができる。 Also, the gap 712 between the mounting area 721 of the optical chip 121 and the mounting area 722 of the optical chip 122 suppresses heat interference between the optical chips 121 and 122 and controls the temperature of the optical chips 121 and 122. Can be done individually. Therefore, reliability can be improved while improving the performance of the optical chips 121 and 122 .
　また、間隙７１２が形成された放熱板７１１をパッケージ７００に設けることにより、一枚の放熱板７１１を基板１０１に貼り付けることで、開口部１８１および１８２を塞ぐことができる。このため、上述の第１の実施の形態の複数の放熱板１１１および１１２を基板１０１に貼り付ける方法に比べて、放熱板７１１の貼り付けにかかる工程数を減少させることができる。 Also, by providing the package 700 with the heat sink 711 having the gap 712 formed therein, the openings 181 and 182 can be closed by attaching one heat sink 711 to the substrate 101 . Therefore, compared to the method of attaching the plurality of heat sinks 111 and 112 to the substrate 101 of the first embodiment, the number of steps required for attaching the heat sink 711 can be reduced.
　なお、上述の第７の実施の形態において、上述の第２の実施の形態乃至第６の実施の形態のいずれかと同様の構成を適用してもよい。また、上述の第７の実施の形態において、上述の第２の実施の形態乃至第６の実施の形態のいずれかを組み合わせて適用してもよい。 It should be noted that, in the seventh embodiment described above, a configuration similar to that of any one of the second to sixth embodiments described above may be applied. Further, in the above-described seventh embodiment, any one of the above-described second to sixth embodiments may be combined and applied.
　また、上述の実施の形態では、放熱板で塞がれる開口部を１つの基板に２つ設けた例を示したが、放熱板で塞がれる開口部を１つの基板に３つ以上設けてもよい。また、基板に設けられる複数の開口部の配置方法は、複数の開口部を一列に並べてもよいし、複数の開口部をマトリックス状に並べてもよい。 Further, in the above-described embodiments, an example in which two openings blocked by a heat sink are provided in one substrate is shown, but three or more openings blocked by a heat sink are provided in one substrate. good too. In addition, the plurality of openings provided in the substrate may be arranged in a line or in a matrix.
　また、上述の実施の形態では、光学素子が形成された光学チップのパッケージを例にとったが、光学素子以外の半導体素子が形成された半導体チップのパッケージでもよい。光学素子以外の半導体素子は、例えば、プロセッサ、メモリ、ロジック回路またはパワー素子でもよい。光学チップは、例えば、固体撮像素子を備える光学チップが、ロジック回路を備える半導体チップ上に積層された構造でもよい。 In addition, in the above-described embodiments, an optical chip package in which an optical element is formed is taken as an example, but a semiconductor chip package in which a semiconductor element other than an optical element is formed may also be used. Semiconductor elements other than optical elements may be, for example, processors, memories, logic circuits or power elements. The optical chip may have, for example, a structure in which an optical chip having a solid-state imaging device is stacked on a semiconductor chip having a logic circuit.
　また、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。また、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 In addition, the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the scope of claims have corresponding relationships. Similarly, the matters specifying the invention in the scope of claims and the matters in the embodiments of the present technology with the same names have corresponding relationships. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope of the present technology. Also, the effects described herein are merely examples and are not limiting, and other effects may also occur.
　なお、本技術は以下のような構成もとることができる。
（１）複数の開口部が設けられた基板と、
　前記基板と比べて熱伝導率が高く、前記開口部が塞がれる位置にそれぞれ設けられた複数の板材と、
　少なくとも一部が前記開口部内にそれぞれ位置し、前記複数の板材上にそれぞれ実装された複数のチップと
を具備するパッケージ。
（２）前記板材の材料は、金属またはフィラーが混入された樹脂である
前記（１）記載のパッケージ。
（３）前記板材は、前記基板と比べて熱膨張率が前記チップに近い
前記（１）または（２）に記載のパッケージ。
（４）前記複数の板材のうちの少なくとも１つは、板厚および材料の少なくとも１つが他の板材と異なる
前記（１）から（３）のいずれかに記載のパッケージ。
（５）前記複数のチップのうちの少なくとも１つと、前記チップが実装された板材との間に設けられたペルチェ素子をさらに備える前記（１）から（４）のいずれかに記載のパッケージ。
（６）前記複数の板材のうちの少なくとも１つの裏面側に設けられたヒートシンクをさらに備える前記（１）から（５）のいずれかに記載のパッケージ。
（７）前記基板の裏面上に直立して設けられたコネクタをさらに備える前記（１）から（６）のいずれかに記載のパッケージ。
（８）前記チップは、光学素子が形成された光学チップを含む
前記（１）から（７）のいずれかに記載のパッケージ。
（９）前記複数の光学チップのうちの少なくとも１つは、他の光学チップと種類が異なる
前記（８）記載のパッケージ。
（１０）前記光学チップに光を集光するレンズと、
　前記基板に締結され、前記レンズを前記光学チップ上で支持する筐体とをさらに備える前記（８）記載のパッケージ。
（１１）　複数の開口部が設けられた基板と、
　少なくとも一部が前記開口部内にそれぞれ位置する複数のチップと、
　前記複数のチップが離間して実装され、前記基板と比べて熱伝導率が高く、前記複数のチップのそれぞれの実装領域の間に間隙を有し、前記複数の開口部が塞がれる位置に設けられた板材と
を具備するパッケージ。
（１２）前記板材の材料は、金属またはフィラーが混入された樹脂である
前記（１１）記載のパッケージ。
（１３）前記板材は、前記基板と比べて熱膨張率が前記チップに近い
前記（１１）または（１２）に記載のパッケージ。
（１４）前記複数の開口部の少なくとも１つの位置において前記板材の板厚が他の開口部の位置の前記板材の板厚と異なる
前記（１１）から（１３）のいずれかに記載のパッケージ。
（１５）前記複数のチップのうちの少なくとも１つと、前記チップの実装位置における板材との間に設けられたペルチェ素子をさらに備える前記（１１）から（１４）のいずれかに記載のパッケージ。
（１６）前記複数の開口部の少なくとも１つの位置において前記板材の裏面側に設けられたヒートシンクをさらに備える前記（１１）から（１５）のいずれかに記載のパッケージ。
（１７）前記基板の裏面上に直立して設けられたコネクタをさらに備える前記（１１）から（１６）のいずれかに記載のパッケージ。
（１８）前記チップは、光学素子が形成された光学チップを含む
前記（１１）から（１７）のいずれかに記載のパッケージ。
（１９）前記複数の光学チップのうちの少なくとも１つは、他の光学チップと種類が異なる
前記（１８）記載のパッケージ。
（２０）前記光学チップに光を集光するレンズと、
　前記基板に締結され、前記レンズを前記光学チップ上で支持する筐体とをさらに備える前記（１８）記載のパッケージ。 Note that the present technology can also have the following configuration.
(1) a substrate provided with a plurality of openings;
a plurality of plate members each having a higher thermal conductivity than the substrate and provided at a position where the opening is blocked;
and a plurality of chips at least partially positioned in the openings and respectively mounted on the plurality of plate members.
(2) The package according to (1), wherein the material of the plate material is metal or resin mixed with filler.
(3) The package according to (1) or (2), wherein the plate material has a coefficient of thermal expansion closer to that of the chip than that of the substrate.
(4) The package according to any one of (1) to (3), wherein at least one of the plurality of plate members is different from the other plate members in at least one of plate thickness and material.
(5) The package according to any one of (1) to (4) above, further comprising a Peltier element provided between at least one of the plurality of chips and a plate on which the chip is mounted.
(6) The package according to any one of (1) to (5), further comprising a heat sink provided on the back side of at least one of the plurality of plate members.
(7) The package according to any one of (1) to (6), further comprising a connector provided upright on the back surface of the substrate.
(8) The package according to any one of (1) to (7), wherein the chip includes an optical chip having an optical element formed thereon.
(9) The package according to (8), wherein at least one of the plurality of optical chips is of a different type from the other optical chips.
(10) a lens for condensing light onto the optical chip;
The package according to (8), further comprising a housing that is fastened to the substrate and supports the lens on the optical chip.
(11) a substrate provided with a plurality of openings;
a plurality of chips each having at least a portion located within the opening;
The plurality of chips are mounted separately, have higher thermal conductivity than the substrate, have gaps between respective mounting regions of the plurality of chips, and are located at positions where the plurality of openings are closed. A package comprising a provided plate.
(12) The package according to (11), wherein the material of the plate material is metal or resin mixed with filler.
(13) The package according to (11) or (12), wherein the plate material has a coefficient of thermal expansion closer to that of the chip than that of the substrate.
(14) The package according to any one of (11) to (13), wherein the thickness of the plate at at least one position of the plurality of openings is different from the thickness of the plate at the positions of other openings.
(15) The package according to any one of (11) to (14), further comprising a Peltier element provided between at least one of the plurality of chips and a plate material at the mounting position of the chip.
(16) The package according to any one of (11) to (15), further comprising a heat sink provided on the back side of the plate member at a position of at least one of the plurality of openings.
(17) The package according to any one of (11) to (16), further comprising a connector provided upright on the back surface of the substrate.
(18) The package according to any one of (11) to (17), wherein the chip includes an optical chip having an optical element formed thereon.
(19) The package according to (18), wherein at least one of the plurality of optical chips is of a different type from the other optical chips.
(20) a lens for condensing light onto the optical chip;
The package according to (18), further comprising a housing that is fastened to the substrate and supports the lens on the optical chip.
　１００　パッケージ
　１０１　基板
　１０２　コネクタ
　１１１および１１２　放熱属板
　１２１および１２２　光学チップ
　１３１、１３２　カラーフィルタ
　１４１、１４２　オンチップレンズ
　１５１および１５２　ボンディングワイヤ
　１６１および１６２　スペーサ
　１７１および１７２　カバーガラス
　１８１および１８２　開口部
　１９１から１９３　締結穴 100 Package 101 Substrate 102 Connector 111 and 112 Heat Dissipating Metal Plate 121 and 122 Optical Chip 131, 132 Color Filter 141, 142 On- Chip Lens 151 and 152 Bonding Wire 161 and 162 Spacer 171 and 172 Cover Glass 181 and 182 Opening 191 to 193 fastening hole

Claims (20)

  1. 　複数の開口部が設けられた基板と、
    　前記基板と比べて熱伝導率が高く、前記開口部が塞がれる位置にそれぞれ設けられた複数の板材と、
    　少なくとも一部が前記開口部内にそれぞれ位置し、前記複数の板材上にそれぞれ実装された複数のチップと
    を具備するパッケージ。     a substrate provided with a plurality of openings;
    a plurality of plate members each having a higher thermal conductivity than the substrate and provided at a position where the opening is blocked;
    and a plurality of chips at least partially positioned in the openings and respectively mounted on the plurality of plate members.
  2. 　前記板材の材料は、金属またはフィラーが混入された樹脂である
    請求項１記載のパッケージ。     2. The package according to claim 1, wherein the plate material is metal or resin mixed with filler.
  3. 　前記板材は、前記基板と比べて熱膨張率が前記チップに近い
    請求項１記載のパッケージ。     2. The package according to claim 1, wherein said plate material has a coefficient of thermal expansion closer to that of said chip than said substrate.
  4. 　前記複数の板材のうちの少なくとも１つは、板厚および材料の少なくとも１つが他の板材と異なる
    請求項１記載のパッケージ。     2. The package according to claim 1, wherein at least one of the plurality of plate members is different from the other plate members in at least one of plate thickness and material.
  5. 　前記複数のチップのうちの少なくとも１つと、前記チップが実装された板材との間に設けられたペルチェ素子をさらに備える請求項１記載のパッケージ。 The package according to claim 1, further comprising a Peltier element provided between at least one of said plurality of chips and a plate on which said chip is mounted.
  6. 　前記複数の板材のうちの少なくとも１つの裏面側に設けられたヒートシンクをさらに備える請求項１記載のパッケージ。 The package according to claim 1, further comprising a heat sink provided on the back side of at least one of the plurality of plate members.
  7. 　前記基板の裏面上に直立して設けられたコネクタをさらに備える請求項１記載のパッケージ。 The package according to claim 1, further comprising a connector provided upright on the back surface of said substrate.
  8. 　前記チップは、光学素子が形成された光学チップを含む
    請求項１記載のパッケージ。     2. The package according to claim 1, wherein said chip includes an optical chip having an optical element formed thereon.
  9. 　前記複数の光学チップのうちの少なくとも１つは、他の光学チップと種類が異なる
    請求項８記載のパッケージ。     9. The package according to claim 8, wherein at least one of said plurality of optical chips is of a different type from other optical chips.
  10. 　前記光学チップに光を集光するレンズと、
    　前記基板に締結され、前記レンズを前記光学チップ上で支持する筐体とをさらに備える請求項８記載のパッケージ。     a lens for condensing light onto the optical chip;
    9. The package of claim 8, further comprising a housing fastened to said substrate and supporting said lens over said optical chip.
  11. 　複数の開口部が設けられた基板と、
    　少なくとも一部が前記開口部内にそれぞれ位置する複数のチップと、
    　前記複数のチップが離間して実装され、前記基板と比べて熱伝導率が高く、前記複数のチップのそれぞれの実装領域の間に間隙を有し、前記複数の開口部が塞がれる位置に設けられた板材と
    を具備するパッケージ。     a substrate provided with a plurality of openings;
    a plurality of chips each having at least a portion located within the opening;
    The plurality of chips are mounted separately, have higher thermal conductivity than the substrate, have gaps between respective mounting regions of the plurality of chips, and are located at positions where the plurality of openings are closed. A package comprising a provided plate.
  12. 　前記板材の材料は、金属またはフィラーが混入された樹脂である
    請求項１１記載のパッケージ。     12. The package according to claim 11, wherein the plate material is metal or resin mixed with filler.
  13. 　前記板材は、前記基板と比べて熱膨張率が前記チップに近い
    請求項１１記載のパッケージ。     12. The package according to claim 11, wherein said plate material has a coefficient of thermal expansion closer to that of said chip than said substrate.
  14. 　前記複数の開口部の少なくとも１つの位置において前記板材の板厚が他の開口部の位置の前記板材の板厚と異なる
    請求項１１記載のパッケージ。     12. The package according to claim 11, wherein the thickness of the plate material at at least one position of the plurality of openings is different from the thickness of the plate material at other opening positions.
  15. 　前記複数のチップのうちの少なくとも１つと、前記チップの実装位置における板材との間に設けられたペルチェ素子をさらに備える請求項１１記載のパッケージ。 12. The package according to claim 11, further comprising a Peltier element provided between at least one of said plurality of chips and a plate material at a mounting position of said chip.
  16. 　前記複数の開口部の少なくとも１つの位置において前記板材の裏面側に設けられたヒートシンクをさらに備える請求項１１記載のパッケージ。 12. The package according to claim 11, further comprising a heat sink provided on the back surface side of said plate material at at least one position of said plurality of openings.
  17. 　前記基板の裏面上に直立して設けられたコネクタをさらに備える請求項１１記載のパッケージ。 The package according to claim 11, further comprising a connector provided upright on the back surface of said substrate.
  18. 　前記チップは、光学素子が形成された光学チップを含む
    請求項１１記載のパッケージ。     12. The package according to claim 11, wherein said chip includes an optical chip having an optical element formed thereon.
  19. 　前記複数の光学チップのうちの少なくとも１つは、他の光学チップと種類が異なる
    請求項１８記載のパッケージ。     19. The package according to claim 18, wherein at least one of said plurality of optical chips is of a different type from other optical chips.
  20. 　前記光学チップに光を集光するレンズと、
    　前記基板に締結され、前記レンズを前記光学チップ上で支持する筐体とをさらに備える請求項１８記載のパッケージ。     a lens for condensing light onto the optical chip;
    19. The package of claim 18, further comprising a housing fastened to said substrate and supporting said lens over said optical chip.
PCT/JP2022/042698 2022-01-11 2022-11-17 Package WO2023135929A1 (en)

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