WO2023126027A2 - 显示面板的驱动电路 - Google Patents

显示面板的驱动电路 Download PDF

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Publication number
WO2023126027A2
WO2023126027A2 PCT/CN2023/078776 CN2023078776W WO2023126027A2 WO 2023126027 A2 WO2023126027 A2 WO 2023126027A2 CN 2023078776 W CN2023078776 W CN 2023078776W WO 2023126027 A2 WO2023126027 A2 WO 2023126027A2
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WO
WIPO (PCT)
Prior art keywords
pulse width
conduction
frequency
conduction pulse
generates
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PCT/CN2023/078776
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English (en)
French (fr)
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WO2023126027A3 (zh
Inventor
苏忠信
Original Assignee
矽创电子股份有限公司
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Priority to CN202380014519.2A priority Critical patent/CN118355426A/zh
Publication of WO2023126027A2 publication Critical patent/WO2023126027A2/zh
Publication of WO2023126027A3 publication Critical patent/WO2023126027A3/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • the present invention relates to a driving circuit, in particular to a driving circuit of a display panel.
  • Display devices have become necessary equipment for electronic products for displaying information.
  • Display devices have developed from liquid crystal display devices to submillimeter light-emitting diode (Mini LED) display devices and micro light-emitting diode (Micro LED) display devices.
  • a light emitting diode can improve the display quality of a display device.
  • the driving method of the above-mentioned light-emitting diodes in the conventional technology will cause high electromagnetic interference (Electromagnetic Interference, EMI), which will affect the display quality.
  • EMI Electromagnetic Interference
  • the present invention provides a driving circuit for a display panel, which can reduce EMI and improve display quality.
  • An object of the present invention is to provide a driving circuit for a display panel, which changes the frequency of a driving signal for driving a display element during a frame period, so as to reduce electromagnetic interference and improve display quality.
  • the present invention provides a driving circuit of a display panel, which includes a driving signal generating circuit, the driving signal generating circuit generates a driving signal during a frame period to drive a display element of the display panel, and the driving signal has at least one first conduction Pulse width, at least one second conduction pulse width, at least one third conduction pulse width, the first conduction pulse width is greater than the second conduction pulse width and the third conduction pulse width, the second The conduction pulse width is smaller than the third conduction pulse width.
  • the driving signal generation circuit first generates the third conduction pulse width at a time in the frame period, and then generates the first conduction pulse width or the second conduction pulse width successively.
  • the present invention further provides a driving circuit for a display panel, which includes a driving signal generating circuit, and the driving signal generating circuit generates a driving signal during a frame period to drive a display element of the display panel, and the driving signal has at least one first conductive signal.
  • a cut-off pulse width is smaller than a second cut-off pulse width.
  • the present invention also provides a driving circuit for a display panel, which includes a driving signal generating circuit, and the driving signal generating circuit generates a driving signal with a plurality of first conduction pulse widths during an F-1 frame period to drive the display panel a display element, and generate a driving signal with a plurality of second conduction pulse widths during an F frame period to drive the display element.
  • the second on-pulse widths are different from the first on-pulse widths, the time of the F-1 frame period is the same as the F-th frame period, and F is an integer greater than 2.
  • Fig. 1 it is the schematic diagram of an embodiment of the driving framework of the present invention
  • Fig. 2 it is the block diagram of an embodiment of driver and display element of the present invention
  • Fig. 3 it is the block diagram of an embodiment of controller and driver of the present invention.
  • Fig. 4 it is the block diagram of an embodiment of the drive circuit of the present invention.
  • Fig. 5 it is the schematic diagram of the first embodiment of driving signal
  • Fig. 6 it is the schematic diagram of the second embodiment of driving signal
  • Fig. 7 it is the schematic diagram of the third embodiment of driving signal
  • Fig. 8 it is the schematic diagram of the fourth embodiment of driving signal
  • Fig. 9 it is the schematic diagram of the fifth embodiment of driving signal
  • Fig. 10 it is the schematic diagram of the sixth embodiment of driving signal
  • 11 to 13 are schematic diagrams of seventh to ninth embodiments of driving signals.
  • FIG. 1 is a schematic diagram of an embodiment of a driving architecture of the present invention
  • FIG. 2 is a block diagram of an embodiment of a driver and a display element of the present invention
  • the driving structure includes a controller 1 and a plurality of drivers 2 for driving the sub-pixels of the plurality of pixels of the display panel 10 to display images.
  • the drivers 2 are arranged in plural columns, and each driver 2 is coupled to a plurality of display elements 4 to drive the display elements 4 to emit light, and the display elements 4 are sub-pixels.
  • the display elements 4 can be submillimeter LEDs, micro LEDs or LEDs.
  • the controller 1 is coupled to the drivers 2 and sends an input data Din, a timing signal DCK, a clock signal PWMCLK and an enable signal EN to the drivers 2 .
  • the controller 1 can be an independent chip. Since the drivers 2 are arranged in plural columns, the pixels arranged in rows and columns on the display panel 10 can be controlled.
  • each driver 2 includes an enabling circuit 6 , a storage circuit 7 and a driving circuit 9 .
  • the enabling circuit 6 receives the enabling signal EN, and enables the storage circuit 7 according to the timing signal DCK according to the enabling signal EN Receive input data Din.
  • the driving circuit 9 is coupled to the storage circuit 7 and the display elements 4, and generates a plurality of driving signals according to the input data Din and the clock signal PWMCLK received by the storage circuit 7 to drive the display elements 4 to generate light to display images.
  • the enable circuit 6 of the first driver 2 will disable the storage circuit 7 of the first driver 2, and send an enable signal EN to the second driver 2.
  • the enabling circuit 6 is used to perform the above actions to drive the display elements 4 coupled to the second driver 2 , and so on.
  • FIG. 4 is a block diagram of an embodiment of the driving circuit of the present invention.
  • the storage circuit 7 is coupled to the enabling circuit 6 and receives the input data Din and the timing signal DCK.
  • the enabling circuit 6 enables the storage circuit 7 according to the received enabling signal, and drives the storage circuit 7 to receive input according to the timing signal DCK.
  • Data Din and store the input data Din.
  • the driving circuit 9 includes a driving signal generating circuit, which includes a complex comparison circuit 91 , a counter 93 , and a complex level conversion circuit 95 .
  • the comparison circuits 91 are coupled to the storage circuit 7 and the counter 93 .
  • the counter 93 receives the clock signal PWMCLK, and counts the clock pulses of the clock signal PWMCLK according to the clock signal PWMCLK to output a count signal, and the count signal changes with the count of the counter 93 .
  • it may further include a clock generating circuit, which generates the clock signal PWMCLK, and the frequency of the clock signal PWMCLK can be changed.
  • Each comparison circuit 91 receives the count signal and the pixel data of the input data Din stored in the storage circuit 7, and compares the count signal with the pixel data. When the pixel data is greater than the count signal, the comparison circuit 91 outputs a drive signal with a drive level. For example high level.
  • the comparison circuit 91 when the pixel data is less than the count signal, the comparison circuit 91 outputs a driving signal with a driving level.
  • the level conversion circuits 95 are coupled to the comparison circuits 91 and convert the driving signals output by the comparison circuits 91 . In an embodiment of the present invention, the level conversion circuit 95 may not be needed.
  • One end of these display elements 4 is coupled to a supply voltage VDD, a switch MOS is coupled between the other end of these display elements 4 and a ground end, and the driving signal generated by the comparison circuit 91 is used to control the switch MOS to drive the current Light flows through these display elements 4 to generate light.
  • a switch MOS2 can be further coupled between the switch MOS and the ground, and the switch MOS2 is controlled by a reference voltage Vref.
  • Vref a reference voltage
  • the time during which the comparison circuit 91 continues to generate the driving level of the driving signal is the driving time, that is, the time for driving the display element 4 , which determines the brightness of the display element 4 .
  • the common anode structure is used to drive the display elements 4
  • the present invention is not limited thereto, and the common cathode structure can also be used to drive the display elements 4 .
  • FIG. 5 is a schematic diagram of an embodiment of a driving signal.
  • the driving signal has an on-pulse width (high level) and an off-pulse width (low level) in one frame period, that is, the driving signal has a pulse width modulation (PWM), leading
  • PWM pulse width modulation
  • FIG. 6 is a schematic diagram of another embodiment of the driving signal.
  • the driving signal has a complex on-pulse width and a complex off-pulse width in one frame period, that is, the driving signal has N pulse width modulations.
  • the driving signal shown in Figure 6 is better than that shown in Figure 5
  • the driving signal can reduce the flicker phenomenon of the display element 4 .
  • the display element 4 is driven to display for 0.1 second, and the frame period is 0.2 second.
  • the driving signal in FIG. 5 drives the display element 4 to be continuously on for 0.1 second, and to be off for 0.1 second, so flickering is likely to occur. If the driving signal shown in FIG.
  • FIG. 7 is a schematic diagram of a third embodiment of the driving signal.
  • the driving circuit 9 generates a driving signal during one frame period.
  • the driving signal has a plurality of first conduction pulse widths and a plurality of second conduction pulse widths.
  • the first conduction pulse width is greater than the second conduction pulse width.
  • Wave width which indicates that the frequency of the clock signal PWMCLK received by the driving circuit 9 is the first frequency f1 or the second frequency f2, and the driving circuit 9 generates the first conduction pulse width according to the clock signal PWMCLK having the first frequency f1, And depend on
  • the second conduction pulse width is generated according to the clock signal PWMCLK having the second frequency f2.
  • the first frequency f1 is smaller than the second frequency f2. Since the frequency of the driving signal changes within a frame period, electromagnetic interference can be reduced.
  • the counter 93 counts based on a fixed number of clocks to generate the first on-pulse width and the second on-pulse width. For example, the counter 93 counts again every time the clock signal PWMCLK reaches 4096, It indicates that the maximum value of the count signal is 4096.
  • the comparator circuit 91 compares the count signal and the pixel data to generate the conduction pulse width.
  • the comparator circuit 91 when the value of the count signal is not greater than 1900, the comparator circuit 91 generates the conduction pulse width; when the count signal is When the value is greater than 1900, the comparison circuit 91 generates a cut-off pulse width until the value of the count signal is equal to 4096.
  • the counter 93 counts the clock signal PWMCLK with the first frequency f1 to generate the count signal, since the first frequency f1 is smaller than the second frequency f2, it takes a long time for the value of the count signal to change from 0 to 1900, so the first conduction pulse The wave width is larger than the second conduction pulse wave width.
  • FIG. 8 is a schematic diagram of a fourth embodiment of the driving signal.
  • the driving circuit 9 generates a driving signal during one frame period.
  • the driving signal has a plurality of first conduction pulse widths, a plurality of second conduction pulse widths, and a plurality of third conduction pulse widths.
  • the first conduction The pulse width is greater than the second conduction pulse width and the third conduction pulse width, and the second conduction pulse width is smaller than the third conduction pulse width, which means that the frequency of the clock signal PWMCLK received by the drive circuit 9 is The first frequency f1, the second frequency f2 or the third frequency f3, the driving circuit 9 generates the first conduction pulse width according to the clock signal PWMCLK with the first frequency f1, and generates the first conduction pulse width according to the clock signal PWMCLK with the second frequency f2 The second conduction pulse width is generated, and the driving circuit 9 generates the third conduction pulse width according to the clock signal PWMCLK having the third frequency f3.
  • the first frequency f1 is lower than the second frequency f2 and the third frequency f3, and the third frequency f3 is lower than the second frequency f2.
  • the order in which the drive circuit 9 generates the first, second, and third conduction pulse widths can be changed arbitrarily.
  • the third on-pulse width is generated first, and then the first on-pulse width or the second on-pulse width is generated successively, that is, according to with third frequency
  • the frequency f3 clock signal PWMCLK first generates the third conduction pulse width, and then generates the first conduction pulse width or the second conduction pulse width according to the clock signal PWMCLK with the first frequency f1 or the second frequency f2 .
  • the counter 93 counts based on a fixed number of clocks to generate first, second, and third conduction pulse widths.
  • the driving signal generation circuit sequentially generates N first conduction pulse widths of the first conduction pulse widths, the first conduction pulse widths, and the second Q third conduction pulse widths of the three conduction pulse widths, P second conduction pulse widths of the second conduction pulse widths, N, P, Q are integers greater than 0, that is, they can be Continuously generate the first, third or second conduction pulse width. Or, sequentially generate P second conduction pulse widths of the second conduction pulse widths, Q third conduction pulse widths of the third conduction pulse widths, and the first N first on-pulse widths of on-pulse widths.
  • the driving circuit 9 of the present invention generates a driving signal during a plurality of frame periods, and the time of these frame periods is the same, and the driving signal has at least one of the first, second and third conduction pulse widths. That is, a driving signal is generated during an F-1 frame period, an F frame period, and an F+1 frame period, and the driving signal has a first conduction pulse width, a second conduction pulse width and a third conduction pulse width. Turning on at least one of the pulse widths, the time of the F-1th frame period, the time of the F-th frame period and the time of the F+1-th frame period are the same, and F is an integer greater than 2.
  • FIG. 9 is a schematic diagram of a fifth embodiment of the driving signal.
  • the frequency of the clock signal PWMCLK increases from the first frequency f1 to the second frequency f2 over time, and then decreases from the second frequency f2 to the first frequency f1 over time.
  • the driving circuit 9 generates the first on-pulse width and the first off-pulse width according to the clock signal PWMCLK, and
  • the frequency of PWMCLK changes from the second frequency f2 to the first frequency f1 according to the clock signal PWMCLK
  • a second on-pulse width and a second off-pulse width are generated.
  • the first on-pulse width is greater than the second on-pulse width, and the first off-pulse width is smaller than the second off-pulse width.
  • the first on-pulse width may be equal to the second off-pulse width
  • the second on-pulse width may be equal to the first off-pulse width.
  • the counter 93 counts based on a fixed number of clocks to generate a first on-pulse width, a first off-pulse width, a second on-pulse width, and a second off-pulse width.
  • FIG. 10 is a schematic diagram of a sixth embodiment of the driving signal.
  • the frequency of the clock signal PWMCLK is directly converted from the first frequency f1 to the third frequency f3 with time, then directly converted to the second frequency f2 with time, and then directly converted from the second frequency f2 with time.
  • the driving circuit 9 Convert to the third frequency f3, and then directly convert to the first frequency f1 over time, for the driving circuit 9 to generate a driving signal with a variable pulse width, and the driving circuit 9 converts from the first frequency f1 at the frequency of the clock signal PWMCLK During the period to the second frequency f2, the driving circuit 9 generates the first on-pulse width and the first off-pulse width according to the clock signal PWMCLK, and changes the frequency of the clock signal PWMCLK from the second frequency f2 to the first frequency f1 During this period, a second on-pulse width and a second off-pulse width are generated according to the clock signal PWMCLK, and the driving signals thereof are similar to those of the embodiment shown in FIG. 9 .
  • the driving circuit 9 of the present invention generates driving signals during a plurality of frames, and the time of these frame periods is the same to drive the same display element, and the driving signals generated during each frame have the same On-pulse width and cut-off pulse width, but the on-pulse width and off-pulse width are different in different frame periods, which means that the driving circuit 9 generates drive in different frame periods according to three different frequency clock signals PWMCLK signal.
  • FIG. 11 shows that the drive circuit 9 generates a drive signal with the first on-pulse width and the first off-pulse width according to the clock signal PWMCLK with the first frequency during the F-1 frame period.
  • FIG. 11 shows that the drive circuit 9 generates a drive signal with the first on-pulse width and the first off-pulse width according to the clock signal PWMCLK with the first frequency during the F-1 frame period.
  • FIG. 12 shows the drive circuit 9 During an F frame period, a driving signal with a third on-pulse width and a third off-pulse width is generated according to a clock signal PWMCLK having a third frequency.
  • FIG. 13 shows the drive circuit 9 during a F+1 frame period. According to the clock signal with the second frequency
  • the PWMCLK generates a driving signal having a second on-pulse width and a second off-pulse width, and the time during the F-1 frame period, the time during the F-frame period, and the time during the F+1-th frame period are the same, F is an integer greater than 2.
  • the counter 93 counts based on a fixed number of clocks to generate the first on-pulse width, the first off-pulse width, the second on-pulse width, the second off-pulse width, the third on-pulse width width and the third cutoff pulse width.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

本发明提供一种显示面板的驱动电路，其包含一驱动讯号产生电路，于一帧期间产生一驱动讯号，以驱动显示面板的一显示元件，驱动讯号具有至少一第一导通脉波宽度与至少一第一截止脉波宽度、至少一第二导通脉波宽度、至少一第二截止脉波宽度，第一导通脉波宽度大于第二导通脉波宽度，第一截止脉波宽度小于第二截止脉波宽度。运用本发明的驱动电路可降低电磁干扰，而提升显示质量。

Description

显示面板的驱动电路 技术领域
本发明关于一种驱动电路，尤其指一种显示面板的驱动电路。
背景技术
显示设备已成为电子产品必要装备，以用于显示信息。显示设备已从液晶显示设备发展至次毫米发光二极管(Mini LED)显示设备及微发光二极管(Micro LED)显示设备。发光二极管作为显示元件，可以提升显示设备的显示质量。习用技术驱动上述发光二极管的方式会造成高电磁干扰(Electromagnetic Interference，EMI)，如此会影响显示质量。
基于上述，本发明提供一种显示面板的驱动电路，运用此驱动电路可降低EMI，而提升显示质量。
发明内容
本发明的一目的在于提供一种显示面板的驱动电路，其于一帧期间变换驱动显示元件的驱动讯号的频率，如此可以降低电磁干扰，而提升显示质量。
本发明提供一种显示面板的驱动电路，其包含一驱动讯号产生电路，驱动讯号产生电路于一帧期间产生一驱动讯号，以驱动显示面板的一显示元件，驱动讯号具有至少一第一导通脉波宽度、至少一第二导通脉波宽度、至少一第三导通脉波宽度，第一导通脉波宽度大于第二导通脉波宽度与第三导通脉波宽度，第二导通脉波宽度小于第三导通脉波宽度。驱动讯号产生电路于帧期间内的一时间，先产生第三导通脉波宽度，并接续产生第一导通脉波宽度或第二导通脉波宽度。
本发明另提供一种显示面板的驱动电路，其包含一驱动讯号产生电路，驱动讯号产生电路于一帧期间产生一驱动讯号，以驱动显示面板的一显示元件，驱动讯号具有至少一第一导通脉波宽度与至少一第一截止脉波宽度、至少一第二导通脉波宽度、至少一第二截止脉波宽度，第一导通脉波宽度大于第二导通脉波宽度，第一截止脉波宽度小于第二截止脉波宽度。
本发明又提供一种显示面板的驱动电路，其包含一驱动讯号产生电路，驱动讯号产生电路于一第F-1帧期间产生具有复数第一导通脉波宽度的一驱动讯号以驱动显示面板的一显示元件，并于一第F帧期间产生具有复数第二导通脉波宽度的驱动讯号以驱动此显示元件。该些第二导通脉波宽度不同于该些第一导通脉波宽度，第F-1帧期间的时间和第F帧期间的时间为相同，F为大于2的整数。
附图说明
图1：其为本发明的驱动架构的一实施例的示意图；
图2：其为本发明的驱动器与显示元件的一实施例的方块图；
图3：其为本发明的控制器与驱动器的一实施例的方块图；
图4：其为本发明的驱动电路的一实施例的方块图；
图5：其为驱动讯号的第一实施例的示意图；
图6：其为驱动讯号的第二实施例的示意图；
图7：其为驱动讯号的第三实施例的示意图；
图8：其为驱动讯号的第四实施例的示意图；
图9：其为驱动讯号的第五实施例的示意图；
图10：其为驱动讯号的第六实施例的示意图；
图11至图13：其为驱动讯号的第七至九实施例的示意图。
【图号对照说明】
1          控制器
2          驱动器
4          显示元件
6          致能电路
7          储存电路
9          驱动电路
91         比较电路
93         计数器
95         准位转换电路
10         显示面板
Din        输入数据
DCK        时序讯号
EN         致能讯号
f1         第一频率
f2         第二频率
f3         第三频率
MOS        开关
MOS2       开关
PWMCLK     时脉讯号
VDD        供应电压
Vref       参考电压
具体实施方式
为了使本发明的结构特征及所达成的功效有更进一步的了解与认识，特用较佳的实施例及配合详细的说明，说明如下：
在说明书及权利要求当中使用了某些词汇指称特定的组件，然，所属本发明技术领域中具有通常知识者应可理解，制造商可能会用不同的名词称呼同一个组件，而且，本说明书及权利要求并不以名称的差异作为区分组件的方式，而是以组件在整体技术上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的「包含」为一开放式用语，故应解释成「包含但不限定于」。再者，「耦接」一词在此包含任何直接及间接的连接手段。因此，若文中描述一第一装置耦接一第二装置，则代表该第一装置可直接连接该第二装置，或可透过其他装置或其他连接手段间接地连接至该第二装置。
请参阅图1和图2，图1为本发明的驱动架构的一实施例的示意图，图2为本发明的驱动器与显示元件的一实施例的方块图。如图所示，驱动架构包含一控制器1和复数个驱动器2，以驱动显示面板10的复数像素的子像素而显示影像。该些驱动器2呈复数列排列，每一驱动器2耦接复数显示元件4，以驱动该些显示元件4发射光线，该些显示元件4即为子像素。于本发明的一实施例中，该些显示元件4可为次毫米发光二极管、微发光二极管或者发光二极管。控制器1耦接该些驱动器2，并传送一输入数据Din、一时序讯号DCK、一时脉讯号PWMCLK和一致能讯号EN至驱动器2。于本发明的一实施例中，控制器1可为一独立芯片。由于该些驱动器2呈复数列排列，如此可以控制呈行列排列于显示面板10的像素。
请参阅图3，其为本发明的控制器与驱动器的一实施例的方块图。如图所示，每一驱动器2包含一致能电路6、一储存电路7与一驱动电路9。致能电路6接收致能讯号EN，并依据致能讯号EN致能储存电路7依据时序讯号DCK 接收输入数据Din。驱动电路9耦接储存电路7与该些显示元件4，并依据储存电路7接收的输入数据Din与时脉讯号PWMCLK产生复数驱动讯号，以驱动该些显示元件4产生光线，以可显示影像。当第一个驱动器2驱动该些显示元件4后，第一个驱动器2的致能电路6会禁能第一个驱动器2的储存电路7，并发出致能讯号EN至第二个驱动器2的致能电路6，以进行上述的动作，而驱动第二个驱动器2所耦接的该些显示元件4，依此类推。
请参阅图4，其为本发明的驱动电路的一实施例的方块图。如图所示，储存电路7耦接致能电路6并接收输入数据Din及时序讯号DCK，致能电路6依据接收的致能讯号致能储存电路7，驱使储存电路7依据时序讯号DCK接收输入数据Din，并储存输入数据Din。驱动电路9包含一驱动讯号产生电路，其包含复数比较电路91、一计数器93、复数准位转换电路95。该些比较电路91耦接储存电路7与计数器93。计数器93接收时脉讯号PWMCLK，并依据时脉讯号PWMCLK计数时脉讯号PWMCLK的时脉而输出一计数讯号，计数讯号随着计数器93的计数而改变。于本发明的一实施例中，更可包含一时脉产生电路，其产生时脉讯号PWMCLK，且时脉讯号PWMCLK的频率可改变。每一比较电路91接收计数讯号与储存电路7储存的输入数据Din的画素数据，并比较计数讯号与画素数据，当画素数据大于计数讯号时，比较电路91则输出具驱动准位的驱动讯号，例如高准位。于本发明的另一实施例中，当画素数据小于计数讯号时，比较电路91则输出具驱动准位的驱动讯号。该些准位转换电路95耦接该些比较电路91，并转换比较电路91输出的驱动讯号。于本发明的一实施例中，可不需要准位转换电路95。该些显示元件4的一端耦接一供应电压VDD，一开关MOS耦接于该些显示元件4的另一端与一接地端间，比较电路91产生的驱动讯号用于控制开关MOS，以驱使电流流过该些显示元件4，而产生光线。于 本发明的一实施例中，一开关MOS2更可耦接于开关MOS与接地端间，开关MOS2受控于一参考电压Vref。由上述说明可知，比较电路91持续产生驱动讯号的驱动准位的时间为驱动时间，即驱动显示元件4的时间，其会决定显示元件4的亮度。此实施例运用共阳极架构驱动该些显示元件4，本发明并不以此为限，亦可运用共阴极架构驱动该些显示元件4。
请参阅图5，其为驱动讯号的一实施例的示意图。如图所示，驱动讯号于一帧期间具有一导通脉波宽度(高准位)与一截止脉波宽度(低准位)，即驱动讯号具有一个脉波宽度调变(PWM)，导通脉波宽度决定显示元件4产生光线的时间。
请参阅图6，其为驱动讯号的另一实施例的示意图。如图所示，驱动讯号于一帧期间具有复数导通脉波宽度与复数截止脉波宽度，即驱动讯号具有N个脉波宽度调变，图6所示的驱动讯号优于图5所示的驱动讯号，其可降低显示元件4的闪烁现象。同样驱使显示元件4显示0.1秒下，而帧期间为0.2秒，图5的驱动讯号驱动显示元件4持续亮0.1秒，而持续不亮0.1秒，如此容易产生闪烁。若图6所示的驱动讯号具有10个导通脉波宽度，即表示将0.1秒分担到10个导通脉波宽度，分别驱动显示元件4显示0.01秒，如此于帧期间，显示元件4仍然亮0.1秒，但可以降低闪烁。然而，持续用相同宽度的导通脉波宽度驱使显示元件4，会有较高的电磁干扰。
请参阅图7，其为驱动讯号的第三实施例的示意图。如图所示，驱动电路9于一帧期间产生驱动讯号，驱动讯号具有复数第一导通脉波宽度、复数第二导通脉波宽度，第一导通脉波宽度大于第二导通脉波宽度，其表示驱动电路9接收的时脉讯号PWMCLK的频率为第一频率f1或者第二频率f2，驱动电路9依据具有第一频率f1的时脉讯号PWMCLK产生第一导通脉波宽度，而依 据具有第二频率f2的时脉讯号PWMCLK产生第二导通脉波宽度。第一频率f1小于第二频率f2。由于驱动讯号的频率于一帧期间内变换，如此可以降低电磁干扰。计数器93基于依据一固定数量的时脉进行计数，以产生第一导通脉波宽度和第二导通脉波宽度，例如计数器93每次计数时脉讯号PWMCLK的时脉到4096即重新计数，其表示计数讯号的最大值为4096。比较电路91比较计数讯号与画素数据产生导通脉波宽度，举一例说明，若画素数据为1900，当计数讯号的值未大于1900前，比较电路91产生导通脉波宽度；当计数讯号的值大于1900时，比较电路91产生截止脉波宽度止到计数讯号的值等于4096。计数器93计数具有第一频率f1的时脉讯号PWMCLK产生计数讯号时，由于第一频率f1小于第二频率f2，所以计数讯号的值从0变化到1900的时间较长，因此第一导通脉波宽度大于第二导通脉波宽度。
请参阅图8，其为驱动讯号的第四实施例的示意图。如图所示，驱动电路9于一帧期间产生驱动讯号，驱动讯号具有复数第一导通脉波宽度、复数第二导通脉波宽度、复数第三导通脉波宽度，第一导通脉波宽度大于第二导通脉波宽度与第三导通脉波宽度，第二导通脉波宽度小于第三导通脉波宽度，其表示驱动电路9接收的时脉讯号PWMCLK的频率为第一频率f1、第二频率f2或者第三频率f3，驱动电路9依据具有第一频率f1的时脉讯号PWMCLK产生第一导通脉波宽度，而依据具有第二频率f2的时脉讯号PWMCLK产生第二导通脉波宽度，驱动电路9依据具有第三频率f3的时脉讯号PWMCLK产生第三导通脉波宽度。第一频率f1小于第二频率f2和第三频率f3，第三频率f3小于第二频率f2。驱动电路9产生第一、第二、第三导通脉波宽度的顺序可任意变换。于本发明的一实施例中，于该帧期间内的某一时间，先产生第三导通脉波宽度，并接续产生第一导通脉波宽度或第二导通脉波宽度，即依据具有第三频 率f3的时脉讯号PWMCLK先产生第三导通脉波宽度，再依据具有第一频率f1或者第二频率f2的时脉讯号PWMCLK产生第一导通脉波宽度或者第二导通脉波宽度。计数器93基于依据固定数量的时脉进行计数，以产生第一、第二、第三导通脉波宽度。
于本发明的一实施例中，驱动讯号产生电路于帧期间内且于某一时间外，依序产生该些第一导通脉波宽度的N个第一导通脉波宽度、该些第三导通脉波宽度的Q个第三导通脉波宽度、该些第二导通脉波宽度的P个第二导通脉波宽度，N、P、Q大于0的整数，也就是可以连续产生第一、第三或者第二导通脉波宽度。又或者，依序产生该些第二导通脉波宽度的P个第二导通脉波宽度、该些第三导通脉波宽度的Q个第三导通脉波宽度、该些第一导通脉波宽度的N个第一导通脉波宽度。
本发明的驱动电路9于复数帧期间产生驱动讯号，且该些帧期间的时间为相同，驱动讯号具有第一、第二及第三导通脉波宽度的至少一者。也就是，于一第F-1帧期间、一第F帧期间、一第F+1帧期间产生驱动讯号，驱动讯号具有第一导通脉波宽度、第二导通脉波宽度及第三导通脉波宽度的至少一者，该第F-1帧期间的时间、该第F帧期间的时间和该第F+1帧期间的时间为相同，F为大于2的整数。
请参阅图9，其为驱动讯号的第五实施例的示意图。如图所示，于一帧期间，时脉讯号PWMCLK的频率随着时间从第一频率f1不断增加变换至第二频率f2，再从第二频率f2随时间不断减少变换至第一频率f1，如此于时脉讯号PWMCLK的频率从第一频率f1变换至第二频率f2期间，驱动电路9依据时脉讯号PWMCLK产生第一导通脉波宽度与第一截止脉波宽度，并于时脉讯号PWMCLK的频率从第二频率f2变换至第一频率f1期间依据时脉讯号PWMCLK 产生第二导通脉波宽度与第二截止脉波宽度。第一导通脉波宽度大于第二导通脉波宽度，第一截止脉波宽度小于第二截止脉波宽度。第一导通脉波宽度可等于第二截止脉波宽度，第二导通脉波宽度可等于第一截止脉波宽度。计数器93基于依据固定数量的时脉进行计数，以产生第一导通脉波宽度、第一截止脉波宽度以及第二导通脉波宽度、第二截止脉波宽度。
请参阅图10，其为驱动讯号的第六实施例的示意图。如图所示，于一帧期间，时脉讯号PWMCLK的频率从第一频率f1随时间直接变换至第三频率f3再随时间直接变换至第二频率f2，再从第二频率f2随时间直接变换至第三频率f3，再随时间直接变换至第一频率f1，以供驱动电路9产生具有变化的脉波宽度的驱动讯号，驱动电路9于时脉讯号PWMCLK的频率从第一频率f1变换至第二频率f2期间，驱动电路9依据时脉讯号PWMCLK产生第一导通脉波宽度与第一截止脉波宽度，并于时脉讯号PWMCLK的频率从第二频率f2变换至第一频率f1期间依据时脉讯号PWMCLK产生第二导通脉波宽度与第二截止脉波宽度，其驱动讯号相似于图9的实施例的驱动讯号。
请参阅图11至图13，本发明的驱动电路9于复数帧期间产生驱动讯号，且该些帧期间的时间为相同，以驱动同一显示元件，于每一帧期间产生的驱动讯号具有相同的导通脉波宽度与截止脉波宽度，但不同帧期间的导通脉波宽度与截止脉波宽度不相同，其表示驱动电路9依据三种不同频率的时脉讯号PWMCLK于不同帧期间产生驱动讯号。例如图11是驱动电路9于第F-1帧期间依据具有第一频率的时脉讯号PWMCLK产生具有第一导通脉波宽度与第一截止脉波宽度的驱动讯号、图12是驱动电路9于一第F帧期间依据具有第三频率的时脉讯号PWMCLK产生具有第三导通脉波宽度与第三截止脉波宽度的驱动讯号、图13是驱动电路9于一第F+1帧期间依据具有第二频率的时脉讯号 PWMCLK产生具有第二导通脉波宽度与第二截止脉波宽度的驱动讯号，第F-1帧期间的时间、该第F帧期间的时间和该第F+1帧期间的时间为相同，F为大于2的整数。计数器93基于依据固定数量的时脉进行计数，以产生第一导通脉波宽度、第一截止脉波宽度、第二导通脉波宽度、第二截止脉波宽度、第三导通脉波宽度与第三截止脉波宽度。
上文仅为本发明的较佳实施例而已，并非用来限定本发明实施的范围，凡依本发明权利要求范围所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的权利要求范围内。

Claims (15)

  1. 一种显示面板的驱动电路，其特征在于，包含：
    一驱动讯号产生电路，于一帧期间产生一驱动讯号，以驱动该显示面板的一显示元件，该驱动讯号具有至少一第一导通脉波宽度、至少一第二导通脉波宽度、至少一第三导通脉波宽度，该第一导通脉波宽度大于该第二导通脉波宽度与该第三导通脉波宽度，该第二导通脉波宽度小于该第三导通脉波宽度；
    其中，该驱动讯号产生电路于该帧期间内的一时间，先产生该第三导通脉波宽度，并接续产生该第一导通脉波宽度或该第二导通脉波宽度。
  2. 如权利要求1所述的驱动电路，其特征在于，其中该驱动讯号产生电路于该帧期间的该时间内，先产生该第三导通脉波宽度，并接续产生该第一导通脉波宽度，且接续产生该第二导通脉波宽度。
  3. 如权利要求1所述的驱动电路，其特征在于，其中该驱动讯号产生电路于该帧期间的该时间内，先产生该第三导通脉波宽度，并接续产生该第二导通脉波宽度，且接续产生该第一导通脉波宽度。
  4. 如权利要求1所述的驱动电路，其特征在于，其中该驱动讯号产生电路依据一固定数量的复数时脉产生该第一导通脉波宽度、该第二导通脉波宽度及该第三导通脉波宽度。
  5. 如权利要求4所述的驱动电路，其特征在于，其中该驱动讯号产生电路依据一时脉讯号产生该驱动讯号，该时脉讯号具有复数时脉，该时脉讯号的一频率为一第一频率、一第二频率或者一第三频率，该驱动讯号产生电路依据具该第一频率的该时脉讯号产生该第一导通脉波宽度、依据具该第二频率的该时脉讯号产生该第二导通脉波宽度、依据具该第三频率的该时脉讯号产生该第三导通脉波宽度。
  6. 如权利要求1所述的驱动电路，其特征在于，其中该至少一第一导通 脉波宽度包含复数第一导通脉波宽度、该至少一第二导通脉波宽度包含复数第二导通脉波宽度、该至少一第三导通脉波宽度包含复数第三导通脉波宽度，该驱动讯号产生电路于该帧期间内且于该时间外，依序产生该些第一导通脉波宽度的N个第一导通脉波宽度、该些第三导通脉波宽度的Q个第三导通脉波宽度、该些第二导通脉波宽度的P个第二导通脉波宽度，N、P、Q大于0的整数。
  7. 如权利要求1所述的驱动电路，其特征在于，其中该至少一第一导通脉波宽度包含复数第一导通脉波宽度、该至少一第二导通脉波宽度包含复数第二导通脉波宽度、该至少一第三导通脉波宽度包含复数第三导通脉波宽度，该驱动讯号产生电路于该帧期间内且于该时间外，依序产生该些第二导通脉波宽度的P个第二导通脉波宽度、该些第三导通脉波宽度的Q个第三导通脉波宽度、该些第一导通脉波宽度的N个第一导通脉波宽度，N、P、Q为大于0的整数。
  8. 如权利要求1所述的驱动电路，其特征在于，其中该帧期间为一第F帧期间，该驱动讯号产生电路于一第F-1帧期间与一第F+1帧期间产生该驱动讯号，该驱动讯号具有该第一导通脉波宽度、该第二导通脉波宽度及该第三导通脉波宽度的至少一者，该第F-1帧期间的时间、该第F帧期间的时间和该第F+1帧期间的时间为相同，F为大于2的整数。
  9. 一种显示面板的驱动电路，其特征在于，包含：
    一驱动讯号产生电路，于一帧期间产生一驱动讯号，以驱动该显示面板的一显示元件，该驱动讯号具有至少一第一导通脉波宽度与至少一第一截止脉波宽度、至少一第二导通脉波宽度、至少一第二截止脉波宽度，该第一导通脉波宽度大于该第二导通脉波宽度，该第一截止脉波宽度小于该第二截止脉波宽度。
  10. 如权利要求9所述的驱动电路，其中该驱动讯号产生电路依据一固定数量的复数时脉产生该第一导通脉波宽度及该第二导通脉波宽度。
  11. 如权利要求10所述的驱动电路，其特征在于，其中该驱动讯号产生电路依据一时脉讯号产生该驱动讯号，该时脉讯号具有复数时脉，该时脉讯号的一频率从一第一频率随时间变换至一第二频率，再从该第二频率随时间变换至该第一频率，该第二频率高于该第一频率，于该时脉讯号的该频率从该第一频率变换至该二频率期间，该驱动讯号产生电路依据该时脉讯号产生该第一导通脉波宽度与该第一截止脉波宽度，并于该时脉讯号的该频率从该第二频率变换至该第一频率期间依据该时脉讯号产生该第二导通脉波宽度与该第二截止脉波宽度。
  12. 一种显示面板的驱动电路，其特征在于，包含：
    一驱动讯号产生电路，于一第F-1帧期间产生具有复数第一导通脉波宽度的一驱动讯号以驱动该显示面板的一显示元件，并于一第F帧期间产生具有复数第二导通脉波宽度的该驱动讯号以驱动该显示元件；
    其中，该些第二导通脉波宽度不同于该些第一导通脉波宽度，该第F-1帧期间的时间和该第F帧期间的时间为相同，F为大于2的整数。
  13. 如权利要求12所述的驱动电路，其特征在于，其中该驱动讯号产生电路于一第F+1帧期间产生具有复数第三导通脉波宽度的该驱动讯号以驱动该显示元件，该些第三导通脉波宽度不同于该些第一导通脉波宽度与该些第二导通脉波宽度，该第F-1帧期间的时间、该第F帧期间的时间和该第F+1帧期间的时间为相同。
  14. 如权利要求13所述的驱动电路，其特征在于，其中该驱动讯号产生电路依据一固定数量的复数频率产生该些第一导通脉波宽度、该些第二导通脉波宽度及该些第三导通脉波宽度。
  15. 如权利要求14所述的驱动电路，其特征在于，其中该驱动讯号产生 电路依据一时脉讯号产生该驱动讯号，该时脉讯号具有复数频率，该时脉讯号的一频率为一第一频率、一第二频率或者一第三频率，该驱动讯号产生电路依据具该第一频率的该时脉讯号产生该些第一导通脉波宽度、依据具该第二频率的该时脉讯号产生该些第二导通脉波宽度、依据具该第三频率的该时脉讯号产生该些第三导通脉波宽度。
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Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI303407B (en) 2004-12-24 2008-11-21 Innolux Display Corp Driving circuit of display and method of driving the circuit
CN102298903B (zh) * 2010-06-28 2016-03-16 石井房雄 使用脉冲光源的显示装置
KR102017084B1 (ko) * 2011-05-13 2019-09-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
US9013386B2 (en) * 2012-01-09 2015-04-21 Himax Technologies Limited Liquid crystal display and method for operating the same
KR102005496B1 (ko) * 2012-09-21 2019-10-02 삼성디스플레이 주식회사 표시장치 및 그 구동 방법
KR102126534B1 (ko) * 2013-10-31 2020-06-25 엘지디스플레이 주식회사 광원 구동장치 및 이를 이용한 액정표시장치
KR102268047B1 (ko) * 2014-09-25 2021-06-22 엘지전자 주식회사 영상 처리 장치 및 그 방법
KR102582642B1 (ko) * 2016-05-19 2023-09-26 삼성디스플레이 주식회사 표시 장치
KR102648367B1 (ko) * 2016-11-03 2024-03-15 삼성디스플레이 주식회사 컨버터 및 이를 포함하는 표시 장치
CN107610636B (zh) * 2017-10-30 2021-02-02 武汉天马微电子有限公司 一种显示面板及显示装置
US10916189B2 (en) * 2018-06-22 2021-02-09 Lg Display Co., Ltd. Scan driver and display device using the same
US10902793B2 (en) * 2018-09-12 2021-01-26 Lg Display Co., Ltd. Gate driver circuit outputting a plurality of emission signals having different delay times or pulse widths or combinations thereof
KR102553594B1 (ko) 2018-09-14 2023-07-10 삼성전자주식회사 디스플레이 장치 및 그 제어 방법
KR102652923B1 (ko) * 2018-12-26 2024-03-29 엘지디스플레이 주식회사 백라이트 유닛 및 디스플레이 장치
KR102644863B1 (ko) * 2019-03-19 2024-03-11 삼성디스플레이 주식회사 표시 장치
KR102661704B1 (ko) * 2019-04-16 2024-05-02 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR102620829B1 (ko) * 2019-08-27 2024-01-03 삼성전자주식회사 발광소자 패키지 및 이를 포함하는 디스플레이 장치
KR20210130389A (ko) * 2020-04-22 2021-11-01 주식회사 엘엑스세미콘 디밍처리장치 및 디스플레이장치
US11087663B1 (en) * 2020-05-15 2021-08-10 Novatek Microelectronics Corp. Display device and driving method thereof for reducing difference in brightness between areas with different widths
CN113077762A (zh) 2021-03-17 2021-07-06 Tcl华星光电技术有限公司 Mini LED背光模组的驱动方法、驱动电路及显示装置

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