WO2023126020A1 - 滤波器、多工器、射频前端及制造滤波器的方法 - Google Patents

滤波器、多工器、射频前端及制造滤波器的方法 Download PDF

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WO2023126020A1
WO2023126020A1 PCT/CN2023/077778 CN2023077778W WO2023126020A1 WO 2023126020 A1 WO2023126020 A1 WO 2023126020A1 CN 2023077778 W CN2023077778 W CN 2023077778W WO 2023126020 A1 WO2023126020 A1 WO 2023126020A1
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Prior art keywords
groove
filter
pads
present application
piezoelectric substrate
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PCT/CN2023/077778
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English (en)
French (fr)
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杜波
王华磊
倪建兴
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锐石创芯(重庆)科技有限公司
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Publication of WO2023126020A1 publication Critical patent/WO2023126020A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/64—Filters using surface acoustic waves

Definitions

  • the present application relates to the technical field of filters, in particular to filters, multiplexers, radio frequency front-ends and methods for manufacturing filters.
  • a filter is generally included in a radio frequency front end of a communication device to filter radio frequency signals.
  • Acoustic wave filter is a kind of filter, which includes surface acoustic wave (Surface Acoustic Wave, SAW) filter and bulk acoustic wave (Bulk Acoustic Wave, BAW) filter.
  • SAW Surface Acoustic Wave
  • SAW filters are currently widely used in RF front-ends due to their high operating frequency, wide passband, good frequency selection characteristics, small size and light weight, etc., and are simple to manufacture and low in cost. .
  • a SAW filter includes a plurality of resonators, input pads, output pads, and ground pads, which are arranged on a piezoelectric substrate. It is composed of an Interdigital Transducer (IDT), and the traces on the piezoelectric substrate mainly make the electrical connection between the pad and the resonator and between the resonators.
  • IDT Interdigital Transducer
  • the embodiment of the present application provides a filter, a multiplexer, a radio frequency front-end and a manufacturing method of the filter, so as to reduce parasitic capacitance and improve the out-of-band suppression level of the filter.
  • the first aspect of the embodiment of the present application provides a filter, including:
  • a piezoelectric substrate, the piezoelectric substrate is provided with grooves;
  • Pads the pads include input pads, output pads and ground pads;
  • At least one of the traces is disposed on the groove.
  • the second aspect of the embodiment of the present application provides a filter, including:
  • a piezoelectric substrate, the piezoelectric substrate is provided with grooves;
  • Pads the pads include input pads, output pads and ground pads;
  • At least one of the pads is disposed on the groove.
  • a third aspect of the embodiments of the present application provides a multiplexer, including a receiving filter and a sending filter, where at least one of the receiving filter and the sending filter includes any filter described above.
  • a fourth aspect of the embodiments of the present application provides a radio frequency front end, including any filter described above.
  • the fifth aspect of the embodiment of the present application provides a method of manufacturing a filter, the method comprising:
  • a conductive pattern is formed on the target surface, the conductive pattern is composed of a resonator, a trace and a pad, wherein at least one of the traces and/or at least one of the pads is located in the concave on the slot.
  • the filter includes a piezoelectric substrate provided with grooves, a plurality of resonators arranged on the piezoelectric substrate, pads, and wires, at least one of the pads and/or wires in the wires At least one is provided on the groove.
  • FIG. 1A is a schematic plan view of a filter provided by an embodiment of the present application.
  • Fig. 1B is a partial cross-sectional schematic diagram of the filter shown in Fig. 1A;
  • FIG. 1C is a schematic plan view of another filter provided by the embodiment of the present application.
  • Fig. 1D is a partial cross-sectional schematic diagram of the filter shown in Fig. 1C;
  • FIG. 1E is a schematic plan view of another filter provided by the embodiment of the present application.
  • FIG. 2A is a schematic plan view of another filter provided by an embodiment of the present application.
  • Fig. 2B is a partial cross-sectional schematic view of the filter shown in Fig. 2A;
  • FIG. 2C is a schematic plan view of another filter provided by the embodiment of the present application.
  • Fig. 2D is a partial cross-sectional schematic diagram of the filter shown in Fig. 2C;
  • FIG. 2E is a schematic plan view of another filter provided by the embodiment of the present application.
  • Fig. 3 is a signal simulation diagram of the filter provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a duplexer provided in an embodiment of the present application.
  • FIG. 5A is a signal simulation diagram of a duplexer provided in an embodiment of the present application.
  • FIG. 5B is another signal simulation diagram of the duplexer provided by the embodiment of the present application.
  • FIG. 5C is a signal isolation diagram of the duplexer provided by the embodiment of the present application.
  • Fig. 6 is a schematic flowchart of a method for manufacturing a filter provided by an embodiment of the present application.
  • Spatial terms such as “below”, “under”, “beneath”, “below”, “above”, “above”, etc., may be used herein for convenience of description The relationship of one element or feature to other elements or features shown in the figures is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the present application relates to the technical field of filters, in particular to a filter, a multiplexer, a radio frequency front-end and a method for manufacturing the filter.
  • the existing SAW filter not only generates parasitic capacitance due to potential difference between traces, but also generates parasitic capacitance between pads, thereby reducing the out-of-band suppression level of the filter.
  • the inventive concept of the present application which will be specifically described through the following examples:
  • FIG. 1A is a schematic plan view of a filter provided by an embodiment of the present application.
  • the filter 100 described in this embodiment includes a piezoelectric substrate 121, and resonators 101, 103 and 104, a filter 102, an input pad 105, an output pad 106, and a ground pad arranged on the piezoelectric substrate 121. pads 107 and 108 , traces 109 - 115 and 118 - 120 , jumper material 116 and 117 , and groove 122 .
  • Resonators 101, 103 and 104, filter 102 include reflectors arranged at both ends and an IDT between the reflectors, resonators 101, 103 and 104 are transversely coupled SAW resonators, and 102 is a double-mode surface acoustic wave ( Double-Mode SAW, DMS) filter.
  • the input pad 105 is connected to the resonator 101 through a trace 109 .
  • One end of the IDT in the middle of the DMS filter 102 is connected to the resonator 101 through the trace 112, and the other end is connected to the ground pad 107 through the trace 115, and one end of the IDT on both sides of the DMS filter 102 is respectively connected through the trace 110 and
  • the wire 111 is connected to the ground pad 108 , and its other end is electrically connected to the resonator 103 through the wire 114 and the wire 113 respectively.
  • the resonator 103 is electrically connected to the output pad 106 through a trace 118 .
  • the resonator 104 is connected in parallel with the resonator 103 through the trace 119 , and connected to the ground pad 107 through the trace 120 .
  • the jumper material 116 and the jumper material 117, the jumper material 116 and the jumper material 117 can specifically be insulating materials, such as silicon dioxide SiO 2 , silicon nitride Si 3 N 4 or polyimide, etc., the embodiment of the present application No limit.
  • At least one trace 109 is arranged on the groove 122, specifically, part of the trace 109 may be arranged on the groove 122, or all of the traces 109 may be arranged on the groove 122,
  • the embodiment of this application is not limited.
  • the input signal is input to the resonator 101 through the input pad 105 and the wiring 109, and after the electrical-acoustic and acoustic-electric conversion by the resonator 101, it is output to the DMS filter 102 through the wiring 112, and the DMS filter 102 After processing, the signal is output to the resonator 103 via the wire 113 and the wire 114 respectively. After being processed by the resonator 103 , it is sent to the output pad 106 via the wire 118 , and the filtering process of the signal is completed so far.
  • Fig. 1A is only a preferred embodiment of the present application.
  • the groove on the piezoelectric substrate can be located under any at least one trace, specifically, the groove can be arranged on two oppositely arranged and has a potential difference below one of the traces in the For example, because there is a potential difference between the wiring 109 and the wiring 118 , the groove 122 may also be located under the wiring 118 .
  • the groove can also be located under any one of the wiring 114 and the wiring 113, and there can also be multiple grooves on the piezoelectric substrate, which are respectively located under multiple wirings,
  • the embodiments of this application are not limited.
  • the shape of the groove is not limited to the shape shown in FIG. 1A , and may also be square, circular, elliptical, polygonal, irregular, and other shapes, which are not limited in this embodiment of the present application.
  • FIG. 1B is a partial cross-sectional schematic diagram of the filter shown in FIG. 1A .
  • the groove 122 is disposed on the piezoelectric substrate 121 , and the trace 109 is located on the groove 122 .
  • the cross section of the groove 122 can be set as a trapezoid or a rectangle, which is not limited in this embodiment of the present application.
  • the depth of the groove may range from 50nm to 3um, which is not limited in this embodiment of the present application.
  • the material of the piezoelectric substrate 121 may include at least one of lithium tantalate LiTaO 3 and lithium niobate LiNbO 3 , which is not limited in the embodiment of the present application.
  • the metal material used in the wiring of the prior art generally has a relatively low hardness.
  • the bottom layer of the wiring can be set as a metal layer with a relatively high hardness, such as molybdenum Mo, tungsten W, etc.
  • the embodiment of the present application is not limited, so that the mechanical strength of the wiring can be increased to prevent deformation.
  • the metal layer can be set on the bottom layer of all traces, or the metal layer can be set on the bottom layer of the traces arranged on the groove.
  • the bottom layer of the trace 109 shown in FIG. 1A is set to a harder metal layer.
  • the groove 122 can be filled with air or an insulating material, and the dielectric constant of the insulating material is lower than that of the piezoelectric substrate, usually a material with a dielectric constant less than 10, for example, Silicon dioxide SiO 2 , silicon nitride Si 3 N 4 and the like are not limited in this embodiment of the application.
  • the width of the wire 109 is greater than the width of the groove 122 , that is, the wire 109 is partially disposed on the groove 122 .
  • the width of the wiring 109 may also be less than or equal to the width of the groove 122, that is, the wiring 109 is erected on the groove 122, that is, partly arranged on the air, as shown in FIG. 1E ,
  • FIG. 1E is a schematic plan view of another filter provided by the embodiment of the present application, specifically, a schematic plan view in which the width of the trace 109 is smaller than the width of the groove 122 .
  • the width of the wiring 109 may be greater than, less than or equal to the width of the groove 122, that is, the wiring 109 may also be disposed on the insulating material, which is not limited in this embodiment.
  • FIG. 1C is a schematic plan view of another filter provided by the embodiment of the present application
  • FIG. 1D is a partial cross-sectional schematic view of the filter shown in FIG. 1C. Specifically, it is a section taken along the transverse direction of FIG. 1C and perpendicular to the trace 109 .
  • a supporting layer 123 can be provided, and the supporting layer 123 is arranged to cover the groove 122 .
  • the hardness of the material used for the supporting layer 123 is greater than that of the wiring 109 , for example, may include at least one of aluminum nitride AlN and silicon nitride Si 3 N 4 , which is not limited in this embodiment of the present application.
  • a support layer 123 is provided between the groove 122 and the trace 109, so as to prevent deformation of the trace and improve the mechanical strength of the trace.
  • the groove 122 below the wiring 109 may be one, or may be composed of multiple grooves with relatively dense layout and smaller openings. In this case, if the groove is filled with air, the wiring There is also no need to provide an additional supporting layer between the groove and the groove, or the bottom layer of the wiring does not need a metal layer with high hardness, so as to ensure the mechanical strength of the wiring, which is not limited in this embodiment of the present application.
  • the embodiment of this application describes only one type of SAW filter, that is, a hybrid SAW filter.
  • the embodiment of this application can also be applied to DMS filters, ladder filters, transverse coupling filters, balanced-non For a filter with parasitic capacitance between traces, such as a balanced filter, this embodiment of the present application does not limit it.
  • FIG. 3 is a signal simulation diagram of a filter provided by an embodiment of the present application.
  • the dotted line represents the pass-band signal of the filter under the conventional design
  • the solid line represents the pass-band signal of the filter when the groove 122 is arranged under the trace 109 as in Fig. 1A, as can be seen from Fig. Setting the groove 122 under the line 109 can improve the out-of-band rejection level of the filter.
  • a groove is provided on the piezoelectric substrate of the filter, and at least one of the traces is arranged on the groove, which can reduce the parasitic capacitance between the traces and improve the out-of-band suppression level of the filter, thereby Improve filter performance.
  • FIG. 2A is a schematic plan view of another filter provided by an embodiment of the present application.
  • the filter 200 described in this embodiment includes a piezoelectric substrate 221, and resonators 201, 203 and 204, a filter 202, an input pad 205, an output pad 206, and a ground pad are arranged on the piezoelectric substrate 221.
  • the resonators 201 , 203 and 204 and the filter 202 include reflectors arranged at both ends and an IDT between the reflectors.
  • the resonators 201 , 203 and 204 are laterally coupled SAW resonators, and the filter 202 is a DMS filter.
  • the input pad 205 is connected to the resonator 201 through a trace 209 .
  • One end of the IDT in the middle of the DMS filter 202 is connected to the resonator 201 through the trace 212, and the other end is connected to the ground pad 207 through the trace 215, and one end of the IDT on both sides of the DMS filter 202 is respectively connected through the trace 210 and
  • the wire 211 is connected to the ground pad 208 , and its other end is electrically connected to the resonator 203 through the wire 214 and the wire 213 respectively.
  • the resonator 203 is electrically connected to the output pad 206 through the wire 218 .
  • the resonator 204 is connected in parallel with the resonator 203 through the trace 219 , and connected to the ground pad 207 through the trace 220 .
  • the jumper material 216 and the jumper material 217, the jumper material 216 and the jumper material 217 can specifically be insulating materials, such as silicon dioxide SiO 2 , silicon nitride Si 3 N 4 or polyamide Imine, etc., are not limited in the embodiments of the present application.
  • At least one pad is set on the groove 222 as shown in FIG. It may be all arranged on the groove 222, which is not limited in this embodiment of the present application.
  • the input signal is input to the resonator 201 through the input pad 205 and the wiring 209, and after the electrical-acoustic and acoustic-electric conversion by the resonator 201, it is output to the DMS filter 202 through the wiring 212, and the DMS filter 202 After processing, the signals are respectively output to the resonator 203 via the wiring 213 and the wiring 214 , and then to the output pad 206 via the wiring 218 after being processed by the resonator 203 , so far the signal filtering process is completed.
  • Fig. 2A is only a preferred embodiment of the present application.
  • the groove on the piezoelectric substrate can be located under any at least one welding pad, specifically, the groove can be arranged on any two existing pads. Potential difference between the pads which pads are below. For example, since the parasitic capacitance generated by the potential difference between the output pad 205 and the output pad 206 has a great influence on the filter 200 , the groove 222 may also be located below the input pad 205 .
  • the groove can also be located under any one of the ground pad 207 and the ground pad 208, and there can also be multiple grooves on the piezoelectric substrate, which are respectively located under a plurality of pads , which is not limited in the embodiment of this application.
  • the shape of the groove is not limited to the shape shown in FIG. 2A , and may also be other shapes such as rectangle, circle, ellipse, polygon, and irregular figure, which are not limited in this embodiment of the present application.
  • FIG. 2B is a partial cross-sectional schematic diagram of the filter shown in FIG. 2A .
  • a groove 222 is disposed on the piezoelectric substrate 221 , and the output pad 206 is located on the groove 222 .
  • the cross section of the groove 222 can be set as a trapezoid or a rectangle, which is not limited in this embodiment of the present application.
  • the depth of the groove may range from 50nm to 3um, which is not limited in this embodiment of the present application.
  • the material of the piezoelectric substrate 221 may include at least one of lithium tantalate LiTaO 3 and lithium niobate LiNbO 3 , which is not limited in the embodiment of the present application.
  • the metal materials generally used in the pads of the prior art have relatively low hardness.
  • the bottom layer of the pad can be set as a metal layer with high hardness, such as molybdenum Mo, tungsten W, etc.
  • the embodiment of the present application is not limited, so that the mechanical strength of the pad can be increased to prevent deformation.
  • the metal layer can be set at the bottom layer of all pads, or the metal layer can be set at the bottom layer of the pad arranged on the groove.
  • the bottom layer of the output pad 206 shown in FIG. 2A is set to have a higher hardness. metal layer.
  • the groove 222 can be filled with air or an insulating material, and the dielectric constant of the insulating material is lower than that of the piezoelectric substrate, usually a material with a dielectric constant less than 10, for example, silica SiO 2 , silicon nitride Si 3 N 4 and the like are not limited in this embodiment of the present application.
  • the output pad 206 can be set covering the groove 222, that is, the pad 206 is partially set on the groove 222, and can also be erected on the groove 222.
  • 2E which is a schematic plan view of another filter provided by the embodiment of the present application.
  • the output pad 206 may cover the groove 222 or be disposed on the insulating material, which is not limited in this embodiment of the present application.
  • FIG. 2C is a schematic plan view of another filter provided by the embodiment of the present application
  • FIG. 2D is a partial cross-sectional schematic view of the filter shown in FIG. 2C. Specifically, it is a section taken along the longitudinal direction of FIG. 2C and perpendicular to the output pad 206 .
  • a supporting layer 223 may also be disposed, and the supporting layer 223 is arranged to cover the groove 222 .
  • the hardness of the material used for the support layer 223 is greater than that of the output pad 206 , for example, may include at least one of aluminum nitride AlN and silicon nitride Si 3 N 4 , which is not limited in the embodiment of the present application.
  • a supporting layer 223 is provided between the groove 222 and the output pad 206, so as to prevent deformation of the pad and improve the mechanical strength of the pad.
  • the groove 222 below the output pad 206 may be one, or may be composed of multiple grooves with relatively dense layout and smaller openings. In this case, if the groove is filled with air, the soldering It is also possible to ensure the mechanical strength of the pad without providing an additional support layer between the pad and the groove, or without a hard metal layer at the bottom of the pad, which is not limited in this embodiment of the present application.
  • the embodiment of this application describes only one type of SAW filter, that is, a hybrid SAW filter.
  • the embodiment of this application can also be applied to ladder filters, DMS filters, transverse coupling filters, balanced-non For a filter with parasitic capacitance between pads, such as a balanced filter, this embodiment of the present application does not limit it.
  • a groove is provided on the piezoelectric substrate of the filter, and at least one of the pads with a potential difference is provided on the groove, which can reduce the gap between the pads, especially the input pad and the output pad.
  • the parasitic capacitance between them can improve the out-of-band rejection level of the filter, thereby improving the filter performance.
  • FIG. 4 is a schematic structural diagram of a duplexer provided in an embodiment of the present application.
  • the duplexer includes a transmission port TX, a reception port RX, an antenna port ANT, and a transmission filter 401 and a reception filter 402 .
  • at least one of the receiving filter 401 and the transmitting filter 402 is any filter as described in the above embodiments.
  • the transmission port TX inputs the signal into the transmission filter 401, and after filtering by the transmission filter 401, the processed signal is sent out through the antenna port ANT; the antenna port ANT receives an external signal and inputs it to the The receiving filter 402 is filtered by the receiving filter 402 and output through the receiving port RX.
  • Figure 5A is a signal simulation diagram of the duplexer provided by the embodiment of the present application
  • Figure 5B is another signal simulation diagram of the duplexer provided by the embodiment of the present application
  • Figure 5C is a signal simulation diagram of the duplexer provided by the embodiment of the present application Signal isolation diagram.
  • the dotted line in FIGS. 5A-5C represents the passband signal of the duplexer under the conventional design
  • the solid line represents the passband signal of the duplexer described in the embodiment of the present application.
  • Figure 5A is the passband signal between the transmit port TX and the antenna port ANT
  • Figure 5B is the passband signal between the receive port RX and the antenna port ANT
  • Figure 5C is the signal isolation between the transmit port TX and the receive port RX Spend. It can be seen that the duplexer provided by the embodiment of the present application has better out-of-band suppression level and better isolation than the duplexer of conventional design.
  • the embodiment of the present application also provides a radio frequency front-end including any filter described above, which will not be described in detail in the embodiment of the present application.
  • the filter can reduce the parasitic capacitance and improve the level of out-of-band suppression, the performance of the radio frequency front end can be improved.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a filter provided by an embodiment of the present application. As shown in Figure 6, the method includes:
  • the filter is composed of a piezoelectric substrate, a plurality of resonators, an input pad, an output pad, a ground pad, and wires. Traces are used for connections between pads and resonators, and between resonators.
  • the material of the piezoelectric substrate may include at least one of lithium tantalate LiTaO 3 and lithium niobate LiNbO 3 .
  • the target surface indicates a certain surface of the piezoelectric substrate, that is, the upper surface.
  • grooves are first formed by etching, then the target material is deposited in the grooves, and then a flat surface is formed by CMP process.
  • the groove may be one or multiple, which is not limited in this embodiment of the present application.
  • the shape of the groove may be any shape such as rectangle, square, ellipse, polygon, or irregular figure, which is not limited in this embodiment of the present application.
  • the depth of the groove may range from 50nm to 3um, which is not limited in this embodiment of the present application.
  • a conductive pattern on the target surface where the conductive pattern is composed of a resonator, a wire, and a pad, wherein at least one of the wires and/or at least one of the pads is located on the groove.
  • a layer of photoresist is placed, and the conductive pattern of the photoresist is determined through an exposure and development process, and then a conductive metal layer is deposited on the photoresist , and finally dissolve the photoresist with glue remover, so that the part of the non-conductive pattern in the conductive metal layer is peeled off from the piezoelectric substrate, thereby forming a conductive pattern.
  • the pad part can be thickened by using a lift-off process.
  • the conductive pattern may include multiple metal layers, and the conductive pattern includes a resonator, wires and bonding pads, wherein the resonator is composed of multiple IDTs and reflectors located on both sides of the multiple IDTs.
  • the IDT has two opposite rows of metal bus bars and a comb-shaped metal electrode finger group layer connected to the two rows of bus bars, and the reflector is also composed of metal materials.
  • the conductive pattern when forming the conductive pattern, at least one of the traces or at least one of the pads is arranged on the groove on the piezoelectric substrate. Wherein, the wires or pads may be partially or completely located on the groove.
  • the target material is a sacrificial material
  • grooves are formed by etching on the target surface of the piezoelectric substrate, and the sacrificial material is deposited in the grooves.
  • a support layer is formed on the groove, and a pattern of the support layer is formed by etching, and a through hole is formed between the support layer and the sacrificial layer.
  • an etching material is injected into the groove through the through hole to etch the sacrificial material, wherein at least one of the traces and/or at least one of the pads are specifically located on the supporting layer.
  • the corrosive material may be corrosive liquid or corrosive gas, which is not limited in this embodiment of the present application.
  • the support layer may be at least one of aluminum nitride AlN, molybdenum Mo, tungsten W, etc., which is not limited in this embodiment of the present application.
  • the hardness of the supporting layer is greater than that of the metal layer forming the conductive pattern, and is sufficient to support the traces or pads on the groove without deformation.
  • the sacrificial material silicon Si can be sputtered into the groove, and the etching gas XeF 2 is injected into the groove through the through hole to etch the silicon Si.
  • the sacrificial material PSG may also be filled into the groove, and the etching liquid hydrogen fluoride HF is injected into the groove through the through hole to etch the PSG.
  • the embodiment of this application is not limited.
  • the groove is filled with air in the above manner.
  • the bottom layer of the conductive pattern may specifically be that the bottom layer of the wires and/or pads located above the groove may be a metal material with relatively high hardness.
  • the bottom layer of the conductive pattern may specifically be that the bottom layer of the wiring and/or pad located above the groove is a metal material with relatively high hardness.
  • the target material is an insulating material, wherein, the dielectric constant of the insulating material is lower than the dielectric constant of the piezoelectric substrate, generally a material with a dielectric constant less than 10, such as Silicon SiO2, silicon nitride Si 3 N 4 and the like are not limited in this embodiment of the present application.
  • the groove is filled with an insulating material. Therefore, the wiring or pad may cover the groove or be located on the insulating material, which is not limited in this embodiment of the present application.
  • the groove located under the trace or pad can be one, or it can be composed of multiple densely laid out grooves.
  • the grooves with smaller openings are not limited in this embodiment of the present application.
  • a piezoelectric substrate with a groove can be formed, and at least one of the traces and/or at least one of the pads is formed on the groove, thereby reducing the gap between the traces or the pads.
  • the parasitic capacitance between them can improve the out-of-band rejection level of the filter to improve the filter performance.

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Abstract

本申请涉及滤波器技术领域，具体提供一种滤波器、多工器、射频前端及制造滤波器的方法。本申请中的滤波器包括设有凹槽的压电基片，设置在压电基片上的多个谐振器，焊盘包括输入焊盘、输出焊盘和接地焊盘以及用于连接焊盘与多个谐振器，多个谐振器之间的走线，其中，焊盘中的至少一个和/或走线中的至少一个设置在凹槽上。

Description

滤波器、多工器、射频前端及制造滤波器的方法
本申请要求于2021年12月31日提交中国专利局、申请号为CN 202111676549.9、申请名称为“滤波器、多工器、射频前端及制造滤波器的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及滤波器技术领域，尤其涉及滤波器、多工器、射频前端及制造滤波器的方法。
背景技术
在通信设备的射频前端中一般包括有滤波器，以过滤射频信号。声波滤波器是滤波器的一种，其包括声表面波(Surface Acoustic Wave，SAW)滤波器和体声波(Bulk Acoustic Wave，BAW)滤波器。声表面波(Surface Acoustic Wave，SAW)滤波器由于其具有工作频率高、通频带宽、选频特性好、体积小和重量轻等特点，且制造简单，成本低，目前在射频前端中广泛应用。
通常，SAW滤波器包括多个谐振器、输入焊盘、输出焊盘以及接地焊盘，这些设置在压电基片上，谐振器由两个反射器以及位于反射器之间的多个叉指换能器(Interdigital Transducer，IDT)组成，压电基片上的走线主要使焊盘与谐振器以及谐振器之间电连接。
现有技术中，压电基片上的走线之间产生的寄生电容会降低滤波器的带外抑制水平，从而影响滤波器性能。因此，如何减小滤波器的寄生电容已成为亟待解决的问题。
发明内容
本申请实施例提供一种滤波器、多工器、射频前端及滤波器的制造方法，以减小寄生电容提高滤波器的带外抑制水平。
本申请实施例第一方面提供了一种滤波器，包括：
压电基片，所述压电基片设有凹槽；
多个谐振器；
焊盘，所述焊盘包括输入焊盘、输出焊盘和接地焊盘；
走线，用于所述焊盘与所述多个谐振器之间的连接，以及所述多个谐振器之间的连接；
其中，所述走线中的至少一个设于所述凹槽上。
本申请实施例第二方面提供了一种滤波器，包括：
压电基片，所述压电基片上设有凹槽；
多个谐振器；
焊盘，所述焊盘包括输入焊盘、输出焊盘和接地焊盘；
走线，用于所述焊盘与所述多个谐振器之间的连接，以及所述多个谐振器之间的连接；
其中，所述焊盘中的至少一个设于所述凹槽上。
本申请实施例第三方面提供了一种多工器，包括接收滤波器和发送滤波器，所述接收滤波器和所述发送滤波器中的至少一个包括以上所描述的任一种滤波器。
本申请实施例第四方面提供了一种射频前端，包括以上所描述的任意一种滤波器。
本申请实施例第五方面提供了一种制造滤波器的方法，该方法包括：
在压电基片的目标表面上形成凹槽，并在所述凹槽中沉积目标材料；
在所述目标表面上形成导电图形，所述导电图形由谐振器、走线和焊盘组成，其中，所述走线中的至少一个和/或所述焊盘中的至少一个位于所述凹槽上。
本申请实施例中，滤波器包括设有凹槽的压电基片、设置在压电基片上的多个谐振器、焊盘以及走线，焊盘中的至少一个和/或走线中的至少一个设置在凹槽上。通过本发明实施例，可以减少寄生电容的产生，提高滤波器的带外抑制水平，从而提高滤波器性能。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1A是本申请实施例提供的一种滤波器的平面示意图；
图1B是图1A所示滤波器的部分剖面示意图；
图1C是本申请实施例提供的另一种滤波器的平面示意图；
图1D是图1C所示滤波器的部分剖面示意图；
图1E是本申请实施例提供的又一种滤波器的平面示意图；
图2A是本申请实施例提供的又一种滤波器的平面示意图；
图2B是图2A所示滤波器的部分剖面示意图；
图2C是本申请实施例提供的又一种滤波器的平面示意图；
图2D是图2C所示滤波器的部分剖面示意图；
图2E是本申请实施例提供的又一种滤波器的平面示意图；
图3是本申请实施例提供的滤波器的信号仿真图；
图4是本申请实施例提供的一种双工器的示意图；
图5A是本申请实施例提供的双工器的一信号仿真图；
图5B是本申请实施例提供的双工器的另一信号仿真图；
图5C是本申请实施例提供的双工器的信号隔离度图；
图6是本申请实施例提供的一种制造滤波器的方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”、“连接至”、“与…连接”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本申请涉及滤波器的技术领域，具体涉及到一种滤波器、多工器、射频前端以及制造滤波器的方法。在实践中发现，现有的SAW滤波器不仅走线之间由于电位差会产生寄生电容，焊盘之间也会产生寄生电容，从而降低滤波器的带外抑制水平。为了解决上述的问题，因此有了本申请的发明构思，具体将通过以下的实施例进行说明：
请参见图1A，图1A是本申请实施例提供的一种滤波器的平面示意图。本实施例所描述的滤波器100包括压电基片121，以及设置在压电基片121上的谐振器101、103和104、滤波器102、输入焊盘105、输出焊盘106、接地焊盘107和108、多条走线109-115和118-120、跨线材料116和117以及凹槽122。
谐振器101、103和104、滤波器102包括两端设置的反射器以及位于反射器之间的IDT，谐振器101、103以及104为横向耦合的SAW谐振器，102为双模声表面波(Double-Mode SAW，DMS)滤波器。输入焊盘105通过走线109与谐振器101连接。DMS滤波器102位于中间的IDT一端与谐振器101通过走线112连接，另一端通过走线115接入到接地焊盘107，DMS滤波器102位于两侧的IDT的一端分别通过走线110和走线111与接地焊盘108连接，其另一端分别通过走线114和走线113与谐振器103电连接。谐振器103通过走线118与输出焊盘106电连接。谐振器104通过走线119与谐振器103并联，并通过走线120接入到接地焊盘107。由于走线110与走线112之间以及走线114与走线115之间均存在跨线的情况，因此在走线110与走线112以及走线114与走线115的跨线部分分别设置跨线材料116和跨线材料117，跨线材料116和跨线材料117具体可以为绝缘材料，如二氧化硅SiO2、氮化硅Si3N4或聚酰亚胺等，本申请实施例不做限定。
其中，设置在压电基片上的走线中，至少一条走线109设置在凹槽122上，具体可以是走线109部分设置在凹槽122上，也可以是全部设置在凹槽122上，本申请实施例不做限定。
具体的，输入信号经过输入焊盘105以及走线109输入到谐振器101，经过谐振器101电-声以及声-电转换后，通过走线112输出到DMS滤波器102，在DMS滤波器102进行处理后，分别由走线113和走线114输出到谐振器103，经过谐振器103的处理后，经由走线118到输出焊盘106，至此完成信号的滤波处理。
需要说明的是，图1A仅为本申请一优选实施例，在实际应用中，压电基片上的凹槽可以位于任意至少一条走线的下方，具体可以是将凹槽设置在两条相对设置且具有电位差 的走线中的其中一条走线的下方。例如，由于走线109与走线118之间存在电位差，因此，凹槽122也可以位于走线118的下方。
可选的(图中未示出)，凹槽也可以位于走线114与走线113中任意一条的下方，压电基片上也可以存在多个凹槽，分别位于多条走线的下方，本申请实施例不做限定。
进一步的，凹槽的形状不限定于如图1A所示的形状，也可以是正方形、圆形，椭圆形、多边形、不规则图形等其他形状，本申请实施例不做限定。
进一步的，沿图1A横向垂直于走线109所取一剖面，得到图1B，图1B是图1A所示滤波器的部分剖面示意图。如图1B所示，凹槽122设置在压电基片121上，走线109位于凹槽122上。凹槽122的剖面可以设置为梯形或矩形等，本申请实施例不做限定。
可选的，凹槽的深度范围可以为50nm～3um，本申请实施例不做限定。
本申请实施例中，压电基片121的材料可以包括钽酸锂LiTaO3、铌酸锂LiNbO3中的至少一种，本申请实施例不做限定。
在一种可行的实施方式中，现有技术的走线一般采用的金属材料硬度较小，本申请实施例可以在走线的底层设置为硬度较大的金属层，如钼Mo、钨W等，本申请实施例不做限定，这样可以增加走线的机械强度，防止变形。
具体的，可以在所有走线底层设置为该金属层，也可以在设置于凹槽上的走线底层设置该金属层，如图1A所示出的走线109的底层设置为硬度较大的金属层。
在另一种可行的实施方式中，凹槽122中可以填充空气或者绝缘材料，绝缘材料的介电常数小于压电基片的介电常数，通常是介电常数小于10的材料，例如可以是二氧化硅SiO2、氮化硅Si3N4等，本申请实施例不做限定。
当凹槽122中填充的是空气时，如图1B中所示的剖面图，走线109的宽度大于凹槽122宽度，即走线109部分设置于凹槽122上。可选的(图中未示出)，走线109的宽度也可以小于或等于凹槽122的宽度，即走线109架设于凹槽122上，即部分设置于空气上，如图1E所示，图1E是本申请实施例提供的又一滤波器的平面示意图，具体为走线109的宽度小于凹槽122宽度的平面示意图。
当凹槽122中填充的是绝缘材料时，走线109的宽度可以大于、小于或等于凹槽122的宽度，即走线109也可设置于绝缘材料上，本申请实施例不做限定。
在又一种可行的实施方式中，请参见图1C和图1D，图1C是本申请实施例提供的另一种滤波器的平面示意图，图1D是图1C所示滤波器的部分剖面示意图，具体是沿图1C横向垂直于走线109所取的剖面。如图1C和图1D所示，在凹槽122与走线109之间，还 可以设置一支撑层123，且支撑层123覆盖凹槽122设置。支撑层123所用材料的硬度大于走线109的硬度，例如可以包括氮化铝AlN、氮化硅Si3N4中的至少一种，本申请实施例不做限定。
优选的，在凹槽122所填充的是空气时，在凹槽122与走线109之间设置支撑层123，从而可以防止走线变形，提高走线的机械强度。
需要说明的是，走线109下方的凹槽122可以为一个，也可以由布局比较密集的多个开口较小的凹槽组成，在这种情况下，如果凹槽填充的是空气，走线与凹槽之间也可不用另外设置支撑层，或者走线底层不设置硬度较大的金属层，也可以保障走线的机械强度，在此本申请实施例不做限定。另外，本申请实施例所描述的仅仅是SAW滤波器中的一种，即混合型SAW滤波器，本申请实施例还可以应用在DMS滤波器、梯形滤波器、横向耦合滤波器、平衡-非平衡滤波器等走线之间存在寄生电容的滤波器中，本申请实施例不做限定。
图3是本申请实施例提供的滤波器的信号仿真图。在图3中，虚线表示常规设计下滤波器的通带信号，实线表示如图1A中在走线109下设置凹槽122时滤波器的通带信号，由图3可看出，在走线109下设置凹槽122可以提高滤波器的带外抑制水平。
本申请实施例中，滤波器的压电基片上设置凹槽，且将走线中的至少一条设置在凹槽上，可以减少走线之间的寄生电容，提高滤波器带外抑制水平，从而提高滤波器性能。
请参见图2A，图2A是本申请实施例提供的又一种滤波器的平面示意图。本实施例所描述的滤波器200包括压电基片221，以及设置在压电基片221上的谐振器201、203和204、滤波器202、输入焊盘205、输出焊盘206、接地焊盘207和208、多条走线209-215和218-220、跨线材料216和217以及凹槽222。
谐振器201、203和204、滤波器202包括两端设置的反射器以及位于反射器之间的IDT，谐振器201、203以及204为横向耦合的SAW谐振器，202为DMS滤波器。输入焊盘205通过走线209与谐振器201连接。DMS滤波器202位于中间的IDT一端与谐振器201通过走线212连接，另一端通过走线215接入到接地焊盘207，DMS滤波器202位于两侧的IDT的一端分别通过走线210和走线211与接地焊盘208连接，其另一端分别通过走线214和走线213与谐振器203电连接。谐振器203通过走线218与输出焊盘206电连接。谐振器204通过走线219与谐振器203并联，并通过走线220接入到接地焊盘207。由于走线210与走线212之间以及走线214与走线215之间均存在跨线的情况，因此在走线210与走线212以及走线214与走线215的跨线部分分别设置跨线材料216和跨线材料217，跨线材料216和跨线材料217具体可以为绝缘材料，如二氧化硅SiO2、氮化硅Si3N4或聚酰 亚胺等，本申请实施例不做限定。
其中，设置在压电基片上的焊盘中，至少一个焊盘如图2A所示的输出焊盘206设置在凹槽222上，具体可以是输出焊盘206部分设置在凹槽222上，也可以是全部设置在凹槽222上，本申请实施例不做限定。
具体的，输入信号经过输入焊盘205以及走线209输入到谐振器201，经过谐振器201电-声以及声-电转换后，通过走线212输出到DMS滤波器202，在DMS滤波器202进行处理后，分别由走线213和走线214输出到谐振器203，经过谐振器203的处理后，经由走线218到输出焊盘206，至此完成信号的滤波处理。
需要说明的是，图2A仅为本申请一优选实施例，在实际应用中，压电基片上的凹槽可以位于任意至少一个焊盘的下方，具体可以是将凹槽设置在任意两个存在电位差的焊盘中其中焊盘的下方。例如，由于输出焊盘205与输出焊盘206之间的电位差产生的寄生电容对滤波器200影响较大，因此，凹槽222也可以位于输入焊盘205的下方。
可选的(图中未示出)，凹槽也可以位于接地焊盘207和接地焊盘208任一个的下方，压电基片上也可以存在多个凹槽，分别位于多个焊盘的下方，本申请实施例不做限定。
进一步的，凹槽的形状不限定于如图2A所示的形状，也可以是矩形、圆形，椭圆形、多边形、不规则图形等其他形状，本申请实施例不做限定。
进一步的，沿图2A中纵向垂直于输出焊盘206所取一剖面，得到图2B，图2B是图2A所示滤波器的部分剖面示意图。如图2B所示，凹槽222设置在压电基片221上，输出焊盘206位于凹槽222上。凹槽222的剖面可以设置为梯形或矩形等，本申请实施例不做限定。
可选的，凹槽的深度范围可以为50nm～3um，本申请实施例不做限定。
本申请实施例中，压电基片221的材料可以包括钽酸锂LiTaO3、铌酸锂LiNbO3中的至少一种，本申请实施例不做限定。
在一种可行的实施方式中，现有技术的焊盘一般采用的金属材料硬度较小，本申请实施例可以在焊盘的底层设置为硬度较大的金属层，如钼Mo、钨W等，本申请实施例不做限定，这样可以增加焊盘的机械强度，防止变形。
具体的，可以在所有焊盘底层设置为该金属层，也可以在设置于凹槽上的焊盘底层设置该金属层，如图2A所示出的输出焊盘206的底层设置为硬度较大的金属层。
在另一种可行的实施方式中，凹槽222中可以填充空气或者绝缘材料，绝缘材料的介电常数小于压电基片的介电常数，通常是介电常数小于10的材料，例如可以是二氧化硅 SiO2、氮化硅Si3N4等，本申请实施例不做限定。
当凹槽222中填充的是空气时，如图2A和图2B所示，输出焊盘206可覆盖凹槽222设置，即焊盘206部分设置与凹槽222上，也可架设于凹槽222上，即部分设置于空气上，如图2E所示，图2E是本申请实施例提供的又一滤波器的平面示意图。
当凹槽222中填充的是绝缘材料时，输出焊盘206可覆盖凹槽222设置，也可设置于绝缘材料上，本申请实施例不做限定。
在又一种可行的实施方式中，请参见图2C和图2D，图2C是本申请实施例提供的又一种滤波器的平面示意图，图2D是图2C所示滤波器的部分剖面示意图，具体是沿图2C纵向垂直于输出焊盘206所取的剖面。如图2C和图2D所示，在凹槽222与输出焊盘206之间，还可以设置一支撑层223，且支撑层223覆盖凹槽222设置。支撑层223所用材料的硬度大于输出焊盘206的硬度，例如可以包括氮化铝AlN、氮化硅Si3N4中的至少一种，本申请实施例不做限定。
优选的，在凹槽222所填充的是空气时，在凹槽222与输出焊盘206之间设置支撑层223，从而可以防止焊盘变形，提高焊盘的机械强度。
需要说明的是，输出焊盘206下方的凹槽222可以为一个，也可以由布局比较密集的多个开口较小的凹槽组成，在这种情况下，如果凹槽填充的是空气，焊盘与凹槽之间也可不用另外设置支撑层，或者焊盘底层不设置硬度较大的金属层，也可以保障焊盘的机械强度，在此本申请实施例不做限定。另外，本申请实施例所描述的仅仅是SAW滤波器中的一种，即混合型SAW滤波器，本申请实施例还可以应用在梯形滤波器、DMS滤波器、横向耦合滤波器、平衡-非平衡滤波器等焊盘之间存在寄生电容的滤波器中，本申请实施例不做限定。
本申请实施例中，滤波器的压电基片上设置凹槽，且将具有电位差的焊盘中的至少一个设置在凹槽上，可以减少焊盘之间尤其是输入焊盘与输出焊盘之间的寄生电容，提高滤波器带外抑制水平，从而提高滤波器性能。
请参见图4，图4是本申请实施例提供的一种双工器的结构示意图。如图4所示，双工器包括发送端口TX，接收端口RX，天线端口ANT，以及发送滤波器401和接收滤波器402。在本申请实施例中，接收滤波器401和发送滤波器402中的至少有一个是如上述实施例所描述的任意一种滤波器。
在图4中，发送端口TX将信号输入发送滤波器401，经发送滤波器401滤波处理后，将处理过的信号通过天线端口ANT发送出去；天线端口ANT接收到外部信号并输入到接 收滤波器402，经接收滤波器402滤波处理后，通过接收端口RX输出。
图5A是本申请实施例提供的双工器的一信号仿真图，图5B是本申请实施例提供的双工器的另一信号仿真图，图5C是本申请实施例提供的双工器的信号隔离度图。其中，图5A-5C中虚线表示常规设计下双工器得通带信号，实线表示本申请实施例所描述的双工器的通带信号。图5A是发送端口TX与天线端口ANT之间的通带信号，图5B是接收端口RX与天线端口ANT之间的通带信号，而图5C是发送端口TX与接收端口RX之间的信号隔离度。由此可看出，本申请实施例所提供的双工器与常规设计的双工器相比，具有更好的带外抑制水平以及更好的隔离度。
需要说明的是，本申请实施例所描述的仅仅是本申请所应用的一种方案，本申请还可以应用在三工器、四工器等多工器中，本申请实施例不做限定。
本申请实施例还提供了一种包含如上所描述的任意一种滤波器的射频前端，本申请实施例不再进行详细说明。
本申请实施例中，滤波器由于可以减少寄生电容，提高带外抑制水平，从而可以提高该射频前端的性能，
请参见图6，图6是本申请实施例提供的一种制造滤波器的方法的流程示意图。如图6所示，该方法包括：
601、在压电基片的目标表面上形成凹槽，并在凹槽中沉积目标材料。
本申请实施例中，滤波器由压电基片、多个谐振器、输入焊盘、输出焊盘、接地焊盘和走线组成。走线用于焊盘与谐振器之间的连接，以及谐振器之间的连接。
压电基片的材料可以包括钽酸锂LiTaO3、铌酸锂LiNbO3中的至少一种。目标表面表示的是压电基片的某一表面，即上表面。在压电基片的目标表面上，首先通过刻蚀形成凹槽，然后在凹槽钟沉积目标材料，之后采用CMP工艺形成平坦表面。
其中，该凹槽可以是一个，也可以是多个，本申请实施例不做限定。该凹槽的形状可以是矩形、正方形、椭圆形、多边形、不规则图形等任意形状，本申请实施例不做限定。凹槽的深度范围可以为50nm～3um，本申请实施例不做限定。
602、在目标表面上形成导电图形，该导电图形由谐振器、走线和焊盘组成，其中，走线中的至少一个和/或焊盘中的至少一个位于凹槽上。
具体的，在压电基片形成有凹槽的同一表面，即目标表面上，垫一层光刻胶，通过曝光显影工艺，确定光刻胶导电图案，然后在光刻胶上沉积导电金属层，最后用去胶液溶解光刻胶，使导电金属层中非导电图案部分从压电基片上剥离，从而形成导电图形。
进一步的，还可以在形成导电图形的基础上，采用lift-off工艺对焊盘部分进行金属加厚。
本申请实施例中，导电图形可以包含多层金属层，导电图形包含谐振器，走线和焊盘，其中，谐振器由多个IDT和位于多个IDT两侧的反射器组层。IDT两排相对设置的金属汇流条以及连接两排汇流条交错设置的具有梳齿状的金属电极指组层，反射器也由金属材料组成。
本申请实施例中，在形成导电图形时，将走线中的至少一个或焊盘中的至少一个设置在位于压电基片的凹槽上。其中，走线或焊盘可以是部分或全部位于凹槽上。
在一种可行的实施方式中，目标材料为牺牲材料，在压电基片的目标表面上通过刻蚀形成凹槽，在凹槽中沉积牺牲材料，采用CMP工艺形成平坦表面之后，需要在凹槽上形成支撑层，通过刻蚀形成支撑层图形，支撑层与牺牲层之间存在形成通孔。在目标表面上形成导电图形后，通过通孔向凹槽注入腐蚀材料以刻蚀牺牲材料，其中，走线中的至少一个和/或焊盘中的至少一个具***于支撑层上。
其中，腐蚀材料可以是腐蚀液体或腐蚀气体，本申请实施例不做限定。支撑层可以是氮化铝AlN、钼Mo、钨W等中的至少一种，本申请实施例不做限定。支撑层的硬度大于形成导电图形的金属层硬度，且足够支撑凹槽上的走线或焊盘而不发生变形。
具体的，可以将牺牲材料硅Si溅射到凹槽中，腐蚀气体二氟化氙XeF2通过通孔注入凹槽，以对硅Si进行刻蚀。也可以将牺牲材料PSG填充到凹槽中，腐蚀液体氟化氢HF通过通孔注入凹槽，以对PSG进行刻蚀。本申请实施例不做限定。通过上述方式使得凹槽中填充空气。
可选的，通孔可以是一个也可以是多个，本申请实施例不做限定。
可选的，导电图形的底层具体可以是位于凹槽上方的走线和/或焊盘的底层可以为硬度较大的金属材料。
优选的，当凹槽填充的是空气时，导电图形的底层具体可以是位于凹槽上方的走线和/或焊盘的底层为硬度较大的金属材料。
在另一种可行的实施方式中，目标材料为绝缘材料，其中，该绝缘材料的介电常数小于压电基片的介电常数，一般为介电常数小于10的材料，例如可以是二氧化硅SiO2、氮化硅Si3N4等，本申请实施例不做限定。在本方案中，凹槽填充的是绝缘材料，因此，走线或焊盘可以覆盖凹槽，也可以位于绝缘材料上，本申请实施例不做限定。
需要说明的是，位于走线或焊盘下的凹槽可以是一个，也可以由布局比较密集的多个 开口较小的凹槽组成，本申请实施例不做限定。
通过本申请实施例，可以形成带有凹槽的压电基片，并在走线中的至少一个和/或焊盘中的至少一个形成于凹槽上，从而减小走线之间或焊盘之间的寄生电容，提高滤波器带外抑制水平，以提高滤波器性能。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种滤波器，包括：
    压电基片，所述压电基片设有凹槽；
    多个谐振器；
    焊盘，所述焊盘包括输入焊盘、输出焊盘和接地焊盘；
    走线，用于所述焊盘与所述多个谐振器之间的连接，以及所述多个谐振器之间的连接；
    其中，所述走线中的至少一个设于所述凹槽上。
  2. 如权利要求1所述的滤波器，其中，所述凹槽中填充有绝缘材料或空气，所述绝缘材料的介电常数小于所述压电基片的介电常数。
  3. 如权利要求2所述的滤波器，其中，所述绝缘材料的介电常数小于10。
  4. 如权利要求2所述的滤波器，其中，设于所述凹槽上的走线与所述凹槽之间设有支撑层，所述支撑层的硬度大于所述设于所述凹槽上的走线的硬度。
  5. 如权利要求1所述的滤波器，其中，所述走线部分设置在凹槽上，或者，所述走线全部设置在凹槽上。
  6. 如权利要求1所述的滤波器，其中，所述凹槽的剖面为梯形或矩形。
  7. 如权利要求1所述的滤波器，其中，所述凹槽的深度范围为50nm～3um。
  8. 一种滤波器，包括：
    压电基片，所述压电基片上设有凹槽；
    多个谐振器；
    焊盘，所述焊盘包括输入焊盘、输出焊盘和接地焊盘；
    走线，用于所述焊盘与所述多个谐振器之间的连接，以及所述多个谐振器之间的连接；
    其中，所述焊盘中的至少一个设于所述凹槽上。
  9. 如权利要求8所述的滤波器，其中，所述凹槽中填充有绝缘材料或空气，所述绝缘材料的介电常数小于所述压电基板的介电常数。
  10. 如权利要求9所述的滤波器，其中，所述绝缘材料的介电常数小于10。
  11. 如权利要求9所述的滤波器，其中，设于所述凹槽上的焊盘与所述凹槽之间设有支撑层，所述支撑层的硬度大于所述设于所述凹槽上的焊盘的硬度。
  12. 如权利要求8所述的滤波器，其中，所述焊盘部分设置在凹槽上，或者，所述焊盘全部设置在凹槽上。
  13. 如权利要求8所述的滤波器，其中，所述凹槽的剖面为梯形或矩形。
  14. 如权利要求8所述的滤波器，其中，所述凹槽的深度范围为50nm～3um。
  15. 一种多工器，包括：接收滤波器和发送滤波器，所述接收滤波器和所述发送滤波器中的至少一个包括如权利要求1-14中任一项所述的滤波器。
  16. 一种射频前端，包括如权利要求1-14中任一项所述的滤波器。
  17. 一种制造滤波器的方法，所述方法包括：
    在压电基片的目标表面上形成凹槽，并在所述凹槽中沉积目标材料；
    在所述目标表面上形成导电图形，所述导电图形由谐振器、走线和焊盘组成，其中，所述走线中的至少一个和/或所述焊盘中的至少一个位于所述凹槽上。
  18. 如权利要求17所述的方法，其中，所述目标材料为牺牲材料，所述在压电基片的目标表面上形成凹槽，并在所述凹槽中沉积目标材料之后，所述方法还包括：
    在所述凹槽上形成支撑层，所述支撑层包含通孔；
    所述在所述目标表面上形成导电图形之后，所述方法还包括：
    通过所述通孔向所述凹槽注入腐蚀材料以刻蚀所述牺牲材料；
    所述走线中的至少一个和/或所述焊盘中的至少一个位于所述凹槽上具体为：
    所述走线中的至少一个和/或所述焊盘中的至少一个位于所述支撑层上。
  19. 如权利要求17所述的方法，其中，所述目标材料为绝缘材料，所述绝缘材料的介电常数小于所述压电基片的介电常数。
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