WO2023125838A1 - 数据处理方法、装置、终端设备及计算机可读存储介质 - Google Patents
数据处理方法、装置、终端设备及计算机可读存储介质 Download PDFInfo
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
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- G06F17/153—Multidimensional correlation or convolution
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- the present application belongs to the technical field of data processing, and in particular relates to a data processing method, device, terminal equipment, and computer-readable storage medium.
- a neural network processor is a processor used to perform computational tasks of a neural network model, such as a neural network-based target detection task and target tracking task.
- the neural network model includes a variety of operators, such as convolution operators, conversion operators, and reorg operators.
- the neural network processor can more efficiently perform calculation tasks of some operators with relatively simple logic, such as convolution operators and transformation operators. However, for operators with complex logic such as the reorg operator, the execution efficiency of the neural network processor is low.
- Embodiments of the present application provide a data processing method, device, terminal equipment, and computer-readable storage medium, which can improve the execution efficiency of a neural network processor for logically complex operators.
- the embodiment of the present application provides a data processing method applied to a neural network processor, the method comprising:
- the tensor shape of the output tensor of the basic operator is converted to obtain a target tensor, and the tensor shape of the target tensor is consistent with the tensor shape of the output tensor of the operator to be processed.
- the second calculation parameter of the basic operator is set according to the first calculation parameter of the operator to be processed, so that the calculation task of the operator to be processed is performed by the basic operator; finally, the output of the basic operator is Quantities converted to a target tensor that conforms to the tensor shape of the output tensor of the operator being processed.
- it is equivalent to converting the calculation task corresponding to the operator to be processed into a calculation task composed of basic operators.
- the above method when the neural network processor performs logically complex image processing tasks or audio and video processing tasks, it can convert the logically complex processing tasks into logically simple processing tasks, which can effectively improve the execution efficiency of the neural network processor, thereby effectively improving the image quality.
- the processing efficiency of processing tasks or audio and video processing tasks can be converted into logically simple processing tasks, which can effectively improve the execution efficiency of the neural network processor, thereby effectively improving the image quality.
- the basic operator is a two-dimensional convolution operator, and correspondingly, the second calculation parameters include a weight matrix, a step size, and a convolution kernel;
- the setting the second calculation parameter of the basic operator of the neural network processor according to the first calculation parameter includes:
- the size of each dimension of the convolution kernel is set as the first calculation parameter.
- the generating the weight matrix includes:
- the basic operator is used to calculate the input tensor of the operator to be processed, and the input tensor of the basic operator is obtained.
- Output tensors including:
- the basic operator is used to calculate the first intermediate tensor to obtain an output tensor of the basic operator.
- converting the tensor shape of the input tensor of the operator to be processed to obtain the first intermediate tensor includes:
- converting the tensor shape of the output tensor of the basic operator to obtain the target tensor includes:
- the embodiment of the present application provides a data processing device, which is applied to a neural network processor, and the device includes:
- An acquisition unit configured to acquire the input tensor and the first calculation parameter of the operator to be processed
- a setting unit configured to set a second calculation parameter of a basic operator of the neural network processor according to the first calculation parameter
- a calculation unit configured to use the basic operator to calculate the input tensor of the operator to be processed based on the second calculation parameter, and obtain an output tensor of the basic operator;
- a conversion unit configured to convert the tensor shape of the output tensor of the basic operator to obtain a target tensor, the tensor shape of the target tensor is consistent with the tensor shape of the output tensor of the operator to be processed .
- an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein the processor executes the The computer program implements the data processing method as described in any one of the above first aspects.
- the embodiment of the present application provides a computer-readable storage medium
- the embodiment of the present application provides a computer-readable storage medium
- the computer-readable storage medium stores a computer program, and it is characterized in that the When the computer program is executed by the processor, the data processing method according to any one of the above-mentioned first aspects is realized.
- an embodiment of the present application provides a computer program product, which enables the terminal device to execute the data processing method described in any one of the above first aspects when the computer program product is run on the terminal device.
- Fig. 1 is a schematic diagram of the convolution process provided by the embodiment of the present application.
- Fig. 2 is a schematic diagram of data conversion provided by the embodiment of the present application.
- Fig. 3 is a schematic diagram of data processing of the reorg operator provided by the embodiment of the present application.
- FIG. 4 is a schematic flow diagram of a data processing method provided in an embodiment of the present application.
- Fig. 5 is a structural block diagram of a data processing device provided by an embodiment of the present application.
- FIG. 6 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
- the neural network model includes a variety of operators, such as convolution operators, conversion operators, and reorg operators. As an example, the following operators are introduced.
- FIG. 1 it is a schematic diagram of a convolution process provided by an embodiment of the present application.
- the left side is the image to be processed, each square represents a pixel of the image to be processed, and the number on the square represents the pixel value.
- the right side is the convolution kernel, and the numbers in the convolution kernel are weights.
- convolution is started from the upper left starting position of the image to be processed, and the convolution kernel is weighted with the pixels in the shaded box in the left figure to obtain a convolution value.
- the step size of the convolution is 1, that is, move the shadow box to the right by one pixel, as shown in (c) in Figure 1, continue to weight the pixels in the shadow box at this time with the convolution kernel to obtain the second convolution value.
- the final convolution value can be obtained, as shown in (d) in Figure 1.
- the size of the convolution kernel determines the size of the receptive field
- the size of the step size determines the accuracy of the extracted data.
- Conversion operators are used to implement data conversion, such as reshape operators are used to convert input data into data of a specific dimension. As shown in Figure 2, the left side is a 3 ⁇ 4 matrix A, and the target dimension is set to 2 ⁇ 6, and a 2 ⁇ 6 matrix B is obtained after reshape transformation.
- the reshape operator can not only realize the conversion of data dimensions, but also ensure that the original data remains unchanged.
- the reorg operator is used to rearrange data and connect feature maps of different levels and sizes together.
- the left side is a 2W ⁇ 2W feature map P
- the feature map is input into the reorg operator to obtain 4 W ⁇ W feature maps Q on the right side.
- Neural network processors are usually used to perform tasks such as image processing (such as target recognition, target tracking, etc.) and audio and video processing (such as sound detection, etc.).
- image processing such as target recognition, target tracking, etc.
- audio and video processing such as sound detection, etc.
- some logic-complex computing tasks are often involved.
- the neural network processor executes this operator to realize the rearrangement of image or audio and video features.
- the neural network processor can more efficiently perform calculation tasks of some operators with relatively simple logic, such as convolution operators and transformation operators.
- the execution efficiency of the neural network processor is low, which in turn affects the processing efficiency of image processing tasks or audio and video processing tasks.
- FIG. 4 it is a schematic flow diagram of a data processing method provided in an embodiment of the present application.
- the method may include the following steps:
- an operator to be processed refers to an operator with relatively complex calculation logic.
- the following embodiments take the reorg operator as an example for introduction.
- the input/output data of each layer in a neural network is usually tensor data, that is, multidimensional data.
- the dimensions of the input/output tensor are (N, C, H, W), where N represents the number of batches of two-dimensional data, C represents the number of channels, H represents the height of two-dimensional data, and W represents two The width of the dimension data.
- the tensor shape of the input tensor of the reorg operator is (N, C, H, W).
- the first calculation parameter is the stride (S).
- the basic operator in the embodiment of the present application refers to an operator with relatively simple calculation logic. It should be noted that, in the embodiment of the present application, one basic operator or a combination of multiple basic operators may be used to realize the calculation task of the operator to be processed. For easy description, the following embodiments take a convolution operator as an example for introduction.
- the basic operator is a two-dimensional convolution operator
- the second calculation parameters include a weight matrix, a step size, and a convolution kernel.
- S402 includes:
- the tensor shape of the weight matrix is determined by the first calculation parameter; the size of each dimension of the step size is set as the first calculation parameter; the convolution kernel The size of each dimension is set as the first computational parameter.
- the way to generate the weight matrix is:
- the identity matrix can be converted by using the reshape operator, and the specific conversion principle can refer to the description in the embodiment in FIG. 2 .
- the first parameter in the Reshape function is the input data
- the second parameter is the tensor shape of the output data.
- the input data is the unit matrix weight_in
- the tensor shape of the input tensor of the operator to be processed may be inconsistent with the tensor shape of the input data of the basic operator. In order to solve this problem, it is necessary to convert the tensor shape of the input tensor of the operator to be processed first.
- S403 includes:
- the way to obtain the first intermediate tensor is:
- the reshape operator can be used to convert the tensor shape of the input tensor of the operator to be processed. For the specific conversion principle, refer to the description in the embodiment in FIG. 2 .
- X is the first intermediate tensor.
- the tensor shape of the output tensor of the basic operator is inconsistent with the tensor shape of the output tensor of the operator to be processed.
- the tensor Quantitative shape conversion In order to obtain a calculation result equivalent to that of the operator to be processed, the tensor Quantitative shape conversion.
- the way to obtain the target tensor is:
- the reshape operator can be used to convert the tensor shape of the input tensor of the operator to be processed. For the specific conversion principle, refer to the description in the embodiment in FIG. 2 .
- the second calculation parameter of the basic operator is set according to the first calculation parameter of the operator to be processed, so that the calculation task of the operator to be processed is performed by the basic operator; finally, the output of the basic operator is Quantities converted to a target tensor that conforms to the tensor shape of the output tensor of the operator being processed.
- it is equivalent to converting the calculation task corresponding to the operator to be processed into a calculation task composed of basic operators.
- the above method when the neural network processor performs logically complex image processing tasks or audio and video processing tasks, it can convert logically complex processing tasks into logically simple processing tasks, effectively improving the execution efficiency of the neural network processor, thereby effectively improving the The processing efficiency of image processing tasks or audio and video processing tasks.
- converting the calculation task of the reorg operator to be realized by reshape and conv can improve the performance of the neural network processor. While improving execution efficiency, ensure that the execution result is consistent with the execution result of the reorg operator.
- FIG. 5 is a structural block diagram of a data processing device provided by the embodiment of the present application. For the convenience of description, only the parts related to the embodiment of the present application are shown.
- the device includes:
- the obtaining unit 51 is configured to obtain the input tensor and the first calculation parameter of the operator to be processed.
- a setting unit 52 configured to set a second calculation parameter of a basic operator of the neural network processor according to the first calculation parameter, wherein the algorithm complexity of the basic operator is lower than that of the operator to be processed Algorithmic complexity.
- the calculation unit 53 is configured to use the basic operator to calculate the input tensor of the operator to be processed based on the second calculation parameter, so as to obtain the output tensor of the basic operator.
- a conversion unit 54 configured to convert the tensor shape of the output tensor of the basic operator to obtain a target tensor, the tensor shape of the target tensor is the same as the tensor shape of the output tensor of the operator to be processed unanimous.
- the basic operator is a two-dimensional convolution operator
- the second calculation parameters include a weight matrix, a step size, and a convolution kernel.
- the setting unit 52 is also used for:
- the tensor shape of the weight matrix is determined by the first calculation parameter; the size of each dimension of the step size is set as the first calculation parameter; the convolution kernel The size of each dimension is set as the first computational parameter.
- the setting unit 52 is also used for:
- calculation unit 53 is also used for:
- the basic operator is used to calculate the first intermediate tensor to obtain an output tensor of the basic operator.
- calculation unit 53 is also used for:
- the conversion unit 54 is also used for:
- the data processing device shown in FIG. 5 may be a software unit, a hardware unit, or a combination of software and hardware built in existing terminal equipment, or it may be integrated into the terminal equipment as an independent pendant, or it may be Exists as an independent terminal device.
- FIG. 6 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
- the terminal device 6 of this embodiment includes: at least one processor 60 (only one is shown in FIG. 6), a processor, a memory 61, and stored in the memory 61 and can be processed in the at least one processor
- the terminal device may be computing devices such as desktop computers, notebooks, palmtop computers, and cloud servers.
- the terminal device may include, but not limited to, a processor and a memory.
- FIG. 6 is only an example of the terminal device 6, and does not constitute a limitation to the terminal device 6. It may include more or less components than those shown in the figure, or combine certain components, or different components. , for example, may also include input and output devices, network access devices, and so on.
- the so-called processor 60 can be a central processing unit (Central Processing Unit, CPU), and the processor 60 can also be other general processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit , ASIC), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
- a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
- the storage 61 may be an internal storage unit of the terminal device 6 in some embodiments, such as a hard disk or memory of the terminal device 6 .
- the memory 61 can also be an external storage device of the terminal device 6 in other embodiments, such as a plug-in hard disk equipped on the terminal device 6, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, flash memory card (Flash Card), etc. Further, the memory 61 may also include both an internal storage unit of the terminal device 6 and an external storage device.
- the memory 61 is used to store an operating system, an application program, a boot loader (Boot Loader), data, and other programs, such as program codes of the computer program.
- the memory 61 can also be used to temporarily store data that has been output or will be output.
- the embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in each of the foregoing method embodiments can be realized.
- An embodiment of the present application provides a computer program product.
- the terminal device can implement the steps in the foregoing method embodiments when executed.
- the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the procedures in the method of the above-mentioned embodiments in the present application can be completed by instructing related hardware through a computer program.
- the computer program can be stored in a computer-readable storage medium.
- the computer program When executed by a processor, the steps in the above-mentioned various method embodiments can be realized.
- the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form.
- the computer-readable medium may at least include: any entity or device capable of carrying computer program codes to a device/terminal device, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), electrical carrier signals, telecommunication signals, and software distribution media.
- ROM read-only memory
- RAM Random Access Memory
- electrical carrier signals telecommunication signals
- software distribution media Such as U disk, mobile hard disk, magnetic disk or optical disk, etc.
- computer readable media may not be electrical carrier signals and telecommunication signals under legislation and patent practice.
- the disclosed apparatus/terminal device and method may be implemented in other ways.
- the device/terminal device embodiments described above are only illustrative.
- the division of the modules or units is only a logical function division.
- the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
- the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
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Abstract
本申请适用于数据处理技术领域,提供了一种数据处理方法、装置、终端设备及计算机可读存储介质,应用于神经网络处理器,所述方法包括:获取待处理算子的输入张量和第一计算参数;根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数;基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量;转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。通过上述方法,可以提高神经网络处理器对逻辑复杂算子的执行效率。
Description
本申请要求于2021年12月30日提交中国专利局,申请号为202111652480.6、发明名称为“数据处理方法、装置、终端设备及计算机可读存储介质”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请属于数据处理技术领域,尤其涉及数据处理方法、装置、终端设备及计算机可读存储介质。
神经网络处理器是一种用于执行神经网络模型的计算任务的处理器,如用于执行基于神经网络的目标检测任务和目标跟踪任务等。神经网络模型中包括多种算子,如卷积算子、转换算子和reorg算子等。神经网络处理器可以较为高效地执行一些逻辑较为简单的算子的计算任务,如卷积算子和转换算子等。但对于如reorg算子这种逻辑较复杂的算子,神经网络处理器的执行效率较低。
发明内容
本申请实施例提供了一种数据处理方法、装置、终端设备及计算机可读存储介质,可以提高神经网络处理器对逻辑复杂算子的执行效率。
第一方面,本申请实施例提供了一种数据处理方法,应用于神经网络处理器,所述方法包括:
获取待处理算子的输入张量和第一计算参数;
根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数,其中,所述基础算子的算法复杂度低于所述待处理算子的算法复杂度;
基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量;
转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。
在本申请实施例中,根据待处理算子的第一计算参数设置基础算子的第二计算参数,以通过基础算子来执行待处理算子的计算任务;最后将基础算子的输出张量转换为符合待处理算子的输出张量的张量形状的目标张量。上述方法中,相当于将待处理算子对应的计算任务转为由基础算子组成的计算任务,由于基础算子的算法复杂度比待处理算子的算法复杂度低,因此,通过上述方法,当神经网络处理器执行逻辑复杂的图像处理任务或音视频处理任务时,可以将逻辑复杂的处理任务转换为逻辑简单的处理任务,可以有效提高神经网络处理器的执行效率,进而有效提高图像处理任务或音视频处理任务的处理效率。
在第一方面的一种可能的实现方式中,所述基础算子为二维卷积算子,相应的,所述第二计算参数包括权重矩阵、步长和卷积核;
所述根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数,包括:
生成所述权重矩阵,其中,所述权重矩阵的张量形状由所述第一计算参数确定;
将所述步长每个维度的大小设置为所述第一计算参数;
将所述卷积核每个维度的大小设置为所述第一计算参数。
在第一方面的一种可能的实现方式中,所述生成所述权重矩阵,包括:
根据所述第一计算参数计算第一张量形状;
获取与所述第一计算参数相匹配的单位矩阵;
将所述单位矩阵转换为符合所述第一张量形状的权重矩阵。
在第一方面的一种可能的实现方式中,所述基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量,包括:
转换所述待处理算子的输入张量的张量形状,获得第一中间张量,所述第一中间张量的张量形状与所述第二计算参数相匹配;
基于所述第二计算参数,利用所述基础算子对所述第一中间张量进行计算, 获得所述基础算子的输出张量。
在第一方面的一种可能的实现方式中,所述转换所述待处理算子的输入张量的张量形状,获得第一中间张量,包括:
根据所述待处理算子的输入张量的张量形状和所述第一计算参数,计算第二张量形状;
将所述待处理算子的输入张量转换为符合所述第二张量形状的所述第一中间张量。
在第一方面的一种可能的实现方式中,所述转换所述基础算子的输出张量的张量形状,获得目标张量,包括:
根据所述待处理算子的输入张量的张量形状和所述第一计算参数计算第三张量形状;
将所述基础算子的输出张量转换为符合所述第三张量形状的所述目标张量。
第二方面,本申请实施例提供了一种数据处理装置,应用于神经网络处理器,所述装置包括:
获取单元,用于获取待处理算子的输入张量和第一计算参数;
设置单元,用于根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数;
计算单元,用于基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量;
转换单元,用于转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。
第三方面,本申请实施例提供了一种终端设备,包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序,其特征在于,所述处理器执行所述计算机程序时实现如上述第一方面中任一项所述的数据处理方法。
第四方面,本申请实施例提供了一种计算机可读存储介质,本申请实施例提供了一种计算机可读存储介质,所述计算机可读存储介质存储有计算机程序,其特征在于,所述计算机程序被处理器执行时实现如上述第一方面中任一项所述的数据处理方法。
第五方面,本申请实施例提供了一种计算机程序产品,当计算机程序产品在终端设备上运行时,使得终端设备执行上述第一方面中任一项所述的数据处理方法。
可以理解的是,上述第二方面至第五方面的有益效果可以参见上述第一方面中的相关描述,在此不再赘述。
下面将对本申请实施例中所需要使用的附图作介绍。
图1是本申请实施例提供的卷积过程示意图;
图2是本申请实施例提供数据转换的示意图;
图3是本申请实施例提供的reorg算子的数据处理示意图;
图4是本申请实施例提供的数据处理方法的流程示意图;
图5是本申请实施例提供的数据处理装置的结构框图;
图6是本申请实施例提供的终端设备的结构示意图。
下面结合附图对本申请的实施例进行描述。
首先介绍本申请的技术背景。
神经网络模型中包括多种算子,如卷积算子、转换算子和reorg算子等。示例性的,介绍以下几种算子。
卷积算子用于实现卷积计算。参见图1,是本申请实施例提供的卷积过程示意图。如图1中的(a)所示,左侧为待处理图像,每个方格表示待处理图像的一个像素,方格上的数字表示像素值。右侧为卷积核,卷积核中的数字为权值。如图1中的(b)所示,从待处理图像的左上方起始位置开始卷积,将卷积 核与左侧图中阴影框内的像素进行加权,获得一个卷积值。假设卷积的步长为1,即将阴影框向右移动一个像素,如图1中的(c)所示,继续将此时的阴影框内的像素与卷积核进行加权,获得第二个卷积值。依次类推,可以得到最终的卷积值,如图1中的(d)所示。其中,卷积核的大小决定了感受野的大小,步长的大小决定了提取数据的精度。
转换算子用于实现数据的转换,如reshape算子用于将输入数据转换为特定维度的数据。如图2所示,左侧为3×4的矩阵A,设置目标维度为2×6,通过reshape转换后得到2×6的矩阵B。reshape算子既可以实现数据维度的转换,又可以保证原有数据不变。
reorg算子用于实现数据的重排,将不同层级不同大小的特征图连接在一起。如图3所示,左侧为2W×2W的特征图P,将该特征图输入reorg算子,可以得到右侧的4个W×W的特征图Q。每次从特征图P中取4个元素分别分配给4个特征图Q,按照这种方式从左到右,从上到下遍历就可以得到4个W*W的特征图Q。
神经网络处理器通常用于执行图像处理(如目标识别、目标跟踪等)和音视频处理(如声音检测等)等任务,在执行上述处理任务的过程中,往往涉及一些逻辑较为复杂的计算任务。例如,上述的reorg算子,神经网络处理器执行该算子,以实现对图像或音视频特征的重排。神经网络处理器可以较为高效地执行一些逻辑较为简单的算子的计算任务,如卷积算子和转换算子等。但对于如reorg算子这种逻辑较复杂的算子,神经网络处理器的执行效率较低,进而影响图像处理任务或音视频处理任务的处理效率。
为了解决上述问题,本申请实施例提供了一种数据处理方法。参见图4,是本申请实施例提供的数据处理方法的流程示意图,作为示例而非限定,所述方法可以包括以下步骤:
S401,获取待处理算子的输入张量和第一计算参数。
本申请实施例中的,待处理算子指计算逻辑较为复杂的算子。为了便于描 述,下面实施例以reorg算子为例进行介绍。
神经网络中每个层的输入/输出数据通常为张量数据,即多维数据。通常,输入/输出张量的维度为(N,C,H,W),其中,N表示二维数据的批数(batch),C表示通道数,H表示二维数据的高,W表示二维数据的宽。
reorg算子的输入张量的张量形状为(N,C,H,W),如上述reorg算子的计算逻辑代码所示,其第一计算参数为步长stride(S)。
S402,根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数。
本申请实施例中的基础算子指计算逻辑较为简单的算子。需要说明的是,本申请实施例中,可以采用一个基础算子或多个基础算子的组合来实现待处理算子的计算任务。为了便宜描述,下面实施例以卷积算子为例进行介绍。
在一个实施例中,所述基础算子为二维卷积算子,相应的,所述第二计算参数包括权重矩阵、步长和卷积核。
相应的,S402包括:
生成所述权重矩阵,其中,所述权重矩阵的张量形状由所述第一计算参数确定;将所述步长每个维度的大小设置为所述第一计算参数;将所述卷积核每个维度的大小设置为所述第一计算参数。
可选的,生成权重矩阵的方式为:
根据所述第一计算参数计算第一张量形状;获取与所述第一计算参数相匹配的单位矩阵;将所述单位矩阵转换为符合所述第一张量形状的权重矩阵。
具体的,第一张量形状可以根据公式new_shape1=(S*S,1,S,S))确定,其中,S为第一计算参数,即reorg算子中的步长。
单位矩阵每个维度的大小为S×S,即张量形状为(S×S,S×S)。例如,若S=2,则单位矩阵为:
可以利用reshape算子对单位矩阵进行转换,具体的转换原理可以参见图2实施例中的描述。示例性的,通过函数Weight_out=Reshape(weight_in,new_shape=(S*S,1,S,S))表示转换过程。其中,Reshape函数中第一个参数为输入数据,第二个参数为输出数据的张量形状。上述函数中,输入数据为单位矩阵weight_in,输出数据的张量形状为第一张量形状new_shape1=(S*S,1,S,S))。
示例性的,当卷积核为二维时,卷积核的大小为[S,S],相应的,步长也为[S,S]。
S403,基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量。
待处理算子的输入张量的张量形状与基础算子的输入数据的张量形状可能是不一致。为了解决该问题,需要先对待处理算子的输入张量的张量形状进行转换。
在一个实施例中,S403包括:
转换所述待处理算子的输入张量的张量形状,获得第一中间张量,所述第一中间张量的张量形状与所述第二计算参数相匹配;基于所述第二计算参数,利用所述基础算子对所述第一中间张量进行计算,获得所述基础算子的输出张量。
可选的,获取第一中间张量的方式为:
根据所述待处理算子的输入张量的张量形状和所述第一计算参数,计算第二张量形状;将所述待处理算子的输入张量转换为符合所述第二张量形状的所述第一中间张量。
具体的,第二张量形状可以通过公式new_shape2=(N,1,C*H/S,W*S)确定。 可以利用reshape算子对待处理算子的输入张量的张量形状进行转换,具体的转换原理可以参见图2实施例中的描述。
将基础算子的参数设置为第二计算参数。获得第一中间张量之后,将第一中间张量作为基础算子的输入数据,由基础算子计算后,得到基础算子的输出张量。
示例性的,通过函数Y=Conv2D(X,Weight_out,strides=(S,S),kernel_size=(S,S))表示卷积算子的计算。其中,X为第一中间张量。
S404,转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。
基础算子的输出张量的张量形状与待处理算子的输出张量的张量形状不一致,为了获取与待处理算子等价的计算结果,需要对基础算子的输出张量的张量形状进行转换。
在一个实施例中,获取目标张量的方式为:
根据所述待处理算子的输入张量的张量形状和所述第一计算参数计算第一张量形状;将所述基础算子的输出张量转换为符合所述第一张量形状的所述目标张量。
具体的,第三张量形状可以通过公式new_shape3=(N,C*S*S,H/S,W/S)确定。同样的,可以利用reshape算子对待处理算子的输入张量的张量形状进行转换,具体的转换原理可以参见图2实施例中的描述。
在本申请实施例中,根据待处理算子的第一计算参数设置基础算子的第二计算参数,以通过基础算子来执行待处理算子的计算任务;最后将基础算子的输出张量转换为符合待处理算子的输出张量的张量形状的目标张量。上述方法中,相当于将待处理算子对应的计算任务转为由基础算子组成的计算任务,由于基础算子的算法复杂度比待处理算子的算法复杂度低,因此,通过上述方法,当神经网络处理器执行逻辑复杂的图像处理任务或音视频处理任务时,可以将逻辑复杂的处理任务转换为逻辑简单的处理任务,有效提高了神经网络处理器 的执行效率,进而有效提高了图像处理任务或音视频处理任务的处理效率。
另外,由于reshape的过程不会丢失数据,可以保证原有数据不变,因此,将reorg算子的计算任务转换为由reshape和conv(卷积算子)实现,可以在提高神经网络处理器的执行效率的同时,保证执行结果与reorg算子的执行结果一致。
应理解,上述实施例中各步骤的序号的大小并不意味着执行顺序的先后,各过程的执行顺序应以其功能和内在逻辑确定,而不应对本申请实施例的实施过程构成任何限定。
对应于上文实施例所述的数据处理方法,图5是本申请实施例提供的数据处理装置的结构框图,为了便于说明,仅示出了与本申请实施例相关的部分。
参照图5,该装置包括:
获取单元51,用于获取待处理算子的输入张量和第一计算参数。
设置单元52,用于根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数,其中,所述基础算子的算法复杂度低于所述待处理算子的算法复杂度。
计算单元53,用于基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量。
转换单元54,用于转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。
可选的,所述基础算子为二维卷积算子,相应的,所述第二计算参数包括权重矩阵、步长和卷积核。
相应的,设置单元52还用于:
生成所述权重矩阵,其中,所述权重矩阵的张量形状由所述第一计算参数确定;将所述步长每个维度的大小设置为所述第一计算参数;将所述卷积核每个维度的大小设置为所述第一计算参数。
可选的,设置单元52还用于:
根据所述第一计算参数计算第一张量形状;
获取与所述第一计算参数相匹配的单位矩阵;
将所述单位矩阵转换为符合所述第一张量形状的权重矩阵。
可选的,计算单元53还用于:
转换所述待处理算子的输入张量的张量形状,获得第一中间张量,所述第一中间张量的张量形状与所述第二计算参数相匹配;
基于所述第二计算参数,利用所述基础算子对所述第一中间张量进行计算,获得所述基础算子的输出张量。
可选的,计算单元53还用于:
根据所述待处理算子的输入张量的张量形状和所述第一计算参数,计算第二张量形状;
将所述待处理算子的输入张量转换为符合所述第二张量形状的所述第一中间张量。
可选的,转换单元54还用于:
根据所述待处理算子的输入张量的张量形状和所述第一计算参数计算第三张量形状;
将所述基础算子的输出张量转换为符合所述第三张量形状的所述目标张量。
需要说明的是,上述装置/单元之间的信息交互、执行过程等内容,由于与本申请方法实施例基于同一构思,其具体功能及带来的技术效果,具体可参见方法实施例部分,此处不再赘述。
另外,图5所示的数据处理装置可以是内置于现有的终端设备内的软件单元、硬件单元、或软硬结合的单元,也可以作为独立的挂件集成到所述终端设备中,还可以作为独立的终端设备存在。
所属领域的技术人员可以清楚地了解到,为了描述的方便和简洁,仅以上述各功能单元、模块的划分进行举例说明,实际应用中,可以根据需要而将上 述功能分配由不同的功能单元、模块完成,即将所述装置的内部结构划分成不同的功能单元或模块,以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中,上述集成的单元既可以采用硬件的形式实现,也可以采用软件功能单元的形式实现。另外,各功能单元、模块的具体名称也只是为了便于相互区分,并不用于限制本申请的保护范围。上述***中单元、模块的具体工作过程,可以参考前述方法实施例中的对应过程,在此不再赘述。
图6是本申请实施例提供的终端设备的结构示意图。如图6所示,该实施例的终端设备6包括:至少一个处理器60(图6中仅示出一个)处理器、存储器61以及存储在所述存储器61中并可在所述至少一个处理器60上运行的计算机程序62,所述处理器60执行所述计算机程序62时实现上述任意各个数据处理方法实施例中的步骤。
所述终端设备可以是桌上型计算机、笔记本、掌上电脑及云端服务器等计算设备。该终端设备可包括,但不仅限于,处理器、存储器。本领域技术人员可以理解,图6仅仅是终端设备6的举例,并不构成对终端设备6的限定,可以包括比图示更多或更少的部件,或者组合某些部件,或者不同的部件,例如还可以包括输入输出设备、网络接入设备等。
所称处理器60可以是中央处理单元(Central Processing Unit,CPU),该处理器60还可以是其他通用处理器、数字信号处理器(Digital Signal Processor,DSP)、专用集成电路(Application Specific Integrated Circuit,ASIC)、现成可编程门阵列(Field-Programmable Gate Array,FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器61在一些实施例中可以是所述终端设备6的内部存储单元,例如终端设备6的硬盘或内存。所述存储器61在另一些实施例中也可以是所述终 端设备6的外部存储设备,例如所述终端设备6上配备的插接式硬盘,智能存储卡(Smart Media Card,SMC),安全数字(Secure Digital,SD)卡,闪存卡(Flash Card)等。进一步地,所述存储器61还可以既包括所述终端设备6的内部存储单元也包括外部存储设备。所述存储器61用于存储操作***、应用程序、引导装载程序(Boot Loader)、数据以及其他程序等,例如所述计算机程序的程序代码等。所述存储器61还可以用于暂时地存储已经输出或者将要输出的数据。
本申请实施例还提供了一种计算机可读存储介质,所述计算机可读存储介质存储有计算机程序,所述计算机程序被处理器执行时实现可实现上述各个方法实施例中的步骤。
本申请实施例提供了一种计算机程序产品,当计算机程序产品在终端设备上运行时,使得终端设备执行时实现可实现上述各个方法实施例中的步骤。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。基于这样的理解,本申请实现上述实施例方法中的全部或部分流程,可以通过计算机程序来指令相关的硬件来完成,所述的计算机程序可存储于一计算机可读存储介质中,该计算机程序在被处理器执行时,可实现上述各个方法实施例的步骤。其中,所述计算机程序包括计算机程序代码,所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质至少可以包括:能够将计算机程序代码携带到装置/终端设备的任何实体或装置、记录介质、计算机存储器、只读存储器(ROM,Read-Only Memory)、随机存取存储器(RAM,Random Access Memory)、电载波信号、电信信号以及软件分发介质。例如U盘、移动硬盘、磁碟或者光盘等。在某些司法管辖区,根据立法和专利实践,计算机可读介质不可以是电载波信号和电信信号。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述或记载的部分,可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到,结合本文中所公开的实施例描述的各示例的单元及算法步骤,能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中,应该理解到,所揭露的装置/终端设备和方法,可以通过其它的方式实现。例如,以上所描述的装置/终端设备实施例仅仅是示意性的,例如,所述模块或单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个***,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口,装置或单元的间接耦合或通讯连接,可以是电性,机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
以上所述实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围,均应包含在本申请的保护范围之内。
Claims (10)
- 一种数据处理方法,其特征在于,应用于神经网络处理器,所述方法包括:获取待处理算子的输入张量和第一计算参数;根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数,其中,所述基础算子的算法复杂度低于所述待处理算子的算法复杂度;基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量;转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。
- 如权利要求1所述的数据处理方法,其特征在于,所述基础算子为二维卷积算子,相应的,所述第二计算参数包括权重矩阵、步长和卷积核;所述根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数,包括:生成所述权重矩阵,其中,所述权重矩阵的张量形状由所述第一计算参数确定;将所述步长每个维度的大小设置为所述第一计算参数;将所述卷积核每个维度的大小设置为所述第一计算参数。
- 如权利要求2所述的数据处理方法,其特征在于,所述生成所述权重矩阵,包括:根据所述第一计算参数计算第一张量形状;获取与所述第一计算参数相匹配的单位矩阵;将所述单位矩阵转换为符合所述第一张量形状的权重矩阵。
- 如权利要求1所述的数据处理方法,其特征在于,所述基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量,包括:转换所述待处理算子的输入张量的张量形状,获得第一中间张量,所述第一中间张量的张量形状与所述第二计算参数相匹配;基于所述第二计算参数,利用所述基础算子对所述第一中间张量进行计算,获得所述基础算子的输出张量。
- 如权利要求4所述的数据处理方法,其特征在于,所述转换所述待处理算子的输入张量的张量形状,获得第一中间张量,包括:根据所述待处理算子的输入张量的张量形状和所述第一计算参数,计算第二张量形状;将所述待处理算子的输入张量转换为符合所述第二张量形状的所述第一中间张量。
- 如权利要求1所述的数据处理方法,其特征在于,所述转换所述基础算子的输出张量的张量形状,获得目标张量,包括:根据所述待处理算子的输入张量的张量形状和所述第一计算参数计算第三张量形状;将所述基础算子的输出张量转换为符合所述第三张量形状的所述目标张量。
- 一种数据处理装置,其特征在于,应用于神经网络处理器,所述装置包括:获取单元,用于获取待处理算子的输入张量和第一计算参数;设置单元,用于根据所述第一计算参数设置所述神经网络处理器的基础算子的第二计算参数,其中,所述基础算子的算法复杂度低于所述待处理算子的算法复杂度;计算单元,用于基于所述第二计算参数,利用所述基础算子对所述待处理算子的输入张量进行计算,获得所述基础算子的输出张量;转换单元,用于转换所述基础算子的输出张量的张量形状,获得目标张量,所述目标张量的张量形状与所述待处理算子的输出张量的张量形状一致。
- 如权利要求7所述的数据处理装置,其特征在于,所述基础算子为二维卷积算子,相应的,所述第二计算参数包括权重矩阵、步长和卷积核;所述设置单元还用于:生成所述权重矩阵,其中,所述权重矩阵的张量形状由所述第一计算参数确定;将所述步长每个维度的大小设置为所述第一计算参数;将所述卷积核每个维度的大小设置为所述第一计算参数。
- 一种终端设备,包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序,其特征在于,所述处理器执行所述计算机程序时实现如权利要求1至6任一项所述的方法。
- 一种计算机可读存储介质,所述计算机可读存储介质存储有计算机程序,其特征在于,所述计算机程序被处理器执行时实现如权利要求1至6任一项所述的方法。
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