WO2023125212A1 - 数据传输方法、装置、设备及介质 - Google Patents
数据传输方法、装置、设备及介质 Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/14—Handling requests for interconnection or transfer
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present disclosure relates to the field of information technology, and in particular to a data transmission method, device, equipment and medium.
- the present disclosure provides a data transmission method, device, device, medium, computer program product and computer program.
- an embodiment of the present disclosure provides a data transmission method, including:
- Receive the data packet to be transmitted, the data packet to be transmitted includes the data to be transmitted and chip identification information;
- first PCIE physical layer ports determine the target first PCIE physical layer port corresponding to the chip identification information, and a plurality of first PCIE physical layer ports are interconnected with a plurality of chips in one-to-one correspondence;
- the data packet to be transmitted is sent to the receiving chip through the target first PCIE physical layer port, and the receiving chip is a chip interconnected with the target first PCIE physical layer port.
- an embodiment of the present disclosure provides a data transmission method, including:
- the second PCIE physical layer port of the target is a port interconnected with the sending chip among the multiple second PCIE physical layer ports, and the multiple second PCIE physical layer ports are connected to multiple chips One-to-one correspondence interconnection, the data packet to be transmitted includes the data to be transmitted and the chip identification information;
- the data packet to be transmitted is sent to the local user layer.
- an embodiment of the present disclosure provides a data transmission device, including:
- the data packet receiving module is used to receive the data packet to be transmitted, and the data packet to be transmitted includes the data to be transmitted and chip identification information;
- the first port determination module is used to determine the target first PCIE physical layer port corresponding to the chip identification information in a plurality of first PCIE physical layer ports, and a plurality of first PCIE physical layer ports are interconnected with a plurality of chips in one-to-one correspondence;
- the data packet distribution module is used to distribute the data packets to be transmitted to the first PCIE physical layer port of the target;
- the data packet sending module is used to send the data packet to be transmitted to the receiving chip through the first PCIE physical layer port of the target, and the receiving chip is a chip interconnected with the first PCIE physical layer port of the target.
- an embodiment of the present disclosure provides a data transmission device, including:
- the data packet sending module is used to receive the data packet to be transmitted through the second PCIE physical layer port of the target, and the second PCIE physical layer port of the target is a port interconnected with the sending chip in a plurality of second PCIE physical layer ports, and the plurality of second PCIE physical layer ports
- the physical layer port is interconnected with multiple chips in one-to-one correspondence, and the data packet to be transmitted includes the data to be transmitted and chip identification information;
- the data packet receiving module is configured to send the data packet to be transmitted to the local user layer when it is determined that the chip identification information is the same as the local chip identification information.
- an embodiment of the present disclosure provides a data transmission device, including:
- the processor is used to read executable instructions from the memory, and execute the executable instructions to implement the data transmission method of the first aspect or the second aspect.
- an embodiment of the present disclosure provides a computer-readable storage medium, the storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the data transmission method of the first aspect or the second aspect .
- an embodiment of the present disclosure provides a computer program product, including a computer program, when the computer program is executed by a processor, the data transmission method of the first aspect or the second aspect is implemented.
- an embodiment of the present disclosure provides a computer program, the computer program includes computer program code, and when the computer program code is run on a computer, the computer executes the data transmission method of the first aspect or the second aspect .
- the data transmission method, device, equipment, medium, computer program product, and computer program of the embodiments of the present disclosure can be interconnected with multiple chips one by one through multiple first PCIE physical layer ports, and when performing data transmission, determine and wait The target first PCIE physical layer port corresponding to the chip identification information in the transmission data packet, and then the data can be transmitted to the receiving chip through the target first PCIE physical layer port. Since the first PCIE physical layer port interconnected with multiple chips in one-to-one correspondence can realize direct and high-bandwidth mutual transmission of information between multiple chips, thereby improving the data transmission efficiency between multiple chips.
- FIG. 1 shows a schematic diagram of a data transmission architecture provided by an embodiment of the present disclosure
- FIG. 2 shows a schematic diagram of another data transmission architecture provided by an embodiment of the present disclosure
- FIG. 3 shows a schematic flowchart of a data transmission method provided by an embodiment of the present disclosure
- FIG. 4 shows a schematic flowchart of another data transmission method provided by an embodiment of the present disclosure
- FIG. 5 shows a schematic flowchart of another data transmission method provided by an embodiment of the present disclosure
- FIG. 6 shows a schematic flowchart of another data transmission method provided by an embodiment of the present disclosure
- FIG. 7 shows a schematic structural diagram of a data transmission device provided by an embodiment of the present disclosure
- FIG. 8 shows a schematic structural diagram of another data transmission device provided by an embodiment of the present disclosure.
- Fig. 9 is a schematic structural diagram of a data transmission device provided by an embodiment of the present disclosure.
- the term “comprise” and its variations are open-ended, ie “including but not limited to”.
- the term “based on” is “based at least in part on”.
- the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one further embodiment”; the term “some embodiments” means “at least some embodiments.” Relevant definitions of other terms will be given in the description below.
- the embodiments of the present disclosure provide a data transmission method, device, device, and medium, which can realize direct and high-bandwidth transmission of information between multiple chips by using one-to-one interconnected PCIE physical layer ports.
- Mutual transmission improves the efficiency of data transmission between multiple chips, such as high-speed data transmission in the scenario of multi-chip big data interaction.
- a multi-chip high-speed Serializer/Deserializer (Serializer/Deserializer, SerDer) technology can be realized based on the idea of an Ethernet switch and the idea of high-speed data transmission of the PCIE protocol.
- FIG. 1 shows a schematic diagram of a data transmission architecture provided by an embodiment of the present disclosure.
- the data transmission architecture of each chip may include a user layer (User Layer) 110, a protocol layer 120, and multiple PCIE physical layer ports.
- User Layer User Layer
- protocol layer 120 a protocol layer
- PCIE physical layer ports Exemplarily, taking data exchange between 4 chips C1-C4 as an example, each chip may include 3 PCIE physical layer ports. The 3 PCIE physical layer ports can be interconnected with the remaining 3 chips one by one.
- any two chips can perform bidirectional data exchange through the PCIE physical layer port interconnected between them.
- the chip C1 and the chip C2 can transmit information to each other through their respective PCIE physical layer ports 131 .
- the number of interconnected chips is not limited to 4, but can also be 3 or more. The number of interconnected chips can be set according to actual scenarios and specific needs, and is not specifically limited.
- the user layer 110 of the chip C1 can generate a data packet to be transmitted based on the data to be transmitted input by the user and the chip identification information of the chip C4. Then the user layer 110 of the chip C1 sends the data packet to be transmitted to the protocol layer 120 of the chip C1.
- the protocol layer 120 of the chip C1 determines the PCIE physical layer port interconnected with the chip C4 among the multiple PCIE physical layer ports of the chip C1 through the chip identification information of the chip C4 in the data packet to be transmitted, that is, the PCIE physical layer port 133 of the chip C1 .
- the data packet to be transmitted is sent to the PCIE physical layer port 131 of the chip C4 by the PCIE physical layer port 133 of the chip C1, so that the direct and direct communication of information between multiple chips can be realized through the PCIE physical layer port interconnected with a plurality of chips one by one.
- High-bandwidth mutual transmission improves the efficiency of data transmission between multiple chips.
- the PCIE physical layer port 131 of the chip C4 uploads the received data packet to be transmitted to the protocol layer 120.
- the protocol layer 120 of the chip C4 judges whether the chip identification information in the data packet to be transmitted is the same as the chip identification information of the chip C4. If they are the same, the protocol layer 12 of the chip C4 continues to send the data packet to be transmitted to the user of the chip C4. Layer, so that the direct and high-bandwidth mutual transmission of information between multiple chips can be realized through the PCIE physical layer port interconnected with multiple chips one by one, which improves the data transmission efficiency between multiple chips.
- the protocol layer 120 of chip C4 determines that the chip identification information in the data packet to be transmitted is different from the chip identification information of chip C4, for example, the chip identification information in the data packet to be transmitted is chip C3 chip identification information, then the protocol layer 120 of the chip C4 can distribute the data packet to be transmitted to the PCIE physical layer port 133 of the chip C4 (that is, the physical layer port interconnected with the chip C3), thereby the PCIE physical layer of the chip C4 can The port 133 sends the data packet to be transmitted to the PCIE physical layer port 132 of the chip C3, so that high-speed data forwarding can be realized.
- PCIE physical layer ports 131 to 133 in the embodiment of the present disclosure may be ports encapsulated with a PCIE physical layer, so as to realize high-speed SerDer data transmission.
- the user can define the data to be transmitted and the chip identification information of the receiving chip for the data to be transmitted at this layer.
- a PCIE physical layer port may include two physical layers.
- FIG. 2 shows a schematic diagram of another data transmission architecture provided by an embodiment of the present disclosure.
- each PCIE physical layer port includes a first physical layer (phy layer) and a second physical layer (Physical layer).
- the PCIE physical layer port 131 may include a phy layer 1311 and a Physical layer 1312
- the PCIE physical layer port 132 may include a phy layer 1321 and a Physical layer 1322
- the PCIE physical layer port 133 may include a phy layer 1331 and a Physical layer 1332 .
- the phy layer and the Physical layer can mainly implement the physical coding sublayer (Physical coding sublayer, PCS) sublayer, physical medium attachment (Physical Medium Attachment, PMA) sublayer and physical medium related (Physical Medium Dependent, PMD)
- PCS Physical coding sublayer
- PMA Physical Medium Attachment
- PMD Physical Medium Dependent
- the PMD sublayer may be an electrical block responsible for serial signal transmission.
- the PMA sublayer can be responsible for serialization/deserialization, and the PCS sublayer can be responsible for encoding/decoding of data streams.
- the protocol layer 120 may include a data link layer (Data link layer) and a transport layer (Transaction layer).
- the data link layer can perform data interaction with one or more PCIE physical layer ports.
- it may be multiple data link layers corresponding to multiple PCIE physical layer ports one-to-one.
- it may be a data link layer that performs data transmission with multiple PCIE physical layer ports, which is not limited.
- the protocol layer 120 includes three data link layers 1211 to 1213 and a transport layer 122 .
- each data link layer corresponds to a PCIE physical layer port.
- the data link layer 1211 corresponds to the phy layer 1311 and the physical layer 1312 of the PCIE physical layer port 131 .
- the data link layer 1211 can receive the data packet to be transmitted sent by the PCIE physical layer port 131, and after performing data alignment on the data packet to be transmitted, send the aligned data packet to be transmitted to the transport layer 122, so that the physical layer 122 can be strengthened.
- other data link layers may perform data alignment on their corresponding physical layer ports, which will not be repeated here.
- the data link layer 1211 can receive the data packet to be transmitted sent by the transport layer 122, and after performing data alignment on the data packet to be transmitted, send the aligned data packet to be transmitted to the PCIE physical layer corresponding to the chip identification information port, so that the function of the original bit stream transmitted by the physical layer port can be enhanced.
- other data link layers can perform data alignment on the transport layer, which will not be repeated here.
- the data link layer 1212 can perform error monitoring on the PCIE physical layer port 132, specifically, modify the possible error physical link provided by the PCIE physical layer port into a logically error-free data link, thereby improving the stability of data transmission sex.
- other data link layers may perform error monitoring on their corresponding PCIE physical layer ports, which will not be repeated here.
- the above data link layer can be used to establish data links with other chips, and perform data transmission between the PCIE physical layer port and the transport layer.
- transport layer mainly deals with the transaction of transmission. For example, group or unpack specific data packets so that the upper or lower layers can further process the data packets, and interweave and distribute data between multiple PCIE physical layer ports and the user layer.
- Fig. 3 shows a schematic flowchart of a data transmission method provided by an embodiment of the present disclosure.
- the data transmission method shown in FIG. 3 may be applied to a chip that needs to perform data transmission among multiple chips, that is, the sending chip, which is not specifically limited.
- the plurality of chips may be multiple control chips in one driving controller of the vehicle or chips in different driving controllers, which is not specifically limited.
- the data transmission method may include the following steps: S310-S340.
- the data packet to be transmitted includes data to be transmitted and chip identification information.
- the data packet to be transmitted may be received through the user layer of the sending chip itself.
- the sending chip may be a chip sending data packets to be transmitted,
- the data to be transmitted may be user-defined data that needs to be transmitted to the receiving chip.
- the data to be transmitted may include chip configuration data of the receiving chip, control instructions for the receiving chip, business data that needs to be transmitted to the receiving chip, and the like.
- the data packets to be transmitted corresponding to the chip configuration data may be called configuration data packets
- the data packets to be transmitted corresponding to control instructions may be called control data packets
- the data packets to be transmitted corresponding to business data may be called message data Bag.
- the chip configuration data it may be the power-on configuration data of the receiving chip, etc., and the configuration data of the chip type of the receiving chip.
- the configuration data of the chip type is used to configure the receiving chip as a working chip or a backup chip.
- control command it is used to control the receiving chip. For example, receiving a chip cooling control command, start command or stop operation command, etc.
- the service data it may be the service data to be migrated from the sending chip to the receiving chip during data migration.
- multiple chips can be used to realize joint processing of data, and some chips can be used to perform disaster recovery processing on other chips, or master-slave control between multiple chips, etc.
- the chip identification information is used to uniquely identify the receiving chip of the data packet to be transmitted among multiple chips.
- the port identifier of the target PCIE physical layer port of the receiving chip, or the chip identity identifier of the receiving chip is not limited.
- the target first PCIE physical layer port may be a port interconnected with the sending chip among the multiple first PCIE physical layer ports of the receiving chip.
- the target first PCIE physical layer port may be determined from the multiple first PCIE physical layer ports of the sending chip through the protocol layer of the sending chip.
- the multiple first PCIE physical layer ports are interconnected with the multiple chips in one-to-one correspondence. It should be noted that, for the interconnection relationship between the multiple first PCIE physical layer ports and the multiple chips, refer to the relevant description in the above part of the embodiment of the present disclosure in conjunction with FIG. 1 , and details are not repeated here.
- the target first PCIE physical layer port corresponding to the target PCIE physical layer port may be determined according to the port identification.
- the corresponding relationship between a plurality of first PCIE physical layer ports and the chip identification can be preset, so that based on the corresponding relationship, the PCIE port corresponding to the chip identification information can be determined.
- Physical layer port For example, continuing to take Fig. 1 as an example, the preset corresponding relationship in the protocol layer 120 may include: the first sub-relationship between the chip ID of the chip C2 and the PCIE physical layer port 131, the chip ID of the chip C3 and the PCIE physical layer The second sub-relationship of the port 132, the chip ID of the chip C4 and the third sub-relationship of the PCIE physical layer port 133.
- the data packet to be transmitted may be sent to the target first PCIE physical layer port of the sending chip through the protocol layer of the sending chip.
- the chip C1 may distribute the data packets to be transmitted to the PCIE physical layer port 133 after determining that the PCIE physical layer port 133 is the target first PCIE physical layer port.
- the protocol layer can also perform error monitoring on the physical link of the PCIE physical layer port, so as to modify the wrong physical link to a logically error-free data link.
- the data packet to be transmitted may be sent to the target PCIE physical layer port of the receiving chip through the target first PCIE physical layer port of the sending chip.
- the target PCIE physical layer port may be a port connected to the target first PCIE physical layer port of the sending chip among the plurality of first PCIE physical layer ports of the receiving chip.
- Fig. 1 continue to take Fig. 1 as an example, if the sending chip is chip C3, and the receiving chip is chip C2, then the data to be transmitted can be sent to the PCIE physical layer port 132 of chip C2 through the PCIE physical layer port 133 of chip C3 Bag.
- the sending chip may forward the data packet to be transmitted to the receiving chip through other chips.
- the first PCIE physical layer port failure of the target chip the target PCIE physical layer port failure of the receiving chip, the abnormality of the transmission line between the first PCIE physical layer port of the target and the target PCIE physical layer end, etc.
- the sending chip cannot successfully send the data packet to be transmitted to the receiving chip, the transmission of the data packet to be transmitted is realized by forwarding the data packet, which improves the stability of data transmission.
- a plurality of first PCIE physical layer ports can be interconnected with a plurality of chips in one-to-one correspondence, and when data transmission is performed, the PCIE physical layer port corresponding to the chip identification information in the data packet to be transmitted is determined, Then, the data can be transmitted to the receiving chip through the PCIE physical layer port. Because the PCIE physical layer ports interconnected with multiple chips in one-to-one correspondence can realize direct and high-bandwidth mutual transmission of information between multiple chips, improving the data transmission efficiency between multiple chips.
- the data can be directly sent to the target chip, which can greatly improve the data transmission efficiency and reduce the central processing unit (Central Processing Unit, CPU) resources of the chip.
- the utilization rate can realize high-speed interconnection of chips.
- the data transmission method before S330, the data transmission method further includes step A1 and step A2.
- Step A1 determine the data type of the data packet to be transmitted.
- step A1 the data type of the data packet to be transmitted can be determined through the protocol layer of the sending chip.
- step A2 the data to be transmitted is packaged according to the package format corresponding to the data type, and the packaged data package to be transmitted is obtained.
- step A1 packet processing may be performed through the protocol layer of the sending chip.
- S330 may specifically include distributing the packetized data packets to be transmitted to the target first PCIE physical layer port.
- the packetized data packets to be transmitted may be distributed to the target first PCIE physical layer port through the protocol layer of the sending chip.
- step A1 and step A2 may be implemented through the transport layer. And after the data packet to be transmitted after the packet is distributed to the target data link layer corresponding to the first PCIE physical layer port of the target through the transport layer, the target data link layer continues to transmit the packet to be transmitted down to the target first PCIE physical layer port.
- a PCIE physical layer port A PCIE physical layer port.
- Fig. 4 shows a schematic flowchart of another data transmission method provided by an embodiment of the present disclosure.
- the embodiments of the present disclosure are optimized on the basis of the foregoing embodiments, and the embodiments of the present disclosure may be combined with various optional solutions in the foregoing one or more embodiments.
- the method shown in FIG. 4 may be applied to a chip that needs to perform data transmission among multiple chips, that is, the sending chip, which is not specifically limited.
- the plurality of chips may be multiple control chips in one driving controller of the vehicle or chips in different driving controllers, which is not specifically limited.
- the data transmission may include the following steps: S410-S440.
- the target first PCIE physical layer port corresponding to the chip identification information may be determined through the transmission layer of the sending chip.
- the data to be transmitted may be distributed to the target first PCIE physical layer port through the transport layer and the target data link layer.
- the data packet to be transmitted may be distributed to the target data link layer corresponding to the target first PCIE physical layer port based on the chip identification information through the transport layer of the sending chip. And transmit the data packet to be transmitted to the target first PCIE physical layer port through the target data link layer of the sending chip.
- the sending chip is chip C1 and the receiving chip is chip C3
- the data packet to be transmitted can be distributed to the data link layer 1212 of chip C1 through the transport layer 122 of chip C1.
- the data link layer 1212 of the chip C1 may send it to the Physical layer 1322 of the PCIE physical layer port 132 of the chip C1.
- S440 Send the data packet to be transmitted to the receiving chip through the target first PCIE physical layer port.
- the receiving chip is a chip interconnected with the target first PCIE physical layer port.
- S440 is similar to S340, and reference may be made to related content of S340, which will not be repeated here.
- a plurality of first PCIE physical layer ports can be interconnected with a plurality of chips in one-to-one correspondence, and when data transmission is performed, the PCIE physical layer port corresponding to the chip identification information in the data packet to be transmitted is determined, Then, the data can be transmitted to the receiving chip through the PCIE physical layer port. Because the PCIE physical layer ports interconnected with multiple chips in one-to-one correspondence can realize direct and high-bandwidth mutual transmission of information between multiple chips, improving the data transmission efficiency between multiple chips.
- the data transmission method before S430, the data transmission method further includes step B1.
- Step B1 aligning the data bit width of the data packet to be transmitted with the data bit width of the target first PCIE physical layer port to obtain the aligned data packet to be transmitted.
- data bit width alignment may be performed on the data packet to be transmitted through the target data link layer of the sending chip.
- the data bit width of the aligned data packet to be transmitted is the same as the data bit width of the target first PCIE physical layer port.
- S430 may specifically include: transmitting the aligned data packets to be transmitted to the target first PCIE physical layer port.
- the aligned data packet to be transmitted may be transmitted to the target first PCIE physical layer port through the target data link layer of the sending chip.
- the aligned data packets to be transmitted can be processed by the PCIE physical layer port by means of data bit width alignment.
- the data transmission method further includes step C1 and step C2.
- Step C1 performing error monitoring on physical links of multiple first PCIE physical layer ports respectively.
- step C1 if the protocol layer includes a plurality of data link layers, and each of the data link layers corresponds to a described PCIE physical layer port, then multiple data link layers can be utilized for the respective corresponding PCIE physical layer ports Physical links are monitored for errors.
- Step C2 when an error is detected in the physical link of any PCIE physical layer port, modify the errored physical link to an error-free data link.
- step C2 when any data link layer monitors that the physical link of the corresponding PCIE physical layer port has an error, the physical link with error is modified to an error-free data link by any data link layer.
- error correction is performed through error monitoring, so that the links provided by each PCIE physical layer can appear as error-free links to the transport layer.
- Fig. 5 shows a schematic flowchart of another data transmission method provided by an embodiment of the present disclosure.
- the data transmission method shown in FIG. 5 may be applied to a target chip that receives data to be transmitted among multiple chips, and there is no specific limitation thereto.
- the plurality of chips may be multiple control chips in one driving controller of the vehicle or chips in different driving controllers, which is not specifically limited.
- the data transmission method may include the following steps: S510-S520.
- the second PCIE physical layer port of the target is a port interconnected with the sending chip in a plurality of second PCIE physical layer ports, and a plurality of second PCIE physical layer ports are interconnected with a plurality of chips in one-to-one correspondence, and the data packets to be transmitted include data to be transmitted and Chip identification information.
- the target chip may receive the data packet to be transmitted through its own target second PCIE physical layer port.
- Fig. 1 continue to take Fig. 1 as an example, if the sending chip is chip C2, and the receiving chip is chip C1, then receiving chip C1 can receive the PCIE physical layer port of sending chip C2 through its own PCIE physical layer port 131 The data packet to be transmitted sent by 131 .
- the data packet to be transmitted may be sent to the local user layer of the target chip under the condition that the identification information of the chip is determined to be the same as the identification information of the local chip through the protocol layer of the target chip.
- chip identification information For the chip identification information, reference may be made to the specific description of the chip identification information in the foregoing embodiments, which will not be repeated here.
- the local chip identification information can be the chip identity of the target chip, and if the local chip identification information is consistent with the chip identity, it can be determined that the target chip is the target chip.
- Receiver chip for transmitting data packets. Wherein, when receiving the chip, the user specifies the target receiver of the data to be transmitted through the user layer of the sending chip.
- the chip identification information is the port identification of the target PCIE physical layer port, it can be determined whether there is a port with the second PCIE physical layer port of the target in the port identification of a plurality of second PCIE physical layer ports of the target chip If there is a port identifier with the same identifier, it is determined that the chip identifier information is the same as the local chip identifier information, and accordingly it is determined that the target chip is the receiving chip of the data packet to be transmitted.
- the data packet to be transmitted may be sent to the local user layer of the target chip when the protocol layer determines that the chip identification information is the same as the local chip identification information. Furthermore, the data packet to be transmitted can be transmitted to the memory of the target chip.
- multiple second PCIE physical layer ports can be connected to multiple chips in one-to-one correspondence, and the sending chip can be directly obtained through the PCIE physical layer port directly interconnected with the sending chip during data transmission. transmitted data. Because the PCIE physical layer ports interconnected with multiple chips in one-to-one correspondence can realize direct and high-bandwidth mutual transmission of information between multiple chips, improving the data transmission efficiency between multiple chips.
- the data transmission method further includes steps D1 and D2.
- Step D1 send the data packet to be transmitted to the transport layer through the data link layer corresponding to the target second PCIE physical layer port.
- Step D2 judging whether the chip identification information is the same as the local chip identification information through the transport layer.
- step D2 may participate in the specific content of S520, which will not be repeated here.
- the information to be transmitted can be correctly transmitted to the receiving chip by judging whether the chip identification information is the same as the local chip identification information, thereby improving the accuracy of data transmission.
- the data transmission method before step S520, the data transmission method further includes step D3.
- Step D3 aligning the data bit width of the data packet to be transmitted with the data bit width of the transport layer to obtain the aligned data to be transmitted.
- step D3 the data bit width of the data packet to be transmitted can be aligned with the data bit width of the transport layer through the data link layer corresponding to the target second PCIE physical layer port, and the aligned data to be transmitted can be obtained.
- the data bit width of the aligned data to be transmitted may be the same as the data bit width of the transmission layer of the target chip.
- step S520 may specifically include: in a case where it is determined that the chip identification information is the same as the local chip identification information, sending the aligned data packets to be transmitted to the transport layer.
- the aligned data packets to be transmitted may be sent to the transport layer through the data link layer corresponding to the target second PCIE physical layer port. Then the transport layer transmits the aligned data packets to be transmitted to the local user layer of the target chip through the transport layer when judging that the chip identification information is the same as the local chip identification information.
- the aligned data packets to be transmitted can be processed by the transport layer by means of data bit width alignment.
- the data transmission method before S520, the data transmission method further includes step E1 and step E2.
- Step E1 determine the data type of the data packet to be transmitted.
- step E1 the data type of the data packet to be transmitted can be determined through the protocol layer of the target chip.
- Step E2 unpack the data to be transmitted according to the unpacking format corresponding to the data type, and obtain the unpacked data to be transmitted.
- step E1 unpacking may be performed through the protocol layer of the target chip.
- step E1 and step E2 reference may be made to the relevant descriptions of step A1 and step A2, which will not be repeated here.
- the data packets to be transmitted are sent to the user layer, including
- the data packet to be transmitted may be sent to the local user layer of the target chip through the protocol layer of the target chip.
- unpacking in a specific format can be performed on different types of data packets to be transmitted, so that the format redefinition of various types of data packets can be realized.
- Fig. 6 shows a schematic flowchart of another data transmission method provided by an embodiment of the present disclosure.
- the embodiments of the present disclosure are optimized on the basis of the foregoing embodiments, and the embodiments of the present disclosure may be combined with various optional solutions in the foregoing one or more embodiments.
- the data transmission method shown in FIG. 6 may be applied to a target chip that receives a data packet to be transmitted among multiple chips, and there is no specific limitation thereto.
- the plurality of chips may be multiple control chips in one driving controller of the vehicle or chips in different driving controllers, which is not specifically limited.
- the data transmission method may include the following steps: S610-S650.
- the second PCIE physical layer port of the target is a port interconnected with the sending chip in a plurality of second PCIE physical layer ports, and a plurality of second PCIE physical layer ports are interconnected with a plurality of chips in one-to-one correspondence, and the data packets to be transmitted include data to be transmitted and Chip identification information.
- S610 is similar to S510, please refer to the specific content of S510, and will not repeat them here.
- S620 is similar to S520, and the specific content of S520 can be referred to, and will not be repeated here.
- the identification information is different from the local chip identification information, determine a third PCIE physical layer port corresponding to the chip identification information among the plurality of second PCIE physical layer ports.
- the third PCIE physical layer port corresponding to the chip identification information may be determined among the plurality of second PCIE physical layer ports through the protocol layer of the target chip.
- the third PCIE physical layer port interconnected with other chips may be determined.
- the data packet to be transmitted may be sent to the third PCIE physical layer port through the protocol layer of the target chip.
- the sending chip is chip C3, the target chip is chip C1, and the receiving chip is chip C2, then after chip C1 receives the data packet to be transmitted through the PCIE physical layer port 132, if the receiving chip is found to be chip C2 , the transmission data packet can be distributed to the PCIE physical layer port 131 of the chip C1, so as to forward the data packet to be transmitted to the chip C2.
- S650 is similar to S340, please refer to related content of S340, and will not repeat them here.
- the data transmission method, device, equipment, and medium of the embodiments of the present disclosure can be interconnected with multiple chips in one-to-one correspondence through multiple second PCIE physical layer ports.
- the layer port can directly obtain the data transmitted by the sending chip. Because the PCIE physical layer ports interconnected with multiple chips one by one can realize direct and high-bandwidth mutual transmission of information between multiple chips, which improves the data transmission efficiency between multiple chips.
- Fig. 7 shows a schematic structural diagram of a data transmission device provided by an embodiment of the present disclosure.
- the data transmission device shown in FIG. 7 may be applied to a sending chip among multiple interconnected chips, which is not specifically limited.
- the data transmission device 700 may include a first data packet receiving module 710 , a first port determination module 720 , a data packet distribution module 730 and a first data packet sending module 740 .
- the first data packet receiving module 710 may be used to receive a data packet to be transmitted, the data packet to be transmitted includes data to be transmitted and chip identification information;
- the first port determination module 720 can be used to determine the target first PCIE physical layer port corresponding to the chip identification information among the multiple first PCIE physical layer ports, and the multiple first PCIE physical layer ports correspond to multiple chips one by one interconnected;
- the data packet distribution module 730 can be used for distributing the data packets to be transmitted to the target first PCIE physical layer port;
- the first data packet sending module 740 may be configured to send the data packet to be transmitted to the receiving chip through the target first PCIE physical layer port, and the receiving chip is a chip interconnected with the target first PCIE physical layer port.
- a plurality of first PCIE physical layer ports can be interconnected with a plurality of chips in one-to-one correspondence, and when data transmission is performed, the PCIE physical layer port corresponding to the chip identification information in the data packet to be transmitted is determined, Then, the data can be transmitted to the receiving chip through the PCIE physical layer port. Because the PCIE physical layer ports interconnected with multiple chips in one-to-one correspondence can realize direct and high-bandwidth mutual transmission of information between multiple chips, improving the data transmission efficiency between multiple chips.
- the first port determination module 720 may be specifically configured to: among a plurality of first PCIE physical layer ports, determine the target first PCIE physical layer port corresponding to the chip identification information;
- the data packet distribution module 730 may be specifically configured to distribute the data packet to be transmitted to the target first PCIE physical layer port based on the chip identification information.
- the data transmission device 700 may further include a data alignment module.
- the data alignment module can be used to align the data bit width of the data packet to be transmitted with the data bit width of the target first PCIE physical layer port, and obtain the aligned data packet to be transmitted;
- the above-mentioned data transmission unit can be specifically used for:
- the data transmission device 700 may further include a data type determination module and a packet module.
- the data type determination module can be used to determine the data type of the data packet to be transmitted
- the package module can be used to package the data to be transmitted according to the package format corresponding to the data type, and obtain the packaged data package to be transmitted;
- the data packet distribution module 730 may be specifically configured to: distribute the packetized data packets to be transmitted to the target first PCIE physical layer port.
- the data transmission device 700 may further include an error monitoring module and an error correction module.
- the error monitoring module can be used to respectively monitor the physical links of multiple first PCIE physical layer ports for error monitoring;
- the error correction module can be used to modify the physical link with error to a data link without error when monitoring any error in the physical link of the PCIE physical layer port.
- the data transmission device 700 shown in FIG. 7 can execute each step in the method embodiment shown in FIG. 3 to FIG. 4 , and realize each process and effects, which will not be described here.
- Fig. 8 shows a schematic structural diagram of another data transmission device provided by an embodiment of the present disclosure.
- the data transmission device shown in FIG. 8 may be applied to a target chip among multiple interconnected chips, which is not specifically limited.
- the data transmission device 800 may include a second data packet sending module 810 and a second data packet receiving module 820 .
- the second data packet sending module 810 is used to receive the data packet to be transmitted by the second PCIE physical layer port of the target, and the second PCIE physical layer port of the target is a port interconnected with the sending chip in a plurality of second PCIE physical layer ports, and multiple The second PCIE physical layer port is interconnected with multiple chips in one-to-one correspondence, and the data packet to be transmitted includes data to be transmitted and chip identification information;
- the second data packet receiving module 820 is configured to send the data packet to be transmitted to the local user layer when it is determined that the chip identification information is the same as the local chip identification information.
- multiple second PCIE physical layer ports can be connected to multiple chips in one-to-one correspondence, and the sending chip can be directly obtained through the PCIE physical layer port directly interconnected with the sending chip during data transmission. transmitted data. Because the PCIE physical layer ports interconnected with multiple chips in one-to-one correspondence can realize direct and high-bandwidth mutual transmission of information between multiple chips, improving the data transmission efficiency between multiple chips.
- the data transmission device 800 may further include a second port determination module, a data packet transmission module and a third data packet sending module.
- the second port determination module can be used to determine the third PCIE physical layer port corresponding to the chip identification information in a plurality of second PCIE physical layer ports when the identification information is different from the local chip identification information;
- the data packet transmission module can be used to send the data packet to be transmitted to the third PCIE physical layer port;
- the third data packet sending module can be used to send the data packet to be transmitted to the receiving chip through the third PCIE physical layer port, and the receiving chip is a chip interconnected with the third PCIE physical layer port.
- the data transmission device 800 may further include a data alignment module.
- the data alignment module can be used to align the data bit width of the data packet to be transmitted with the data bit width of the transport layer through the data link layer corresponding to the second PCIE physical layer port of the target, and obtain the aligned data to be transmitted;
- the second data packet receiving module 820 can be specifically configured to: send the aligned data packet to be transmitted to the transport layer when it is determined that the chip identification information is the same as the local chip identification information.
- the data transmission device 800 may further include a data type determination module and an unpacking module.
- the data type determination module can be used to determine the data type of the data packet to be transmitted
- the unpacking module can be used to unpack the data to be transmitted according to the unpacking format corresponding to the data type, and obtain the unpacked data to be transmitted;
- the second data packet receiving module 820 may be specifically configured to: distribute the unpacked data packets to be transmitted to the local user layer.
- the data transmission device 800 shown in FIG. 8 can execute each step in the method embodiment shown in FIG. 5 to FIG. 6 , and realize each process and effects, which will not be described here.
- Fig. 9 shows a schematic structural diagram of a data transmission device provided by an embodiment of the present disclosure.
- the data transmission device may include a controller 901 and a memory 902 storing computer program instructions.
- controller 901 may include a central processing unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present disclosure.
- CPU central processing unit
- ASIC Application Specific Integrated Circuit
- Memory 902 may include mass storage for information or instructions.
- memory 902 may include a hard disk drive (Hard Disk Drive, HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a Universal Serial Bus (Universal Serial Bus, USB) drive or two or more A combination of the above.
- Storage 902 may include removable or non-removable (or fixed) media, where appropriate.
- Memory 902 may be internal or external to the integrated gateway device, where appropriate.
- memory 902 is a non-volatile solid-state memory.
- the memory 902 includes a read-only memory (Read-Only Memory, ROM).
- the ROM can be a mask programmed ROM, a programmable ROM (Programmable ROM, PROM), an erasable PROM (Electrical Programmable ROM, EPROM), an electrically erasable PROM (Electrically Erasable Programmable ROM, EEPROM) ), electrically rewritable ROM (Electrically Alterable ROM, EAROM) or flash memory, or a combination of two or more of these.
- the controller 901 executes the steps of the data transmission method provided by the embodiments of the present disclosure by reading and executing the computer program instructions stored in the memory 902 .
- the data transmission device may further include a transceiver 903 and a bus 904 .
- the controller 901 , the memory 902 and the transceiver 903 are connected through a bus 904 and complete mutual communication.
- Bus 904 includes hardware, software, or both.
- a bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Super Transmission (Hyper Transport, HT) interconnection, Industrial Standard Architecture (Industrial Standard Architecture, ISA) bus, Infinity Bandwidth interconnection, Low Pin Count (Low Pin Count, LPC) bus, memory bus, Micro Channel Architecture (Micro Channel Architecture) , MCA) bus, Peripheral Component Interconnect (PCI) bus, PCI-Express (PCI-X) bus, Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) bus, Video Electronics Standards Association local (Video Electronics Standards Association Local Bus, VLB) bus or other suitable bus or a combination of two or more of these.
- Bus 904 may comprise one or more buses, where appropriate.
- the embodiment of the present disclosure also provides a computer-readable storage medium, the storage medium can store a computer program, and when the computer program is executed by the processor, the processor implements the data transmission method provided by the embodiment of the present disclosure.
- the above-mentioned storage medium may include, for example, a memory 902 of computer program instructions, and the above-mentioned instructions can be executed by the processor 901 of the data transmission device to complete the data transmission method provided by the embodiment of the present disclosure.
- the storage medium can be a non-transitory computer-readable storage medium, for example, the non-transitory computer-readable storage medium can be ROM, random access memory (Random Access Memory, RAM), optical disc read-only memory (Compact Disc ROM, CD-ROM), magnetic tape, floppy disk and optical data storage devices, etc.
- the embodiment of the present disclosure also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the data transmission method provided by the embodiment of the present disclosure is implemented.
- a computer program is also proposed, wherein the computer program includes computer program code, and when the computer program code is run on the computer, the computer is made to execute the data transmission method provided by the embodiments of the present disclosure.
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Abstract
提出了一种数据传输方法、装置、设备及介质,其中,数据传输方法包括:接收待传输数据包,待传输数据包包括待传输数据和芯片标识信息;在多个第一PCIE物理层端口中,确定芯片标识信息对应的目标第一PCIE物理层端口,多个第一PCIE物理层端口与多个芯片一一对应互联;将待传输数据包分发至目标第一PCIE物理层端口;通过目标第一PCIE物理层端口向接收芯片发送待传输数据包,接收芯片为与目标第一PCIE物理层端口互联的芯片。
Description
相关申请的交叉引用
本申请基于申请号为202111637732.8、申请日为2021年12月29日的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本申请作为参考。
本公开涉及信息技术领域,具体涉及一种数据传输方法、装置、设备及介质。
随着信息技术的领域发展,现阶段往往需要利用多个芯片协同进行数据处理,比如可以应用于车载环境中解决大数据交互的问题。
然而,因现阶段仅可以实现两个芯片之间的高速互传,当涉及到三个以上(即芯片数量大于或等于3)的多芯片的协同数据处理时,无法直接在多个芯片间进行数据互传,影响多芯片间的数据传输效率。
发明内容
本公开提供了一种数据传输方法、装置、设备、介质、计算机程序产品和计算机程序。
第一方面,本公开实施例提供了一种数据传输方法,包括:
接收待传输数据包,待传输数据包包括待传输数据和芯片标识信息;
在多个第一PCIE物理层端口中,确定芯片标识信息对应的目标第一PCIE物理层端口,多个第一PCIE物理层端口与多个芯片一一对应互联;
将待传输数据包分发至目标第一PCIE物理层端口;
通过目标第一PCIE物理层端口向接收芯片发送待传输数据包,接收芯片为与目标第一PCIE物理层端口互联的芯片。
第二方面,本公开实施例提供了一种数据传输方法,包括:
通过目标第二PCIE物理层端口接收待传输数据包,目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,多个第二PCIE物理层端口与多个芯片一一对应互联,待传输数据包包括待传输数据和芯片标识信息;
在确定芯片标识信息与本地芯片标识信息相同的情况下,将待传输数据包发送至本地的用户层。
第三方面,本公开实施例提供了数据传输装置,包括:
数据包接收模块,用于接收待传输数据包,待传输数据包包括待传输数据和芯片标识信息;
第一端口确定模块,用于在多个第一PCIE物理层端口中,确定芯片标识信息对应的 目标第一PCIE物理层端口,多个第一PCIE物理层端口与多个芯片一一对应互联;
数据包分发模块,用将待传输数据包分发至目标第一PCIE物理层端口;
数据包发送模块,用于通过目标第一PCIE物理层端口向接收芯片发送待传输数据包,接收芯片为与目标第一PCIE物理层端口互联的芯片。
第四方面,本公开实施例提供了一种数据传输装置,包括:
数据包发送模块,用于通过目标第二PCIE物理层端口接收待传输数据包,目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,多个第二PCIE物理层端口与多个芯片一一对应互联,待传输数据包包括待传输数据和芯片标识信息;
数据包接收模块,用于在确定芯片标识信息与本地芯片标识信息相同的情况下,将待传输数据包发送至本地的用户层。
第五方面,本公开实施例提供了一种数据传输设备,包括:
处理器;
存储器,用于存储可执行指令;
其中,处理器用于从存储器中读取可执行指令,并执行可执行指令以实现第一方面或第二方面的数据传输方法。
第六方面,本公开实施例提供了一种计算机可读存储介质,该存储介质存储有计算机程序,当计算机程序被处理器执行时,使得处理器实现第一方面或第二方面的数据传输方法。
第七方面,本公开实施例提供了一种计算机程序产品,包括计算机程序,所述计算机程序在被处理器执行时实现第一方面或第二方面的数据传输方法。
第八方面,本公开实施例提供了一种计算机程序,所述计算机程序包括计算机程序代码,当所述计算机程序代码在计算机上运行时,使得计算机执行第一方面或第二方面的数据传输方法。
本公开实施例提供的技术方案与相关技术相比具有如下优点:
本公开实施例的数据传输方法、装置、设备、介质、计算机程序产品和计算机程序,能够通过多个第一PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,确定与待传输数据包中的芯片标识信息对应的目标第一PCIE物理层端口,进而通过该目标第一PCIE物理层端口即可将数据传输至接收芯片。由于与多个芯片一一对应互联的第一PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
结合附图并参考以下具体实施方式,本公开各实施例的上述和其他特征、优点及方面将变得更加明显。贯穿附图中,相同或相似的附图标记表示相同或相似的元素。应当理解附图是示意性的,原件和元素不一定按照比例绘制。
图1示出了本公开实施例提供的一种数据传输架构的示意图;
图2示出了本公开实施例提供的另一种数据传输架构的示意图;
图3示出了本公开实施例提供的一种数据传输方法的流程示意图;
图4示出了本公开实施例提供的另一种数据传输方法的流程示意图;
图5示出了本公开实施例提供的又一种数据传输方法的流程示意图;
图6示出了本公开实施例提供的再一种数据传输方法的流程示意图;
图7示出了本公开实施例提供的一种数据传输装置的结构示意图;
图8示出了本公开实施例提供的另一种数据传输装置的结构示意图;
图9为本公开实施例提供的一种数据传输设备的结构示意图。
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例,然而应当理解的是,本公开可以通过各种形式来实现,而且不应该被解释为限于这里阐述的实施例,相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是,本公开的附图及实施例仅用于示例性作用,并非用于限制本公开的保护范围。
应当理解,本公开的方法实施方式中记载的各个步骤可以按照不同的顺序执行,和/或并行执行。此外,方法实施方式可以包括附加的步骤和/或省略执行示出的步骤。本公开的范围在此方面不受限制。
本文使用的术语“包括”及其变形是开放性包括,即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”;术语“另一实施例”表示“至少一个另外的实施例”;术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。
需要注意,本公开中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分,并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意,本公开中提及的“一个”、“多个”的修饰是示意性而非限制性的,本领域技术人员应当理解,除非在上下文另有明确指出,否则应该理解为“一个或多个”。
本公开实施方式中的多个装置之间所交互的消息或者信息的名称仅用于说明性的目的,而并不是用于对这些消息或信息的范围进行限制。
为了解决上述的问题,本公开实施例提供了一种数据传输方法、装置、设备和介质,可以利用多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率,例如在多芯片大数据交互场景下的数据高速传输。以及,可以基于以太网的交换机思想以及PCIE协议的高速数据传输思想,实现了多芯片的高速串行器/解串器(Serializer/Deserializer,SerDer)技术。
下面,首先对本公开实施例提供的数据传输方法进行说明。
为了便于整体上理解本公开实施例提供的数据传输方案,本公开实施例在开始介绍数 据传输方法、装置、设备和介质之前,先结合附图对数据传输架构展开具体说明。
图1示出了本公开实施例提供的一种数据传输架构的示意图。如图1所示,在多芯片数据交互场景下,每个芯片的数据传输架构可以包括用户层(User Layer)110、协议层120以及多个PCIE物理层端口。示例性地,以4芯片C1-C4间数据交互为例,每一芯片可以包括3个PCIE物理层端口。3个PCIE物理层端口可以与剩余3个芯片一一对应互联。比如,对于芯片C1,其PCIE物理层端口131可以与芯片C2的PCIE物理层端口131互联,其PCIE物理层端口132可以与芯片C2的PCIE物理层端口131互联,其PCIE物理层端口133可以与芯片C3的PCIE物理层端口131互联。相应地,任意两个芯片可以通过二者间互联的PCIE物理层端口进行数据的双向交互。比如,芯片C1和芯片C2间可以通过各自的PCIE物理层端口131进行信息互传。需要说明的是,互联的芯片的个数不限于4个,还可以是3个或者大于4个,可以根据实际场景和具体需求设置互联芯片的个数,对此不作具体限定。
例如,需要由芯片C1向芯片C4传输数据时,芯片C1的用户层110可以基于用户输入的待传输数据以及芯片C4的芯片标识信息生成待传输数据包。然后芯片C1的用户层110将待传输数据包发送给芯片C1的协议层120。芯片C1的协议层120通过待传输数据包中芯片C4的芯片标识信息,在芯片C1的多个PCIE物理层端口中确定与芯片C4互联的PCIE物理层端口,即芯片C1的PCIE物理层端口133。然后通过芯片C1的PCIE物理层端口133将待传输数据包发送至芯片C4的PCIE物理层端口131,从而通过与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
又例如,在芯片C1通过自身的PCIE物理层端口133向芯片C4的PCIE物理层端口131发送待传输数据包之后,芯片C4的PCIE物理层端口131将所接收的待传输数据包上传至协议层120,芯片C4的协议层120判断待传输数据包中的芯片标识信息与芯片C4的芯片标识信息是否相同,如果相同,则芯片C4的协议层12继续将待传输数据包发送至芯片C4的用户层,从而通过与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
在一些实施例中,继续上一示例,如果芯片C4的协议层120确定待传输数据包中的芯片标识信息与芯片C4的芯片标识信息不同,比如待传输数据包中的芯片标识信息为芯片C3的芯片标识信息,则可以芯片C4的协议层120可以将待传输数据包分发至芯片C4的PCIE物理层端口133(即与芯片C3互联的物理层端口),从而可以通过芯片C4的PCIE物理层端口133将待传输数据包发送至芯片C3的PCIE物理层端口132,从而可以实现数据的高速转发。
需要说明的是,本公开实施例中的PCIE物理层端口131至133可以是封装有PCIE物理层的端口,从而可以实现高速SerDer的数据传输。
需要说明的是,对于上述用户层,用户可以在该层定义待传输数据,以及定义待传输 数据的接收芯片的芯片标识信息。
在一些实施例中,PCIE物理层端口可以包括两个物理层。比如,图2示出了本公开实施例提供的另一种数据传输架构的示意图。如图2所示,每一PCIE物理层端口包括第一物理层(phy层)以及第二物理层(Physical层)。比如,PCIE物理层端口131可以包括phy层1311以及Physical层1312,PCIE物理层端口132可以包括phy层1321以及Physical层1322,PCIE物理层端口133可以包括phy层1331以及Physical层1332。
需要说明的是,phy层以及Physical层主要可以实现物理编码子层(Physical coding sublayer,PCS)子层、物理媒介附加(Physical Medium Attachment,PMA)子层以及物理介质相关(Physical Medium Dependent,PMD)子层的功能在数字信号与模拟信号之间进行编码和传输。
需要说明的是,PMD子层可以是负责串行信号传输的电气块。PMA子层可以负责串化/解串化,PCS子层可以负责数据流的编码/解码。
在一些实施例中,协议层120可以包括数据链接层(Data link layer)以及传输层(Transaction layer)。其中,数据链接层可以与一个或者多个PCIE物理层端口进行数据交互。比如,可以是与多个PCIE物理层端口一一对应的多个数据链接层。又或者,可以是与多个PCIE物理层端口进行数据传输的一个数据链接层,对此不作限定。
在一个示例中,继续参见图2,协议层120包括3个数据链接层1211至1213以及传输层122。其中,每一数据链接层对应一个PCIE物理层端口。比如,数据链接层1211对应于PCIE物理层端口131的phy层1311以及Physical层1312。
例如,数据链接层1211可以接收PCIE物理层端口131发送的待传输数据包,以及对该待传输数据包进行数据对齐后,将对齐后的待传输数据包发送至传输层122,从而可以加强物理层端口传输的原始比特流的功能。同理地,其他数据链接层可以对与其对应的物理层端口进行数据对齐,对此不再赘述。
又例如,数据链接层1211可以接收传输层122发送的待传输数据包,以及对该待传输数据包进行数据对齐后,将对齐后的待传输数据包发送至与芯片标识信息对应的PCIE物理层端口,从而可以加强物理层端口传输的原始比特流的功能。同理地,其他数据链接层可以对传输层进行数据对齐,对此不再赘述。
又例如,数据链接层1212可以对PCIE物理层端口132进行差错监控,具体地,将PCIE物理层端口提供的可能差错的物理链接修改为逻辑上无差错的数据链接,从而可以提高数据传输的稳定性。同理地,其他数据链接层可以对与其对应的PCIE物理层端口进行差错监控,对此不再赘述。
需要说明的是,上述数据链接层可以用于与其他芯片建立数据链接,以及在PCIE物理层端口和传输层之间进行数据传输。
需要说明的是,上述传输层主要处理传输的事务。比如,对特定数据包进行组包或者拆包等以使其上层或者下层能够对数据包进行进一步处理,以及在多个PCIE物理层端口 与用户层之间进行数据的交织和分发等。
图3示出了本公开实施例提供的一种数据传输方法的流程示意图。
在本公开一些实施例中,图3所示的数据传输方法可以应用于多个芯片中需要进行数据传输的芯片,即发送芯片,对此不作具体限定。在一个示例中,多个芯片可以是车辆的一个驾驶控制器中的多个控制芯片或者不同驾驶控制器中的芯片,对此不作具体限定。
如图3所示,该数据传输方法可以包括如下步骤:S310-S340。
S310,接收待传输数据包。其中,待传输数据包包括待传输数据和芯片标识信息。
在本公开实施例中,可以通过发送芯片自身的用户层接收待传输数据包。其中,发送芯片可以为发送待传输数据包的芯片,
在一些实施例中,待传输数据可以是用户自定义的需要传输到接收芯片的数据。
在一些实施例中,从数据类型上,待传输数据可以包括接收芯片的芯片配置数据,针对接收芯片的控制指令,需要向接收芯片传输的业务数据等。相应地,芯片配置数据对应的待传输数据包可以称之为配置数据包,控制指令对应的待传输数据包可以称之为控制数据包,业务数据对应的待传输数据包可以称之为消息数据包。
对于芯片配置数据,其可以是接收芯片的开机配置数据等,以及接收芯片的芯片类型的配置数据。其中,芯片类型的配置数据用于配置接收芯片为工作芯片或者备份芯片等。
对于控制指令,其用于对接收芯片进行控制。比如,接收芯片的降温控制指令、启动指令或者停止运行指令等。
对于业务数据,其可以是发送芯片在向接收芯片进行数据迁移的过程中待迁移的业务数据。
需要说明的是,通过上述不同类型的待传输数据,可以利用多个芯片实现数据的共同处理,以及利用部分芯片对其他芯片进行容灾处理,或者多个芯片之间的主从控制等。
在一些实施例中,芯片标识信息用于在多个芯片中唯一表征待传输数据包的接收芯片。比如,接收芯片的目标PCIE物理层端口的端口标识,或者是接收芯片的芯片身份标识,对此不作限定。其中,目标第一PCIE物理层端口可以是接收芯片的多个第一PCIE物理层端口中、与发送芯片所互联的端口。
S320,在多个第一PCIE物理层端口中,确定芯片标识信息对应的目标第一PCIE物理层端口。在本公开实施例中,可以通过发送芯片的协议层在发送芯片的多个第一PCIE物理层端口中确定目标第一PCIE物理层端口。
其中,多个第一PCIE物理层端口与多个芯片一一对应互联。需要说明的是,多个第一PCIE物理层端口与多个芯片的互联关系可以参见本公开实施例上述部分结合图1的相关说明,在此不再赘述。
在一些实施例中,若芯片标识信息为接收芯片的目标PCIE物理层端口的端口标识,则可以根据端口标识确定与目标PCIE物理层端口对应的目标第一PCIE物理层端口。
在一些实施例中,若芯片标识信息为芯片身份标识,可以预先设置多个第一PCIE物 理层端口与芯片身份标识的对应关系,从而基于该对应关系,即可确定与芯片标识信息对应的PCIE物理层端口。比如,继续以图1为例,在协议层120中预先设置的对应关系可以包括:芯片C2的芯片身份标识与PCIE物理层端口131的第一子关系、芯片C3的芯片身份标识与PCIE物理层端口132的第二子关系、芯片C4的芯片身份标识与PCIE物理层端口133的第三子关系。
S330,将待传输数据包分发至目标第一PCIE物理层端口。
在本公开实施例中,可以通过发送芯片的协议层将待传输数据包发送至发送芯片的目标第一PCIE物理层端口。
在一些实施例中,继续以图1为例,芯片C1在确定PCIE物理层端口133为目标第一PCIE物理层端口之后,可以将待传输数据包分发至PCIE物理层端口133。
在一些实施例中,协议层还可以对PCIE物理层端口的物理链接进行差错监控,以将错误的物理链接修改为逻辑上无错误的数据链接。
S340,通过目标第一PCIE物理层端口向接收芯片发送待传输数据包,接收芯片为与目标第一PCIE物理层端口互联的芯片。
在本公开实施例中,可以通过发送芯片的目标第一PCIE物理层端口向接收芯片的目标PCIE物理层端口发送待传输数据包。目标PCIE物理层端口可以是接收芯片的多个第一PCIE物理层端口中与发送芯片的目标第一PCIE物理层端口相连接的端口。
在一些实施例中,继续以图1为例,若发送芯片为芯片C3,接收芯片为芯片C2,则可以通过芯片C3的PCIE物理层端口133向芯片C2的PCIE物理层端口132发送待传输数据包。
在一些实施例中,若发送芯片无法成功向接收芯片发送待传输数据包,则发送芯片可以通过其他芯片向接收芯片转发待传输数据包。
通过本实施例,可以在发送芯片的目标第一PCIE物理层端口故障、接收芯片的目标PCIE物理层端口故障、目标第一PCIE物理层端口与目标PCIE物理层端之间的传输线路异常等原因导致发送芯片无法成功向接收芯片发送待传输数据包时通过数据包转发的方式实现待传输数据包的传输,提高了数据传输的稳定性。
又或者,当待传输数据包发送至错误的PCIE物理层端口时,比如传输到除接收芯片之外的其他芯片的PCIE物理层端口时,能够通过转发的方式,正确传输至接收芯片,提高了数据传输的正确率。
在本公开实施例中,能够通过多个第一PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,确定与待传输数据包中的芯片标识信息对应的PCIE物理层端口,进而通过该PCIE物理层端口即可将数据传输至接收芯片。由于与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
另外,通过与多个芯片一一对应互联的PCIE物理层端口,能够将数据直接发送到目 标芯片中,可以极大的提高数据传输效率,降低芯片的中央处理器(Central Processing Unit,CPU)资源的使用率,可以实现芯片的高速互联。
此外,通过本公开实施例,即使多个芯片中某个芯片出现问题,也不会影响到其他芯片之间的数据互传,提高了数据传输的稳定性。
在一些实施例中,在S330之前,数据传输方法还包括步骤A1和步骤A2。
步骤A1,确定待传输数据包的数据类型。
在步骤A1中,可以通过发送芯片的协议层来确定待传输数据包的数据类型。
在一些实施例中,数据类型可以参见S310中对于数据类型的相关说明。
步骤A2,按照数据类型对应的封包格式,对待传输数据进行封包,得到封包后的待传输数据包。
在步骤A1中,可以通过发送芯片的协议层来进行封包处理。
相应地,S330可以具体包括将封包后的待传输数据包分发至目标第一PCIE物理层端口。具体地,可以通过发送芯片的协议层将封包后的待传输数据包分发至目标第一PCIE物理层端口。
在一些实施例中,若协议层包括传输层以及与多个第一PCIE物理层端口一一对应的多个数据链接层时,可以通过传输层实现步骤A1和步骤A2。以及通过传输层将封包后的待传输数据包分发给与目标第一PCIE物理层端口对应的目标数据链接层之后,目标数据链接层将封包后的待传输数据包分继续向下传输至目标第一PCIE物理层端口。
通过本实施例,可以对不同类型的待传输数据包进行特定格式的封包,从而可以实现对各类数据包的格式重定义。
图4示出了本公开实施例提供的另一种数据传输方法的流程示意图。本公开实施例在上述实施例的基础上进行优化,本公开实施例可以与上述一个或者多个实施例中各个可选方案结合。
在本公开一些实施例中,图4所示的方法可以应用于多个芯片中需要进行数据传输的芯片,即发送芯片,对此不作具体限定。在一个示例中,多个芯片可以是车辆的一个驾驶控制器中的多个控制芯片或者不同驾驶控制器中的芯片,对此不作具体限定。
如图4所示,该数据传输可以包括如下步骤:S410-S440。
S410,接收待传输数据包,待传输数据包包括待传输数据和芯片标识信息。
其中,S410可以参见S310的具体内容,在此不再赘述。
S420,在多个第一PCIE物理层端口中,确定芯片标识信息对应的目标第一PCIE物理层端口,多个第一PCIE物理层端口与多个芯片一一对应互联。
在本公开实施例中,可以通过发送芯片的传输层确定与芯片标识信息对应的目标第一PCIE物理层端口。
其中,S420可以参见S320的具体内容,在此不再赘述。
S430,基于芯片标识信息将待传输数据包分发至目标第一PCIE物理层端口。
在本公开实施例中,可以通过传输层和目标数据链路层将待传输数据分发至目标第一PCIE物理层端口。具体地,可以通过发送芯片的传输层基于芯片标识信息将待传输数据包分发至目标第一PCIE物理层端口对应的目标数据链接层。以及通过发送芯片的目标数据链接层将将待传输数据包传输至目标第一PCIE物理层端口。
在一些实施例中,以图2为例,若发送芯片为芯片C1,接收芯片为芯片C3,则可以通过芯片C1的传输层122将待传输数据包分发至芯片C1的数据链接层1212。
芯片C1的数据链接层1212接收到待传输数据包之后,可以将其发送至芯片C1的PCIE物理层端口132的Physical层1322。
S440,通过目标第一PCIE物理层端口向接收芯片发送待传输数据包。其中,接收芯片为与目标第一PCIE物理层端口互联的芯片。
需要说明的是,S440与S340类似,可以参见S340的相关内容,在此不再赘述。
在本公开实施例中,能够通过多个第一PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,确定与待传输数据包中的芯片标识信息对应的PCIE物理层端口,进而通过该PCIE物理层端口即可将数据传输至接收芯片。由于与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
在一些实施例中,S430之前,数据传输方法还包括步骤B1。
步骤B1,将待传输数据包的数据位宽与目标第一PCIE物理层端口的数据位宽对齐,得到对齐后的待传输数据包。
在本公开实施例中,可以通过发送芯片的目标数据链接层对待传输数据包进行数据位宽对齐。其中,对齐后的待传输数据包的数据位宽与目标第一PCIE物理层端口的数据位宽相同。
相应地,S430可以具体包括:将对齐后的待传输数据包传输至目标第一PCIE物理层端口。具体地,可以通过发送芯片的目标数据链接层将对齐后的待传输数据包传输至目标第一PCIE物理层端口。
通过本实施例,可以在传输层与PCIE物理层的数据位宽不同时,通过数据位宽对齐的方式,使对齐后的待传输数据包能够被PCIE物理层端口进行数据处理。
在一些实施例中,数据传输方法还包括步骤C1和步骤C2。
步骤C1,分别对多个第一PCIE物理层端口的物理链接进行差错监控。
在步骤C1中,若协议层包括多个数据链路层,每个所述数据链路层对应一个所述PCIE物理层端口,则可以利用多个数据链接层对各自对应的PCIE物理层端口的物理链接进行差错监控。
步骤C2,在监控到任意PCIE物理层端口的物理链接有差错时,将有差错的物理链接修改为无差错的数据链接。
在步骤C2中,可以在任意数据链接层监控到对应的PCIE物理层端口的物理链接有 差错时,通过任意数据链接层将有差错的物理链接修改为无差错的数据链接。
通过本实施例,通过差错监控进行误差纠正,可以使各PCIE物理层提供的链路对传输层表现为无差错的链路。
图5示出了本公开实施例提供的又一种数据传输方法的流程示意图。
在本公开一些实施例中,图5所示的数据传输方法可以应用于多个芯片中接收到待传输数据的目标芯片,对此不作具体限定。在一个示例中,多个芯片可以是车辆的一个驾驶控制器中的多个控制芯片或者不同驾驶控制器中的芯片,对此不作具体限定。
如图5所示,该数据传输方法可以包括如下步骤:S510-S520。
S510,通过目标第二PCIE物理层端口接收待传输数据包。目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,多个第二PCIE物理层端口与多个芯片一一对应互联,待传输数据包包括待传输数据和芯片标识信息。
在本公开实施例,目标芯片可以通过自身的目标第二PCIE物理层端口接收待传输数据包。
需要说明的是,S510可以参见本公开实施例上述部分的相关说明,在此不再赘述。
在一些实施例中,继续以图1为例,若发送芯片为芯片C2,接收芯片为芯片C1,则接收芯片C1通过自身的PCIE物理层端口131即可接收到发送芯片C2的PCIE物理层端口131发送的待传输数据包。
S520,在确定芯片标识信息与本地芯片标识信息相同的情况下,将待传输数据包发送至本地的用户层。
在本公开实施例中,可以通过目标芯片自身的协议层在确定芯片标识信息与本地芯片标识信息相同的情况下,将待传输数据包发送至目标芯片本地的用户层。
其中,芯片标识信息可以参见上述实施例对芯片标识信息的具体描述,在此不再赘述。
在一些实施例中,若芯片标识信息为接收芯片的芯片身份标识,本地芯片标识信息可以是目标芯片的芯片身份标识,若本地芯片标识信息与芯片身份标识一致,则可以确定目标芯片即是待传输数据包的接收芯片。其中,接收芯片时用户通过发送芯片的用户层指定的待传输数据的目标接收方。
在一些实施例中,若芯片标识信息为目标PCIE物理层端口的端口标识,则可以确定目标芯片的多个第二PCIE物理层端口的端口标识中是否存在与目标第二PCIE物理层端口的端口标识相同的端口标识,若存在,即确定芯片标识信息与本地芯片标识信息相同,相应地确定目标芯片即是待传输数据包的接收芯片。
在一些实施例中,可以在通过协议层在确定芯片标识信息与本地芯片标识信息相同的情况下,可以将待传输数据包发送至目标芯片本地的用户层。进而可以将待传输数据包传输至目标芯片的内存中。
在本公开实施例中,能够通过多个第二PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,能够通过与发送芯片直接互联的PCIE物理层端口即可直接获取发送 芯片传输的数据。由于与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
在一些实施例中,若协议层包括传输层以及多个数据链接层,每个数据链接层对应一个PCIE物理层端口,则S520之前,数据传输方法还包括步骤D1和步骤D2。
步骤D1,通过目标第二PCIE物理层端口对应的数据链接层,将待传输数据包发送至传输层。
步骤D2,通过传输层判断芯片标识信息与本地芯片标识信息是否相同。
在一些实施例中,步骤D2可以参加S520的具体内容,在此不再赘述。
通过本实施例,能够通过判断芯片标识信息与本地芯片标识信息是否相同的方式,正确的将待传输信息传输至接收芯片,提高了数据传输的正确率。
在一些实施例中,在步骤S520之前,数据传输方法还包括步骤D3。
步骤D3,将待传输数据包的数据位宽与传输层的数据位宽对齐,得到对齐后的待传输数据。
在步骤D3中,可以通过目标第二PCIE物理层端口对应的数据链接层,将待传输数据包的数据位宽与传输层的数据位宽对齐,得到对齐后的待传输数据。
需要说明的是,对齐后的待传输数据的数据位宽可以与目标芯片的传输层的数据位宽相同。
相应地,步骤S520可以具体包括:在确定芯片标识信息与本地芯片标识信息相同的情况下,将对齐后的待传输数据包发送至传输层。
具体地,可以通过目标第二PCIE物理层端口对应的数据链接层,将对齐后的待传输数据包发送至传输层。然后传输层在判断芯片标识信息与本地芯片标识信息相同的情况下,通过传输层将对齐后的待传输数据包传输至目标芯片本地的用户层。
通过本实施例,可以在传输层与PCIE物理层的数据位宽不同时,通过数据位宽对齐的方式,使对齐后的待传输数据包能够被传输层进行数据处理。
在一些实施例中,在S520之前,数据传输方法还包括步骤E1和步骤E2。
步骤E1,确定待传输数据包的数据类型。
在步骤E1中,可以通过目标芯片的协议层确定待传输数据包的数据类型。
步骤E2,按照数据类型对应的拆包格式,对待传输数据进行拆包,得到拆包后的待传输数据。
在步骤E1中,可以通过目标芯片的协议层进行拆包处理。
需要说明的是,步骤E1和步骤E2可以参见步骤A1和步骤A2的相关说明,对此不再赘述。
其中,将待传输数据包发送至用户层,包括
将拆包后的待传输数据包分发至本地的用户层。具体地,可以通过目标芯片的协议层将待传输数据包发送至目标芯片本地的用户层。
通过本实施例,可以对不同类型的待传输数据包进行特定格式的拆包,从而可以实现对各类数据包的格式重定义。
图6示出了本公开实施例提供的再一种数据传输方法的流程示意图。本公开实施例在上述实施例的基础上进行优化,本公开实施例可以与上述一个或者多个实施例中各个可选方案结合。
在本公开一些实施例中,图6所示的数据传输方法可以应用于多个芯片中接收到待传输数据包的目标芯片,对此不作具体限定。在一个示例中,多个芯片可以是车辆的一个驾驶控制器中的多个控制芯片或者不同驾驶控制器中的芯片,对此不作具体限定。
如图6所示,该数据传输方法可以包括如下步骤:S610-S650。
S610,通过目标第二PCIE物理层端口接收待传输数据包。目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,多个第二PCIE物理层端口与多个芯片一一对应互联,待传输数据包包括待传输数据和芯片标识信息。
其中,S610与S510类似,可以参见S510的具体内容,在此不再赘述。
S620,在确定芯片标识信息与本地芯片标识信息相同的情况下,将待传输数据包发送至本地的用户层。
其中,S620与S520类似,可以参见S520的具体内容,在此不再赘述。
S630,在标识信息与本地芯片标识信息不相同的情况下,在多个第二PCIE物理层端口中确定与芯片标识信息对应的第三PCIE物理层端口。
在本公开实施例中,可以通过目标芯片的协议层在多个第二PCIE物理层端口中确定与芯片标识信息对应的第三PCIE物理层端口。
在一些实施例中,若确定芯片标识信息对应于除目标芯片之外的其他芯片时,可以确定与其他芯片互联的第三PCIE物理层端口。
S640,将待传输数据包发送至第三PCIE物理层端口。
在本公开实施例中,可以通过目标芯片的协议层将待传输数据包发送至第三PCIE物理层端口。
继续以图1为例,若发送芯片为芯片C3,目标芯片为芯片C1,接收芯片为芯片C2,则芯片C1通过PCIE物理层端口132接收到待传输数据包之后,若发现接收芯片为芯片C2,则可以将传输数据包分发至芯片C1的PCIE物理层端口131,以将待传输数据包转发至芯片C2。
S650,通过第三PCIE物理层端口将待传输数据包发送至接收芯片,接收芯片为与第三PCIE物理层端口互联的芯片。
S650与S340类似,可参见S340的相关内容,在此不再赘述。
本公开实施例的数据传输方法、装置、设备及介质,能够通过多个第二PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,能够通过与发送芯片直接互联的PCIE物理层端口即可直接获取发送芯片传输的数据。由于与多个芯片一一对应互联的PCIE物 理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
图7示出了本公开实施例提供的一种数据传输装置的结构示意图。
在本公开一些实施例中,图7所示的数据传输装置可以应用于多个互联芯片中的发送芯片,对此不作具体限定。
如图7所示,该数据传输装置700可以包括第一数据包接收模块710、第一端口确定模块720、数据包分发模块730和第一数据包发送模块740。
该第一数据包接收模块710可以用于接收待传输数据包,待传输数据包包括待传输数据和芯片标识信息;
该第一端口确定模块720可以用于在多个第一PCIE物理层端口中,确定芯片标识信息对应的目标第一PCIE物理层端口,多个第一PCIE物理层端口与多个芯片一一对应互联;
该数据包分发模块730可以用于将待传输数据包分发至目标第一PCIE物理层端口;
该第一数据包发送模块740可以用于通过目标第一PCIE物理层端口向接收芯片发送待传输数据包,接收芯片为与目标第一PCIE物理层端口互联的芯片。
在本公开实施例中,能够通过多个第一PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,确定与待传输数据包中的芯片标识信息对应的PCIE物理层端口,进而通过该PCIE物理层端口即可将数据传输至接收芯片。由于与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
在一些实施例中,第一端口确定模块720可以具体用于:在多个第一PCIE物理层端口中,确定芯片标识信息对应的目标第一PCIE物理层端口;
数据包分发模块730可以具体用于基于芯片标识信息将待传输数据包分发至目标第一PCIE物理层端口。
在一些实施例中,数据传输装置700还可以包括数据对齐模块。
该数据对齐模块可以用于将待传输数据包的数据位宽与目标第一PCIE物理层端口的数据位宽对齐,得到对齐后的待传输数据包;
其中,上述数据传输单元可以具体用于:
将对齐后的待传输数据包传输至目标第一PCIE物理层端口。
在一些实施例中,数据传输装置700还可以包括数据类型确定模块和封包模块。
该数据类型确定模块可以用于确定待传输数据包的数据类型;
该封包模块可以用于按照数据类型对应的封包格式,对待传输数据进行封包,得到封包后的待传输数据包;
其中,数据包分发模块730可以具体用于:将封包后的待传输数据包分发至目标第一PCIE物理层端口。
在一些实施例中,数据传输装置700还可以包括差错监控模块以及差错修正模块。
该差错监控模块可以用于分别对多个第一PCIE物理层端口的物理链接进行差错监控;
该差错修正模块可以用于在监控到任意PCIE物理层端口的物理链接有差错时,将有差错的物理链接修改为无差错的数据链接。
需要说明的是,图7所示的数据传输装置700可以执行图3至图4所示的方法实施例中的各个步骤,并且实现图3至图4所示的方法实施例中的各个过程和效果,在此不做赘述。
图8示出了本公开实施例提供的另一种数据传输装置的结构示意图。
在本公开一些实施例中,图8所示的数据传输装置可以应用于多个互联芯片中的目标芯片,对此不作具体限定。
如图8所示,该数据传输装置800可以包括第二数据包发送模块810和第二数据包接收模块820。
第二数据包发送模块810,用于通过目标第二PCIE物理层端口接收待传输数据包,目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,多个第二PCIE物理层端口与多个芯片一一对应互联,待传输数据包包括待传输数据和芯片标识信息;
第二数据包接收模块820,用于在确定芯片标识信息与本地芯片标识信息相同的情况下,将待传输数据包发送至本地的用户层。
在本公开实施例中,能够通过多个第二PCIE物理层端口与多个芯片一一对应互联,在进行数据传输时,能够通过与发送芯片直接互联的PCIE物理层端口即可直接获取发送芯片传输的数据。由于与多个芯片一一对应互联的PCIE物理层端口能够实现多芯片间信息直接的、高带宽的互传,提高了多芯片间的数据传输效率。
在一些实施例中,该数据传输装置800还可以包括第二端口确定模块、数据包传输模块和第三数据包发送模块。
该第二端口确定模块可以用于在标识信息与本地芯片标识信息不相同的情况下,在多个第二PCIE物理层端口中确定与芯片标识信息对应的第三PCIE物理层端口;
该数据包传输模块可以用于将待传输数据包发送至第三PCIE物理层端口;
该第三数据包发送模块可以用于通过第三PCIE物理层端口将待传输数据包发送至接收芯片,接收芯片为与第三PCIE物理层端口互联的芯片。
在一些实施例中,该数据传输装置800还可以包括数据对齐模块。
该数据对齐模块可以用于通过目标第二PCIE物理层端口对应的数据链接层,将待传输数据包的数据位宽与传输层的数据位宽对齐,得到对齐后的待传输数据;
其中,第二数据包接收模块820可以具体用于:在确定芯片标识信息与本地芯片标识信息相同的情况下,将对齐后的待传输数据包发送至传输层。
在一些实施例中,该数据传输装置800还可以包括数据类型确定模块和拆包模块。
该数据类型确定模块可以用于确定待传输数据包的数据类型;
该拆包模块可以用于按照数据类型对应的拆包格式,对待传输数据进行拆包,得到拆包后的待传输数据;
其中,该第二数据包接收模块820可以具体用于:将拆包后的待传输数据包分发至本地的用户层。
需要说明的是,图8所示的数据传输装置800可以执行图5至图6所示的方法实施例中的各个步骤,并且实现图5至图6所示的方法实施例中的各个过程和效果,在此不做赘述。
图9示出了本公开实施例提供的一种数据传输设备的结构示意图。
如图9所示,该数据传输设备可以包括控制器901以及存储有计算机程序指令的存储器902。
具体地,上述控制器901可以包括中央处理器(CPU),或者特定集成电路(Application Specific Integrated Circuit,ASIC),或者可以被配置成实施本公开实施例的一个或多个集成电路。
存储器902可以包括用于信息或指令的大容量存储器。举例来说而非限制,存储器902可以包括硬盘驱动器(Hard Disk Drive,HDD)、软盘驱动器、闪存、光盘、磁光盘、磁带或通用串行总线(Universal Serial Bus,USB)驱动器或者两个及其以上这些的组合。在合适的情况下,存储器902可包括可移除或不可移除(或固定)的介质。在合适的情况下,存储器902可在综合网关设备的内部或外部。在特定实施例中,存储器902是非易失性固态存储器。在特定实施例中,存储器902包括只读存储器(Read-Only Memory,ROM)。在合适的情况下,该ROM可以是掩模编程的ROM、可编程ROM(Programmable ROM,PROM)、可擦除PROM(Electrical Programmable ROM,EPROM)、电可擦除PROM(Electrically Erasable Programmable ROM,EEPROM)、电可改写ROM(Electrically Alterable ROM,EAROM)或闪存,或者两个或及其以上这些的组合。
控制器901通过读取并执行存储器902中存储的计算机程序指令,以执行本公开实施例所提供的数据传输方法的步骤。
在一个示例中,该数据传输设备还可包括收发器903和总线904。其中,如图9所示,控制器901、存储器902和收发器903通过总线904连接并完成相互间的通信。
总线904包括硬件、软件或两者。举例来说而非限制,总线可包括加速图形端口(Accelerated Graphics Port,AGP)或其他图形总线、增强工业标准架构(Extended Industry Standard Architecture,EISA)总线、前端总线(Front Side BUS,FSB)、超传输(Hyper Transport,HT)互连、工业标准架构(Industrial Standard Architecture,ISA)总线、无限带宽互连、低引脚数(Low Pin Count,LPC)总线、存储器总线、微信道架构(Micro Channel Architecture,MCA)总线、***控件互连(Peripheral Component Interconnect,PCI)总线、PCI-Express(PCI-X)总线、串行高级技术附件(Serial Advanced Technology Attachment,SATA)总线、视频电子标准协会局部(Video Electronics Standards Association Local Bus, VLB)总线或其他合适的总线或者两个或更多个以上这些的组合。在合适的情况下,总线904可包括一个或多个总线。尽管本公开实施例描述和示出了特定的总线,但本公开考虑任何合适的总线或互连。
本公开实施例还提供了一种计算机可读存储介质,该存储介质可以存储有计算机程序,当计算机程序被处理器执行时,使得处理器实现本公开实施例所提供的数据传输方法。
上述的存储介质可以例如包括计算机程序指令的存储器902,上述指令可由数据传输设备的处理器901执行以完成本公开实施例所提供的数据传输方法。在一些实施例中,存储介质可以是非临时性计算机可读存储介质,例如,非临时性计算机可读存储介质可以是ROM、随机存取存储器(Random Access Memory,RAM)、光盘只读存储器(Compact Disc ROM,CD-ROM)、磁带、软盘和光数据存储设备等。
本公开实施例还提供了一种计算机程序产品,包括计算机程序,该计算机程序在被处理器执行时实现本公开实施例所提供的数据传输方法。
在一个实施例中,还提出一种计算机程序,其中该计算机程序包括计算机程序代码,当该计算机程序代码在计算机上运行时,使得计算机执行本公开实施例所提供的数据传输方法。
需要说明的是,前述对数据传输方法实施例的解释说明也适用于上述实施例中的设备、非瞬时计算机可读存储介质、计算机程序产品和计算机程序,此处不再赘述。
需要说明的是,在本文中,诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。
以上所述仅是本公开的具体实施方式,使本领域技术人员能够理解或实现本公开。对这些实施例的多种修改对本领域的技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本公开的精神或范围的情况下,在其它实施例中实现。因此,本公开将不会被限制于本文所述的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims (15)
- 一种数据传输方法,包括:接收待传输数据包,所述待传输数据包包括待传输数据和芯片标识信息;在多个第一高速串行计算机扩展总线标准PCIE物理层端口中,确定所述芯片标识信息对应的目标第一PCIE物理层端口,所述多个第一PCIE物理层端口与多个芯片一一对应互联;将所述待传输数据包分发至所述目标第一PCIE物理层端口;通过所述目标第一PCIE物理层端口向接收芯片发送所述待传输数据包,所述接收芯片为与所述目标第一PCIE物理层端口互联的芯片。
- 根据权利要求1所述的方法,其中,所述在多个高速串行计算机扩展总线标准PCIE物理层端口中,确定所述芯片标识信息对应的目标第一PCIE物理层端口,包括:在所述多个第一PCIE物理层端口中,确定所述芯片标识信息对应的目标第一PCIE物理层端口;所述将所述待传输数据包分发至所述目标第一PCIE物理层端口,包括:基于所述芯片标识信息将所述待传输数据包分发至所述目标第一PCIE物理层端口。
- 根据权利要求2所述的方法,其中,所述基于所述芯片标识信息将所述待传输数据包分发至所述目标第一PCIE物理层端口之前,所述方法还包括:将所述待传输数据包的数据位宽与所述目标第一PCIE物理层端口的数据位宽对齐,得到对齐后的待传输数据包;其中,所述基于所述芯片标识信息将所述待传输数据包分发至所述目标第一PCIE物理层端口,包括:将所述对齐后的待传输数据包传输至所述目标第一PCIE物理层端口。
- 根据权利要求1至3中任一项所述的方法,其中,所述将所述待传输数据包分发至所述目标第一PCIE物理层端口之前,所述方法还包括:确定所述待传输数据包的数据类型;按照所述数据类型对应的封包格式,对所述待传输数据进行封包,得到封包后的待传输数据包;其中,所述将所述待传输数据包分发至所述目标第一PCIE物理层端口,包括:将所述封包后的待传输数据包分发至所述目标第一PCIE物理层端口。
- 根据权利要求1至4中任一项所述的方法,其中,所述方法还包括:分别对多个第一PCIE物理层端口的物理链接进行差错监控;在监控到任意PCIE物理层端口的物理链接有差错时,将所述有差错的物理链接修改为无差错的数据链接。
- 一种数据传输方法,包括:通过目标第二PCIE物理层端口接收待传输数据包,所述目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,所述多个第二PCIE物理层端口与多个芯片一一对应互联,所述待传输数据包包括待传输数据和芯片标识信息;在确定所述芯片标识信息与本地芯片标识信息相同的情况下,将所述待传输数据包发送至本地的用户层。
- 根据权利要求6所述的方法,其中,所述通过目标第二PCIE物理层端口接收待传输数据包之后,所述方法还包括:在所述标识信息与所述本地芯片标识信息不相同的情况下,在所述多个第二PCIE物理层端口中确定与所述芯片标识信息对应的第三PCIE物理层端口;将所述待传输数据包发送至所述第三PCIE物理层端口;通过所述第三PCIE物理层端口将所述待传输数据包发送至接收芯片,所述接收芯片为与所述第三PCIE物理层端口互联的芯片。
- 根据权利要求7所述的方法,其中,所述将所述待传输数据包发送至本地的用户层之前,所述方法还包括:将所述待传输数据包的数据位宽与传输层的数据位宽对齐,得到对齐后的待传输数据;其中,所述在确定所述芯片标识信息与本地芯片标识信息相同的情况下,将所述待传输数据包发送至本地的用户层,包括:在确定所述芯片标识信息与本地芯片标识信息相同的情况下,将所述对齐后的待传输数据包发送至所述传输层。
- 根据权利要求6至8中任一项所述的方法,其中,所述将所述待传输数据包发送至本地的用户层之前,所述方法还包括:确定所述待传输数据包的数据类型;按照所述数据类型对应的拆包格式,对所述待传输数据进行拆包,得到拆包后的待传输数据;其中,所述将所述待传输数据包发送至用户层,包括:将所述拆包后的待传输数据包分发至所述本地的用户层。
- 一种数据传输装置,包括:第一数据包接收模块,用于接收待传输数据包,所述待传输数据包包括待传输数据和芯片标识信息;第一端口确定模块,用于在多个第一PCIE物理层端口中,确定所述芯片标识信息对应的目标第一PCIE物理层端口,所述多个第一PCIE物理层端口与多个芯片一一对应互联;数据包分发模块,用于将所述待传输数据包分发至所述目标第一PCIE物理层端口;第一数据包发送模块,用于通过所述目标第一PCIE物理层端口向接收芯片发送所述 待传输数据包,所述接收芯片为与所述目标第一PCIE物理层端口互联的芯片。
- 一种数据传输装置,包括:第二数据包发送模块,用于通过目标第二PCIE物理层端口接收待传输数据包,所述目标第二PCIE物理层端口是多个第二PCIE物理层端口中与发送芯片互联的端口,所述多个第二PCIE物理层端口与多个芯片一一对应互联,所述待传输数据包包括待传输数据和芯片标识信息;第二数据包接收模块,用于在确定所述芯片标识信息与本地芯片标识信息相同的情况下,将所述待传输数据包发送至本地的用户层。
- 一种数据传输设备,包括:处理器;存储器,用于存储可执行指令;其中,所述处理器用于从所述存储器中读取所述可执行指令,并执行所述可执行指令以实现上述权利要求1至5或6至9中任一项所述的数据传输方法。
- 一种计算机可读存储介质,其特征在于,所述存储介质存储有计算机程序,当所述计算机程序被处理器执行时,使得处理器实现用上述权利要求1至5或6至9中任一项所述的数据传输方法。
- 一种计算机程序产品,包括计算机程序,其中所述计算机程序在被处理器执行时实现如权利要求1至5或6至9中任一项所述的数据传输方法。
- 一种计算机程序,所述计算机程序包括计算机程序代码,其中当所述计算机程序代码在计算机上运行时,使得计算机执行如权利要求1至5或6至9中任一项所述的数据传输方法。
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