WO2023123032A1 - 显示基板及其驱动方法、显示面板 - Google Patents

显示基板及其驱动方法、显示面板 Download PDF

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Publication number
WO2023123032A1
WO2023123032A1 PCT/CN2021/142413 CN2021142413W WO2023123032A1 WO 2023123032 A1 WO2023123032 A1 WO 2023123032A1 CN 2021142413 W CN2021142413 W CN 2021142413W WO 2023123032 A1 WO2023123032 A1 WO 2023123032A1
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Prior art keywords
gate
transistor
double
pull
coupled
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PCT/CN2021/142413
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English (en)
French (fr)
Inventor
王杰
古宏刚
陈旭
王海宏
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京东方科技集团股份有限公司
南京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 南京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/142413 priority Critical patent/WO2023123032A1/zh
Priority to CN202180004304.3A priority patent/CN116802725A/zh
Publication of WO2023123032A1 publication Critical patent/WO2023123032A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a driving method thereof, and a display panel.
  • GOA Gate Driver on array
  • the purpose of the present disclosure is to provide a display substrate, a driving method thereof, and a display panel.
  • a first aspect of the present disclosure provides a display substrate, including a gate drive circuit, the gate drive circuit includes a plurality of shift register units, and the shift register units include a pull-up node, a pull-down node, and a pull-up controller Circuit; the pull-up control sub-circuit includes:
  • the first double-gate transistor, the first gate of the first double-gate transistor and the second gate of the first double-gate transistor are respectively coupled to the pull-down node, and the first gate of the first double-gate transistor is The pole is coupled to the pull-up node, and the second pole of the first double-gate transistor is coupled to the first level signal input terminal.
  • the shift register unit further includes an output control subcircuit
  • the output control subcircuit includes a second double-gate transistor, the first gate of the second double-gate transistor and the second double-gate transistor
  • the second gates of the second double-gate transistors are respectively coupled to the pull-up nodes, the first poles of the second double-gate transistors are coupled to the corresponding clock signal input terminals, and the second poles of the second double-gate transistors are connected to the The driving signal output terminal of the shift register unit is coupled.
  • the shift register unit also includes:
  • An output reset subcircuit the output reset subcircuit is respectively coupled to the pull-down node, the drive signal output end of the gate drive circuit, and the first level signal input end, and the output reset subcircuit is used for Under the control of the pull-down node, control the electrical connection between the drive signal output terminal and the first level signal input terminal to be turned on or off;
  • a storage subcircuit the first terminal of the storage subcircuit is coupled to the pull-up node, and the second terminal of the storage capacitor is coupled to the drive signal output terminal.
  • the shift register unit further includes: a pull-down control subcircuit, the pull-down control subcircuit is connected to the pull-up node, the pull-down node, the first level signal input terminal and the second voltage level respectively.
  • the level signal input terminal is coupled, and the pull-down control subcircuit is used to control the electrical connection between the pull-down node and the first level signal input terminal to be turned on or off under the control of the pull-up node. , and is further used for controlling on or off the electrical connection between the pull-down node and the second level signal input terminal under the control of the second level signal input terminal.
  • the shift register unit also includes:
  • the input sub-circuit is respectively coupled to the input control terminal, the input signal terminal and the pull-up node, and the input sub-circuit is used to control the conduction or disconnection of the input control terminal under the control of the input control terminal.
  • the output reset subcircuit includes a third transistor, the gate of the third transistor is coupled to the pull-down node, and the first pole of the third transistor is coupled to the drive signal output end, The second pole of the third transistor is coupled to the first level signal input terminal;
  • the storage sub-circuit includes a storage capacitor, a first end of the storage capacitor is coupled to the pull-up node, and a second end of the storage capacitor is coupled to the driving signal output end.
  • the pull-down control subcircuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor and the first pole of the fourth transistor are both coupled to the second level signal input terminal , the second pole of the fourth transistor is coupled to the pull-down node; the gate of the fifth transistor is coupled to the pull-up node, and the first pole of the fifth transistor is coupled to the pull-down node , the second pole of the fifth transistor is coupled to the first level signal input terminal.
  • the input sub-circuit includes a sixth transistor, the gate of the sixth transistor is coupled to the input control terminal, and the first pole of the sixth transistor is coupled to the input signal terminal, so The second pole of the sixth transistor is coupled to the pull-up node.
  • the display substrate includes a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels
  • the sub-pixels include pixel circuits and pixel electrodes
  • the pixel circuits include pixel double-gate transistors
  • the pixel double-gate transistors The first gate of the pixel double-gate transistor and the second gate of the pixel double-gate transistor are respectively coupled to the corresponding gate line
  • the first electrode of the pixel double-gate transistor is coupled to the corresponding data line
  • the pixel double-gate transistor The second pole of is coupled to the pixel electrode.
  • the first double-gate transistor, the second double-gate transistor and the pixel double-gate transistor adopt the following structure:
  • a first gate, a first insulating layer, an active layer, a source-drain metal layer, a second insulating layer and a second gate are sequentially stacked in a direction away from the base of the display substrate; the active layer is on the base
  • the orthographic projection on the substrate overlaps at least partially the orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate respectively;
  • the source-drain metal layer forms the first gate of the transistor A pole and a second pole, the first pole and the second pole overlap with the active layer respectively.
  • the second aspect of the present disclosure provides a driving method of the display substrate, which is applied to the above-mentioned display substrate, and the driving method includes:
  • the first gate and the second gate of the first double-gate transistor are controlled by the pull-down node to control the first double-gate transistor to be cut off;
  • the first gate and the second gate of the first double-gate transistor are controlled by the pull-down node to control the first double-gate transistor to be turned on.
  • the shift register unit further includes an output control subcircuit
  • the output control subcircuit includes a second double-gate transistor, a first gate of the second double-gate transistor and a first gate of the second double-gate transistor.
  • the two gates are respectively coupled to the pull-up nodes, the first pole of the second double-gate transistor is coupled to the corresponding clock signal input terminal, and the second pole of the second double-gate transistor is connected to the drive of the gate drive circuit.
  • the signal output terminal is coupled; the driving method also includes:
  • the first gate and the second gate of the second double-gate transistor are controlled by the pull-up node to control the conduction of the second double-gate transistor;
  • the first gate and the second gate of the second double-gate transistor are controlled by the pull-up node to control the second double-gate transistor to be turned off.
  • the display substrate includes a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels
  • the sub-pixels include pixel circuits and pixel electrodes
  • the pixel circuits include pixel double-gate transistors
  • the pixel double-gate transistors The first gate of the pixel double-gate transistor and the second gate of the pixel double-gate transistor are respectively coupled to the corresponding gate line, the first electrode of the pixel double-gate transistor is coupled to the corresponding data line, and the pixel double-gate transistor
  • the second pole of the pixel electrode is coupled to the pixel electrode;
  • the driving method further includes:
  • the first gate and the second gate of the pixel double-gate transistor are controlled by the corresponding gate line to control the pixel double-gate transistor to be turned on;
  • the first gate and the second gate of the pixel double-gate transistor are controlled by the corresponding gate line to control the pixel double-gate transistor to be turned off.
  • a third aspect of the present disclosure provides a display panel, including the above-mentioned display substrate.
  • the display panel further includes an opposite substrate and a liquid crystal layer, the opposite substrate is disposed opposite to the display substrate, and the liquid crystal layer is located between the opposite substrate and the display substrate.
  • FIG. 1 is a schematic cross-sectional view of a double-gate transistor provided by an embodiment of the present disclosure
  • FIG. 2 is a circuit symbol diagram of a double-gate transistor provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a curve showing the influence of the top gate voltage on the current provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of leakage current distribution in various regions provided by an embodiment of the present disclosure.
  • FIG. 5 is an equivalent schematic diagram of a pull-down control subcircuit provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a first circuit structure of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 7 is a working sequence diagram of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a second circuit structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of parasitic capacitance generated by a second double-gate transistor provided by an embodiment of the present disclosure.
  • FIG. 10 is a working timing diagram of a second double-gate transistor provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of gate driving signals and data signal waveforms provided by an embodiment of the present disclosure.
  • the present disclosure provides a display substrate including a display area and a non-display area surrounding the display area.
  • the display area includes a plurality of sub-pixels, and each sub-pixel includes a thin film transistor, and the thin film transistor can drive the sub-pixel to realize a display function.
  • the non-display area includes the GOA circuit, and the GOA circuit is generally composed of multi-stage shift register units, and each stage of the shift register unit is composed of several thin film transistors.
  • thin film transistors can have a larger current when they are in the on state, and they can be turned off very well when they are in the off state.
  • the leakage current is as small as possible.
  • the threshold voltage (Vth) of the thin film transistor needs to be relatively large to meet the purpose of preventing false opening and reducing leakage current; and in the open state, the Vth of the thin film transistor needs to be relatively small to meet the large current in the on state.
  • Vth the threshold voltage of the thin film transistor
  • the Vth of the traditional thin film transistor cannot be changed after the process is completed.
  • the inability to change mentioned here does not consider the Vth drift caused by the long-term working stress of the thin film transistor, and this drift is only the change of the initial Vth of the thin film transistor, and the Vth cannot be dynamically adjusted according to the switching state requirements of the thin film transistor.
  • an embodiment of the present disclosure provides a display substrate, including a gate drive circuit, the gate drive circuit includes a plurality of shift register units, and the shift register units include a pull-up node PU , the pull-down node PD and the pull-up control subcircuit 10; the pull-up control subcircuit 10 includes:
  • the first double-gate transistor M1, the first gate of the first double-gate transistor M1 and the second gate of the first double-gate transistor M1 are respectively coupled to the pull-down node PD, and the first double-gate
  • the first pole of the transistor M1 is coupled to the pull-up node PU
  • the second pole of the first double-gate transistor M1 is coupled to the first level signal input terminal (connected to the negative power supply signal VSS or VGL).
  • the display substrate includes a display area and a non-display area surrounding the display area, and the gate driving circuit is located in the non-display area.
  • the display area includes multiple sub-pixels, and the multiple sub-pixels are distributed in an array.
  • the sub-pixels include pixel circuits capable of controlling the display of the sub-pixels.
  • the plurality of sub-pixels are divided into multiple rows of sub-pixels, and the driving signal output terminal Gout of the shift register unit is coupled to a row of pixel circuits included in a corresponding row of sub-pixels, and is used to output gate pole drive signal.
  • the potential of the pull-up node PU is opposite to the potential of the pull-down node PD.
  • the pull-up control sub-circuit 10 includes a first double-gate transistor M1, and the specific structure of the first double-gate transistor M1 is varied.
  • the first double-gate transistor M1 includes a first gate and a second gate, one of the first gate and the second gate is located under the active layer, As a bottom gate BG, the other of the first gate and the second gate is located above the active layer as a top gate TG.
  • the orthographic projection of the active layer on the base of the display substrate at least partially overlaps the orthographic projection of the first grid on the base, and the orthographic projection of the active layer on the base overlaps with Orthographic projections of the second grid on the substrate are at least partially overlapped.
  • the thin film transistor When the thin film transistor is in the off state, the top gate inputs a low voltage, and the Vth of the thin film transistor will become larger, which can better turn off the thin film transistor, avoid false opening, and reduce leakage current.
  • the thin film transistor When the thin film transistor is in an on state, a high voltage is input to the top gate, and the Vth of the thin film transistor becomes smaller, so that the on state current of the thin film transistor becomes larger. Therefore, through this dual-gate technology, the Vth of the thin film transistor can be dynamically adjusted according to the switching state of the thin film transistor, so as to achieve the purpose of better closing, reducing leakage current and increasing on-state current.
  • Each layer is formed on the substrate in order and in a certain graphic shape: bottom gate (English: bottom gate, referred to as: BG), gate insulating layer, active layer, source layer, drain layer, passivation insulating layer, pixel Electrode and top gate (English: top gate, abbreviation: TG).
  • bottom gate English: bottom gate, referred to as: BG
  • gate insulating layer active layer
  • source layer drain layer
  • passivation insulating layer pixel Electrode
  • top gate Terms: top gate, abbreviation: TG.
  • the top gate is added, and the added top gate is above the bottom gate, so when the double gate transistor is applied to the sub-pixel, the aperture ratio of the pixel will not be reduced.
  • FIG. 2 it is a circuit symbol diagram of a double-gate thin film transistor. There are four ports, namely top gate TG, bottom gate BG, source S and drain D.
  • FIG. 3 it is the transfer output curve current (Ids) of the double-gate thin film transistor under the influence of different top gate voltages.
  • Traditional thin film transistors have three port inputs, which will form two voltages that need to be focused on, namely: VBG_S (bottom gate-source voltage) and VDS (source-drain voltage), these two voltages will directly affect the thin film transistor. current.
  • VBG_S bottom gate-source voltage
  • VDS source-drain voltage
  • the Vth of the double-gate thin film transistor can be controlled by controlling the top gate voltage of the double-gate thin film transistor.
  • the abscissa V DG_S in Figure 3 represents the Vgs corresponding to the bottom gate, that is, the difference between the voltage Vg of the bottom gate and the source voltage Vs, and the value of Vgs corresponding to the bottom gate is between -15V and +15V.
  • FIG. 4 it is a schematic diagram of a thin film transistor transfer curve and leakage current analysis.
  • the transfer curve diagram can be divided into three parts, corresponding to three regions: the leakage current region, the subthreshold region and the upper threshold region.
  • the leakage current is generally considered to occur in the leakage current region and the sub-threshold region.
  • the leakage current in the leakage current region is small; the subthreshold region can be divided into two parts: the on-state current part where Vgs is greater than Vth and the leakage current in the subthreshold region where Vgs is lower than Vth.
  • Vth is equal to the voltage of Vgs when the current Ids (after normalization) of the thin film transistor is 10nA. It can be found that the leakage current in the leakage current region is small, while the leakage current in the subthreshold region is relatively large. If we control the Vth positive drift of the double-gate thin film transistor through double-gate technology, let the Vgs applied to the thin-film transistor fall in the leakage current region and stay away from the sub-threshold region. In addition to effectively avoiding the false opening of the thin-film transistor, it can also effectively reduce leakage current. Similarly, if the negative shift of Vth of the double-gate thin film transistor is controlled, the on-state current of the thin film crystal can be effectively increased.
  • V DG_S in Figure 4 represents the Vgs corresponding to the bottom gate, that is, the difference between the voltage Vg of the bottom gate and the source voltage Vs, and the value of Vgs corresponding to the bottom gate is between -5V and +15V.
  • the 10nA value method is to use the Vgs of the device at 10nA as the threshold voltage Vth after the on-state current Ids of the device is normalized.
  • the duty cycle is 50%, or 8 clock signal lines, 12 clock signal lines , 16 clock signal lines, etc., an even number of clock signal lines greater than or equal to 2 may be used, which is not limited here.
  • Each level of shift register unit is sequentially connected to the corresponding clock signal, for example, the Gn-2 level shift register unit is connected to CK1, the Gn-1 level shift register unit is connected to CK2, the Gn level shift register unit is connected to CK3, and the Gn level shift register unit is connected to CK3.
  • the +1-level shift register unit is connected to CK4, and so on, and the four-level shift register unit is connected to the clock signal in a cycle.
  • PUn-2 to PUn+4 in FIG. 7 represent the pull-up nodes in the shift register units of each stage.
  • Gn-2 to Gn+4 in FIG. 7 represent the drive signal output terminals in the shift register units of each stage.
  • the GOA circuit needs to be suspended to collect touch signals.
  • the clock signal requires the suspension of the pulse signal, which is set as a constant voltage low voltage signal (such as: VGL signal), the clock signal can return to the normal pulse signal after the touch period ends. It is inevitable that the pull-up nodes PU of some shift register units store a high voltage during the touch period, and the GOA circuit can continue to work normally after the touch period is over.
  • the pull-up node PU in the Gn-1 level shift register unit, Gn level shift register unit, Gn+1 level shift register unit and Gn+2 level shift register unit is stored in the touch stage
  • the high voltage is called the pit level; most of the shift register units pull up the node PU to a low voltage during the touch period.
  • FIG. 5 is a specific structural diagram of the pull-down control sub-circuit 50 in the above-mentioned shift register unit, and an equivalent circuit diagram of the pull-down control sub-circuit 50 .
  • the pull-down control subcircuit 50 includes a fourth transistor M4 and a fifth transistor M5.
  • the fourth transistor M4 and the fifth transistor M5 form an inverter, the input signal is the voltage of the pull-up node PU, and the output signal is the voltage of the pull-down node PD, and the pull-down node PD is connected to the gate of the first double-gate transistor M1 maintaining the pull-up node PU. pole.
  • the VDD (positive power supply signal) voltage is a constant high voltage of 20V
  • the VSS (negative power supply signal) voltage is a constant low voltage of -10V.
  • the pull-up node PU is a high voltage, so that the fourth transistor M4 and the fifth transistor M5 are in the open state at the same time, VDD and VSS form a path, and the fourth transistor M4 and the fifth transistor M5 can be equivalent to two resistors with different resistances (such as R1 and R2 ), and the voltage of the pull-down node PD depends on the ratio of the two equivalent resistors of the fourth transistor M4 and the fifth transistor M5 . According to simple physical and electrical knowledge, the voltage of the pull-down node PD will be greater than the VSS voltage and less than the VDD voltage.
  • the equivalent resistance can be adjusted by adjusting the channel width-to-length ratio of the fourth transistor M4 and the fifth transistor M5, the pull-down node PD It must be greater than the VSS voltage, which is assumed to be -8V here.
  • the gate voltage is -8V of the pull-down node PD
  • the source voltage is -10V of the VSS voltage
  • the drain is the high voltage of the pull-up node PU
  • the first double-gate transistor M1 If the Vth of the first double-gate transistor M1 is less than 2V, the first double-gate transistor M1 is in the open state, and the high voltage of the pull-up node PU will be drained soon, and the GOA circuit cannot continue to work normally after the stop pit is completed; if at this time The Vgs voltage applied to the first double-gate transistor M1 falls in the sub-threshold region to leak current. Generally speaking, the pit stop time is relatively long, for example, about 200 microseconds, which is enough to drain the voltage of the pull-up node PU.
  • the voltage difference between the stop-pit level and the non-stop pit-level pull-up node PU may cause a problem of stop pits. Only when the Vgs voltage applied to the first double-gate transistor M1 falls in the leakage current region, can the pit stop time be passed safely and the normal operation of the subsequent GOA circuit can be guaranteed.
  • the Vth of the first double-gate transistor M1 should be as large as possible during the stop pit time, so that the voltage of Vgs applied to the first double-gate transistor M1 It should be smaller than the Vth of the first double-gate transistor M1, preferably falling in the leakage current region of the transfer curve of the first double-gate transistor M1. It is worth noting that the Vth of the traditional thin film transistors cannot be adjusted after the display panel process is completed, and the Vth of all the thin film transistors on the display panel can only be made smaller or larger during the manufacturing process of the display panel. If Vth is deliberately made too positive or too large in the process, problems such as insufficient potential maintenance of the pull-up node PU and the driving signal output terminal Gout and insufficient pixel charging rate will occur on the display panel.
  • the Vth of the first double-gate transistor M1 can be dynamically adjusted positively or negatively according to the requirement.
  • the pull-up node PU is at a high voltage
  • the pull-down node PD is at a low voltage
  • the top gate of the first double-gate transistor M1 is connected to the pull-down node PD, so the first double-gate transistor
  • the Vth of M1 becomes larger, which can greatly increase the voltage range of the leakage current region of the transfer curve of the first double-gate transistor M1.
  • the Vth of the first double-gate transistor M1 is originally 3V, the Vgs voltage range of the leakage current entering the subthreshold region is 0V to 3V, and the Vgs voltage range of the leakage current region is less than 0V. If the Vgs of the first double-gate transistor M1 is 2V at this time, the traditional thin film transistor device enters the leakage current in the sub-threshold region, and the leakage problem of the pull-up node PU will occur as described above. However, if the first double-gate transistor M1 with adjustable Vth is used, the top gate is connected to the voltage of the pull-down node PD.
  • the Vth of the first double-gate transistor M1 will increase at this time, such as 10V, and enter the Vgs of the sub-threshold region and the leakage current region The voltage will also increase correspondingly, for example, 7V to 10V and less than 7V respectively.
  • the voltage Vgs applied to the first double-gate transistor M1 remains unchanged, or 2V, which falls in the leakage current region of the first double-gate transistor M1, which is much smaller than the entry subthreshold
  • the Vgs voltage of the zone is 7V. In this way, the reliability of the GOA circuit is further improved, and the tolerance range of the positive voltage Vgs applied to the first double-gate transistor M1 during the touch period is improved.
  • the pull-up node PU in the shift register unit when the pull-up node PU in the shift register unit is at a low voltage, the pull-down node PD is at a high voltage, and the top gate of the first double-gate transistor M1 is connected to The node PD is pulled down, so the Vth of the first double-gate transistor M1 will become smaller, for example, from 2V to -5V. It can be seen that the current Ids passing through the first double-gate transistor M1 will increase at this time, thus increasing the first double-gate transistor M1.
  • the gate transistor M1 maintains the ability to pull up the low voltage of the node PU.
  • the pull-up control sub-circuit 10 includes the first double-gate transistor M1, which can automatically adjust the Vth of the first double-gate transistor M1 timely, so as to reduce the leakage current or increase the on-state current.
  • the leakage current of the first double-gate transistor M1 is reduced, the reliability of the GOA circuit is improved, and the tolerance range of the Vgs positive voltage applied to the first double-gate transistor M1 is improved.
  • the open state of the first double-gate transistor M1 is increased. current, so that the first double-gate transistor M1 can better maintain the pull-up node PU.
  • the pull-up control sub-circuit 10 is set to include a first double-gate transistor M1.
  • the first double-gate transistor M1 Vth can drift positively.
  • the charge stored on the pull-up node PU leaks through the first double-gate transistor M1 will be reduced, ensuring that the shift register unit can continue to work normally after the stop pit is over.
  • the shift register unit further includes an output control subcircuit 20, and the output control subcircuit 20 includes a second double-gate transistor M2, and the second double-gate transistor M2
  • the first gate and the second gate of the second double-gate transistor M2 are respectively coupled to the pull-up node PU, and the first pole of the second double-gate transistor M2 is coupled to the corresponding clock signal input terminal CKm.
  • the second pole of the second double-gate transistor M2 is coupled to the drive signal output terminal Gout of the shift register unit.
  • m takes any value from 1 to 4.
  • the output control sub-circuit 20 includes a second double-gate transistor M2, and the specific structure of the second double-gate transistor M2 is varied.
  • the second double-gate transistor M2 includes a first gate and a second gate, and one of the first gate and the second gate is located under the active layer as a bottom gate, and the The other of the first gate and the second gate is located above the active layer as a top gate.
  • the orthographic projection of the active layer on the base of the display substrate at least partially overlaps the orthographic projection of the first grid on the base, and the orthographic projection of the active layer on the base overlaps with Orthographic projections of the second grid on the substrate 70 are at least partially overlapped.
  • FIG. 9 it is a double-gate structure diagram of the second double-gate transistor M2.
  • FIG. 10 it is a waveform diagram of signals input or output by each port of the second double-gate transistor M2 .
  • the first gate and the second gate of the second double-gate transistor M2 are connected to the pull-up node PU signal
  • the drain of the second double-gate transistor M2 is connected to the corresponding clock signal CKm
  • the source is coupled to the driving signal output terminal Gout to output the gate driving signal.
  • one frame of the waveform of the voltage signal on the pull-up node PU can be divided into two parts, a high voltage part and a low voltage part.
  • the pull-up node PU When the pull-up node PU is in a low-voltage state, the voltage of the pull-up node PU needs to be kept in a low-voltage state at this time, so as to prevent the second double-gate transistor M2 from turning on by mistake, causing the GOA circuit to output signals incorrectly.
  • the gate and drain of the second double-gate transistor M2 generally form a parasitic capacitance Cgd, and this parasitic capacitance changes when the clock signal changes from a low voltage to a high voltage, or When the high voltage changes to a low voltage, it will couple to the pull-up node PU or instantly pull up the pull-up node PU voltage, or instantly pull down the pull-up node PU voltage, forming small peaks and troughs, burr-like shapes, called ripple.
  • the gate drive signal When this kind of ripple is small, the gate drive signal will also form this kind of ripple through coupling; if the ripple exists in the signal of the pull-up node PU is large, the ripple will transiently apply a larger Vgs to the second double-gate transistor M2 Voltage, and the clock signal is in a high voltage state at this time, it is very likely to cause the GOA circuit to be turned on by mistake, and the gate drive signal will be output by mistake.
  • the output control sub-circuit 20 by setting the output control sub-circuit 20 to include a second double-gate transistor M2, the top gate of the second double-gate transistor M2 is connected to the voltage of the pull-up node PU.
  • the pull-up node PU is a low voltage, so that the Vth of the second double-gate transistor M2 will become larger, and the Vgs voltage applied to the second double-gate transistor M2 by the transient ripple of the pull-up node PU will be much smaller than that of the second double-gate transistor M2 Vth, so the tolerance of the pull-up node PU ripple is greatly improved, and the reliability of the shift register unit is further improved.
  • the second double-gate transistor M2 when the pull-up node PU is in a high voltage state, the second double-gate transistor M2 is in an on state, and a larger current is required to form a gate driving signal, that is, the larger the current within a certain range, the better.
  • the output control sub-circuit 20 By setting the output control sub-circuit 20 to include the second double-gate transistor M2, the Vth of the second double-gate transistor M2 will become smaller, and according to the current formula of the thin film transistor, the current will become larger. This will effectively reduce the rise and fall times of the gate drive signal.
  • the output control sub-circuit 20 by setting the output control sub-circuit 20 to include the second double-gate transistor M2, the top gate of the second double-gate transistor M2 is connected to the pull-up node PU signal, when the pull-up When the node PU is at a low voltage, the tolerance of the second double-gate transistor M2 to the pull-up node PU ripple can be greatly improved, and the reliability of the GOA circuit is improved; and when the pull-up node PU is at a high voltage, the second double-gate transistor M2 can be increased.
  • the output current of the gate transistor M2 reduces the rise and fall times of the gate drive signal.
  • the shift register unit also includes:
  • the output reset sub-circuit 30, the output reset sub-circuit 30 is respectively coupled to the pull-down node PD, the drive signal output terminal Gout of the gate drive circuit, and the first level signal input terminal, the output The reset sub-circuit 30 is configured to control on or off the electrical connection between the drive signal output terminal Gout and the first level signal input terminal under the control of the pull-down node PD;
  • a storage sub-circuit 40 a first terminal of the storage sub-circuit 40 is coupled to the pull-up node PU, and a second terminal of the storage capacitor is coupled to the driving signal output terminal Gout.
  • the output reset subcircuit 30 controls and conducts the electrical connection between the drive signal output terminal Gout and the first level signal input terminal under the control of the pull-down node PD. .
  • the output reset subcircuit 30 controls to disconnect the drive signal output terminal Gout from the first level signal input under the control of the pull-down node PD. electrical connection between terminals.
  • the output reset sub-circuit 30 includes a third transistor M3, the gate of the third transistor M3 is coupled to the pull-down node PD, and the first pole of the third transistor M3 is connected to the driving signal The output terminal Gout is coupled, and the second pole of the third transistor M3 is coupled to the first level signal input terminal;
  • the storage sub-circuit 40 includes a storage capacitor Cst, a first terminal of the storage capacitor Cst is coupled to the pull-up node PU, and a second terminal of the storage capacitor Cst is coupled to the driving signal output terminal Gout.
  • the third transistor M3 in the holding period, the third transistor M3 is turned on, and in the input period, the output period and the reset period, the third transistor M3 is turned off.
  • the shift register unit further includes: a pull-down control subcircuit 50, the pull-down control subcircuit 50 is connected to the pull-up node PU, the pull-down node PD, the first level signal input terminal is coupled to the second level signal input terminal, and the pull-down control subcircuit 50 is used to control the turn-on or turn-off of the pull-up node PU under the control of the pull-up node PU
  • the electrical connection between the pull-down node PD and the first level signal input terminal is also used to control on or off the pull-down node PD and the first level signal input terminal under the control of the second level signal input terminal. Electrical connection between two-level signal input terminals.
  • a negative power supply signal is written into the first level signal input terminal, and a positive power supply signal is written into the second level signal input terminal.
  • the pull-down control subcircuit 50 is used to control the conduction of the pull-down node PD and the first level signal under the control of the pull-up node PU.
  • the electrical connection between the input terminals is also used to control and conduct the electrical connection between the pull-down node PD and the second level signal input terminal under the control of the second level signal input terminal.
  • the pull-down control subcircuit 50 is used to control the disconnection of the electrical connection between the pull-down node PD and the first level signal input terminal under the control of the pull-up node PU, and also use Under the control of the second level signal input end, the electrical connection between the pull-down node PD and the second level signal input end is controlled to be turned on.
  • the pull-down control sub-circuit 50 includes a fourth transistor M4 and a fifth transistor M5, the gate of the fourth transistor M4 and the first pole of the fourth transistor M4 are both connected to the second level
  • the signal input terminal is coupled, the second pole of the fourth transistor M4 is coupled to the pull-down node PD; the gate of the fifth transistor M5 is coupled to the pull-up node PU, and the gate of the fifth transistor M5
  • a first pole is coupled to the pull-down node PD, and a second pole of the fifth transistor M5 is coupled to the first level signal input terminal.
  • both the fourth transistor M4 and the fifth transistor M5 are turned on.
  • the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off.
  • the shift register unit also includes:
  • the input sub-circuit 60, the input sub-circuit 60 is respectively coupled with the input control terminal CKm-1, the input signal terminal In and the pull-up node PU, and the input sub-circuit 60 is used to be under the control of the input control terminal , controlling to turn on or off the electrical connection between the input signal terminal and the pull-up node PU.
  • the input signal terminal In is connected to a signal corresponding to Gn-1 in FIG. 7 .
  • the input subcircuit 60 is used to control and conduct the electrical connection between the input signal terminal and the pull-up node PU under the control of the input control terminal. .
  • the input sub-circuit 60 is used to disconnect the electrical connection between the input signal terminal and the pull-up node PU under the control of the input control terminal.
  • the input sub-circuit 60 is configured to disconnect the electrical connection between the input signal terminal and the pull-up node PU under the control of the input control terminal.
  • the input sub-circuit 60 includes a sixth transistor M6, the gate of the sixth transistor M6 is coupled to the input control terminal, the first pole of the sixth transistor M6 is connected to the input signal terminal The second pole of the sixth transistor M6 is coupled to the pull-up node PU.
  • the sixth transistor M6 is turned on. In the second half of the output period and the reset period, and at least part of the hold period, the sixth transistor M6 is turned off.
  • the sixth transistor M6 can control the potential of the pull-up node PU.
  • the second double-gate transistor M2 can control the output of the driving signal output terminal Gout.
  • the fourth transistor M4 and the fifth transistor M5 form an inverter, the input signal is the signal of the pull-up node PU, and the output signal is the signal of the pull-down node PD.
  • the first double-gate transistor M1 maintains the potential of the pull-up node PU.
  • the third transistor M3 maintains the potential of the driving signal output terminal Gout.
  • the specific structures of the input subcircuit 60 , the pull-down control subcircuit 50 and the output reset subcircuit 30 are not limited to the above exemplary structures.
  • the display substrate includes a plurality of gate lines GA, a plurality of data lines DA and a plurality of sub-pixels, the sub-pixels include pixel circuits and pixel electrodes, and the pixels
  • the circuit includes a pixel double-gate transistor T1, the first gate of the pixel double-gate transistor T1 and the second gate of the pixel double-gate transistor T1 are respectively coupled to the corresponding gate line GA, and the pixel double-gate transistor T1
  • the first pole of the pixel double-gate transistor T1 is coupled to the corresponding data line DA, and the second pole of the pixel double-gate transistor T1 is coupled to the pixel electrode.
  • the gate line GA intersects the data line DA.
  • the gate line GA is coupled to a corresponding shift register unit to receive a gate driving signal.
  • the pixel double-gate transistor T1 turns on or off the electrical connection between the data line DA and the pixel electrode.
  • the pixel double-gate transistor T1 includes a first gate and a second gate, one of the first gate and the second gate is located under the active layer as a bottom gate, and the first gate The other of the first gate and the second gate is located above the active layer as a top gate.
  • the orthographic projection of the active layer on the base 70 of the display substrate at least partially overlaps the orthographic projection of the first grid on the base 70, and the active layer on the base 70 The orthographic projection at least partially overlaps the orthographic projection of the second grid on the substrate 70 .
  • the gate driving signal received by the first gate and the second gate of the pixel dual-gate transistor T1 can be divided into two parts: a high voltage part and a low voltage part.
  • the pixel thin film transistor is in the on state when the voltage is high, and a large current is required at this time to quickly charge the pixel capacitor (including the liquid crystal capacitor C1 and the storage capacitor C2 ) in a short period of time to ensure the charging rate.
  • the above described pixel circuit includes a pixel double-gate transistor T1, and the top gate of the pixel double-gate transistor T1 is connected to the gate drive signal.
  • the Vth of the pixel double-gate transistor T1 becomes smaller, and the pixel double-gate transistor T1 The current of T1 will become larger, which is beneficial to the charging rate. It should be noted that the other ends of the liquid crystal capacitor C1 and the storage capacitor C2 are connected to the common electrode signal Vcom.
  • the pixel circuit in the above setting includes a pixel double-gate transistor T1, and the gate drive signal connected to the top gate is low at this time, which will increase the Vth of the pixel double-gate transistor T1, so that the Vgs voltage applied to the pixel thin film transistor will be far lower. It is smaller than Vth, which can ensure that the pixel double-gate transistor T1 is better turned off, and can reduce the leakage current of the data signal to the pixel capacitance.
  • the pixel circuit in the above setting includes a pixel double-gate transistor T1, and the top gate is connected to the gate output signal.
  • the gate driving signal is a high voltage
  • the current of the pixel double-gate transistor T1 can be increased, preferably Guaranteed pixel charge rate.
  • the gate driving signal is at a low voltage
  • the pixel double-gate transistor T1 can be better turned off to avoid charging wrong data signals.
  • the gate driving signal is at a low voltage
  • the Vth of the pixel double-gate transistor T1 becomes larger, and the tolerance to ripple generated by the gate driving signal becomes higher, and it is not easy to turn on by mistake and charge wrong data signals.
  • the first double-gate transistor M1, the second double-gate transistor M2 and the pixel double-gate transistor T1 adopt the following structure:
  • the orthographic projection of the active layer 73 on the substrate 70 overlaps at least partially the orthographic projection of the first grid 71 on the substrate 70, the active
  • the orthographic projection of the layer 73 on the substrate 70 at least partially overlaps the orthographic projection of the second gate 77 on the substrate 70;
  • the source-drain metal layer forms the first pole 74 and the second pole of the transistor 75, the first pole 74 and the second pole 75 overlap with the active layer respectively.
  • the first insulating layer includes a gate insulating layer
  • the second insulating layer includes a passivation insulating layer
  • one of the first pole and the second pole serves as a source, and the other of the first pole and the second pole serves as a drain.
  • an etch barrier layer can also be provided in the double-gate transistor, a part of the etch barrier layer can be disposed between the source-drain metal layer and the active layer, and the other part covers the active layer without contacting the source-drain metal layer. overlapping parts.
  • the double-gate transistor may be an N-type transistor, a P-type transistor, or a CMOS transistor.
  • the Vth of the double-gate transistor can be dynamically adjusted according to the switching state of the transistor, so as to achieve the purpose of better closing, reducing leakage current and increasing on-state current.
  • An embodiment of the present disclosure also provides a method for driving a display substrate, which is applied to the display substrate provided in the above embodiments, and the driving method includes:
  • the first gate and the second gate of the first double-gate transistor M1 are controlled by the pull-down node PD to control the first double-gate transistor M1 to be cut off;
  • the first gate and the second gate of the first double-gate transistor M1 are controlled by the pull-down node PD to control the first double-gate transistor M1 to be turned on.
  • each driving cycle includes an input period P1 , an output period P2 , a reset period P3 and a hold period P4 in sequence.
  • the output period P2 the drive signal output terminal outputs the same high level as the clock signal.
  • the reset period P3 the clock signal is at a low potential, and the signal output from the driving signal output terminal is reset.
  • the Vth of the first double-gate transistor M1 can be automatically adjusted timely, thereby reducing the leakage current or increasing the on-state current.
  • the leakage current of the first double-gate transistor M1 is reduced, the reliability of the GOA circuit is improved, and the tolerance range of the Vgs positive voltage applied to the first double-gate transistor M1 is improved.
  • the open state of the first double-gate transistor M1 is increased. current, so that the first double-gate transistor M1 can better maintain the pull-up node PU.
  • the Vth of the first double-gate transistor M1 can drift forward. .
  • the charge stored on the pull-up node PU leaks through the first double-gate transistor M1 will be reduced, ensuring that the shift register unit can continue to work normally after the stop pit is over.
  • the shift register unit further includes an output control subcircuit 20, and the output control subcircuit 20 includes a second double-gate transistor M2, the first gate of the second double-gate transistor M2 and the first The second gates of the two double-gate transistors M2 are respectively coupled to the pull-up node PU, the first poles of the second double-gate transistor M2 are coupled to the corresponding clock signal input terminals, and the second gates of the second double-gate transistor M2 are coupled to each other.
  • the second pole is coupled to the drive signal output terminal Gout of the gate drive circuit; the drive method also includes:
  • the first gate and the second gate of the second double-gate transistor are controlled by the pull-up node to control the conduction of the second double-gate transistor;
  • the first gate and the second gate of the second double-gate transistor are controlled by the pull-up node to control the second double-gate transistor to be turned off.
  • the pull-up node PU When the pull-up node PU is at a high voltage, the first gate and the second gate of the second double-gate transistor M2 are controlled by the pull-up node PU to control the conduction of the second double-gate transistor M2; when the pull-up When the node PU is at a low voltage, the first gate and the second gate of the second double-gate transistor M2 are controlled by the pull-up node PU to control the second double-gate transistor M2 to be turned off.
  • the top gate of the second double-gate transistor M2 is connected to the signal of the pull-up node PU.
  • the tolerance of the pull-up node PU ripple improves the reliability of the GOA circuit; and when the pull-up node PU is at a high voltage, the output current of the second double-gate transistor M2 can be increased to reduce the rise and fall time of the gate drive signal .
  • the display substrate includes a plurality of gate lines GA, a plurality of data lines DA and a plurality of sub-pixels
  • the sub-pixels include a pixel circuit and a pixel electrode
  • the pixel circuit includes a pixel double-gate transistor T1, so The first gate of the pixel double-gate transistor T1 and the second gate of the pixel double-gate transistor T1 are respectively coupled to the corresponding gate line GA, and the first electrode of the pixel double-gate transistor T1 is connected to the corresponding data line DA is coupled, and the second pole of the pixel double-gate transistor T1 is coupled to the pixel electrode;
  • the driving method further includes:
  • the first gate and the second gate of the pixel double-gate transistor T1 are controlled by the corresponding gate line GA to control the pixel double-gate transistor T1 to conduct and write data signals to the pixel electrode;
  • the first gate and the second gate of the pixel double-gate transistor T1 are controlled by the corresponding gate line GA to control the pixel double-gate transistor T1 to be turned off, and stop writing data signals to the pixel electrode.
  • the top gate of the pixel double-gate transistor T1 is connected to the gate output signal.
  • the gate driving signal is a high voltage
  • the current of the pixel double-gate transistor T1 can be increased, which is better. Guaranteed pixel charge rate.
  • the double-gate transistor T1 of the pixel can be turned off better, so as to avoid charging an erroneous data signal.
  • the gate driving signal is at a low voltage
  • the Vth of the pixel double-gate transistor T1 becomes larger, and the tolerance to ripple generated by the gate driving signal becomes higher, and it is not easy to turn on by mistake and charge wrong data signals.
  • Embodiments of the present disclosure also provide a display panel, including the display substrate provided in the above embodiments.
  • the above display panel includes a liquid crystal display panel and an organic light emitting diode display panel, but not limited thereto.
  • the Vth of the first double-gate transistor can drift forward.
  • the charge stored on the pull-up node will be reduced through the first double-gate transistor, which ensures that the shift register unit can continue to work normally after the pit stops.
  • the top gate of the second double-gate transistor is connected to the pull-up node signal.
  • the pull-up node is at a low voltage
  • the tolerance of the second double-gate transistor to the pull-up node ripple can be greatly improved, and the The reliability of the GOA circuit is improved; and when the pull-up node is at a high voltage, the output current of the second double-gate transistor can be increased, and the rising and falling time of the gate driving signal can be reduced.
  • the top gate of the pixel double-gate transistor is connected to the gate output signal, and when the gate driving signal is a high voltage, the current of the pixel double-gate transistor can be increased to better ensure the charging rate of the pixel. And when the gate driving signal is at a low voltage, the double-gate transistor of the pixel can be turned off better to avoid charging wrong data signals. Moreover, when the gate drive signal is at a low voltage, the Vth of the pixel double-gate transistor becomes larger, and the tolerance to ripple generated by the gate drive signal becomes higher, and it is not easy to turn on by mistake and charge wrong data signals.
  • the display panel provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display panel further includes an opposite substrate and a liquid crystal layer, the opposite substrate is disposed opposite to the display substrate, and the liquid crystal layer is located between the opposite substrate and the display substrate.
  • the display panel can be applied to any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display panel can also be combined with a flexible circuit board, a printed circuit board, etc. Boards and backplanes, etc. are used in combination.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous.
  • These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

本公开提供一种显示基板及其驱动方法、显示面板。所述显示基板包括栅极驱动电路，所述栅极驱动电路包括多个移位寄存器单元，所述移位寄存器单元包括上拉节点，下拉节点和上拉控制子电路；所述上拉控制子电路包括：第一双栅晶体管，所述第一双栅晶体管的第一栅极和所述第一双栅晶体管的第二栅极分别与所述下拉节点耦接，所述第一双栅晶体管的第一极与所述上拉节点耦接，所述第一双栅晶体管的第二极与第一电平信号输入端耦接。

Description

显示基板及其驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其驱动方法、显示面板。
背景技术
随着显示技术的不断发展，高分辨率、窄边框成为显示产品发展的趋势。同时为了节约生产成本，一般采用GOA(英文：Gate Driver on array)技术，采用这种技术不需要在显示基板上设置栅极驱动芯片，节约了材料成本。
发明内容
本公开的目的在于提供一种显示基板及其驱动方法、显示面板。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括栅极驱动电路，所述栅极驱动电路包括多个移位寄存器单元，所述移位寄存器单元包括上拉节点，下拉节点和上拉控制子电路；所述上拉控制子电路包括：
第一双栅晶体管，所述第一双栅晶体管的第一栅极和所述第一双栅晶体管的第二栅极分别与所述下拉节点耦接，所述第一双栅晶体管的第一极与所述上拉节点耦接，所述第一双栅晶体管的第二极与第一电平信号输入端耦接。
可选的，所述移位寄存器单元还包括输出控制子电路，所述输出控制子电路包括第二双栅晶体管，所述第二双栅晶体管的第一栅极和所述第二双栅晶体管的第二栅极分别与所述上拉节点耦接，所述第二双栅晶体管的第一极与对应的时钟信号输入端耦接，所述第二双栅晶体管的第二极与所述移位寄存器单元的驱动信号输出端耦接。
可选的，所述移位寄存器单元还包括：
输出复位子电路，所述输出复位子电路分别与所述下拉节点，所述栅极驱动电路的驱动信号输出端，以及所述第一电平信号输入端耦接，所述输出 复位子电路用于在所述下拉节点的控制下，控制导通或断开所述驱动信号输出端与所述第一电平信号输入端之间的电连接；
存储子电路，所述存储子电路的第一端与所述上拉节点耦接，所述存储电容的第二端与所述驱动信号输出端耦接。
可选的，所述移位寄存器单元还包括：下拉控制子电路，所述下拉控制子电路分别与所述上拉节点，所述下拉节点，所述第一电平信号输入端和第二电平信号输入端耦接，所述下拉控制子电路用于在所述上拉节点的控制下，控制导通或断开所述下拉节点与所述第一电平信号输入端之间的电连接，还用于在所述第二电平信号输入端的控制下，控制导通或断开所述下拉节点与所述第二电平信号输入端之间的电连接。
可选的，所述移位寄存器单元还包括：
输入子电路，所述输入子电路分别与输入控制端，输入信号端和所述上拉节点耦接，所述输入子电路用于在所述输入控制端的控制下，控制导通或断开所述输入信号端与所述上拉节点之间的电连接。
可选的，所述输出复位子电路包括第三晶体管，所述第三晶体管的栅极与所述下拉节点耦接，所述第三晶体管的第一极与所述驱动信号输出端耦接，所述第三晶体管的第二极与所述第一电平信号输入端耦接；
所述存储子电路包括存储电容，所述存储电容的第一端与所述上拉节点耦接，所述存储电容的第二端与所述驱动信号输出端耦接。
可选的，所述下拉控制子电路包括第四晶体管和第五晶体管，所述第四晶体管的栅极和所述第四晶体管的第一极均与所述第二电平信号输入端耦接，所述第四晶体管的第二极与所述下拉节点耦接；所述第五晶体管的栅极所述上拉节点耦接，所述第五晶体管的第一极与所述下拉节点耦接，所述第五晶体管的第二极与所述第一电平信号输入端耦接。
可选的，所述输入子电路包括第六晶体管，所述第六晶体管的栅极与所述输入控制端耦接，所述第六晶体管的第一极与所述输入信号端耦接，所述第六晶体管的第二极与所述上拉节点耦接。
可选的，所述显示基板包括多条栅线，多条数据线和多个子像素，所述子像素包括像素电路和像素电极，所述像素电路包括像素双栅晶体管，所述 像素双栅晶体管的第一栅极和所述像素双栅晶体管的第二栅极分别与对应的栅线耦接，所述像素双栅晶体管的第一极与对应的数据线耦接，所述像素双栅晶体管的第二极与所述像素电极耦接。
可选的，第一双栅晶体管，第二双栅晶体管和像素双栅晶体管采用如下结构：
沿远离显示基板的基底的方向依次层叠设置的第一栅极，第一绝缘层，有源层，源漏金属层，第二绝缘层和第二栅极；所述有源层在所述基底上的正投影分别与所述第一栅极在所述基底上的正投影和所述第二栅极在所述基底上的正投影至少部分交叠；所述源漏金属层形成晶体管的第一极和第二极，该第一极和第二极分别与所述有源层搭接。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示基板的驱动方法，应用于上述显示基板，所述驱动方法包括：
输入时段，输出时段和复位时段，第一双栅晶体管的第一栅极和第二栅极在下拉节点的控制下，控制所述第一双栅晶体管截止；
保持时段，所述第一双栅晶体管的第一栅极和第二栅极在下拉节点的控制下，控制所述第一双栅晶体管导通。
可选的，移位寄存器单元还包括输出控制子电路，所述输出控制子电路包括第二双栅晶体管，所述第二双栅晶体管的第一栅极和所述第二双栅晶体管的第二栅极分别与上拉节点耦接，所述第二双栅晶体管的第一极与对应的时钟信号输入端耦接，所述第二双栅晶体管的第二极与栅极驱动电路的驱动信号输出端耦接；所述驱动方法还包括：
在输入时段，输出时段和复位时段，第二双栅晶体管的第一栅极和第二栅极在上拉节点的控制下，控制所述第二双栅晶体管导通；
在保持时段，第二双栅晶体管的第一栅极和第二栅极在上拉节点的控制下，控制所述第二双栅晶体管截止。
可选的，所述显示基板包括多条栅线，多条数据线和多个子像素，所述子像素包括像素电路和像素电极，所述像素电路包括像素双栅晶体管，所述像素双栅晶体管的第一栅极和所述像素双栅晶体管的第二栅极分别与对应的栅线耦接，所述像素双栅晶体管的第一极与对应的数据线耦接，所述像素双 栅晶体管的第二极与所述像素电极耦接；所述驱动方法还包括：
像素驱动时段，像素双栅晶体管的第一栅极和第二栅极在对应的栅线的控制下，控制所述像素双栅晶体管导通；
非像素驱动时段，像素双栅晶体管的第一栅极和第二栅极在对应的栅线的控制下，控制所述像素双栅晶体管截止。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示面板，包括上述显示基板。
可选的，所述显示面板还包括对向基板和液晶层，所述对向基板与所述显示基板相对设置，所述液晶层位于所述对向基板和所述显示基板之间。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的双栅晶体管的截面示意图；
图2为本公开实施例提供的双栅晶体管的电路符号图；
图3为本公开实施例提供的顶栅电压对电流影响的曲线示意图；
图4为本公开实施例提供的漏电流在各区域分布示意图；
图5为本公开实施例提供的下拉控制子电路的等效示意图；
图6为本公开实施例提供的移位寄存器单元的第一电路结构示意图；
图7为本公开实施例提供的移位寄存器单元的工作时序图；
图8为本公开实施例提供的移位寄存器单元的第二电路结构示意图；
图9为本公开实施例提供的第二双栅晶体管产生的寄生电容的示意图；
图10为本公开实施例提供的第二双栅晶体管的工作时序图；
图11为本公开实施例提供的像素电路结构示意图；
图12为本公开实施例提供的栅极驱动信号和数据信号波形示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其驱动方法、显示面板， 下面结合说明书附图进行详细描述。
本公开提供一种显示基板，显示基板包括显示区域和包围所述显示区域的非显示区域。显示区域中包括多个子像素，每个子像素均包括薄膜晶体管，该薄膜晶体管能够驱动子像素实现显示功能。非显示区域中包括GOA电路，GOA电路一般为多级移位寄存器单元组成，每级移位寄存器单元均由若干个薄膜晶体管组成。
经研究发现，为了更好的保证薄膜晶体管的工作性能，我们希望薄膜晶体管在开态时能够有更大的电流，在关态时能非常好的关闭，不要出现误打开的情况，同时也希望薄膜晶体管处于关闭状态时漏电流尽可能的小。
而在关态时需要薄膜晶体管的阈值电压(Vth)比较大才能满足防止误打开和减小漏电流的目的；而开启时需要薄膜晶体管的Vth比较小才能满足开态时有较大的电流。这样就需要薄膜晶体管的Vth是能够根据开关状态动态可调节的，但是目前传统的薄膜晶体管的Vth在工艺完成后是无法改变的。需要说明，此处所说的无法改变是不考虑薄膜晶体管长时间工作应力导致的Vth漂移，且这种漂移也只是薄膜晶体管初始的Vth发生了改变，无法根据薄膜晶体管开关状态需求动态调节Vth。
请参阅图2和图6，本公开实施例提供了一种显示基板，包括栅极驱动电路，所述栅极驱动电路包括多个移位寄存器单元，所述移位寄存器单元包括上拉节点PU，下拉节点PD和上拉控制子电路10；所述上拉控制子电路10包括：
第一双栅晶体管M1，所述第一双栅晶体管M1的第一栅极和所述第一双栅晶体管M1的第二栅极分别与所述下拉节点PD耦接，所述第一双栅晶体管M1的第一极与所述上拉节点PU耦接，所述第一双栅晶体管M1的第二极与第一电平信号输入端(接入负电源信号VSS或者VGL)耦接。
示例性的，所述显示基板包括显示区域和包围所述显示区域的非显示区域，所述栅极驱动电路位于所述非显示区域。所述显示区域包括多个子像素，所述多个子像素呈阵列分布。所述子像素包括像素电路，像素电路能够控制子像素显示。
示例性的，所述多个子像素划分为多行子像素，所述移位寄存器单元的 驱动信号输出端Gout与对应的一行子像素中包括的一行像素电路耦接，用于向像素电路输出栅极驱动信号。
示例性的，所述上拉节点PU的电位和所述下拉节点PD的电位相反。
所述上拉控制子电路10包括第一双栅晶体管M1，所述第一双栅晶体管M1的具体结构多种多样。示例性的，如图2所示，所述第一双栅晶体管M1包括第一栅极和第二栅极，所述第一栅极和第二栅极中的一个位于有源层的下方，作为底栅BG，所述第一栅极和第二栅极中的另一个位于有源层的上方，作为顶栅TG。所述有源层在所述显示基板的基底上的正投影与所述第一栅极在所述基底上的正投影至少部分交叠，所述有源层在所述基底上的正投影与所述第二栅极在所述基底上的正投影至少部分交叠。
更详细地说，以N型薄膜晶体管为例。当薄膜晶体管处于关闭状态时，顶栅输入低电压，薄膜晶体管的Vth会变大，这样可以更好的关闭薄膜晶体管，避免误打开的情况，并且可以减小漏电流。当薄膜晶体管处于开态时，顶栅输入高电压，薄膜晶体管的Vth会变小，这样薄膜晶体管的开态电流会变大。因此，通过这种双栅技术，就可以根据薄膜晶体管的开关状态，动态的调整薄膜晶体管的Vth，达到关闭更好，减少漏电流以及增加开态电流的目的。
为双栅晶体管的膜层结构示意图。需要说明，所示双栅晶体管的具体结构多种多样，下面给出一种示例性的结构。
在基底上按顺序和一定图形形状形成各图层：底栅(英文：bottom gate，简称：BG)、栅极绝缘层、有源层、源极层，漏极层、钝化绝缘层、像素电极和顶栅(英文：top gate，简称：TG)。与传统薄膜晶体管相比，增加了顶栅，增加的顶栅是在底栅上方，因此在将双栅晶体管应用于子像素中时，不会减小像素的开口率。
如图2所示，为双栅薄膜晶体管的电路符号图。有四个端口，分别为顶栅TG、底栅BG和源极S和漏极D。
如图3所示，为双栅薄膜晶体管在不同顶栅电压影响下的转移输出曲线电流(Ids)。传统薄膜晶体管有三个端口输入，会形成两种需要重点关注的电压，即：VBG_S(底栅-源极电压)和VDS(源极-漏极电压)，这两种电压 会直接影响薄膜晶体管的电流。双栅薄膜晶体管除了上述两种之外的电压还会多形成一个电压VTG_S(顶栅-源极电压)。从图3中能够发现，当顶栅VTG_S＝5V时，双栅薄膜晶体管电流Ids整体向左侧移动；而当顶栅VTG_S＝-5V时，双栅薄膜晶体管电流整体向右移动。当VTG_S＞0V时，双栅薄膜晶体管的Vth负漂移；当VTG_S＜0V时，双栅薄膜晶体管Vth正漂移。双栅薄膜晶体管的Vth漂移和VTG_S成负相关，即在一定范围内，VTG_S正值越大，Vth负漂移越多；VTG_S负值越小，Vth正漂移越大多。因此通过控制双栅薄膜晶体管的顶栅电压能够控制双栅薄膜晶体管的Vth。需要说明的是，图3的横坐标V DG_S代表底栅对应的Vgs，即底栅的电压Vg与源极电压Vs的差值，底栅对应的Vgs取值在-15V至+15V之间。
如图4所示，为薄膜晶体管转移曲线和漏电流分析示意图。转移曲线图可以分为三个部分，对应三个区域：漏电流区、亚阈值区和上阈值区。根据施加在薄膜晶体管上的Vgs电压，漏电流一般认为发生在漏电流区和亚阈值区。其中漏电流区漏电流较小；而亚阈值区可分为两部分：Vgs大于Vth的开态电流部分和Vgs低于Vth的亚阈值区的漏电流。其中可认为Vth等于薄膜晶体管的电流Ids(归一化后)为10nA时Vgs的电压。能够发现，漏电流区的漏电流较小，而亚阈值区的漏电流较大。如果我们通过双栅技术控制双栅薄膜晶体管的Vth正漂移，让施加在薄膜晶体管上的Vgs落在漏电流区，远离亚阈值区，除了可以有效的避免误打开薄膜晶体管，还可以有效的减少漏电流。同样，如果控制双栅薄膜晶体管的Vth负漂移，可以有效的增加薄膜晶体的开态电流。需要说明的是，图4的横坐标V DG_S代表底栅对应的Vgs，即底栅的电压Vg与源极电压Vs的差值，底栅对应的Vgs取值在-5V至+15V之间。
值得注意，归一化为测得的开态电流Ids除以器件的沟道宽长比。10nA取值法是器件的开态电流Ids归一化后，以在10nA时此时器件的Vgs作为阈值电压Vth。
如图7所示，以栅极驱动电路采用四条时钟信号线(CK1，CK2，CK3和CK4)驱动为例，占空比为50％，也可以是8条时钟信号线，12条时钟信号线，16条时钟信号线等，大于等于2的偶数条时钟信号线均可，在此不做限定。
每级移位寄存器单元依次接入对应的时钟信号，例如Gn-2级移位寄存器单元接入CK1，Gn-1级移位寄存器单元接入CK2，Gn级移位寄存器单元接入CK3，Gn+1级移位寄存器单元接入CK4，以此类推，四级移位寄存器单元为一个循环接入时钟信号。需要说明，图7中的PUn-2至PUn+4代表各级移位寄存器单元中的上拉节点。图7中的Gn-2至Gn+4代表各级移位寄存器单元中的驱动信号输出端。
同时需要注意的是，图7中存在一个触控时段，在触控时间段需要暂停GOA电路，来用于收集触控信号，此时时钟信号要求暂停脉冲信号，设置为恒压低电压信号(如：VGL信号)，在触控时段结束后，时钟信号才能恢复正常脉冲信号。这样不可避免的需要有些移位寄存器单元的上拉节点PU在触控时段内存储高电压，等待触控时段结束后，GOA电路才能继续正常工作。图7中Gn-1级移位寄存器单元、Gn级移位寄存器单元、Gn+1级移位寄存器单元和Gn+2级移位寄存器单元中的上拉节点PU就是在触控阶段内存储了高电压，称之为停坑级；而绝大部分的移位寄存器单元在触控时段内上拉节点PU为低电压。
图5为上述移位寄存器单元中下拉控制子电路50的具体结构图，以及下拉控制子电路50的等效电路图。下拉控制子电路50包括第四晶体管M4和第五晶体管M5。
第四晶体管M4和第五晶体管M5形成了反向器，输入信号为上拉节点PU电压，输出信号为下拉节点PD电压，下拉节点PD接入维持上拉节点PU的第一双栅晶体管M1栅极。这里假定VDD(正电源信号)电压为20V恒压高电压，而VSS(负电源信号)电压为-10V恒压低电压。在触控时段停坑级中，上拉节点PU是高电压，这样第四晶体管M4和第五晶体管M5就同时处于开启状态，VDD和VSS就形成了一个通路，第四晶体管M4和第五晶体管M5就可以等效成两个不同阻值的电阻(如R1和R2)，而下拉节点PD电压取决于第四晶体管M4和第五晶体管M5这两个等效电阻比值。根据简单的物理电学知识可知，下拉节点PD电压会大于VSS电压而小于VDD电压，虽然可以通过调整第四晶体管M4和第五晶体管M5的沟道宽长比来调整等效电阻，但是下拉节点PD肯定会大于VSS电压，这里假设为-8V电压。这样对于第一双栅晶体管M1来说， 栅极电压为下拉节点PD的-8V，源极电压为VSS电压-10V，而漏极为上拉节点PU高电压，第一双栅晶体管M1的栅源电压Vgs＝V PD-VSS＝2V。如果第一双栅晶体管M1的Vth小于2V，第一双栅晶体管M1处于开启状态，上拉节点PU的高电压很快会被漏完，停坑结束后GOA电路无法正常继续工作；如果此时施加在第一双栅晶体管M1上的Vgs电压落在亚阈值区漏电流，一般而言停坑时间都是较长的，例如200微秒左右，这个时间足够将上拉节点PU的电压漏完，即使没有将停坑级的上拉节点PU电压漏完，停坑级和非停坑级上拉节点PU的电压差异问题也会很可能形成停坑纹的问题。只有将施加在第一双栅晶体管M1上的Vgs电压落在漏电流区，才能安全的度过停坑时间，保证后续GOA电路的正常工作。
根据上述分析可知，对于处于停坑级的移位寄存器单元，在停坑时间内，第一双栅晶体管M1的Vth要尽可能的大，使施加在第一双栅晶体管M1上的Vgs的电压要小于第一双栅晶体管M1的Vth，最好落在第一双栅晶体管M1转移曲线的漏电流区。值得注意，传统的薄膜晶体管的Vth在显示面板工艺结束后是不可调节的，只能在制作显示面板的工艺过程中整体对显示面板上所有薄膜晶体管Vth做的偏小或偏大。如果工艺上刻意整体将Vth做的过正过大，这样显示面板上会产生上拉节点PU和驱动信号输出端Gout的电位维持不足，以及像素充电率不足等问题。
通过设置上拉控制子电路10包括第一双栅晶体管M1，能够根据需求动态的正向或负向的调控第一双栅晶体管M1的Vth。对于停坑级在触控时段时，上拉节点PU为高电压，而下拉节点PD为低电压，而第一双栅晶体管M1的顶栅接入的是下拉节点PD，因此第一双栅晶体管M1的Vth变大，这样可以大大的增加了第一双栅晶体管M1转移曲线漏电流区电压的范围。示例性的，第一双栅晶体管M1的Vth原本为3V，进入亚阈值区漏电流的Vgs电压范围为0V至3V，进入漏电流区的Vgs电压范围为小于0V。如果此时第一双栅晶体管M1的Vgs为2V，传统的薄膜晶体管器件进入了亚阈值区漏电流，如上述所述会出现上拉节点PU漏电问题。而如果采用Vth可调的第一双栅晶体管M1，顶栅接入下拉节点PD电压。停坑级在触控时段，由于下拉节点PD为负电压，例如-8V，此时第一双栅晶体管M1的Vth会增大，例如变为10V，而 进入亚阈值区和漏电流区的Vgs电压也会相应的变大，例如分别变为7V至10V和小于7V。而由于电路中没有其他的变化，所以施加在第一双栅晶体管M1上的电压Vgs是不变的，还是2V，落在了第一双栅晶体管M1的漏电流区，远远小于进入亚阈值区的Vgs电压7V。这样GOA电路的可靠性得到进一步提升，触控时段内对施加在第一双栅晶体管M1上的Vgs正电压容忍范围得到了提升。
此外，对触控时段内的非停坑级和非触控时段，移位寄存器单元中上拉节点PU为低电压时，下拉节点PD为高电压，第一双栅晶体管M1的顶栅接入下拉节点PD，因此第一双栅晶体管M1的Vth会变小，例如从2V变成了-5V，可知此时通过第一双栅晶体管M1的电流Ids会增大，这样就增加了第一双栅晶体管M1维持上拉节点PU低电压的能力。
综上所述，上拉控制子电路10包括第一双栅晶体管M1，可以适时自动调节第一双栅晶体管M1的Vth，从而能够减少漏电流或增加开态电流。对触控时段内的停坑级，减少了第一双栅晶体管M1的漏电流，提升了GOA电路的可靠性，并对施加在第一双栅晶体管M1上的Vgs正电压容忍范围得到了提升；而对于触控时段内的非停坑级和非触控时段，对于正常工作时上拉节点PU为低电压的移位寄存器单元而言，则是增加了第一双栅晶体管M1的开态电流，从而使第一双栅晶体管M1对上拉节点PU的维持更好。
因此，本公开实施例提供的显示基板中，设置上拉控制子电路10包括第一双栅晶体管M1，在上拉节点PU为高电压，下拉节点PD为低电压时，第一双栅晶体管M1的Vth能够正向漂移。对触控时段内的停坑级而言，上拉节点PU上存储的电荷通过第一双栅晶体管M1漏掉的会减少，保证了停坑结束后移位寄存器单元能够继续正常工作。
如图8所示，在一些实施例中，所述移位寄存器单元还包括输出控制子电路20，所述输出控制子电路20包括第二双栅晶体管M2，所述第二双栅晶体管M2的第一栅极和所述第二双栅晶体管M2的第二栅极分别与所述上拉节点PU耦接，所述第二双栅晶体管M2的第一极与对应的时钟信号输入端CKm耦接，所述第二双栅晶体管M2的第二极与所述移位寄存器单元的驱动信号输出端Gout耦接。
示例性的，m取值1至4中的任意一个。
所述输出控制子电路20包括第二双栅晶体管M2，所述第二双栅晶体管M2的具体结构多种多样。示例性的，所述第二双栅晶体管M2包括第一栅极和第二栅极，所述第一栅极和第二栅极中的一个位于有源层的下方，作为底栅，所述第一栅极和第二栅极中的另一个位于有源层的上方，作为顶栅。所述有源层在所述显示基板的基底上的正投影与所述第一栅极在所述基底上的正投影至少部分交叠，所述有源层在所述基底上的正投影与所述第二栅极在所述基底70上的正投影至少部分交叠。
如图9所示，为第二双栅晶体管M2的双栅结构图。如图10所示，为第二双栅晶体管M2各端口输入或输出的信号波形图。示例性的，第二双栅晶体管M2的第一栅极和第二栅极接上拉节点PU信号，第二双栅晶体管M2的漏极接对应的时钟信号CKm，第二双栅晶体管M2的源极与驱动信号输出端Gout耦接，输出栅极驱动信号。
如图10所示，更详细地说，上拉节点PU上的电压信号的波形一帧可分为两个部分，高电压部分和低电压部分。在上拉节点PU处于低电压状态时，此时需要上拉节点PU电压保持低电压状态，避免第二双栅晶体管M2误打开，导致GOA电路错误输出信号。
如图9和图10所示，在工艺制作时，第二双栅晶体管M2的栅极和漏极一般会形成一个寄生电容Cgd，这个寄生电容在时钟信号由低电压变为高电压时，或高电压变为低电压时，会对上拉节点PU偶合或瞬间拉高上拉节点PU电压，或瞬间拉低上拉节点PU电压，形成一个个小波峰波谷，毛刺一样的形状，称之为ripple。当这种ripple较小时，通过偶合会让栅极驱动信号同样形成这种ripple；如果上拉节点PU的信号存在的ripple较大，ripple会对第二双栅晶体管M2瞬态施加较大的Vgs电压，而且此时时钟信号处于高电压状态，非常有可能造成GOA电路的误打开，误输出栅极驱动信号。
而上述实施例提供的显示基板中，通过设置所述输出控制子电路20包括第二双栅晶体管M2，第二双栅晶体管M2的顶栅接入上拉节点PU的电压，此时上拉节点PU为低电压，这样第二双栅晶体管M2的Vth会变大，上拉节点PU这种瞬态的ripple施加的对第二双栅晶体管M2的Vgs电压会远远小于第 二双栅晶体管M2的Vth，这样对上拉节点PU ripple的容忍度大大提升，进一步提高了移位寄存器单元的可靠性。
而当上拉节点PU为高电压状态时，第二双栅晶体管M2处于开启状态，需要较大的电流来形成栅极驱动信号，即希望电流一定范围内越大越好。通过设置所述输出控制子电路20包括第二双栅晶体管M2，第二双栅晶体管M2的Vth会变小，而根据薄膜晶体管的电流公式，电流会变大。这样会有效的减少栅极驱动信号的上升和下降时间。
综上所述，上述实施例提供的显示基板中，通过设置所述输出控制子电路20包括第二双栅晶体管M2，第二双栅晶体管M2顶栅接入上拉节点PU信号，当上拉节点PU为低电压时，可以大大提升第二双栅晶体管M2对上拉节点PU ripple的容忍度，提高了GOA电路的可靠性；而当上拉节点PU为高电压时，可以增加第二双栅晶体管M2的输出电流，减小栅极驱动信号的上升和下降时间。
如图6和图8所示，在一些实施例中，所述移位寄存器单元还包括：
输出复位子电路30，所述输出复位子电路30分别与所述下拉节点PD，所述栅极驱动电路的驱动信号输出端Gout，以及所述第一电平信号输入端耦接，所述输出复位子电路30用于在所述下拉节点PD的控制下，控制导通或断开所述驱动信号输出端Gout与所述第一电平信号输入端之间的电连接；
存储子电路40，所述存储子电路40的第一端与所述上拉节点PU耦接，所述存储电容的第二端与所述驱动信号输出端Gout耦接。
示例性的，在保持时段，所述输出复位子电路30在所述下拉节点PD的控制下，控制导通所述驱动信号输出端Gout与所述第一电平信号输入端之间的电连接。
示例性的，在输入时段，输出时段和复位时段，所述输出复位子电路30在所述下拉节点PD的控制下，控制断开所述驱动信号输出端Gout与所述第一电平信号输入端之间的电连接。
示例性的，所述输出复位子电路30包括第三晶体管M3，所述第三晶体管M3的栅极与所述下拉节点PD耦接，所述第三晶体管M3的第一极与所述驱动信号输出端Gout耦接，所述第三晶体管M3的第二极与所述第一电平信号 输入端耦接；
所述存储子电路40包括存储电容Cst，所述存储电容Cst的第一端与所述上拉节点PU耦接，所述存储电容Cst的第二端与所述驱动信号输出端Gout耦接。
示例性的，在保持时段，所述第三晶体管M3导通，在输入时段，输出时段和复位时段，所述第三晶体管M3截止。
如图6和图8所示，在一些实施例中，所述移位寄存器单元还包括：下拉控制子电路50，所述下拉控制子电路50分别与所述上拉节点PU，所述下拉节点PD，所述第一电平信号输入端和第二电平信号输入端耦接，所述下拉控制子电路50用于在所述上拉节点PU的控制下，控制导通或断开所述下拉节点PD与所述第一电平信号输入端之间的电连接，还用于在所述第二电平信号输入端的控制下，控制导通或断开所述下拉节点PD与所述第二电平信号输入端之间的电连接。
示例性的，所述第一电平信号输入端写入负电源信号，所述第二电平信号输入端写入正电源信号。
示例性的，在输入时段，输出时段和复位时段，所述下拉控制子电路50用于在所述上拉节点PU的控制下，控制导通所述下拉节点PD与所述第一电平信号输入端之间的电连接，还用于在第二电平信号输入端的控制下，控制导通所述下拉节点PD与所述第二电平信号输入端之间的电连接。在保持时段，所述下拉控制子电路50用于在所述上拉节点PU的控制下，控制断开所述下拉节点PD与所述第一电平信号输入端之间的电连接，还用于在第二电平信号输入端的控制下，控制导通所述下拉节点PD与所述第二电平信号输入端之间的电连接。
示例性的，所述下拉控制子电路50包括第四晶体管M4和第五晶体管M5，所述第四晶体管M4的栅极和所述第四晶体管M4的第一极均与所述第二电平信号输入端耦接，所述第四晶体管M4的第二极与所述下拉节点PD耦接；所述第五晶体管M5的栅极所述上拉节点PU耦接，所述第五晶体管M5的第一极与所述下拉节点PD耦接，所述第五晶体管M5的第二极与所述第一电平信号输入端耦接。
示例性的，在输入时段，输出时段和复位时段，所述第四晶体管M4和所述第五晶体管M5均导通。在保持时段，所述第四晶体管M4导通，所述第五晶体管M5截止。
如图6和图8所示，在一些实施例中，所述移位寄存器单元还包括：
输入子电路60，所述输入子电路60分别与输入控制端CKm-1，输入信号端In和所述上拉节点PU耦接，所述输入子电路60用于在所述输入控制端的控制下，控制导通或断开所述输入信号端与所述上拉节点PU之间的电连接。
示例性的，输入信号端In接入如图7中Gn-1对应的信号。
示例性的，在输入时段和前半部分输出时段，所述输入子电路60用于在所述输入控制端的控制下，控制导通所述输入信号端与所述上拉节点PU之间的电连接。在后半部分输出时段和复位时段，所述输入子电路60用于在所述输入控制端的控制下，控制断开所述输入信号端与所述上拉节点PU之间的电连接。在保持时段中的至少部分时段，所述输入子电路60用于在所述输入控制端的控制下，控制断开所述输入信号端与所述上拉节点PU之间的电连接。
示例性的，所述输入子电路60包括第六晶体管M6，所述第六晶体管M6的栅极与所述输入控制端耦接，所述第六晶体管M6的第一极与所述输入信号端耦接，所述第六晶体管M6的第二极与所述上拉节点PU耦接。
在输入时段和前半部分输出时段，所述第六晶体管M6导通。在后半部分输出时段和复位时段，以及在保持时段中的至少部分时段，所述第六晶体管M6截止。
上述实施例提供的移位寄存器单元中，第六晶体管M6能够控制上拉节点PU的电位。第二双栅晶体管M2能够控制驱动信号输出端Gout输出。第四晶体管M4和第五晶体管M5形成反相器，输入信号为上拉节点PU信号，输出信号为下拉节点PD信号。第一双栅晶体管M1起到维持上拉节点PU的电位的作用。第三晶体管M3起到维持驱动信号输出端Gout的电位作用。
需要说明的是，上述实施例提供的移位寄存器单元中，输入子电路60，下拉控制子电路50和输出复位子电路30的具体结构不仅限于上述示例性的结构。
如图11和图12所示，在一些实施例中，所述显示基板包括多条栅线GA， 多条数据线DA和多个子像素，所述子像素包括像素电路和像素电极，所述像素电路包括像素双栅晶体管T1，所述像素双栅晶体管T1的第一栅极和所述像素双栅晶体管T1的第二栅极分别与对应的栅线GA耦接，所述像素双栅晶体管T1的第一极与对应的数据线DA耦接，所述像素双栅晶体管T1的第二极与所述像素电极耦接。
示例性的，所述栅线GA与所述数据线DA相交。
示例性的，所述栅线GA与对应的移位寄存器单元耦接，接收栅极驱动信号。所述像素双栅晶体管T1在所述栅极驱动信号的控制下，导通或断开所述数据线DA与所述像素电极之间的电连接。
示例性的，所述像素双栅晶体管T1包括第一栅极和第二栅极，所述第一栅极和第二栅极中的一个位于有源层的下方，作为底栅，所述第一栅极和第二栅极中的另一个位于有源层的上方，作为顶栅。所述有源层在所述显示基板的基底70上的正投影与所述第一栅极在所述基底70上的正投影至少部分交叠，所述有源层在所述基底70上的正投影与所述第二栅极在所述基底70上的正投影至少部分交叠。
如图11所示，所述像素双栅晶体管T1的第一栅极和第二栅极接收的栅极驱动信号可以分为两个部分：高电压部分和低电压部分。在高电压时像素薄膜晶体管处于开启状态，此时需要较大的电流，以在较短时间内将像素电容(包括液晶电容C1和存储电容C2)快速充满，保证充电率。上述设置所述像素电路包括像素双栅晶体管T1，像素双栅晶体管T1的顶栅接入栅极驱动信号，当栅极驱动信号为高电压时，像素双栅晶体管T1Vth变小，像素双栅晶体管T1的电流会变大，对充电率有利。需要说明，液晶电容C1和存储电容C2的另一端接入公共电极信号Vcom。
而当栅极驱动信号为低电压时，需要保证像素双栅晶体管T1处于关闭状态，避免充入错误的数据信号。上述设置所述像素电路包括像素双栅晶体管T1，接入顶栅的栅极驱动信号此时为低，会使像素双栅晶体管T1的Vth变大，使施加在像素薄膜晶体管上的Vgs电压远小于Vth，这样可以保证像素双栅晶体管T1更好的关闭，并可以减少数据信号对像素电容的漏电流。
综上所述，上述设置所述像素电路包括像素双栅晶体管T1，顶栅接入栅 极输出信号，当栅极驱动信号为高电压时，能使像素双栅晶体管T1电流增大，更好的保证像素充电率。而当栅极驱动信号为低电压时，能使像素双栅晶体管T1更好的关闭，避免充入错误数据信号。而且当栅极驱动信号为低电压时，像素双栅晶体管T1的Vth变大，对栅极驱动信号产生的ripple容忍度变高，不容易误打开，充入错误的数据信号。
如图1所示，在一些实施例中，第一双栅晶体管M1，第二双栅晶体管M2和像素双栅晶体管T1采用如下结构：
沿远离显示基板的基底70的方向依次层叠设置的第一栅极71，第一绝缘层72，有源层73，源漏金属层(包括第一极74和第二级75)，第二绝缘层76和第二栅极77；所述有源层73在所述基底70上的正投影与所述第一栅极71在所述基底70上的正投影至少部分交叠，所述有源层73在所述基底70上的正投影与所述第二栅极77在所述基底70上的正投影至少部分交叠；所述源漏金属层形成晶体管的第一极74和第二极75，该第一极74和第二极75分别与所述有源层搭接。
示例性的，所述第一绝缘层包括栅极绝缘层，所述第二绝缘层包括钝化绝缘层。
示例性的，所述第一极和所述第二极中的一个作为源极，所述第一极和所述第二极中的另一个作为漏极。
示例性的，双栅晶体管中也可以设置刻蚀阻挡层，刻蚀阻挡层的一部分可以设置于源漏金属层和有源层之间，另一部分覆盖所述有源层没有与源漏金属层搭接的部分。
示例性的，所述双栅晶体管可以为N型晶体管，P型晶体管或CMOS管等。
上述结构的双栅晶体管，当薄膜晶体管处于关闭状态时，顶栅输入低电压，双栅晶体管的Vth会变大，这样可以更好的关闭双栅晶体管，避免误打开的情况，并且可以减小漏电流。当双栅晶体管处于开态时，顶栅输入高电压，双栅晶体管的Vth会变小，这样双栅晶体管的开态电流会变大。因此，通过这种双栅技术，就可以根据晶体管的开关状态，动态的调整双栅晶体管的Vth，达到关闭更好，减少漏电流以及增加开态电流的目的。
本公开实施例还提供了一种显示基板的驱动方法，应用于上述实施例提 供的显示基板，所述驱动方法包括：
输入时段，输出时段和复位时段，第一双栅晶体管M1的第一栅极和第二栅极在下拉节点PD的控制下，控制所述第一双栅晶体管M1截止；
保持时段，所述第一双栅晶体管M1的第一栅极和第二栅极在下拉节点PD的控制下，控制所述第一双栅晶体管M1导通。
如图10所示，示例性的，每个驱动周期依次包括输入时段P1，输出时段P2，复位时段P3和保持时段P4。在输出时段P2驱动信号输出端输出与时钟信号相同的高电平。在复位时段P3时钟信号处于低电位，对驱动信号输出端输出的信号进行复位。
采用本公开实施例提供的驱动方法驱动上述实施例提供的显示基板时，可以适时自动调节第一双栅晶体管M1的Vth，从而能够减少漏电流或增加开态电流。对触控时段内的停坑级，减少了第一双栅晶体管M1的漏电流，提升了GOA电路的可靠性，并对施加在第一双栅晶体管M1上的Vgs正电压容忍范围得到了提升；而对于触控时段内的非停坑级和非触控时段，对于正常工作时上拉节点PU为低电压的移位寄存器单元而言，则是增加了第一双栅晶体管M1的开态电流，从而使第一双栅晶体管M1对上拉节点PU的维持更好。
因此，采用本公开实施例提供的驱动方法驱动上述实施例提供的显示基板时，在上拉节点PU为高电压，下拉节点PD为低电压时，第一双栅晶体管M1的Vth能够正向漂移。对触控时段内的停坑级而言，上拉节点PU上存储的电荷通过第一双栅晶体管M1漏掉的会减少，保证了停坑结束后移位寄存器单元能够继续正常工作。
在一些实施例中，移位寄存器单元还包括输出控制子电路20，所述输出控制子电路20包括第二双栅晶体管M2，所述第二双栅晶体管M2的第一栅极和所述第二双栅晶体管M2的第二栅极分别与上拉节点PU耦接，所述第二双栅晶体管M2的第一极与对应的时钟信号输入端耦接，所述第二双栅晶体管M2的第二极与栅极驱动电路的驱动信号输出端Gout耦接；所述驱动方法还包括：
在输入时段，输出时段和复位时段，第二双栅晶体管的第一栅极和第二栅极在上拉节点的控制下，控制所述第二双栅晶体管导通；
在保持时段，第二双栅晶体管的第一栅极和第二栅极在上拉节点的控制下，控制所述第二双栅晶体管截止。
当上拉节点PU是高电压时，第二双栅晶体管M2的第一栅极和第二栅极在上拉节点PU的控制下，控制所述第二双栅晶体管M2导通；当上拉节点PU为低电压时，第二双栅晶体管M2的第一栅极和第二栅极在上拉节点PU的控制下，控制所述第二双栅晶体管M2截止。
采用上述实施例提供的驱动方法驱动显示基板时，第二双栅晶体管M2顶栅接入上拉节点PU信号，当上拉节点PU为低电压时，可以大大提升第二双栅晶体管M2对上拉节点PU ripple的容忍度，提高了GOA电路的可靠性；而当上拉节点PU为高电压时，可以增加第二双栅晶体管M2的输出电流，减小栅极驱动信号的上升和下降时间。
在一些实施例中，所述显示基板包括多条栅线GA，多条数据线DA和多个子像素，所述子像素包括像素电路和像素电极，所述像素电路包括像素双栅晶体管T1，所述像素双栅晶体管T1的第一栅极和所述像素双栅晶体管T1的第二栅极分别与对应的栅线GA耦接，所述像素双栅晶体管T1的第一极与对应的数据线DA耦接，所述像素双栅晶体管T1的第二极与所述像素电极耦接；所述驱动方法还包括：
像素驱动时段，像素双栅晶体管T1的第一栅极和第二栅极在对应的栅线GA的控制下，控制所述像素双栅晶体管T1导通，向像素电极写入数据信号；
非像素驱动时段，像素双栅晶体管T1的第一栅极和第二栅极在对应的栅线GA的控制下，控制所述像素双栅晶体管T1截止，停止向像素电极写入数据信号。
采用上述实施例提供的驱动方法驱动显示基板时，像素双栅晶体管T1顶栅接入栅极输出信号，当栅极驱动信号为高电压时，能使像素双栅晶体管T1电流增大，更好的保证像素充电率。而当栅极驱动信号为低电压时，能使像素双栅晶体管T1更好的关闭，避免充入错误数据信号。而且当栅极驱动信号为低电压时，像素双栅晶体管T1的Vth变大，对栅极驱动信号产生的ripple容忍度变高，不容易误打开，充入错误的数据信号。
本公开实施例还提供了一种显示面板，包括上述实施例提供的显示基板。
示例性的，上述显示面板包括液晶显示面板和有机发光二极管显示面板，但不仅限于此。
上述实施例提供的显示基板中，在上拉节点为高电压，下拉节点为低电压时，第一双栅晶体管的Vth能够正向漂移。对触控时段内的停坑级而言，上拉节点上存储的电荷通过第一双栅晶体管漏掉的会减少，保证了停坑结束后移位寄存器单元能够继续正常工作。
上述实施例提供的显示基板中，第二双栅晶体管顶栅接入上拉节点信号，当上拉节点为低电压时，可以大大提升第二双栅晶体管对上拉节点ripple的容忍度，提高了GOA电路的可靠性；而当上拉节点为高电压时，可以增加第二双栅晶体管的输出电流，减小栅极驱动信号的上升和下降时间。
上述实施例提供的显示基板中，像素双栅晶体管顶栅接入栅极输出信号，当栅极驱动信号为高电压时，能使像素双栅晶体管电流增大，更好的保证像素充电率。而当栅极驱动信号为低电压时，能使像素双栅晶体管更好的关闭，避免充入错误数据信号。而且当栅极驱动信号为低电压时，像素双栅晶体管的Vth变大，对栅极驱动信号产生的ripple容忍度变高，不容易误打开，充入错误的数据信号。
因此，本公开实施例提供的显示面板在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
在一些实施例中，所述显示面板还包括对向基板和液晶层，所述对向基板与所述显示基板相对设置，所述液晶层位于所述对向基板和所述显示基板之间。
需要说明的是，所述显示面板可以应用于：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示显示面板还可以与柔性电路板、印刷电路板和背板等结合使用。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续 的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示基板，包括栅极驱动电路，所述栅极驱动电路包括多个移位寄存器单元，所述移位寄存器单元包括上拉节点，下拉节点和上拉控制子电路；所述上拉控制子电路包括：
    第一双栅晶体管，所述第一双栅晶体管的第一栅极和所述第一双栅晶体管的第二栅极分别与所述下拉节点耦接，所述第一双栅晶体管的第一极与所述上拉节点耦接，所述第一双栅晶体管的第二极与第一电平信号输入端耦接。
  2. 根据权利要求1所述的显示基板，其中，所述移位寄存器单元还包括输出控制子电路，所述输出控制子电路包括第二双栅晶体管，所述第二双栅晶体管的第一栅极和所述第二双栅晶体管的第二栅极分别与所述上拉节点耦接，所述第二双栅晶体管的第一极与对应的时钟信号输入端耦接，所述第二双栅晶体管的第二极与所述移位寄存器单元的驱动信号输出端耦接。
  3. 根据权利要求1所述的显示基板，其中，所述移位寄存器单元还包括：
    输出复位子电路，所述输出复位子电路分别与所述下拉节点，所述栅极驱动电路的驱动信号输出端，以及所述第一电平信号输入端耦接，所述输出复位子电路用于在所述下拉节点的控制下，控制导通或断开所述驱动信号输出端与所述第一电平信号输入端之间的电连接；
    存储子电路，所述存储子电路的第一端与所述上拉节点耦接，所述存储电容的第二端与所述驱动信号输出端耦接。
  4. 根据权利要求1所述的显示基板，其中，所述移位寄存器单元还包括：下拉控制子电路，所述下拉控制子电路分别与所述上拉节点，所述下拉节点，所述第一电平信号输入端和第二电平信号输入端耦接，所述下拉控制子电路用于在所述上拉节点的控制下，控制导通或断开所述下拉节点与所述第一电平信号输入端之间的电连接，还用于在所述第二电平信号输入端的控制下，控制导通或断开所述下拉节点与所述第二电平信号输入端之间的电连接。
  5. 根据权利要求1所述的显示基板，其中，所述移位寄存器单元还包括：
    输入子电路，所述输入子电路分别与输入控制端，输入信号端和所述上拉节点耦接，所述输入子电路用于在所述输入控制端的控制下，控制导通或 断开所述输入信号端与所述上拉节点之间的电连接。
  6. 根据权利要求3所述的显示基板，其中，
    所述输出复位子电路包括第三晶体管，所述第三晶体管的栅极与所述下拉节点耦接，所述第三晶体管的第一极与所述驱动信号输出端耦接，所述第三晶体管的第二极与所述第一电平信号输入端耦接；
    所述存储子电路包括存储电容，所述存储电容的第一端与所述上拉节点耦接，所述存储电容的第二端与所述驱动信号输出端耦接。
  7. 根据权利要求4所述的显示基板，其中，所述下拉控制子电路包括第四晶体管和第五晶体管，所述第四晶体管的栅极和所述第四晶体管的第一极均与所述第二电平信号输入端耦接，所述第四晶体管的第二极与所述下拉节点耦接；所述第五晶体管的栅极所述上拉节点耦接，所述第五晶体管的第一极与所述下拉节点耦接，所述第五晶体管的第二极与所述第一电平信号输入端耦接。
  8. 根据权利要求5所述的显示基板，其中，所述输入子电路包括第六晶体管，所述第六晶体管的栅极与所述输入控制端耦接，所述第六晶体管的第一极与所述输入信号端耦接，所述第六晶体管的第二极与所述上拉节点耦接。
  9. 根据权利要求1所述的显示基板，其中，所述显示基板包括多条栅线，多条数据线和多个子像素，所述子像素包括像素电路和像素电极，所述像素电路包括像素双栅晶体管，所述像素双栅晶体管的第一栅极和所述像素双栅晶体管的第二栅极分别与对应的栅线耦接，所述像素双栅晶体管的第一极与对应的数据线耦接，所述像素双栅晶体管的第二极与所述像素电极耦接。
  10. 根据权利要求1、2或9中任一项所述的显示基板，其中，第一双栅晶体管，第二双栅晶体管和像素双栅晶体管采用如下结构：
    沿远离显示基板的基底的方向依次层叠设置的第一栅极，第一绝缘层，有源层，源漏金属层，第二绝缘层和第二栅极；所述有源层在所述基底上的正投影分别与所述第一栅极在所述基底上的正投影和所述第二栅极在所述基底上的正投影至少部分交叠；所述源漏金属层形成晶体管的第一极和第二极，该第一极和第二极分别与所述有源层搭接。
  11. 一种显示基板的驱动方法，应用于如权利要求1～10中任一项所述的 显示基板，所述驱动方法包括：
    输入时段，输出时段和复位时段，第一双栅晶体管的第一栅极和第二栅极在下拉节点的控制下，控制所述第一双栅晶体管截止；
    保持时段，所述第一双栅晶体管的第一栅极和第二栅极在下拉节点的控制下，控制所述第一双栅晶体管导通。
  12. 根据权利要求11所述的显示基板的驱动方法，其中，移位寄存器单元还包括输出控制子电路，所述输出控制子电路包括第二双栅晶体管，所述第二双栅晶体管的第一栅极和所述第二双栅晶体管的第二栅极分别与上拉节点耦接，所述第二双栅晶体管的第一极与对应的时钟信号输入端耦接，所述第二双栅晶体管的第二极与栅极驱动电路的驱动信号输出端耦接；所述驱动方法还包括：
    在输入时段，输出时段和复位时段，第二双栅晶体管的第一栅极和第二栅极在上拉节点的控制下，控制所述第二双栅晶体管导通；
    在保持时段，第二双栅晶体管的第一栅极和第二栅极在上拉节点的控制下，控制所述第二双栅晶体管截止。
  13. 根据权利要求11所述的显示基板的驱动方法，其中，所述显示基板包括多条栅线，多条数据线和多个子像素，所述子像素包括像素电路和像素电极，所述像素电路包括像素双栅晶体管，所述像素双栅晶体管的第一栅极和所述像素双栅晶体管的第二栅极分别与对应的栅线耦接，所述像素双栅晶体管的第一极与对应的数据线耦接，所述像素双栅晶体管的第二极与所述像素电极耦接；所述驱动方法还包括：
    像素驱动时段，像素双栅晶体管的第一栅极和第二栅极在对应的栅线的控制下，控制所述像素双栅晶体管导通；
    非像素驱动时段，像素双栅晶体管的第一栅极和第二栅极在对应的栅线的控制下，控制所述像素双栅晶体管截止。
  14. 一种显示面板，包括如权利要求1～10中任一项所述的显示基板。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括对向基板和液晶层，所述对向基板与所述显示基板相对设置，所述液晶层位于所述对向基板和所述显示基板之间。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013725A (zh) * 2006-07-10 2007-08-08 友达光电股份有限公司 双栅极晶体管及应用此双栅极晶体管的像素结构
JP2008191517A (ja) * 2007-02-07 2008-08-21 Seiko Epson Corp 電気光学装置用基板及び電気光学装置、並びに電子機器
US20100231492A1 (en) * 2008-10-10 2010-09-16 Kyo Ho Moon Liquid crystal display device
CN103236245A (zh) * 2013-04-27 2013-08-07 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN104732935A (zh) * 2015-02-10 2015-06-24 昆山龙腾光电有限公司 一种栅极驱动单元及使用其的显示装置
CN109427310A (zh) * 2017-08-31 2019-03-05 京东方科技集团股份有限公司 移位寄存器单元、驱动装置、显示装置以及驱动方法
CN113053447A (zh) * 2021-03-16 2021-06-29 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013725A (zh) * 2006-07-10 2007-08-08 友达光电股份有限公司 双栅极晶体管及应用此双栅极晶体管的像素结构
JP2008191517A (ja) * 2007-02-07 2008-08-21 Seiko Epson Corp 電気光学装置用基板及び電気光学装置、並びに電子機器
US20100231492A1 (en) * 2008-10-10 2010-09-16 Kyo Ho Moon Liquid crystal display device
CN103236245A (zh) * 2013-04-27 2013-08-07 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN104732935A (zh) * 2015-02-10 2015-06-24 昆山龙腾光电有限公司 一种栅极驱动单元及使用其的显示装置
CN109427310A (zh) * 2017-08-31 2019-03-05 京东方科技集团股份有限公司 移位寄存器单元、驱动装置、显示装置以及驱动方法
CN113053447A (zh) * 2021-03-16 2021-06-29 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

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