WO2023108527A1 - Pixel soi-jfet et son procédé de fabrication - Google Patents

Pixel soi-jfet et son procédé de fabrication Download PDF

Info

Publication number
WO2023108527A1
WO2023108527A1 PCT/CN2021/138692 CN2021138692W WO2023108527A1 WO 2023108527 A1 WO2023108527 A1 WO 2023108527A1 CN 2021138692 W CN2021138692 W CN 2021138692W WO 2023108527 A1 WO2023108527 A1 WO 2023108527A1
Authority
WO
WIPO (PCT)
Prior art keywords
jfet
layer
photodiode
region
buried oxide
Prior art date
Application number
PCT/CN2021/138692
Other languages
English (en)
Inventor
Hidekazu Takahashi
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to CN202180096519.2A priority Critical patent/CN117203774A/zh
Priority to PCT/CN2021/138692 priority patent/WO2023108527A1/fr
Publication of WO2023108527A1 publication Critical patent/WO2023108527A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14679—Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8086—Thin film JFET's

Definitions

  • the present invention relates to an SOI-JFET pixel and a method of fabricating the same.
  • CMOS image sensors CIS
  • Conventional CISs operate according to a method comprising a step of storing charges caused by photoelectron conversion in a photodiode for a certain period, and a step of amplifying and reading out the charges by an in-pixel source follower amplifier. Due to a dark current caused in the storage period and thermal noise and RTS (Random Telegraph Signal) noise in the in-pixel source follower amplifier additionally caused during reading out, the output includes noises having a level of several electrons with respect to an input. Furthermore, due to the pixel size reduction, it is difficult to keep saturation charges at a sufficient level.
  • the photon counting may allow further pixel size reduction, improvement of a signal to noise ratio, and increase in a dynamic range.
  • SPAD photon avalanche diode
  • ToF Time of Flight
  • SPADs generally have a large pixel size and require a large electric field to cause the charge avalanche, which results in a great number of white spots. Therefore, there is difficulty in applying SPADs to image sensors.
  • a device referred to as JOT has been proposed for application to image sensors.
  • a JOT reduces a capacitance of an photoelectron conversion portion of a pixel to one-third or less of a CIS, and increases an photoelectron conversion coefficient.
  • the small capacity of the JOT reduces the noise of the pixel to sub- electron level.
  • a JFET Joint Field Effect Transistor
  • a gate of a transistor of a JFET has a p-n junction. Since JFET does not comprise an oxide film as MOSFET, the JFET has a small input capacity, and therefore advantageously reduces 1/f noise and RTS noise. Therefore, the JFET may provide a noise level lower than that of a MOSFET.
  • LBCAST is known as an implemented JFET type image sensor (Japanese Unexamined Patent Application, First Publication No. H11-177076) .
  • Figure 9 (A) and 9 (B) show a planar diagram and a cross-sectional diagram of such an LBCAST device 801, respectively.
  • the LBCAST device 801 comprises a photodiode 812, a JFET 816, a transfer gate 816, and a reset device including a reset gate 830 and a reset drain 840. Charges caused by photoelectron conversion in the photodiode 812 are transferred to a gate 826 when the transfer gate 816 is turned on.
  • the transferred charges vary the electric potential of the gate 826, and therefore output of the JFET 816 from a source region 820 to a drain region 822 and to a vertical signal line 836 is changed.
  • the JFET 816 has a channel region 824 in the substrate horizontally interposed between the gates 826.
  • JFET size reduction of a JFET is more difficult than a MOSFET due to process precision and variation.
  • the JFET requires a layout area larger than the MOSFET, and there is a difficulty in implementing a pixel having a dimension of 1 ⁇ m or smaller. Improvement of a conversion gain by further reducing an input capacity is required in order to increase the precision of the photon counting. Therefore, new technical development is required.
  • a photon counting sensor using a conventional JFET has technical problems such as large element size, and large capacitance due to the size.
  • the size of an element limits pixel size reduction to a sub-micron level. In order to increase a conversion gain, an input capacity has to be reduced. Therefore, a large element size makes noise reduction difficult.
  • the object of the present invention is a photon counting imaging sensor having sub-micron size pixels and realizing noise reduction by miniaturizing a JFET.
  • a first embodiment of the present invention provides a pixel structure comprising:
  • an SOI (Silicon on Insulator) substrate comprising:
  • a buried oxide layer covering a part of the base layer and comprising an aperture
  • an SOI layer covering at least a part of a second surface of the buried oxide layer opposite to a first surface of the buried oxide layer contacting with the base layer, the SOI layer being electrically coupled to the base layer;
  • the photodiode comprising:
  • a transfer gate disposed such that the transfer gate overlaps with at least a part of the second portion of the photodiode in a plan view and such that an insulation film is interposed between the transfer gate and the second portion of the photodiode;
  • the JFET comprising:
  • a gate region having a portion covering at least a part of the channel region and a portion disposed on a side of the channel region closer to the second portion of the photodiode
  • the JFET is disposed through the buried oxide layer to face the first portion of the photodiode
  • the pixel structure according to the first embodiment comprises the JFET formed in the SOI layer, the pixel is significantly miniaturized compared with the prior art, which results in reducing the parasitic capacitance and further improving the conversion gain.
  • the base layer may be electrically coupled to the SOI layer by contacting each other in the aperture of the buried oxide layer. There is no need to fabricate any vias, which results in simplifying the structure.
  • At least a part of the second portion of the photodiode may extend into the SOI layer. Charges generated by the photoelectron conversion are effectively transferred to the floating diffusion region.
  • the base layer may be separated from the SOI layer
  • the base layer may comprise a floating diffusion region disposed between the buried oxide layer and the photodiode,
  • the buried oxide layer may comprise a via electrically coupling the gate region and the floating diffusion region, and
  • the base layer may be electrically coupled with the SOI layer by the via.
  • the via can be formed by a known fabrication process.
  • the reset element may comprise a MOS transistor.
  • the MOS transistor can be formed by a known fabrication process.
  • the reset element may comprise a punch-through element.
  • the punch-through element can significantly reduce the small input capacity and therefore reduce 1/f noise and RTS noise.
  • the JFET may be shared with at least one adjacent solid-state imaging device.
  • the footprint of the JFET is reduced, which results in the miniaturization of the pixel structure.
  • the JFET may further comprise an additional gate region disposed opposite to the gate region with respect to the channel region in a plan view.
  • the input capacity and therefore the 1/f noise and the RTS noise can be further reduced.
  • a second embodiment of the present invention provides a method for manufacturing a pixel structure, comprising the steps of:
  • doping the base layer to form a photodiode comprising a first portion covered by the buried oxide layer and a second portion disposed in the aperture;
  • the JFET comprises:
  • a gate region having a portion covering at least a part of the channel region and a portion disposed on a side of the channel region closer to the second portion of the photodiode;
  • the pixel structure fabricated by the method according to the second embodiment comprises the JFET formed in the SOI layer, the pixel is significantly miniaturized compared with the prior art, which results in reducing the parasitic capacitance and further improving the conversion gain.
  • forming the electric coupling structure may comprise depositing the same material as materials of the SOI layer and the base layer to cover the base layer exposed in the aperture and to contact with the SOI layer. There is no need to fabricate any vias, which results in simplifying the structure.
  • forming the electric coupling structure may further comprise doping the electric coupling structure to extend at least a part of the second portion of the photodiode into the SOI layer. Charges generated by the photoelectron conversion are effectively transferred to the floating diffusion region.
  • forming the photodiode may comprise forming a floating diffusion region between the buried oxide layer and the first portion of the photodiode by doping, and
  • forming the electric coupling structure may comprise forming a via in the buried oxide layer, the via electrically contacting the floating diffusion region and the gate region in a plan view.
  • the via can be formed by a known fabrication process.
  • the reset element may comprise a MOS transistor.
  • the MOS transistor can be formed by a known fabrication process.
  • the reset element comprises a punch-through element.
  • the punch-through element can significantly reduce the small input capacity and therefore reduce 1/f noise and RTS noise.
  • the JFET is shared with at least one adjacent solid-state imaging device.
  • the footprint of the JFET is reduced, which results in the miniaturization of the pixel structure.
  • the JFET may further comprise an additional gate region disposed opposite to the gate region with respect to the channel region in a plan view.
  • the input capacity and therefore the 1/f noise and the RTS noise can be further reduced.
  • Figure 1 shows a cross-sectional diagram of a JFET pixel according to one embodiment of the present invention.
  • Figure 2 shows an expanded plan view diagram of the JFET pixel shown in Figure 1.
  • Figure 3 shows a circuit diagram of the JFET pixel shown in Figures 1 and 2.
  • Figure 4 shows a flow chart of the method of operating the JFET pixel shown in Figures 1 to 3.
  • Figure 5 shows a cross-sectional diagram of the JFET pixel according to another embodiment of the present invention.
  • Figure 6 shows an expanded plan view of the JFET pixel shown in Figure 4.
  • Figure 7 shows an expanded plan view of a JFET pixel according to some embodiments of the present invention.
  • Figure 8 shows a method for fabricating a JFET pixel according to some embodiments of the present invention.
  • Figure 9 shows a conventional JFET pixel.
  • FIG. 1 shows a cross-sectional diagram of a pixel structure of a JFET pixel 1 according to one embodiment of the present invention.
  • Figure 2 shows an expanded plan view of a JFET 18 of the JFET pixel 1 shown in Figure 1.
  • the JFET pixel 1 comprises an SOI (silicon on insulator) substrate 10 comprising: a base layer 2 which comprises a semiconductor material, preferably silicon; a BOX (buried oxide) layer 4 covering a part of the base layer 2 and having an aperture 8; and an SOI layer 6 covering at least a part of a second surface 4-2 of the BOX layer 4 opposite to a first surface 4-1 contacting the base layer 2, and comprising a semiconductor material, preferably silicon.
  • SOI silicon on insulator
  • the base layer 2 may be electrically coupled to the SOI layer 6 by contacting the SOI layer 6 in the aperture 8. This electric coupling may be provided by, for example, depositing the same material as the material of the base layer 2 and the SOI layer 6 in the aperture 8.
  • the base layer 2 and the SOI layer 6 may be, for example, p-type doped.
  • a photodiode 12 may be disposed in the SOI layer 6.
  • the photodiode 12 may comprise a first portion 12-1 facing the first surface 4-1 of the BOX layer 4, and a second portion 12-2 disposed in the aperture 8. At least a part of the second portion 12-2 may be, for example, extended to the SOI layer 6 via the aperture 8.
  • the photodiode 12 may be, for example, n-type doped.
  • the photodiode 12 may be, for example, a depleted type deep photodiode extending from a side of the base layer 2 closed to the BOX layer 4 to the opposite side of the base layer 2.
  • a transfer gate 16 may be disposed over the SOI layer 6 such that at least a part of the transfer gate 16 overlaps the second part 12-2 of the photodiode 12 in a plan view via an insulation film 14.
  • a JFET 18 may be disposed in the SOI layer 6 facing the first portion 12-1 of the photodiode 12 via the BOX layer 4.
  • the JFET 18 may comprise: a source region 20; a drain region 22; a channel region 24 disposed between the source region 20 and the drain region 22; and a gate region 26 having a portion at least partially covering the channel region 24 and a portion disposed on a side of the channel region 24 closer to the second portion 12-2 of the photodiode 12.
  • the JFET 18 may also function as a source follower device. At least a part of the transfer gate 16 may also function as a floating diffusion region 28.
  • a reset device 30 may be disposed in the SOI layer 6 and adjacent to a side of the JFET 18 opposite to the side on which the gate region 26 is disposed, with respect to the channel region.
  • the source region 20 and the drain region 22 may be, for example, p+ doped.
  • the gate region 26 and the reset element 30 may be, for example, n+ doped.
  • the JFET pixel 1 may comprise a row select transistor 33 of which a drain is coupled to the source region 20 of the JFET 18.
  • the reset element 30 may be, for example, a MOS transistor. Alternatively, the reset element 30 may be a punch through element.
  • a DTI (deep trench isolation) 32 providing an isolation from adjacent JFET pixels may be disposed at a periphery of the JFET pixel 1.
  • the DTI 32 may be a trench at least partially surrounding the JFET pixel 1 and filled with an insulation material.
  • the DTI 32 may extend across a part of or the entire thickness of the SOI substrate 10.
  • FIG 3 shows a circuit diagram of the JFET imaging element 1 shown in Figures 1 and 2.
  • the photodiode 12 may be coupled to the floating diffusion region 28 via the transfer gate 16.
  • the floating diffusion region 28 may also be the gate region 26 of the JFET 18 which is a source follower device as described above.
  • the source region 20 of the JFET 18 may be coupled to a drain of the row select transistor 33.
  • a source of the row select transistor 33 may be coupled to a constant current supply 34.
  • the constant current supply 34 may be coupled to a column output line 36.
  • a reset drain of the reset element 30 may be coupled to the floating diffusion region 28.
  • a source of the reset device 30 may be, for example, coupled to a device power source.
  • FIG. 1 shows the flow chart of the method of operating the JFET pixel 1.
  • the transfer gate 16 When light impinges on the photodiode 12, charges are caused by photoelectron conversion. The charges may be stored in the photodiode 12.
  • the transfer gate 16 When the transfer gate 16 is turned on, the charges may be transferred from the photodiode 12 to the floating diffusion region 28. Since the floating diffusion region 28 may also be the gate region 26 of the JFET 18, the transferred charges may affect the electric potential of the gate region 26.
  • the row select transistor 33 is turned on, charges flowing through the JFET 18 may be varied in response to the electric potential of the gate region 26. Thus, charges output to the column output line 36 may also be varied.
  • the transferred charges are gained by the JFET 18 through the change of the electric potential of the gate region 26, and the output to the column output line 36 is affected. Therefore, the amount of the charges caused by the photoelectron conversion, i.e., the amount of light impinging the photodiode 12 may be detected by measuring the output voltage of the column output line 36. After the measurement is finished, the reset element 30 may be turned on to reset the floating diffusion region 28 by applying the voltage, which is, for example, the device power source VDD.
  • the JFET imaging element 1 shown in Figures 1 to 3 comprises a JFET formed in the SOI layer instead of forming a JFET in a bulk Si as in the prior art. Forming a JFET in an SOI layer may allow significant size reduction compared with the prior art. The size reduction of the JFET leads to a small parasitic capacitance, and further improvement of a conversion gain.
  • the JFET may be a p-channel type or an n-channel type depending on a conductive type of the substrate.
  • the operation method of the JFET pixel 1 may be implemented at the same timing as conventional imaging devices. Since the JFET 18 is an SOI device, a voltage for driving the JFET 18 may be reduced compared to the prior art. Therefore, the embodiment of the present invention may provide an imaging device having a small size, a low noise, and a high sensitivity compared to devices in the prior art. As a result, the noise level becomes significantly lower than one-electron level, and a photon counting device, which can detect one photon, may be provided as a sub-micron pixel.
  • the JFET 18 may be shared with at least one adjacent photodiodes.
  • one JFET 18 may also be coupled to the photodiode of the adjacent imaging device via a transfer gate.
  • a photodiode, of which charges are to be transferred to the JFET 18, may be selected by selecting the transfer gate to be turned on.
  • the JFET 18 may be disposed at a midpoint between two imaging pixels and may be coupled to the photodiodes of the two imaging devices. Therefore, a two-shared pixel may be provided.
  • the JFET 18 may be disposed at a midpoint of four photodiodes to provide a four-shared pixel.
  • the number of the imaging devices coupled to one JFET 18 may not be limited to 2 and 4.
  • Figure 5 shows a cross-sectional diagram of a JFET pixel 101 according to a second embodiment of the present invention.
  • Figure 6 shows an expanded plan view of a JFET 118 of the JFET pixel 101 shown in Figure 5.
  • the base layer 2 and the SOI layer 6 of the JFET pixel 101 are separated from each other, and are not in contact with each other. Instead, a via 138 is disposed in the BOX layer 4.
  • the via 138 may be a conductive layer such as metal filled in a through hole provided in the BOX layer 4.
  • the base layer 2 may be electrically coupled to the SOI layer 6 through the via 138.
  • a floating diffusion region 140 may be formed in the base layer 2, for example, by doping such that the floating diffusion region 140 contacts the via 138.
  • a gate region 126 of the JFET 118 is formed to contact the via 138. Therefore, the floating diffusion region 140 is coupled to the gate region 126.
  • a transfer gate 116 is formed in the aperture 8 via an insulation film 114.
  • the JFET pixel 101 having such a configuration has the floating diffusion region 140 and the gate region 126 aligned in a vertical direction. Therefore, the pixel may be further miniaturized.
  • FIG 7 shows an extended plan view of a JFET 218 of a JFET pixel 201 according to a third embodiment of the present invention.
  • the JFET 218 of the JFET pixel 201 is different from the JFET 18 of the JFET pixel 1 shown in Figure 1 because an additional gate region 242 is disposed on a side of the channel region 224 opposite to the side on which a gate region 226 is disposed in a plan view.
  • the other configurations of the JFET pixel 201 are similar to those of the JFET pixel 1 shown in Figure 1.
  • Figure 8 shows steps of a method 700 of fabricating a JFET pixel according to some embodiments of the present invention.
  • an SOI substrate 10 is provided.
  • the SOI substrate 10 comprises a base layer 2, an SOI layer 6, and a BOX layer 4 disposed between the base layer 2 and the SOI layer 6.
  • the base layer 2 and the SOI layer 6 may comprise a semiconductor material, for example, silicon.
  • the base layer 2 and the SOI layer 6 may be, for example, p-type doped.
  • a part of the SOI layer 6 and the BOX layer 4 are removed by, for example, known wet etching and/or dry etching to form an aperture 8 and to expose a part of the base layer 2.
  • the base layer 2 is doped to form a photodiode 12 comprising a first portion 12-1 covered by the BOX layer 4 and a second portion 12-2 disposed in the aperture 8.
  • an electric coupling structure for electrically coupling the base layer 2 and the SOI layer 6 is formed.
  • the electric coupling structure may be provided by depositing the same material as the base layer 2 and the SOI layer 6 in the aperture 8 to contact the base layer 2 and the SOI layer 6.
  • the deposited material of the electric coupling structure may be doped to extend the second portion 12-2 of the photodiode to the electric coupling structure.
  • a via 138 coupling the base layer 2 and the SOI layer 6 may be formed by forming a through hole in the BOX layer 4 and by filling the through hole with a conductive material such as metal to form the electric coupling structure.
  • a floating diffusion region 140 may be formed between the first portion 12-1 of the photodiode 12 and the BOX layer 4 by doping before or after the via 138 is formed.
  • a JFET 18 is formed in the SOI layer 6 to face the first portion 12-1 of the photodiode 12 via the BOX layer 4.
  • the JFET 18 comprises a source region 20, a drain region 22, a channel region 24 disposed between the source region 20 and the drain region 22, and a gate region 26 covering at least a part of the channel region 24 and disposed on a side of the channel region 24 closed to the second portion 12-2 of the photodiode 12.
  • a reset element 30 may be disposed in the SOI layer 6 and adjacent to the gate region of the JFET 18.
  • the JFET 18 and the reset device 30 may be formed by using conventional semiconductor processes.
  • an insulation film 14 is formed to cover at least the aperture 8 in a plan view.
  • a transfer gate 16 is formed on the insulation film 14 and at a position overlapping at least a part of the aperture 8 in a plan view, such that the transfer gate 16 overlaps at least a part of the second portion 12-2 of the photodiode 12 in a plan view to finally obtain the JFET pixel.
  • An image sensor comprising JFET pixels according to the present invention provides low noise, high sensitivity, and miniaturized pixels, which lead to image s having a high definition, a high SN ratio, and a wide dynamic range by the photon counting scheme.
  • An imaging system comprising JFET pixels according to the present invention provides clear images even under a low illumination condition, images having a wide dynamic range from low to high brightness, and high-definition images by increased pixels. If the system comprises the same number of pixels as prior art, the chip size can be miniaturized, which leads to a low cost and miniaturized camera.
  • An image sensor comprising JFET pixels according to the present invention can be applied to conventional CIS fields such as smartphones, mobile devices, cameras, security cameras, and automotive cameras. Further improvement of performance and cost reduction of the image sensors in these fields by the present invention may contribute to the market growth.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention concerne un dispositif d'imagerie à semi-conducteurs comprenant : un substrat SOI (silicium sur isolant) comprenant : une couche de base; une couche d'oxyde enfouie recouvrant une partie de la couche de base et comprenant une ouverture; et une couche SOI recouvrant au moins une partie d'une seconde surface de la couche d'oxyde enfouie opposée à une première surface de la couche d'oxyde enfouie en contact avec la couche de base, la couche SOI étant électriquement couplée à la couche de base; une photodiode dont au moins une partie est disposée dans la couche de base, la photodiode comprenant : une première partie faisant face à la première surface de la couche d'oxyde enfouie; et une seconde partie disposée dans l'ouverture de la couche d'oxyde enfouie; une grille de transfert disposée de telle sorte que la grille de transfert chevauche au moins une partie de la seconde partie de la photodiode dans une vue en plan et de telle sorte qu'un film d'isolation est interposé entre la grille de transfert et la seconde partie de la photodiode; un JFET disposé dans la couche SOI, le JFET comprenant : une région de source; une région de drain; une région de canal située entre la région de source et la région de drain; et une région de grille recouvrant au moins une partie de la région de canal et disposée sur un côté de la région de canal plus proche de la seconde partie de la photodiode, le JFET étant disposé à travers la couche d'oxyde enfouie pour faire face à la première partie de la photodiode; et un élément de réinitialisation disposé dans la couche SOI et adjacent à la région de grille du JFET.
PCT/CN2021/138692 2021-12-16 2021-12-16 Pixel soi-jfet et son procédé de fabrication WO2023108527A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180096519.2A CN117203774A (zh) 2021-12-16 2021-12-16 Soi-jfet像素及其制造方法
PCT/CN2021/138692 WO2023108527A1 (fr) 2021-12-16 2021-12-16 Pixel soi-jfet et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/138692 WO2023108527A1 (fr) 2021-12-16 2021-12-16 Pixel soi-jfet et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2023108527A1 true WO2023108527A1 (fr) 2023-06-22

Family

ID=86775048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/138692 WO2023108527A1 (fr) 2021-12-16 2021-12-16 Pixel soi-jfet et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN117203774A (fr)
WO (1) WO2023108527A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281531B1 (en) * 1997-10-23 2001-08-28 Nikon Corporation Solid picture element
US8072006B1 (en) * 2005-12-21 2011-12-06 American Semiconductor, Inc. Double-gated sensor cell
CN102326254A (zh) * 2008-11-04 2012-01-18 阵列光电子公司 用于所结合支持件上的超薄光电二极管阵列的器件和方法
US8319307B1 (en) * 2004-11-19 2012-11-27 Voxtel, Inc. Active pixel sensors with variable threshold reset
US20160150169A1 (en) * 2014-11-25 2016-05-26 Semiconductor Components Industries, Llc Image sensor pixels having p-channel source follower transistors and increased photodiode charge storage capacity

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281531B1 (en) * 1997-10-23 2001-08-28 Nikon Corporation Solid picture element
US8319307B1 (en) * 2004-11-19 2012-11-27 Voxtel, Inc. Active pixel sensors with variable threshold reset
US8072006B1 (en) * 2005-12-21 2011-12-06 American Semiconductor, Inc. Double-gated sensor cell
CN102326254A (zh) * 2008-11-04 2012-01-18 阵列光电子公司 用于所结合支持件上的超薄光电二极管阵列的器件和方法
US20160150169A1 (en) * 2014-11-25 2016-05-26 Semiconductor Components Industries, Llc Image sensor pixels having p-channel source follower transistors and increased photodiode charge storage capacity

Also Published As

Publication number Publication date
CN117203774A (zh) 2023-12-08

Similar Documents

Publication Publication Date Title
US8513761B2 (en) Backside illumination semiconductor image sensor
US7394056B2 (en) Image sensor having pinned floating diffusion diode
KR101683307B1 (ko) 고체 촬상 장치, 고체 촬상 장치의 제조 방법, 및 전자 기기
US8835981B2 (en) Solid-state image sensor
US7884401B2 (en) CMOS image sensor and manufacturing method thereof
US7235831B2 (en) Light-receiving element and photoelectric conversion device
US7855407B2 (en) CMOS image sensor and method for manufacturing the same
US7821046B2 (en) Methods, structures and sytems for an image sensor device for improving quantum efficiency of red pixels
CN103828052B (zh) 图像传感器的单位像素及其光电探测器
US11417691B2 (en) Image sensor including dummy patterns positioned between adjacent transfer gates
US11437416B2 (en) Pixel device layout to reduce pixel noise
US20180294300A1 (en) Image sensor and image-capturing device
JP2012147169A (ja) 固体撮像装置
US11552116B2 (en) Image sensors with multi-channel type transistors
US10276614B2 (en) Methods and apparatus for an image sensor with a multi-branch transistor
CN111564459B (zh) 图像感测装置及其形成方法
US20080017893A1 (en) Back-lit image sensor
CN116435323A (zh) Cmos图像传感器及其形成方法
WO2023108527A1 (fr) Pixel soi-jfet et son procédé de fabrication
US7994551B2 (en) Image sensor and method of fabricating the same
US20100297807A1 (en) Cmos imager having a nitride dielectric
US20190393253A1 (en) Image sensor
US20240194702A1 (en) Photodetection device and electronic device
US20230253438A1 (en) Image sensors
US20080048221A1 (en) Image sensor and manufacturing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21967662

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180096519.2

Country of ref document: CN