WO2023093585A1 - 授时信号转换的方法和装置、计算机可读介质 - Google Patents

授时信号转换的方法和装置、计算机可读介质 Download PDF

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Publication number
WO2023093585A1
WO2023093585A1 PCT/CN2022/132202 CN2022132202W WO2023093585A1 WO 2023093585 A1 WO2023093585 A1 WO 2023093585A1 CN 2022132202 W CN2022132202 W CN 2022132202W WO 2023093585 A1 WO2023093585 A1 WO 2023093585A1
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timing signal
signal
initial
format
1pps
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PCT/CN2022/132202
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English (en)
French (fr)
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朱小三
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Definitions

  • the present disclosure relates to but not limited to the technical field of time service.
  • the timing output of the modem (modem) chip in the CPE (customer pre-equipment) device of 5G (fifth generation mobile communication technology) is usually in the format of 1 pulse per second plus time of day (1PPS+TOD), but in the power terminal
  • the timing signal used is generally in the format of the remote communication working group B code (IRIG-B), so here it is necessary to convert the IRIG-B timing signal according to the 1PPS+TOD timing signal, which is used for the timing of the power terminal.
  • the disclosure provides a timing signal conversion method and device, and a computer-readable medium.
  • the present disclosure provides a method for converting a timing signal, which includes: a conversion unit obtains a second initial timing signal corresponding to the same time according to the first timing signal, and outputs the second initial timing signal; a logic OR gate receives The trigger signal of the first timing signal and the second initial timing signal, and output the second timing signal; wherein, the first timing signal has a first format, and the second initial timing signal and the second timing signal have a first format In the second format, the timing points of the trigger signal of the first timing signal, the second initial timing signal, and the second timing signal are all rising edges.
  • the present disclosure provides a timing signal conversion device, which includes: a conversion unit configured to obtain a second initial timing signal corresponding to the same time according to the first timing signal, and output the second initial timing signal; logic OR gate, configured to receive the trigger signal of the first timing signal and the second initial timing signal, and output the second timing signal; wherein, the first timing signal has a first format, the second initial timing signal, The second timing signal has a second format, and the timing points of the trigger signal of the first timing signal, the second initial timing signal, and the second timing signal are all rising edges thereof.
  • the present disclosure provides a computer-readable medium on which a computer program is stored, and when the computer program is executed by a processor, the processor is made to implement any timing signal conversion method described in the present disclosure.
  • Figure 1 is a schematic diagram of the format of different symbols in the IRIG-B timing signal
  • FIG. 2 is a flow chart of a method for timing signal conversion provided by the present disclosure
  • FIG. 3 is a flow chart of another method for timing signal conversion provided by the present disclosure.
  • FIG. 4 is a schematic diagram of a signal processing process of a timing signal conversion method provided by the present disclosure
  • FIG. 5 is a schematic diagram of a process of obtaining a second initial signal in another timing signal conversion method provided by the present disclosure
  • FIG. 6 is a block diagram of a timing signal conversion device provided by the present disclosure.
  • Fig. 7 is a composition block diagram of a computer-readable medium provided by the present disclosure.
  • the present disclosure may be described with reference to plan views and/or cross-sectional views by way of idealized schematic views of the present disclosure. Accordingly, the example illustrations may be modified according to manufacturing techniques and/or tolerances.
  • the terms used in the present disclosure are for describing specific embodiments only, and are not intended to limit the present disclosure.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise.
  • the terms “comprising”, “made up of” designate the presence of said features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, Integrals, steps, operations, elements, components and/or groups thereof.
  • the present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations formed based on manufacturing processes. Accordingly, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.
  • the format of the timing signal it is necessary to convert the format of the timing signal. For example, in the process of timing the power terminal, it may be necessary to convert the 1PPS+TOD timing signal into an IRIG-B timing signal.
  • 1PPS+TOD (1 Pulse Per Second+Time of Day) is the format of "1 pulse per second plus time of day", which includes the trigger signal as the basis of on time (On Time), and the time of day (TOD) representing the specific time Signal.
  • the sending period of the trigger signal is 1 second (1PPS), and its rising edge (starting edge) is the punctual point; while the TOD signal is sent 1ms after the punctual point of the trigger signal, which is used to represent the specific time.
  • punctual point is also called “punctual edge”
  • the moment when the timing point arrives is defined as the time represented by the timing signal. For example, if the time corresponding to a timing signal is 15:00:00, and its punctual point is the rising edge of the trigger signal, the device receiving the timing signal will think that the time is 15:00 when the rising edge of the trigger signal arrives. :00:00.
  • the IRIG-B (Inter Range Instrumentation Group-B) timing signal is in the format of "Telecommunication Working Group B Code", referred to as "B Code", which is timed once per second, and each timing signal (one frame signal) includes 100 pulses ( 100PPS), the rising edge of the first pulse is used as the punctual point, and the pulses of different bits are used to represent the second, ten seconds, minute, tenth, hour, ten o'clock, day, ten days, hundred days and other information of the time, and As an identification mark (P code), etc.
  • the total duration of each symbol is 10ms, and its meaning is determined by the pulse width (that is, the duty cycle of the symbol). As shown in Figure 1, a pulse width of 2ms represents a "0" code, and a pulse width of 5ms represents a "1" code. , pulse width 8ms means identification mark (P code).
  • the conversion of the signal will inevitably consume a certain amount of time, resulting in a delay in the converted timing signal compared to the original timing signal, that is, its time is not accurate, the precision is low, and it cannot meet the practical application of many scenarios (such as power differential protection scenarios). need.
  • the present disclosure provides a method for timing signal conversion.
  • the timing signal conversion method of the present disclosure is used to convert an input timing signal of one format into a timing signal of another format, and then output it; thus, the method can be used in the format of the original timing signal that can be obtained and the target device (such as power terminals) the required timing signal format does not match the situation.
  • the method for converting the timing signal of the present disclosure can be performed by a device for converting the timing signal.
  • the device for converting the timing signal can be an independent device specially used for conversion, or it can be connected with the equipment that generates the original timing signal (such as supporting 5G timing function) Power 5G CPE products, devices supporting GPS timing, etc.) or combined with target equipment (such as power terminals) that require converted timing signals.
  • the method of the present disclosure may include step S101 and step S102 .
  • step S101 the conversion unit obtains a second initial timing signal corresponding to the same time according to the first timing signal, and outputs the second initial timing signal.
  • step S102 the logical OR gate receives the trigger signal of the first timing signal and the second initial timing signal, and outputs the second timing signal.
  • the first timing signal has a first format
  • the second initial timing signal and the second timing signal have a second format
  • the trigger signal of the first timing signal, the second initial timing signal, and the punctual points of the second timing signal are its rising edge
  • the conversion unit of the device for timing signal conversion receives a timing signal of a format (first format), and converts it into another different format (second format), representing the timing signal of the same time (the second initial timing signal ); then the second initial timing signal and the trigger signal of the original first timing signal are input into a logical OR gate, and the output of the logical OR gate is used as the second timing signal finally converted.
  • the second initial timing signal (IRIG-B (initial) among Fig. 4) that converts must delay with respect to first timing signal (1PPS+TOD timing signal among Fig. 4), That is, the punctual point (On Time, rising edge) of the second initial timing signal is slightly later than the punctual point (rising edge) of the trigger signal of the first timing signal, and through the "or" operation, the final output of the second timing signal can be The punctual point (rising edge) of (IRIG-B (output) in Fig.
  • the second timing signal is synchronized with the punctual point of the trigger signal of the first timing signal, that is, "guarantee that the second timing signal obtained by the final conversion is consistent with the original first timing
  • the time represented by the second timing signal is the same as that of the first timing signal. Therefore, the second timing signal can accurately realize timing with high precision.
  • the pulse (symbol) width in the timing signal is at least millisecond (ms) level, and the conversion time is at most tens of microseconds ( ⁇ s), that is, the delay caused by the conversion must be much shorter than the code of the timing signal. Therefore, although the above "or" operation has changed the pulse width (duty cycle) of the first pulse of the second timing signal, it only affects the punctual point, and does not affect the actual expression of the symbol information.
  • the second initial timing signal in the second format is converted according to the first timing signal in the first format, but instead of outputting it directly, the second initial timing signal and the trigger signal of the first timing signal are input together Logical OR gate; and through the "OR" operation, it can be guaranteed that the punctual point of the output of the logical OR gate must be the same as the punctual point of the trigger signal of the first timing signal, which is equivalent to the second timing signal converted from the first timing signal "Advance" to synchronize with the first timing signal, thereby eliminating the delay of the second timing signal caused by the time-consuming conversion, ensuring that the first timing signal and the second timing signal are aligned in time, that is, ensuring the accuracy of the converted signal High ( ⁇ 1 ⁇ s), meeting the actual application requirements of various scenarios (such as power differential protection scenarios).
  • the conversion unit includes a micro control unit MCU.
  • the conversion unit may include a micro control unit (MCU, Micro Controller Unit), for example, the conversion unit may be a "single-chip microcomputer".
  • MCU Micro Control Unit
  • the conversion unit may be a "single-chip microcomputer”.
  • a Field Programmable Gate Array (FPGA, Field Programmable Gate Array) can be used to convert the timing signal.
  • the circuit board (PCB) of the above FPGA is large in size, high in cost and high in power consumption, making it difficult to realize practical application.
  • MCU Compared with FPGA, MCU has the advantages of low cost, low power consumption, small size, and practicality, but its conversion accuracy is usually lower.
  • the accuracy of the conversion of the MCU itself does not actually affect the accuracy of the second timing signal that is finally output.
  • the MCU is used As a conversion unit, it can realize timing signal conversion with low cost, low power consumption, small size and high precision.
  • the specific form of the conversion unit in the present disclosure is not limited to the MCU, for example, an FPGA can be used as the conversion unit.
  • the first format is 1PPS+TOD; the second format is IRIG-B; the trigger signal of the first timing signal is 1PPS signal.
  • this method can be used to convert the 1PPS+TOD timing signal into an IRIG-B timing signal; correspondingly, the first timing signal at this time is the 1PPS+TOD timing signal, and
  • the trigger signal is 1PPS signal, the second initial timing signal is IRIG-B (initial), and the second timing signal is IRIG-B (output).
  • the 1PPS+TOD timing signal and the IRIG-B timing signal are used as examples for illustration.
  • timing signal in the present disclosure is not limited thereto, and it is also used for conversion of timing signals in other formats (including but not limited to DCLS timing signals, NTP timing signals, PTP timing signals, etc.), as long as the timing point of the timing signal Just for the rising edge.
  • the conversion unit obtains the second initial timing signal corresponding to the same time according to the first timing signal, and outputs the second initial timing signal (S101) may include steps S1011 to S1013.
  • step S1011 the converting unit acquires the TOD signal and the 1PPS signal of the first timing signal.
  • step S1012 the conversion unit generates the information of the second initial timing signal according to the time corresponding to the TOD signal plus the preset duration, and stores it in the cache.
  • step S1013 the conversion unit responds to the rising edge of the 1PPS signal of a first timing signal, and obtains from the buffer memory the information of the second initial timing signal generated according to the first timing signal before the preset time length, so as to generate and output the second initial timing signal.
  • Initial timing signal the conversion unit responds to the rising edge of the 1PPS signal of a first timing signal, and obtains from the buffer memory the information of the second initial timing signal generated according to the first timing signal before the preset time length, so as to generate and output the second initial timing signal.
  • conversion unit can receive (as being carried out by TOD time information receiving module) the TOD signal in 1PPS+TOD timing signal (the first timing signal); Analyze afterwards (as being carried out by B code format conversion module) TOD signal Time, after adding the preset duration (for example, 1s) to the time, recode according to the obtained time (for example, the time of TOD signal is 15:00:00, then the time after adding 1s is 15:00:01) (such as BCD code ) obtain the information of the IRIG-B timing signal (the second initial timing signal) (such as the type of each symbol of the IRIG-B timing signal); and store the information of the IRIG-B timing signal in the cache; and when preset When the 1PPS signal (trigger signal) of the (as follows) 1PPS+TOD timing signal arrives after a long period of time, it can be triggered (for example, by the 1PPS trigger module) to read the information of the current IRIG-B timing signal in the cache
  • the TOD signal of the same timing signal itself is 1ms later than the 1PPS signal, and it takes a certain time to convert it to the second initial timing signal, that is, the actual generation time of the second initial timing signal (IRIG-B (initial)) must be It has a larger delay than the time represented by the directly corresponding TOD signal; therefore, in order to avoid the time difference between the second initial timing signal and the 1PPS signal being too large, the first code of the second timing signal obtained through the logical OR gate If the element deformation is too large and wrong, you can add the time corresponding to the TOD signal to the preset duration (such as 1s) before converting, and wait for the 1PPS signal after the preset duration (the following 1s 1PPS signal) to be triggered before outputting (because the 1PPS signal It must be one 1s, so such an output is still accurate).
  • the preset duration such as 1s
  • the above preset duration may be 1 second, and the signal before/after the corresponding preset duration is the previous/subsequent signal.
  • the information of the second initial timing signal is the PWM information of each pulse.
  • the IRIG-B timing signal pulse since the number and position (interval 10ms) of the IRIG-B timing signal pulse (symbol) are all determined, only the pulse width (such as 8ms, 5ms, 2ms) of each pulse is determined. ) to distinguish the meaning of the corresponding symbol, therefore, as long as the PWM (Pulse Width Modulation) information (such as duty cycle, or pulse width, etc.) of each pulse (symbol) is stored, it can represent the IRIG-B timing signal All signals of the system can reduce the amount of information to be stored and simplify the information format.
  • PWM Pulse Width Modulation
  • 100 duty cycle values corresponding to its 100 pulses can be sequentially stored in the cache, and the array of the 100 values is used as its corresponding information.
  • the timer of 10ms can be started, so that every 10ms from the cached array Read a value, generate and output a single pulse with corresponding pulse width according to the value.
  • the information of the second initial timing signal is in other forms or stored in other ways.
  • the preset duration is 1 second
  • the cache is a ping-pong cache.
  • the cache for storing information of the second initial timing signal may be a "ping-pong cache".
  • the ping-pong cache actually includes two buffer areas, namely, buffer1 and buffer2, when the information of the second initial timing signal is written to buffer1, the information of the second initial timing signal stored before can be read from buffer2 and A second initial timing signal is generated; and when the information of the second initial timing signal is written into buffer2, the previously stored information of the second initial timing signal can be read from buffer1 and the second initial timing signal is generated.
  • a read pointer and a write pointer can be set, and the two pointers point to buffer1 and buffer2 in turn, so as to perform read and write operations on buffer1 and buffer2 in turn.
  • the disclosed method can run well and output the second initial timing signal continuously and reliably.
  • the specific form of the cache in the embodiments of the present disclosure is not limited thereto, as long as the cache can realize the writing and reading of the information of the second initial timing signal in time.
  • the present disclosure provides a timing signal conversion device.
  • the device for converting the timing signal of the present disclosure is used to realize the above method for converting the timing signal.
  • the timing signal conversion device of the present disclosure may be an independent device specially used for conversion, and may also be combined with equipment that generates original timing signals (such as power 5G CPE products that support 5G timing functions, devices that support GPS timing, etc.) integrated, or integrated with target equipment (such as power terminals) that require converted timing signals.
  • equipment that generates original timing signals such as power 5G CPE products that support 5G timing functions, devices that support GPS timing, etc.
  • target equipment such as power terminals
  • the timing signal conversion device of the present disclosure includes: a conversion unit configured to obtain a second initial timing signal corresponding to the same time according to the first timing signal, and output the second initial timing signal; logic The OR gate is configured to receive the trigger signal of the first timing signal and the second initial timing signal, and output the second timing signal; wherein, the first timing signal has a first format, and the second initial timing signal and the second timing signal have a first format. In the second format, the trigger signal of the first timing signal, the punctual point of the second initial timing signal, and the second timing signal are all rising edges.
  • the conversion unit includes an MCU.
  • the first format is 1PPS+TOD; the second format is IRIG-B; the trigger signal of the first timing signal is 1PPS signal.
  • the present disclosure provides a computer-readable medium on which a computer program is stored.
  • the processor implements the timing signal conversion method in any embodiment of the present disclosure.
  • the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute.
  • Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as ASIC.
  • a processor such as a central processing unit (CPU), digital signal processor, or microprocessor
  • Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
  • Computer storage media include but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage ; compact disc read-only (CD-ROM), digital versatile disc (DVD) or other optical disk storage; magnetic cartridge, magnetic tape, magnetic disk storage or other magnetic storage; any other which can be used to store desired information and which can be accessed by a computer medium.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

本公开提供了一种授时信号转换的方法，该方法包括：转换单元根据第一授时信号得到对应相同时间的第二初始授时信号，并输出所述第二初始授时信号；逻辑或门接收所述第一授时信号的触发信号和第二初始授时信号，并输出第二授时信号；其中，所述第一授时信号具有第一格式，所述第二初始授时信号、第二授时信号具有第二格式，所述第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。本公开还提供了一种授时信号转换的装置、计算机可读介质。

Description

授时信号转换的方法和装置、计算机可读介质
相关申请的交叉引用
本申请要求2021年11月24日提交给中国专利局的第202111403539.8号专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开涉及但不限于授时技术领域。
背景技术
很多情况下，对授时信号的格式进行转换是必要的。例如，5G(第五代移动通信技术)的CPE(客户前置设备)设备中的modem(调制解调器)芯片的授时输出通常为每秒1脉冲加日时间(1PPS+TOD)格式，但在电力终端使用的被授时信号一般为远程通信工作组B码(IRIG-B)格式，故此处就需要根据1PPS+TOD授时信号转换得到IRIG-B授时信号，用于电力终端的授时。
发明内容
本公开提供一种授时信号转换的方法和装置、计算机可读介质。
第一方面，本公开提供一种授时信号转换的方法，其包括：转换单元根据第一授时信号得到对应相同时间的第二初始授时信号，并输出所述第二初始授时信号；逻辑或门接收所述第一授时信号的触发信号和第二初始授时信号，并输出第二授时信号；其中，所述第一授时信号具有第一格式，所述第二初始授时信号、第二授时信号具有第二格式，所述第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。
第二方面，本公开提供一种授时信号转换的装置，其包括：转换单元，配置为根据第一授时信号得到对应相同时间的第二初始授时信号，并输出所述第二初始授时信号；逻辑或门，配置为接收所述第一 授时信号的触发信号和第二初始授时信号，并输出第二授时信号；其中，所述第一授时信号具有第一格式，所述第二初始授时信号、第二授时信号具有第二格式，所述第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。
第三方面，本公开提供一种计算机可读介质，其上存储有计算机程序，所述计算机程序被处理器执行时，使得所述处理器实现本公开所述的任一授时信号转换的方法。
附图说明
图1为IRIG-B授时信号中不同码元的格式示意图；
图2为本公开提供的一种授时信号转换的方法的流程图；
图3为本公开提供的另一种授时信号转换的方法的流程图；
图4为本公开提供的一种授时信号转换的方法的信号处理过程的示意图；
图5为本公开提供的另一种授时信号转换的方法中得到第二初始信号的过程的示意图；
图6为本公开提供的一种授时信号转换的装置的组成框图；
图7为本公开提供的一种计算机可读介质的组成框图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开实施方式提供的授时信号转换的方法和装置、计算机可读介质进行详细描述。
在下文中将参考附图更充分地描述本公开，但是所示的实施方式可以以不同形式来体现，且本公开不应当被解释为限于以下阐述的实施方式。反之，提供这些实施方式的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施方式的附图用来提供对本公开实施方式的进一步理解，并且构成说明书的一部分，与详细实施方式一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细实施方式进行描述， 以上和其它特征和优点对本领域技术人员将变得更加显而易见。
本公开可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。
在不冲突的情况下，本公开各实施方式及实施方式中的各特征可相互组合。
本公开所使用的术语仅用于描述特定实施方式，且不意欲限制本公开。如本公开所使用的术语“和/或”包括一个或多个相关列举条目的任何和所有组合。如本公开所使用的单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。如本公开所使用的术语“包括”、“由……制成”，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本公开所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本公开明确如此限定。
本公开不限于附图中所示的实施方式，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
在一些相关技术中，需要进行授时信号格式的转换，例如在为电力终端授时的过程中，就可能需要将1PPS+TOD授时信号转换为IRIG-B授时信号。
其中，1PPS+TOD(1 Pulse Per Second+Time of Day)为“每秒1脉冲加日时间”格式，其包括作为准时(On Time)基础的触发信号，以及表征具体时间的日时间(TOD)信号。其中，触发信号的发送周期为1秒(1PPS)，其上升沿(开始沿)为准时点；而TOD信号在触发信号的准时点后1ms开始发送，用于表征具体的时间。
其中，“准时点”也称“准时沿”，在授时信号(如授时信号的 触发信号)中，将该准时点到来的瞬间，定为授时信号所表示的时间。例如，若某个授时信号对应的时间为15:00:00，其准时点为其触发信号的上升沿，则接收该授时信号的设备会在触发信号的上升沿到来的瞬间，认为时间是15:00:00。
IRIG-B(Inter Range Instrumentation Group-B)授时信号为“远程通信工作组B码”格式，简称“B码”，其每秒授时一次，每个授时信号(一帧信号)包括100个脉冲(100PPS)，第1个脉冲的上升沿作为准时点，而不同位的脉冲分别用于表示时间的秒、十秒、分、十分、时、十时、天、十天、百天等信息，以及作为识别标志(P码)等。其中，每个码元的总时长为10ms，其含义通过脉宽(即码元的占空比)决定，如参照图1，脉宽2ms表示“0”码，脉宽5ms表示“1”码，脉宽8ms表示识别标志(P码)。
但是，信号的转换必然会消耗一定时间，从而导致转换出的授时信号相对原授时信号有延迟，即其时间并不准确，精度低，无法满足很多场景(如电力差动保护场景)的实际应用需求。
第一方面，本公开提供一种授时信号转换的方法。
本公开的授时信号转换的方法，用于将输入的一种格式的授时信号，转换为另一种格式的授时信号，之后输出；从而该方法可用在能获取的原授时信号的格式与目标设备(如电力终端)所需的授时信号格式不匹配的情况。
其中，本公开的授时信号转换的方法可由授时信号转换的装置执行，该授时信号转换的装置可以是专门用于进行转换的独立装置，也可与产生原授时信号的设备(如支持5G授时功能的电力5G CPE产品、支持GPS授时的设备等)结合为一体，或者是与需要转换后的授时信号的目标设备(如电力终端)结合为一体。
参照图2、图4、图6，在一些实施方式中，本公开的方法可以包括步骤S101和步骤S102。
在步骤S101，转换单元根据第一授时信号得到对应相同时间的第二初始授时信号，并输出第二初始授时信号。
在步骤S102，逻辑或门接收第一授时信号的触发信号和第二初 始授时信号，并输出第二授时信号。
其中，第一授时信号具有第一格式，第二初始授时信号、第二授时信号具有第二格式，第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。
授时信号转换的装置的转换单元接收一种格式(第一格式)的授时信号，并将其转变为另一种不同格式(第二格式)的、表示相同时间的授时信号(第二初始授时信号)；之后将该第二初始授时信号与原第一授时信号的触发信号一起输入逻辑或门，并以逻辑或门的输出作为最终转换得到的第二授时信号。
参照图4，由于转换需要时间，故转换得到的第二初始授时信号(图4中的IRIG-B(初始))必然相对第一授时信号(图4中的1PPS+TOD授时信号)有延迟，即第二初始授时信号的准时点(On Time，上升沿)略晚于第一授时信号的触发信号的准时点(上升沿)，而通过“或”操作，可使最终输出的第二授时信号(图4中的IRIG-B(输出))的准时点(上升沿)与第一授时信号的触发信号的准时点同步，也即是“保证最终转换得到的第二授时信号与原第一授时信号的准时点对齐”，同时，第二授时信号表征的时间也与第一授时信号一样，因此，第二授时信号可很准确的实现授时，精度高。
其中，授时信号中的脉冲(码元)宽度至少都在毫秒(ms)级，而转换耗时最多也不过数十微秒(μs)，即转换造成的延迟必定远远短于授时信号的码元的长度，因此，以上“或”操作虽然改变了第二授时信号的第一个脉冲的脉宽(占空比)，但其只是影响准时点，而并不会影响该码元实际表达的信息。
本公开中，根据第一格式的第一授时信号转换得到第二格式的第二初始授时信号，但不是直接将其输出，而是将第二初始授时信号和第一授时信号的触发信号一起输入逻辑或门；而通过“或”操作，可保证逻辑或门的输出的准时点必然与第一授时信号的触发信号的准时点相同，即相当于将由第一授时信号转换得到的第二授时信号“提前”到与第一授时信号同步，从而消除因转换耗时造成的第二授时信号的延迟，保证第一授时信号和第二授时信号在时间上对齐，也 就是保证转化得到的信号的精度高(<1μs)，满足各种场景(如电力差动保护场景)的实际应用需求。
在一些实施方式中，转换单元包括微控制单元MCU。
作为本公开的一种实施方式，参照图4，转换单元可包括微控制单元(MCU，Micro Controller Unit)，例如转换单元可就是“单片机”。
在一些相关技术中，可使用现场可编程门阵列(FPGA，Field Programmable Gate Array)进行授时信号的转换。但是，以上FPGA的线路板(PCB)尺寸大，成本高，功耗高，难以实现实际应用。
相对FPGA，MCU具有成本低、功耗低、尺寸小、便于实用等优点，但其转换时的精度通常也更低。
而本公开中，由于通过逻辑或门实现授时信号的对齐，故MCU本身转换的精度(第二初始授时信号的精度)实际并不影响最终输出的第二授时信号的精度，从而，若使用MCU为转换单元，则可实现成本低、功耗低、尺寸小、精度高的授时信号转换。
当然，本公开中转换单元的具体形式不限于MCU，例如可用FPGA作为转换单元。
在一些实施方式中，第一格式为1PPS+TOD；第二格式为IRIG-B；第一授时信号的触发信号为1PPS信号。
作为本公开的一种实施方式，示例性地，本方法可用于将1PPS+TOD授时信号转换为IRIG-B授时信号；相应的，此时的第一授时信号即为1PPS+TOD授时信号，而其中的触发信号为1PPS信号，而第二初始授时信号为IRIG-B(初始)，第二授时信号则为IRIG-B(输出)。
以下的部分内容中，用1PPS+TOD授时信号和IRIG-B授时信号为例进行说明。
当然，本公开中授时信号的具体格式不限于此，其也用于其它格式的授时信号(包括但不限于DCLS授时信号、NTP授时信号、PTP授时信号等)的转换，只要授时信号的准时点为上升沿即可。
在一些实施方式中，参照图3、图5，转换单元根据第一授时信 号得到对应相同时间的第二初始授时信号，并输出第二初始授时信号(S101)可以包括步骤S1011至S1013。
在步骤S1011，转换单元获取第一授时信号的日时间TOD信号和1PPS信号。
在步骤S1012，转换单元根据TOD信号对应的时间加预设时长后的时间，产生第二初始授时信号的信息，并存入缓存。
在步骤S1013，转换单元响应于一个第一授时信号的1PPS信号的上升沿，从缓存中获取根据预设时长前的第一授时信号产生的第二初始授时信号的信息，以产生并输出第二初始授时信号。
参照图5，转换单元可接收(如由TOD时间信息接收模块进行)1PPS+TOD授时信号(第一授时信号)中的TOD信号；之后解析(如由B码格式转换模块进行)出TOD信号的时间，将该时间加预设时长(例如1s)后，根据所得时间(如TOD信号的时间为15:00:00，则加1s后的时间为15:00:01)重新编码(如BCD编码)得到IRIG-B授时信号(第二初始授时信号)的信息(如IRIG-B授时信号每个码元的类型)；并将该IRIG-B授时信号的信息存储到缓存中；而当预设时长后的(如下一个)1PPS+TOD授时信号的1PPS信号(触发信号)到来时，则可触发(如由1PPS触发模块进行)读出缓存中当前IRIG-B授时信号的信息，并输出(如由B码输出模块进行)根据该信息产生的第二初始授时信号，即图4和图5中的IRIG-B(初始)。其中，以上触发实际也可理解为，每个1PPS信号触发预设时长前的(如上一个)TOD信号对应信息的输出。
其中,同一授时信号的TOD信号本身就比1PPS信号晚1ms，且由其转换得到第二初始授时信号也需要一定时间，即第二初始授时信号(IRIG-B(初始))实际产生的时间必然是比直接对应的TOD信号所代表的时间有较大延迟的；因此，为了避免第二初始授时信号与1PPS信号的时间差过大而造成通过逻辑或门得到的第二授时信号的第一个码元变形过大而错误，可将TOD信号对应的时间加预设时长(如1s)后再转换，并等待预设时长后的1PPS信号(如下1s的1PPS信号)的触发后输出(因为1PPS信号必然是1s一个，故这样的输出 仍然是准确的)。
当然，为了尽可能缩短时间差，故以上预设时长可就是1秒，而对应的预设时长前/后的信号，就是前一个/后一个信号。
在一些实施方式中，第二初始授时信号的信息为其各脉冲的脉冲宽度调制PWM信息。
作为本公开的一种实施方式，由于IRIG-B授时信号脉冲(码元)的个数和位置(间隔10ms)都是确定的，而只是通过每个脉冲的脉宽(如8ms、5ms、2ms)来区分相应码元的意义，因此，只要存储下其每个脉冲(码元)的PWM(Pulse Width Modulation)信息(如占空比，或脉宽等)，即可代表IRIG-B授时信号的全部信号，从而可减少要存储的信息量，简化信息格式。
例如，对每个IRIG-B授时信号，可依次在缓存中存储其100个脉冲对应的100个占空比值，以该100个值的数组作为其对应的信息。
从而，在开始根据该信息产生IRIG-B授时信号(即B码的第二初始授时信号)时(如接到下一个1PPS信号时)，可启动10ms的定时器，从而每10ms从缓存的数组读取一个值，根据该值产生并输出一个相应脉宽的单脉冲。
当然，如果第二初始授时信号的信息为其它形式，或以其它方式存储，也是可行的。
在一些实施方式中，预设时长为1秒，缓存为乒乓缓存。
作为本公开的一种实施方式，用于存储第二初始授时信号的信息的缓存可以是“乒乓缓存”。参照图5，乒乓缓存实际包括两个缓存区，即，buffer1和buffer2，当对buffer1写入第二初始授时信号的信息时，可从buffer2中读取之前存储的第二初始授时信号的信息并产生第二初始授时信号；而当对buffer2写入第二初始授时信号的信息时，可从buffer1中读取之前存储的第二初始授时信号的信息并产生第二初始授时信号。
例如，参照图5，可设置一个读指针和一个写指针，该两个指针轮流指向buffer1和buffer2，以轮流对buffer1和buffer2进行读操作 和写操作。
通过乒乓缓存，可仅用很小的缓存空间，在不进行信息复制等操作的情况下，在任何时间都同时实现信息的读取和写入，从而在结构简单、成本低的情况下(如在MCU中)，本公开的方法能良好的运行，持续可靠的输出第二初始授时信号。
当然，本公开实施方式中缓存的具体形式也不限于此，只要该缓存能及时实现第二初始授时信号的信息的写入和读取即可。
第二方面，本公开提供一种授时信号转换的装置。
本公开的授时信号转换的装置用于实现以上授时信号转换的方法。
其中，本公开的授时信号转换的装置可以是专门用于进行转换的独立装置，也可与产生原授时信号的设备(如支持5G授时功能的电力5G CPE产品、支持GPS授时的设备等)结合为一体，或者是与需要转换后的授时信号的目标设备(如电力终端)结合为一体。
参照图6，在一个实施方式中，本公开的授时信号转换的装置包括：转换单元，配置为根据第一授时信号得到对应相同时间的第二初始授时信号，并输出第二初始授时信号；逻辑或门，配置为接收第一授时信号的触发信号和第二初始授时信号，并输出第二授时信号；其中，第一授时信号具有第一格式，第二初始授时信号、第二授时信号具有第二格式，第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。
在一些实施方式中，转换单元包括MCU。
在一些实施方式中，第一格式为1PPS+TOD；第二格式为IRIG-B；第一授时信号的触发信号为1PPS信号。
第三方面，参照图8，本公开提供一种计算机可读介质，其上存储有计算机程序，计算机程序被处理器执行时，使得处理器实现本公开任意实施方式的授时信号转换的方法。
本领域普通技术人员可以理解，上文中所公开的全部或某些步骤、***、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。
在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。
某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器(CPU)、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其它数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于随机存取存储器(RAM，更具体如SDRAM、DDR等)、只读存储器(ROM)、带电可擦可编程只读存储器(EEPROM)、闪存(FLASH)或其它磁盘存储器；只读光盘(CD-ROM)、数字多功能盘(DVD)或其它光盘存储器；磁盒、磁带、磁盘存储或其它磁存储器；可以用于存储期望的信息并且可以被计算机访问的任何其它的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其它传输机制之类的调制数据信号中的其它数据，并且可包括任何信息递送介质。
本公开已经公开了示例实施方式，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施方式相结合描述的特征、特性和/或元素，或可与其它实施方式相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种授时信号转换的方法，包括：
    转换单元根据第一授时信号得到对应相同时间的第二初始授时信号，并输出所述第二初始授时信号；
    逻辑或门接收所述第一授时信号的触发信号和第二初始授时信号，并输出第二授时信号；
    其中，所述第一授时信号具有第一格式，所述第二初始授时信号、第二授时信号具有第二格式，所述第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。
  2. 根据权利要求1所述的方法，其中，
    所述转换单元包括微控制单元MCU。
  3. 根据权利要求1所述的方法，其中，
    所述第一格式为每秒1脉冲加日时间1PPS+TOD；
    所述第二格式为远程通信工作组B码IRIG-B；
    所述第一授时信号的触发信号为每秒1脉冲1PPS信号。
  4. 根据权利要求3所述的方法，其中，所述转换单元根据第一授时信号得到对应相同时间的第二初始授时信号，并输出所述第二初始授时信号包括：
    所述转换单元获取第一授时信号的日时间TOD信号和1PPS信号；
    所述转换单元根据TOD信号对应的时间加预设时长后的时间，产生所述第二初始授时信号的信息，并存入缓存；
    所述转换单元响应于一个第一授时信号的1PPS信号的上升沿，从缓存中获取根据预设时长前的第一授时信号产生的第二初始授时信号的信息，以产生并输出第二初始授时信号。
  5. 根据权利要求4所述的方法，其中，
    所述预设时长为1s；
    所述缓存为乒乓缓存。
  6. 根据权利要求4所述的方法，其中，所述第二初始授时信号的信息为其各脉冲的脉冲宽度调制PWM信息。
  7. 一种授时信号转换的装置，包括：
    转换单元，配置为根据第一授时信号得到对应相同时间的第二初始授时信号，并输出所述第二初始授时信号；
    逻辑或门，配置为接收所述第一授时信号的触发信号和第二初始授时信号，并输出第二授时信号；
    其中，所述第一授时信号具有第一格式，所述第二初始授时信号、第二授时信号具有第二格式，所述第一授时信号的触发信号、第二初始授时信号、第二授时信号的准时点均为其上升沿。
  8. 根据权利要求7所述的装置，其中，
    所述转换单元包括微控制单元MCU。
  9. 根据权利要求7所述的装置，其中，
    所述第一格式为每秒1脉冲加日时间1PPS+TOD；
    所述第二格式为远程通信工作组B码IRIG-B；
    所述第一授时信号的触发信号为1PPS信号。
  10. 一种计算机可读介质，其上存储有计算机程序，所述计算机程序被处理器执行时，使得所述处理器实现权利要求1至6中任意一项所述的授时信号转换的方法。
PCT/CN2022/132202 2021-11-24 2022-11-16 授时信号转换的方法和装置、计算机可读介质 WO2023093585A1 (zh)

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