WO2023090197A1 - Carte de câblage et son procédé de fabrication - Google Patents

Carte de câblage et son procédé de fabrication Download PDF

Info

Publication number
WO2023090197A1
WO2023090197A1 PCT/JP2022/041489 JP2022041489W WO2023090197A1 WO 2023090197 A1 WO2023090197 A1 WO 2023090197A1 JP 2022041489 W JP2022041489 W JP 2022041489W WO 2023090197 A1 WO2023090197 A1 WO 2023090197A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
seed layer
conductive layer
seed
wiring board
Prior art date
Application number
PCT/JP2022/041489
Other languages
English (en)
Japanese (ja)
Inventor
智之 石井
健央 高田
優樹 梅村
Original Assignee
凸版印刷株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 凸版印刷株式会社 filed Critical 凸版印刷株式会社
Priority to JP2023561537A priority Critical patent/JPWO2023090197A1/ja
Publication of WO2023090197A1 publication Critical patent/WO2023090197A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Definitions

  • the present invention relates to a wiring board and its manufacturing method.
  • a multilayer wiring board using a glass material as a core board (hereinafter referred to as a "glass circuit board”, etc.) is often used as an interposer.
  • a glass circuit board hereinafter referred to as a "glass circuit board”, etc.
  • thin film capacitors having an MIM structure Metal Insulator Metal in which a dielectric is sandwiched between a lower electrode layer and an upper electrode layer are formed as part of the passive circuit inside the substrate.
  • Patent Document 1 a substrate having an insulating surface, a first conductive layer disposed on the substrate, the first portion having a first thickness and a second thickness less than the first thickness. a first conductive layer including a second portion adjacent to the first portion; a first insulating layer spaced from the second portion and disposed on the first portion; and a second conductive layer disposed opposite the first portion.
  • Patent Document 1 discloses providing a step in the vicinity of the boundary between the first conductive layer and the first insulating layer in order to relieve the stress in the first conductive layer of the MIM.
  • one typical method for manufacturing a wiring board comprises: a substrate having an insulating surface; a first seed layer disposed on the substrate; a first conductive layer disposed over the first conductive layer; a first insulating layer disposed over the first conductive layer; a second seed layer disposed over the first insulating layer; A wiring board having a second conductive layer disposed above the layer, Patterning the first seed layer by etching includes etching using an etch mask wider than the first conductive layer in at least one direction.
  • one typical wiring board of the present invention is a substrate having an insulating surface;
  • a wiring board including the following layers (1) to (5), (1) a first seed layer disposed on the substrate; (2) a first conductive layer disposed above the first seed layer; and (3) a first insulating layer disposed above the first conductive layer.
  • FIG. 1 is a cross-sectional view showing a basic structure to which the present invention is directed.
  • FIG. 2 is a cross-sectional view for explaining the step of forming the first conductive layer.
  • FIG. 3 is a cross-sectional view for explaining the step of forming the first conductive layer.
  • FIG. 4 is a cross-sectional view for explaining the step of forming the first conductive layer.
  • FIG. 5 is a cross-sectional view for explaining the step of forming the first conductive layer.
  • FIG. 6 is a cross-sectional view for explaining side etching in a conventional example.
  • FIG. 7 is a cross-sectional view for explaining the step of forming the second conductive layer in the embodiment.
  • FIG. 1 is a cross-sectional view showing a basic structure to which the present invention is directed.
  • FIG. 2 is a cross-sectional view for explaining the step of forming the first conductive layer.
  • FIG. 3 is a cross-sectional view for explaining the step of forming
  • FIG. 8 is a cross-sectional view for explaining the step of forming the second conductive layer in the embodiment.
  • FIG. 9 is a cross-sectional view for explaining the process of forming the MIM structure.
  • FIG. 10 is a cross-sectional view for explaining the etching process of the first seed layer.
  • FIG. 11 is a cross-sectional view illustrating a wiring board on which MIM capacitors are formed.
  • FIG. 12 is a cross-sectional view of a wiring board formed on a multilayer wiring board.
  • 13A and 13B are cross-sectional views for explaining the formation process of the second embodiment.
  • 14A and 14B are cross-sectional views for explaining the formation process of the second embodiment.
  • 15A and 15B are cross-sectional views for explaining the formation process of the second embodiment.
  • 16A and 16B are cross-sectional views for explaining the formation process of the second embodiment.
  • 17A and 17B are cross-sectional views for explaining the formation process of the second embodiment.
  • the term “surface” may refer not only to the surface of the plate-like member, but also to the interface between the layers included in the plate-like member that is substantially parallel to the surface of the plate-like member.
  • the terms “upper surface” and “lower surface” refer to the upper or lower surface of the drawing when a plate-like member or a layer included in the plate-like member is illustrated.
  • the “upper surface” and “lower surface” may also be referred to as “first surface” and "second surface”.
  • the “side surface” means a surface of a plate-like member or a layer included in the plate-like member or a portion of the thickness of the layer. Furthermore, a part of a surface and a side surface may be collectively referred to as an "end”. Moreover, “upper” means the vertically upward direction when the plate-like member or layer is placed horizontally. Further, “upward” and “downward” opposite to this are sometimes referred to as “Z-axis positive direction” and “Z-axis negative direction”, and horizontal directions are referred to as “X-axis direction” and "Y-axis direction”. It is sometimes called “direction”.
  • planar shape and “planar view” mean the shape when a surface or layer is viewed from above, that is, from the positive direction to the negative direction of the z-axis.
  • cross-sectional shape and “cross-sectional view” mean the shape of a plate-like member or layer cut in a specific direction and viewed from the horizontal direction.
  • core means the core of a face or layer, but not the periphery.
  • central direction means a direction from the periphery of a surface or layer toward the center of the planar shape of the surface or layer.
  • FIG. 1 shows a substrate 1 having an insulating surface, a first seed layer 3 arranged on the substrate 1, a first conductive layer 4 arranged above the first seed layer 3, and the first conductive layer 4 arranged above the first seed layer 3.
  • a first insulating layer 6 disposed above one conductive layer 4; a second seed layer 8 disposed above said first insulating layer 6; a second seed layer 8 disposed above said second seed layer 8; 2 is a cross-sectional view of a wiring board having a conductive layer 9;
  • the first conductive layer 4 serves as the lower electrode of the MIM
  • the first insulating layer 6 serves as the dielectric layer of the MIM
  • the second conductive layer 9 serves as the upper electrode of the MIM
  • the substrate 1 configure MIM capacitors at
  • the substrate 1 is desirably made of transparent glass having optical transparency. There are no particular restrictions on the composition of the glass or the blending ratio of each component contained in the glass, and the method of manufacturing the glass. Examples of glass include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, but any glass material containing silicate as a main component may be used. Furthermore, other so-called glass materials may be used.
  • the thickness of the glass substrate is preferably 1 mm or less, but more preferably 0.1 mm or more and 0.8 mm or less in consideration of the ease of the glass through-hole forming process and the handling during manufacturing.
  • Examples of the method for manufacturing a glass substrate include a float method, a down-draw method, a fusion method, an up-draw method, a roll-out method, and the like.
  • the coefficient of linear expansion of the glass is preferably -1 ppm/K or more and 15.0 ppm/K or less. The reason for this is that if the concentration is -1 ppm/K or less, it becomes difficult to select the glass material itself, and it cannot be manufactured at a low cost. On the other hand, when it is 15.0 ppm/K or more, the difference in thermal expansion coefficient from other layers is large, and the reliability is lowered. Moreover, when a silicon chip is mounted on the substrate 1, the connection reliability with the silicon chip is lowered.
  • the linear expansion coefficient of glass is more preferably 0.5 ppm/K or more and 8.0 ppm/K or less, and still more preferably 1.0 ppm/K or more and 4.0 ppm/K or less.
  • a functional film such as an antireflection film or an IR cut filter may be formed in advance on the glass substrate.
  • functions such as strength imparting, antistatic imparting, coloring, and texture control may be imparted.
  • these functional films include a hard coat film for imparting strength, an antistatic film for imparting antistatic properties, an optical filter film for coloring, and an antiglare and light scattering film for texture control. Not as long.
  • deposition techniques such as vapor deposition, sputtering, and wet methods are used.
  • the metal layer forming the first seed layer 3 functions as a power supply layer for electrolytic plating in the formation of wiring in the semi-additive method.
  • the seed metal layer provided directly above the substrate 1 and on the inner wall of the through hole formed in the substrate 1 is formed by, for example, sputtering or CVD, and includes Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu 3 N 4 , Cu alloys alone or in combination are used .
  • An electroless plating layer (electroless copper plating, electroless nickel plating, etc.) may be formed over the first seed layer 3 of the present disclosure.
  • the upper surface of the substrate 1 and the first insulating layer 6 is subjected to the electrical properties, manufacturability and cost considerations. Considering this, it is desirable to form the adhesion layer 2 from titanium deposited by a sputtering method.
  • the lower adhesion layer 5 has the function of improving the adhesion between the first conductive layer, which is the lower electrode, and the dielectric layer, and the upper adhesion layer 7 improves the adhesion between the dielectric layer and the seed metal layer. It has the function of improving
  • the material of the lower adhesion layer and the upper adhesion layer is Ti, for example.
  • Ti is superior in terms of adhesion, electrical conductivity, ease of manufacture, and cost.
  • the thickness of the lower adhesion layer and the upper adhesion layer is, for example, 10 nm or more and 1 ⁇ m or less. If it is less than 10 nm, the adhesion strength may be insufficient. If the thickness exceeds 1 ⁇ m, in the manufacturing process to be described later, not only does the film formation take too long to impede mass production, but there is a possibility that the process of removing unnecessary portions will take even more time.
  • the thicknesses of the lower adhesion layer and the upper adhesion layer are more preferably 10 nm or more and 500 nm or less. Although the thicknesses of the lower adhesion layer and the upper adhesion layer may be different, it is preferable that they have the same thickness in order to simplify the structure. Further, if the adhesion between the lower electrode and the dielectric layer is sufficient, the lower adhesion layer may be omitted. If the adhesion between the dielectric layer and the seed metal layer is sufficient, the upper adhesion layer may be omitted.
  • the adhesion layer 2, the first seed layer 3, and the first conductive layer 4 formed on the substrate 1 can be used as wiring for circuit formation in regions on the substrate 1 other than where MIM capacitors are formed.
  • the total thickness of the titanium and copper layers is preferably 5 ⁇ m or less because it is advantageous for fine wiring formation by the semi-additive method. If the thickness is more than 5 ⁇ m, it is difficult to form fine wiring with a pitch of 30 ⁇ m or less.
  • electrolytic copper plating is desirable because it is simple and inexpensive and has good electrical conductivity, considering that it is also used as a circuit. However, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, and the like may be used.
  • the dielectric layer which is the first insulating layer 6, should be selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate from the viewpoint of insulation and dielectric constant. can be done.
  • the thickness of the dielectric layer is desirably 10 nm or more and 5 ⁇ m or less. If the thickness of the dielectric layer is 10 nm or less, the insulating properties cannot be maintained and the function as a capacitor cannot be exhibited. If the thickness of the dielectric layer is 5 ⁇ m or more, it takes too much time to form the film, which not only impedes mass production, but also takes more time in the process of removing unnecessary portions. More preferably, it is 50 nm or more and 1 ⁇ m or less.
  • the second seed layer 8 is a power supply layer for forming the upper electrode, which is the second conductive layer of the capacitor, by a semi-additive method.
  • the second seed layer 8 is made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, a Cu alloy alone or in combination. can be applied. Copper is desirable because it can be easily removed by etching later.
  • the thickness of the seed metal layer is desirably 50 nm or more and 5 ⁇ m or less.
  • the thickness of the seed metal layer is less than 50 nm, there is a possibility that poor conduction will occur in the subsequent electroplating process. If the thickness of the seed metal layer exceeds 5 ⁇ m, it will take a long time to remove it by etching.
  • the thickness of the seed metal layer is more preferably 100 nm or more and 500 nm or less.
  • the upper electrode which is the second conductive layer 9, is an electrolytic plating layer.
  • Electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity. However, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, and the like may be used.
  • the thickness of the upper electrode is desirably 3 ⁇ m or more and 30 ⁇ m or less. If the thickness is less than 3 ⁇ m, the circuit may disappear depending on the etching process after the upper electrode is formed.
  • the electrolytic copper plating thickness exceeds 30 ⁇ m, it is necessary to form a resist layer with a thickness of 30 ⁇ m or more, which increases manufacturing costs. Furthermore, since the resist resolution is lowered, it becomes difficult to form fine wiring with a pitch of 30 ⁇ m or less. More preferably, it is 5 ⁇ m or more and 25 ⁇ m or less. More desirably, the thickness is 10 ⁇ m or more and 20 ⁇ m or less.
  • FIGS. 2 to 6 a conventional example of manufacturing a wiring board having an MIM capacitor structured as shown in FIG. 1 will be described.
  • an adhesion layer 2 and a first seed layer 3 are formed above a substrate 1 having an insulating surface, and a pattern of a resist 11 is formed thereon.
  • the first conductive layer 4 is formed by electrolytic plating using the first seed layer 3 as a power supply layer.
  • the resist 11 is removed, and as shown in FIG. 5, unnecessary portions of the adhesion layer 2 and the first seed layer 3 are removed using the first conductive layer 4 as an etching mask.
  • the first insulating layer 6 as the dielectric layer is formed.
  • the seed layer 8 is formed, power is supplied to the second seed layer to form the second conductive layer 9 that will serve as the upper electrode.
  • the upper adhesion layer 7 and the second seed layer 8 are formed by a sputtering method, the sputter coating on the side wall of the first conductive layer 4, which is the lower electrode layer, will not adhere to the first conductive layer 4. Much depends on the shape of the end. Therefore, as shown in FIG.
  • the adhesion layer 2 and the first seed layer 3 are etched using the first conductive layer 4 as an etching mask as shown in FIG.
  • This will adversely affect the precision and yield of the capacitor.
  • the smoothness of the interface between the lower electrode and the dielectric can be maintained, and short-circuiting of capacitors due to surface roughness and variations in capacitance due to variations in electrode surface area can be reduced. Therefore, it is possible to improve the yield of the capacitor and to stably manufacture the capacitor.
  • Step 1 Since Steps 1 to 6 in the first embodiment are the same as in the conventional example, they will be explained with reference to FIGS. 2 to 4.
  • FIG. 1 although not shown in FIGS. 2 to 11 and FIGS. 13 to 17, the substrate 1 may have a through hole penetrating from the upper surface of the substrate 1 to the lower surface.
  • the cross-sectional shape and diameter of the through hole may be, for example, a shape in which the diameter of the central portion is narrower than the top diameter and the bottom diameter of the through hole, or a shape in which the bottom diameter is smaller than the top diameter. Further, the shape may be such that the diameter of the central portion is larger than the top and bottom diameters of the through hole.
  • Step 2 Next, as shown in FIG. 2, when the surface of the substrate 1 and through holes are formed, the adhesion layer 2 and the first seed layer 3 are also formed in the through holes.
  • the adhesion layer 2 and the first seed layer 3 act as power supply layers for electroplating in the wiring forming process in the semi-additive method.
  • the steps of forming the adhesion layer 2 and the first seed layer 3 include forming titanium as the adhesion layer 2 on the substrate 1 by sputtering, then forming a copper layer as the first seed layer 3 by sputtering, and then forming a copper layer. Additionally, an additional metal layer is preferably formed by electroless plating.
  • the electroless plating layer may be electroless copper plating or electroless nickel plating, but electroless nickel plating is preferable because it has good adhesion to the glass, titanium, or copper layer. If the nickel plating layer is too thick, it may become difficult to form fine wiring. Further, the adhesion may be lowered due to the increase in film stress. Therefore, the electroless nickel plating thickness is preferably 1 ⁇ m or less. Moreover, it is more preferably 0.5 ⁇ m or less, and still more preferably 0.3 ⁇ m or less.
  • the electroless nickel plating film may contain phosphorus, which is a co-deposit derived from the reducing agent, and sulfur, lead, bismuth, and the like contained in the electroless nickel plating solution.
  • Step 3 Subsequently, as shown in FIG. 2, a pattern of resist 11 is formed above the first seed layer.
  • a layer of the resist 11 is formed on the entire surface of the first seed layer.
  • a negative dry film resist, a negative liquid resist, and a positive liquid resist can be used as the resist, but the negative photoresist is preferable because the formation of the resist layer is simple and inexpensive.
  • Step 4 a pattern for forming a desired conductor circuit layer is formed on the photoresist layer by a known photolithographic method. That is, the pattern of the resist 11 is aligned so that the portion where the conductor circuit layer is to be formed later is exposed, and patterning is realized by exposure and development.
  • the thickness of the resist layer depends on the thickness of the conductive circuit layer, it is preferably 5 ⁇ m or more and 25 ⁇ m or less. If the thickness is less than 5 ⁇ m, the electroplated layer, which will be the conductive circuit layer, cannot be increased to 5 ⁇ m or more, and the connection reliability of the circuit may be lowered. If the thickness is more than 25 ⁇ m, it becomes difficult to form fine wiring with a pitch of 30 ⁇ m or less. Thus, a substrate having a photoresist pattern formed thereon is obtained.
  • Step 5 Subsequently, by supplying power to the first seed layer and immersing it in a plating solution, an electrolytic plating layer, which is a first conductive layer that will later become a conductive circuit layer, is formed on the upper surface of the first seed layer where the photoresist pattern is not formed. to form
  • Step 6 Subsequently, the unnecessary photoresist pattern is removed to expose the first conductive layer and the first seed layer 3 as shown in FIG.
  • the method for removing the resist 11 is not limited to any particular method, for example, the resist 11 can be peeled off with an alkaline aqueous solution.
  • Step 7 Subsequently, as shown in FIG. 7, a lower adhesion layer 5, a first insulating layer 6, an upper adhesion layer 7, and a second seed layer 8 are sequentially formed over the entire surface of the lower electrode, which is the first conductive layer 4.
  • Form deposits Methods for forming the above layers include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser abrasion method, and a CVD method, but are not limited by this embodiment.
  • the lower adhesion layer 5 under the first insulating layer 6 has the function of improving the adhesion between the first insulating layer 6 and the first conductive layer 4 .
  • the lower adhesion layer 5 may be omitted.
  • the first insulating layer and the second seed layer are formed without etching the first seed layer. Therefore, when the second seed layer is formed, it is possible to suppress abnormal throwing power of the second seed layer. As a result, the second conductive layer can also be stably formed.
  • the second seed layer functions as a power feeding layer for forming the upper electrode of the capacitor by a semi-additive method.
  • a pattern of resist 11 is formed on the upper surface of the second seed layer 8 in a region other than where the second conductive layer 9 is to be formed.
  • the formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above.
  • the opening region of the pattern of the resist 11 is formed so as to be inside the first conductive layer 4 (lower electrode). is formed inside the first conductive layer 4 (lower electrode).
  • Step 9 Subsequently, power is supplied to the second seed layer to form the second conductive layer 9 (upper electrode) by electroplating.
  • Step 10 Subsequently, the pattern of the resist 11 is removed.
  • the removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution.
  • a pattern of resist 11 is formed so as to surround the second conductive layer 9 (upper electrode).
  • the formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above.
  • the non-opening region of the photoresist pattern is formed so as to be outside the upper electrode and inside the first conductor layer (lower electrode). It is formed so as to be inside the first conductive layer 4 (lower electrode) except for the portion of .
  • etching is performed so that the end surfaces of the second seed layer 8, the upper adhesion layer 7, the first insulating layer 6, and the lower adhesion layer 5 are outside the second conductive layer and inside the first conductive layer, respectively, A MIM capacitor structure is formed.
  • Step 12 The removal of unnecessary portions of the second seed layer 8 and the upper adhesion layer 7 is not limited to being performed in this step. 7 may be removed. By doing so, the area of the first insulating layer 6 on the outer surface of the MIM capacitor device is increased, and current leakage from the side surface between the upper electrode and the lower electrode can be suppressed.
  • Step 13 Subsequently, the pattern of the resist 11 is removed.
  • the removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution.
  • a pattern of resist 11 is again formed so as to surround first conductive layer 4 as well. That is, the pattern of the resist 11 is formed such that the pattern of the resist 11 becomes an etching mask wider than the first conductive layer in at least one width direction (the direction in the xy plane perpendicular to the z-axis). That is, the width of the etching mask, which is wider than the first conductive layer, corresponds to the width of the first seed layer 3 in the MIM capacitor.
  • the non-opening region of the photoresist pattern is formed so as to be outside the lower electrode, and even in a plan view in the stacking direction, the first conductive layer 4 is formed except for the portion of the connection line to the outside of the MIM capacitor. (lower electrode).
  • the relationship between the width b in the xy plane (horizontal direction) of the resist 11 in at least one direction and the width a in the xy plane of the first conductive layer (lower electrode) in the same direction is, of course, as follows.
  • Expression (1) is satisfied.
  • a and b satisfy the following formula (2).
  • "(ba)/2" indicates the width difference between the first conductive layer (lower electrode) 4 and the resist 11 on one side.
  • the reason why the upper limit of the width difference on one side is set to 50 ⁇ m is that if it is larger than this, the pattern design is restricted.
  • the height c of the adhesion layer 2 and the first seed layer 3 in the z-axis direction (total thickness of the two layers) satisfies the following formula (3).
  • the reason why the lower limit of c is set to 50 nm in Equation (3) is that 50 nm is required as the minimum value for the adhesion layer 2 and the first seed layer 3 to function as power supply layers.
  • the reason why the upper limit of c is set to 5 ⁇ m is that the wiring width that can be formed is restricted when the seed layer is etched.
  • a, b, and c satisfy the following formula (4).
  • Step 15 Subsequently, the exposed portion of the first seed layer is removed.
  • the electroless Ni layer, the copper layer, and the titanium layer can be removed sequentially by chemical etching.
  • the type of etchant is appropriately selected according to the metal species to be removed, and the removal method is not limited to the methods described in the present disclosure.
  • Step 16 Subsequently, when the pattern of the resist 11 is removed. As shown in FIG. 11, a wiring substrate having MIM capacitors formed thereon can be formed. The removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution. A capacitor is formed by the above steps.
  • Step 17 Thereafter, as shown in FIG. 12, an insulating resin layer 12 and via holes 13 are formed on the wiring board.
  • a multilayer wiring board is formed by repeatedly forming a laminated conductor circuit layer and an insulating resin layer.
  • the conductor circuit and laminated structure on the wiring substrate can be formed using a known semi-additive method or subtractive method.
  • a wiring board according to the present disclosure may have laminated conductor circuit layers, external connection terminals, and solder balls on one side, or may have both sides as a modification. Further, semiconductor chips and chip parts may be mounted.
  • step 6 of the first embodiment shown in FIG. 4 is followed by step 20, described below.
  • Step 20 After step 6 of the first embodiment, as shown in FIG. 13, a pattern of resist 11 is formed so as to surround the first conductive layer.
  • the resist pattern can be formed by the same method as the resist pattern described above. In this case, the non-opening region of the resist pattern is formed so as to be outside the lower electrode, and even in a plan view in the stacking direction, the first conductive layer 4 ( bottom electrode).
  • the length b of the resist 11 in the xy plane, the length a of the first conductive layer (lower electrode) in the xy plane in the same direction, and the height of the adhesion layer 2 and the first seed layer 3 in the z-axis direction is the same as described in step 14 in the first embodiment.
  • Step 21 Subsequently, the first seed layer 3 and the adhesion layer 2 are removed using the pattern of the resist 11 as an etching mask.
  • the first seed layer 3 and the adhesion layer 2 can be removed by chemically etching the electroless Ni layer, the copper layer, and the titanium layer sequentially.
  • the type of etchant is appropriately selected depending on the metal species to be removed, and is not limited at all.
  • Step 22 Subsequently, by removing the pattern of the resist 11, the cross section shown in FIG. 14 can be obtained.
  • the removal of the resist 11 can be performed by a known method of removing and peeling with an alkaline aqueous solution.
  • Step 23 Subsequently, as shown in FIG. 15, the lower adhesion layer 5, the first insulating layer 6, the upper adhesion layer 5, the first insulating layer 6, and the upper adhesion layer are formed over the entire surface of the lower electrode, which is the first conductive layer 4, in the same manner as in step 7 of the first embodiment.
  • a layer 7 and a second seed layer 8 are sequentially deposited.
  • Methods for forming the above layers include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser abrasion method, and a CVD method, but are not limited by this embodiment.
  • the lower adhesion layer 5 under the first insulating layer 6 has the function of improving the adhesion between the first insulating layer 6 and the first conductive layer 4 . However, if the adhesion between the first insulating layer 6 and the first conductive layer 4 is sufficient, the lower adhesion layer 5 may be omitted.
  • the second seed layer functions as a power feeding layer for forming the upper electrode of the capacitor by a semi-additive method.
  • a pattern of resist 11 is formed in a region other than where the second conductive layer 9 is to be formed.
  • the formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above.
  • the opening region of the pattern of the resist 11 is formed so as to be inside the first conductive layer 4 (lower electrode). is formed inside the first conductive layer 4 (lower electrode).
  • Step 25 Subsequently, power is supplied to the second seed layer to form the second conductive layer 9 (upper electrode) by electroplating.
  • Step 26 Subsequently, the pattern of the resist 11 is removed.
  • the removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution.
  • a pattern of resist 11 is formed so as to surround the second conductive layer 9 (upper electrode).
  • the formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above.
  • the non-opening region of the photoresist pattern is formed so as to be outside the upper electrode and inside the first conductor layer (lower electrode). It is formed so as to be inside the first conductive layer 4 (lower electrode) except for the portion of . It is desirable to form them so that they are on the outside and inside, respectively.
  • Step 28 Subsequently, as in step 12, unnecessary portions of the second seed layer 8, the upper adhesion layer 7, the first insulating layer 6, and the lower adhesion layer 5 are removed using the pattern of the resist 11 as a mask.
  • the removal of the second seed layer 8, the upper adhesion layer 7, the first insulating layer, and the lower adhesion layer 5 can be carried out using known methods such as chemical etching and dry etching. A different removal method may be employed for each layer, or the same removal method may be applied to all layers.
  • the pattern of the resist 11 is formed inside the first conductive layer 4 (lower electrode). It is formed so as to remain only inside one conductive layer (lower electrode).
  • the unnecessary portions of the second seed layer and the upper adhesion layer 7 may be removed by etching using the second conductive layer 9 (upper electrode) as a mask immediately after the step 27, even if they are not removed in the step 28. Also good. By doing so, the area of the first insulating layer on the outer surface of the MIM capacitor device is increased, and current leakage from the side surface between the upper electrode and the lower electrode can be suppressed.
  • Step 29 Subsequently, when the pattern of the resist 11 is removed.
  • a wiring substrate having MIM capacitors formed thereon can be formed as shown in FIG.
  • the removal of the resist pattern can be carried out by using a known alkaline aqueous solution.
  • a capacitor is formed by the above steps.
  • step 29 in the second embodiment are the same as in the first embodiment, so descriptions thereof are omitted.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

La présente invention aborde le problème selon lequel, lors de la formation d'une électrode de condensateur par placage électrolytique à l'aide d'une couche de germe, si la constriction de l'étape se produit en raison d'une gravure latérale dans une étape pendant la formation de la couche de germe, la formation complète de la couche de germe peut échouer, et la formation complète de l'électrode par placage électrolytique peut échouer. Ainsi, l'objectif de la présente invention est de fournir une carte de câblage dans laquelle une gravure latérale ne se produit pas dans une couche de germe.　Par conséquent, dans la présente invention, dans une carte de câblage ayant une structure de condensateur MIM comprenant une carte (1) ayant une surface isolante, une première couche de germe (3), une première couche conductrice (4), une première couche isolante (6), une seconde couche de germe (8), et une seconde couche conductrice (9), une étape de formation de motifs sur la première couche de germe par gravure comprend la réalisation d'une gravure à l'aide d'un masque de gravure ayant une largeur supérieure à la première couche conductrice dans au moins une direction.
PCT/JP2022/041489 2021-11-18 2022-11-08 Carte de câblage et son procédé de fabrication WO2023090197A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023561537A JPWO2023090197A1 (fr) 2021-11-18 2022-11-08

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021188035 2021-11-18
JP2021-188035 2021-11-18

Publications (1)

Publication Number Publication Date
WO2023090197A1 true WO2023090197A1 (fr) 2023-05-25

Family

ID=86396965

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/041489 WO2023090197A1 (fr) 2021-11-18 2022-11-08 Carte de câblage et son procédé de fabrication

Country Status (3)

Country Link
JP (1) JPWO2023090197A1 (fr)
TW (1) TW202331950A (fr)
WO (1) WO2023090197A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009188401A (ja) * 2008-02-07 2009-08-20 Ibiden Co Ltd キャパシタ内蔵プリント配線板
JP2018191003A (ja) * 2016-12-21 2018-11-29 大日本印刷株式会社 貫通電極基板、半導体装置及び貫通電極基板の製造方法
WO2019244382A1 (fr) * 2018-06-21 2019-12-26 大日本印刷株式会社 Substrat de câblage et dispositif à semi-conducteur
JP2021100007A (ja) * 2019-12-19 2021-07-01 Tdk株式会社 電子部品及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009188401A (ja) * 2008-02-07 2009-08-20 Ibiden Co Ltd キャパシタ内蔵プリント配線板
JP2018191003A (ja) * 2016-12-21 2018-11-29 大日本印刷株式会社 貫通電極基板、半導体装置及び貫通電極基板の製造方法
WO2019244382A1 (fr) * 2018-06-21 2019-12-26 大日本印刷株式会社 Substrat de câblage et dispositif à semi-conducteur
JP2021100007A (ja) * 2019-12-19 2021-07-01 Tdk株式会社 電子部品及びその製造方法

Also Published As

Publication number Publication date
JPWO2023090197A1 (fr) 2023-05-25
TW202331950A (zh) 2023-08-01

Similar Documents

Publication Publication Date Title
JP7083600B2 (ja) キャパシタ内蔵ガラス回路基板及びその製造方法
TWI765941B (zh) 電子零件及電子零件製造方法
US10923439B2 (en) Core substrate, multi-layer wiring substrate, semiconductor package, semiconductor module, copper-clad substrate, and method for manufacturing core substrate
US11756846B2 (en) Glass core, multilayer circuit board, and method of manufacturing glass core
JP7444210B2 (ja) キャパシタ内蔵ガラス回路基板
US20210076491A1 (en) Glass circuit board and method of manufacturing same
JPWO2005027605A1 (ja) 両面配線ガラス基板の製造方法
JP2003197463A (ja) 薄膜キャパシタ及びその製造方法
JP2018107256A (ja) ガラス配線板、半導体パッケージ基板、半導体装置、及び半導体装置の製造方法
JP2019114723A (ja) キャパシタ内蔵ガラス回路基板及びキャパシタ内蔵ガラス回路基板の製造方法
WO2023090197A1 (fr) Carte de câblage et son procédé de fabrication
JP6946745B2 (ja) ガラス回路基板及びその製造方法
JP2019197791A (ja) キャパシタ内蔵ガラス基板、及びキャパシタ内蔵回路基板
JP7009958B2 (ja) キャパシタ内蔵ガラス基板の製造方法
JP2022190464A (ja) ガラス配線基板及びガラス配線基板の製造方法
WO2023171240A1 (fr) Substrat en verre, électrode traversante, substrat de câblage multicouche et procédé de fabrication de substrat en verre
JP2005086026A (ja) 両面配線ガラス基板およびその製造方法
JP2024006905A (ja) 多層配線基板、多層配線基板の製造方法、および母材基板
JP2004055593A (ja) 配線基板およびその製造方法
JP2001358166A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22895479

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2023561537

Country of ref document: JP