WO2023087284A1 - 封装结构、其制备方法、封装模组及电子设备 - Google Patents

封装结构、其制备方法、封装模组及电子设备 Download PDF

Info

Publication number
WO2023087284A1
WO2023087284A1 PCT/CN2021/131935 CN2021131935W WO2023087284A1 WO 2023087284 A1 WO2023087284 A1 WO 2023087284A1 CN 2021131935 W CN2021131935 W CN 2021131935W WO 2023087284 A1 WO2023087284 A1 WO 2023087284A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive connection
connection pad
electronic component
electrically connected
hole
Prior art date
Application number
PCT/CN2021/131935
Other languages
English (en)
French (fr)
Inventor
童亮
张珊
孙世虎
刘国文
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21964438.2A priority Critical patent/EP4398295A1/en
Priority to PCT/CN2021/131935 priority patent/WO2023087284A1/zh
Priority to CN202180099259.4A priority patent/CN117480601A/zh
Publication of WO2023087284A1 publication Critical patent/WO2023087284A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Definitions

  • the present application relates to the technical field of semiconductor packaging, especially to a packaging structure, its preparation method, packaging module and electronic equipment.
  • the printed circuit board (Printed Circuit Board, PCB) of the power circuit contains more electronic components, but the use environment of the power circuit is becoming more and more stringent. The area is getting smaller and smaller, and the ability to resist corrosion and radiation is getting bigger and bigger.
  • various electronic components 01 are generally packaged on the front and back of the packaging substrate 02 and then mounted on the PCB (in Figure 1 not shown), wherein the electronic components located on the front side of the packaging substrate 02 in FIG. 1 have been molded by the molding compound 03 .
  • Such a packaging method will result in height differences between different conductive pads (Pads) on the back of the packaging substrate 02 , for example, there is a height difference between the conductive pads 021 on the packaging substrate 02 and the conductive pads 011 on the electronic component 01 .
  • solder balls (solder ball) 041 are usually arranged on the conductive connection pads 021 of the package substrate 02, but due to the high temperature reflow soldering (solder ball) 041 reflow) is in a liquid state, so affected by tension, the maximum height is low, generally not exceeding 300 ⁇ m, which cannot solve the problem of large height differences.
  • the present application provides a package structure, its preparation method, package module and electronic equipment, which are used to solve the problem of the height difference between different conductive connection pads on the package base.
  • the present application provides a package structure, which is used to be mounted on the back of a package substrate and then mounted on a circuit board.
  • the packaging structure includes a frame board, a first electronic component, a filling material and a plurality of conductive connection pads.
  • the frame plate may be formed of any dielectric material suitable for forming a frame plate, without limitation here.
  • the frame plate has a first surface and a second surface which are opposite and arranged in parallel, and the frame plate includes a through hole, and there is a hollow area in the frame plate.
  • the application does not limit the number of hollow areas and the number of through holes, which can be designed according to actual products.
  • the present application does not limit the number of the first electronic components in the hollow area, which can be specifically designed according to the actual product.
  • the plurality of conductive connection pads may include: a first conductive connection pad located on the first surface and electrically connected to the via hole, a second conductive connection pad located on the second surface and electrically connected to the via hole, located on the first surface and The third conductive connection pad electrically connected to the first electronic component is located on the second surface and the fourth conductive connection pad is electrically connected to the first electronic component.
  • the present application does not limit the numbers of the third conductive connection pads and the fourth conductive connection pads, which are specifically determined by the structure of the first electronic component itself.
  • the second conductive connection pad and the fourth conductive connection pad are both located on the second surface.
  • the surface of the third conductive connection pad and the surface of the first conductive connection pad can be located on the same plane, thereby realizing the height of the conductive connection pad of the first electronic component, that is, the height of the third conductive connection pad and The height of the first conductive connection pad is consistent; on the second surface side, the surface of the fourth conductive connection pad can be located on the same plane as the surface of the second conductive connection pad, thereby realizing the conductive connection pad of the first electronic component, that is, the second conductive connection pad.
  • the height of the fourth conductive connection pad is consistent with the height of the second conductive connection pad.
  • electronic components are generally plastic-sealed on the front of the packaging substrate, and the conductive connection pads of the electronic components on the front of the packaging substrate are led out through the conductive connection pads arranged on the back of the packaging substrate.
  • the packaging structure provided by the embodiment of the present application is attached to the back of the packaging substrate, the first electronic component in the packaging substrate can be packaged on the back of the packaging substrate, and at the same time, the back surface of the packaging substrate can be sealed by using the through holes in the packaging structure.
  • the conductive connection pads of the package substrate are drawn out, thereby solving the problem of the height difference between the conductive connection pads on the back of the packaging substrate and the conductive connection pads of the first electronic component.
  • both the through hole and the first electronic component are packaged in the frame plate, that is, the packaging structure adopts a structure in which the through hole and the first electronic component are modularized together, so that the conductive part electrically connected to the through hole can be The connection pads and the conductive connection pads electrically connected to the first electronic components are formed on the same surface, so that the height difference of the conductive connection pads on the same surface can be controlled within 20 ⁇ m, thereby reducing the packaging structure and circuit board mounting. risks of.
  • both the through holes and the first electronic components are packaged in the frame plate, and the thickness of the frame plate can be designed according to the height of the first electronic components, so the problem of the connection between the conductive connection pads and the electronic components on the packaging substrate can be solved.
  • a plurality of first electronic components can be packaged in the packaging structure and mounted on the back of the packaging substrate through a single mounting process, which can reduce the number of mounting times, thereby improving production efficiency and reducing product processing costs.
  • the packaging structure provided by the embodiment of the present application is compatible with conventional equipment and conventional manufacturing processes, and has a simple manufacturing process and a high yield.
  • the surfaces of different conductive connection pads located on the same plane are allowed to have a height difference within a range of 20 ⁇ m.
  • the first electronic component may be an integrated chip, a switch element, a resistor, a capacitor, a magnetic core, etc., wherein the integrated chip may be a voltage conversion chip, a transformer chip, etc., which is not limited herein.
  • the thickness of the frame board can be designed according to the height of the first electronic component.
  • the heights of the first electronic components located in the hollow area are basically the same.
  • the package structure provided by the application further includes a second electronic component, and the plurality of conductive connection pads further include a The fifth conductive connection pad; the second electronic component is fixed in the hollow area through the filling material. That is, the filling material fills the gap existing after placing the first electronic component and the second electronic component in the hollow area.
  • the first electronic component and the second electronic component are packaged in the same package structure, so that they can be mounted on the back of the packaging substrate through one mounting process, which can reduce the number of mounting times, thereby improving production efficiency and Reduce product processing costs.
  • the second electronic component may be an integrated chip, a switch element, a resistor, a capacitor, a magnetic core, etc., wherein the integrated chip may be a voltage conversion chip, a transformer chip, etc., which is not limited herein.
  • the main difference between the first electronic component and the second electronic component is that both sides of the first electronic component have conductive connection pads, while only one side of the second electronic component has conductive pads. connection pad.
  • the first electronic component needs to be electrically connected to both the packaging substrate and the PCB in practical application
  • the second electronic component only needs to be electrically connected to the packaging substrate or to the PCB in practical application.
  • the height of the second electronic component is generally smaller than or equal to the height of the first electronic component.
  • the second electronic component is arranged close to the first surface side, and the filling material covers the second electronic component on the second surface side.
  • the conductive material in order to electrically connect the conductive connection pads on both sides of the through hole, may be filled in the through hole.
  • the conductive material can be formed on the sidewall of the through hole, and then the resin is filled in the area defined by the conductive material. Material.
  • the conductive material may be a metal material, such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium and the like.
  • the resin material may be materials such as epoxy resin, which is not limited herein.
  • the frame board may include at least two layers of dielectric material boards stacked; each layer of dielectric material boards has via holes in them, and one through hole may include one via hole in each dielectric material board.
  • a wiring layer is also arranged between any adjacent two layers of dielectric material plates, and the via holes of any adjacent two layers of dielectric material plates are electrically connected through the wiring layer. That is, the positions of the via holes belonging to the same via hole can be different, and different via holes are electrically connected through the wiring layer, which can make the package structure have the possibility of rewiring, so that the positions of the first conductive connection pad and the second conductive connection pad It can be set flexibly, thereby reducing the routing pressure on the packaging substrate.
  • the wiring layer may include at least one conductive layer and an insulating medium layer, and circuit wiring is arranged on the conductive layer.
  • the wiring layer includes two or more conductive layers, dielectric through holes are provided in the insulating dielectric layer for connecting circuit wiring on different conductive layers.
  • metal traces may be provided on the sidewall of the hollowed-out area of the frame plate, and the metal traces may extend from the side of the first surface to the side of the second surface through the sidewall of the hollowed-out area;
  • the conductive connection pads may further include: a sixth conductive connection pad located on the first surface and electrically connected to the metal trace, and a seventh conductive connection pad located on the second surface and electrically connected to the metal trace. That is, metal traces are used instead of through holes, so that the number of through holes in the packaging structure can be reduced.
  • metal traces may be arranged at intervals to ensure that different metal traces are insulated from each other.
  • the metal traces may be formed using materials such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., which are not limited herein.
  • the package structure may further include an interconnection circuit layer, the interconnection circuit layer is located on the second surface of the frame board, and the second conductive connection pad and the fourth conductive connection pad are both located on the interconnection circuit layer.
  • the second conductive connection pad is electrically connected to the through hole through the interconnection layer
  • the fourth conductive connection pad is electrically connected to the first electronic component through the interconnection layer. Therefore, the positions of the second conductive connection pads and the second and fourth conductive connection pads can be rearranged by using the interconnection circuit layer.
  • the present application also provides a package module, including a package substrate and a package structure according to the first aspect or various implementation manners of the first aspect mounted on the package substrate.
  • the packaging substrate may be any structure of circuits provided on a redistribution layer, a substrate, or a silicon interposer, which is not limited herein.
  • the packaging structure may be mounted and pasted on the packaging substrate by surface mounting and other technologies.
  • the packaging structure can be attached to the back of the packaging substrate, and the front of the packaging substrate is generally provided with electronic components, and the conductive connection pads of the electronic components on the front of the packaging substrate pass through the conductive connection pads on the back of the packaging substrate. lead out.
  • the packaging structure can also be mounted on the front surface of the packaging substrate, or the above packaging structure can be arranged on both sides of the packaging substrate, which is not limited here and can be designed according to actual needs.
  • the first surface side of the frame substrate in the packaging structure may face the packaging substrate, or the second surface side of the frame substrate in the packaging structure may face
  • the setting of the packaging substrate is not limited here, and can be designed according to actual requirements.
  • the packaging structure when the packaging structure is mounted on the back of the packaging substrate, the first surface side of the frame board in the packaging structure may be arranged to face the packaging substrate.
  • the packaging structure can not only package the first electronic components on the back of the packaging substrate, but also use the through holes in the packaging structure to lead out the conductive connection pads on the back of the packaging substrate, thereby solving the problem of the connection between the conductive connection pads on the back of the packaging substrate and the second.
  • the present application also provides an electronic device, including: a casing, a circuit board located in the casing, and the packaging module according to various implementations of the second aspect; the packaging module is located on the circuit board, And the packaging module is electrically connected with the circuit board.
  • the circuit board is a PCB. Since the problem-solving principle of the electronic device is similar to that of the aforementioned packaging module, the implementation of the electronic device can refer to the implementation of the aforementioned packaging module, and the repetition will not be repeated.
  • the present application also provides a method for preparing a packaging structure, which may include the following steps: step S101, forming a first conductive connection pad on the first surface of the frame board; step S102, connecting the first conductive pad in the frame board A through hole is formed in the area corresponding to the conductive connection pad; step S103, forming a hollow area in the frame plate; step S104, making the first surface of the frame plate face down, placing the first electronic component in the hollow area, and the first electronic component
  • the device has a third conductive connection pad, so that the surface of the third conductive connection pad is on the same plane as the surface of the first conductive connection pad; step S105, filling the gaps in the hollowed out area with filling material; step S105, the second The surface is ground and flattened, wherein the second surface is opposite to and parallel to the first surface; step S106, forming a fourth conductive connection pad electrically connected to the first electronic component and a first conductive connection pad electrically connected to the through hole on the second surface
  • each electronic component is packaged in the hollow area of the frame plate, and when the electronic component is placed in the hollow area, the electronic component is located on the conductive connection pad on the side of the first surface and the second hole connected to the through hole.
  • a conductive connection pad is located on the same plane.
  • the first electronic component may also include: placing the frame board formed with the first conductive connection pad and the through hole on the peelable glue; The peelable glue is peeled off after the fourth conductive connection pad electrically connected with the electronic component and the second conductive connection pad electrically connected with the through hole.
  • the material of the peelable adhesive is ultraviolet photoreleasable adhesive; the peelable adhesive can be peeled off by ultraviolet light irradiation.
  • forming a through hole in the area of the frame plate corresponding to the first conductive connection pad may include: opening a hole in the area of the frame plate corresponding to the first conductive connection pad; plating a conductive material on the side wall of the hole ; Filling the resin material in the hole plated with the conductive material.
  • the frame board may include a first dielectric material board, a second dielectric material board and a wiring layer; a first conductive connection pad is formed on the first surface of the frame board, and is connected to the first conductive connection pad in the frame board.
  • Forming a through hole in the corresponding area includes: forming a first conductive connection pad on one side surface of the first dielectric material plate; forming a first via hole in the area corresponding to the first conductive connection pad in the first dielectric material plate ;
  • a wiring layer is formed on the side of the first dielectric material board away from the first conductive connection pad, and the wiring layer is electrically connected to the first via hole of the first dielectric material board; on the side of the wiring layer away from the first dielectric material board forming a second dielectric material plate; forming a second via hole in the second dielectric material plate, and the wiring layer is electrically connected to the second via hole of the second dielectric material plate.
  • the hollow area in the frame plate after forming the hollow area in the frame plate, before filling the gaps of the hollow area with filling material, it also includes: placing a second electronic component in the hollow area, and the second electronic component has a fifth conductive connection pad , so that the surface of the fifth conductive connection pad of the second electronic component and the surface of the first conductive connection pad are located on the same plane.
  • first conductive connection pad on the first surface of the frame board may further include: forming a sixth conductive connection pad on the first surface of the frame board; forming a hollow area in the frame board Afterwards, before placing the first electronic component in the hollow area, it also includes: forming a metal wiring on the side wall of the hollow area, and electrically connecting the metal wiring to the sixth conductive connection pad;
  • the fourth conductive connection pad electrically connected to the electronic component is electrically connected to the second conductive connection pad electrically connected to the through hole, it further includes: forming a seventh conductive connection pad electrically connected to the metal wiring on the second surface. That is, metal traces are used instead of through holes, so that the number of through holes in the packaging structure can be reduced. Exemplarily, the metal traces may be formed by electroplating, which is not limited here.
  • FIG. 1 is a partial structural schematic diagram of an existing power supply circuit
  • FIG. 2 is a schematic diagram of a partial structure of a power supply circuit provided by the related art
  • FIG. 3 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a packaging structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an application scenario of the packaging structure provided by the embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a method for preparing a package structure provided in the embodiment of the present application.
  • 11a to 11k are structural schematic diagrams of the preparation process of a packaging structure provided by the embodiment of the present application.
  • 12a to 12e are partial structural schematic diagrams of the preparation process of another package structure provided by the embodiment of the present application.
  • FIG. 13 is a schematic cross-sectional structure diagram of a packaging module provided by an embodiment of the present application.
  • V2 hollow area 310 peelable glue
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • the packaging structure proposed in the embodiments of the present application can be applied to various electronic devices.
  • it can be applied to power supply circuit, microprocessor (Micro controller Unit, MCU), central processing unit (Central Processing Unit, CPU), image processor (Graphics Processing Unit, GPU), baseband (Baseband) chip, or system on chip ( System on Chip, SoC) chips, etc.
  • microprocessor Micro controller Unit, MCU
  • central processing unit Central Processing Unit, CPU
  • image processor Graphics Processing Unit, GPU
  • Baseband Baseband
  • SoC System on Chip
  • the packaging structures proposed in the embodiments of the present application are intended to include, but not be limited to, applications in these and any other suitable types of electronic devices. Exemplarily, taking the power supply circuit as an example, as shown in FIG.
  • the packaging substrate 20 includes a packaging substrate 20 and electronic components (not shown) located on both sides of the packaging substrate 20 .
  • the electronic components located between the packaging substrate and the circuit board can be packaged in the packaging structure 10 first and then mounted on the packaging substrate 20 .
  • FIG. 4 exemplarily shows a schematic cross-sectional structural view of a packaging structure 10 provided by an embodiment of the present application.
  • the package structure 10 includes a frame board 110 , a first electronic component 121 , a filling material 120 and a plurality of conductive connection pads.
  • the frame plate 110 may be formed of any dielectric material suitable for forming a frame plate, which is not limited herein.
  • the frame plate 110 has a first surface 110a and a second surface 110b which are opposite and arranged in parallel, and the frame plate 110 includes a through hole V1, and has a hollow area V2 in the frame plate 110 .
  • the application does not limit the number of hollow areas and the number of through holes, which can be designed according to actual products. Wherein, in FIG. 4 , one hollow area and four through holes are taken as examples for illustration.
  • both the filling material 120 and the first electronic component 121 are located in the hollow area V2 , and the first electronic component 121 is fixed in the hollow area V2 through the filling material 120 . That is, the first electronic component 121 and the frame board 110 are packaged together by the filling material 120 .
  • the present application does not limit the number of first electronic components 121 in the hollow area V2, which can be designed according to actual products.
  • one first electronic component 121 is set in the hollow area as an example.
  • the plurality of conductive connection pads include: a first conductive connection pad 001 located on the first surface 110a and electrically connected to the via V1, a second conductive connection pad 001 located on the second surface 110b and electrically connected to the via V1.
  • the first electronic component 121 can be electrically connected to the outside through the third conductive connection pad 003; or the first electronic component 121 can be electrically connected to the outside through the fourth conductive connection pad 004; or the first electronic component 121
  • the electrical connection with the outside can be realized through the third conductive connection pad 003 and the fourth conductive connection pad 004 .
  • the present application does not limit the numbers of the third conductive connection pads 003 and the fourth conductive connection pads 004 , which are specifically determined by the structure of the first electronic component 121 itself.
  • the first conductive connection pad 001 and the third conductive connection pad 003 are both located on the first surface 110a
  • the second conductive connection pad 002 and the fourth conductive connection pad 004 are both located on the second surface 110b.
  • the surface of the third conductive connection pad 003 and the surface of the first conductive connection pad 001 can be located on the same plane, thereby realizing the conductive connection pad of the first electronic component 121, that is, the third conductive connection.
  • the height of the pad 003 is consistent with the height of the first conductive connection pad 001; on the side of the second surface 110b, the surface of the fourth conductive connection pad 004 and the surface of the second conductive connection pad 002 can be located on the same plane, thereby realizing the first
  • the height of the conductive connection pad of the electronic component 121 that is, the fourth conductive connection pad 004 is consistent with the height of the second conductive connection pad 002 .
  • FIG. 5 is a schematic structural diagram of an application scenario of the encapsulation structure provided by the embodiment of the present application.
  • the package structure 10 provided by the embodiment of the present application is used to be mounted on the back of the package substrate 20 and then mounted on the circuit board 2 .
  • the front side of the packaging substrate 20 is generally plastic-sealed with electronic components 21, and the conductive connection pads (not shown in the figure) of the electronic components 21 on the front side of the packaging substrate 20 pass through the conductive connection pads 22 arranged on the back side of the packaging substrate 20. lead out.
  • the package structure 10 When the package structure 10 provided by the embodiment of the present application is mounted on the back of the package substrate 20, the first electronic component 121 in the package substrate 20 can be packaged on the back of the package substrate 20, and at the same time, the package structure 10 can be used
  • the through holes lead out the conductive connection pads on the back of the package substrate 20 , thereby solving the problem of the height difference between the conductive connection pads on the back of the package substrate 20 and the conductive connection pads of the first electronic component 20 .
  • the packaging structure 10 adopts a modularized structure of the through hole and the first electronic component 121, so that the through hole and the first electronic component 121 can be combined
  • the conductive connection pads electrically connected to the conductive connection pads electrically connected to the first electronic component 121 are formed on the same surface, so that the height difference of the conductive connection pads on the same surface can be controlled within 20 ⁇ m, thereby reducing the packaging structure. 10 with the risk of circuit board 2 mounting.
  • both the through holes and the first electronic components are packaged in the frame plate, and the thickness of the frame plate can be designed according to the height of the first electronic components, so the problem of the connection between the conductive connection pads and the electronic components on the packaging substrate can be solved.
  • the problem of large height differences in the conductive connection pads on the device can be solved.
  • a plurality of first electronic components 121 can be packaged in the packaging structure 10 and can be mounted on the back of the packaging substrate 20 through a single mounting process, which can reduce the number of mounting times, thereby improving production efficiency and reducing Product processing costs.
  • the packaging structure 10 provided by the embodiment of the present application is compatible with conventional equipment and conventional manufacturing processes, and has a simple manufacturing process and a high yield.
  • the surfaces of different conductive connection pads located on the same plane are allowed to have a height difference within a range of 20 ⁇ m.
  • the first electronic component 121 may be an integrated chip, a switch element, a resistor, a capacitor, a magnetic core, etc., wherein the integrated chip may be a voltage conversion chip, a transformer chip, etc., which is not limited herein.
  • the thickness L1 of the frame board 110 can be designed according to the height H1 of the first electronic component 121 .
  • the heights of the first electronic components 121 located in the hollow area are basically the same.
  • FIG. 6 is a schematic cross-sectional structure diagram of another package structure provided by an embodiment of the present application.
  • the package structure 10 provided by the present application also includes a second electronic component 122 , and the plurality of conductive connection pads also include a fifth conductive pad located on the first surface 110 a and connected to the second electronic component 122 .
  • the connection pad 005 ; the second electronic component 122 is fixed in the hollow area V2 through the filling material 120 . That is, the filling material 120 fills the gap existing after the first electronic component 121 and the second electronic component 122 are placed in the hollow area.
  • the first electronic component 121 and the second electronic component 122 are packaged in the same package structure 10, so that they can be mounted on the back of the packaging substrate 20 through one mounting process, which can reduce the number of mounting times, thereby Improve production efficiency and reduce product processing costs.
  • the second electronic component 122 may be an integrated chip, a switch element, a resistor, a capacitor, a magnetic core and the like, wherein the integrated chip may be a voltage conversion chip, a transformer chip, etc., which is not limited herein.
  • the main difference between the first electronic component 121 and the second electronic component 122 is that both sides of the first electronic component 121 have conductive connection pads, while the second electronic component 122 only has One side has conductive connection pads.
  • the first electronic component 121 needs to be electrically connected to both the packaging substrate and the PCB in practical application
  • the second electronic component 122 only needs to be electrically connected to the packaging substrate or to the PCB in practical application.
  • the height H2 of the second electronic component 122 is generally smaller than or equal to the height H1 of the first electronic component 121 .
  • the second electronic component 122 is disposed close to the side of the first surface 110a, and the filling material 120 covers the second electronic component 122 on the side of the second surface 110b.
  • the conductive material in order to electrically connect the conductive connection pads on both sides of the through hole, the conductive material may be filled in the through hole.
  • the conductive material 111 can be formed on the side of the through hole V1 wall, and then fill the area defined by the conductive material 111 with the resin material 112 .
  • the conductive material 111 may be a metal material, such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium and the like.
  • the resin material 112 may be materials such as epoxy resin, which is not limited herein.
  • the frame board 110 may include at least two layers of dielectric material boards stacked; Each layer of dielectric material plates 1101 and 1102 has a via hole in it, and one via hole may include one via hole in each dielectric material plate.
  • a wiring layer 1103 is also provided between any adjacent two layers of dielectric material plates 1101 and 1102, and the via holes of any adjacent two layers of dielectric material plates 1101 and 1102 are electrically connected through the wiring layer 1103.
  • the positions of the via holes belonging to the same via hole can be different, and different via holes are electrically connected through the wiring layer 1103, so that the package structure 10 has the possibility of rewiring, so that the first conductive connection pad 001 and the second conductive connection pad 001
  • the position of the pad 002 can be flexibly set, thereby reducing the wiring pressure on the packaging substrate 20 .
  • the wiring layer 1103 may include at least one conductive layer 1131 and an insulating medium layer 1132 , and circuit wiring is disposed on the conductive layer 1131 .
  • the wiring layer 1103 includes two or more conductive layers 1131 , dielectric through holes are provided in the insulating dielectric layer 1132 for connecting circuit wiring on different conductive layers 1131 .
  • FIG. 8 is a schematic cross-sectional structure diagram of another package structure provided by an embodiment of the present application.
  • metal traces 123 may be provided on the sidewall of the hollowed-out area V2 of the frame plate 110, and the metal traces 123 may extend from the side of the first surface 110a to the second surface 110b through the sidewall of the hollowed-out area V2.
  • the plurality of conductive connection pads may also include: a sixth conductive connection pad 006 located on the first surface 110a and electrically connected to the metal wiring 123 and a sixth conductive connection pad 006 located on the second surface 110b and electrically connected to the metal wiring 123
  • the seventh conductive connection pad 007 that is, the metal traces 123 are used instead of the through holes, so that the number of the through holes V1 in the package structure 10 can be reduced.
  • metal traces may be arranged at intervals to ensure that different metal traces are insulated from each other.
  • the metal traces may be formed using materials such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., which are not limited herein.
  • FIG. 9 is a schematic cross-sectional structure diagram of another package structure provided by an embodiment of the present application.
  • the package structure 10 may further include an interconnect circuit layer 210, the interconnect circuit layer 210 is located on the second surface 110b of the frame board 110, and the second conductive connection pad 002 and the fourth conductive connection pad 004 are located on On the interconnection layer 210 , the second conductive connection pad 002 is electrically connected to the through hole through the interconnection layer 210 , and the fourth conductive connection pad 004 is electrically connected to the first electronic component 121 through the interconnection layer 210 . Therefore, the positions of the second conductive connection pad 002 and the second fourth conductive connection pad 004 can be rearranged by using the interconnection circuit layer 210 .
  • the interconnection layer 210 may include an insulating dielectric layer 212 and at least two conductive layers 211, each conductive layer 211 is provided with circuit wiring, and the insulating dielectric layer 212 is provided with dielectric perforations for connecting different conductive layers. Circuit routing on layer 211.
  • FIG. 10 is a method for preparing a package structure provided in the embodiment of the present application.
  • the method may include the following steps:
  • Step S101 forming a first conductive connection pad on the first surface of the frame board.
  • the frame plate 110 may be formed of a dielectric material, and the frame plate 110 has a first surface 110a and a second surface 110b that are opposite and arranged in parallel.
  • the thickness of the frame board can be designed according to the height of the first electronic component.
  • a copper layer may be electroplated on the first surface of the frame board 110 , and then the copper layer may be etched to form a first conductive connection pad 001 .
  • Step S102 forming a through hole in a region of the frame plate 110 corresponding to the first conductive connection pad 001 .
  • a hole is drilled in a region of the frame plate 110 corresponding to the first conductive connection pad 001 by means of mechanical drilling.
  • a conductive material 111 may be plated on the sidewall of the hole first; then, as shown in FIG. 11e, a resin material 112 is filled in the hole plated with the conductive material 111 to form a through hole V1 .
  • the frame plate 110 may also be formed by a multi-layer dielectric material plate.
  • the frame plate 110 is formed by two layers of dielectric material plates as an example.
  • step S101 the first surface of the frame plate
  • the forming of the first conductive connection pad and the step S102 of forming a through hole in the region of the frame board corresponding to the first conductive connection pad may include:
  • a first conductive connection pad 001 is formed on one side surface of a first dielectric material plate 1101 .
  • a first via hole is formed in a region of the first dielectric material plate 1101 corresponding to the first conductive connection pad 001 .
  • mechanical drilling may be performed at the region corresponding to the first conductive connection pad 001 in the first dielectric material board, so as to form the first via hole, and then the side wall of the first via hole is plated with conductive material 111 , and then fill the resin material 112 in the first via hole plated with the conductive material 111 .
  • a wiring layer 1103 is formed on the side of the first dielectric material plate 1101 away from the first conductive connection pad 001 , and the wiring layer 1103 is electrically connected to the first via hole of the first dielectric material plate 1101 .
  • the wiring layer 1103 may include at least one conductive layer 113 and an insulating medium layer 114 , and circuit wiring is disposed on the conductive layer 113 .
  • the wiring layer 1103 includes two or more conductive layers 113 , dielectric through holes are provided in the insulating dielectric layer 114 for connecting circuit wiring on different conductive layers 113 .
  • a second dielectric material plate 1102 is formed on a side of the wiring layer 1103 away from the first dielectric material plate 1101 .
  • a second via hole is formed in the second dielectric material plate 1102 , and the wiring layer 1103 is electrically connected to the second via hole of the second dielectric material plate 1102 .
  • the surface of the first dielectric material plate 1101 provided with the first conductive connection pad 001 is the first surface 110a of the frame case 110
  • the surface of the second dielectric material plate 1102 away from the first conductive connection pad 001 is the first surface 110a of the frame case 110.
  • Two surfaces 110b Two surfaces 110b.
  • mechanical drilling may be performed in the second dielectric material plate 1102 at a region corresponding to the second conductive connection pad 002 to be formed, so as to form the second via hole, and then plated on the side wall of the second via hole
  • the conductive material 111 is coated, and then the resin material 112 is filled in the second via hole coated with the conductive material 111 .
  • Step S103 as shown in FIG. 11f , forming a hollow area V2 in the frame plate 110 .
  • a milling cutter may be used to form a hollow area in the frame plate.
  • Step S104 make the first surface of the frame board face down, place the first electronic component in the hollow area, and the first electronic component has a third conductive connection pad, connect the surface of the third conductive connection pad to the first conductive
  • the surfaces of the pads lie on the same plane.
  • the first surface 110a of the frame plate 110 faces downward, and a first conductive connection pad 001, a through hole V1, and The frame plate 110 of conductive material 111 is placed on the peelable glue 310 .
  • the position of the first electronic component 121 is fixed by the adhesiveness of the peelable adhesive 310 .
  • the material of the peelable adhesive may be ultraviolet light-induced peelable adhesive, and the ultraviolet light-induced peelable adhesive may lose its viscosity after being irradiated with ultraviolet light.
  • the first electronic component 121 is placed in the hollow area V2, and the first electronic component 121 has a third conductive connection pad 003, so that the surface of the third conductive connection pad 003 is in contact with the first conductive connection pad 001 surfaces lie on the same plane.
  • the second electronic component 122 can also be placed in the hollow area V2, and the second electronic component 122 has a fifth conductive connection pad 005 , so that the surface of the fifth conductive connection pad 005 and the surface of the first conductive connection pad 001 are on the same plane.
  • all electronic components can be mounted in the hollowed-out area by using a Surface Mounted Technology (SMT) machine.
  • SMT Surface Mounted Technology
  • Step S105 as shown in FIG. 11 i , filling the filling material 120 in the gap of the hollow area.
  • a glue dispensing machine can be used to dispense filling material, such as filling glue, at the gap between the electronic components and the frame plate in the hollowed out area, and fill up the hollowed out area.
  • Step S106 smoothing the second surface of the frame plate 110 .
  • the second surface of the frame plate 110 is ground until the conductive connection of the first electronic component 121 is exposed, so that the second surface electrically connected to the first electronic component 121 is subsequently formed on the second surface.
  • Four conductive connection pads are provided.
  • Step S107 as shown in FIG. 11 k , form a fourth conductive connection pad 004 electrically connected to the first electronic component 121 and a second conductive connection pad 002 electrically connected to the through hole on the second surface 110 b.
  • a copper layer may be electroplated on the second surface first, and then the copper layer may be etched to form the second conductive connection pad and the fourth conductive connection pad.
  • the peelable glue 310 when the first surface is placed on the peelable glue, after the second conductive connection pad 002 and the fourth conductive connection pad 004 are formed, the peelable glue 310 needs to be peeled off, so as to form the Encapsulation structure 10.
  • the peelable adhesive when the peelable adhesive is an ultraviolet photo-releasable adhesive, the ultraviolet light-induced peelable adhesive can be irradiated with ultraviolet light to lose its viscosity, and then the peelable adhesive can be peeled off from the side of the first surface.
  • packaging structure In practice, when preparing the packaging structure, generally multiple packaging structures are prepared on a large frame board, and multiple independent packaging structures can be formed by sticking the sheets after peeling off the peelable adhesive.
  • multiple packaging structures can be mounted on multiple packaging substrates at the same time before the order is cut, and then the order can be placed, which can further improve production efficiency.
  • a single package structure can also be attached after the order is placed. On a single package substrate, there is no limitation here.
  • each electronic component is packaged in the hollow area of the frame plate, and when the electronic component is placed in the hollow area, the electronic component is located on the conductive connection pad on the side of the first surface and the second hole connected to the through hole.
  • a conductive connection pad is located on the same plane.
  • first conductive connection pad on the first surface of the frame board may further include: forming a sixth conductive connection pad on the first surface of the frame board; forming a hollow area in the frame board Afterwards, before placing the first electronic component in the hollow area, it also includes: forming a metal wiring on the side wall of the hollow area, and electrically connecting the metal wiring to the sixth conductive connection pad;
  • the fourth conductive connection pad electrically connected to the electronic component is electrically connected to the second conductive connection pad electrically connected to the through hole, it further includes: forming a seventh conductive connection pad electrically connected to the metal wiring on the second surface. That is, metal traces are used instead of through holes, so that the number of through holes in the packaging structure can be reduced. Exemplarily, the metal traces may be formed by electroplating, which is not limited here.
  • the present application also provides a packaging module 3, including a packaging substrate 20 and a packaging structure 10 mounted on the packaging substrate 20.
  • the packaging structure 10 is the above-mentioned Any package structure 10 . Since the problem-solving principle of the packaging module 3 is similar to that of the aforementioned packaging structure 10 , the implementation of the packaging module 3 can refer to the implementation of the aforementioned packaging structure 10 , and repeated descriptions will not be repeated.
  • the packaging substrate may be any structure of circuits provided on a redistribution layer, a substrate, or a silicon interposer, and is not limited herein.
  • the package structure may be mounted and attached on the package substrate by SMT and other technologies.
  • the packaging structure 10 can be attached to the back of the packaging substrate 20, the front of the packaging substrate 20 is generally provided with electronic components 21, and the conductive connection pads of the electronic components 21 on the front of the packaging substrate 20 (not shown in the figure) shown) are led out through the conductive connection pads 22 provided on the back of the package substrate 20 .
  • the packaging structure can also be mounted on the front surface of the packaging substrate, or the above packaging structure can be arranged on both sides of the packaging substrate, which is not limited here and can be designed according to actual needs.
  • the first surface side of the frame substrate in the packaging structure may face the packaging substrate, or the second surface side of the frame substrate in the packaging structure may face
  • the setting of the packaging substrate is not limited here, and can be designed according to actual requirements.
  • the packaging structure 10 can not only package the first electronic component 121 on the back of the packaging substrate 20, but also use the through holes in the packaging structure 10 to lead out the conductive connection pads on the back of the packaging substrate 20, thereby solving the problem of the back surface of the packaging substrate 20.
  • the problem of the height difference between the conductive connection pads of the first electronic component 20 and the conductive connection pads of the first electronic component 20 is not only package the first electronic component 121 on the back of the packaging substrate 20, but also use the through holes in the packaging structure 10 to lead out the conductive connection pads on the back of the packaging substrate 20, thereby solving the problem of the back surface of the packaging substrate 20.
  • the packaging structure 10 adopts a structure in which the through hole and the first electronic component 121 are modularized, the tolerances of the packaging structure 10 itself will basically not affect the conductive connection pads whose surfaces are located in the same plane. Therefore, the height difference between the second conductive connection pad 002 and the fourth conductive connection pad 004, and the height difference between the first conductive connection pad 001 and the third conductive connection pad 003 can be controlled within 20 ⁇ m, thereby reducing the upper surface of the packaging module. board risk.
  • a plurality of first electronic components 121 can be packaged in the package structure 10 and mounted on the back of the package substrate 20 through one mounting process. Compared with each first electronic component in the related art 121 and the elevated plate are mounted separately, which can significantly reduce the number of mounting times, thereby improving production efficiency and reducing product processing costs.
  • the present application also provides an electronic device, as shown in FIG. , and the packaging module 3 is electrically connected to the circuit board 2 .
  • the circuit board may be a PCB. Since the problem-solving principle of the electronic device is similar to that of the packaging module 3 mentioned above, the implementation of the electronic device can refer to the implementation of the packaging module 3 mentioned above, and the repetition will not be repeated.
  • the electronic device may be a power circuit, which is used to perform functions such as conversion, distribution, detection, and other power management and control of electric energy.
  • the electronic device may also be a microprocessor, a central processing unit, an image processor, a baseband chip, or a system-on-chip chip.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本申请公开了一种封装结构、其制备方法、封装模组及电子设备。其中，在封装结构中包括框架板、第一电子元器件、填充材料和多个导电连接垫；框架板具有第一表面和第二表面，框架板中有通孔和镂空区域；第一电子元器件通过填充材料固定于镂空区域内；多个导电连接垫包括与通孔电连接的且位于第一表面上的第一导电连接垫和位于第二表面上的第二导电连接垫，与第一电子元器件电连接且位于第一表面上的第三导电连接垫和位于第二表面上的第四导电连接垫。由于与通孔电连接的导电连接垫和与第一电子元器件电连接的导电连接垫形成在同一表面上，这样就可以使位于同一表面上的导电连接垫的高度差控制在20μm内，从而降低封装结构与电路板装贴的风险。

Description

封装结构、其制备方法、封装模组及电子设备 技术领域
本申请涉及半导体封装技术领域，尤指一种封装结构、其制备方法、封装模组及电子设备。
背景技术
随着通信技术的发展，对为通信装置供电的电源电路的需求也越来越多。为了实现较高效率的功率变换，电源电路的印刷电路板(Printed Circuit Board，PCB)上包含的电子元器件较多，但是电源电路的使用环境却越来越严苛，例如要求电源电路占版面积越来越小、抗腐蚀与抗辐射能力越来越大。为了减小电源电路占板面积即减小PCB的面积，如图1所示，一般会将各种电子元器件01分别封装在封装基板02的正面和背面后再装贴在PCB(图1中未示出)上，其中图1中位于封装基板02正面的电子元器件已经被塑封料03塑封。而这样的封装方式会导致封装基板02背面不同导电连接垫(Pad)之间存在高度差，例如封装基板02上的导电连接垫021与电子元器件01上的导电连接垫011存在高度差。
为了解决不同导电连接垫之间存在的高度差问题，如图2所示，通常在封装基板02的导电连接垫021上设置焊球(solder ball)041，但是由于焊球041在高温回流焊(reflow)时为液态，因此受张力的影响，最大高度较低，一般不超过300μm，无法解决大的高度差问题。
发明内容
本申请提供了一种封装结构、其制备方法、封装模组及电子设备，用于解决封装基上不同导电连接垫之间的高度差的问题。
第一方面，本申请提供的一种该封装结构，该封装结构用于装贴于封装基板的背面后再装贴在电路板上。该封装结构包括框架板、第一电子元器件、填充材料和多个导电连接垫。该框架板可以由任何适合形成框架板的电介质材料形成，在此不作限定。其中，框架板具有相对且平行设置的第一表面和第二表面，且该框架板包括通孔，且该框架板中具有镂空区域。本申请对镂空区域的数量以及通孔的数量不作限定，具体可以根据实际产品进行设计。填充材料和第一电子元器件均位于镂空区域内，且第一电子元器件通过填充材料固定于镂空区域内。即通过填充材料将第一电子元器件与框架板封装在一起。本申请对镂空区域内第一电子元器件的数量不作限定，具体可以根据实际产品进行设计。多个导电连接垫可以包括：位于第一表面上且与通孔电连接的第一导电连接垫，位于第二表面上且与通孔电连接的第二导电连接垫，位于第一表面上且与第一电子元器件电连接的第三导电连接垫位于第二表面上且与第一电子元器件电连接的第四导电连接垫。本申请对第三导电连接垫和第四导电连接垫的数量不作限定，具体由第一电子元器件的自身结构决定。
在本申请中，由于第一导电连接垫和第三导电连接垫均位于第一表面上，第二导电连接垫和第四导电连接垫均位于第二表面上。这样，在第一表面一侧，可以使第三导电连接垫的表面与第一导电连接垫的表面位于同一平面，从而实现第一电子元器件的导电连接垫即第三导电连接垫的高度与第一导电连接垫的高度一致；在第二表面一侧，可以使第四导 电连接垫的表面与第二导电连接垫的表面位于同一平面，从而实现第一电子元器件的导电连接垫即第四导电连接垫的高度与第二导电连接垫的高度一致。
在实际应用中，封装基板的正面一般塑封有电子元器件，封装基板正面的电子元器件的导电连接垫通过设置在封装基板背面的导电连接垫引出。当本申请实施例提供的封装结构装贴于封装基板背面时，既可以将封装基板中的第一电子元器件封装在封装基板的背面，同时又可以利用封装结构中的通孔将封装基板背面的导电连接垫引出，从而解决封装基板背面的导电连接垫与第一电子元器件的导电连接垫存在的高度差的问题。并且，由于通孔与第一电子元器件均封装在框架板中，即该封装结构采用的是将通孔与第一电子元器件同一模块化的结构，从而可以将与通孔电连接的导电连接垫和与第一电子元器件电连接的导电连接垫形成在同一表面上，这样就可以使位于同一表面上的导电连接垫的高度差控制在20μm内，从而降低封装结构与电路板装贴的风险。并且，本申请中，将通孔和第一电子元器件均封装在框架板中，框架板的厚度可以根据第一电子元器件的高度设计，因此可以解决封装基板上的导电连接垫与电子元器件上的导电连接垫存在的大高度差的问题。另外，本申请中，可以将多个第一电子元器件封装于封装结构中通过一次装贴工艺就可以装贴在封装基板的背面，可以减少装贴次数，从而提高生产效率和降低产品加工成本。并且，本申请实施例提供的封装结构可以兼容常规设备和常规制程，制程简单，良率高。
需要说明的是，本申请实施例中，“位于同一平面”的概念并不是严格意义上的位于同一平面，在封装结构的制备过程中，由于制备工艺和制备设备的影响，可能存在并非严格位于同一平面的情况，这种情况是由于具体制备流程导致的，并不能说明不严格位于同一平面的情况超脱本申请的保护范围。此外，对于“平行”这种位置关系也有类似理解，此处不再赘述。
在具体实施时，本申请中位于同一平面的不同导电连接垫的表面允许存在20μm范围内高度差。
示例性的，第一电子元器件可以为集成芯片、开关元件、电阻、电容、磁芯等元件，其中，集成芯片可以电压变换芯片、变压器芯片等，在此不作限定。
在具体实施时，框架板的厚度可以根据第一电子元器件的高度进行设计。在本申请中，位于镂空区域的各第一电子元器件的高度基本上一致。
示例性的，在本申提供的封装结构中，在本申提供的封装结构中还包括第二电子元器件，多个导电连接垫还包括位于第一表面上且与第二电子元器件连接的第五导电连接垫；第二电子元器件通过填充材料固定于镂空区域内。即填充材料填充镂空区域内放置第一电子元器件和第二电子元器件之后存在的间隙。本申请中，将第一电子元器件和第二电子元器件封装于同一封装结构中，这样通过一次装贴工艺就可以装贴在封装基板的背面，可以减少装贴次数，从而提高生产效率和降低产品加工成本。
示例性的，第二电子元器件可以为集成芯片、开关元件、电阻、电容、磁芯等元件，其中，集成芯片可以电压变换芯片、变压器芯片等，在此不作限定。
需要说明的是，本申请中，第一电子元器件与第二电子元器件的主要区别在于，第一电子元器件的两侧均具有导电连接垫，而第二电子元器件仅有一侧具有导电连接垫。示例性的，第一电子元器件在实际应用时需要与封装基板以及PCB均电连接，第二电子元器件在实际应用时仅需要与封装基板或与PCB电连接。在具体实施时，第二电子元器件的高度一般小于或等于第一电子元器件的高度。第二电子元器件靠近第一表面一侧设置，在第二 表面一侧，填充材料覆盖第二电子元器件。
在具体实施时，为了使通孔两侧的导电连接垫实现电连接，可以使导电材填充于通孔内。但是，当框架板的厚度比较厚时，导电材料完全填充通孔的工艺会比较难，示例性的，可以将导电材料形成于通孔的侧壁，然后再在导电材料限定的区域内填充树脂材料。
示例性的，导电材料可以为金属材料，例如金、银、铝、锌、铜、铬、镍、钯等。树脂材料可以为环氧树脂等材料，在此不作限定。
示例性的，框架板可以包括层叠设置的至少两层介电材料板；每一层介电材料板和中均具有过孔，一个通孔可以包括每一介电材料板中的一个过孔。在任意相邻两层介电材料板之间还设置有布线层，且任意相邻两层介电材料板的过孔通过布线层电连接。即属于同一通孔的各过孔的位置可以不相同，不同过孔通过布线层电连接，这样可以使得封装结构具有再布线的可能，从而使第一导电连接垫和第二导电连接垫的位置可以灵活设置，从而减少封装基板的走线压力。
示例性的，布线层可以包括至少一层导电层和绝缘介质层，导电层上设置有电路布线。当布线层包括两层或者多层导电层时，绝缘介质层中则会设置有介质穿孔用于连通不同导电层上的电路布线。
可选的，在封装结构中，可以在框架板的镂空区域的侧壁设置金属走线，金属走线可以由第一表面一侧经镂空区域的侧壁延伸至第二表面一侧；多个导电连接垫还可以包括：位于所述第一表面上且与金属走线电连接的第六导电连接垫和位于第二表面上且与金属走线电连接的第七导电连接垫。即利用金属走线代替通孔，从而可以减少封装结构中的通孔的数量。
本申请对金属走线的数量不作限定，具体根据实际产品进行设计。当金属走线为多条是，金属走线之间可以间隔设置，以保证不同金属走线之间相互绝缘。
示例性的，金属走线可以采用金、银、铝、锌、铜、铬、镍、钯等材料形成，在此不作限定。
可选的，在本申请中，该封装结构中还可以包括互连线路层，互连线路层位于框架板的第二表面上，第二导电连接垫和第四导电连接垫均位于互连线路层上，第二导电连接垫通过互连线路层与通孔电连接，第四导电连接垫通过互连线路层与第一电子元器件电连接。从而利用互连线路层使第二导电连接垫和第二四导电连接垫的位置可以重新布局。
第二方面，本申请还提供了一种封装模组，包括封装基板和装贴于该封装基板上的如第一方面或第一方面的各种实施方式的封装结构。
在具体实施时，封装基板可以为重布线层、基板或者硅中介板等设置有的线路的任意结构，在此不作限定。
示例性的，封装结构可以通过表面贴装等技术实装贴于该封装基板上。
在一种实施例中，封装结构可以装贴于封装基板的背面，封装基板的正面一般设置有电子元器件，封装基板正面的电子元器件的导电连接垫通过设置在封装基板背面的导电连接垫引出。
当然，在具体实施时，也可以将封装结构装贴于封装基板的正面，或者，在封装基板的两侧均设置上述封装结构，在此不作限定，可以根据实际需求进行设计。
进一步的，在本申请中，封装结构装贴于封装基板时，可以是封装结构中框架基板的第一表面一侧面向封装基板设置，也可以是封装结构中框架基板的第二表面一侧面向封装 基板设置，在此不作限定，可以根据实际需求进行设计。
示例性的，在本申请中，当封装结构装贴于封装基板的背面时，可以将封装结构中框架板的第一表面一侧面向封装基板设置。这样，封装结构既可以将第一电子元器件封装在封装基板的背面，同时又可以利用封装结构中的通孔将封装基板背面的导电连接垫引出，从而解决封装基板背面的导电连接垫与第一电子元器件的导电连接垫存在的高度差的问题。
第三方面，本申请还提供了一种电子设备，包括：壳体、位于所述壳体内的电路板和如第二方面的各种实施方式的封装模组；封装模组位于电路板上，且封装模组与电路板电连接。示例性的，该电路板为PCB。由于该电子设备解决问题的原理与前述一种封装模组相似，因此该电子设备的实施可以参见前述封装模组的实施，重复之处不再赘述。
第四方面，本申请还提供了一种封装结构的制备方法，可以包括以下步骤：步骤S101、在框架板的第一表面上形成第一导电连接垫；步骤S102、在框架板中与第一导电连接垫对应的区域形成通孔；步骤S103、在框架板中形成镂空区域；步骤S104、使框架板的第一表面朝下，在镂空区域内放置第一电子元器件，且第一电子元器件具有第三导电连接垫，使第三导电连接垫的表面与第一导电连接垫的表面处于同一平面；步骤S105、在镂空区域的间隙处填充填充材料；步骤S105、对框架板的第二表面进行磨平处理，其中，第二表面与第一表面相对且平行；步骤S106、在第二表面上形成与第一电子元器件电连接的第四导电连接垫和与通孔电连接的第二导电连接垫。
在本申请中，将各电子元器件封装在框架板的镂空区域内，在镂空区域内放置电子元器件时，使电子元器件位于第一表面一侧的导电连接垫和与通孔连接的第一导电连接垫位于同一平面。而将各电子元器件封装在框架板的镂空区域后，对框架板的第二表面进行磨平处理，可以使与电子元器件连接的导电连接垫和与通孔连接的第二导电连接垫是在框架板的同一平面上形成的，从而可以使封装结构位于同一平面的导电连接垫的高度差控制在20μm内。
可选地，在镂空区域内放置第一电子元器件之前，还可以包括：将形成有第一导电连接垫和通孔的框架板放置于可剥离胶上；在第二表面上形成与第一电子元器件电连接的第四导电连接垫和与通孔电连接的第二导电连接垫之后剥离可剥离胶。
示例性的，可剥离胶的材料为紫外光致可剥离胶；可以通过紫外光照射剥离可剥离胶。
示例性的，在框架板中与第一导电连接垫对应的区域形成通孔，可以包括：在框架板中与第一导电连接垫对应的区域进行开孔；在孔的侧壁镀覆导电材料；在镀覆有导电材料的孔内填充树脂材料。
可选地，框架板可以包括第一介电材料板、第二介电材料板和布线层；在框架板的第一表面上形成第一导电连接垫，在框架板中与第一导电连接垫对应的区域形成通孔，包括：在第一介电材料板的一侧表面上形成第一导电连接垫；在第一介电材料板中与第一导电连接垫对应的区域形成第一过孔；在第一介电材料板远离第一导电连接垫一侧形成布线层，且布线层与第一介电材料板的第一过孔电连接；在布线层远离第一介电材料板一侧形成第二介电材料板；在第二介电材料板中形成第二过孔，且布线层与第二介电材料板的第二过孔电连接。
示例性的，在框架板中形成镂空区域之后，在镂空区域的间隙处填充填充材料之前，还包括：在镂空区域内放置第二电子元器件，且第二电子元器件具有第五导电连接垫，使 第二电子元器件的第五导电连接垫的表面与第一导电连接垫的表面位于同一平面。
可选地，在本申请中，在框架板的第一表面上形成第一导电连接垫时还可以包括：在框架板的第一表面上形成第六导电连接垫；在框架板中形成镂空区域之后，在镂空区域内放置第一电子元器件之前，还包括：在镂空区域的侧壁形成金属走线，且金属走线与第六导电连接垫电连接；在第二表面上形成与第一电子元器件电连接的第四导电连接垫和与通孔电连接的第二导电连接垫时，还包括：在第二表面上形成与金属走线电连接的第七导电连接垫。即利用金属走线代替通孔，从而可以减少封装结构中的通孔的数量。示例性的，金属走线可以通过电镀方式形成，在此不作限定。
第二方面至第四方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1为现有的电源电路的局部结构示意图；
图2为相关技术提供的一种电源电路的局部结构示意图；
图3为本申请实施例提供的一种电子设备的结构示意图；
图4为本申请实施例提供的一种封装结构的剖面结构示意图；
图5为本申请实施例提供的封装结构一种应用场景的示意图；
图6为本申请实施例提供的又一种封装结构的剖面结构示意图；
图7为本申请实施例提供的又一种封装结构的剖面结构示意图；
图8为本申请实施例提供的又一种封装结构的剖面结构示意图；
图9为本申请实施例提供的又一种封装结构的剖面结构示意图；
图10为本申请实施例提供的一种封装结构的制备方法的流程示意图；
图11a至图11k为本申请实施例提供的一种封装结构的制备过程的结构示意图；
图12a至图12e为本申请实施例提供的又一种封装结构的制备过程的部分结构示意图；
图13为本申请实施例提供的一种封装模组的剖面结构示意图。
附图标记说明：
1            壳体；                     2           电路板；
3            封装模组；                 10          封装结构；
20           封装基板；                 110         框架板；
110a         第一表面；                 110b        第二表面；
001          第一导电连接垫；           002         第二导电连接垫；
003          第三导电连接垫；           004         第四导电连接垫；
005          第五导电连接垫；           111         导电材料；
120          填充材料；                 121         第一电子元器件；
122          第二电子元器件；           1101        第一介电材料板；
1102         第二介电材料板；           1103        布线层；
210          互连线路层；               V1          通孔；
V2           镂空区域；                 310         可剥离胶；
21           封装基板正面的电子元器件；
22           封装基板背面的导电连接垫；
L1             框架板的厚度；
H1             第一电子元器件的高度；
H2             第二电子元器件的高度；
1131           布线层的导电层；
1132           布线层的绝缘介质层；
211            互连线路层的导电层；
212            互连线路层的绝缘介质层。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本申请的描述中，需要说明的是，术语“中”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本发明保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
为了方便理解本申请实施例提供的封装结构，首先说明一下其应用场景。本申请实施例提出的封装结构可以应用于各种电子设备中。例如可以应用于电源电路、微处理器(Micro controller Unit，MCU)、中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)、基带(Baseband)芯片、或者片上***(System on Chip，SoC)芯片等。应注意，本申请实施例提出的封装结构旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。示例性的，以电源电路为例，如图3所示，电子设备包含壳体1以及设置在壳体1内的电路板2，该电路板2上设置有封装模组3，封装模组3中包括封装基板20和位于封装基板20两侧的电子元器件(图中未示出)。为了减小封装模组3上板的风险，可以将位于封装基板与电路板之间的电子元器件可以先封装于封装结构10后再装贴在封装基板20上。下面将结合附图对本申请作进一步地详细描述。
图4示例性示出了本申请实施例提供的一种封装结构10的剖面结构示意图。参见图4，该封装结构10包括框架板110、第一电子元器件121、填充材料120和多个导电连接垫。该框架板110可以由任何适合形成框架板的电介质材料形成，在此不作限定。其中，框架 板110具有相对且平行设置的第一表面110a和第二表面110b，且该框架板110包括通孔V1，且该框架板110中具有镂空区域V2。本申请对镂空区域的数量以及通孔的数量不作限定，具体可以根据实际产品进行设计。其中，图4中以1个镂空区域和4个通孔为例进行示意。
继续参见图4，其中，填充材料120和第一电子元器件121均位于镂空区域V2内，且第一电子元器件121通过填充材料120固定于镂空区域V2内。即通过填充材料120将第一电子元器件121与框架板110封装在一起。本申请对镂空区域V2内第一电子元器件121的数量不作限定，具体可以根据实际产品进行设计，图4中以镂空区域内设置有1个第一电子元器件121为例进行示意。
继续参见图4，多个导电连接垫包括：位于第一表面110a上且与通孔V1电连接的第一导电连接垫001，位于第二表面110b上且与通孔V1电连接的第二导电连接垫002，位于第一表面110a上且与第一电子元器件121电连接的第三导电连接垫003，位于第二表面110b上且与第一电子元器件121电连接的第四导电连接垫004。第一电子元器件121可以通过第三导电连接垫003实现与外部的电连接；或者第一电子元器件121可以通过第四导电连接垫004实现与外部的电连接；或者第一电子元器件121可以通过第三导电连接垫003和第四导电连接垫004实现与外部的电连接。本申请对第三导电连接垫003和第四导电连接垫004的数量不作限定，具体由第一电子元器件121的自身结构决定。
在本申请中，由于第一导电连接垫001和第三导电连接垫003均位于第一表面110a上，第二导电连接垫002和第四导电连接垫004均位于第二表面110b上。这样，在第一表面110a一侧，可以使第三导电连接垫003的表面与第一导电连接垫001的表面位于同一平面，从而实现第一电子元器件121的导电连接垫即第三导电连接垫003的高度与第一导电连接垫001的高度一致；在第二表面110b一侧，可以使第四导电连接垫004的表面与第二导电连接垫002的表面位于同一平面，从而实现第一电子元器件121的导电连接垫即第四导电连接垫004的高度与第二导电连接垫002的高度一致。
参见图5，图5为本申请实施例提供的封装结构的一种应用场景的结构示意图。如图5所示，本申请实施例提供的封装结构10，用于装贴于封装基板20的背面后再装贴在电路板2上。在实际应用中，封装基板20的正面一般塑封有电子元器件21，封装基板20正面的电子元器件21的导电连接垫(图中未示出)通过设置在封装基板20背面的导电连接垫22引出。当本申请实施例提供的封装结构10装贴于封装基板20背面时，既可以将封装基板20中的第一电子元器件121封装在封装基板20的背面，同时又可以利用封装结构10中的通孔将封装基板20背面的导电连接垫引出，从而解决封装基板20背面的导电连接垫与第一电子元器件20的导电连接垫存在的高度差的问题。并且，由于通孔与第一电子元器件121均封装在框架板110中，即该封装结构10采用的是将通孔与第一电子元器件121同一模块化的结构，从而可以将与通孔电连接的导电连接垫和与第一电子元器件121电连接的导电连接垫形成在同一表面上，这样就可以使位于同一表面上的导电连接垫的高度差控制在20μm内，从而降低封装结构10与电路板2装贴的风险。并且，本申请中，将通孔和第一电子元器件均封装在框架板中，框架板的厚度可以根据第一电子元器件的高度设计，因此可以解决封装基板上的导电连接垫与电子元器件上的导电连接垫存在的大高度差的问题。另外，本申请中，可以将多个第一电子元器件121封装于封装结构10中通过一次装贴工艺就可以装贴在封装基板20的背面，可以减少装贴次数，从而提高生产效 率和降低产品加工成本。并且，本申请实施例提供的封装结构10可以兼容常规设备和常规制程，制程简单，良率高。
需要说明的是，本申请实施例中，“位于同一平面”的概念并不是严格意义上的位于同一平面，在封装结构的制备过程中，由于制备工艺和制备设备的影响，可能存在并非严格位于同一平面的情况，这种情况是由于具体制备流程导致的，并不能说明不严格位于同一平面的情况超脱本申请的保护范围。此外，对于“平行”这种位置关系也有类似理解，此处不再赘述。
在具体实施时，本申请中位于同一平面的不同导电连接垫的表面允许存在20μm范围内高度差。
示例性的，第一电子元器件121可以为集成芯片、开关元件、电阻、电容、磁芯等元件，其中，集成芯片可以电压变换芯片、变压器芯片等，在此不作限定。
在具体实施时，框架板110的厚度L1可以根据第一电子元器件121的高度H1进行设计。在本申请中，位于镂空区域的各第一电子元器件121的高度基本上一致。
示例性的，参见图6，图6为本申请实施例提供的另一种封装结构的剖面结构示意图。如图6所示，在本申提供的封装结构10中还包括第二电子元器件122，多个导电连接垫还包括位于第一表面110a上且与第二电子元器件122连接的第五导电连接垫005；第二电子元器件122通过填充材料120固定于镂空区域V2内。即填充材料120填充镂空区域内放置第一电子元器件121和第二电子元器件122之后存在的间隙。本申请中，将第一电子元器件121和第二电子元器件122封装于同一封装结构10中，这样通过一次装贴工艺就可以装贴在封装基板20的背面，可以减少装贴次数，从而提高生产效率和降低产品加工成本。
示例性的，第二电子元器件122可以为集成芯片、开关元件、电阻、电容、磁芯等元件，其中，集成芯片可以电压变换芯片、变压器芯片等，在此不作限定。
需要说明的是，本申请中，第一电子元器件121与第二电子元器件122的主要区别在于，第一电子元器件121的两侧均具有导电连接垫，而第二电子元器件122仅有一侧具有导电连接垫。示例性的，第一电子元器件121在实际应用时需要与封装基板以及PCB均电连接，第二电子元器件122在实际应用时仅需要与封装基板或与PCB电连接。在具体实施时，如图6所示，第二电子元器件122的高度H2一般小于或等于第一电子元器件121的高度H1。第二电子元器件122靠近第一表面110a一侧设置，在第二表面110b一侧，填充材料120覆盖第二电子元器件122。
在具体实施时，为了使通孔两侧的导电连接垫实现电连接，可以使导电材填充于通孔内。但是，当框架板110的厚度比较厚时，导电材料111完全填充通孔的工艺会比较难，示例性的，如图4至图6所示，可以将导电材料111形成于通孔V1的侧壁，然后再在导电材料111限定的区域内填充树脂材料112。
示例性的，导电材料111可以为金属材料，例如金、银、铝、锌、铜、铬、镍、钯等。树脂材料112可以为环氧树脂等材料，在此不作限定。
示例性的，参见图7，图7为本申请实施例提供的另一种封装结构的剖面结构示意图。在本申请中，框架板110可以包括层叠设置的至少两层介电材料板；图中以两层介电材料板1101和1102为例进行示意。每一层介电材料板1101和1102中均具有过孔，一个通孔可以包括每一介电材料板中的一个过孔。在任意相邻两层介电材料板1101和1102之间还 设置有布线层1103，且任意相邻两层介电材料板1101和1102的过孔通过布线层1103电连接。即属于同一通孔的各过孔的位置可以不相同，不同过孔通过布线层1103电连接，这样可以使得封装结构10具有再布线的可能，从而使第一导电连接垫001和第二导电连接垫002的位置可以灵活设置，从而减少封装基板20的走线压力。
示例性的，继续参见图7，布线层1103可以包括至少一层导电层1131和绝缘介质层1132，导电层1131上设置有电路布线。当布线层1103包括两层或者多层导电层1131时，绝缘介质层1132中则会设置有介质穿孔用于连通不同导电层1131上的电路布线。
可选的，参见图8，图8为本申请实施例提供的另一种封装结构的剖面结构示意图。在封装结构10中，可以在框架板110的镂空区域V2的侧壁设置金属走线123，金属走线123可以由第一表面110a一侧经镂空区域V2的侧壁延伸至第二表面110b一侧；多个导电连接垫还可以包括：位于所述第一表面110a上且与金属走线123电连接的第六导电连接垫006和位于第二表面110b上且与金属走线123电连接的第七导电连接垫007。即利用金属走线123代替通孔，从而可以减少封装结构10中的通孔V1的数量。
本申请对金属走线的数量不作限定，具体根据实际产品进行设计。当金属走线为多条是，金属走线之间可以间隔设置，以保证不同金属走线之间相互绝缘。
示例性的，金属走线可以采用金、银、铝、锌、铜、铬、镍、钯等材料形成，在此不作限定。
可选的，参见图9，图9为本申请实施例提供的另一种封装结构的剖面结构示意图。在本申请中，该封装结构10中还可以包括互连线路层210，互连线路层210位于框架板110的第二表面110b上，第二导电连接垫002和第四导电连接垫004均位于互连线路层210上，第二导电连接垫002通过互连线路层210与通孔电连接，第四导电连接垫004通过互连线路层210与第一电子元器件121电连接。从而利用互连线路层210使第二导电连接垫002和第二四导电连接垫004的位置可以重新布局。
在具体实施时，互连线路层210可以包括绝缘介质层212和至少两层导电层211，各导电层211上设置有电路布线，绝缘介质层212中则会设置有介质穿孔用于连通不同导电层211上的电路布线。
参见图10，图10为本申请实施例提供的一种封装结构的制备方法，该制备方法可以包括以下步骤：
步骤S101、在框架板的第一表面上形成第一导电连接垫。
在具体实施时，如图11a所示，框架板110可以由电介质材料形成，该框架板110具有相对且平行设置的第一表面110a和第二表面110b。
在具体实施时，框架板的厚度可以根据第一电子元器件的高度进行设计。
示例性的，如图11b所示，可以在框架板110的第一表面先电镀铜层，然后对铜层进行刻蚀形成第一导电连接垫001。
步骤S102、在框架板110中与第一导电连接垫001对应的区域形成通孔。
示例性的，如图11c所示，在框架板110中与第一导电连接垫001对应的区域处通过机械钻孔方式进行开孔。
示例性的，如图11d所示，可以先在孔的侧壁镀覆导电材料111；然后，如图11e所示，在镀覆有导电材料111的孔内填充树脂材料112从而形成通孔V1。
可选的，在本申请中，框架板110也可以是由多层介电材料板形成，在此以框架板110 由两层介电材料板形成为例，步骤S101在框架板的第一表面上形成第一导电连接垫和步骤S102在框架板中与第一导电连接垫对应的区域形成通孔，可以包括：
如图12a所示，在第一介电材料板1101的一侧表面上形成第一导电连接垫001。
如图12b所示，在第一介电材料板1101中与第一导电连接垫001对应的区域形成第一过孔。
示例性的，可以在第一介电材料板中与第一导电连接垫001对应的区域处进行机械钻孔，从而形成第一过孔，然后在第一过孔的侧壁镀覆导电材料111，之后在镀覆有导电材料111的第一过孔内填充树脂材料112。
如图12c所示，在第一介电材料板1101远离第一导电连接垫001一侧形成布线层1103，且布线层1103与第一介电材料板1101的第一过孔电连接。
示例性的，布线层1103可以包括至少一层导电层113和绝缘介质层114，导电层113上设置有电路布线。当布线层1103包括两层或者多层导电层113时，绝缘介质层114中则会设置有介质穿孔用于连通不同导电层113上的电路布线。
如图12d所示，在布线层1103远离第一介电材料板1101一侧形成第二介电材料板1102。
如图12e所示，在第二介电材料板1102中形成第二过孔，且布线层1103与第二介电材料板1102的第二过孔电连接。其中，第一介电材料板1101设置第一导电连接垫001的表面为框架案110的第一表面110a，第二介电材料板1102远离第一导电连接垫001的表面为框架案110的第二表面110b。
示例性的，可以在第二介电材料板1102中与将要形成的第二导电连接垫002对应的区域处进行机械钻孔，从而形成第二过孔，然后在第二过孔的侧壁镀覆导电材料111，之后在镀覆有导电材料111的第二过孔内填充树脂材料112。
步骤S103、如图11f所示，在框架板110中形成镂空区域V2。
示例性的，可以使用铣刀在框架板中形成镂空区域。
步骤S104、使框架板的第一表面朝下，在镂空区域内放置第一电子元器件，且第一电子元器件具有第三导电连接垫，使第三导电连接垫的表面与第一导电连接垫的表面位于同一平面。
可选的，如图11g所示，在镂空区域内放置第一电子元器件121之前，使框架板110的第一表面110a朝下，将形成有第一导电连接垫001、通孔V1、以及导电材料111的框架板110放置于可剥离胶310上。以利用可剥离胶310的黏性固定第一电子元器件121的位置。
示例性的，可剥离胶的材料可以为紫外光致可剥离胶，紫外光致可剥离胶经紫外光照射后可以失去黏性。
如图11h所示，在镂空区域V2内放置第一电子元器件121，且第一电子元器件121具有第三导电连接垫003，使第三导电连接垫003的表面与第一导电连接垫001的表面位于同一平面。
可选地，当封装结构中需要设置第二电子元器件时，参见图11h，还可以在镂空区域V2内放置第二电子元器件122，且第二电子元器件122具有第五导电连接垫005，使第五导电连接垫005的表面与第一导电连接垫001的表面位于同一平面。
在具体实施时，可以采用表面贴装技术(Surface Mounted Technology，SMT)机台将所有的电子元器件装帖在镂空区域内。
步骤S105、如图11i所示，在镂空区域的间隙处填充填充材料120。
在具体实施时，可以采用点胶机台在镂空区域内电子元器件与框架板之间的间隙处点填充材料，例如填充胶，并填平镂空区域。
步骤S106、如图11j所示，对框架板110的第二表面进行磨平处理。
在具体实施时，对框架板110的第二表面进行磨平处理，直至露出第一电子元器件121的导电连接处，以便后续在第二表面上形成与第一电子元器件121电连接的第四导电连接垫。
步骤S107、如图11k所示，在第二表面110b上形成与第一电子元器件121电连接的第四导电连接垫004和与通孔电连接的第二导电连接垫002。
示例性的，可以在第二表面先电镀铜层，然后对铜层进行刻蚀形成第二导电连接垫和第四导电连接垫。
在具体实施时，当第一表面是放置于可剥离胶上时，在形成第二导电连接垫002和第四导电连接垫004后还需要剥离可剥离胶310，从而形成如图6所示的封装结构10。
在具体实施时，当可剥离胶为紫外光致可剥离胶时，可以通过紫外光照射使紫外光致可剥离胶失去黏性，然后将可剥离从第一表面一侧剥离。
在具体实施时，在制备封装结构时，一般会在一大块框架板上制备多个封装结构，当剥离可剥离胶之后进行贴单就可以形成多个独立的多个封装结构。
在本申请中，可以在切单前将多个封装结构同时装贴在多个封装基板上，之后在进行贴单，这样可以进一步提升生产效率，当然也可以贴单后将单个封装结构装贴在单个封装基板上，在此不作限定。
在本申请中，将各电子元器件封装在框架板的镂空区域内，在镂空区域内放置电子元器件时，使电子元器件位于第一表面一侧的导电连接垫和与通孔连接的第一导电连接垫位于同一平面。而将各电子元器件封装在框架板的镂空区域后，对框架板的第二表面进行磨平处理，可以使与电子元器件连接的导电连接垫和与通孔连接的第二导电连接垫是在框架板的同一平面上形成的，从而可以使封装结构位于同一平面的导电连接垫的高度差控制在20μm内。
可选地，在本申请中，在框架板的第一表面上形成第一导电连接垫时还可以包括：在框架板的第一表面上形成第六导电连接垫；在框架板中形成镂空区域之后，在镂空区域内放置第一电子元器件之前，还包括：在镂空区域的侧壁形成金属走线，且金属走线与第六导电连接垫电连接；在第二表面上形成与第一电子元器件电连接的第四导电连接垫和与通孔电连接的第二导电连接垫时，还包括：在第二表面上形成与金属走线电连接的第七导电连接垫。即利用金属走线代替通孔，从而可以减少封装结构中的通孔的数量。示例性的，金属走线可以通过电镀方式形成，在此不作限定。
需要说明的是，本申请提供的制备方法中有一些步骤的顺序是可以调换的，不限于上述实施例中提到的顺序。
相应地，如图13所示，本申请还提供了一种封装模组3，包括封装基板20和装贴于该封装基板20上的封装结构10，该封装结构10为本申请实施例提供的上述任一种封装结构10。由于该封装模组3解决问题的原理与前述一种封装结构10相似，因此该封装模组3的实施可以参见前述封装结构10的实施，重复之处不再赘述。
在具体实施时，封装基板可以为重布线层、基板或者硅中介板(interposer)等设置有 的线路的任意结构，在此不作限定。
示例性的，封装结构可以通过SMT等技术实装贴于该封装基板上。
在一种实施例中，封装结构10可以装贴于封装基板20的背面，封装基板20的正面一般设置有电子元器件21，封装基板20正面的电子元器件21的导电连接垫(图中未示出)通过设置在封装基板20背面的导电连接垫22引出。
当然，在具体实施时，也可以将封装结构装贴于封装基板的正面，或者，在封装基板的两侧均设置上述封装结构，在此不作限定，可以根据实际需求进行设计。
进一步的，在本申请中，封装结构装贴于封装基板时，可以是封装结构中框架基板的第一表面一侧面向封装基板设置，也可以是封装结构中框架基板的第二表面一侧面向封装基板设置，在此不作限定，可以根据实际需求进行设计。
示例性的，在本申请中，参见图13，当封装结构10装贴于封装基板20的背面时，可以将封装结构10中框架板110的第一表面一侧面向封装基板20设置。这样，封装结构10既可以将第一电子元器件121封装在封装基板20的背面，同时又可以利用封装结构10中的通孔将封装基板20背面的导电连接垫引出，从而解决封装基板20背面的导电连接垫与第一电子元器件20的导电连接垫存在的高度差的问题。并且，由于该封装结构10采用的是将通孔与第一电子元器件121同一模块化的结构，因此，由封装结构10自身存在的公差基本不会影响表面位于同一平面内的导电连接垫，因此，可以使第二导电连接垫002和第四导电连接垫004的高度差，以及第一导电连接垫001和第三导电连接垫003的高度差控制在20μm内，从而降低封装模组的上板风险。并且，本申请中，可以将多个第一电子元器件121封装于封装结构10中通过一次装贴工艺就可以装贴在封装基板20的背面，相比相关技术中每个第一电子元器件121和架高板均是单独装贴，可以明显减少装贴次数，从而提高生产效率和降低产品加工成本。
相应地，本申请还提供了一种电子设备，如图3所示，包括：壳体1、位于壳体1内的电路板2和封装模组3；该封装模组3位于电路板2上，且封装模组3与电路板2电连接。示例性的，该电路板可以为PCB。由于该电子设备解决问题的原理与前述一种封装模组3相似，因此该电子设备的实施可以参见前述封装模组3的实施，重复之处不再赘述。
在具体实施时，该电子设备可以为电源电路，该电源电路用于执行电能的变换、分配、检测及其他电能管理与控制等功能。
在本申请其他变更实施例中，电子设备还可以为微处理器、中央处理器、图像处理器、基带芯片、或者片上***芯片等。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种封装结构，其特征在于，包括：框架板、第一电子元器件、填充材料和多个导电连接垫；其中，
    所述框架板由介电材料形成，所述框架板具有相对且平行设置的第一表面和第二表面，所述框架板包括通孔，且所述框架板中具有镂空区域；
    所述填充材料和所述第一电子元器件均位于所述镂空区域内，且所述第一电子元器件通过所述填充材料固定于所述镂空区域内；
    所述多个导电连接垫包括：位于所述第一表面上且与所述通孔电连接的第一导电连接垫，位于所述第二表面上且与所述通孔电连接的第二导电连接垫，位于所述第一表面上且与所述第一电子元器件电连接的第三导电连接垫，位于所述第二表面上且与所述第一电子元器件电连接的第四导电连接垫。
  2. 如权利要求1所述的封装结构，其特征在于，所述框架板包括层叠设置的至少两层介电材料板；
    所述通孔包括位于各所述介电材料板中的过孔；
    在任意相邻两层所述介电材料板之间还设置有布线层，且任意相邻两层所述介电材料板的过孔通过所述布线层电连接。
  3. 如权利要求1或2所述的封装结构，其特征在于，所述框架板还包括由所述第一表面一侧经所述镂空区域侧壁延伸至所述第二表面一侧的金属走线；
    所述多个导电连接垫还包括：位于所述第一表面上且与所述金属走线电连接的第六导电连接垫和位于所述第二表面上且与所述金属走线电连接的第七导电连接垫。
  4. 如权利要求1-3任一项所述的封装结构，其特征在于，所述封装结构中还包括第二电子元器件，所述多个导电连接垫还包括位于所述第一表面上且与所述第二电子元器件连接的第五导电连接垫；
    所述第二电子元器件通过所述填充材料固定于所述镂空区域内。
  5. 如权利要求1-4任一项所述的封装结构，其特征在于，所述通孔的侧壁形成有所述导电材料，所述导电材料限定的区域内还填充有树脂材料。
  6. 如权利要求1-4任一项所述的封装结构，其特征在于，所述通孔内填充有导电材料。
  7. 一种封装模组，其特征在于，包括封装基板和装贴于所述封装基板上的如权利要求1-6任一项所述的封装结构。
  8. 一种电子设备，其特征在于，包括：壳体、位于所述壳体内的电路板和如权利要求7所述的封装模组；所述封装模组位于所述电路板上，且所述封装模组与所述电路板电连接。
  9. 一种封装结构的制备方法，其特征在于，包括：
    在框架板的第一表面上形成第一导电连接垫；
    在所述框架板中与所述第一导电连接垫对应的区域形成通孔；
    在所述框架板中形成镂空区域；
    使所述框架板的第一表面朝下，在所述镂空区域内放置第一电子元器件，且所述第一电子元器件具有第三导电连接垫，使所述第三导电连接垫的表面与所述第一导电连接垫的表面处于同一平面；
    在所述镂空区域的间隙处填充填充材料；
    对所述框架板的第二表面进行磨平处理，其中，所述第二表面与所述第一表面相对且平行；
    在所述第二表面上形成与所述第一电子元器件电连接的第四导电连接垫和与所述通孔电连接的第二导电连接垫。
  10. 如权利要求9所述的制备方法，其特征在于，在所述镂空区域内放置第一电子元器件之前，还包括：将形成有所述第一导电连接垫和所述通孔的所述框架板放置于可剥离胶上；
    在所述第二表面上形成与所述第一电子元器件电连接的第四导电连接垫和与所述通孔电连接的第二导电连接垫之后，还包括：剥离所述可剥离胶。
  11. 如权利要求10所述的制备方法，其特征在于，所述可剥离胶的材料为紫外光致可剥离胶；
    剥离所述可剥离胶，包括：通过紫外光照射剥离所述可剥离胶。
  12. 如权利要求9-11任一项所述的制备方法，其特征在于，在所述框架板中与所述第一导电连接垫对应的区域形成通孔，包括：
    在所述框架板中与所述第一导电连接垫对应的区域进行开孔；
    在所述孔的侧壁镀覆导电材料；
    在镀覆有所述导电材料的孔内填充树脂材料。
  13. 如权利要求9-12任一项所述的制备方法，其特征在于，所述框架板包括第一介电材料板、第二介电材料板和布线层；在框架板的第一表面上形成第一导电连接垫，在所述框架板中与所述第一导电连接垫对应的区域形成通孔，包括：
    在所述第一介电材料板的一侧表面上形成第一导电连接垫；
    在所述第一介电材料板中与所述第一导电连接垫对应的区域形成第一过孔；
    在所述第一介电材料板远离所述第一导电连接垫一侧形成布线层，且所述布线层与所述第一介电材料板的第一过孔电连接；
    在所述布线层远离所述第一介电材料板一侧形成所述第二介电材料板；
    在所述第二介电材料板中形成第二过孔，且所述布线层与所述第二介电材料板的第二过孔电连接。
  14. 如权利要求9-13任一项所述的制备方法，其特征在于，在所述框架板的第一表面上形成第一导电连接垫时还包括：在所述框架板的第一表面上形成第六导电连接垫；
    在所述框架板中形成镂空区域之后，在所述镂空区域内放置第一电子元器件之前，还包括：在所述镂空区域的侧壁形成金属走线，且所述金属走线与所述第六导电连接垫电连接；
    在所述第二表面上形成与所述第一电子元器件电连接的第四导电连接垫和与所述通孔电连接的第二导电连接垫时，还包括：在所述第二表面上形成与所述金属走线电连接的第七导电连接垫。
  15. 如权利要求9-14任一项所述的制备方法，其特征在于，在所述框架板中形成镂空区域之后，在所述镂空区域的间隙处填充填充材料之前，还包括：
    在所述镂空区域内放置第二电子元器件，且所述第二电子元器件具有第五导电连接垫，使所述第二电子元器件的第五导电连接垫的表面与所述第一导电连接垫的表面位于同一平面。
PCT/CN2021/131935 2021-11-19 2021-11-19 封装结构、其制备方法、封装模组及电子设备 WO2023087284A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP21964438.2A EP4398295A1 (en) 2021-11-19 2021-11-19 Packaging structure and preparation method therefor, packaging module, and electronic device
PCT/CN2021/131935 WO2023087284A1 (zh) 2021-11-19 2021-11-19 封装结构、其制备方法、封装模组及电子设备
CN202180099259.4A CN117480601A (zh) 2021-11-19 2021-11-19 封装结构、其制备方法、封装模组及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/131935 WO2023087284A1 (zh) 2021-11-19 2021-11-19 封装结构、其制备方法、封装模组及电子设备

Publications (1)

Publication Number Publication Date
WO2023087284A1 true WO2023087284A1 (zh) 2023-05-25

Family

ID=86396031

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/131935 WO2023087284A1 (zh) 2021-11-19 2021-11-19 封装结构、其制备方法、封装模组及电子设备

Country Status (3)

Country Link
EP (1) EP4398295A1 (zh)
CN (1) CN117480601A (zh)
WO (1) WO2023087284A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116709642A (zh) * 2023-08-07 2023-09-05 荣耀终端有限公司 电路板组件、电子设备及框架板和元器件的集成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085192A1 (en) * 2007-10-01 2009-04-02 Phoenix Precision Technology Corporation Packaging substrate structure having semiconductor chip embedded therein and fabricating method thereof
US20190131242A1 (en) * 2017-10-31 2019-05-02 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN112188731A (zh) * 2019-07-02 2021-01-05 欣兴电子股份有限公司 内埋式元件结构及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085192A1 (en) * 2007-10-01 2009-04-02 Phoenix Precision Technology Corporation Packaging substrate structure having semiconductor chip embedded therein and fabricating method thereof
US20190131242A1 (en) * 2017-10-31 2019-05-02 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN112188731A (zh) * 2019-07-02 2021-01-05 欣兴电子股份有限公司 内埋式元件结构及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116709642A (zh) * 2023-08-07 2023-09-05 荣耀终端有限公司 电路板组件、电子设备及框架板和元器件的集成方法

Also Published As

Publication number Publication date
CN117480601A (zh) 2024-01-30
EP4398295A1 (en) 2024-07-10

Similar Documents

Publication Publication Date Title
US10121768B2 (en) Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same
US10354984B2 (en) Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same
EP1356520B1 (en) Microelectronic substrate with integrated devices
US8324513B2 (en) Wiring substrate and semiconductor apparatus including the wiring substrate
US7838967B2 (en) Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
EP2798675B1 (en) Method for a substrate core layer
CN102867807B (zh) 无核心层的封装基板的制造方法
US8294253B2 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure
CN101228625B (zh) 具有镀金属连接部的半导体封装
TWI402954B (zh) Assembly board and semiconductor module
TW201220446A (en) Package structure of embedded semiconductor component and manufacturing method thereof
KR20160120011A (ko) 인쇄회로기판, 그 제조방법, 및 전자부품 모듈
CN103794515A (zh) 芯片封装基板和结构及其制作方法
TWI511250B (zh) Ic載板、具有該ic載板的半導體器件及製作方法
WO2023087284A1 (zh) 封装结构、其制备方法、封装模组及电子设备
WO2015083345A1 (ja) 部品内蔵配線基板及びその製造方法
CN212967737U (zh) 一种led产品封装结构
US6207354B1 (en) Method of making an organic chip carrier package
CN105789161B (zh) 封装结构及其制法
WO2018098650A1 (zh) 集成电路封装结构及方法
TW202310092A (zh) 一種封裝機構及其製備方法
JPH07226456A (ja) Ｉｃパッケージ及びその製造方法
CN112086546A (zh) 一种led产品封装结构及封装方法
CN203086852U (zh) 内埋式印刷电路板结构
WO2023071446A1 (zh) 封装载板、其制备方法、线路基板、封装结构及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21964438

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180099259.4

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2021964438

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021964438

Country of ref document: EP

Effective date: 20240404