WO2023073831A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

Info

Publication number
WO2023073831A1
WO2023073831A1 PCT/JP2021/039646 JP2021039646W WO2023073831A1 WO 2023073831 A1 WO2023073831 A1 WO 2023073831A1 JP 2021039646 W JP2021039646 W JP 2021039646W WO 2023073831 A1 WO2023073831 A1 WO 2023073831A1
Authority
WO
WIPO (PCT)
Prior art keywords
case
semiconductor device
sealing portion
sealing
control board
Prior art date
Application number
PCT/JP2021/039646
Other languages
French (fr)
Japanese (ja)
Inventor
幸樹 岸本
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2021/039646 priority Critical patent/WO2023073831A1/en
Publication of WO2023073831A1 publication Critical patent/WO2023073831A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • the structure of a general semiconductor device used for high-power control of motors for electric railways, etc. surrounds an assembly consisting of an insulating substrate with a semiconductor element mounted on its front surface and a base plate bonded to the back surface of the insulating substrate.
  • the case is fixed to the base plate, the control board is arranged inside the case with a gap from the insulating board, and the insulating board and the control board are electrically connected to the outside by external connection terminals.
  • the semiconductor element and the electrodes are electrically connected by bonding wires.
  • a silicone gel with a very small elastic modulus is used inside the case to protect the semiconductor element and prevent partial discharge and dielectric breakdown. Filled with hard resin.
  • Patent Document 1 an adhesion-inhibiting layer is provided at the interface between a silicone gel and a hard resin to prevent the hard resin from binding the silicone gel, which thermally shrinks at low temperatures. Therefore, the structure suppresses the generation of air bubbles in the silicone gel and the occurrence of interfacial peeling between the silicone gel and the insulating substrate.
  • the upper surface of the silicone gel is less restrained from above, and when the temperature is low, as the silicone gel thermally contracts, the upper surface of the silicone gel is pulled inward and displaced downward. do.
  • the silicone gel is constrained by the wall surface of the case, the stress is concentrated at the triple point composed of the adhesion inhibiting layer, air and case. For this reason, there is a problem that shear stress acts on the silicone gel, and interfacial peeling between the silicone gel and the case tends to occur. Interfacial peeling between the silicone gel and the case causes partial discharge or dielectric breakdown in the semiconductor device.
  • the hard resin and the adhesion-inhibiting layer are not provided, and the upper part of the silicone gel is filled with air. Also in this configuration, stress concentration occurs at the triple point of the silicone gel, air, and the case, so interfacial separation between the silicone gel and the case at low temperatures is likely to occur.
  • the present disclosure has been made to solve the above-described problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can prevent interfacial peeling between the silicone gel and the case.
  • a semiconductor device includes an insulating substrate on which a semiconductor element is mounted, a base plate bonded to the back surface of the insulating substrate, a case fixed to the base plate and surrounding the insulating substrate, and a case filled inside the case. , a first sealing portion that seals the semiconductor element and the insulating substrate; The first sealing portion is filled so as to be in contact with at least the bottom surface of the protruding portion. is.
  • the method of manufacturing a semiconductor device includes an assembling step of assembling an assembly in which the semiconductor element is bonded to the upper surface of the insulating substrate and the base plate is bonded to the lower surface of the insulating substrate from the insulating substrate, the semiconductor element, and the base plate. and a case having a through-hole penetrating in a direction viewed from the top inside the inner wall of the case, and having a protruding portion filling an area from the inner wall of the case to the through-hole when viewed from the top, fixed to the base plate.
  • a first encapsulant comprising a fixing step and a first encapsulant step of encapsulating the insulating substrate and the semiconductor element with the first encapsulant, and the first encapsulant obtained by the first encapsulant curing step is The case is filled so that the upper surface thereof is located above the lower surface of the projecting portion.
  • interfacial peeling between the silicone gel and the case can be prevented.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment
  • FIG. 3 is a plan view showing the configuration of the projecting portion of the semiconductor device according to the first embodiment
  • FIG. 3 is a plan view showing the configuration of the projecting portion of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 3A to 3C are diagrams showing a manufacturing process
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment
  • FIG. FIG. 5 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment
  • FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment
  • FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment
  • FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment
  • FIG. 10 is a cross-sectional view showing a configuration of a modified example of the projecting portion of the semiconductor device according to the present disclosure
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device 1000 according to Embodiment 1.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device 1000 according to Embodiment 1.
  • a semiconductor device 1000 includes a base plate 1, an insulating substrate 2, a semiconductor element 4, bonding wires 5, bus bars 6, a control substrate 7, a case 8, a protrusion 9, a lid 10, A silicone gel seal 11 and solder 12 are provided.
  • the base plate 1 is made of a material with excellent heat conductivity, such as aluminum alloy or copper.
  • the base plate 1 has flat front and back surfaces and has a rectangular plate shape when viewed from above.
  • a fin or the like may be provided on the back surface of the base plate 1 in order to improve cooling performance of the semiconductor device 1000 .
  • the insulating substrate 2 is bonded to the surface of the base plate 1 using solder 12 .
  • the insulating substrate 2 includes an insulating layer 22 made of ceramic such as aluminum nitride or silicon nitride or resin such as epoxy resin, and an upper electrode 21 and a lower electrode 23 made of a metal such as an aluminum alloy or copper, respectively. and a structure in which it is attached to the lower surface.
  • a wiring pattern is formed on the upper electrode 21 provided on the upper surface (one surface) side of the insulating substrate 2 .
  • a plurality of upper electrodes 21 are provided so as to be separated from each other, and the semiconductor element 4 is joined to one of them using solder 12 .
  • solder 12 plate solder, solder paste, soft solder, or the like is used.
  • the semiconductor element 4 bonded to the upper electrode 21 of the insulating substrate 2 is, for example, an IGBT (Insulated Gate Bipolar Transistor) made of silicon (Si) material, a diode, or a reverse-conducting IGBT.
  • the semiconductor element 4 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Schottky diode, or the like made of a material having a larger bandgap than Si, such as silicon carbide (SiC) or gallium nitride (GaN).
  • the number of semiconductor elements 4 mounted on the insulating substrate 2 is not limited, and the required number of semiconductor elements 4 may be mounted according to the application.
  • the bonding wires 5 electrically connect the semiconductor element 4 and the upper electrode 21 on which the semiconductor element 4 is not mounted.
  • a wire rod made of an aluminum alloy or a copper alloy having a wire diameter of 0.1 to 0.5 mm is used.
  • the bonding wire 5 is used in Embodiment 1, it is not limited to this, and a bonding ribbon or the like may be used.
  • the busbar 6 is attached to the insulating substrate 2 and the control substrate 7 .
  • the busbars 6 include two first busbars 61 and two second busbars 62 .
  • the two first bus bars 61 are attached to different upper electrodes 21 of the insulating substrate 2, and the two second bus bars 62 are attached to the control substrate 7 by soldering (not shown).
  • One first bus bar 61 and one second bus bar 62 are electrically connected through the control board 7 , and the other first bus bar 61 and the other second bus bar 62 connect the control board 7 . are electrically connected via During operation of the semiconductor device 1000 , a high voltage and a ground voltage are supplied to the semiconductor element 4 through the two second bus bars 62 .
  • the busbar 6 is made of metal such as an aluminum alloy or copper.
  • the number of first busbars 61 and the number of second busbars 62 are not limited to two, and may be three or more.
  • the control board 7 is arranged inside the case 8 with a gap from the insulating board 2 .
  • the control board 7 has a control circuit for controlling the semiconductor element 4 .
  • electronic components (not shown) are mounted on the control board 7 .
  • This electronic component is a control IC (Integrated Circuit) in which a semiconductor chip forming the control circuit is sealed with resin.
  • the control board 7 is electrically connected to the semiconductor element 4 via signal lines (not shown).
  • Signal terminals (not shown) are electrically connected to a semiconductor chip in the control IC through the control board 7 .
  • the number of electronic components mounted on the control board 7 is not limited, and the necessary number of electronic components may be mounted depending on the application.
  • control board 7 having a control circuit is used separately from the insulating board 2 on which the semiconductor element 4 is mounted.
  • a control circuit may be provided on the substrate 2 .
  • the control circuit may be provided outside the semiconductor device 1000 instead of the insulating substrate 2 without providing the control substrate 7 .
  • the case 8 is a member formed by integrally molding four planar side walls surrounding a space, and stores the insulating substrate 2 on which the semiconductor element 4 is mounted in the space.
  • the case 8 serves as a framework for pouring silicone gel as a sealing material, and is made of, for example, PPS (Polyphenylene sulfide).
  • PPS Polyphenylene sulfide
  • the case 8 is adhered to the base plate 1 with a silicone-based or epoxy-based adhesive (not shown).
  • FIGS. 2 and 3 are top views of the projecting portion 9 according to the first embodiment, and are views of the projecting portion 9 extracted from FIG.
  • the outer edge of the projecting portion 9 shown in FIGS. 2 and 3 is provided in contact with the inner wall of the case 8 .
  • the protruding portion 9 has a through hole 90 penetrating in a top view direction (a direction perpendicular to the surface of the base plate 1 in FIG. 1) inside the inner wall of the case 8. , and has a shape in which the region from the inner wall of the case 8 to the through hole 90 is filled in when viewed from above. That is, the through hole 90 penetrates the upper surface of the projecting portion 9 and the bottom surface thereof, and does not contact the inner wall of the case 8 .
  • the inner side surface of the protruding portion 9 constitutes the side wall of the through hole 90 .
  • the protruding portion 9 is provided in a range from a height at which the bottom surface of the protruding portion 9 is positioned above the semiconductor element 4 and the bonding wires 5 to a height at which the upper surface of the protruding portion 9 is positioned below the control substrate 7. be done.
  • the inner surface of the protruding portion 9 is substantially orthogonal to the upper surface of the silicone gel sealing portion 11 .
  • the area ratio between the through hole 90 and the area from the inner wall of the case 8 to the through hole 90 in a top view is about 9:1 to 5:5.
  • the through hole 90 is provided so as to be positioned substantially in the center of the area formed by the inner wall of the case 8 when viewed from above.
  • the protruding part 9 is formed integrally with the case 8 or separately from the case.
  • the projecting portion 9 is compression-molded with the case 8 using a mold, and the case 8 and the projecting portion 9 form a single member.
  • the projecting portion 9 and the case 8 are formed separately, the projecting portion 9 and the case 8 that are separately molded are bonded together by a silicone-based or epoxy-based adhesive (not shown) or screws (not shown). ) to the inner wall of the case 8 .
  • the projecting portion 9 is made of, for example, PPS (Polyphenylene sulfide).
  • the cross-sectional shape of the through-hole 90a of the projecting portion 9a in FIG. 2 is rectangular, and the cross-sectional shape of the through-hole 90b of the projecting portion 9b in FIG. 3 is elliptical.
  • the top view shape of the through hole 90 is not limited to the shape shown in FIGS. 2 and 3, and may be square or circular, for example.
  • a plurality of through-holes may be distributed and provided in the protruding portion 9 .
  • the through holes may be provided inside the inner wall of the case 8 .
  • the two first busbars 61 pass through the through-holes 90, but as an example of the plurality of through-holes, a through-hole for passing through the busbars may be provided in addition to the through-holes 90. .
  • the through holes in that case are provided at locations that match the arrangement of the busbars.
  • the silicone gel sealing portion 11 is formed by filling a region surrounded by the base plate 1 and the case 8 with silicone gel.
  • Silicone gel has a penetration of 65 or more after curing, a very small elastic modulus, and a volume expansion coefficient of about 900 to 1200 ppm/K after curing. becomes.
  • the silicone gel sealing portion 11 seals the semiconductor element 4 and the insulating substrate 2 , and fills the inside of the case 8 so that the top surface of the silicone gel sealing portion 11 is higher than the bottom surface of the projecting portion 9 . That is, the silicone gel sealing portion 11 is bonded to at least the bottom surface of the projecting portion 9 .
  • the top surface of silicone gel sealing portion 11 may be formed at the same height as the bottom surface of protruding portion 9
  • the top surface of silicone gel sealing portion 11 is at the same height as the top surface of protruding portion 9 . formed in Accordingly, the silicone gel sealing portion 11 is filled in the through hole 90 and joined to the bottom surface and inner side surface of the protruding portion 9 and the side surface of the case 8 .
  • the upper surface of the silicone gel sealing portion 11 may be provided at a position higher than the upper surface of the projecting portion 9 , it is desirable to keep it below the control board 7 .
  • the lid 10 is installed on the top of the case 8 and seals the inside of the case 8 .
  • the lid 10 separates the inside and outside of the semiconductor device 1000 to prevent dust and the like from entering the inside of the semiconductor device 1000 .
  • it is made of PPS (Polyphenylene sulfide) and fixed to the case 8 with a silicone-based or epoxy-based adhesive (not shown) or screws (not shown).
  • a space is formed above the silicone gel sealing portion 11 , and the upper surface of the silicone gel sealing portion 11 is in contact with the air 13 .
  • the lid 10 is provided with through holes (not shown) having substantially the same shape as the cross section of the second busbars 62 , the number of which is the same as the number of the second busbars 62 .
  • a bus bar 62 is inserted. Therefore, a portion of second bus bar 62 is exposed from semiconductor device 1000 .
  • the busbars 6 including the first busbar 61 and the second busbar 62 function as external connection terminals for electrical connection with the outside.
  • step S1 a base plate 1, an insulating substrate 2 having an upper electrode 21 and a lower electrode 23 formed on both surfaces of an insulating layer 22, a semiconductor element 4, and two first bus bars 61 are prepared. do.
  • the base plate 1 and the insulating substrate 2 are joined with solder 12 .
  • the upper electrode 21 of the insulating substrate 2 and the semiconductor element 4 are joined with solder 12 .
  • Semiconductor element 4 and upper electrode 21 are connected by bonding wire 5 .
  • the two first bus bars 61 are soldered to the upper electrode 21 .
  • step S1 the semiconductor element 4 is bonded to the upper surface of the insulating substrate 2 and the base plate 1 is bonded to the lower surface of the insulating substrate 2 from the insulating substrate 2, the semiconductor element 4, and the base plate 1 to form a first assembly.
  • An assembly process for assembling 100 is performed.
  • step S2 after step S1, a through hole 90 penetrating in the direction viewed from the top is provided inside the inner wall of the case 8, and a region from the inner wall of the case 8 to the through hole 90 is formed in the top view.
  • a case 8 provided with a protruding portion 9 for filling is prepared.
  • the case 8 is fixed to the base plate 1 with an adhesive, screws, or the like so that the case 8 surrounds the first assembly 100 produced in step S1.
  • step S2 a case fixing step of fixing the case 8 provided with the projecting portion 9 to the base plate 1 of the first assembly 100 is performed, and as a result, the second assembly 101 is formed.
  • step S3 silicone gel as a sealing member is injected into the region surrounded by the base plate 1 and the case 8 of the second assembly 101 produced in step S2. do.
  • Silicone gel is a low-viscosity liquid substance.
  • the second assembly 101 into which the silicone gel has been injected is heated in an oven at 70° C. for 1 hour to cure the silicone gel and form the silicone gel sealing portion 11 for sealing the insulating substrate 2 and the semiconductor element 4 . be done.
  • the silicone gel sealing portion 11 is filled in the case 8 so that its upper surface is level with the upper surface of the projecting portion 9 .
  • a first sealing process is performed to seal the insulating substrate 2 and the semiconductor element 4 with silicone gel, and as a result, the third assembly 102 is formed.
  • the upper surface of the silicone gel sealing portion 11 should be at least as high as the bottom surface of the projecting portion 9 . Therefore, the injection amount of the silicone gel to be injected before curing is changed according to the height of the upper surface of the silicone gel sealing portion 11 to be formed.
  • step S4 after step S3, the control board 7 to which the two second bus bars 62 are connected is prepared.
  • the control board 7 is attached to the third assembly 102 formed in step S3. Specifically, the control board 7 is soldered to the portion of the first bus bar 61 exposed from the silicone gel sealing portion 11 .
  • the second bus bar 62 is electrically connected to the first bus bar 61 through an electrical path formed inside the control board 7 .
  • a control board mounting step is performed to mount the control board 7 at a position higher than the upper surface of the projecting portion 9, and as a result, the fourth assembly 103 is formed.
  • step S5 after step S4, the lid 10 is fixed to the upper part of the case 8 of the fourth assembly 103 formed in step S5 using an adhesive or screws, thereby sealing the case 8. At this time, a part of each of the two second bus bars 62 protrudes outward from the lid 10 . Thus, the structure of the semiconductor device 1000 shown in FIG. 1 is obtained.
  • step S5 necessary electrical characteristics are inspected, and the semiconductor device 1000 is completed.
  • FIG. 8 is a cross-sectional view of the semiconductor device 1000 according to the first embodiment near the triple point composed of the silicone gel sealing portion 11, the protruding portion 9, and the case 8, and
  • FIG. 9 is a silicone gel sealing of a conventional semiconductor device.
  • 3 is a cross-sectional view of the vicinity of the triple point composed of the portion 11, the air 13 and the case 8.
  • the thermal contraction of the silicone gel sealing portion 11 at low temperatures pulls the upper surface of the silicone gel sealing portion 11, which is not restrained, inward and downward. Although it is displaced, the side surface of the silicone gel sealing portion 11 is constrained by the wall surface of the case 8 , so the stress concentrates on the triple point formed by the silicone gel sealing portion 11 , the air 13 and the case 8 . This stress acts as a downward shearing stress from the triple point, and at a low temperature of, for example, about ⁇ 70° C., as shown in FIG. obtain.
  • the projecting portion 9 is provided, and the silicone gel sealing portion 11 is in contact with at least the bottom surface of the projecting portion 9. It is also constrained by the bottom surface of the protruding portion 9. Therefore, stress concentration at the triple point formed by the silicone gel sealing portion 11, the protruding portion 9 and the case 8 is alleviated. Therefore, the shear stress acting on the silicone gel sealing portion 11 is suppressed compared to the case where the protruding portion 9 is not provided. Therefore, it is possible to suppress partial discharge and dielectric breakdown in the semiconductor device 1000 caused by interfacial peeling.
  • silicone gel 110 as the sealing member for the semiconductor element 4 and the insulating substrate 2
  • other insulating gel-like sealing materials and resin sealing materials may be used.
  • FIG. 10 is a cross-sectional view showing a schematic configuration of a semiconductor device 1001 according to the second embodiment.
  • Embodiment 1 the configuration in which the space above silicone gel sealing portion 11 inside case 8 is filled with air 13 has been described. The difference is that an adhesion inhibiting layer 15 is provided between the silicone gel sealing portion 11 and the epoxy resin sealing portion 14 to prevent adhesion between the silicone gel sealing portion 11 and the epoxy resin sealing portion 14 .
  • Other configurations are the same as those of the first embodiment.
  • the epoxy resin sealing portion 14 is filled on the upper side of the silicone gel sealing portion 11, and the adhesion between the silicone gel sealing portion 11 and the epoxy resin sealing portion 14 is inhibited.
  • An adhesion inhibiting layer 15 is provided.
  • the adhesion inhibiting layer 15 is provided inside the case 8 so as to be in contact with the upper surface of the silicone gel sealing portion 11 and the upper surface of the projecting portion 9 .
  • the structure of the adhesion inhibiting layer 15 includes (1) a material layer that is difficult to adhere to the epoxy resin sealing portion 14 but adheres to the silicone gel sealing portion 11, and (2) the epoxy resin sealing portion 14 and silicone gel sealing. (3) A material layer that adheres to both the portion 11 but is very fragile, and (3) a substance layer that does not easily adhere to both the epoxy resin sealing portion 14 and the silicone gel sealing portion 11 may be placed at the interface.
  • Specific materials for the adhesion-inhibiting layer 15 include components different from silicone gel, and (1) is a single or multiple substance selected from powders, fluorine-containing substances, and silicon-containing substances; 2) is a single or multiple powder substance selected from powdered silica, powdered alumina, and talc, and (3) is a liquid substance such as silicone oil.
  • the epoxy resin sealing portion 14 is provided inside the case 8 so as to be in contact with the adhesion inhibiting layer 15 .
  • the epoxy resin sealing portion 14 is made of epoxy resin or a material containing epoxy resin as a main component, and has a volume expansion coefficient of about 60 to 150 ppm/K.
  • the epoxy resin sealing portion 14 is filled so that the upper surface of the epoxy resin sealing portion 14 is higher than the upper surface of the control board 7 . Even if the epoxy resin sealing portion 14 is filled, a gap is provided between the upper surface of the epoxy resin sealing portion 14 and the lid 10 as shown in FIG. contact is desirable.
  • FIG. Steps S1 to S3 in the first embodiment are also applied to the second embodiment.
  • step S6 after step S3, the adhesion inhibiting layer 15 is formed inside the case 8 of the third assembly 102.
  • a sheet-like adhesion inhibiting substance is placed, an adhesion inhibiting substance is sprayed with a spray or the like, or a paste adhesion is performed.
  • the adhesion-inhibiting layer 15 is formed by applying an adhesion-inhibiting substance, baking the adhesion-inhibiting substance at a low temperature, or the like. At this time, part of the two first bus bars 61 protrude from the upper surface of the adhesion inhibition layer 15 .
  • the adhesion inhibiting layer arranging step of arranging the adhesion inhibiting layer 15 on the upper surface of the silicone gel sealing portion 11 is performed, and as a result, the fifth assembly 104 is formed.
  • step S7 after step S6, the control board 7 to which the two second bus bars 62 are connected is prepared.
  • the control board 7 is attached to the fifth assembly 104 formed in step S6.
  • the control board 7 is soldered to the portion of the first bus bar 61 exposed from the adhesion inhibition layer 15 .
  • the second bus bar 62 is electrically connected to the first bus bar 61 through an electrical path formed inside the control board 7 .
  • a control board mounting step is performed to mount the control board 7 at a position higher than the upper surface of the projecting portion 9, and as a result, the sixth assembly 105 is formed.
  • step S8 after step S7, the epoxy resin sealing portion 14 is formed inside the case 8 of the sixth assembly 105.
  • a sealing material which is an epoxy resin or a material containing epoxy resin as a main component, is injected onto the upper surface of the adhesion inhibiting layer 15 .
  • the sixth assembly 105 into which the sealing material has been injected is heated in an oven at 150° C. for 1 to 2 hours and then at 200° C. for 2 hours to harden the sealing material, and the epoxy resin sealing portion 14 is formed.
  • the upper surface of the epoxy resin sealing portion 14 is positioned above the upper surface of the control board 7 .
  • a second sealing process is performed to seal the upper surface of the adhesion inhibiting layer 15 with epoxy resin, and as a result, the seventh assembly 106 is formed.
  • step S8 the same process as step S5 of the first embodiment is performed to obtain the structure of the semiconductor device 1001 shown in FIG.
  • the adhesion inhibition layer 15 is made of a material that is difficult to adhere to the epoxy resin sealing portion 14 but adheres to the silicone gel sealing portion 11, As the silicone gel sealing portion 11 thermally shrinks at a low temperature, the compressive stress acting on the silicone gel sealing portion 11 causes the air bubbles contained in the silicone gel sealing portion 11 and the adhesion inhibiting layer 15 to move, resulting in adhesion. A gap is formed between the inhibition layer 15 and the epoxy resin sealing portion 14 .
  • any of (1) to (3) when the temperature is low, the upper surface of the silicone gel sealing portion 11 is displaced downward by a pulling force from the inside.
  • the silicone gel sealing portion 11 is in contact with the bottom surface of the projecting portion 9 , and is constrained by the bottom surface of the projecting portion 9 . Even if the upper surface of the silicone gel sealing portion 11 is displaced, the concentration of stress on the triple point formed by the silicone gel sealing portion 11, the protrusion 9, and the case 8 can be avoided by restraint from the bottom surface of the protrusion 9. be done. Therefore, interfacial separation between the silicone gel sealing portion 11 and the case 8 can be prevented.
  • the thermally expanding silicone gel 110 is pressed by the epoxy resin sealing portion 14, so a compressive stress acts on the silicone gel 110, and the silicone gel 110 is compressed. In 110, the generation of air bubbles can be prevented. Interfacial separation between the silicone gel 110 and the insulating substrate 2 can be prevented. Therefore, it is possible to suppress partial discharge and dielectric breakdown in the semiconductor device 1001 at high temperature or low pressure.
  • the example of using the epoxy resin sealing portion 14 as the sealing member filled on the upper side of the first sealing material that seals the semiconductor element 4 and the insulating substrate 2 has been described.
  • a resin harder than the sealing material may be used as the sealing member.
  • the second sealing material may be a resin having a smaller volume expansion coefficient than the first sealing material.
  • FIG. 14 is a cross-sectional view showing a configuration of a protruding portion 9a as a modified example of the protruding portion 9 of the semiconductor device 1000 and the semiconductor device 1001 according to the present disclosure.
  • the inner side surface of the protruding portion 9 forms a plane substantially perpendicular to the upper surface of the silicone gel sealing portion 11 .
  • the corners between the inner surface and the upper surface and the corners between the inner surface and the bottom surface are rounded. Since the stress generated in the silicone gel sealing portion 11 is relieved at this rounded portion, the silicone gel sealing portion 11 is less likely to separate from the projecting portion 9 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device (1000) comprises: an insulating substrate (2) having a semiconductor element (4) mounted thereon; a base plate (1) joined to a back surface of the insulating substrate (2); a case (8) fixed to the base plate (1) and surrounding the insulating substrate (4); a first sealing portion (11) filling the inside of the case (8) and sealing the semiconductor element (4) and the insulating substrate (2); and a protrusion (9) protruding from an inner wall of the case (8). The protrusion (9) has a through-hole (90) penetrating in a top-view direction inside the inner wall of the case (8), and fills a region from the inner wall of the case (8) to the through-hole (90) in a top view. The first sealing portion (11) is filled so as to be in contact with at least the bottom surface of the protrusion (9). In this way, stress concentration to the first sealing portion (11) is reduced, making it possible to prevent interfacial delamination between the first sealing portion (11) and the case (8).

Description

半導体装置及び半導体装置の製造方法Semiconductor device and method for manufacturing semiconductor device
　本開示は、半導体装置及び半導体装置の製造方法に関わる。 The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
　電鉄用モータ等の大電力制御に用いられる一般的な半導体装置の構成は、表面に半導体素子が搭載された絶縁基板、及び絶縁基板の裏面に接合されたベース板から構成される組立体を取り囲むようにケースがベース板に固定されており、ケース内部に絶縁基板と間隔を空けて制御基板が配置され、絶縁基板及び制御基板は外部接続端子により外部に電気的に接続される。さらに、半導体素子及び電極はボンディングワイヤにより電気的に接続される。また、ケース内部に半導体素子保護、並びに部分放電及び絶縁破壊防止のための弾性率が非常に小さいシリコーンゲル、及びシリコーンゲルの上側に端子固定及びパッケージの機密保持のためにエポキシ樹脂組成物等の硬質樹脂が充填されている。 The structure of a general semiconductor device used for high-power control of motors for electric railways, etc. surrounds an assembly consisting of an insulating substrate with a semiconductor element mounted on its front surface and a base plate bonded to the back surface of the insulating substrate. The case is fixed to the base plate, the control board is arranged inside the case with a gap from the insulating board, and the insulating board and the control board are electrically connected to the outside by external connection terminals. Furthermore, the semiconductor element and the electrodes are electrically connected by bonding wires. In addition, a silicone gel with a very small elastic modulus is used inside the case to protect the semiconductor element and prevent partial discharge and dielectric breakdown. Filled with hard resin.
　この従来の半導体装置では、低温時、熱収縮するシリコーンゲルが硬質樹脂に拘束されることにより、シリコーンゲルに引張応力が働く。そのためシリコーンゲルと絶縁基板との間で界面剥離の発生を招きやすい。 In this conventional semiconductor device, tensile stress acts on the silicone gel as the silicone gel, which thermally shrinks at low temperatures, is constrained by the hard resin. Therefore, interfacial peeling is likely to occur between the silicone gel and the insulating substrate.
　そこで、シリコーンゲルの構造欠損の発生を抑制する技術が検討されている。例えば、特許文献１では、シリコーンゲルと硬質樹脂との界面に接着阻害層を設置することによって、低温時、熱収縮するシリコーンゲルが硬質樹脂から拘束されるのを防止する。よってシリコーンゲル中に気泡の発生、及びシリコーンゲルと絶縁基板との間での界面剥離の発生を抑制する構造としている。 Therefore, techniques for suppressing the occurrence of structural defects in silicone gel are being studied. For example, in Patent Document 1, an adhesion-inhibiting layer is provided at the interface between a silicone gel and a hard resin to prevent the hard resin from binding the silicone gel, which thermally shrinks at low temperatures. Therefore, the structure suppresses the generation of air bubbles in the silicone gel and the occurrence of interfacial peeling between the silicone gel and the insulating substrate.
特開平８－３１６３５７Japanese Patent Laid-Open No. 8-316357
　特許文献１の半導体装置によれば、シリコーンゲルの上面はその上方からの拘束が弱くなり、低温時、シリコーンゲルが熱収縮することに伴い、シリコーンゲルの上面が内側に引っ張られ、下方に変位する。他方でシリコーンゲルはケースの壁面に拘束されるので、接着阻害層、空気及びケースから構成される三重点に応力が集中する。このため、シリコーンゲルにせん断応力が働き、シリコーンゲルとケースとの間での界面剥離が発生しやすくなるという課題があった。シリコーンゲルとケースとの間の界面剥離は、半導体装置内における部分放電又は絶縁破壊の原因となる。 According to the semiconductor device of Patent Document 1, the upper surface of the silicone gel is less restrained from above, and when the temperature is low, as the silicone gel thermally contracts, the upper surface of the silicone gel is pulled inward and displaced downward. do. On the other hand, since the silicone gel is constrained by the wall surface of the case, the stress is concentrated at the triple point composed of the adhesion inhibiting layer, air and case. For this reason, there is a problem that shear stress acts on the silicone gel, and interfacial peeling between the silicone gel and the case tends to occur. Interfacial peeling between the silicone gel and the case causes partial discharge or dielectric breakdown in the semiconductor device.
　また硬質樹脂および接着阻害層を設けず、シリコーンゲルの上方を空気で満たすように構成する場合もある。この構成においても同様に、シリコーンゲル、空気及びケースの三重点への応力集中が生じるので、低温時のシリコーンゲルとケースとの間の界面剥離が発生しやすい。 In some cases, the hard resin and the adhesion-inhibiting layer are not provided, and the upper part of the silicone gel is filled with air. Also in this configuration, stress concentration occurs at the triple point of the silicone gel, air, and the case, so interfacial separation between the silicone gel and the case at low temperatures is likely to occur.
　本開示は、上述した課題を解決するためになされたものであり、シリコーンゲルとケースとの間での界面剥離を阻止できる半導体装置及び半導体装置の製造方法を提供することを目的とする。 The present disclosure has been made to solve the above-described problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can prevent interfacial peeling between the silicone gel and the case.
　本開示に係る半導体装置は、表面に半導体素子が搭載された絶縁基板と、絶縁基板の裏面に接合されたベース板と、ベース板に固定され絶縁基板を取り囲むケースと、ケースの内部に充填され、半導体素子及び絶縁基板を封止する第一の封止部と、ケースの内壁から突出するように設けられた突出部と、を備え、その突出部は上面視する方向に貫通する貫通孔をケースの内壁より内側に有し、上面視でケースの内壁から貫通孔までの領域を埋め、第一の封止部が突出部の少なくとも底面に接するように充填されたことを、特徴とするものである。 A semiconductor device according to the present disclosure includes an insulating substrate on which a semiconductor element is mounted, a base plate bonded to the back surface of the insulating substrate, a case fixed to the base plate and surrounding the insulating substrate, and a case filled inside the case. , a first sealing portion that seals the semiconductor element and the insulating substrate; The first sealing portion is filled so as to be in contact with at least the bottom surface of the protruding portion. is.
　また、本開示に係る半導体装置の製造方法は、絶縁基板、半導体素子及びベース板から、絶縁基板の上面に半導体素子が、絶縁基板の下面にベース板がそれぞれ接合された組立体を組み立てる組み立て工程と、上面視する方向に貫通する貫通孔をケースの内壁より内側に有し、上面視でケースの内壁から貫通孔までの領域を埋める突出部が設けられたケースを、ベース板に固定するケース固定工程と、絶縁基板及び半導体素子を第一の封止材で封止する第一の封止工程と、を備え、第一の封止材硬化工程により得られる第一の封止材は、その上面が突出部の下面以上に位置するようにケース内に充填されているものである。 Further, the method of manufacturing a semiconductor device according to the present disclosure includes an assembling step of assembling an assembly in which the semiconductor element is bonded to the upper surface of the insulating substrate and the base plate is bonded to the lower surface of the insulating substrate from the insulating substrate, the semiconductor element, and the base plate. and a case having a through-hole penetrating in a direction viewed from the top inside the inner wall of the case, and having a protruding portion filling an area from the inner wall of the case to the through-hole when viewed from the top, fixed to the base plate. A first encapsulant comprising a fixing step and a first encapsulant step of encapsulating the insulating substrate and the semiconductor element with the first encapsulant, and the first encapsulant obtained by the first encapsulant curing step is The case is filled so that the upper surface thereof is located above the lower surface of the projecting portion.
　本開示によれば、シリコーンゲルとケースとの間での界面剥離を阻止することができる。 According to the present disclosure, interfacial peeling between the silicone gel and the case can be prevented.
実施の形態１に係る半導体装置の概略構成を示す断面図である。1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment; FIG. 実施の形態１に係る半導体装置の突出部の構成を示す平面図である。3 is a plan view showing the configuration of the projecting portion of the semiconductor device according to the first embodiment; FIG. 実施の形態１に係る半導体装置の突出部の構成を示す平面図である。3 is a plan view showing the configuration of the projecting portion of the semiconductor device according to the first embodiment; FIG. 実施の形態１に係る半導体装置の製造工程を示す図である。3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment; FIG. 実施の形態１に係る半導体装置の製造工程を示す図である。3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment; FIG. 実施の形態１に係る半導体装置の製造工程を示す図である。3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment; FIG. 実施の形態１に係る半導体装置の製造工程を示す図である。3A to 3C are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment; FIG. 実施の形態１に係る半導体装置の概略構成を示す断面図である。1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment; FIG. 実施の形態１に係る半導体装置の概略構成を示す断面図である。1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment; FIG. 実施の形態２に係る半導体装置の概略構成を示す断面図である。FIG. 5 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment; 実施の形態２に係る半導体装置の製造工程を示す図である。FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment; 実施の形態２に係る半導体装置の製造工程を示す図である。FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment; 実施の形態２に係る半導体装置の製造工程を示す図である。FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment; 本開示に係る半導体装置の突出部の変形例の構成を示す断面図である。FIG. 10 is a cross-sectional view showing a configuration of a modified example of the projecting portion of the semiconductor device according to the present disclosure;
実施の形態１．
　図１～図３を用いて実施の形態１における半導体装置１０００について説明する。
　図１は、実施の形態１における半導体装置１０００の概略構成を示す断面図である。 Embodiment 1.
A semiconductor device 1000 according to the first embodiment will be described with reference to FIGS. 1 to 3. FIG.
FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device 1000 according to Embodiment 1. FIG.
　図１に示すように、実施の形態１における半導体装置１０００は、ベース板１、絶縁基板２、半導体素子４、ボンディングワイヤ５、バスバー６、制御基板７、ケース８、突出部９、蓋１０、シリコーンゲル封止部１１及びはんだ１２を備える。 As shown in FIG. 1, a semiconductor device 1000 according to the first embodiment includes a base plate 1, an insulating substrate 2, a semiconductor element 4, bonding wires 5, bus bars 6, a control substrate 7, a case 8, a protrusion 9, a lid 10, A silicone gel seal 11 and solder 12 are provided.
　ベース板１は、例えば、アルミニウム合金、銅等の熱伝導に優れる材料で作られる。ベース板１は、表面及び裏面が平坦であり且つ上面視で矩形の板状であり、半導体素子４が搭載された絶縁基板２を支持し、ケース８を固定する。ベース板１の裏面には、半導体装置１０００の冷却性を向上させるため、例えばフィン等が設けられてもよい。 The base plate 1 is made of a material with excellent heat conductivity, such as aluminum alloy or copper. The base plate 1 has flat front and back surfaces and has a rectangular plate shape when viewed from above. For example, a fin or the like may be provided on the back surface of the base plate 1 in order to improve cooling performance of the semiconductor device 1000 .
　絶縁基板２は、ベース板１の表面にはんだ１２を用いて接合されている。絶縁基板２は、窒化アルミニウム、窒化ケイ素等のセラミック、またはエポキシ樹脂等の樹脂で構成された絶縁層２２に、アルミニウム合金、銅等の金属で構成された上部電極２１及び下部電極２３をそれぞれ上面及び下面に貼り合わせた構造となっている。絶縁基板２の上面（一方の面）側に設けられた上部電極２１には配線パターンが形成されている。上部電極２１は互いに分離されるように複数設けられ、そのうちの一つに半導体素子４がはんだ１２を用いて接合されている。はんだ１２として、具体的には、板はんだ、はんだペースト、軟ろう等が用いられている。 The insulating substrate 2 is bonded to the surface of the base plate 1 using solder 12 . The insulating substrate 2 includes an insulating layer 22 made of ceramic such as aluminum nitride or silicon nitride or resin such as epoxy resin, and an upper electrode 21 and a lower electrode 23 made of a metal such as an aluminum alloy or copper, respectively. and a structure in which it is attached to the lower surface. A wiring pattern is formed on the upper electrode 21 provided on the upper surface (one surface) side of the insulating substrate 2 . A plurality of upper electrodes 21 are provided so as to be separated from each other, and the semiconductor element 4 is joined to one of them using solder 12 . Specifically, as the solder 12, plate solder, solder paste, soft solder, or the like is used.
　絶縁基板２の上部電極２１に接合される半導体素子４は、例えば、シリコン（Ｓｉ）素材のＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ダイオード又は逆導通ＩＧＢＴである。または半導体素子４は、シリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）等、Ｓｉに比べてバンドギャップの大きい素材で作製されたＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、ショットキーダイオード等としてもよい。絶縁基板２に搭載される半導体素子４の個数は限定されず、用途に応じて必要な個数の半導体素子４が搭載されてよい。 The semiconductor element 4 bonded to the upper electrode 21 of the insulating substrate 2 is, for example, an IGBT (Insulated Gate Bipolar Transistor) made of silicon (Si) material, a diode, or a reverse-conducting IGBT. Alternatively, the semiconductor element 4 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Schottky diode, or the like made of a material having a larger bandgap than Si, such as silicon carbide (SiC) or gallium nitride (GaN). The number of semiconductor elements 4 mounted on the insulating substrate 2 is not limited, and the required number of semiconductor elements 4 may be mounted according to the application.
　ボンディングワイヤ５は、半導体素子４及びその半導体素子４の搭載されない上部電極２１を電気的に接続している。ボンディングワイヤ５は、線径０．１～０．５ｍｍのアルミニウム合金製若しくは銅合金製の線材が用いられる。実施の形態１ではボンディングワイヤ５を用いているが、これに限定されるものではなく、ボンディングリボン等を用いてもよい。 The bonding wires 5 electrically connect the semiconductor element 4 and the upper electrode 21 on which the semiconductor element 4 is not mounted. As the bonding wire 5, a wire rod made of an aluminum alloy or a copper alloy having a wire diameter of 0.1 to 0.5 mm is used. Although the bonding wire 5 is used in Embodiment 1, it is not limited to this, and a bonding ribbon or the like may be used.
　バスバー６は、絶縁基板２及び制御基板７に取り付けられる。具体的にはバスバー６は２つの第一のバスバー６１及び２つの第二のバスバー６２を含む。２つの第一のバスバー６１は絶縁基板２のそれぞれ異なる上部電極２１に、２つの第二のバスバー６２は制御基板７に、それぞれ図示されないはんだを用いて接合され、取り付けられる。一方の第一のバスバー６１と一方の第二のバスバー６２とが制御基板７を介して電気的に接続され、他方の第一のバスバー６１と他方の第二のバスバー６２とが制御基板７を介して電気的に接続される。半導体装置１０００の動作時、２つの第二のバスバー６２を通じてそれぞれ高電圧及び接地電圧が半導体素子４に供給される。バスバー６は、アルミニウム合金、銅等の金属で構成される。第一のバスバー６１の数および第二のバスバー６２の数はそれぞれ２つに限らず、３つ以上でもよい。 The busbar 6 is attached to the insulating substrate 2 and the control substrate 7 . Specifically, the busbars 6 include two first busbars 61 and two second busbars 62 . The two first bus bars 61 are attached to different upper electrodes 21 of the insulating substrate 2, and the two second bus bars 62 are attached to the control substrate 7 by soldering (not shown). One first bus bar 61 and one second bus bar 62 are electrically connected through the control board 7 , and the other first bus bar 61 and the other second bus bar 62 connect the control board 7 . are electrically connected via During operation of the semiconductor device 1000 , a high voltage and a ground voltage are supplied to the semiconductor element 4 through the two second bus bars 62 . The busbar 6 is made of metal such as an aluminum alloy or copper. The number of first busbars 61 and the number of second busbars 62 are not limited to two, and may be three or more.
　制御基板７は、絶縁基板２と間隔を空けてケース８の内部に配置される。制御基板７は、半導体素子４の制御を行う制御回路を有する。具体的には制御基板７上には図示されない電子部品が搭載される。この電子部品は、当該制御回路を形成する半導体チップが樹脂封止された制御ＩＣ（Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）である。電子部品が半導体素子４を制御するために、制御基板７は図示されない信号線を介して半導体素子４と電気的に接続される。また図示されない信号端子は制御基板７を介して、制御ＩＣ内にある半導体チップに電気的に接続されている。制御基板７に搭載される電子部品の搭載個数は限定されず、用途に応じて必要な個数の電子部品が搭載されてよい。 The control board 7 is arranged inside the case 8 with a gap from the insulating board 2 . The control board 7 has a control circuit for controlling the semiconductor element 4 . Specifically, electronic components (not shown) are mounted on the control board 7 . This electronic component is a control IC (Integrated Circuit) in which a semiconductor chip forming the control circuit is sealed with resin. In order for the electronic components to control the semiconductor element 4, the control board 7 is electrically connected to the semiconductor element 4 via signal lines (not shown). Signal terminals (not shown) are electrically connected to a semiconductor chip in the control IC through the control board 7 . The number of electronic components mounted on the control board 7 is not limited, and the necessary number of electronic components may be mounted depending on the application.
　実施の形態１では、半導体素子４が搭載された絶縁基板２とは別に制御回路を有する制御基板７が用いられているが、これに限定されるものではなく、制御基板７を設けずに絶縁基板２上に制御回路を有してもよい。または制御基板７を設けずに制御回路を、絶縁基板２ではなく半導体装置１０００の外側に設けるようにしてもよい。 In Embodiment 1, the control board 7 having a control circuit is used separately from the insulating board 2 on which the semiconductor element 4 is mounted. A control circuit may be provided on the substrate 2 . Alternatively, the control circuit may be provided outside the semiconductor device 1000 instead of the insulating substrate 2 without providing the control substrate 7 .
　ケース８は、空間を取り囲む４つの平面状の側壁が一体成形されてなる部材であり、その空間に半導体素子４が搭載された絶縁基板２を格納する。ケース８は、封止材としてシリコーンゲルが流し込まれる際の枠組みとなる役割を果たし、例えば、ＰＰＳ（Ｐｏｌｙｐｈｅｎｙｌｅｎｅｓｕｌｆｉｄｅ）で形成される。ケース８は、シリコーン系又はエポキシ系等の接着剤（図示せず）によりベース板１に接着される。 The case 8 is a member formed by integrally molding four planar side walls surrounding a space, and stores the insulating substrate 2 on which the semiconductor element 4 is mounted in the space. The case 8 serves as a framework for pouring silicone gel as a sealing material, and is made of, for example, PPS (Polyphenylene sulfide). The case 8 is adhered to the base plate 1 with a silicone-based or epoxy-based adhesive (not shown).
　突出部９はケース８の内壁から突出するようにケース８の内壁に設けられる。ここで、図２及び図３は、実施の形態１における突出部９を上面視した上面図であり、図１から突出部９を抜き出した図である。
　図２及び図３に示された突出部９の外縁がケース８の内壁に接して設けられる。図２、図３に示すように、突出部９は、上面視する方向（図１で言えば、ベース板１の表面に垂直な方向）に貫通する貫通孔９０を、ケース８の内壁より内側に有し、上面視でケース８の内壁から貫通孔９０までの領域を埋めた形状である。つまり貫通孔９０は突出部９の上面及びその裏面である底面を貫通し、ケース８の内壁には接しない。突出部９の内側面が貫通孔９０の側壁を構成する。 The protrusion 9 is provided on the inner wall of the case 8 so as to protrude from the inner wall of the case 8 . Here, FIGS. 2 and 3 are top views of the projecting portion 9 according to the first embodiment, and are views of the projecting portion 9 extracted from FIG.
The outer edge of the projecting portion 9 shown in FIGS. 2 and 3 is provided in contact with the inner wall of the case 8 . As shown in FIGS. 2 and 3, the protruding portion 9 has a through hole 90 penetrating in a top view direction (a direction perpendicular to the surface of the base plate 1 in FIG. 1) inside the inner wall of the case 8. , and has a shape in which the region from the inner wall of the case 8 to the through hole 90 is filled in when viewed from above. That is, the through hole 90 penetrates the upper surface of the projecting portion 9 and the bottom surface thereof, and does not contact the inner wall of the case 8 . The inner side surface of the protruding portion 9 constitutes the side wall of the through hole 90 .
　突出部９は、突出部９の底面が半導体素子４及びボンディングワイヤ５よりも上側に位置する高さから、突出部９の上面が制御基板７よりも下側に位置する高さまでの範囲に設けられる。突出部９の内側面は、シリコーンゲル封止部１１の上面にほぼ直交する。貫通孔９０とケース８の内壁から貫通孔９０までの領域との上面視の面積比（貫通孔９０：ケース８の内壁から貫通孔９０までの領域）はおおよそ９：１～５：５であることが望ましく、上面視で貫通孔９０は、ケース８の内壁で形成される領域のほぼ中央に位置するように設けられる。 The protruding portion 9 is provided in a range from a height at which the bottom surface of the protruding portion 9 is positioned above the semiconductor element 4 and the bonding wires 5 to a height at which the upper surface of the protruding portion 9 is positioned below the control substrate 7. be done. The inner surface of the protruding portion 9 is substantially orthogonal to the upper surface of the silicone gel sealing portion 11 . The area ratio between the through hole 90 and the area from the inner wall of the case 8 to the through hole 90 in a top view (through hole 90: area from the inner wall of the case 8 to the through hole 90) is about 9:1 to 5:5. Desirably, the through hole 90 is provided so as to be positioned substantially in the center of the area formed by the inner wall of the case 8 when viewed from above.
　突出部９は、ケース８に一体成形で又はケースと別々に形成される。突出部９は、一体成形の場合、金型を用いてケース８と圧縮成形され、ケース８と突出部９とが単一の部材となる。突出部９とケース８とが別々に形成される場合、個別に成形された突出部９とケース８とが、シリコーン系若しくはエポキシ系等の接着剤（図示せず）、又はネジ（図示せず）でケース８内壁に固定される。突出部９は、例えばＰＰＳ（Ｐｏｌｙｐｈｅｎｙｌｅｎｅｓｕｌｆｉｄｅ）で形成される。 The protruding part 9 is formed integrally with the case 8 or separately from the case. In the case of integral molding, the projecting portion 9 is compression-molded with the case 8 using a mold, and the case 8 and the projecting portion 9 form a single member. When the projecting portion 9 and the case 8 are formed separately, the projecting portion 9 and the case 8 that are separately molded are bonded together by a silicone-based or epoxy-based adhesive (not shown) or screws (not shown). ) to the inner wall of the case 8 . The projecting portion 9 is made of, for example, PPS (Polyphenylene sulfide).
　貫通孔９０の上面視の形状として、図２の突出部９ａの貫通孔９０ａの断面形状は長方形、図３の突出部９ｂの貫通孔９０ｂの断面形状は楕円形に形成されている。貫通孔９０の上面視形状は、図２，３に示した形状に限らず、例えば、正方形又は円形でもよい。 As for the top view shape of the through-hole 90, the cross-sectional shape of the through-hole 90a of the projecting portion 9a in FIG. 2 is rectangular, and the cross-sectional shape of the through-hole 90b of the projecting portion 9b in FIG. 3 is elliptical. The top view shape of the through hole 90 is not limited to the shape shown in FIGS. 2 and 3, and may be square or circular, for example.
　なお複数の貫通孔が分散して突出部９に設けられてもよい。いずれも貫通孔もケース８の内壁より内側に設けられていればよい。実施の形態１では、貫通孔９０に２つの第一のバスバー６１が通されるが、複数の貫通孔の例として、貫通孔９０とは別に、バスバー貫通用の貫通孔が設けられてもよい。その場合の貫通孔はバスバーの配置に一致する箇所に設けられる。 It should be noted that a plurality of through-holes may be distributed and provided in the protruding portion 9 . In both cases, the through holes may be provided inside the inner wall of the case 8 . In the first embodiment, the two first busbars 61 pass through the through-holes 90, but as an example of the plurality of through-holes, a through-hole for passing through the busbars may be provided in addition to the through-holes 90. . The through holes in that case are provided at locations that match the arrangement of the busbars.
　シリコーンゲル封止部１１は、シリコーンゲルをベース板１とケース８とで囲まれる領域内に充填することにより形成される。シリコーンゲルは、硬化後の針入度が６５以上で弾性率が非常に小さく、硬化後の体積膨張係数が９００～１２００ｐｐｍ／Ｋ程度であり、硬化前は低粘度の液体、硬化後はゲル状となる。また、シリコーンゲルには、加熱硬化型と室温硬化型があるが、以下では加熱硬化型を用いて説明する。 The silicone gel sealing portion 11 is formed by filling a region surrounded by the base plate 1 and the case 8 with silicone gel. Silicone gel has a penetration of 65 or more after curing, a very small elastic modulus, and a volume expansion coefficient of about 900 to 1200 ppm/K after curing. becomes. There are two types of silicone gel: heat-curable and room-temperature-curable, but the heat-curable type will be described below.
　シリコーンゲル封止部１１は、半導体素子４及び絶縁基板２を封止し、シリコーンゲル封止部１１の上面が突出部９の底面以上の高さとなるようにケース８内部に充填されている。つまりシリコーンゲル封止部１１が突出部９の少なくとも底面に接合されている。
　シリコーンゲル封止部１１の上面が突出部９の底面と同じ高さに形成されてもよいが、実施の形態１においてはシリコーンゲル封止部１１の上面が突出部９の上面と同じ高さに形成される。よってシリコーンゲル封止部１１は貫通孔９０に充填され、突出部９の底面及び内側面並びにケース８の側面に接合される。シリコーンゲル封止部１１の上面が突出部９の上面よりさらに高い位置に設けられてもよいが、制御基板７よりも下側の位置に抑えるのが望ましい。 The silicone gel sealing portion 11 seals the semiconductor element 4 and the insulating substrate 2 , and fills the inside of the case 8 so that the top surface of the silicone gel sealing portion 11 is higher than the bottom surface of the projecting portion 9 . That is, the silicone gel sealing portion 11 is bonded to at least the bottom surface of the projecting portion 9 .
Although the top surface of silicone gel sealing portion 11 may be formed at the same height as the bottom surface of protruding portion 9 , in the first embodiment, the top surface of silicone gel sealing portion 11 is at the same height as the top surface of protruding portion 9 . formed in Accordingly, the silicone gel sealing portion 11 is filled in the through hole 90 and joined to the bottom surface and inner side surface of the protruding portion 9 and the side surface of the case 8 . Although the upper surface of the silicone gel sealing portion 11 may be provided at a position higher than the upper surface of the projecting portion 9 , it is desirable to keep it below the control board 7 .
　蓋１０は、ケース８の上部に設置され、ケース８内部を密封する。蓋１０により、半導体装置１０００の内部と外部を分離し、粉塵等が半導体装置１０００内部に侵入することを防いでいる。例えば、ＰＰＳ（Ｐｏｌｙｐｈｅｎｙｌｅｎｅｓｕｌｆｉｄｅ）で形成され、シリコーン系若しくはエポキシ系等の接着剤（図示せず）又はネジ（図示せず）でケース８に固定される。シリコーンゲル封止部１１の上は空隙となっており、シリコーンゲル封止部１１の上面は空気１３と接する。 The lid 10 is installed on the top of the case 8 and seals the inside of the case 8 . The lid 10 separates the inside and outside of the semiconductor device 1000 to prevent dust and the like from entering the inside of the semiconductor device 1000 . For example, it is made of PPS (Polyphenylene sulfide) and fixed to the case 8 with a silicone-based or epoxy-based adhesive (not shown) or screws (not shown). A space is formed above the silicone gel sealing portion 11 , and the upper surface of the silicone gel sealing portion 11 is in contact with the air 13 .
　蓋１０には第二のバスバー６２の断面とほぼ同じ形状を有する貫通孔（不図示）が第二のバスバー６２の数だけ設けられ、蓋１０がケース８に取り付けられると貫通孔に第二のバスバー６２が挿通される。よって第二のバスバー６２の一部は半導体装置１０００から露出される。第一のバスバー６１及び第二のバスバー６２を含むバスバー６は、外と電気的な接続を行う外部接続端子として機能する。 The lid 10 is provided with through holes (not shown) having substantially the same shape as the cross section of the second busbars 62 , the number of which is the same as the number of the second busbars 62 . A bus bar 62 is inserted. Therefore, a portion of second bus bar 62 is exposed from semiconductor device 1000 . The busbars 6 including the first busbar 61 and the second busbar 62 function as external connection terminals for electrical connection with the outside.
　図４～図７を用いて、実施の形態１における半導体装置１０００の製造方法について説明する A method for manufacturing the semiconductor device 1000 according to the first embodiment will be described with reference to FIGS.
　図４を参照し、ステップＳ１にて、ベース板１、絶縁層２２の両面に上部電極２１及び下部電極２３が形成された絶縁基板２、及び半導体素子４、２つの第一のバスバー６１を用意する。
　ベース板１と絶縁基板２とをはんだ１２で接合する。絶縁基板２の上部電極２１と半導体素子４をはんだ１２で接合する。半導体素子４と上部電極２１とをボンディングワイヤ５で接続する。さらに、上部電極２１に２つの第一のバスバー６１をはんだで接合する。このようにしてステップＳ１では、絶縁基板２、半導体素子４及びベース板１から、絶縁基板２の上面に半導体素子４が、絶縁基板２の下面にベース板１がそれぞれ接合された第一組立体１００を組み立てる組み立て工程が行われる。 4, in step S1, a base plate 1, an insulating substrate 2 having an upper electrode 21 and a lower electrode 23 formed on both surfaces of an insulating layer 22, a semiconductor element 4, and two first bus bars 61 are prepared. do.
The base plate 1 and the insulating substrate 2 are joined with solder 12 . The upper electrode 21 of the insulating substrate 2 and the semiconductor element 4 are joined with solder 12 . Semiconductor element 4 and upper electrode 21 are connected by bonding wire 5 . Furthermore, the two first bus bars 61 are soldered to the upper electrode 21 . In this way, in step S1, the semiconductor element 4 is bonded to the upper surface of the insulating substrate 2 and the base plate 1 is bonded to the lower surface of the insulating substrate 2 from the insulating substrate 2, the semiconductor element 4, and the base plate 1 to form a first assembly. An assembly process for assembling 100 is performed.
　図５を参照し、ステップＳ１の後のステップＳ２にて、上面視する方向に貫通する貫通孔９０をケース８内壁より内側に有し、上面視でケース８の内壁から貫通孔９０までの領域を埋める突出部９が設けられたケース８が用意される。ケース８がステップＳ１で作製された第一組立体１００を取り囲むように、ケース８をベース板１に接着剤又はネジ等で固定する。このようにしてステップＳ２では、突出部９が設けられたケース８を第一組立体１００のベース板１に固定するケース固定工程が行われ、その結果、第二組立体１０１が形成される。 Referring to FIG. 5, in step S2 after step S1, a through hole 90 penetrating in the direction viewed from the top is provided inside the inner wall of the case 8, and a region from the inner wall of the case 8 to the through hole 90 is formed in the top view. A case 8 provided with a protruding portion 9 for filling is prepared. The case 8 is fixed to the base plate 1 with an adhesive, screws, or the like so that the case 8 surrounds the first assembly 100 produced in step S1. Thus, in step S2, a case fixing step of fixing the case 8 provided with the projecting portion 9 to the base plate 1 of the first assembly 100 is performed, and as a result, the second assembly 101 is formed.
　図６を参照し、ステップＳ２の後のステップＳ３にて、ステップＳ２で作製した第二組立体１０１のベース板１とケース８とで取り囲まれた領域に、封止部材であるシリコーンゲルを注入する。シリコーンゲルは、低粘度の液体状物質である。その後、シリコーンゲルが注入された第二組立体１０１をオーブンにより７０℃で１時間加熱することによりシリコーンゲルが硬化し、絶縁基板２及び半導体素子４を封止するシリコーンゲル封止部１１が形成される。シリコーンゲル封止部１１は、その上面が突出部９の上面と同じ高さとなるようケース８の中に充填される。このようにしてステップＳ３では、絶縁基板２及び半導体素子４をシリコーンゲルで封止する第一の封止工程が行われ、その結果、第三組立体１０２を形成する。 Referring to FIG. 6, in step S3 after step S2, silicone gel as a sealing member is injected into the region surrounded by the base plate 1 and the case 8 of the second assembly 101 produced in step S2. do. Silicone gel is a low-viscosity liquid substance. After that, the second assembly 101 into which the silicone gel has been injected is heated in an oven at 70° C. for 1 hour to cure the silicone gel and form the silicone gel sealing portion 11 for sealing the insulating substrate 2 and the semiconductor element 4 . be done. The silicone gel sealing portion 11 is filled in the case 8 so that its upper surface is level with the upper surface of the projecting portion 9 . Thus, in step S3, a first sealing process is performed to seal the insulating substrate 2 and the semiconductor element 4 with silicone gel, and as a result, the third assembly 102 is formed.
　なおシリコーンゲル封止部１１の上面は少なくとも突出部９の底面の高さにあればよい。よって形成すべきシリコーンゲル封止部１１の上面の高さに応じて硬化前に注入されるシリコーンゲルの注入量を変える。 The upper surface of the silicone gel sealing portion 11 should be at least as high as the bottom surface of the projecting portion 9 . Therefore, the injection amount of the silicone gel to be injected before curing is changed according to the height of the upper surface of the silicone gel sealing portion 11 to be formed.
　図７を参照し、ステップＳ３の後のステップＳ４にて、２つの第二のバスバー６２が接続された制御基板７を用意する。その制御基板７をステップＳ３で形成された第三組立体１０２に取りつける。具体的には、制御基板７はシリコーンゲル封止部１１から露出した第一のバスバー６１の部分とはんだで接合する。このとき第二のバスバー６２は制御基板７の内部に形成された電気経路を介して第一のバスバー６１と電気的に接続された状態となる。このようにしてステップＳ４では、制御基板７を突出部９の上面より高い位置に取り付ける制御基板取付工程が行われ、その結果、第四組立体１０３が形成される。 Referring to FIG. 7, in step S4 after step S3, the control board 7 to which the two second bus bars 62 are connected is prepared. The control board 7 is attached to the third assembly 102 formed in step S3. Specifically, the control board 7 is soldered to the portion of the first bus bar 61 exposed from the silicone gel sealing portion 11 . At this time, the second bus bar 62 is electrically connected to the first bus bar 61 through an electrical path formed inside the control board 7 . In this manner, in step S4, a control board mounting step is performed to mount the control board 7 at a position higher than the upper surface of the projecting portion 9, and as a result, the fourth assembly 103 is formed.
　ステップＳ４の後のステップＳ５にて、蓋１０が接着剤又はネジ等を用いてステップＳ５で形成された第四組立体１０３のケース８上部に固定され、ケース８を密閉する。このとき２つの第二のバスバー６２のそれぞれ一部が蓋１０から外側に突出する。このようにして図１に示される半導体装置１０００の構造が得られる。 In step S5 after step S4, the lid 10 is fixed to the upper part of the case 8 of the fourth assembly 103 formed in step S5 using an adhesive or screws, thereby sealing the case 8. At this time, a part of each of the two second bus bars 62 protrudes outward from the lid 10 . Thus, the structure of the semiconductor device 1000 shown in FIG. 1 is obtained.
　ステップＳ５の後、必要な電気的特性等を検査して半導体装置１０００を完成させる。 After step S5, necessary electrical characteristics are inspected, and the semiconductor device 1000 is completed.
　図８及び図９を用いて、実施の形態１における半導体装置１０００の効果について説明する。図８は、実施の形態１に係る半導体装置１０００のシリコーンゲル封止部１１、突出部９及びケース８から構成される三重点付近の断面図、図９は従来の半導体装置のシリコーンゲル封止部１１、空気１３及びケース８から構成される三重点付近の断面図である。 Advantages of the semiconductor device 1000 according to the first embodiment will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is a cross-sectional view of the semiconductor device 1000 according to the first embodiment near the triple point composed of the silicone gel sealing portion 11, the protruding portion 9, and the case 8, and FIG. 9 is a silicone gel sealing of a conventional semiconductor device. 3 is a cross-sectional view of the vicinity of the triple point composed of the portion 11, the air 13 and the case 8. FIG.
　図９に示すように半導体装置１０００に突出部９がない場合、低温時、シリコーンゲル封止部１１の熱収縮により、拘束を受けないシリコーンゲル封止部１１の上面は内側に引っ張られ下方に変位するが、シリコーンゲル封止部１１の側面はケース８の壁面に拘束されるので、シリコーンゲル封止部１１、空気１３及びケース８から構成される三重点に応力が集中する。この応力が三重点から下方向へのせん断応力として働き、例えば約－７０℃の低温にもなると、図９のように、シリコーンゲル封止部１１とケース８との間での界面剥離が起こり得る。 As shown in FIG. 9, when the semiconductor device 1000 does not have the protruding portion 9, the thermal contraction of the silicone gel sealing portion 11 at low temperatures pulls the upper surface of the silicone gel sealing portion 11, which is not restrained, inward and downward. Although it is displaced, the side surface of the silicone gel sealing portion 11 is constrained by the wall surface of the case 8 , so the stress concentrates on the triple point formed by the silicone gel sealing portion 11 , the air 13 and the case 8 . This stress acts as a downward shearing stress from the triple point, and at a low temperature of, for example, about −70° C., as shown in FIG. obtain.
　これに対し、図８に示すように、実施の形態１に係る半導体装置１０００では、突出部９を設け、シリコーンゲル封止部１１が突出部９の少なくとも底面に接するので、ケース８壁面だけでなく突出部９の底面にも拘束される。そのため、シリコーンゲル封止部１１、突出部９及びケース８から構成される三重点への応力集中が緩和される。よって突出部９を設けない場合と比べて、シリコーンゲル封止部１１に働くせん断応力が抑制されるので、シリコーンゲル封止部１１とケース８との間での界面剥離を阻止できる。従って、界面剥離が起因する半導体装置１０００における部分放電及び絶縁破壊の抑制が可能となる。 In contrast, as shown in FIG. 8, in the semiconductor device 1000 according to the first embodiment, the projecting portion 9 is provided, and the silicone gel sealing portion 11 is in contact with at least the bottom surface of the projecting portion 9. It is also constrained by the bottom surface of the protruding portion 9. Therefore, stress concentration at the triple point formed by the silicone gel sealing portion 11, the protruding portion 9 and the case 8 is alleviated. Therefore, the shear stress acting on the silicone gel sealing portion 11 is suppressed compared to the case where the protruding portion 9 is not provided. Therefore, it is possible to suppress partial discharge and dielectric breakdown in the semiconductor device 1000 caused by interfacial peeling.
　なおシリコーンゲル封止部１１の上面が突出部９の上面と同じ高さに位置とした場合、図８のように、低温時のシリコーンゲル封止部１１の収縮によって、シリコーンゲル封止部１１、空気及び突出部９の三重点にシリコーンゲル封止部１１の界面剥離が生じる。しかし突出部９の底面からの拘束力により、その界面剥離はシリコーンゲル封止部１１、突出部９及びケース８の三重点には進行しにくい。
　また、シリコーンゲル封止部１１の上面が突出部９の上面より高い位置にある場合、低温時に、シリコーンゲル封止部１１、空気及びケース８の三重点から界面剥離が生じる。その界面剥離がさらに突出部９の上面にも及んだとしても、突出部９の底面からの拘束力により、その界面剥離はシリコーンゲル封止部１１、突出部９及びケース８の三重点には進行しにくい。 When the upper surface of the silicone gel sealing portion 11 is positioned at the same height as the upper surface of the protruding portion 9, as shown in FIG. , at the triple point of air and the protrusion 9, interfacial delamination of the silicone gel sealing portion 11 occurs. However, due to the restraining force from the bottom surface of the projecting portion 9 , the interfacial peeling does not easily progress to the triple point of the silicone gel sealing portion 11 , the projecting portion 9 and the case 8 .
Further, when the upper surface of the silicone gel sealing portion 11 is higher than the upper surface of the protruding portion 9, interfacial peeling occurs from the triple point of the silicone gel sealing portion 11, air, and case 8 at low temperatures. Even if the interfacial peeling extends to the upper surface of the protrusion 9, the restraining force from the bottom surface of the protruding portion 9 causes the interfacial peeling to occur at the triple point of the silicone gel sealing portion 11, the protruding portion 9, and the case 8. is difficult to progress.
　なお、半導体素子４及び絶縁基板２の封止部材としてシリコーンゲル１１０を使用する例について説明したが、その他の絶縁性のゲル状封止材及び樹脂封止材を用いてもよい。 Although the example of using the silicone gel 110 as the sealing member for the semiconductor element 4 and the insulating substrate 2 has been described, other insulating gel-like sealing materials and resin sealing materials may be used.
実施の形態２．
　図１０を用いて実施の形態２における半導体装置１００１について説明する。
　図１０は、実施の形態２における半導体装置１００１の概略構成を示す断面図である。 Embodiment 2.
A semiconductor device 1001 according to the second embodiment will be described with reference to FIG.
FIG. 10 is a cross-sectional view showing a schematic configuration of a semiconductor device 1001 according to the second embodiment.
　実施の形態１において、ケース８の内側においてシリコーンゲル封止部１１の上方が空気１３で満たされる構成について説明したが、実施の形態２では、ケース８の内部に、エポキシ樹脂封止部１４がシリコーンゲル封止部１１の上側に充填され、シリコーンゲル封止部１１とエポキシ樹脂封止部１４との間に、両者の接着を阻害する接着阻害層１５が設けられている点が異なる。それ以外の構成は実施の形態１と同様である。 In Embodiment 1, the configuration in which the space above silicone gel sealing portion 11 inside case 8 is filled with air 13 has been described. The difference is that an adhesion inhibiting layer 15 is provided between the silicone gel sealing portion 11 and the epoxy resin sealing portion 14 to prevent adhesion between the silicone gel sealing portion 11 and the epoxy resin sealing portion 14 . Other configurations are the same as those of the first embodiment.
　図１０に示すように、エポキシ樹脂封止部１４がシリコーンゲル封止部１１の上側に充填され、シリコーンゲル封止部１１とエポキシ樹脂封止部１４との間に、両者の接着を阻害する接着阻害層１５が設けられている。 As shown in FIG. 10, the epoxy resin sealing portion 14 is filled on the upper side of the silicone gel sealing portion 11, and the adhesion between the silicone gel sealing portion 11 and the epoxy resin sealing portion 14 is inhibited. An adhesion inhibiting layer 15 is provided.
　接着阻害層１５はケース８の内側においてシリコーンゲル封止部１１の上面及び突出部９の上面に接するように設けられる。
　接着阻害層１５の構成として、（１）エポキシ樹脂封止部１４とは接着し難く、シリコーンゲル封止部１１とは接着する物質層、（２）エポキシ樹脂封止部１４及びシリコーンゲル封止部１１共に接着するが、非常に破壊しやすい物質層、（３）エポキシ樹脂封止部１４及びシリコーンゲル封止部１１共に接着しにくい物質層を当該界面に設置することが考えられる。 The adhesion inhibiting layer 15 is provided inside the case 8 so as to be in contact with the upper surface of the silicone gel sealing portion 11 and the upper surface of the projecting portion 9 .
The structure of the adhesion inhibiting layer 15 includes (1) a material layer that is difficult to adhere to the epoxy resin sealing portion 14 but adheres to the silicone gel sealing portion 11, and (2) the epoxy resin sealing portion 14 and silicone gel sealing. (3) A material layer that adheres to both the portion 11 but is very fragile, and (3) a substance layer that does not easily adhere to both the epoxy resin sealing portion 14 and the silicone gel sealing portion 11 may be placed at the interface.
　接着阻害層１５の具体的な材質としては、シリコーンゲルとは異なる成分を有しており、（１）は粉体、フッ素含有物質、ケイ素含有物質から選択される単一あるいは複数の物質、（２）は粉末シリカ，粉末アルミナ，タルクから選択される単一若しくは複数の粉体物質、（３）はシリコーンオイル等の液体状の物質が挙げられる。 Specific materials for the adhesion-inhibiting layer 15 include components different from silicone gel, and (1) is a single or multiple substance selected from powders, fluorine-containing substances, and silicon-containing substances; 2) is a single or multiple powder substance selected from powdered silica, powdered alumina, and talc, and (3) is a liquid substance such as silicone oil.
　エポキシ樹脂封止部１４は、ケース８の内側において接着阻害層１５に接するように設けられる。エポキシ樹脂封止部１４はエポキシ樹脂又はエポキシ樹脂を主成分とする材料からなり、その体積膨張係数は６０～１５０ｐｐｍ／Ｋ程度である。エポキシ樹脂封止部１４は、エポキシ樹脂封止部１４の上面が制御基板７の上面以上の高さまで充填されている。エポキシ樹脂封止部１４を充填するとしても、図１０のように、エポキシ樹脂封止部１４の上面と蓋１０との間には空隙を設け、エポキシ樹脂封止部１４の上面は空気１３と接するのが望ましい。 The epoxy resin sealing portion 14 is provided inside the case 8 so as to be in contact with the adhesion inhibiting layer 15 . The epoxy resin sealing portion 14 is made of epoxy resin or a material containing epoxy resin as a main component, and has a volume expansion coefficient of about 60 to 150 ppm/K. The epoxy resin sealing portion 14 is filled so that the upper surface of the epoxy resin sealing portion 14 is higher than the upper surface of the control board 7 . Even if the epoxy resin sealing portion 14 is filled, a gap is provided between the upper surface of the epoxy resin sealing portion 14 and the lid 10 as shown in FIG. contact is desirable.
　図１１～図１３を用いて、実施の形態２における半導体装置１００１の製造方法について説明する。実施の形態１におけるステップＳ１～Ｓ３は実施の形態２にも適用される。 A method for manufacturing the semiconductor device 1001 according to the second embodiment will be described with reference to FIGS. 11 to 13. FIG. Steps S1 to S3 in the first embodiment are also applied to the second embodiment.
　図１１を参照し、ステップＳ３の後のステップＳ６にて、第三組立体１０２のケース８の内部に接着阻害層１５を形成する。具体的には、第三組立体１０２のシリコーンゲル封止部１１の上面及び突出部９の上面に、シート状の接着阻害物質を配置する、スプレー等で接着阻害物質を吹き付ける、ペースト状の接着阻害物質を塗布する、又は接着阻害物質を低温で焼き入れる、等により接着阻害層１５が形成される。このとき２つの第一のバスバー６１の一部は接着阻害層１５の上面から突出している。このようにしてステップＳ６では、シリコーンゲル封止部１１の上面に接着阻害層１５を配置する接着阻害層配置工程が行われ、その結果、第五組立体１０４が形成される。 Referring to FIG. 11, in step S6 after step S3, the adhesion inhibiting layer 15 is formed inside the case 8 of the third assembly 102. As shown in FIG. Specifically, on the upper surface of the silicone gel sealing portion 11 and the upper surface of the protruding portion 9 of the third assembly 102, a sheet-like adhesion inhibiting substance is placed, an adhesion inhibiting substance is sprayed with a spray or the like, or a paste adhesion is performed. The adhesion-inhibiting layer 15 is formed by applying an adhesion-inhibiting substance, baking the adhesion-inhibiting substance at a low temperature, or the like. At this time, part of the two first bus bars 61 protrude from the upper surface of the adhesion inhibition layer 15 . In this way, in step S6, the adhesion inhibiting layer arranging step of arranging the adhesion inhibiting layer 15 on the upper surface of the silicone gel sealing portion 11 is performed, and as a result, the fifth assembly 104 is formed.
　図１２を参照し、ステップＳ６の後のステップＳ７にて、２つの第二のバスバー６２が接続された制御基板７を用意する。その制御基板７をステップＳ６で形成された第五組立体１０４に取り付ける。具体的には、制御基板７は接着阻害層１５から露出した第一のバスバー６１の部分とはんだで接合する。このとき第二のバスバー６２は制御基板７の内部に形成された電気経路を介して第一のバスバー６１と電気的に接続された状態となる。このようにしてステップＳ７では、制御基板７を突出部９の上面より高い位置に取り付ける制御基板取付工程が行われ、その結果、第六組立体１０５が形成される。 With reference to FIG. 12, in step S7 after step S6, the control board 7 to which the two second bus bars 62 are connected is prepared. The control board 7 is attached to the fifth assembly 104 formed in step S6. Specifically, the control board 7 is soldered to the portion of the first bus bar 61 exposed from the adhesion inhibition layer 15 . At this time, the second bus bar 62 is electrically connected to the first bus bar 61 through an electrical path formed inside the control board 7 . In this way, in step S7, a control board mounting step is performed to mount the control board 7 at a position higher than the upper surface of the projecting portion 9, and as a result, the sixth assembly 105 is formed.
　図１３を参照し、ステップＳ７の後のステップＳ８にて、第六組立体１０５のケース８の内部にエポキシ樹脂封止部１４を形成する。具体的には、エポキシ樹脂又はエポキシ樹脂を主成分とする材料である封止材を接着阻害層１５の上面に注入する。続いて、その封止材が注入された第六組立体１０５をオーブンにより１５０℃で１～２時間、引き続き２００℃で２時間加熱して封止材を硬化し、エポキシ樹脂封止部１４を形成する。このときエポキシ樹脂封止部１４の上面は、制御基板７の上面以上に位置する。このようにしてステップＳ８では、接着阻害層１５の上面をエポキシ樹脂で封止する第二の封止工程が行われ、その結果、第七組立体１０６が形成される。 Referring to FIG. 13, in step S8 after step S7, the epoxy resin sealing portion 14 is formed inside the case 8 of the sixth assembly 105. As shown in FIG. Specifically, a sealing material, which is an epoxy resin or a material containing epoxy resin as a main component, is injected onto the upper surface of the adhesion inhibiting layer 15 . Subsequently, the sixth assembly 105 into which the sealing material has been injected is heated in an oven at 150° C. for 1 to 2 hours and then at 200° C. for 2 hours to harden the sealing material, and the epoxy resin sealing portion 14 is formed. Form. At this time, the upper surface of the epoxy resin sealing portion 14 is positioned above the upper surface of the control board 7 . Thus, in step S8, a second sealing process is performed to seal the upper surface of the adhesion inhibiting layer 15 with epoxy resin, and as a result, the seventh assembly 106 is formed.
　ステップＳ８の後、実施の形態１のステップＳ５と同じ工程が実施されることによって、図１０に示される半導体装置１００１の構造が得られる。 After step S8, the same process as step S5 of the first embodiment is performed to obtain the structure of the semiconductor device 1001 shown in FIG.
　実施の形態２に係る半導体装置１００１において、上記（１）のように、接着阻害層１５がエポキシ樹脂封止部１４とは接着し難く、シリコーンゲル封止部１１とは接着する材料である場合、低温時にシリコーンゲル封止部１１が熱収縮することに伴い、シリコーンゲル封止部１１に働く圧縮応力によりシリコーンゲル封止部１１及び接着阻害層１５の中に含まれる気泡が移動し、接着阻害層１５とエポキシ樹脂封止部１４との間に空隙が生じる。 In the semiconductor device 1001 according to the second embodiment, as in (1) above, when the adhesion inhibition layer 15 is made of a material that is difficult to adhere to the epoxy resin sealing portion 14 but adheres to the silicone gel sealing portion 11, As the silicone gel sealing portion 11 thermally shrinks at a low temperature, the compressive stress acting on the silicone gel sealing portion 11 causes the air bubbles contained in the silicone gel sealing portion 11 and the adhesion inhibiting layer 15 to move, resulting in adhesion. A gap is formed between the inhibition layer 15 and the epoxy resin sealing portion 14 .
　上記（２）のように、接着阻害層１５がエポキシ樹脂封止部１４及びシリコーンゲル封止部１１共に接着するが非常に破壊しやすい材料である場合、シリコーンゲル封止部１１が熱収縮すると、接着阻害層１５がエポキシ樹脂封止部１４に拘束されるものの接着阻害層１５に破壊が起こり、接着阻害層１５に空隙が生じる。 As in (2) above, when the adhesion inhibiting layer 15 adheres to both the epoxy resin sealing portion 14 and the silicone gel sealing portion 11 but is made of a material that is very easily destroyed, if the silicone gel sealing portion 11 thermally shrinks, Although the adhesion inhibiting layer 15 is restrained by the epoxy resin sealing portion 14 , the adhesion inhibiting layer 15 is broken and voids are generated in the adhesion inhibiting layer 15 .
　さらに上記（３）のように、エポキシ樹脂封止部１４及びシリコーンゲル封止部１１共に接着しにくい材料である場合、シリコーンゲル封止部１１及び接着阻害層１５の中に含まれる気泡が移動し、接着阻害層１５とエポキシ樹脂封止部１４との間に空隙が生じる。
　接着阻害層１５がシリコーンゲル封止部１１に接着しにくい材料であっても、シリコーンゲル封止部１１と接着阻害層１５との間に空隙が生じないのは、上記（３）が液体状だからである。 Furthermore, as in (3) above, when both the epoxy resin sealing portion 14 and the silicone gel sealing portion 11 are made of materials that are difficult to adhere to, air bubbles contained in the silicone gel sealing portion 11 and the adhesion inhibiting layer 15 move. Then, a gap is generated between the adhesion inhibiting layer 15 and the epoxy resin sealing portion 14 .
Even if the adhesion-inhibiting layer 15 is made of a material that is difficult to adhere to the silicone gel sealing portion 11, no gap is formed between the silicone gel-sealing portion 11 and the adhesion-inhibiting layer 15 because (3) above is a liquid state. That's why.
　（１）～（３）のいずれであっても、低温時、シリコーンゲル封止部１１の上面は内側からの引っ張り力によって下方に変位する。しかし実施の形態１と同様、シリコーンゲル封止部１１は、突出部９の底面に接するので、突出部９の底面に拘束される。シリコーンゲル封止部１１の上面が変位しても、突出部９の底面からの拘束によってシリコーンゲル封止部１１、突出部９及びケース８から構成される三重点に応力が集中することが避けられる。従って、シリコーンゲル封止部１１とケース８との間での界面剥離を阻止できる。 In any of (1) to (3), when the temperature is low, the upper surface of the silicone gel sealing portion 11 is displaced downward by a pulling force from the inside. However, as in the first embodiment, the silicone gel sealing portion 11 is in contact with the bottom surface of the projecting portion 9 , and is constrained by the bottom surface of the projecting portion 9 . Even if the upper surface of the silicone gel sealing portion 11 is displaced, the concentration of stress on the triple point formed by the silicone gel sealing portion 11, the protrusion 9, and the case 8 can be avoided by restraint from the bottom surface of the protrusion 9. be done. Therefore, interfacial separation between the silicone gel sealing portion 11 and the case 8 can be prevented.
　さらに、高温時（例えば約１８０℃）又は低気圧時（例えば、約１０ｋＰａ）、熱膨張するシリコーンゲル１１０がエポキシ樹脂封止部１４により押さえられるため、シリコーンゲル１１０に圧縮応力が働き、シリコーンゲル１１０中で気泡の発生を阻止でき。シリコーンゲル１１０と絶縁基板２との間で界面剥離の発生を阻止できる。従って高温時又は低気圧時における半導体装置１００１における部分放電及び絶縁破壊の抑制が可能となる。 Furthermore, when the temperature is high (for example, about 180° C.) or when the pressure is low (for example, about 10 kPa), the thermally expanding silicone gel 110 is pressed by the epoxy resin sealing portion 14, so a compressive stress acts on the silicone gel 110, and the silicone gel 110 is compressed. In 110, the generation of air bubbles can be prevented. Interfacial separation between the silicone gel 110 and the insulating substrate 2 can be prevented. Therefore, it is possible to suppress partial discharge and dielectric breakdown in the semiconductor device 1001 at high temperature or low pressure.
　なお、半導体素子４及び絶縁基板２を封止する第一の封止材の上側に充填される封止部材としてエポキシ樹脂封止部１４を使用する例について説明したが、ウレタン樹脂等、第一の封止材より硬質の樹脂を封止部材として用いてもよい。 The example of using the epoxy resin sealing portion 14 as the sealing member filled on the upper side of the first sealing material that seals the semiconductor element 4 and the insulating substrate 2 has been described. A resin harder than the sealing material may be used as the sealing member.
　また、半導体素子４及び絶縁基板２を封止する第一の封止材にシリコーンゲル、第一の封止材の上側に充填される第二の封止材にエポキシ樹脂を用いる例について説明したが、第二の封止材は、第一の封止材よりも体積膨張係数が小さい樹脂であればよい。 Also, an example has been described in which silicone gel is used as the first sealing material for sealing the semiconductor element 4 and the insulating substrate 2, and epoxy resin is used as the second sealing material filled on the upper side of the first sealing material. However, the second sealing material may be a resin having a smaller volume expansion coefficient than the first sealing material.
　図１４は、本開示に係る半導体装置１０００及び半導体装置１００１の突出部９の変形例として突出部９ａの構成を示す断面図である。
　半導体装置１０００及び半導体装置１００１では突出部９の内側面が、シリコーンゲル封止部１１の上面にほぼ直交する平面をなしている。図１４に示すように、突出部９ａでは、内側面と上面との角及び内側面と底面との角にそれぞれ丸みをつけている。この丸み部分においてシリコーンゲル封止部１１に生じる応力が緩和されるので、シリコーンゲル封止部１１は突出部９から剥がれにくくなる。 FIG. 14 is a cross-sectional view showing a configuration of a protruding portion 9a as a modified example of the protruding portion 9 of the semiconductor device 1000 and the semiconductor device 1001 according to the present disclosure.
In the semiconductor device 1000 and the semiconductor device 1001 , the inner side surface of the protruding portion 9 forms a plane substantially perpendicular to the upper surface of the silicone gel sealing portion 11 . As shown in FIG. 14, in the projecting portion 9a, the corners between the inner surface and the upper surface and the corners between the inner surface and the bottom surface are rounded. Since the stress generated in the silicone gel sealing portion 11 is relieved at this rounded portion, the silicone gel sealing portion 11 is less likely to separate from the projecting portion 9 .
　また、上述以外にも、各実施の形態の自由な組み合わせ、各実施の形態の任意の構成要素の変形、又は各実施の形態の任意の構成要素の省略が可能である。 In addition to the above, it is possible to freely combine each embodiment, modify any component of each embodiment, or omit any component of each embodiment.
　１　ベース板、２　絶縁基板、４　半導体素子、５　ボンディングワイヤ、６　バスバー、７　制御基板、８　ケース、９　突出部、１０　蓋、１１　シリコーンゲル封止部、１２　はんだ、１３　空気、１４　エポキシ樹脂封止部、１５　接着阻害層、１０００　半導体装置 1 base plate, 2 insulating substrate, 4 semiconductor element, 5 bonding wire, 6 bus bar, 7 control board, 8 case, 9 protrusion, 10 lid, 11 silicone gel sealing portion, 12 solder, 13 air, 14 epoxy resin sealing Stopping portion, 15 Adhesion inhibition layer, 1000 Semiconductor device

Claims (16)

  1. 　表面に半導体素子が搭載された絶縁基板と、
    　前記絶縁基板の裏面に接合されたベース板と、
    　前記ベース板に固定され前記絶縁基板を取り囲むケースと、
    　前記ケースの内部に充填され、前記半導体素子及び前記絶縁基板を封止する第一の封止部と、
    　前記ケースの内壁から突出するように設けられた突出部と、
    を備え、
    　前記突出部は、上面視する方向に貫通する貫通孔を前記ケースの内壁より内側に有し、上面視で前記ケースの内壁から前記貫通孔までの領域を埋め、
    　前記第一の封止部が前記突出部の少なくとも底面に接するように充填されることを、
    　特徴とする半導体装置。     an insulating substrate having a semiconductor element mounted on its surface;
    a base plate bonded to the back surface of the insulating substrate;
    a case fixed to the base plate and surrounding the insulating substrate;
    a first sealing portion filled in the case and sealing the semiconductor element and the insulating substrate;
    a protrusion provided to protrude from the inner wall of the case;
    with
    The protruding portion has a through hole penetrating in a top view direction inside the inner wall of the case, and fills a region from the inner wall of the case to the through hole when viewed from the top,
    that the first sealing portion is filled so as to be in contact with at least the bottom surface of the protruding portion;
    A semiconductor device characterized by:
  2. 　前記ケースの内部に充填され、前記第一の封止部の上側に設けられた第二の封止部と、
    　前記第一の封止部と前記第二の封止部との間に設けられ、前記第一の封止部と前記第二の封止部との接着を阻害する接着阻害層と、
    　をさらに備えることを、
    　特徴とする請求項１に記載の半導体装置。     a second sealing portion filled inside the case and provided above the first sealing portion;
    an adhesion inhibition layer provided between the first sealing portion and the second sealing portion and inhibiting adhesion between the first sealing portion and the second sealing portion;
    to further provide
    2. A semiconductor device according to claim 1.
  3. 　前記第一の封止部はシリコーンゲルであることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first sealing portion is silicone gel.
  4. 　前記第二の封止部は前記第一の封止部よりも体積膨張係数が小さい樹脂により形成されることを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the second sealing portion is made of a resin having a smaller coefficient of volume expansion than the first sealing portion.
  5. 　前記第一の封止部はシリコーンゲルであり、前記第二の封止部はエポキシ樹脂であることを特徴とする請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the first sealing portion is silicone gel, and the second sealing portion is epoxy resin.
  6. 　前記接着阻害層は、前記第一の封止部と異なる成分を有し、
    　前記接着阻害層は、粉体、フッ素含有物質、ケイ素含有物質から選択される単一若しくは複数の物質と、粉末シリカ，粉末アルミナ，タルクから選択される単一若しくは複数の粉体物質と、液体状物質とのうちいずれかであることを特徴とする請求項２に記載の半導体装置。     The adhesion inhibition layer has a component different from that of the first sealing portion,
    The adhesion-inhibiting layer comprises a single or a plurality of substances selected from powder, a fluorine-containing substance, and a silicon-containing substance, a single or a plurality of powder substances selected from powdered silica, powdered alumina, and talc, and a liquid 3. The semiconductor device according to claim 2, wherein the semiconductor device is one of: a.
  7. 　前記突出部の上面より高い位置に、前記絶縁基板と間隔を空けて前記ケースの内部に配置され、前記半導体素子と電気的に接続される制御基板、
    をさらに備えることを特徴とする請求項１～６の何れか１項に記載の半導体装置。     a control board disposed inside the case at a position higher than the upper surface of the projecting portion with a gap from the insulating board and electrically connected to the semiconductor element;
    7. The semiconductor device according to claim 1, further comprising:
  8. 　前記第一の封止部の上面は前記制御基板よりも下側に存在することを特徴とする請求項７に記載の半導体装置。 The semiconductor device according to claim 7, wherein the upper surface of said first sealing portion is located below said control substrate.
  9. 　前記突出部の上面より高い位置に、前記絶縁基板と間隔を空けて前記ケースの内部に配置され、前記半導体素子と電気的に接続される制御基板、
    　をさらに備え、
    　前記第一の封止部の上面は前記制御基板よりも下側に存在し、
    　前記第二の封止部の上面が前記制御基板の上面以上に存在すること、
    　を特徴とする請求項２及び請求項４～６の何れか１項に記載の半導体装置。     a control board disposed inside the case at a position higher than the upper surface of the projecting portion with a gap from the insulating board and electrically connected to the semiconductor element;
    further comprising
    an upper surface of the first sealing portion is located below the control substrate;
    that the upper surface of the second sealing portion is above the upper surface of the control board;
    The semiconductor device according to any one of claims 2 and 4 to 6, characterized by:
  10. 　前記絶縁基板及び前記制御基板に取り付けられ、外部と電気的な接続を行う外部接続端子をさらに備えることを特徴とする請求項７～９のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 7 to 9, further comprising external connection terminals attached to said insulating substrate and said control substrate for electrical connection with the outside.
  11. 　絶縁基板、半導体素子及びベース板から、前記絶縁基板の上面に前記半導体素子が、前記絶縁基板の下面に前記ベース板がそれぞれ接合された組立体を組み立てる組み立て工程と、
    　上面視でする方向に貫通する貫通孔をケースの内壁より内側に有し、上面視で前記ケースの内壁から前記貫通孔までの領域を埋める突出部が設けられた前記ケースを、前記ベース板に固定するケース固定工程と、
    　前記絶縁基板及び前記半導体素子を第一の封止材で封止する第一の封止工程と、
    　を備え、
    　前記第一の封止工程により得られる前記第一の封止材は、その上面が前記突出部のすくなとも下面に接するように前記ケース内に充填されていることを特徴とする半導体装置の製造方法。     an assembling step of assembling an assembly in which the semiconductor element is bonded to the upper surface of the insulating substrate and the base plate is bonded to the lower surface of the insulating substrate from the insulating substrate, the semiconductor element, and the base plate;
    The case having a through hole penetrating in a direction viewed from the top inside the inner wall of the case and provided with a projecting portion filling a region from the inner wall of the case to the through hole when viewed from the top is mounted on the base plate. a case fixing step to be fixed;
    a first sealing step of sealing the insulating substrate and the semiconductor element with a first sealing material;
    with
    Manufacture of a semiconductor device, wherein the first sealing material obtained by the first sealing step is filled in the case so that the upper surface of the first sealing material is in contact with the lower surface of the projecting portion. Method.
  12. 　前記第一の封止材の上面に接着阻害層を配置する接着阻害層配置工程と、
    　前記接着阻害層の上面を第二の封止材で封止する第二の封止工程と、
    　をさらに備えることを特徴とする請求項１１に記載の半導体装置の製造方法。     an adhesion inhibition layer placing step of arranging an adhesion inhibition layer on the upper surface of the first sealing material;
    a second sealing step of sealing the upper surface of the adhesion inhibition layer with a second sealing material;
    12. The method of manufacturing a semiconductor device according to claim 11, further comprising:
  13. 　制御基板を前記ケースの内部に且つ前記突出部の上面よりも高い位置に取り付ける制御基板取付工程をさらに備えることを特徴とする請求項１１及び請求項１２の何れか１項に記載の半導体装置の製造方法。 13. The semiconductor device according to claim 11, further comprising a control board mounting step of mounting a control board inside said case at a position higher than the upper surface of said projecting portion. Production method.
  14. 　前記制御基板取付工程において、前記制御基板は前記第一の封止材の上面より高い位置に取り付けられることを特徴とする請求項１３に記載の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 13, wherein in said control board mounting step, said control board is mounted at a position higher than the upper surface of said first sealing material.
  15. 　制御基板を前記ケースの内部に且つ前記突出部の上面よりも高い位置に取り付ける制御基板取付工程を備え、
    　前記制御基板取付工程において、前記制御基板は前記第一の封止材の上面より高い位置に取り付けられ、
    　前記第二の封止工程は前記制御基板取付工程の後に行われ、前記第二の封止工程により得られる前記第二の封止材は、その上面が前記制御基板の上面以上に位置するように前記ケース内に充填されることを特徴とする請求項１２に記載の半導体装置の製造方法。     A control board mounting step of mounting a control board inside the case at a position higher than the upper surface of the protrusion,
    In the control board mounting step, the control board is mounted at a position higher than the upper surface of the first sealing material,
    The second sealing step is performed after the control board attaching step, and the second sealing material obtained by the second sealing step is arranged such that the upper surface thereof is located above the upper surface of the control substrate. 13. The method of manufacturing a semiconductor device according to claim 12, wherein said case is filled with a metal.
  16. 　前記組み立て工程において、バスバーを前記絶縁基板に取り付けることにより、前記バスバーが前記半導体素子と電気的に接続された前記組立体を組み立て、
    　前記制御基板取付工程は前記第一の封止工程の後に行われ、前記バスバーの前記第一の封止材から露出した部分に前記制御基板が取り付けられることを特徴とする請求項１３～１５の何れか１項に記載の半導体装置の製造方法。     assembling the assembly in which the bus bar is electrically connected to the semiconductor element by attaching the bus bar to the insulating substrate in the assembling step;
    The control board mounting step is performed after the first sealing step, and the control board is mounted on a portion of the bus bar exposed from the first sealing material. A method for manufacturing a semiconductor device according to any one of the items.
PCT/JP2021/039646 2021-10-27 2021-10-27 Semiconductor device and method for manufacturing semiconductor device WO2023073831A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/039646 WO2023073831A1 (en) 2021-10-27 2021-10-27 Semiconductor device and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/039646 WO2023073831A1 (en) 2021-10-27 2021-10-27 Semiconductor device and method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO2023073831A1 true WO2023073831A1 (en) 2023-05-04

Family

ID=86159229

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/039646 WO2023073831A1 (en) 2021-10-27 2021-10-27 Semiconductor device and method for manufacturing semiconductor device

Country Status (1)

Country Link
WO (1) WO2023073831A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464255A (en) * 1990-07-03 1992-02-28 Mitsubishi Electric Corp Semiconductor device
JPH06163745A (en) * 1992-11-24 1994-06-10 Matsushita Electric Works Ltd Module-substrate sealing frame
JPH08316357A (en) * 1995-05-15 1996-11-29 Hitachi Ltd Resin sealed power module
JP2013055150A (en) * 2011-09-01 2013-03-21 Toshiba Corp Semiconductor device and manufacturing method thereof
WO2017082122A1 (en) * 2015-11-12 2017-05-18 三菱電機株式会社 Power module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464255A (en) * 1990-07-03 1992-02-28 Mitsubishi Electric Corp Semiconductor device
JPH06163745A (en) * 1992-11-24 1994-06-10 Matsushita Electric Works Ltd Module-substrate sealing frame
JPH08316357A (en) * 1995-05-15 1996-11-29 Hitachi Ltd Resin sealed power module
JP2013055150A (en) * 2011-09-01 2013-03-21 Toshiba Corp Semiconductor device and manufacturing method thereof
WO2017082122A1 (en) * 2015-11-12 2017-05-18 三菱電機株式会社 Power module

Similar Documents

Publication Publication Date Title
JP5807348B2 (en) Semiconductor device and manufacturing method thereof
JP6309112B2 (en) Power module
US6867484B2 (en) Semiconductor device
JP6676079B2 (en) Semiconductor device and manufacturing method thereof
US10727145B2 (en) Semiconducter device with filler to suppress generation of air bubbles and electric power converter
JP6398270B2 (en) Semiconductor device
CN108292655B (en) Power module
JP7247574B2 (en) semiconductor equipment
JP2009252838A (en) Semiconductor device
US11699625B2 (en) Power semiconductor module arrangement
US20220051960A1 (en) Power Semiconductor Module Arrangement and Method for Producing the Same
JP5328740B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP6820934B2 (en) Power module and its manufacturing method
WO2023073831A1 (en) Semiconductor device and method for manufacturing semiconductor device
JPH10173098A (en) Power semiconductor device and its manufacture
JP7439521B2 (en) Semiconductor module and semiconductor module manufacturing method
JP7157783B2 (en) Semiconductor module manufacturing method and semiconductor module
CN111244061A (en) Packaging structure of gallium nitride equipment
JP7237214B2 (en) METAL SUBSTRATE STRUCTURE FOR SEMICONDUCTOR POWER MODULE, METHOD FOR MANUFACTURING METAL SUBSTRATE STRUCTURE AND SEMICONDUCTOR POWER MODULE
US20240186199A1 (en) Semiconductor power module and method for manufacturing a semiconductor power module
US20230282541A1 (en) Semiconductor device
JP7494521B2 (en) Semiconductor device and method for manufacturing the same
US20230317534A1 (en) Semiconductor device and method of producing semiconductor device
JP2024504838A (en) Metal substrate structure, method for manufacturing metal substrate structure for semiconductor power module, and semiconductor power module
JP2021141237A (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21962380

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE