WO2023071560A1 - Display module and display device - Google Patents

Display module and display device Download PDF

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Publication number
WO2023071560A1
WO2023071560A1 PCT/CN2022/118386 CN2022118386W WO2023071560A1 WO 2023071560 A1 WO2023071560 A1 WO 2023071560A1 CN 2022118386 W CN2022118386 W CN 2022118386W WO 2023071560 A1 WO2023071560 A1 WO 2023071560A1
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WO
WIPO (PCT)
Prior art keywords
pixel
circuit
sub
display module
layer
Prior art date
Application number
PCT/CN2022/118386
Other languages
French (fr)
Chinese (zh)
Inventor
叶成亮
刘长瑜
郭天福
Original Assignee
Oppo广东移动通信有限公司
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Application filed by Oppo广东移动通信有限公司 filed Critical Oppo广东移动通信有限公司
Publication of WO2023071560A1 publication Critical patent/WO2023071560A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a display module and a display device.
  • a display module and a display device are provided.
  • a display module comprising:
  • a pixel circuit array including a plurality of first pixel sub-circuits, a plurality of second pixel sub-circuits and circuit wiring, each of the second pixel sub-circuits is respectively located in two adjacent first pixels in the first direction Between the sub-circuits, the first direction is perpendicular to the thickness direction of the display module;
  • a light emitting device array the size of the light emitting device array in the first direction is larger than the size of the pixel circuit array in the first direction, the light emitting device array includes a plurality of light emitting devices, the light emitting device includes a cathode and an anode, The anodes of the plurality of light-emitting devices are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence;
  • the circuit wiring is connected to the cathodes of a plurality of the light emitting devices.
  • a display device comprising: the above-mentioned display module.
  • FIG. 1 is one of the structural schematic diagrams of a display module of an embodiment
  • FIG. 2 is one of the structural schematic diagrams of a pixel circuit array according to an embodiment
  • Fig. 3 is a schematic structural diagram of a light emitting device array according to an embodiment
  • FIG. 4 is a schematic structural diagram of a display module without a second pixel sub-circuit
  • FIG. 5 is a schematic cross-sectional view of a display module according to an embodiment
  • Fig. 6 is a schematic structural view of a first repeating unit and a corresponding light-emitting device in an embodiment
  • FIG. 7 is a circuit diagram of a first pixel sub-circuit according to an embodiment
  • FIG. 8 is one of partial structural schematic diagrams of a display module of an embodiment
  • FIG. 9 is a schematic cross-sectional view of the display module of the embodiment in FIG. 8;
  • FIG. 10 is a second schematic diagram of a partial structure of a display module of an embodiment
  • FIG. 11 is a schematic cross-sectional view of the display module of the embodiment in FIG. 10;
  • FIG. 12 is a third schematic diagram of a partial structure of a display module of an embodiment
  • FIG. 13 is a schematic cross-sectional view of the display module of the embodiment in FIG. 12;
  • FIG. 14 is one of the simplified cross-sectional schematic diagrams of a display module according to an embodiment
  • FIG. 15 is a second simplified cross-sectional schematic diagram of a display module of an embodiment
  • FIG. 16 is the second structural schematic diagram of a pixel circuit array in an embodiment
  • FIG. 17 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 16;
  • FIG. 18 is a third schematic structural diagram of a pixel circuit array in an embodiment
  • FIG. 19 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 18;
  • FIG. 20 is a fourth schematic structural diagram of a pixel circuit array in an embodiment
  • FIG. 21 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 20 .
  • Pixel circuit array 100; circuit routing: 101; first sub-array area: 110; first pixel circuit: 111; first gate layer: 1101a; second gate layer: 1101b; first source: 1102; First drain: 1103; source contact structure: 1104; drain contact structure: 1105; pixel definition layer: 1106; anode layer: 1107; luminescent material layer: 1108; cathode layer: 1109; substrate: 1110; polyimide Amine (PI) substrate layer: 1110a; first buffer layer: 1110b; first gate insulating layer: 1111; second gate insulating layer: 1112; interlayer insulating layer: 1113; planarization layer: 1114; second pixel circuit: 112; the first metallization hole: 1121; the second metallization hole: 1122; the third metallization hole: 1123; the first repeating unit: 113; the second sub-array area: 120; the third sub-array area: 130; Three-pixel circuit: 131; fourth sub-array area: 140; fourth
  • first, second and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
  • a first direction could be termed a second direction, and, similarly, a second direction could be termed a first direction, without departing from the scope of the present application.
  • Both the first direction and the second direction are directions, but they are not the same direction.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • plural means at least two, such as two, three, etc., unless otherwise specifically defined.
  • severeal means at least one, such as one, two, etc., unless otherwise specifically defined.
  • FIG. 1 is one of the structural schematic diagrams of a display module according to an embodiment.
  • the display module according to this embodiment includes a pixel circuit array and a light emitting device array.
  • the display module of the embodiment of the present application is applied to a display device with a narrow frame.
  • the display device may be a smart phone, a tablet computer, a game device, an augmented reality (Augmented Reality, AR) device, a notebook, a desktop computing device, a wearable device, and the like.
  • AR Augmented Reality
  • FIG. 2 is one of the structural schematic diagrams of a pixel circuit array in an embodiment
  • FIG. 3 is a structural schematic diagram of a light emitting device array in an embodiment.
  • the pixel circuit array 100 and the light emitting device array 200 are stacked in the thickness direction of the display device to form Display mods.
  • the size of the light emitting device array 200 in the first direction is larger than the size of the pixel circuit array 100 in the first direction. It can be understood that, compared with the 1:1 arrangement of the size of the light emitting device array 200 and the pixel circuit array 100, based on the size setting method of this embodiment, the size of the light emitting device array 200 can be kept unchanged, By relatively reducing the size of the pixel circuit array 100 , a certain space is provided for arranging other peripheral circuits.
  • Other peripheral circuits include but are not limited to gate drive circuits, fan-out wire group 500 and so on.
  • other peripheral circuits and the pixel circuit array 100 can be arranged in the same layer, and the light emitting device array 200 can be partially arranged on other peripheral circuits.
  • the size difference between the light emitting device array 200 and the pixel circuit array 100 determines the specific area where other peripheral circuits can be arranged under the light emitting device array 200 . That is, the smaller the size of the pixel circuit array 100 compared with the light emitting device array 200, the larger the specific area that other peripheral circuits can be arranged under the light emitting device array 200.
  • other peripheral circuits are exposed to the light emitting device in the first direction. The smaller the area outside the array 200 is, the smaller the width of the frame used to shield the above-mentioned other peripheral circuits is. Therefore, based on the above arrangement, the frame width of the display module in the first direction can be narrowed.
  • the pixel circuit array 100 includes a plurality of first pixel sub-circuits and a plurality of second pixel sub-circuits.
  • Each of the second pixel sub-circuits is respectively located between two adjacent first pixel sub-circuits in a first direction, and the first direction is perpendicular to the thickness direction of the display module.
  • the first pixel sub-circuit can be understood as a pixel sub-circuit that is actually used to control characteristics such as light-emitting brightness and light-emitting color of the light-emitting device array 200 .
  • the second pixel sub-circuit can be understood as a dummy pixel sub-circuit (dummy pixel). As shown in FIG.
  • the light emitting device array 200 includes a plurality of light emitting devices 201 including cathodes and anodes.
  • the anodes of each of the plurality of light-emitting devices 201 are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence.
  • the dot structure located at the lower part of each first pixel sub-circuit in FIG. 2 is the node for connecting the first pixel sub-circuit to the light emitting device 201.
  • the circle structure in each light emitting device 201 in FIG. 3 is is used to connect the anode of the first pixel sub-circuit. It should be noted that the circle structures in the embodiments in FIG. 2 and FIG.
  • the second pixel sub-circuit can fill the gap between the first pixel sub-circuits caused by size reduction, so as to achieve the above-mentioned purpose of position correspondence, improve the arrangement uniformity of the first pixel sub-circuit, thereby improving the display uniformity of the display module. sex.
  • Fig. 4 is a schematic structural diagram of a display module without a second pixel sub-circuit.
  • the wiring refers to the wiring connected between the light emitting device and the corresponding first pixel sub-circuit.
  • the light emitting device on the left side in FIG. 4 can be understood as the light emitting device near the center of the display module, and the light emitting device on the right side in FIG. 4 can be understood as the light emitting device near the frame of the display module.
  • the length difference between the two driving wires is large, which will lead to the difference in the performance of the light emitting device such as response speed or luminous brightness, resulting in uneven display of the display module in the first direction.
  • the length of the driving trace changes gradually, that is, the closer to the frame, the longer the length of the driving trace. Therefore, there is no region in FIG. 4 where the lengths of the driving traces are set in the same manner.
  • the display module of this embodiment further includes a circuit trace 101 .
  • the first pixel sub-circuit needs to connect a large number of signal lines (that is, a plurality of thin wires 102 extending along the second direction in the figure) to realize the required light emission control function, while the second pixel sub-circuit does not need Therefore, the second pixel sub-circuit does not need to be provided with corresponding signal lines.
  • this will result in a relatively high routing density in the area corresponding to the first pixel sub-circuit, and a relatively small routing density in the area corresponding to the second pixel sub-circuit, and metal routing usually has a certain reflective characteristic.
  • the routing density is different , will lead to different luminous characteristics of the display module in different areas, which will lead to the problem of screen mura.
  • mura refers to the phenomenon that the display module displays unevenly. Therefore, in this embodiment, by setting the circuit traces 101, the traces in the display module are relatively evenly arranged, which can improve the distribution uniformity of the trace density in the display module, thereby avoiding the density difference of the circuit traces 101. The problem of the screen Mura.
  • a display module with a better distribution of wiring density is also conducive to stabilizing the process, ensuring the electrical consistency of the circuit structure in the display module, and ensuring the uniformity of the display.
  • the length of the circuit trace 101 may be equal to the length of the signal line 102 in the first pixel sub-circuit, so as to further improve the consistency between the circuit trace 101 and the signal line 102 .
  • the circuit traces 101 can also be respectively connected to a plurality of second pixel sub-circuits, and the connection mode is corresponding to the connection mode between the first pixel sub-circuits and the signal lines.
  • the types of signal lines connected to the first pixel sub-circuit may be but not limited to data signal lines, gate lines and light emission control lines. Taking the signal line as the data signal line as an example, if the circuit trace 101 is parallel to the data signal line, the connection mode between the circuit trace 101 and the plurality of second pixel sub-circuits may correspond to the connection between the data signal line and the first pixel sub-circuit.
  • connection mode that is, the data signal line is connected to the data signal end of the first pixel sub-circuit, and then the circuit wiring 101 is connected to the data signal end of the second pixel sub-circuit, so as to further improve the flexibility of each wiring structure in the display module. consistency.
  • the cathodes of each light emitting device can be isolated from each other, the cathodes of each light emitting device are connected to the corresponding cathode signal lines, and the electrical signals of the cathodes are respectively obtained from the connected cathode signal lines, wherein the electrical signals of the cathodes can be driven by the display chip output.
  • the cathode of each light-emitting device can also adopt a common cathode design, that is, the cathodes of the light-emitting devices are connected to each other, and the brightness of each light-emitting device is controlled separately by adjusting the electrical signal of the anode, so as to achieve a simpler manufacturing process and control method. It should be noted that the above examples are only for illustration, and are not intended to limit the scope of protection of this embodiment, and the technical solutions of this embodiment can be applied to any of the above cathode structures.
  • the size of the conductive structure used to connect the cathode signal line and the cathode of the light-emitting device will also be relatively reduced, which will easily lead to poor electrical contact or increased contact resistance between the cathode signal line and the cathode of the light-emitting device, and then each emits light.
  • the cathode of the device is electrically non-uniform and may even cause a display mura.
  • the cathode of each light-emitting device can be equivalent to a resistor R1
  • the cathodes of multiple connected light-emitting devices can be equivalent to multiple resistors connected in series, that is, nR1.
  • the circuit traces are respectively connected to the cathodes of a plurality of the light-emitting devices, wherein the extending direction of the circuit traces may be parallel to the gate lines of the display module
  • One of the initialization signal line and the data signal line is not limited in this embodiment.
  • the equivalent resistance of the circuit traces is connected in parallel with the equivalent resistance of the cathodes of the light emitting devices.
  • the impedance of the overall structure after parallel connection is R1R2/(R1+R2), which is less than that of the cathode of a light-emitting device
  • the equivalent resistance R1 reduces the obstruction and loss of the cathode voltage signal during transmission, and improves the consistency of the cathode voltage of each light emitting device.
  • connection between the circuit trace and the cathode of the light emitting device may be a direct connection or an indirect connection.
  • the cathode of the light emitting device may be connected to the circuit trace via a conductive structure, which may be but not limited to a metallized hole, a conductive plug, a trace, and the like.
  • this embodiment does not limit the number of circuit wires.
  • the number of circuit traces may be one, and the cathodes of all light emitting devices in the light emitting device array 200 are connected to the same circuit trace.
  • the number of circuit traces can also be multiple, so when adopting the aforementioned mutually isolated cathode design, the cathodes of some light-emitting devices can be connected to the same circuit traces, and the cathodes of another part of the light-emitting devices can be connected to another same circuit traces . Moreover, when there are multiple circuit traces, multiple light emitting devices connected to the same circuit trace can be selected according to preset rules. As an example, continuing to refer to FIG. 2, FIG. 2 shows cathode nodes (circular structures in FIG. 2) of eight first pixel sub-circuits, and each circuit trace 101 can be respectively connected to the same number of first pixel sub-circuits.
  • a cathode of a pixel sub-circuit, and a plurality of first pixel sub-circuits connected to the same circuit trace 101 are arranged axially symmetrically, and the axis of symmetry is the connected circuit trace 101 . That is, as shown in FIG. 2 , each circuit trace 101 is used to connect the first pixel sub-circuits located in four columns, and two columns are located on the left side of the circuit trace 101, and the other two columns are located on the circuit trace 101 to the right of the . Further, the cathodes of the light emitting devices corresponding to the plurality of first pixel sub-circuits in the same column may be connected to the same circuit wiring 101 .
  • the width of other peripheral circuits exposed to the outside of the light emitting device array 200 in the first direction is reduced, that is, the frame width of the display module is narrowed.
  • the second pixel sub-circuit it is possible to avoid the difference in the response speed or luminance of the light-emitting device caused by the difference in the driving distance of different light-emitting devices, thereby improving the display uniformity of the display module.
  • a circuit wiring 101 connected to the second pixel sub-circuit is also provided to improve the consistency between the first pixel sub-circuit and the second pixel sub-circuit and suppress the screen mura problem, and the above-mentioned circuit wiring 101 It is connected to the cathode of the light-emitting device, and the resistance of the cathode is connected in parallel with the resistance of the circuit trace 101, which is equivalent to reducing the impedance of the overall structure of the cathode and the circuit trace 101.
  • the obstruction and loss of the cathode voltage signal in the transmission process are reduced, thereby improving the consistency of the cathode voltage of each light emitting device, avoiding the influence of the cathode voltage on the display brightness of each light emitting device, and further improving the display mode.
  • Group display uniformity
  • the pixel circuit array 100 includes a plurality of circuit traces 101 , and the plurality of circuit traces 101 are parallel to each other.
  • this embodiment does not limit the specific shape of the circuit traces 101, and the circuit traces 101 may be in a straight line structure, or may be in a zigzag structure or the like.
  • the consistency of the multiple circuit traces 101 can be improved. It can avoid the different reflective states of the circuit traces 101 with different shapes, thereby improving the mura problem of the display module. It can also avoid poor process consistency of circuit traces 101 with different shapes, thereby improving the manufacturing yield of the display module.
  • the display module is provided with a first sub-array area 110, and a plurality of first pixel circuits 111 and a plurality of second pixels are arranged in the first sub-array area 110.
  • a circuit 112 the first pixel circuit 111 includes a plurality of the first pixel sub-circuits
  • the second pixel circuit 112 includes a plurality of the second pixel sub-circuits, and any two in the first direction
  • One second pixel circuit 112 is provided between adjacent first pixel circuits 111 .
  • the projection of the circuit trace 101 on the virtual plane is located in the projection of the second pixel sub-circuit on the virtual plane, and the virtual plane is perpendicular to the thickness direction of the display module.
  • all the projections of the circuit traces 101 on the virtual plane are located in the projections of the second pixel circuit 112 on the virtual plane. That is, a plurality of said circuit traces 101 all extending along the second direction can be arranged correspondingly, so that the extending direction of the circuit traces 101 corresponds to the arrangement direction of the second pixel sub-circuits, thereby avoiding the pairing of the circuit traces 101
  • the first pixel sub-circuit causes shading, that is, avoids affecting the signal line path of the first pixel sub-circuit.
  • the circuit trace 101 can also realize the connection function with the cathode, so as to reduce the overall impedance and improve the connection between the cathodes. voltage uniformity.
  • a plurality of circuit traces 101 are arranged at equal intervals.
  • the equivalent resistance of each circuit trace 101 can be relatively close, and the equivalent resistance of the cathode connected in parallel to each circuit trace 101 can be relatively close, so that After the parallel connection, the impedances of all places on the display module are similar, thereby further improving the consistency of the cathode voltage of the display module.
  • the light emitting device array 200 is divided into a plurality of light emitting repeating units 210 , and each of the light emitting repeating units 210 includes a plurality of light emitting devices 201 respectively.
  • the light emitting repeating unit 210 includes a plurality of repeating subunits 2101.
  • the light emitting repeating unit 210 includes 4n red light emitting devices, 8n green light emitting devices and 4n blue light emitting devices, where n is an integer greater than or equal to 1.
  • two adjacent pixels can share the red light-emitting device or the blue light-emitting device, thereby improving the resolution of the display module, suppressing the color fringing problem of the display module, and further improving the display quality.
  • this embodiment does not specifically limit the arrangement of the red light-emitting devices, green light-emitting devices and blue light-emitting devices, as long as the above-mentioned technical solutions for improving the resolution of the display module can be realized, they all belong to this embodiment. protected range.
  • each of the repeating subunits 2101 includes one of the red light emitting devices, two of the green light emitting devices and one of the blue light emitting devices that are separated from each other, wherein the One of the green light-emitting devices and one of the red light-emitting devices in the repeating subunit 2101 respectively have the centers of the two first vertices of the virtual quadrilateral 2102, and the two first vertices are located on one side of the virtual quadrilateral 2102. on the diagonal.
  • the other green light-emitting device and one blue light-emitting device in the repeating subunit 2101 respectively have the centers of two second vertices located in the virtual quadrilateral 2102, and the two second vertices are located in the virtual quadrilateral 2102 on the other diagonal.
  • each light-emitting device 201 in this embodiment may be, but not limited to, organic light-emitting diodes (Organic light-emitting diodes, OLEDs), quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLEDs) and micron-scale light-emitting diodes (Micro LED), etc.
  • organic light-emitting diodes Organic light-emitting diodes, OLEDs
  • quantum dot light-emitting diodes Quantum Dot Light Emitting Diodes, QLEDs
  • Micro LED micron-scale light-emitting diodes
  • each light-emitting device 201 can be an organic light-emitting diode of different colors, such as red OLED, green OLED and blue OLED, etc., and the driving circuit of each light-emitting device 201 can be the same, but the materials of the light-emitting layers of the light-emitting devices 201 of different colors are different. , so as to realize the display of different colors, so that the display device can realize full-color display.
  • a larger number of light emitting devices 201 may be provided, for example, light emitting devices 201 including four different colors.
  • the display module includes three light emitting devices 201 of different colors, and the three colors may be red (R), green (G) and blue (B) respectively. It can be understood that the above numbers are only used for exemplary description, and are not used to limit the protection scope of this embodiment.
  • FIG. 5 is a schematic cross-sectional view of a display module according to an embodiment, and the cross-sectional direction of FIG. 5 is perpendicular to the display surface of the display module.
  • the display module includes a pixel definition layer 1106 , an anode layer 1107 , a luminescent material layer 1108 and a cathode layer 1109 .
  • the pixel definition layer 1106 is provided with a plurality of pixel openings isolated from each other.
  • the pixel definition layer 1106 can limit the deposition position of the luminescent material layer 1108, thereby improving the positional accuracy when forming a light emitting device, and can also prevent adjacent light emission when emitting light. Color crosstalk occurs between devices, thereby improving the display quality of the display module.
  • the anode layer 1107 is respectively disposed in the plurality of pixel openings, and a part of the anode layer 1107 is buried under the pixel definition layer 1106 .
  • the luminescent material layer 1108 is respectively disposed on the surface of the anode layer 1107 in the plurality of pixel openings.
  • the cathode layer 1109 covers the surfaces of the luminescent material layer 1108 and the pixel definition layer 1106 , and the cathode layer 1109 can be understood as continuously and completely covering the surfaces of the luminescent material layer 1108 and the pixel definition layer 1106 .
  • the anode layer 1107, the light emitting material layer 1108 and the cathode layer 1109 located in the same pixel opening constitute one light emitting device. That is, this embodiment provides a display module with a common cathode structure. Specifically, two light-emitting devices are shown in FIG. , the cathodes of the two light-emitting devices are connected.
  • the cathode preparation method of the display module with a common cathode structure is simple. After forming a complete cathode material film layer, the entire film layer can be used as the cathode of each light-emitting device without complicated patterning process, and it will not affect the performance of the display module. Display quality.
  • the display module further includes a pixel circuit layer 1100 and a planarization layer 1114.
  • the pixel circuit layer 1100 is used to set up the pixel circuit array, that is, the first pixels corresponding to different light emitting devices
  • the sub-circuits are located in the same pixel circuit layer 1100.
  • the two dashed boxes in FIG. In 1100 this embodiment only takes one of the first pixel sub-circuits as an example for illustration.
  • the pixel circuit layer 1100 is formed on the surface of the substrate 1110.
  • the substrate 1110 may include polyimide (PI) substrate layers 1110a and first buffer layers 1110b arranged alternately in sequence. In the embodiment shown in FIG.
  • PI polyimide
  • the substrate 1110 includes Two polyimide (PI) substrate layers 1110a and two first buffer layers 1110b are arranged alternately in sequence. It can be understood that the substrate 1110 may also include more polyimide (PI) substrate layers 1110 a and first buffer layers 1110 b.
  • PI polyimide
  • the pixel circuit layer 1100 essentially includes a plurality of sub-functional layers stacked, each sub-functional layer is respectively formed with structures of different shapes and different materials, and together constitutes the pixel circuit array 100 .
  • the pixel circuit layer 1100 specifically includes a first gate layer 1101a, a second gate layer 1101b, a first source 1102, a drain region 1103, a source contact structure 1104 and a drain contact structure 1105 , wherein the first source 1102 and the drain region 1103 are located in the same sub-functional layer, and the source contact structure 1104 and the drain contact structure 1105 are located in another same sub-functional layer.
  • the display module may also include a first gate insulating layer 1111 for isolating the first source 1102, the drain region 1103 and the first gate layer 1101a, and a first gate insulating layer 1111 for isolating the first gate layer 1101a from the second The second gate insulating layer 1112 of the gate layer 1101b, and the interlayer insulating layer 1113 for isolating the second gate layer 1101b, the source contact structure 1104 and the drain contact structure 1105.
  • the first source 1102 and the drain region 1103 are turned on or off under the control of the first gate 1101 .
  • the first gate layer 1101a is provided with signal traces such as initialization signal lines, gate drive signal lines, and light emission control signal lines, as well as a first gate 1101 and a plate of a storage capacitor (not shown).
  • the second gate layer 1101b is provided with signal traces such as initial signal wires, and is also provided with another plate of the storage capacitor (not shown in the figure).
  • the source-drain layer is used to set the data signal line 430, and is also provided with a source contact structure 1104 and a drain contact structure 1105.
  • the source contact structure 1104 is connected to the first source electrode 1102 located in the active layer, and the drain contact structure 1105 connected to the first source 1102 on the active layer.
  • the voltage on the first gate 1101 controls the conduction of the first source 1102 and the drain region 1103, the voltage signal on the drain contact structure 1105 can pass through the drain region 1103, the first source 1102, and drive away in sequence.
  • the wire is transmitted to the anode 1107 of the light emitting device 201 to drive the light emitting device 201 to emit light.
  • the planarization layer 1114 is arranged between the pixel circuit layer 1100 and the pixel definition layer 1106, and the planarization layer 1114 is provided with a plurality of driving wires L, since the positions of the plurality of light-emitting devices are different, and each light-emitting device The positions of the first pixel sub-circuits corresponding to the devices are also different, therefore, it is necessary to set the driving traces L with different lengths to achieve accurate connection.
  • the planarization layer 1114 can protect the driving wires L, and can also ensure the flatness of the display module structure.
  • One ends of the plurality of driving lines L are respectively connected to the anodes 1107 of the plurality of light-emitting devices in one-to-one correspondence, and the other ends of the plurality of driving lines L are respectively connected to the plurality of first pixel sub-circuits.
  • One-to-one connection so that the anodes 1107 of the plurality of light-emitting devices are electrically connected to the plurality of first pixel sub-circuits in a one-to-one correspondence.
  • the length difference of the driving wires L corresponding to the light-emitting devices of the same color is within the first preset range, and the length difference refers to the difference between the length of the longest driving wire L and the length of the shortest driving wire L. difference between.
  • the first preset range may be, for example, 0 um to 200 um. It can be understood that the first preset range may be jointly determined according to the type and resolution of the display device. For example, the types may include mobile phone, tablet computer and television, and the first preset range of the tablet computer may be larger than the first preset range of the mobile phone and smaller than the first preset range of the TV.
  • the driving wire L may be a transparent metal wire, for example, an indium tin oxide (Indium Tin Oxide, ITO) metal wire, an aluminum zinc oxide (Alumina zinc oxide, AZO) metal wire, or the like.
  • Fig. 6 is a schematic structural diagram of a first repeating unit and a corresponding light-emitting device in an embodiment.
  • one of the adjacent first pixel circuits 111 and one of the second pixel circuits 112 collectively serve as a first repeating unit 113.
  • this embodiment takes the first pixel circuit 111 on the left and the second pixel circuit 112 on the right as an example to divide to form the first repeating unit 113. In other embodiments, it can also be The first pixel circuit 111 on the right and the second pixel circuit 112 on the left are divided as an example. Referring to FIG. 3 and FIG.
  • the plurality of light-emitting repeating units 210 are in one-to-one correspondence with the plurality of first pixel circuits 111 .
  • the difference between the size of the light-emitting repeating unit 210 in the first direction and the size of the first repeating unit 113 in the first direction is within the second preset range, that is, it can be understood that the light-emitting repeating unit 210
  • the size in the first direction is similar to the size of the first repeating unit 113 in the first direction.
  • the second preset range may be, for example, 0 um to 5 um.
  • the correspondence between the positions of the light-emitting repeating unit 210 and the first repeating unit 113 can be realized, thereby setting a shorter driving line, To improve the stability and reliability of the driving current.
  • the size of the first pixel sub-circuit may be the same as that of the second pixel sub-circuit, and the film layer structure of the second pixel sub-circuit may be the same as that of the first pixel sub-circuit, so as to reduce
  • the design difficulty of the pixel circuit array 100 can also reduce the differential influence of various optical effects on the dimensional structure during the exposure preparation process, thereby improving the manufacturing yield of the pixel circuit array 100 and improving the off-screen caused by uneven reflection of the traces. mura.
  • FIG. 7 is a circuit diagram of a first pixel sub-circuit in an embodiment.
  • the first pixel sub-circuit includes a drive transistor T1, an anode initialization unit 1511, a gate initialization unit 1512, and a data writing unit 1513 , a threshold compensation unit 1514 and a light emission control unit 1515 .
  • the driving transistor T1 is used to generate a driving current.
  • the gate of the driving transistor T1 is connected to the gate initialization unit 1512, the first pole of the driving transistor T1 is used to receive the signal of the data signal terminal Data, and the second pole of the driving transistor T1 can output the driving current correspondingly.
  • the current value of the driving current is determined by the signal of the data signal terminal Data, and directly affects the light-emitting brightness of the light-emitting device.
  • the control terminal of the anode initialization unit 1511 is used to receive the signal of the second gate signal terminal Scan(n), the input terminal of the anode initialization unit 1511 is used to receive the initialization signal, and the output terminal of the anode initialization unit 1511 is connected to the anode of the light emitting device.
  • the anode initialization unit 1511 is used to receive an initialization signal through the input terminal after the gate of the driving transistor T1 is initialized, and pull down the anode of the light emitting device connected thereto to the initialization signal, so as to initialize the anode of the light emitting device.
  • the initialization signal can be understood as an initial charging voltage of the anode of the light emitting device.
  • the anode initialization unit 1511 may include a seventh transistor T7, the first pole of the seventh transistor T7 is used to receive the signal of the initialization signal terminal Vinit, the output terminal of the anode initialization unit 1511 is connected to the anode of the light emitting device, and the seventh transistor T7 The gate of is used to receive the signal of the second gate signal terminal Scan(n).
  • the control terminal of the gate initialization unit 1512 is connected to the gate control terminal for receiving the signal of the first gate signal terminal Scan(n-1); the input terminal of the gate initialization unit 1512 is connected to the initialization signal terminal Vinit for Receive the initialization signal; the output terminal of the gate initialization unit 1512 is connected to the gate of the driving transistor T1.
  • the gate initialization unit 1512 can pull down the gate voltage of the driving transistor T1 to the initialization signal according to the signal of the first gate signal terminal Scan(n-1) received by the control terminal, so as to control the gate of the driving transistor T1 to initialize.
  • the data writing unit 1513 includes a second transistor T2, the gate of the second transistor T2 is connected to the second gate signal terminal Scan(n), the first pole of the second transistor T2 is connected to the data signal terminal Data, and the second transistor T2 The second pole of the drive transistor T1 is connected to the first pole, and the second transistor T2 is used to control the connection between the second gate signal line and the first pole of the drive transistor T1 according to the signal of the second gate signal terminal Scan(n). The on-off of the signal transmission path.
  • the second transistor T2 when the signal at the second gate signal terminal Scan(n) is at a low level, the second transistor T2 is turned on and transmits the signal at the data signal terminal Data to The first pole of the driving transistor T1; when the signal of the second gate signal terminal Scan(n) is at low level, the second transistor T2 is turned off.
  • the data writing unit 1513 is not limited to the second transistor T2 in this embodiment, and may also be other circuit structures capable of realizing the signal transmission function according to the enable control signal.
  • the threshold compensation unit 1514 is respectively connected to the gate and the second pole of the driving transistor T1, and is used to control the signal transmission path between the gate and the second pole of the driving transistor T1 according to the signal of the second gate signal terminal Scan(n) on and off. Specifically, by setting the threshold compensation unit 1514, the threshold voltage of the driving transistor T1 can be compensated, so as to prevent the threshold voltage of the driving transistor T1 from affecting the brightness of the light emitting device.
  • the threshold compensation unit 1514 includes a third transistor T3 and a storage capacitor C1.
  • the storage capacitor C1 is connected to the second power supply voltage terminal VDD and the gate of the driving transistor T1 respectively.
  • the gate of the third transistor T3 is connected to the first gate signal line, the first pole of the third transistor T3 is connected to the second pole of the driving transistor T1, and the second pole of the third transistor T3 is connected to the gate of the driving transistor T1 .
  • the third transistor T3 is used for controlling the on-off of the signal transmission path between the gate of the driving transistor T1 and the second electrode according to the signal of the second gate signal terminal Scan(n).
  • the third transistor T3 as a P-type transistor as an example, when the signal of the second gate signal terminal Scan(n) is at a low level, threshold compensation is performed and the storage capacitor C1 is charged, so that the compensation result is stored in storage capacitor C1.
  • the third transistor T3 may be a double-gate transistor.
  • the third transistor T3 with a double-gate transistor structure can effectively improve the reliability of threshold compensation, thereby improving the display quality of the display device. It can be understood that other transistors in the first pixel sub-circuit may also be double-gate transistors to further improve display quality.
  • the light emission control unit 1515 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is used to receive the light-emitting control signal
  • the first pole of the fifth transistor T5 is connected to the second power supply voltage terminal
  • the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T1
  • the fifth transistor T5 is used for controlling the on-off of the signal transmission path between the second power supply voltage terminal and the first pole of the driving transistor T1 according to the light emission control signal EM.
  • the gate of the sixth transistor T6 is used to receive the light emission control signal EM, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T1, the second pole of the sixth transistor T6 is connected to the anode of the light emitting device, and the sixth transistor T6 T6 is used for controlling the on-off of the signal transmission path between the second pole of the driving transistor T1 and the anode of the light-emitting device according to the light-emitting control signal EM.
  • the fifth transistor T5 and the sixth transistor T6 are both P-type transistors as an example for illustration.
  • the fifth transistor T5 and the sixth transistor T6 are turned on to drive the transistor T1
  • the voltage of the first pole of the first driving transistor T1 is pulled up to the second power supply voltage VDD, and the gate-source voltage difference of the first driving transistor T1 changes to generate a driving current and output the driving current to the light-emitting device, thereby controlling the light-emitting device to emit light.
  • various transistors in this embodiment are not limited to the P-type transistors in the foregoing embodiments, and may also be N-type transistors and the like. For different types of transistors, their corresponding driving methods can also be adaptively adjusted.
  • the first pixel sub-circuit of this embodiment is not limited to the 7T1C first pixel sub-circuit in the foregoing embodiments, that is, the first pixel sub-circuit may also have other numbers of transistors, so that A light-weight display device, or a more flexible display function with a larger number of transistors, for example, can also be other types of driving circuits such as 3T1C, 6T1C, and 6T2C.
  • the first pixel subcircuit in the embodiment of FIG. 7 can be implemented based on the structure shown in the embodiment in FIG. 5, and the type of the first pixel subcircuit can be a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) type, that is, All transistors in the first pixel sub-circuit are low temperature polysilicon thin film transistors.
  • some transistors in the first pixel sub-circuit may be oxide thin film transistors, and accordingly, the type of the first pixel sub-circuit is a low temperature poly-silicon oxide (Low Temperature Poly-silicon Oxide, LTPO) type.
  • the oxide thin film transistor has a better performance of suppressing electric leakage, so it is suitable as a switching transistor to achieve more reliable switching performance.
  • FIG. 8 is one of the partial structural schematic diagrams of a display module according to an embodiment.
  • FIG. 9 is a schematic cross-sectional view of the display module according to the embodiment shown in FIG. 8 .
  • the display module further includes gate lines 410 and a plurality of first metallized holes 1121 .
  • the metallized hole refers to a hole-like structure in which a conductive material is plated on the inner wall of the hole, and the conductive material of the plated film may be but not limited to copper. It should be noted that the thickness of the gate line 410 and the circuit trace 101 in FIG. 8 are different, but the difference in thickness in FIG.
  • the gate lines 410 and the circuit traces 101 are defined, that is, the dimensions of the gate lines 410 and the circuit traces 101 may be the same.
  • the position of the first metallization hole 1121 is staggered from the initialization signal line in the second gate layer 1101b, so it can be directly connected to the gate line in the first gate layer 1101a.
  • the gate lines 410 extend along the row direction of the display module.
  • the gate lines 410 are used to transmit gate signals, and the gate lines 410 are respectively connected to the gate signal terminals of a plurality of the first pixel sub-circuits, and the gate signal terminals include Scan(n) and Scan(n) in FIG. 7 . -1). Referring to FIG.
  • the pixel sub-circuit on the left side connected to the anode 1107 is the first pixel sub-circuit
  • the pixel sub-circuit on the right side not connected to the light-emitting device is the second pixel sub-circuit
  • the circuit in the second pixel sub-circuit The line 101 and the gate line are disposed in the same sub-functional layer, ie, the first gate layer 1101a.
  • Each of the first metallization holes 1121 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the first metallization hole 1121 is connected to the cathode layer 1109 The other end of the first metallized hole 1121 is connected to the circuit trace 101 .
  • the connection reliability between the circuit trace 101 and the cathode of the light-emitting device can be ensured, the problem of poor conduction of a single first metallized hole 1121 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved.
  • the circuit traces 101 and the gate lines 410 on the same sub-functional layer, the circuit traces 101 do not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
  • a plurality of first metallized holes 1121 may be arranged at equal intervals along the extending direction of the circuit trace 101, so as to improve the uniform impedance distribution of the overall structure composed of the circuit trace 101, the first metallized hole 1121 and the cathode. To improve the uniformity of the voltage distribution on the cathode, thereby improving the display uniformity of the display module.
  • the second pixel sub-circuit is also configured with a gate signal terminal.
  • the circuit trace 101 may be arranged parallel to the gate line 410 . That is, the extending direction of the circuit traces 101 is parallel to the row direction of the display module, and the first direction in this embodiment can be understood as the row direction of the display module.
  • the circuit trace 101 is connected to the gate signal terminals Scan(n) and Scan(n ⁇ 1) of the second pixel sub-circuit.
  • the structure and connection relationship of the circuit traces 101 are the same as those of the gate lines 410 , therefore, the circuit traces 101 can be prepared directly using the mask of the gate lines 410 , thereby reducing design difficulty and manufacturing cost of the mask.
  • one circuit trace 101 is arranged between two adjacent gate lines 410 in the second direction, and between the circuit trace 101 and one adjacent gate line 410 The distance is equal to the distance between the circuit trace 101 and another adjacent gate line 410 . Based on the above arrangement, the gate lines 410 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura problem of the screen.
  • FIG. 10 is the second schematic diagram of the partial structure of the display module of an embodiment
  • FIG. 11 is a schematic cross-sectional view of the display module of the embodiment of FIG. 10
  • the display module further includes an initialization signal line 420 and a plurality of second metallized holes 1122 .
  • the thickness of the initialization signal line 420 and the circuit trace 101 in FIG. 10 are different, but the difference in thickness in FIG.
  • the specific dimensions of the initialization signal lines 420 and the circuit traces 101 are limited, that is, the dimensions of the initialization signal lines 420 and the circuit traces 101 may be the same.
  • the initialization signal line 420 extends along the row direction of the display module.
  • the initialization signal line 420 is used to transmit an initialization signal, and the initialization signal can be used to initialize the gate of the driving transistor or to initialize the anode of the light emitting device, and the initialization signal line 420 is respectively connected to the plurality of first pixel sub-circuits. Initialize the connection of the signal terminal, the initialization signal terminal includes Vinit in Figure 7. Referring to FIG.
  • the pixel subcircuit on the left side connected to the anode 1107 is the first pixel subcircuit
  • the pixel subcircuit on the right side not connected to the light emitting device is the second pixel subcircuit
  • the circuit in the second pixel subcircuit The line 101 and the initialization signal line are provided in the same sub-functional layer, ie, the second gate layer 1101b.
  • Each second metallization hole 1122 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the second metallization hole 1122 is connected to the cathode layer 1109 The other end of the second metallized hole 1122 is connected to the circuit trace 101 .
  • the connection reliability between the circuit trace 101 and the cathode of the light emitting device can be ensured, the problem of poor conduction of a single second metallization hole 1122 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved.
  • the circuit wiring 101 and the initial signal line on the same sub-functional layer, the circuit wiring 101 does not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
  • the circuit routing 101 is arranged in parallel with the initialization signal line 420, one circuit routing 101 is arranged between two initialization signal lines 420 adjacent in the second direction, and the circuit The distance between the trace 101 and the adjacent one of the initialization signal lines 420 is equal to the distance between the circuit trace 101 and the other adjacent initialization signal line 420 . Based on the above arrangement, the initialization signal lines 420 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura of the screen.
  • a plurality of second metallization holes 1122 can be arranged at equal intervals in the extending direction of the circuit trace 101, so as to improve the impedance distribution of the overall structure composed of the circuit trace 101, the second metallization hole 1122 and the cathode. Uniformity, thereby improving the uniformity of voltage distribution on the cathode, thereby improving the display uniformity of the display module.
  • the circuit trace 101 connected to the first metallized hole 1121 is called a first trace
  • the circuit trace 101 connected to the second metallized hole 1122 is called a second trace.
  • the display module may include multiple first wires and multiple second wires to further reduce the impedance on the cathode, improve the uniformity of the voltage distribution on the cathode, and further improve the display module. display uniformity.
  • Figure 12 is the third schematic diagram of the partial structure of the display module of an embodiment
  • Figure 13 is a schematic cross-sectional view of the display module of the embodiment of Figure 12
  • the display module also includes data signal lines 430 and a plurality of third metal Blowhole 1123.
  • the thickness of the data signal line 430 and the circuit trace 101 in FIG. 12 are different, but the difference in thickness in FIG.
  • the specific dimensions of the data signal line 430 and the circuit trace 101 are limited, that is, the dimensions of the data signal line 430 and the circuit trace 101 may be the same.
  • the data signal lines 430 extend along the column direction of the display module.
  • the data signal line 430 is used to transmit the data signal, and the data signal is used to control the brightness of the light-emitting device.
  • the data signal line 430 is respectively connected to the data signal terminals of a plurality of the first pixel sub-circuits, and the data signal terminal includes the Data in FIG. 7 .
  • the pixel subcircuit on the left side connected to the anode 1107 is the first pixel subcircuit
  • the pixel subcircuit on the right side not connected to the light-emitting device is the second pixel subcircuit
  • the circuit trace 101 in the second pixel subcircuit The same sub-functional layer as the data signal line, that is, the source-drain layer.
  • Each of the third metallization holes 1123 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the third metallization hole 1123 is connected to the cathode layer 1109 The other end of the third metallized hole 1123 is connected to the circuit trace 101 in the pixel circuit layer.
  • the connection reliability between the circuit trace 101 and the cathode of the light emitting device can be ensured, the problem of poor conduction of a single third metallized hole 1123 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved.
  • circuit traces 101 and the data signal lines 430 do not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
  • a plurality of third metallization holes 1123 may be arranged at equal intervals along the extending direction of the circuit traces 101, so as to improve the uniform impedance distribution of the overall structure composed of the circuit traces 101, the third metallization holes 1123 and the cathode. To improve the uniformity of the voltage distribution on the cathode, thereby improving the display uniformity of the display module.
  • the second pixel sub-circuit is also configured with a data signal terminal, and the circuit trace 101 may be arranged in parallel with the data signal line 430 . That is, the extending direction of the circuit traces 101 is parallel to the column direction of the display module, and the first direction in this embodiment can be understood as the column direction of the display module. Moreover, the circuit wiring 101 is connected to the data signal terminal Data of the second pixel sub-circuit. That is, the structure and connection relationship of the circuit traces 101 are the same as those of the data signal lines 430 , therefore, the circuit traces 101 can be prepared directly using the photomask of the data signal lines 430 , thereby reducing design difficulty and manufacturing cost of the photomask.
  • one circuit trace 101 is arranged between two adjacent data signal lines 430 in the first direction, and between the circuit trace 101 and one adjacent data signal line 430 The distance is equal to the distance between the circuit trace 101 and another adjacent data signal line 430 . Based on the above arrangement, the data signal lines 430 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura problem of the screen.
  • the display module includes not only a plurality of first wires, but also a plurality of third wires.
  • the multiple first traces extend along the row direction of the display module
  • the multiple third traces extend along the column direction of the display module
  • both the multiple first traces and the multiple third traces are connected to the light emitting
  • the common cathode of the device is connected to form a parallel mesh trace.
  • the square resistance of the cathode is 12 ⁇ /sq-20 ⁇ /sq; if Ti/Al/Ti or Mo
  • the first wire and the third wire are made of metal, and the first wire and the third wire are respectively connected to the cathode, then the overall square resistance of the above structure after parallel connection is 0.2 ⁇ /sq-0.6 ⁇ /sq, thus greatly
  • the voltage uniformity on the cathode is improved, thereby improving the display uniformity of the display module, especially the display uniformity under low grayscale.
  • the impedance on the cathode can be greatly reduced, the uniformity of the voltage distribution on the cathode can be improved, and the display uniformity of the display module can be further improved.
  • FIG. 14 is one of the simplified cross-sectional diagrams of a display module according to an embodiment.
  • the display module further includes a gate driving circuit 300 .
  • the first direction is the row direction of the display module
  • the third direction is the thickness direction of the display module.
  • the gate drive circuit 300 is arranged adjacent to the pixel circuit array 100 in the first direction, and the projection of the gate drive circuit 300 on the virtual plane 600 along the third direction is along the line of the light emitting device array 200 The projections of the third direction on the virtual plane 600 partially overlap, the third direction is the thickness direction of the display module, and the virtual plane 600 is a plane perpendicular to the third direction.
  • the plane 600 is not a feature that actually exists in the display module, but a reference plane introduced for the convenience of explaining the features of the display module.
  • a display module with a narrower border can be provided.
  • FIG. 15 is a second simplified cross-sectional schematic diagram of a display module according to an embodiment.
  • the display module further includes a fan-out wiring group 500 .
  • the first direction is the column direction of the display module
  • the third direction is the thickness direction of the display module.
  • the fan-out routing group 500 is arranged adjacent to the pixel circuit array 100 in the second direction, and the projection of the fan-out routing group 500 on the virtual plane 600 along the third direction is the same as that of the light emitting device array 200 along the third direction.
  • the projections of the directions on a virtual plane 600 which is a plane perpendicular to the third direction, partially coincide.
  • the display driving unit located in the non-display area is connected to the pixel circuit array 100 through the fan-out wire group 500 to transmit control signals to the pixel circuit array 100 .
  • the display driving unit may be a display driver chip (Display Driver IC, DDIC).
  • DDIC Display Driver IC
  • FIG. 16 is the second structural schematic diagram of a pixel circuit array in an embodiment. Referring to FIG. Adjacent to the first sub-array area 110 in the first direction, a plurality of the first pixel circuits 111 are disposed in the second sub-array area 120 .
  • FIG. 17 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 16. Referring to FIG. In the second sub-array region 120 , a larger number of light emitting devices can be arranged correspondingly, thereby increasing the overlapping area between the light emitting device array 200 and other peripheral circuits (such as the gate driving circuit 300 ).
  • the overlapping area refers to the overlapping area in the third direction, that is, the projection of the light emitting device array 200 on the virtual plane 600 perpendicular to the third direction and the projection of other peripheral circuits on the virtual plane 600 perpendicular to the third direction the overlapping area between.
  • the first sub-array region 110 structure is adopted in the middle area, and
  • the structure of the second sub-array area 120 can not only achieve the purpose of narrowing the display frame to a large extent, but also reduce the impact on user experience. For example, when one layer is used to drive the wiring, a space of 200um to 400um can be obtained at the left and right borders to provide a display module with a narrower border.
  • the second sub-array area 120 in the embodiment of FIG. 16 only shows 8 columns of first pixel sub-circuits, the second sub-array area 120 can actually have more columns of first pixels as required. sub-circuits to further optimize narrow bezel performance.
  • one side edge of the second sub-array region 120 is aligned with the first side edge of the first sub-array region 110 in a second direction, and the second direction perpendicular to the first direction and perpendicular to the thickness direction of the display module.
  • the method of defining the side edges of the first sub-array region 110 in this embodiment is the same as that of the side edges of the first pixel circuit 111 in the foregoing embodiments, and details are not repeated here.
  • the design difficulty of the first pixel sub-circuit can be reduced without affecting the display function.
  • FIG. 18 is the third schematic diagram of the structure of the pixel circuit array of an embodiment.
  • the third sub-array area 130 can be understood as being relatively close to the center of the display module, while the first sub-array area 110 is relatively close to the display module border.
  • a plurality of repeating units and a plurality of third pixel circuits 131 are provided in the third sub-array area 130, and the repeating units include one first pixel circuit 111 and one second pixel circuit 111 adjacent in the first direction.
  • Two pixel circuits 112, and one third pixel circuit 131 is provided between any two adjacent repeating units in the second direction, and the third pixel circuit 131 includes A plurality of the second pixel sub-circuits arranged.
  • a plurality of first wiring lines, a plurality of second wiring lines and a plurality of second wiring lines can be simultaneously set in the display module.
  • a plurality of third wires extend along the column direction of the display module, and the projection of the second wires on the virtual plane is located in the projection of the second pixel circuit on the virtual plane, so that the multiple first wires and the multiple The third routing forms a mesh structure.
  • the specific setting manners of the first routing, the second routing and the third routing can refer to the above-mentioned embodiments, which will not be repeated here.
  • FIG. 19 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 18.
  • the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module.
  • the third sub-array area 130 includes a plurality of first repeating units 113 and a plurality of third pixel circuits 131 .
  • the third pixel circuit 131 includes a plurality of third pixel sub-circuits, the structure of the third pixel sub-circuit may be the same as that of the first pixel sub-circuit, and the third pixel sub-circuit is not the same as the first pixel sub-circuit.
  • the light emitting device is electrically connected.
  • the third pixel sub-circuit identical to the first pixel sub-circuit, it is possible to ensure that the structure and size of each pixel sub-circuit inside the pixel circuit array 100 are consistent, and to avoid the mura problem caused by the inconsistent density of circuit traces 101 .
  • the consistent size and structure of the pixel sub-circuits is also conducive to the stability of the manufacturing process, ensuring the consistency of the electrical properties of the thin film transistors and the uniformity of the display.
  • one side edge of the third sub-array region 130 is aligned with the second side edge of the first sub-array region 110 in the first direction, and the second side edge is connected to the first side edge, and the plurality of third pixel sub-circuits in the third pixel circuit 131 are arranged along the first direction.
  • the difference between the sum of the sizes of the first repeating unit 113 and the third pixel circuit 131 in the second direction and the size of the light emitting repeating unit 210 in the second direction is within a fourth preset range .
  • the fourth preset range may be, for example, 0um to 10um.
  • FIG. 20 is the fourth schematic diagram of the structure of the pixel circuit array in an embodiment.
  • the sub-array area 130 and the fourth sub-array area 140 are adjacent to the third sub-array area 130 in the first direction, and is adjacent to the second sub-array area 120 in the second direction.
  • a plurality of the first pixel circuits 111 and a plurality of fourth pixel circuits 141 are arranged in the fourth sub-array area 140, and any two adjacent first pixel circuits 111 in the second direction There is a fourth pixel circuit 141 between them, and the fourth pixel circuit 141 includes a plurality of second pixel sub-circuits arranged along the first direction, and the fourth pixel circuit 141 in the fourth pixel circuit 141 The number of the second pixel sub-circuits is less than the number of the second pixel sub-circuits in the third pixel circuit 131 .
  • FIG. 21 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 20. Referring to FIG. A larger number of light emitting devices increases the overlapping area of the light emitting device array 200 and other peripheral circuits (such as the gate driving circuit 300 ) in the third direction.
  • the present application also provides a display device, including: the above-mentioned display module.
  • the frame of the display device can be narrowed, and the display uniformity of the display device can be optimized, thereby improving the comprehensive display performance of the display device.

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Abstract

A display module, comprising: a pixel circuit array (100) comprising a plurality of first pixel sub-circuits, a plurality of second pixel sub-circuits, and circuit wires (101), the second pixel sub-circuits being each located between two adjacent first pixel sub-circuits in a first direction, and the first direction being perpendicular to the thickness direction of the display module; and a light-emitting device array (200), the size of the light-emitting device array in the first direction being greater than the size of the pixel circuit array (100) in the first direction, the light-emitting device array (200) comprising a plurality of light-emitting devices (201), the light-emitting devices (201) comprising cathodes and anodes, and the anodes of the plurality of light-emitting devices (201) being respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence, wherein the circuit wires (101) are connected to the cathodes of the plurality of light-emitting devices (201).

Description

显示模组和显示设备Display modules and display devices
相关申请的交叉引用Cross References to Related Applications
本申请要求于2021年10月27日提交中国专利局、申请号为2021112576676、发明名称为“显示模组和显示设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with the application number 2021112576676 and the title of the invention "display module and display device" submitted to the China Patent Office on October 27, 2021, the entire contents of which are incorporated by reference in this application.
技术领域technical field
本申请涉及显示技术领域，特别是涉及一种显示模组和显示设备。The present application relates to the field of display technology, in particular to a display module and a display device.
背景技术Background technique
随着科技的不断发展，人们对显示设备的显示尺寸的要求越来越高，全面屏已经在市场普及，缩小显示屏的边框，提高屏占比显得尤为重要。但是，由于显示尺寸的不断增大，显示设备的显示均匀性也遇到了极大的挑战，现有技术已无法满足人们对大尺寸显示设备的均匀性需求。With the continuous development of technology, people have higher and higher requirements for the display size of display devices. Full screens have been popularized in the market. It is particularly important to reduce the frame of the display screen and increase the screen ratio. However, due to the continuous increase of the display size, the display uniformity of the display device has also encountered great challenges, and the existing technology has been unable to meet people's demand for uniformity of large-size display devices.
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。The statements herein merely provide background information related to the present application and do not necessarily constitute exemplary techniques.
发明内容Contents of the invention
根据本申请的各种实施例，提供一种显示模组和显示设备。According to various embodiments of the present application, a display module and a display device are provided.
一种显示模组，包括：A display module, comprising:
像素电路阵列，包括多个第一像素子电路、多个第二像素子电路和电路走线，各所述第二像素子电路分别位于在第一方向上相邻的两个所述第一像素子电路之间，所述第一方向垂直于所述显示模组的厚度方向；A pixel circuit array, including a plurality of first pixel sub-circuits, a plurality of second pixel sub-circuits and circuit wiring, each of the second pixel sub-circuits is respectively located in two adjacent first pixels in the first direction Between the sub-circuits, the first direction is perpendicular to the thickness direction of the display module;
发光器件阵列，所述发光器件阵列在第一方向上的尺寸大于所述像素电路阵列在第一方向上的尺寸，所述发光器件阵列包括多个发光器件，所述发光器件包括阴极和阳极，多个所述发光器件的阳极分别与多个所述第一像素子电路一一对应地连接；A light emitting device array, the size of the light emitting device array in the first direction is larger than the size of the pixel circuit array in the first direction, the light emitting device array includes a plurality of light emitting devices, the light emitting device includes a cathode and an anode, The anodes of the plurality of light-emitting devices are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence;
其中，所述电路走线与多个所述发光器件的阴极连接。Wherein, the circuit wiring is connected to the cathodes of a plurality of the light emitting devices.
一种显示设备，包括：如上述的显示模组。A display device, comprising: the above-mentioned display module.
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will be apparent from the description, drawings and claims.
附图说明Description of drawings
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。In order to more clearly illustrate the technical solutions in the embodiments or exemplary technologies of the present application, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or exemplary technologies. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain the drawings of other embodiments according to these drawings without creative work.
图1为一实施例的显示模组的结构示意图之一；FIG. 1 is one of the structural schematic diagrams of a display module of an embodiment;
图2为一实施例的像素电路阵列的结构示意图之一；FIG. 2 is one of the structural schematic diagrams of a pixel circuit array according to an embodiment;
图3为一实施例的发光器件阵列的结构示意图；Fig. 3 is a schematic structural diagram of a light emitting device array according to an embodiment;
图4为未设置第二像素子电路的显示模组的结构示意图；4 is a schematic structural diagram of a display module without a second pixel sub-circuit;
图5为一实施例的显示模组的剖视示意图；5 is a schematic cross-sectional view of a display module according to an embodiment;
图6为一实施例的第一重复单元和对应的发光器件的结构示意图；Fig. 6 is a schematic structural view of a first repeating unit and a corresponding light-emitting device in an embodiment;
图7为一实施例的第一像素子电路的电路图；FIG. 7 is a circuit diagram of a first pixel sub-circuit according to an embodiment;
图8为一实施例的显示模组的局部结构示意图之一；FIG. 8 is one of partial structural schematic diagrams of a display module of an embodiment;
图9为图8实施例的显示模组的剖视示意图；FIG. 9 is a schematic cross-sectional view of the display module of the embodiment in FIG. 8;
图10为一实施例的显示模组的局部结构示意图之二；FIG. 10 is a second schematic diagram of a partial structure of a display module of an embodiment;
图11为图10实施例的显示模组的剖视示意图；FIG. 11 is a schematic cross-sectional view of the display module of the embodiment in FIG. 10;
图12为一实施例的显示模组的局部结构示意图之三；FIG. 12 is a third schematic diagram of a partial structure of a display module of an embodiment;
图13为图12实施例的显示模组的剖视示意图；FIG. 13 is a schematic cross-sectional view of the display module of the embodiment in FIG. 12;
图14为一实施例的显示模组的简化剖视示意图之一；FIG. 14 is one of the simplified cross-sectional schematic diagrams of a display module according to an embodiment;
图15为一实施例的显示模组的简化剖视示意图之二；FIG. 15 is a second simplified cross-sectional schematic diagram of a display module of an embodiment;
图16为一实施例的像素电路阵列的结构示意图之二；FIG. 16 is the second structural schematic diagram of a pixel circuit array in an embodiment;
图17为基于图16实施例的像素电路阵列形成的显示模组的结构示意图；FIG. 17 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 16;
图18为一实施例的像素电路阵列的结构示意图之三；FIG. 18 is a third schematic structural diagram of a pixel circuit array in an embodiment;
图19为基于图18实施例的像素电路阵列形成的显示模组的结构示意图；FIG. 19 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 18;
图20为一实施例的像素电路阵列的结构示意图之四；FIG. 20 is a fourth schematic structural diagram of a pixel circuit array in an embodiment;
图21为基于图20实施例的像素电路阵列形成的显示模组的结构示意图。FIG. 21 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 20 .
元件标号说明：Component label description:
像素电路阵列：100；电路走线：101；第一子阵列区：110；第一像素电路：111；第一栅极层：1101a； 第二栅极层：1101b；第一源极：1102；第一漏极：1103；源极接触结构：1104；漏极接触结构：1105；像素定义层：1106；阳极层：1107；发光材料层：1108；阴极层：1109；基板：1110；聚酰亚胺(PI)衬底层：1110a；第一缓冲层：1110b；第一栅绝缘层：1111；第二栅绝缘层：1112；层间绝缘层：1113；平坦化层：1114；第二像素电路：112；第一金属化孔：1121；第二金属化孔：1122；第三金属化孔：1123；第一重复单元：113；第二子阵列区：120；第三子阵列区：130；第三像素电路：131；第四子阵列区：140；第四像素电路：141；阳极初始化单元：1511；栅极初始化单元：1512；数据写入单元：1513；阈值补偿单元：1514；发光控制单元：1515；发光器件阵列：200；发光重复单元：210；重复子单元：2101；虚拟四边形：2102；发光器件：201；栅极驱动电路：300；栅极线：410；初始化信号线：420；数据信号线：430；扇出走线组：500；虚拟平面：600。Pixel circuit array: 100; circuit routing: 101; first sub-array area: 110; first pixel circuit: 111; first gate layer: 1101a; second gate layer: 1101b; first source: 1102; First drain: 1103; source contact structure: 1104; drain contact structure: 1105; pixel definition layer: 1106; anode layer: 1107; luminescent material layer: 1108; cathode layer: 1109; substrate: 1110; polyimide Amine (PI) substrate layer: 1110a; first buffer layer: 1110b; first gate insulating layer: 1111; second gate insulating layer: 1112; interlayer insulating layer: 1113; planarization layer: 1114; second pixel circuit: 112; the first metallization hole: 1121; the second metallization hole: 1122; the third metallization hole: 1123; the first repeating unit: 113; the second sub-array area: 120; the third sub-array area: 130; Three-pixel circuit: 131; fourth sub-array area: 140; fourth pixel circuit: 141; anode initialization unit: 1511; gate initialization unit: 1512; data writing unit: 1513; threshold compensation unit: 1514; light emission control unit : 1515; light-emitting device array: 200; light-emitting repeating unit: 210; repeating subunit: 2101; virtual quadrilateral: 2102; light-emitting device: 201; gate driving circuit: 300; Data signal lines: 430; fan-out routing groups: 500; virtual planes: 600.
具体实施方式Detailed ways
为了便于理解本申请实施例，下面将参照相关附图对本申请实施例进行更全面的描述。附图中给出了本申请实施例的首选实施例。但是，本申请实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请实施例的公开内容更加透彻全面。In order to facilitate understanding of the embodiments of the present application, the following will describe the embodiments of the present application more comprehensively with reference to related drawings. A preferred embodiment of the embodiments of the application is given in the accompanying drawings. However, the embodiments of the present application can be implemented in many different forms, and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the embodiments of this application. The terms used herein in the description of the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
在本申请实施例的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请实施例的限制。In the description of the embodiments of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner" and "outer" are based on the drawings The method or positional relationship shown is only for the convenience of describing the embodiment of the present application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as Limitations on the embodiments of this application.
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请的范围的情况下，可以将第一方向称为第二方向，且类似地，可将第二方向称为第一方向。第一方向和第二方向两者都是方向，但其不是同一方向。It can be understood that the terms "first", "second" and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first direction could be termed a second direction, and, similarly, a second direction could be termed a first direction, without departing from the scope of the present application. Both the first direction and the second direction are directions, but they are not the same direction.
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。在本申请的描述中，“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定。In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present application, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.
图1为一实施例的显示模组的结构示意图之一，本实施例的显示模组包括像素电路阵列和发光器件阵列。本申请实施例的显示模组应用于窄边框的显示设备。显示设备可以为智能手机、平板电脑、游戏设备、增强现实(Augmented Reality，AR)设备、笔记本、桌面计算设备、可穿戴设备等。为了方便理解，下面以显示设备为手机进行举例说明。图2为一实施例的像素电路阵列的结构示意图之一，图3为一实施例的发光器件阵列的结构示意图，像素电路阵列100和发光器件阵列200在显示设备的厚度方向层叠设置，以形成显示模组。FIG. 1 is one of the structural schematic diagrams of a display module according to an embodiment. The display module according to this embodiment includes a pixel circuit array and a light emitting device array. The display module of the embodiment of the present application is applied to a display device with a narrow frame. The display device may be a smart phone, a tablet computer, a game device, an augmented reality (Augmented Reality, AR) device, a notebook, a desktop computing device, a wearable device, and the like. For the convenience of understanding, the following uses the mobile phone as an example for illustration. FIG. 2 is one of the structural schematic diagrams of a pixel circuit array in an embodiment, and FIG. 3 is a structural schematic diagram of a light emitting device array in an embodiment. The pixel circuit array 100 and the light emitting device array 200 are stacked in the thickness direction of the display device to form Display mods.
结合参考图1至图3，所述发光器件阵列200在第一方向上的尺寸大于所述像素电路阵列100在第一方向上的尺寸。可以理解的是，相较于发光器件阵列200和像素电路阵列100的尺寸1：1设置的方式，基于本实施例的尺寸设置方式，能够在保持发光器件阵列200的尺寸不变的基础上，通过相对缩小像素电路阵列100的尺寸，提供一定的空间用于设置其他***电路。其他***电路包括但不限于栅极驱动电路、扇出走线组500等。因此，在本实施例中，可以将其他***电路和像素电路阵列100设置在同一层中，并使发光器件阵列200部分设置在其他***电路上。其中，发光器件阵列200与像素电路阵列100之间的尺寸差异，决定了其他***电路能够设置在发光器件阵列200下的具体面积。即，像素电路阵列100相较于发光器件阵列200的尺寸越小，其他***电路能够设置在发光器件阵列200下的具体面积越大，相应地，其他***电路在第一方向上暴露于发光器件阵列200外部的面积越小，用于遮挡上述其他***电路的边框宽度越小。因此，基于上述设置方式，可以缩窄显示模组在第一方向上的边框宽度。Referring to FIG. 1 to FIG. 3 , the size of the light emitting device array 200 in the first direction is larger than the size of the pixel circuit array 100 in the first direction. It can be understood that, compared with the 1:1 arrangement of the size of the light emitting device array 200 and the pixel circuit array 100, based on the size setting method of this embodiment, the size of the light emitting device array 200 can be kept unchanged, By relatively reducing the size of the pixel circuit array 100 , a certain space is provided for arranging other peripheral circuits. Other peripheral circuits include but are not limited to gate drive circuits, fan-out wire group 500 and so on. Therefore, in this embodiment, other peripheral circuits and the pixel circuit array 100 can be arranged in the same layer, and the light emitting device array 200 can be partially arranged on other peripheral circuits. Wherein, the size difference between the light emitting device array 200 and the pixel circuit array 100 determines the specific area where other peripheral circuits can be arranged under the light emitting device array 200 . That is, the smaller the size of the pixel circuit array 100 compared with the light emitting device array 200, the larger the specific area that other peripheral circuits can be arranged under the light emitting device array 200. Correspondingly, other peripheral circuits are exposed to the light emitting device in the first direction. The smaller the area outside the array 200 is, the smaller the width of the frame used to shield the above-mentioned other peripheral circuits is. Therefore, based on the above arrangement, the frame width of the display module in the first direction can be narrowed.
参考图2，像素电路阵列100包括多个第一像素子电路和多个第二像素子电路。各所述第二像素子电路分别位于在第一方向上相邻的两个所述第一像素子电路之间，所述第一方向垂直于所述显示模组的厚度方向。其中，第一像素子电路可以理解为实际用于控制发光器件阵列200的发光亮度和发光颜色等特性的像素子电路。第二像素子电路可以理解为虚拟像素子电路(dummy pixel)，如图2所示，第二像素子电路不与发光器件连接，而只是用于优化像素电路阵列100的尺寸和排列方式。Referring to FIG. 2, the pixel circuit array 100 includes a plurality of first pixel sub-circuits and a plurality of second pixel sub-circuits. Each of the second pixel sub-circuits is respectively located between two adjacent first pixel sub-circuits in a first direction, and the first direction is perpendicular to the thickness direction of the display module. Wherein, the first pixel sub-circuit can be understood as a pixel sub-circuit that is actually used to control characteristics such as light-emitting brightness and light-emitting color of the light-emitting device array 200 . The second pixel sub-circuit can be understood as a dummy pixel sub-circuit (dummy pixel). As shown in FIG.
参考图3，所述发光器件阵列200包括多个发光器件201，所述发光器件201包括阴极和阳极。各 多个所述发光器件201的阳极分别与多个所述第一像素子电路一一对应地连接。具体地，图2中各第一像素子电路中位于下部的圆点结构即为第一像素子电路用于连接发光器件201的节点，相应地，图3中各发光器件201中的圆圈结构即为用于连接第一像素子电路的阳极。需要说明的是，图2和图3实施例中的圆圈结构仅用于示例性说明，而不用于限定本申请的保护范围。可以理解的是，在相对缩小像素电路阵列100后，需要使第一像素子电路与对应的发光器件201的位置相对应，以避免二者之间的距离过远造成信号传输速度慢或信号传输过程中的损耗，从而避免不同发光器件201的响应速度或发光亮度之间的差异过大。因此，第二像素子电路能够填补缩小尺寸导致的第一像素子电路之间的间隙，以实现上述位置对应的目的，提高第一像素子电路的排列均匀性，从而提高显示模组的显示均匀性。Referring to FIG. 3 , the light emitting device array 200 includes a plurality of light emitting devices 201 including cathodes and anodes. The anodes of each of the plurality of light-emitting devices 201 are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence. Specifically, the dot structure located at the lower part of each first pixel sub-circuit in FIG. 2 is the node for connecting the first pixel sub-circuit to the light emitting device 201. Correspondingly, the circle structure in each light emitting device 201 in FIG. 3 is is used to connect the anode of the first pixel sub-circuit. It should be noted that the circle structures in the embodiments in FIG. 2 and FIG. 3 are only for illustrative purposes, and are not intended to limit the protection scope of the present application. It can be understood that, after the pixel circuit array 100 is relatively reduced, it is necessary to make the first pixel sub-circuit correspond to the position of the corresponding light-emitting device 201, so as to avoid slow signal transmission speed or signal transmission caused by too long distance between the two. loss during the process, so as to avoid excessive differences in the response speed or luminous brightness of different light emitting devices 201 . Therefore, the second pixel sub-circuit can fill the gap between the first pixel sub-circuits caused by size reduction, so as to achieve the above-mentioned purpose of position correspondence, improve the arrangement uniformity of the first pixel sub-circuit, thereby improving the display uniformity of the display module. sex.
图4为未设置第二像素子电路的显示模组的结构示意图，参考图4，在图4的左上角和右下角，分别加粗示出了两个绿色发光器件对应的驱动走线，驱动走线是指连接于发光器件和对应的第一像素子电路之间的走线。其中，位于图4中左侧的发光器件可以理解为靠近显示模组中心的发光器件，而图4中右侧的发光器件可以理解为靠近显示模组边框的发光器件。明显地，两条驱动走线之间的长度差异较大，并会导致发光器件在响应速度或发光亮度等性能上的差异，导致显示模组在第一方向上的显示不均匀。而且，更关键的是，在图4中，驱动走线的长度变化是渐变式的，即，越靠近边框，驱动走线的长度越长。因此，图4中并不存在一个驱动走线的长度的设置方式相同的区域。Fig. 4 is a schematic structural diagram of a display module without a second pixel sub-circuit. Referring to Fig. 4, in the upper left corner and lower right corner of Fig. The wiring refers to the wiring connected between the light emitting device and the corresponding first pixel sub-circuit. Wherein, the light emitting device on the left side in FIG. 4 can be understood as the light emitting device near the center of the display module, and the light emitting device on the right side in FIG. 4 can be understood as the light emitting device near the frame of the display module. Obviously, the length difference between the two driving wires is large, which will lead to the difference in the performance of the light emitting device such as response speed or luminous brightness, resulting in uneven display of the display module in the first direction. Moreover, more critically, in FIG. 4 , the length of the driving trace changes gradually, that is, the closer to the frame, the longer the length of the driving trace. Therefore, there is no region in FIG. 4 where the lengths of the driving traces are set in the same manner.
继续参考图2，本实施例的显示模组还包括电路走线101。可以理解的是，第一像素子电路需要连接大量的信号线(即图中沿第二方向延伸的多条细走线102)，以实现所需要的发光控制功能，而第二像素子电路不用于控制发光器件，因此，第二像素子电路也不需要设置相应的信号线。但是，这会导致第一像素子电路对应区域的走线密度较大，而第二像素子电路对应区域的走线密度较小，而金属走线通常具有一定的反光特性，若走线密度不同，会导致显示模组在不同区域的发光特性不同，从而导致息屏Mura的问题。其中，mura是指显示模组显示不均匀的现象。因此，在本实施例中，通过设置电路走线101，显示模组中的走线排布较为均匀，可以改善显示模组中走线密度的分布均匀性，从而避免电路走线101密度差异引起的息屏Mura的问题。而且，走线密度分布均匀性较好的显示模组也有利于稳定工艺制程，保证显示模组中电路结构的电性一致性，保证显示的均匀性。其中，电路走线101的长度可以与第一像素子电路中的信号线102的长度相等，以进一步提高电路走线101和信号线102的一致性。Continuing to refer to FIG. 2 , the display module of this embodiment further includes a circuit trace 101 . It can be understood that the first pixel sub-circuit needs to connect a large number of signal lines (that is, a plurality of thin wires 102 extending along the second direction in the figure) to realize the required light emission control function, while the second pixel sub-circuit does not need Therefore, the second pixel sub-circuit does not need to be provided with corresponding signal lines. However, this will result in a relatively high routing density in the area corresponding to the first pixel sub-circuit, and a relatively small routing density in the area corresponding to the second pixel sub-circuit, and metal routing usually has a certain reflective characteristic. If the routing density is different , will lead to different luminous characteristics of the display module in different areas, which will lead to the problem of screen mura. Among them, mura refers to the phenomenon that the display module displays unevenly. Therefore, in this embodiment, by setting the circuit traces 101, the traces in the display module are relatively evenly arranged, which can improve the distribution uniformity of the trace density in the display module, thereby avoiding the density difference of the circuit traces 101. The problem of the screen Mura. Moreover, a display module with a better distribution of wiring density is also conducive to stabilizing the process, ensuring the electrical consistency of the circuit structure in the display module, and ensuring the uniformity of the display. Wherein, the length of the circuit trace 101 may be equal to the length of the signal line 102 in the first pixel sub-circuit, so as to further improve the consistency between the circuit trace 101 and the signal line 102 .
其中，电路走线101还可以分别与多个第二像素子电路连接，且连接方式对应于第一像素子电路与信号线的连接方式。具体地，第一像素子电路连接的信号线的类型可以是但不限于数据信号线，栅极线和发光控制线。以信号线为数据信号线为例，若电路走线101平行于数据信号线，则电路走线101与多个第二像素子电路的连接方式可以对应于数据信号线与第一像素子电路的连接方式，即，数据信号线与第一像素子电路的数据信号端连接，则电路走线101就与第二像素子电路的数据信号端连接，以进一步提高显示模组中各走线结构的一致性。Wherein, the circuit traces 101 can also be respectively connected to a plurality of second pixel sub-circuits, and the connection mode is corresponding to the connection mode between the first pixel sub-circuits and the signal lines. Specifically, the types of signal lines connected to the first pixel sub-circuit may be but not limited to data signal lines, gate lines and light emission control lines. Taking the signal line as the data signal line as an example, if the circuit trace 101 is parallel to the data signal line, the connection mode between the circuit trace 101 and the plurality of second pixel sub-circuits may correspond to the connection between the data signal line and the first pixel sub-circuit. The connection mode, that is, the data signal line is connected to the data signal end of the first pixel sub-circuit, and then the circuit wiring 101 is connected to the data signal end of the second pixel sub-circuit, so as to further improve the flexibility of each wiring structure in the display module. consistency.
可选地，各发光器件的阴极可以互相隔离，各发光器件的阴极连接至对应的阴极信号线，并分别从连接的阴极信号线获取阴极的电信号，其中，阴极的电信号可以由显示驱动芯片输出。各发光器件的阴极也可以采用共阴极设计，即发光器件的阴极互相连通，并通过调节阳极的电信号的方式分别控制各发光器件的亮度，以实现更加简单的制备工艺和控制方式。需要说明的是，上述示例仅用于举例说明，而不用于限定本实施例的保护范围，本实施例的技术方案可以应用于上述任一种阴极结构。Optionally, the cathodes of each light emitting device can be isolated from each other, the cathodes of each light emitting device are connected to the corresponding cathode signal lines, and the electrical signals of the cathodes are respectively obtained from the connected cathode signal lines, wherein the electrical signals of the cathodes can be driven by the display chip output. The cathode of each light-emitting device can also adopt a common cathode design, that is, the cathodes of the light-emitting devices are connected to each other, and the brightness of each light-emitting device is controlled separately by adjusting the electrical signal of the anode, so as to achieve a simpler manufacturing process and control method. It should be noted that the above examples are only for illustration, and are not intended to limit the scope of protection of this embodiment, and the technical solutions of this embodiment can be applied to any of the above cathode structures.
可以理解的是，在显示模组中，需要在***电路的区域通过导电结构连接阴极信号线和发光器件的阴极，以将阴极信号线上的电信号传输至发光器件的阴极，从而实现电性导通。但是，在实现前述窄边框的显示模组的过程中，通常情况下需要适当压缩***电路的尺寸。因此，用于连接阴极信号线和发光器件的阴极的导电结构的尺寸也会相对缩小，从而容易导致阴极信号线和发光器件的阴极之间的电性接触不良或者接触阻抗加大，进而各发光器件的阴极电性不均匀，并甚至可能引发显示mura。此外，每个发光器件的阴极可以等效为一个电阻R1，相连接的多个发光器件的阴极可以等效为串联的多个电阻，即nR1，因此，相连接的多个发光器件的阴极越多，等效电阻越大，阴极的电压信号在传输过程中的阻碍和损耗越大，显示模组中各发光器件的阴极电压的一致性越差。It can be understood that in the display module, it is necessary to connect the cathode signal line and the cathode of the light-emitting device through a conductive structure in the area of the peripheral circuit, so as to transmit the electrical signal on the cathode signal line to the cathode of the light-emitting device, thereby realizing electrical performance. conduction. However, in the process of realizing the aforementioned display module with narrow borders, it is usually necessary to properly reduce the size of peripheral circuits. Therefore, the size of the conductive structure used to connect the cathode signal line and the cathode of the light-emitting device will also be relatively reduced, which will easily lead to poor electrical contact or increased contact resistance between the cathode signal line and the cathode of the light-emitting device, and then each emits light. The cathode of the device is electrically non-uniform and may even cause a display mura. In addition, the cathode of each light-emitting device can be equivalent to a resistor R1, and the cathodes of multiple connected light-emitting devices can be equivalent to multiple resistors connected in series, that is, nR1. Therefore, the more connected the cathodes of multiple light-emitting devices The greater the equivalent resistance, the greater the hindrance and loss of the cathode voltage signal during transmission, and the worse the consistency of the cathode voltage of each light-emitting device in the display module.
为了抑制上述阴极电性不均匀的问题，本实施例将所述电路走线分别与多个所述发光器件的阴极连接，其中，电路走线的延伸方向可以平行于显示模组的栅极线、初始化信号线和数据信号线中的一个，本实施例不做限定。在本实施例中，通过将电路走线分别与多个发光器件的阴极连接，可以理解为将电路走线的等效电阻与发光器件的阴极的等效电阻相并联。示例性地，以电路走线的等效电阻与一个发光器件的阴极的等效电阻并联为例，并联后的整体结构的阻抗为R1R2/(R1+R2)，即小于一个发光器件的阴极的等效电阻R1，从而减小了阴极的电压信号在传输过程中的阻碍和损耗，提高了各发光器件的阴极电压的一致性。In order to suppress the above-mentioned problem of uneven electrical properties of the cathode, in this embodiment, the circuit traces are respectively connected to the cathodes of a plurality of the light-emitting devices, wherein the extending direction of the circuit traces may be parallel to the gate lines of the display module One of the initialization signal line and the data signal line is not limited in this embodiment. In this embodiment, by connecting the circuit traces to the cathodes of the plurality of light emitting devices respectively, it can be understood that the equivalent resistance of the circuit traces is connected in parallel with the equivalent resistance of the cathodes of the light emitting devices. Exemplarily, taking the parallel connection of the equivalent resistance of the circuit trace and the equivalent resistance of the cathode of a light-emitting device as an example, the impedance of the overall structure after parallel connection is R1R2/(R1+R2), which is less than that of the cathode of a light-emitting device The equivalent resistance R1 reduces the obstruction and loss of the cathode voltage signal during transmission, and improves the consistency of the cathode voltage of each light emitting device.
可选地，电路走线与发光器件的阴极的连接可以为直接连接，也可以为间接连接。例如，发光器件 的阴极可以经由导电结构连接至电路走线，上述导电结构可以是但不限于金属化孔、导电插塞、走线等。而且，本实施例不对电路走线的数量进行限定。可选地，电路走线的数量可以为一条，则发光器件阵列200中的全部发光器件的阴极连接至同一电路走线。电路走线的数量也可以为多条，则当采用前述互相隔离的阴极设计时，一部分发光器件的阴极可以连接至同一电路走线，另一部分发光器件的阴极可以连接至另外的同一电路走线。而且，当电路走线的数量为多条时，可以根据预设规则选择连接至同一电路走线的多个发光器件。一示例性地，继续参考图2，图2中示出了8个第一像素子电路的阴极节点(图2中的圆圈形结构)，可以使每条电路走线101分别连接相同数量的第一像素子电路的阴极，并且使连接至同一电路走线101的多个第一像素子电路呈轴对称设置，且对称轴即为连接的该电路走线101。即，如图2所示，每条电路走线101用于连接位于四列中的各第一像素子电路，且其中两列位于电路走线101的左侧，另外两列位于电路走线101的右侧。进一步地，可以是位于同一列的多个第一像素子电路对应的发光器件的阴极连接至同一电路走线101。基于上述结构，既可以避免发光器件的阴极所连接的走线过长，也可以使电路走线101对不同区域的阴极具有相近的并联效果，从而使阴极各处对应的并联后电阻值相近，提高了各发光器件的阴极电压的一致性，进而提高了显示的均匀性。Optionally, the connection between the circuit trace and the cathode of the light emitting device may be a direct connection or an indirect connection. For example, the cathode of the light emitting device may be connected to the circuit trace via a conductive structure, which may be but not limited to a metallized hole, a conductive plug, a trace, and the like. Moreover, this embodiment does not limit the number of circuit wires. Optionally, the number of circuit traces may be one, and the cathodes of all light emitting devices in the light emitting device array 200 are connected to the same circuit trace. The number of circuit traces can also be multiple, so when adopting the aforementioned mutually isolated cathode design, the cathodes of some light-emitting devices can be connected to the same circuit traces, and the cathodes of another part of the light-emitting devices can be connected to another same circuit traces . Moreover, when there are multiple circuit traces, multiple light emitting devices connected to the same circuit trace can be selected according to preset rules. As an example, continuing to refer to FIG. 2, FIG. 2 shows cathode nodes (circular structures in FIG. 2) of eight first pixel sub-circuits, and each circuit trace 101 can be respectively connected to the same number of first pixel sub-circuits. A cathode of a pixel sub-circuit, and a plurality of first pixel sub-circuits connected to the same circuit trace 101 are arranged axially symmetrically, and the axis of symmetry is the connected circuit trace 101 . That is, as shown in FIG. 2 , each circuit trace 101 is used to connect the first pixel sub-circuits located in four columns, and two columns are located on the left side of the circuit trace 101, and the other two columns are located on the circuit trace 101 to the right of the . Further, the cathodes of the light emitting devices corresponding to the plurality of first pixel sub-circuits in the same column may be connected to the same circuit wiring 101 . Based on the above-mentioned structure, it is possible to prevent the wiring connected to the cathode of the light-emitting device from being too long, and it is also possible to make the circuit wiring 101 have a similar parallel connection effect on the cathodes in different regions, so that the corresponding parallel resistance values of the cathodes are similar. The uniformity of the cathode voltage of each light-emitting device is improved, thereby improving the display uniformity.
在本实施例中，基于上述显示模组的结构，减小了其他***电路在第一方向上暴露于发光器件阵列200外部的宽度，即缩窄了显示模组的边框宽度。同时，通过加入第二像素子电路，可以避免不同发光器件的驱动距离差异导致的发光器件的响应速度或发光亮度差异，从而提高了显示模组的显示均匀性。而且，本实施例还设置了与第二像素子电路连接的电路走线101，以提高第一像素子电路和第二像素子电路的一致性抑制息屏mura问题，并将上述电路走线101与发光器件的阴极连接，使阴极的电阻与电路走线101的电阻相并联，相当于降低了阴极和电路走线101这一整体结构的阻抗。即，减小了阴极的电压信号在传输过程中的阻碍和损耗，从而提高了各发光器件的阴极电压的一致性，避免了阴极电压对各发光器件的显示亮度的影响，进而提高了显示模组的显示均匀性。In this embodiment, based on the above structure of the display module, the width of other peripheral circuits exposed to the outside of the light emitting device array 200 in the first direction is reduced, that is, the frame width of the display module is narrowed. At the same time, by adding the second pixel sub-circuit, it is possible to avoid the difference in the response speed or luminance of the light-emitting device caused by the difference in the driving distance of different light-emitting devices, thereby improving the display uniformity of the display module. Moreover, in this embodiment, a circuit wiring 101 connected to the second pixel sub-circuit is also provided to improve the consistency between the first pixel sub-circuit and the second pixel sub-circuit and suppress the screen mura problem, and the above-mentioned circuit wiring 101 It is connected to the cathode of the light-emitting device, and the resistance of the cathode is connected in parallel with the resistance of the circuit trace 101, which is equivalent to reducing the impedance of the overall structure of the cathode and the circuit trace 101. That is, the obstruction and loss of the cathode voltage signal in the transmission process are reduced, thereby improving the consistency of the cathode voltage of each light emitting device, avoiding the influence of the cathode voltage on the display brightness of each light emitting device, and further improving the display mode. Group display uniformity.
继续参考图2，在其中一个实施例中，所述像素电路阵列100包括多条所述电路走线101，且多条所述电路走线101互相平行。具体地，本实施例不限制电路走线101的具体形状，电路走线101可以为直线结构，也可以为折线形结构等。通过将多条电路走线101互相平行设置，可以提高多条电路走线101的一致性。既可以避免不同形状的电路走线101的反光状态不同，从而改善显示模组的息屏mura的问题。还可以避免不同形状的电路走线101的工艺一致性不佳，从而提高显示模组的制备良率。Continuing to refer to FIG. 2 , in one embodiment, the pixel circuit array 100 includes a plurality of circuit traces 101 , and the plurality of circuit traces 101 are parallel to each other. Specifically, this embodiment does not limit the specific shape of the circuit traces 101, and the circuit traces 101 may be in a straight line structure, or may be in a zigzag structure or the like. By arranging the multiple circuit traces 101 parallel to each other, the consistency of the multiple circuit traces 101 can be improved. It can avoid the different reflective states of the circuit traces 101 with different shapes, thereby improving the mura problem of the display module. It can also avoid poor process consistency of circuit traces 101 with different shapes, thereby improving the manufacturing yield of the display module.
在其中一个实施例中，继续参考图2，所述显示模组设有第一子阵列区110，所述第一子阵列区110中设有多个第一像素电路111和多个第二像素电路112，所述第一像素电路111包括多个所述第一像素子电路，所述第二像素电路112包括多个所述第二像素子电路，且在所述第一方向上任意两个相邻的所述第一像素电路111之间设有一个所述第二像素电路112。所述电路走线101在虚拟平面上的投影位于所述第二像素子电路在所述虚拟平面上的投影中，所述虚拟平面垂直于所述显示模组的厚度方向。优选地，所述电路走线101在虚拟平面上的投影全部位于所述第二像素电路112在所述虚拟平面上的投影中。即，可以相应设置均沿第二方向延伸的多条所述电路走线101，以使电路走线101的延伸方向与第二像素子电路的排列方向相对应，从而可以避免电路走线101对第一像素子电路造成遮挡，也即避免对第一像素子电路的信号线路径造成影响，同时，电路走线101还能够实现与阴极的连接功能，以降低整体阻抗，提高各阴极之间的电压均匀性。In one of the embodiments, referring to FIG. 2 , the display module is provided with a first sub-array area 110, and a plurality of first pixel circuits 111 and a plurality of second pixels are arranged in the first sub-array area 110. A circuit 112, the first pixel circuit 111 includes a plurality of the first pixel sub-circuits, the second pixel circuit 112 includes a plurality of the second pixel sub-circuits, and any two in the first direction One second pixel circuit 112 is provided between adjacent first pixel circuits 111 . The projection of the circuit trace 101 on the virtual plane is located in the projection of the second pixel sub-circuit on the virtual plane, and the virtual plane is perpendicular to the thickness direction of the display module. Preferably, all the projections of the circuit traces 101 on the virtual plane are located in the projections of the second pixel circuit 112 on the virtual plane. That is, a plurality of said circuit traces 101 all extending along the second direction can be arranged correspondingly, so that the extending direction of the circuit traces 101 corresponds to the arrangement direction of the second pixel sub-circuits, thereby avoiding the pairing of the circuit traces 101 The first pixel sub-circuit causes shading, that is, avoids affecting the signal line path of the first pixel sub-circuit. At the same time, the circuit trace 101 can also realize the connection function with the cathode, so as to reduce the overall impedance and improve the connection between the cathodes. voltage uniformity.
在其中一个实施例中，继续参考图2，多条所述电路走线101等距间隔排列。通过等距间隔排列的多条电路走线101，可以使每条电路走线101的等效电阻相对接近，还可以使并联至每条电路走线101的阴极的等效电阻相对接近，从而使并联后显示模组上各处的阻抗相近，从而进一步提高显示模组的阴极电压的一致性。In one embodiment, continuing to refer to FIG. 2 , a plurality of circuit traces 101 are arranged at equal intervals. By arranging a plurality of circuit traces 101 at equal intervals, the equivalent resistance of each circuit trace 101 can be relatively close, and the equivalent resistance of the cathode connected in parallel to each circuit trace 101 can be relatively close, so that After the parallel connection, the impedances of all places on the display module are similar, thereby further improving the consistency of the cathode voltage of the display module.
在其中一个实施例中，继续参考图3，所述发光器件阵列200划分为多个发光重复单元210，各所述发光重复单元210分别包括多个所述发光器件201。所述发光重复单元210包括多个重复子单元2101，所述发光重复单元210包括4n个红色发光器件、8n个绿色发光器件和4n个蓝色发光器件，所述n为大于等于1的整数。其中，相邻的两个像素可以共用红色发光器件或蓝色发光器件，从而提高显示模组的分辨率，并抑制显示模组的彩边问题，进而提升显示质量。可以理解的是，本实施例不具体限定红色发光器件、绿色发光器件和蓝色发光器件之间的排列方式，只要能够实现上述提升显示模组的分辨率的技术方案，都属于本实施例的保护范围。In one embodiment, referring to FIG. 3 , the light emitting device array 200 is divided into a plurality of light emitting repeating units 210 , and each of the light emitting repeating units 210 includes a plurality of light emitting devices 201 respectively. The light emitting repeating unit 210 includes a plurality of repeating subunits 2101. The light emitting repeating unit 210 includes 4n red light emitting devices, 8n green light emitting devices and 4n blue light emitting devices, where n is an integer greater than or equal to 1. Wherein, two adjacent pixels can share the red light-emitting device or the blue light-emitting device, thereby improving the resolution of the display module, suppressing the color fringing problem of the display module, and further improving the display quality. It can be understood that this embodiment does not specifically limit the arrangement of the red light-emitting devices, green light-emitting devices and blue light-emitting devices, as long as the above-mentioned technical solutions for improving the resolution of the display module can be realized, they all belong to this embodiment. protected range.
在其中一个实施例中，继续参考图3，各所述重复子单元2101分别包括互相分离的一个所述红色发光器件、两个所述绿色发光器件和一个所述蓝色发光器件，其中，所述重复子单元2101中的一个所述绿色发光器件、一个所述红色发光器件分别具有位于虚拟四边形2102的两个第一顶点的中心，两个所述第一顶点位于所述虚拟四边形2102的一条对角线上。所述重复子单元2101中的另一个所述绿色发光器件、一个所述蓝色发光器件分别具有位于虚拟四边形2102的两个第二顶点的中心，两个所述第 二顶点位于所述虚拟四边形2102的另一条对角线上。In one of the embodiments, continuing to refer to FIG. 3 , each of the repeating subunits 2101 includes one of the red light emitting devices, two of the green light emitting devices and one of the blue light emitting devices that are separated from each other, wherein the One of the green light-emitting devices and one of the red light-emitting devices in the repeating subunit 2101 respectively have the centers of the two first vertices of the virtual quadrilateral 2102, and the two first vertices are located on one side of the virtual quadrilateral 2102. on the diagonal. The other green light-emitting device and one blue light-emitting device in the repeating subunit 2101 respectively have the centers of two second vertices located in the virtual quadrilateral 2102, and the two second vertices are located in the virtual quadrilateral 2102 on the other diagonal.
需要说明的是，本实施例中的各发光器件201可以是但不限于有机发光二极管(Organic light-emitting diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)和微米级发光二极管(Micro LED)等。本申请各实施例均以发光器件201为有机发光二极管为例进行说明。其中，各发光器件201可为不同颜色的有机发光二极管，如红色OLED、绿色OLED和蓝色OLED等，每个发光器件201的驱动电路可以相同，但不同颜色的发光器件201的发光层材料不同，从而实现不同颜色的显示，使得显示设备实现全彩显示。It should be noted that each light-emitting device 201 in this embodiment may be, but not limited to, organic light-emitting diodes (Organic light-emitting diodes, OLEDs), quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLEDs) and micron-scale light-emitting diodes (Micro LED), etc. Each embodiment of the present application is described by taking the light emitting device 201 as an organic light emitting diode as an example. Wherein, each light-emitting device 201 can be an organic light-emitting diode of different colors, such as red OLED, green OLED and blue OLED, etc., and the driving circuit of each light-emitting device 201 can be the same, but the materials of the light-emitting layers of the light-emitting devices 201 of different colors are different. , so as to realize the display of different colors, so that the display device can realize full-color display.
示例性地，若显示模组需要实现较丰富的色彩或较大的色域，则可以设置较多数量的发光器件201，例如包括四种不同颜色的发光器件201。在本实施例中，以显示模组包括三种不同颜色的发光器件201为例进行说明，三种颜色可以分别为红色(R)、绿色(G)和蓝色(B)。可以理解的是，上述数量仅用于示例性说明，而不用于限定本实施例的保护范围。For example, if the display module needs to achieve richer colors or a larger color gamut, a larger number of light emitting devices 201 may be provided, for example, light emitting devices 201 including four different colors. In this embodiment, it is illustrated by taking that the display module includes three light emitting devices 201 of different colors, and the three colors may be red (R), green (G) and blue (B) respectively. It can be understood that the above numbers are only used for exemplary description, and are not used to limit the protection scope of this embodiment.
图5为一实施例的显示模组的剖视示意图，图5的剖面方向垂直于显示模组的显示面。在其中一个实施例中，所述显示模组包括像素定义层1106、阳极层1107、发光材料层1108和阴极层1109。FIG. 5 is a schematic cross-sectional view of a display module according to an embodiment, and the cross-sectional direction of FIG. 5 is perpendicular to the display surface of the display module. In one embodiment, the display module includes a pixel definition layer 1106 , an anode layer 1107 , a luminescent material layer 1108 and a cathode layer 1109 .
其中，像素定义层1106设有互相隔离的多个像素开口，像素定义层1106能够限制发光材料层1108的沉积位置，从而提高形成发光器件时的位置精度，还能够防止在发光时相邻的发光器件之间发生颜色的串扰，从而提高显示模组的显示质量。阳极层1107分别设于多个所述像素开口中，且阳极层1107还有部分埋设于像素定义层1106下方。发光材料层1108分别设于多个所述像素开口中所述阳极层1107的表面。阴极层1109覆盖所述发光材料层1108和所述像素定义层1106的表面，阴极层1109可以理解为连续、完整覆盖于发光材料层1108和像素定义层1106的表面。其中，位于同一所述像素开口中的所述阳极层1107、所述发光材料层1108和所述阴极层1109构成一个所述发光器件。即，本实施例提供了一种共阴极结构的显示模组，具体地，图5中示出了两个发光器件，两个虚线框所示分别为两个发光器件对应的第一像素子电路，两个发光器件的阴极相连通。共阴极结构的显示模组的阴极制备方式简单，形成完整的阴极材料膜层后，无需复杂的图形化工艺，即可将整个膜层作为各个发光器件的阴极，而且不会影响显示模组的显示质量。Among them, the pixel definition layer 1106 is provided with a plurality of pixel openings isolated from each other. The pixel definition layer 1106 can limit the deposition position of the luminescent material layer 1108, thereby improving the positional accuracy when forming a light emitting device, and can also prevent adjacent light emission when emitting light. Color crosstalk occurs between devices, thereby improving the display quality of the display module. The anode layer 1107 is respectively disposed in the plurality of pixel openings, and a part of the anode layer 1107 is buried under the pixel definition layer 1106 . The luminescent material layer 1108 is respectively disposed on the surface of the anode layer 1107 in the plurality of pixel openings. The cathode layer 1109 covers the surfaces of the luminescent material layer 1108 and the pixel definition layer 1106 , and the cathode layer 1109 can be understood as continuously and completely covering the surfaces of the luminescent material layer 1108 and the pixel definition layer 1106 . Wherein, the anode layer 1107, the light emitting material layer 1108 and the cathode layer 1109 located in the same pixel opening constitute one light emitting device. That is, this embodiment provides a display module with a common cathode structure. Specifically, two light-emitting devices are shown in FIG. , the cathodes of the two light-emitting devices are connected. The cathode preparation method of the display module with a common cathode structure is simple. After forming a complete cathode material film layer, the entire film layer can be used as the cathode of each light-emitting device without complicated patterning process, and it will not affect the performance of the display module. Display quality.
继续参考图5，在其中一个实施例中，显示模组还包括像素电路层1100和平坦化层1114，像素电路层1100用于设置所述像素电路阵列，即，不同发光器件对应的第一像素子电路位于相同的像素电路层1100中，例如图5中两个虚线框示出了两个发光器件分别对应的第一像素子电路，但这两个第一像素子电路位于相同的像素电路层1100中，本实施例仅以其中一个第一像素子电路为例进行说明。其中，像素电路层1100形成于基板1110表面，基板1110可包括依次交替设置的聚酰亚胺(PI)衬底层1110a和第一缓冲层1110b，在图5所示的实施例中，基板1110包括依次交替设置的两个聚酰亚胺(PI)衬底层1110a和两个第一缓冲层1110b。可以理解的是，基板1110也可以包括更多数量的聚酰亚胺(PI)衬底层1110a和第一缓冲层1110b。Continuing to refer to FIG. 5, in one embodiment, the display module further includes a pixel circuit layer 1100 and a planarization layer 1114. The pixel circuit layer 1100 is used to set up the pixel circuit array, that is, the first pixels corresponding to different light emitting devices The sub-circuits are located in the same pixel circuit layer 1100. For example, the two dashed boxes in FIG. In 1100, this embodiment only takes one of the first pixel sub-circuits as an example for illustration. Wherein, the pixel circuit layer 1100 is formed on the surface of the substrate 1110. The substrate 1110 may include polyimide (PI) substrate layers 1110a and first buffer layers 1110b arranged alternately in sequence. In the embodiment shown in FIG. 5, the substrate 1110 includes Two polyimide (PI) substrate layers 1110a and two first buffer layers 1110b are arranged alternately in sequence. It can be understood that the substrate 1110 may also include more polyimide (PI) substrate layers 1110 a and first buffer layers 1110 b.
像素电路层1100实质上包括层叠设置的多个子功能层，各子功能层中分别形成有不同形状、不同材料的结构，并共同构成像素电路阵列100。具体地，请参阅图5，像素电路层1100具体包括第一栅极层1101a、第二栅极层1101b、第一源极1102、漏极区1103、源极接触结构1104和漏极接触结构1105，其中第一源极1102和漏极区1103位于同一子功能层，源极接触结构1104和漏极接触结构1105位于另外同一子功能层。进一步地，显示模组中还可以包括用于隔离第一源极1102、漏极区1103和第一栅极层1101a的第一栅绝缘层1111、用于隔离第一栅极层1101a和第二栅极层1101b的第二栅绝缘层1112，以及用于隔离第二栅极层1101b、源极接触结构1104和漏极接触结构1105的层间绝缘层1113。通过设置上述各绝缘层，可以对在厚度方向上相邻的两个膜层进行隔离，从而抑制漏电或信号干扰。The pixel circuit layer 1100 essentially includes a plurality of sub-functional layers stacked, each sub-functional layer is respectively formed with structures of different shapes and different materials, and together constitutes the pixel circuit array 100 . Specifically, referring to FIG. 5, the pixel circuit layer 1100 specifically includes a first gate layer 1101a, a second gate layer 1101b, a first source 1102, a drain region 1103, a source contact structure 1104 and a drain contact structure 1105 , wherein the first source 1102 and the drain region 1103 are located in the same sub-functional layer, and the source contact structure 1104 and the drain contact structure 1105 are located in another same sub-functional layer. Further, the display module may also include a first gate insulating layer 1111 for isolating the first source 1102, the drain region 1103 and the first gate layer 1101a, and a first gate insulating layer 1111 for isolating the first gate layer 1101a from the second The second gate insulating layer 1112 of the gate layer 1101b, and the interlayer insulating layer 1113 for isolating the second gate layer 1101b, the source contact structure 1104 and the drain contact structure 1105. By arranging the above insulating layers, two adjacent film layers in the thickness direction can be isolated, thereby suppressing electric leakage or signal interference.
其中，第一源极1102和漏极区1103在第一栅极1101的控制下导通或断开。第一栅极层1101a设置有初始化信号线、栅极驱动信号线、发光控制信号线等信号走线，还设置有第一栅极1101以及存储电容的一个极板(图未示)。第二栅极层1101b设置有初始信号线等信号走线，还设置有存储电容的另一个极板(图未示)。源漏极层用于设置数据信号线430，还设置有源极接触结构1104和漏极接触结构1105，源极接触结构1104连接至位于有源层的第一源极1102，漏极接触结构1105连接至位于有源层的第一源极1102。当第一栅极1101上的电压控制第一源极1102和漏极区1103导通时，漏极接触结构1105上的电压信号即可依次经过漏极区1103、第一源极1102、驱动走线传输至发光器件201的阳极1107，以驱动发光器件201发光。Wherein, the first source 1102 and the drain region 1103 are turned on or off under the control of the first gate 1101 . The first gate layer 1101a is provided with signal traces such as initialization signal lines, gate drive signal lines, and light emission control signal lines, as well as a first gate 1101 and a plate of a storage capacitor (not shown). The second gate layer 1101b is provided with signal traces such as initial signal wires, and is also provided with another plate of the storage capacitor (not shown in the figure). The source-drain layer is used to set the data signal line 430, and is also provided with a source contact structure 1104 and a drain contact structure 1105. The source contact structure 1104 is connected to the first source electrode 1102 located in the active layer, and the drain contact structure 1105 connected to the first source 1102 on the active layer. When the voltage on the first gate 1101 controls the conduction of the first source 1102 and the drain region 1103, the voltage signal on the drain contact structure 1105 can pass through the drain region 1103, the first source 1102, and drive away in sequence. The wire is transmitted to the anode 1107 of the light emitting device 201 to drive the light emitting device 201 to emit light.
平坦化层1114设于所述像素电路层1100和所述像素定义层1106之间，所述平坦化层1114中设有多条驱动走线L，由于多个发光器件的位置不同，且各发光器件对应的第一像素子电路的位置也不同，因此，需要设置不同长度驱动走线L，以实现准确的连接。平坦化层1114能够对驱动走线L进行保护，也能够确保显示模组结构的平整性。多条所述驱动走线L的一端分别与多个所述发光器件的阳极1107 一一对应地连接，多条所述驱动走线L的另一端分别与多个所述第一像素子电路一一对应地连接，以使多个所述发光器件的阳极1107与多个所述第一像素子电路一一对应地电性导通。The planarization layer 1114 is arranged between the pixel circuit layer 1100 and the pixel definition layer 1106, and the planarization layer 1114 is provided with a plurality of driving wires L, since the positions of the plurality of light-emitting devices are different, and each light-emitting device The positions of the first pixel sub-circuits corresponding to the devices are also different, therefore, it is necessary to set the driving traces L with different lengths to achieve accurate connection. The planarization layer 1114 can protect the driving wires L, and can also ensure the flatness of the display module structure. One ends of the plurality of driving lines L are respectively connected to the anodes 1107 of the plurality of light-emitting devices in one-to-one correspondence, and the other ends of the plurality of driving lines L are respectively connected to the plurality of first pixel sub-circuits. One-to-one connection, so that the anodes 1107 of the plurality of light-emitting devices are electrically connected to the plurality of first pixel sub-circuits in a one-to-one correspondence.
其中，相同颜色的各所述发光器件对应的驱动走线L的长度差在第一预设范围内，长度差是指最长的驱动走线L的长度与最短的驱动走线L的长度之间的差值。第一预设范围例如可以为0um至200um。可以理解的是，第一预设范围可以根据显示设备的类型、分辨率等共同确定。例如，类型可以包括手机、平板电脑和电视，则平板电脑的第一预设范围可以大于手机的第一预设范围，且小于电视的第一预设范围。在本实施例中，通过将相同颜色的各所述发光器件对应的驱动走线L的长度差控制在第一预设范围内，可以减少驱动走线L的长度差异导致的发光器件的亮度差异，从而提高显示模组的显示均匀性。可选地，驱动走线L可以是透明金属线，例如，氧化铟锡(Indium Tin Oxide，ITO)金属线、氧化铝锌(Alumina zinc Oxide，AZO)金属线等。Wherein, the length difference of the driving wires L corresponding to the light-emitting devices of the same color is within the first preset range, and the length difference refers to the difference between the length of the longest driving wire L and the length of the shortest driving wire L. difference between. The first preset range may be, for example, 0 um to 200 um. It can be understood that the first preset range may be jointly determined according to the type and resolution of the display device. For example, the types may include mobile phone, tablet computer and television, and the first preset range of the tablet computer may be larger than the first preset range of the mobile phone and smaller than the first preset range of the TV. In this embodiment, by controlling the length difference of the driving wires L corresponding to the light emitting devices of the same color within the first preset range, the brightness difference of the light emitting devices caused by the length difference of the driving wires L can be reduced. , thereby improving the display uniformity of the display module. Optionally, the driving wire L may be a transparent metal wire, for example, an indium tin oxide (Indium Tin Oxide, ITO) metal wire, an aluminum zinc oxide (Alumina zinc oxide, AZO) metal wire, or the like.
图6为一实施例的第一重复单元和对应的发光器件的结构示意图，参考图6，在其中一个实施例中，相邻的一个所述第一像素电路111和一个所述第二像素电路112共同作为一个第一重复单元113。需要说明的是，本实施例以位于左侧的第一像素电路111和位于右侧的第二像素电路112为例进行划分，以形成第一重复单元113，在其他实施例中，也可以以位于右侧的第一像素电路111和位于左侧的第二像素电路112为例进行划分。结合参考图3和图6，多个所述发光重复单元210分别与多个所述第一像素电路111一一对应。所述发光重复单元210在第一方向上的尺寸与所述第一重复单元113在第一方向上的尺寸之间的差值在第二预设范围内，即，可以理解为发光重复单元210在第一方向上的尺寸与所述第一重复单元113在第一方向上的尺寸相近。其中，第二预设范围例如可以为0um至5um。在本实施例中，通过设置发光重复单元210和第一重复单元113的尺寸关系，可以实现发光重复单元210和第一重复单元113之间位置的对应性，从而设置较短的驱动走线，以提升驱动电流的稳定性和可靠性。Fig. 6 is a schematic structural diagram of a first repeating unit and a corresponding light-emitting device in an embodiment. Referring to Fig. 6, in one embodiment, one of the adjacent first pixel circuits 111 and one of the second pixel circuits 112 collectively serve as a first repeating unit 113. It should be noted that this embodiment takes the first pixel circuit 111 on the left and the second pixel circuit 112 on the right as an example to divide to form the first repeating unit 113. In other embodiments, it can also be The first pixel circuit 111 on the right and the second pixel circuit 112 on the left are divided as an example. Referring to FIG. 3 and FIG. 6 together, the plurality of light-emitting repeating units 210 are in one-to-one correspondence with the plurality of first pixel circuits 111 . The difference between the size of the light-emitting repeating unit 210 in the first direction and the size of the first repeating unit 113 in the first direction is within the second preset range, that is, it can be understood that the light-emitting repeating unit 210 The size in the first direction is similar to the size of the first repeating unit 113 in the first direction. Wherein, the second preset range may be, for example, 0 um to 5 um. In this embodiment, by setting the size relationship between the light-emitting repeating unit 210 and the first repeating unit 113, the correspondence between the positions of the light-emitting repeating unit 210 and the first repeating unit 113 can be realized, thereby setting a shorter driving line, To improve the stability and reliability of the driving current.
进一步地，第一像素子电路的尺寸可以与第二像素子电路的尺寸相同，且所述第二像素子电路的膜层结构可以与所述第一像素子电路的膜层结构相同，以降低像素电路阵列100的设计难度，还可以同时降低曝光制备过程中各种光学效应对尺寸结构的差异性影响，从而提高像素电路阵列100的制备良率，并改善走线反光不均产生的息屏mura。Further, the size of the first pixel sub-circuit may be the same as that of the second pixel sub-circuit, and the film layer structure of the second pixel sub-circuit may be the same as that of the first pixel sub-circuit, so as to reduce The design difficulty of the pixel circuit array 100 can also reduce the differential influence of various optical effects on the dimensional structure during the exposure preparation process, thereby improving the manufacturing yield of the pixel circuit array 100 and improving the off-screen caused by uneven reflection of the traces. mura.
图7为一实施例的第一像素子电路的电路图，参考图7，在本实施例中，第一像素子电路包括驱动晶体管T1、阳极初始化单元1511、栅极初始化单元1512、数据写入单元1513、阈值补偿单元1514和发光控制单元1515。FIG. 7 is a circuit diagram of a first pixel sub-circuit in an embodiment. Referring to FIG. 7, in this embodiment, the first pixel sub-circuit includes a drive transistor T1, an anode initialization unit 1511, a gate initialization unit 1512, and a data writing unit 1513 , a threshold compensation unit 1514 and a light emission control unit 1515 .
具体地，驱动晶体管T1用于生成驱动电流。其中，驱动晶体管T1的栅极与栅极初始化单元1512连接，驱动晶体管T1的第一极用于接收数据信号端Data的信号，驱动晶体管T1的第二极可对应输出驱动电流。其中，驱动电流的电流值由数据信号端Data的信号决定，并直接影响发光器件的发光亮度。Specifically, the driving transistor T1 is used to generate a driving current. Wherein, the gate of the driving transistor T1 is connected to the gate initialization unit 1512, the first pole of the driving transistor T1 is used to receive the signal of the data signal terminal Data, and the second pole of the driving transistor T1 can output the driving current correspondingly. Wherein, the current value of the driving current is determined by the signal of the data signal terminal Data, and directly affects the light-emitting brightness of the light-emitting device.
阳极初始化单元1511的控制端用于接收第二栅极信号端Scan(n)的信号，阳极初始化单元1511的输入端用于接收初始化信号，阳极初始化单元1511的输出端与发光器件的阳极连接。阳极初始化单元1511用于在驱动晶体管T1的栅极初始化后，经输入端接收初始化信号，并拉低与之连接的发光器件的阳极至初始化信号，以对发光器件的阳极进行初始化。其中，初始化信号可理解为发光器件的阳极起始充电电压。通过对发光器件的阳极进行初始化，可以释放发光器件的寄生电容中存储的电荷，从而确保发光器件的发光亮度的可靠性。具体地，阳极初始化单元1511可以包括第七晶体管T7，第七晶体管T7的第一极用于接收初始化信号端Vinit的信号，阳极初始化单元1511的输出端与发光器件的阳极连接，第七晶体管T7的栅极用于接收第二栅极信号端Scan(n)的信号。The control terminal of the anode initialization unit 1511 is used to receive the signal of the second gate signal terminal Scan(n), the input terminal of the anode initialization unit 1511 is used to receive the initialization signal, and the output terminal of the anode initialization unit 1511 is connected to the anode of the light emitting device. The anode initialization unit 1511 is used to receive an initialization signal through the input terminal after the gate of the driving transistor T1 is initialized, and pull down the anode of the light emitting device connected thereto to the initialization signal, so as to initialize the anode of the light emitting device. Wherein, the initialization signal can be understood as an initial charging voltage of the anode of the light emitting device. By initializing the anode of the light emitting device, the charge stored in the parasitic capacitance of the light emitting device can be released, thereby ensuring the reliability of the light emitting brightness of the light emitting device. Specifically, the anode initialization unit 1511 may include a seventh transistor T7, the first pole of the seventh transistor T7 is used to receive the signal of the initialization signal terminal Vinit, the output terminal of the anode initialization unit 1511 is connected to the anode of the light emitting device, and the seventh transistor T7 The gate of is used to receive the signal of the second gate signal terminal Scan(n).
栅极初始化单元1512的控制端与栅极控制端连接，用于接收第一栅极信号端Scan(n-1)的信号；栅极初始化单元1512的输入端与初始化信号端Vinit连接，用于接收初始化信号；栅极初始化单元1512的输出端与驱动晶体管T1的栅极连接。具体地，栅极初始化单元1512可根据控制端接收到的第一栅极信号端Scan(n-1)的信号拉低驱动晶体管T1的栅极电压至初始化信号，以对驱动晶体管T1的栅极进行初始化。The control terminal of the gate initialization unit 1512 is connected to the gate control terminal for receiving the signal of the first gate signal terminal Scan(n-1); the input terminal of the gate initialization unit 1512 is connected to the initialization signal terminal Vinit for Receive the initialization signal; the output terminal of the gate initialization unit 1512 is connected to the gate of the driving transistor T1. Specifically, the gate initialization unit 1512 can pull down the gate voltage of the driving transistor T1 to the initialization signal according to the signal of the first gate signal terminal Scan(n-1) received by the control terminal, so as to control the gate of the driving transistor T1 to initialize.
数据写入单元1513包括第二晶体管T2，第二晶体管T2的栅极与第二栅极信号端Scan(n)连接，第二晶体管T2的第一极与数据信号端Data连接，第二晶体管T2的第二极与驱动晶体管T1的第一极连接，第二晶体管T2用于根据第二栅极信号端Scan(n)的信号控制第二栅极信号线和驱动晶体管T1的第一极之间的信号传输路径的通断。具体地，以第二晶体管T2为P型晶体管为例，当第二栅极信号端Scan(n)的信号为低电平时，第二晶体管T2导通，并将数据信号端Data的信号传输至驱动晶体管T1的第一极；当第二栅极信号端Scan(n)的信号为低电平时，第二晶体管T2断开。可以理解的是，数据写入单元1513不局限于本实施例的第二晶体管T2，也可以为其他能够根据使能控制信号，并实现信号传输功能的其他电路结构。The data writing unit 1513 includes a second transistor T2, the gate of the second transistor T2 is connected to the second gate signal terminal Scan(n), the first pole of the second transistor T2 is connected to the data signal terminal Data, and the second transistor T2 The second pole of the drive transistor T1 is connected to the first pole, and the second transistor T2 is used to control the connection between the second gate signal line and the first pole of the drive transistor T1 according to the signal of the second gate signal terminal Scan(n). The on-off of the signal transmission path. Specifically, taking the second transistor T2 as a P-type transistor as an example, when the signal at the second gate signal terminal Scan(n) is at a low level, the second transistor T2 is turned on and transmits the signal at the data signal terminal Data to The first pole of the driving transistor T1; when the signal of the second gate signal terminal Scan(n) is at low level, the second transistor T2 is turned off. It can be understood that the data writing unit 1513 is not limited to the second transistor T2 in this embodiment, and may also be other circuit structures capable of realizing the signal transmission function according to the enable control signal.
阈值补偿单元1514分别与驱动晶体管T1的栅极、第二极连接，用于根据第二栅极信号端Scan(n) 的信号控制驱动晶体管T1的栅极和第二极之间的信号传输路径的通断。具体地，通过设置阈值补偿单元1514，可以对驱动晶体管T1的阈值电压进行补偿，从而避免驱动晶体管T1的阈值电压对发光器件的亮度造成影响。The threshold compensation unit 1514 is respectively connected to the gate and the second pole of the driving transistor T1, and is used to control the signal transmission path between the gate and the second pole of the driving transistor T1 according to the signal of the second gate signal terminal Scan(n) on and off. Specifically, by setting the threshold compensation unit 1514, the threshold voltage of the driving transistor T1 can be compensated, so as to prevent the threshold voltage of the driving transistor T1 from affecting the brightness of the light emitting device.
其中，阈值补偿单元1514包括第三晶体管T3和存储电容C1。存储电容C1分别与第二电源电压端VDD、驱动晶体管T1的栅极连接。第三晶体管T3的栅极与第一栅极信号线连接，第三晶体管T3的第一极与驱动晶体管T1的第二极连接，第三晶体管T3的第二极与驱动晶体管T1的栅极连接。第三晶体管T3用于根据第二栅极信号端Scan(n)的信号控制驱动晶体管T1的栅极和第二极之间的信号传输路径的通断。具体地，以第三晶体管T3为P型晶体管为例，当第二栅极信号端Scan(n)的信号为低电平时，进行阈值补偿并对存储电容C1进行充电，从而将补偿结果存储在存储电容C1中。Wherein, the threshold compensation unit 1514 includes a third transistor T3 and a storage capacitor C1. The storage capacitor C1 is connected to the second power supply voltage terminal VDD and the gate of the driving transistor T1 respectively. The gate of the third transistor T3 is connected to the first gate signal line, the first pole of the third transistor T3 is connected to the second pole of the driving transistor T1, and the second pole of the third transistor T3 is connected to the gate of the driving transistor T1 . The third transistor T3 is used for controlling the on-off of the signal transmission path between the gate of the driving transistor T1 and the second electrode according to the signal of the second gate signal terminal Scan(n). Specifically, taking the third transistor T3 as a P-type transistor as an example, when the signal of the second gate signal terminal Scan(n) is at a low level, threshold compensation is performed and the storage capacitor C1 is charged, so that the compensation result is stored in storage capacitor C1.
可选地，第三晶体管T3可以为双栅极晶体管。在本实施例中，采用双栅极晶体管结构的第三晶体管T3，可以有效改善阈值补偿的可靠性，从而改善显示设备的显示质量。可以理解的是，第一像素子电路中的其他晶体管也可以为双栅极晶体管，以进一步提升显示质量。Optionally, the third transistor T3 may be a double-gate transistor. In this embodiment, the third transistor T3 with a double-gate transistor structure can effectively improve the reliability of threshold compensation, thereby improving the display quality of the display device. It can be understood that other transistors in the first pixel sub-circuit may also be double-gate transistors to further improve display quality.
发光控制单元1515包括第五晶体管T5和第六晶体管T6。其中，第五晶体管T5的栅极用于接收发光控制信号，第五晶体管T5的第一极与第二电源电压端连接，第五晶体管T5的第二极与驱动晶体管T1的第一极连接，第五晶体管T5用于根据发光控制信号EM控制第二电源电压端和驱动晶体管T1的第一极之间的信号传输路径的通断。第六晶体管T6的栅极用于接收发光控制信号EM，第六晶体管T6的第一极与驱动晶体管T1的第二极连接，第六晶体管T6的第二极发光器件的阳极连接，第六晶体管T6用于根据发光控制信号EM控制驱动晶体管T1的第二极和发光器件的阳极之间的信号传输路径的通断。示例性地，以第五晶体管T5和第六晶体管T6均为P型晶体管为例进行说明，当发光控制信号EM为低电平时，第五晶体管T5和第六晶体管T6导通，将驱动晶体管T1的第一极的电压上拉至第二电源电压VDD，第一驱动晶体管T1的栅源电压差变化从而生成驱动电流并将驱动电流输出至发光器件，从而控制发光器件发光。The light emission control unit 1515 includes a fifth transistor T5 and a sixth transistor T6. Wherein, the gate of the fifth transistor T5 is used to receive the light-emitting control signal, the first pole of the fifth transistor T5 is connected to the second power supply voltage terminal, the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T1, The fifth transistor T5 is used for controlling the on-off of the signal transmission path between the second power supply voltage terminal and the first pole of the driving transistor T1 according to the light emission control signal EM. The gate of the sixth transistor T6 is used to receive the light emission control signal EM, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T1, the second pole of the sixth transistor T6 is connected to the anode of the light emitting device, and the sixth transistor T6 T6 is used for controlling the on-off of the signal transmission path between the second pole of the driving transistor T1 and the anode of the light-emitting device according to the light-emitting control signal EM. Exemplarily, the fifth transistor T5 and the sixth transistor T6 are both P-type transistors as an example for illustration. When the light emission control signal EM is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on to drive the transistor T1 The voltage of the first pole of the first driving transistor T1 is pulled up to the second power supply voltage VDD, and the gate-source voltage difference of the first driving transistor T1 changes to generate a driving current and output the driving current to the light-emitting device, thereby controlling the light-emitting device to emit light.
需要说明的是，本实施例中的各种晶体管不局限于前述实施例中的P型晶体管，还可以为N型晶体管等。晶体管的类型不同，其对应的驱动方式也可做适应性调整。另外，本实施例的第一像素子电路不局限于前述实施例中的7T1C第一像素子电路，即，第一像素子电路中也可以具有其他数量的晶体管，从而以较少数量的晶体管实现轻量级的显示设备，或者以较多数量的晶体管实现更加灵活的显示功能，例如，还是可以为3T1C、6T1C、6T2C等其他类型的驱动电路。It should be noted that various transistors in this embodiment are not limited to the P-type transistors in the foregoing embodiments, and may also be N-type transistors and the like. For different types of transistors, their corresponding driving methods can also be adaptively adjusted. In addition, the first pixel sub-circuit of this embodiment is not limited to the 7T1C first pixel sub-circuit in the foregoing embodiments, that is, the first pixel sub-circuit may also have other numbers of transistors, so that A light-weight display device, or a more flexible display function with a larger number of transistors, for example, can also be other types of driving circuits such as 3T1C, 6T1C, and 6T2C.
进一步地，图7实施例的第一像素子电路可以基于图5实施例所示的结构实现，且第一像素子电路的类型可以为低温多晶硅(Low Temperature Poly-silicon，LTPS)类型，即，第一像素子电路中的全部晶体管均为低温多晶硅薄膜晶体管。在一些实施例中，第一像素子电路中的部分晶体管可以为氧化物薄膜晶体管，相应地，第一像素子电路的类型为低温多晶氧化物(Low Temperature Poly-silicon Oxide，LTPO)类型。其中，氧化物薄膜晶体管具有更好的抑制漏电的性能，因此适用于作为开关晶体管，以实现更加可靠的开关性能。Further, the first pixel subcircuit in the embodiment of FIG. 7 can be implemented based on the structure shown in the embodiment in FIG. 5, and the type of the first pixel subcircuit can be a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) type, that is, All transistors in the first pixel sub-circuit are low temperature polysilicon thin film transistors. In some embodiments, some transistors in the first pixel sub-circuit may be oxide thin film transistors, and accordingly, the type of the first pixel sub-circuit is a low temperature poly-silicon oxide (Low Temperature Poly-silicon Oxide, LTPO) type. Among them, the oxide thin film transistor has a better performance of suppressing electric leakage, so it is suitable as a switching transistor to achieve more reliable switching performance.
图8为一实施例的显示模组的局部结构示意图之一，图9为图8实施例的显示模组的剖视示意图，在本实施例中，所述显示模组还包括栅极线410和多个第一金属化孔1121。其中，金属化孔是指孔的内壁上镀膜有导电材料的孔状结构，镀膜的导电材料可以是但不限于铜。需要说明的是，图8中的栅极线410和电路走线101的粗细不相同，但图8中的粗细差异仅用于清晰地标识出栅极线410和电路走线101，而不用于限定栅极线410和电路走线101的具体尺寸，即，栅极线410和电路走线101的尺寸可以相同。此外，第一金属化孔1121的位置与第二栅极层1101b中的初始化信号线等走线相错开，因此可以直接连接到位于第一栅极层1101a中的栅极线。参考图8，栅极线410沿显示模组的行方向延伸。栅极线410用于传输栅极信号，栅极线410分别与多个所述第一像素子电路的栅极信号端连接，栅极信号端包括图7中的Scan(n)和Scan(n-1)。参考图9，左侧连接至阳极1107的像素子电路为第一像素子电路，右侧未连接至发光器件的像素子电路为第二像素子电路，第二像素子电路中的所述电路走线101与所述栅极线设于同一所述子功能层，即第一栅极层1101a。各所述第一金属化孔1121分别沿所述显示模组的厚度方向贯穿所述像素定义层1106和所述平坦化层1114，所述第一金属化孔1121的一端与所述阴极层1109连接，所述第一金属化孔1121的另一端与所述电路走线101连接。在本实施例中，通过设置多个第一金属化孔1121，可以确保电路走线101与发光器件的阴极之间的连接可靠性，避免单一第一金属化孔1121导通不良的问题，并提高各发光器件的阴极之间的电压一致性。而且，通过将电路走线101与栅极线410设于同一子功能层，电路走线101无需单独占用一个子功能层，从而可以提供一种较为轻薄的显示模组。FIG. 8 is one of the partial structural schematic diagrams of a display module according to an embodiment. FIG. 9 is a schematic cross-sectional view of the display module according to the embodiment shown in FIG. 8 . In this embodiment, the display module further includes gate lines 410 and a plurality of first metallized holes 1121 . Wherein, the metallized hole refers to a hole-like structure in which a conductive material is plated on the inner wall of the hole, and the conductive material of the plated film may be but not limited to copper. It should be noted that the thickness of the gate line 410 and the circuit trace 101 in FIG. 8 are different, but the difference in thickness in FIG. Specific dimensions of the gate lines 410 and the circuit traces 101 are defined, that is, the dimensions of the gate lines 410 and the circuit traces 101 may be the same. In addition, the position of the first metallization hole 1121 is staggered from the initialization signal line in the second gate layer 1101b, so it can be directly connected to the gate line in the first gate layer 1101a. Referring to FIG. 8, the gate lines 410 extend along the row direction of the display module. The gate lines 410 are used to transmit gate signals, and the gate lines 410 are respectively connected to the gate signal terminals of a plurality of the first pixel sub-circuits, and the gate signal terminals include Scan(n) and Scan(n) in FIG. 7 . -1). Referring to FIG. 9, the pixel sub-circuit on the left side connected to the anode 1107 is the first pixel sub-circuit, and the pixel sub-circuit on the right side not connected to the light-emitting device is the second pixel sub-circuit, and the circuit in the second pixel sub-circuit The line 101 and the gate line are disposed in the same sub-functional layer, ie, the first gate layer 1101a. Each of the first metallization holes 1121 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the first metallization hole 1121 is connected to the cathode layer 1109 The other end of the first metallized hole 1121 is connected to the circuit trace 101 . In this embodiment, by providing a plurality of first metallized holes 1121, the connection reliability between the circuit trace 101 and the cathode of the light-emitting device can be ensured, the problem of poor conduction of a single first metallized hole 1121 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved. Moreover, by arranging the circuit traces 101 and the gate lines 410 on the same sub-functional layer, the circuit traces 101 do not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
进一步地，多个第一金属化孔1121可以在电路走线101的延伸方向上等距间隔排列，以提高电路走线101、第一金属化孔1121以及阴极共同构成的整体结构的阻抗分布均匀性，从而提高阴极上电压 分布的均匀性，进而提高显示模组的显示均匀性。Further, a plurality of first metallized holes 1121 may be arranged at equal intervals along the extending direction of the circuit trace 101, so as to improve the uniform impedance distribution of the overall structure composed of the circuit trace 101, the first metallized hole 1121 and the cathode. To improve the uniformity of the voltage distribution on the cathode, thereby improving the display uniformity of the display module.
在其中一个实施例中，所述第二像素子电路也被配置有栅极信号端，继续参考图8，电路走线101可以与栅极线410平行设置。即，电路走线101的延伸方向平行于显示模组的行方向，本实施例的第一方向可以理解为显示模组的行方向。而且，电路走线101与第二像素子电路的栅极信号端Scan(n)和Scan(n-1)连接。即，电路走线101的结构和连接关系均与栅极线410相同，因此，可以直接利用栅极线410的光罩制备电路走线101，从而降低设计难度和光罩的制备成本。进一步地，一条所述电路走线101设置在第二方向上相邻的两条所述栅极线410之间，且所述电路走线101与相邻的一条所述栅极线410之间的距离和所述电路走线101与相邻的另一条所述栅极线410之间的距离相等。基于上述设置方式，可以使栅极线410和电路走线101均匀排布，从而进一步抑制息屏mura的问题。In one of the embodiments, the second pixel sub-circuit is also configured with a gate signal terminal. Continuing to refer to FIG. 8 , the circuit trace 101 may be arranged parallel to the gate line 410 . That is, the extending direction of the circuit traces 101 is parallel to the row direction of the display module, and the first direction in this embodiment can be understood as the row direction of the display module. Moreover, the circuit trace 101 is connected to the gate signal terminals Scan(n) and Scan(n−1) of the second pixel sub-circuit. That is, the structure and connection relationship of the circuit traces 101 are the same as those of the gate lines 410 , therefore, the circuit traces 101 can be prepared directly using the mask of the gate lines 410 , thereby reducing design difficulty and manufacturing cost of the mask. Further, one circuit trace 101 is arranged between two adjacent gate lines 410 in the second direction, and between the circuit trace 101 and one adjacent gate line 410 The distance is equal to the distance between the circuit trace 101 and another adjacent gate line 410 . Based on the above arrangement, the gate lines 410 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura problem of the screen.
图10为一实施例的显示模组的局部结构示意图之二，图11为图10实施例的显示模组的剖视示意图，在本实施例中，所述显示模组还包括初始化信号线420和多个第二金属化孔1122。需要说明的是，图10中的初始化信号线420和电路走线101的粗细不相同，但图10中的粗细差异仅用于清晰地标识出初始化信号线420和电路走线101，而不用于限定初始化信号线420和电路走线101的具体尺寸，即，初始化信号线420和电路走线101的尺寸可以相同。参考图10，初始化信号线420沿显示模组的行方向延伸。初始化信号线420用于传输初始化信号，初始化信号可以用于对驱动晶体管的栅极进行初始化或用于对发光器件的阳极进行初始化，初始化信号线420分别与多个所述第一像素子电路的初始化信号端连接，初始化信号端包括图7中的Vinit。参考图11，左侧连接至阳极1107的像素子电路为第一像素子电路，右侧未连接至发光器件的像素子电路为第二像素子电路，第二像素子电路中的所述电路走线101与所述初始化信号线设于同一所述子功能层，即第二栅极层1101b。各所述第二金属化孔1122分别沿所述显示模组的厚度方向贯穿所述像素定义层1106和所述平坦化层1114，所述第二金属化孔1122的一端与所述阴极层1109连接，所述第二金属化孔1122的另一端与所述电路走线101连接。在本实施例中，通过设置多个第二金属化孔1122，可以确保电路走线101与发光器件的阴极之间的连接可靠性，避免单一第二金属化孔1122导通不良的问题，并提高各发光器件的阴极之间的电压一致性。而且，通过将电路走线101与初始信号线设于同一子功能层，电路走线101无需单独占用一个子功能层，从而可以提供一种较为轻薄的显示模组。FIG. 10 is the second schematic diagram of the partial structure of the display module of an embodiment, and FIG. 11 is a schematic cross-sectional view of the display module of the embodiment of FIG. 10 . In this embodiment, the display module further includes an initialization signal line 420 and a plurality of second metallized holes 1122 . It should be noted that the thickness of the initialization signal line 420 and the circuit trace 101 in FIG. 10 are different, but the difference in thickness in FIG. The specific dimensions of the initialization signal lines 420 and the circuit traces 101 are limited, that is, the dimensions of the initialization signal lines 420 and the circuit traces 101 may be the same. Referring to FIG. 10, the initialization signal line 420 extends along the row direction of the display module. The initialization signal line 420 is used to transmit an initialization signal, and the initialization signal can be used to initialize the gate of the driving transistor or to initialize the anode of the light emitting device, and the initialization signal line 420 is respectively connected to the plurality of first pixel sub-circuits. Initialize the connection of the signal terminal, the initialization signal terminal includes Vinit in Figure 7. Referring to FIG. 11 , the pixel subcircuit on the left side connected to the anode 1107 is the first pixel subcircuit, and the pixel subcircuit on the right side not connected to the light emitting device is the second pixel subcircuit, and the circuit in the second pixel subcircuit The line 101 and the initialization signal line are provided in the same sub-functional layer, ie, the second gate layer 1101b. Each second metallization hole 1122 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the second metallization hole 1122 is connected to the cathode layer 1109 The other end of the second metallized hole 1122 is connected to the circuit trace 101 . In this embodiment, by providing a plurality of second metallization holes 1122, the connection reliability between the circuit trace 101 and the cathode of the light emitting device can be ensured, the problem of poor conduction of a single second metallization hole 1122 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved. Moreover, by arranging the circuit wiring 101 and the initial signal line on the same sub-functional layer, the circuit wiring 101 does not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
进一步地，所述电路走线101与所述初始化信号线420平行设置，一条所述电路走线101设置在第二方向上相邻的两条所述初始化信号线420之间，且所述电路走线101与相邻的一条所述初始化信号线420之间的距离和所述电路走线101与相邻的另一条所述初始化信号线420之间的距离相等。基于上述设置方式，可以使初始化信号线420和电路走线101均匀排布，从而进一步抑制息屏mura的问题。Further, the circuit routing 101 is arranged in parallel with the initialization signal line 420, one circuit routing 101 is arranged between two initialization signal lines 420 adjacent in the second direction, and the circuit The distance between the trace 101 and the adjacent one of the initialization signal lines 420 is equal to the distance between the circuit trace 101 and the other adjacent initialization signal line 420 . Based on the above arrangement, the initialization signal lines 420 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura of the screen.
再进一步地，多个第二金属化孔1122可以在电路走线101的延伸方向上等距间隔排列，以提高电路走线101、第二金属化孔1122以及阴极共同构成的整体结构的阻抗分布均匀性，从而提高阴极上电压分布的均匀性，进而提高显示模组的显示均匀性。Furthermore, a plurality of second metallization holes 1122 can be arranged at equal intervals in the extending direction of the circuit trace 101, so as to improve the impedance distribution of the overall structure composed of the circuit trace 101, the second metallization hole 1122 and the cathode. Uniformity, thereby improving the uniformity of voltage distribution on the cathode, thereby improving the display uniformity of the display module.
为了便于说明，将连接至第一金属化孔1121的电路走线101称为第一走线，并将连接至第二金属化孔1122的电路走线101称为第二走线。在一些实施例中，显示模组可以既包括多条第一走线，也包括多条第二走线，以进一步降低阴极上的阻抗，提高阴极上电压分布的均匀性，进而提高显示模组的显示均匀性。For ease of description, the circuit trace 101 connected to the first metallized hole 1121 is called a first trace, and the circuit trace 101 connected to the second metallized hole 1122 is called a second trace. In some embodiments, the display module may include multiple first wires and multiple second wires to further reduce the impedance on the cathode, improve the uniformity of the voltage distribution on the cathode, and further improve the display module. display uniformity.
图12为一实施例的显示模组的局部结构示意图之三，图13为图12实施例的显示模组的剖视示意图，所述显示模组还包括数据信号线430和多个第三金属化孔1123。需要说明的是，图12中的数据信号线430和电路走线101的粗细不相同，但图12中的粗细差异仅用于清晰地标识出数据信号线430和电路走线101，而不用于限定数据信号线430和电路走线101的具体尺寸，即，数据信号线430和电路走线101的尺寸可以相同。参考图12，数据信号线430沿显示模组的列方向延伸。数据信号线430用于传输数据信号，数据信号用于控制发光器件的亮度，数据信号线430分别与多个所述第一像素子电路的数据信号端连接，数据信号端包括图7中的Data。参考图13，左侧连接至阳极1107的像素子电路为第一像素子电路，右侧未连接至发光器件的像素子电路为第二像素子电路，第二像素子电路中的电路走线101与所述数据信号线设于同一所述子功能层，即源漏极层。各所述第三金属化孔1123分别沿所述显示模组的厚度方向贯穿所述像素定义层1106和所述平坦化层1114，所述第三金属化孔1123的一端与所述阴极层1109连接，所述第三金属化孔1123的另一端与位于所述像素电路层中的所述电路走线101连接。在本实施例中，通过设置多个第三金属化孔1123，可以确保电路走线101与发光器件的阴极之间的连接可靠性，避免单一第三金属化孔1123导通不良的问题，并提高各发光器件的阴极之间的电压一致性。而且，通过将电路走线101与数据信号线430设于同一子功能层，电路走线101无需单独占用一个子功能层，从而可以提供一种较为轻薄的显示模组。进一步地，多个第三金属化孔1123可以在电路走线101的延伸方向上等距间隔排列，以提高电路走线101、第三金属化孔1123以及阴极共同构 成的整体结构的阻抗分布均匀性，从而提高阴极上电压分布的均匀性，进而提高显示模组的显示均匀性。Figure 12 is the third schematic diagram of the partial structure of the display module of an embodiment, and Figure 13 is a schematic cross-sectional view of the display module of the embodiment of Figure 12, the display module also includes data signal lines 430 and a plurality of third metal Blowhole 1123. It should be noted that the thickness of the data signal line 430 and the circuit trace 101 in FIG. 12 are different, but the difference in thickness in FIG. The specific dimensions of the data signal line 430 and the circuit trace 101 are limited, that is, the dimensions of the data signal line 430 and the circuit trace 101 may be the same. Referring to FIG. 12, the data signal lines 430 extend along the column direction of the display module. The data signal line 430 is used to transmit the data signal, and the data signal is used to control the brightness of the light-emitting device. The data signal line 430 is respectively connected to the data signal terminals of a plurality of the first pixel sub-circuits, and the data signal terminal includes the Data in FIG. 7 . Referring to FIG. 13 , the pixel subcircuit on the left side connected to the anode 1107 is the first pixel subcircuit, and the pixel subcircuit on the right side not connected to the light-emitting device is the second pixel subcircuit, and the circuit trace 101 in the second pixel subcircuit The same sub-functional layer as the data signal line, that is, the source-drain layer. Each of the third metallization holes 1123 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the third metallization hole 1123 is connected to the cathode layer 1109 The other end of the third metallized hole 1123 is connected to the circuit trace 101 in the pixel circuit layer. In this embodiment, by providing a plurality of third metallized holes 1123, the connection reliability between the circuit trace 101 and the cathode of the light emitting device can be ensured, the problem of poor conduction of a single third metallized hole 1123 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved. Moreover, by arranging the circuit traces 101 and the data signal lines 430 on the same sub-functional layer, the circuit traces 101 do not need to occupy a separate sub-functional layer, thereby providing a thinner display module. Further, a plurality of third metallization holes 1123 may be arranged at equal intervals along the extending direction of the circuit traces 101, so as to improve the uniform impedance distribution of the overall structure composed of the circuit traces 101, the third metallization holes 1123 and the cathode. To improve the uniformity of the voltage distribution on the cathode, thereby improving the display uniformity of the display module.
在其中一个实施例中，所述第二像素子电路也被配置有数据信号端，电路走线101可以与数据信号线430平行设置。即，电路走线101的延伸方向平行于显示模组的列方向，本实施例的第一方向可以理解为显示模组的列方向。而且，电路走线101与第二像素子电路的数据信号端Data连接。即，电路走线101的结构和连接关系均与数据信号线430相同，因此，可以直接利用数据信号线430的光罩制备电路走线101，从而降低设计难度和光罩的制备成本。进一步地，一条所述电路走线101设置在第一方向上相邻的两条所述数据信号线430之间，且所述电路走线101与相邻的一条所述数据信号线430之间的距离和所述电路走线101与相邻的另一条所述数据信号线430之间的距离相等。基于上述设置方式，可以使数据信号线430和电路走线101均匀排布，从而进一步抑制息屏mura的问题。In one of the embodiments, the second pixel sub-circuit is also configured with a data signal terminal, and the circuit trace 101 may be arranged in parallel with the data signal line 430 . That is, the extending direction of the circuit traces 101 is parallel to the column direction of the display module, and the first direction in this embodiment can be understood as the column direction of the display module. Moreover, the circuit wiring 101 is connected to the data signal terminal Data of the second pixel sub-circuit. That is, the structure and connection relationship of the circuit traces 101 are the same as those of the data signal lines 430 , therefore, the circuit traces 101 can be prepared directly using the photomask of the data signal lines 430 , thereby reducing design difficulty and manufacturing cost of the photomask. Further, one circuit trace 101 is arranged between two adjacent data signal lines 430 in the first direction, and between the circuit trace 101 and one adjacent data signal line 430 The distance is equal to the distance between the circuit trace 101 and another adjacent data signal line 430 . Based on the above arrangement, the data signal lines 430 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura problem of the screen.
在其中一个实施例中，显示模组既包括多条第一走线，也包括多条第三走线。具体地，多条第一走线沿显示模组的行方向延伸，多条第三走线沿显示模组的列方向延伸，且多条第一走线和多条第三走线均与发光器件的共阴极连接，从而形成并联的网状走线。示例性地，若采用Mg/Ag合金的成分制作共阴极结构的阴极，阴极透过率为50％，则阴极的方阻为12Ω/sq-20Ω/sq；若采用Ti/Al/Ti或者Mo金属制作第一走线和第三走线，并将第一走线和第三走线分别与阴极连接，则并联后上述结构的整体方阻为0.2Ω/sq-0.6Ω/sq，从而大大提高了阴极上的电压均匀性，进而提高了显示模组的显示均匀性，尤其是低灰阶下的显示均匀性。在本实施例中，通过上述结构，能够极大程度上地降低阴极上的阻抗，提高阴极上电压分布的均匀性，进而提高显示模组的显示均匀性。In one embodiment, the display module includes not only a plurality of first wires, but also a plurality of third wires. Specifically, the multiple first traces extend along the row direction of the display module, the multiple third traces extend along the column direction of the display module, and both the multiple first traces and the multiple third traces are connected to the light emitting The common cathode of the device is connected to form a parallel mesh trace. Exemplarily, if Mg/Ag alloy is used to make a cathode with a common cathode structure, and the cathode transmittance is 50%, the square resistance of the cathode is 12Ω/sq-20Ω/sq; if Ti/Al/Ti or Mo The first wire and the third wire are made of metal, and the first wire and the third wire are respectively connected to the cathode, then the overall square resistance of the above structure after parallel connection is 0.2Ω/sq-0.6Ω/sq, thus greatly The voltage uniformity on the cathode is improved, thereby improving the display uniformity of the display module, especially the display uniformity under low grayscale. In this embodiment, through the above structure, the impedance on the cathode can be greatly reduced, the uniformity of the voltage distribution on the cathode can be improved, and the display uniformity of the display module can be further improved.
图14为一实施例的显示模组的简化剖视示意图之一，参考图14，在其中一个实施例中，显示模组还包括栅极驱动电路300。本实施例的第一方向为显示模组的行方向，第三方向为显示模组的厚度方向。栅极驱动电路300与所述像素电路阵列100在所述第一方向上相邻设置，且所述栅极驱动电路300沿第三方向在虚拟平面600上的投影与所述发光器件阵列200沿第三方向在虚拟平面600上的投影部分重合，所述第三方向为所述显示模组的厚度方向，所述虚拟平面600为垂直于所述第三方向的平面，需要说明的是，虚拟平面600并不是显示模组中实际存在的特征，而是为了方便阐述显示模组的特征而引入的参考平面。在本实施例中，通过将发光器件阵列200与栅极驱动电路300在第三方向上部分重叠设置，可以提供更窄边框的显示模组。FIG. 14 is one of the simplified cross-sectional diagrams of a display module according to an embodiment. Referring to FIG. 14 , in one embodiment, the display module further includes a gate driving circuit 300 . In this embodiment, the first direction is the row direction of the display module, and the third direction is the thickness direction of the display module. The gate drive circuit 300 is arranged adjacent to the pixel circuit array 100 in the first direction, and the projection of the gate drive circuit 300 on the virtual plane 600 along the third direction is along the line of the light emitting device array 200 The projections of the third direction on the virtual plane 600 partially overlap, the third direction is the thickness direction of the display module, and the virtual plane 600 is a plane perpendicular to the third direction. It should be noted that the virtual The plane 600 is not a feature that actually exists in the display module, but a reference plane introduced for the convenience of explaining the features of the display module. In this embodiment, by partially overlapping the light emitting device array 200 and the gate driving circuit 300 in the third direction, a display module with a narrower border can be provided.
图15为一实施例的显示模组的简化剖视示意图之二，参考图15，在其中一个实施例中，显示模组还包括扇出走线组500。本实施例的第一方向为显示模组的列方向，所述第三方向为所述显示模组的厚度方向。扇出走线组500与所述像素电路阵列100在第二方向上相邻设置，且所述扇出走线组500沿第三方向在虚拟平面600上的投影与所述发光器件阵列200沿第三方向在虚拟平面600上的投影部分重合，所述虚拟平面600为垂直于所述第三方向的平面。在本实施例中，位于非显示区的显示驱动单元通过扇出走线组500与像素电路阵列100连接，以向像素电路阵列100传输控制信号。其中，显示驱动单元可以为显示驱动芯片(Display Driver IC，DDIC)。在本实施例中，通过将发光器件阵列200与扇出走线组500在第三方向上部分重叠设置，可以提供更窄边框的显示模组。FIG. 15 is a second simplified cross-sectional schematic diagram of a display module according to an embodiment. Referring to FIG. 15 , in one embodiment, the display module further includes a fan-out wiring group 500 . In this embodiment, the first direction is the column direction of the display module, and the third direction is the thickness direction of the display module. The fan-out routing group 500 is arranged adjacent to the pixel circuit array 100 in the second direction, and the projection of the fan-out routing group 500 on the virtual plane 600 along the third direction is the same as that of the light emitting device array 200 along the third direction. The projections of the directions on a virtual plane 600, which is a plane perpendicular to the third direction, partially coincide. In this embodiment, the display driving unit located in the non-display area is connected to the pixel circuit array 100 through the fan-out wire group 500 to transmit control signals to the pixel circuit array 100 . Wherein, the display driving unit may be a display driver chip (Display Driver IC, DDIC). In this embodiment, by partially overlapping the light-emitting device array 200 and the fan-out wire group 500 in the third direction, a display module with a narrower border can be provided.
图16为一实施例的像素电路阵列的结构示意图之二，参考图16，在其中一个实施例中，所述显示模组还设有第二子阵列区120，所述第二子阵列区120与第一子阵列区110在所述第一方向上相邻，所述第二子阵列区120中设有多个所述第一像素电路111。图17为基于图16实施例的像素电路阵列形成的显示模组的结构示意图，参考图17，在本实施例中，通过在靠近显示模组边缘的区域设置不包含第二像素子电路的第二子阵列区120，可以对应设置更多数量的发光器件，从而增大发光器件阵列200与其他***电路(例如栅极驱动电路300)之间的重叠面积。其中，重叠面积即是指在第三方向上的重叠面积，即发光器件阵列200在垂直于第三方向的虚拟平面600上的投影与其他***电路在垂直于第三方向的虚拟平面600上的投影之间的重叠面积。FIG. 16 is the second structural schematic diagram of a pixel circuit array in an embodiment. Referring to FIG. Adjacent to the first sub-array area 110 in the first direction, a plurality of the first pixel circuits 111 are disposed in the second sub-array area 120 . FIG. 17 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 16. Referring to FIG. In the second sub-array region 120 , a larger number of light emitting devices can be arranged correspondingly, thereby increasing the overlapping area between the light emitting device array 200 and other peripheral circuits (such as the gate driving circuit 300 ). Wherein, the overlapping area refers to the overlapping area in the third direction, that is, the projection of the light emitting device array 200 on the virtual plane 600 perpendicular to the third direction and the projection of other peripheral circuits on the virtual plane 600 perpendicular to the third direction the overlapping area between.
可以理解的是，用户在使用显示设备时，对中间区域的显示均匀性的要求大于对边缘区域的要求，因此，本实施例在中间区域采用第一子阵列区110结构，并在边缘区域采用第二子阵列区120结构，既可以实现较大程度上的缩窄显示边框的目的，还可以减少对用户的使用体验的影响。示例性地，用一层驱动走线时，左右边框处可争取200um至400um的空间，以提供更窄边框的显示模组。需要说明的是，虽然图16实施例中的第二子阵列区120仅示出了8列第一像素子电路，但第二子阵列区120实际上可以根据需要设置更多列的第一像素子电路，以进一步优化窄边框性能。It can be understood that when a user uses a display device, the requirement for display uniformity in the middle area is greater than that in the edge area. Therefore, in this embodiment, the first sub-array region 110 structure is adopted in the middle area, and The structure of the second sub-array area 120 can not only achieve the purpose of narrowing the display frame to a large extent, but also reduce the impact on user experience. For example, when one layer is used to drive the wiring, a space of 200um to 400um can be obtained at the left and right borders to provide a display module with a narrower border. It should be noted that although the second sub-array area 120 in the embodiment of FIG. 16 only shows 8 columns of first pixel sub-circuits, the second sub-array area 120 can actually have more columns of first pixels as required. sub-circuits to further optimize narrow bezel performance.
继续参考图16，在其中一个实施例中，所述第二子阵列区120的一侧边缘与所述第一子阵列区110的第一侧边缘在第二方向上对齐，所述第二方向垂直于所述第一方向且垂直于所述显示模组的厚度方向。可以理解的是，本实施例对第一子阵列区110的各侧边缘的定义方式与前述实施例中对第一像素电路111的侧边缘的定义方式相同，此处不再进行赘述。在本实施例中，通过上述方式，可以在不影响显示功能的基础上，降低第一像素子电路的设计难度。Continuing to refer to FIG. 16, in one embodiment, one side edge of the second sub-array region 120 is aligned with the first side edge of the first sub-array region 110 in a second direction, and the second direction perpendicular to the first direction and perpendicular to the thickness direction of the display module. It can be understood that, the method of defining the side edges of the first sub-array region 110 in this embodiment is the same as that of the side edges of the first pixel circuit 111 in the foregoing embodiments, and details are not repeated here. In this embodiment, through the above method, the design difficulty of the first pixel sub-circuit can be reduced without affecting the display function.
图18为一实施例的像素电路阵列的结构示意图之三，参考图18，在其中一个实施例中，所述显示模组还设有第三子阵列区130，所述第三子阵列区130与第一子阵列区110在所述第二方向上相邻，其中，第三子阵列区130可以理解为相对靠近于显示模组的中心，同时第一子阵列区110相对靠近于显示模组的边框。所述第三子阵列区130中设有多个重复单元和多个第三像素电路131，所述重复单元包括在第一方向上相邻的一个所述第一像素电路111和一个所述第二像素电路112，且在所述第二方向上任意两个相邻的所述重复单元之间设有一个所述第三像素电路131，所述第三像素电路131包括沿所述第一方向排列的多个所述第二像素子电路。在本实施中，基于包括第一子阵列区110和第三子阵列区130的像素电路阵列，可以在显示模组中同时设置多条第一走线、多条第二走线和多条第三走线。具体地，多条第一走线和多条第二走线均沿显示模组的行方向延伸，且第一走线和第二走线在虚拟平面上的投影均位于第三像素电路131在虚拟平面上的投影中。多条第三走线沿显示模组的列方向延伸，且第二走线在虚拟平面上的投影位于第二像素电路在虚拟平面上的投影中，以使多条第一走线和多条第三走线形成网状结构。其中，第一走线、第二走线和第三走线的具体设置方式可参考前述实施例，此处不再进行赘述。FIG. 18 is the third schematic diagram of the structure of the pixel circuit array of an embodiment. Referring to FIG. Adjacent to the first sub-array area 110 in the second direction, wherein the third sub-array area 130 can be understood as being relatively close to the center of the display module, while the first sub-array area 110 is relatively close to the display module border. A plurality of repeating units and a plurality of third pixel circuits 131 are provided in the third sub-array area 130, and the repeating units include one first pixel circuit 111 and one second pixel circuit 111 adjacent in the first direction. Two pixel circuits 112, and one third pixel circuit 131 is provided between any two adjacent repeating units in the second direction, and the third pixel circuit 131 includes A plurality of the second pixel sub-circuits arranged. In this implementation, based on the pixel circuit array including the first sub-array region 110 and the third sub-array region 130, a plurality of first wiring lines, a plurality of second wiring lines and a plurality of second wiring lines can be simultaneously set in the display module. Three lines. Specifically, the plurality of first routing lines and the plurality of second routing lines extend along the row direction of the display module, and the projections of the first routing lines and the second routing lines on the virtual plane are located on the third pixel circuit 131. In projection on a virtual plane. A plurality of third wires extend along the column direction of the display module, and the projection of the second wires on the virtual plane is located in the projection of the second pixel circuit on the virtual plane, so that the multiple first wires and the multiple The third routing forms a mesh structure. Wherein, the specific setting manners of the first routing, the second routing and the third routing can refer to the above-mentioned embodiments, which will not be repeated here.
图19为基于图18实施例的像素电路阵列形成的显示模组的结构示意图，结合参考图18和图19，在本实施例中，第三子阵列区130与所述第一子阵列区110在第二方向上相邻设置，所述第二方向垂直于所述第一方向且垂直于所述显示模组的厚度方向。所述第三子阵列区130包括多个所述第一重复单元113和多个第三像素电路131。其中，所述第三像素电路131包括多个第三像素子电路，所述第三像素子电路的结构可以与所述第一像素子电路的结构相同，所述第三像素子电路不与所述发光器件电连接。通过设置与第一像素子电路相同的第三像素子电路，能够保证像素电路阵列100内部的各像素子电路的结构和大小一致，避免由于电路走线101密度不一致引起的息屏Mura的问题。而且，像素子电路的尺寸结构一致也有利于工艺制程的稳定性，保证薄膜晶体管的电性一致，保证显示的均匀性。FIG. 19 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 18. Referring to FIG. 18 and FIG. adjacently arranged in the second direction, the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module. The third sub-array area 130 includes a plurality of first repeating units 113 and a plurality of third pixel circuits 131 . Wherein, the third pixel circuit 131 includes a plurality of third pixel sub-circuits, the structure of the third pixel sub-circuit may be the same as that of the first pixel sub-circuit, and the third pixel sub-circuit is not the same as the first pixel sub-circuit. The light emitting device is electrically connected. By setting the third pixel sub-circuit identical to the first pixel sub-circuit, it is possible to ensure that the structure and size of each pixel sub-circuit inside the pixel circuit array 100 are consistent, and to avoid the mura problem caused by the inconsistent density of circuit traces 101 . Moreover, the consistent size and structure of the pixel sub-circuits is also conducive to the stability of the manufacturing process, ensuring the consistency of the electrical properties of the thin film transistors and the uniformity of the display.
在其中一个实施例中，所述第三子阵列区130的一侧边缘与所述第一子阵列区110的第二侧边缘在第一方向上对齐，所述第二侧边缘连接第一侧边缘，且所述第三像素电路131中的多个所述第三像素子电路沿所述第一方向排列。所述第一重复单元113与所述第三像素电路131在第二方向上的尺寸之和与所述发光重复单元210在第二方向上的尺寸之间的差值在第四预设范围内。其中，第四预设范围例如可以为0um至10um。通过上述设置方式，可以有效提供发光器件与对应的第一像素子电路之间的对应性，从而避免驱动走线过长，进而提升显示均匀性。In one embodiment, one side edge of the third sub-array region 130 is aligned with the second side edge of the first sub-array region 110 in the first direction, and the second side edge is connected to the first side edge, and the plurality of third pixel sub-circuits in the third pixel circuit 131 are arranged along the first direction. The difference between the sum of the sizes of the first repeating unit 113 and the third pixel circuit 131 in the second direction and the size of the light emitting repeating unit 210 in the second direction is within a fourth preset range . Wherein, the fourth preset range may be, for example, 0um to 10um. Through the above arrangement, the correspondence between the light-emitting device and the corresponding first pixel sub-circuit can be effectively provided, so as to avoid excessively long driving lines, thereby improving display uniformity.
图20为一实施例的像素电路阵列的结构示意图之四，参考图20，在本实施例中，所述像素电路阵列100设有第一子阵列区110、第二子阵列区120、第三子阵列区130和第四子阵列区140。本实施例的第二子阵列区120和第三子阵列区130的设置方式可以参考前述实施例，此处不再进行赘述。所述第四子阵列区140与第三子阵列区130在所述第一方向上相邻，且与所述第二子阵列区120在所述第二方向上相邻。所述第四子阵列区140中设有多个所述第一像素电路111和多个第四像素电路141，且在所述第二方向上任意两个相邻的所述第一像素电路111之间设有一个所述第四像素电路141，所述第四像素电路141包括沿所述第一方向排列的多个所述第二像素子电路，所述第四像素电路141中所述第二像素子电路的数量小于所述第三像素电路131中所述第二像素子电路的数量。所述第四子阵列区140的第三侧边缘与所述第一子阵列区110的第一侧边缘在所述第二方向上对齐，且第四子阵列区140的第四侧边缘与所述第一子阵列区110的第二侧边缘在所述第一方向上对齐，所述第三侧边缘连接所述第四侧边缘。图21为基于图20实施例的像素电路阵列形成的显示模组的结构示意图，参考图21，在本实施例中，通过设置第四子阵列区140，可以相较第三子阵列区130设置更多数量的发光器件，从而增大发光器件阵列200与其他***电路(例如栅极驱动电路300)在第三方向上的重叠面积。FIG. 20 is the fourth schematic diagram of the structure of the pixel circuit array in an embodiment. Referring to FIG. The sub-array area 130 and the fourth sub-array area 140 . For the arrangement of the second sub-array region 120 and the third sub-array region 130 in this embodiment, reference may be made to the foregoing embodiments, and details are not repeated here. The fourth sub-array area 140 is adjacent to the third sub-array area 130 in the first direction, and is adjacent to the second sub-array area 120 in the second direction. A plurality of the first pixel circuits 111 and a plurality of fourth pixel circuits 141 are arranged in the fourth sub-array area 140, and any two adjacent first pixel circuits 111 in the second direction There is a fourth pixel circuit 141 between them, and the fourth pixel circuit 141 includes a plurality of second pixel sub-circuits arranged along the first direction, and the fourth pixel circuit 141 in the fourth pixel circuit 141 The number of the second pixel sub-circuits is less than the number of the second pixel sub-circuits in the third pixel circuit 131 . The third side edge of the fourth sub-array region 140 is aligned with the first side edge of the first sub-array region 110 in the second direction, and the fourth side edge of the fourth sub-array region 140 is aligned with the first side edge of the first sub-array region 110 in the second direction. The second side edges of the first sub-array region 110 are aligned in the first direction, and the third side edges are connected to the fourth side edges. FIG. 21 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 20. Referring to FIG. A larger number of light emitting devices increases the overlapping area of the light emitting device array 200 and other peripheral circuits (such as the gate driving circuit 300 ) in the third direction.
本申请还提供了一种显示设备，包括：如上述的显示模组。在本实施例中，基于上述显示模组，能够缩窄显示设备的边框，并优化显示设备的显示均匀性，从而提高显示设备的综合显示性能。The present application also provides a display device, including: the above-mentioned display module. In this embodiment, based on the above display module, the frame of the display device can be narrowed, and the display uniformity of the display device can be optimized, thereby improving the comprehensive display performance of the display device.
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.
以上所述实施例仅表达了本申请实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请实施例构思的前提下，还可以做出若干变形和改进，这些都属于本申请实施例的保护范围。因此，本申请实施例专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the scope of protection of the embodiment patent of this application should be based on the appended claims.

Claims (20)

  1. 一种显示模组，其中包括：A display module comprising:
    像素电路阵列，包括多个第一像素子电路、多个第二像素子电路和电路走线，各所述第二像素子电路分别位于在第一方向上相邻的两个所述第一像素子电路之间，所述第一方向垂直于所述显示模组的厚度方向；A pixel circuit array, including a plurality of first pixel sub-circuits, a plurality of second pixel sub-circuits and circuit wiring, each of the second pixel sub-circuits is respectively located in two adjacent first pixels in the first direction Between the sub-circuits, the first direction is perpendicular to the thickness direction of the display module;
    发光器件阵列，所述发光器件阵列在第一方向上的尺寸大于所述像素电路阵列在第一方向上的尺寸，所述发光器件阵列包括多个发光器件，所述发光器件包括阴极和阳极，多个所述发光器件的阳极分别与多个所述第一像素子电路一一对应地连接；A light emitting device array, the size of the light emitting device array in the first direction is larger than the size of the pixel circuit array in the first direction, the light emitting device array includes a plurality of light emitting devices, the light emitting device includes a cathode and an anode, The anodes of the plurality of light-emitting devices are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence;
    其中，所述电路走线与多个所述发光器件的阴极连接。Wherein, the circuit wiring is connected to the cathodes of a plurality of the light emitting devices.
  2. 根据权利要求1所述的显示模组，其中所述像素电路阵列包括多条所述电路走线，且多条所述电路走线互相平行。The display module according to claim 1, wherein the pixel circuit array includes a plurality of circuit traces, and the plurality of circuit traces are parallel to each other.
  3. 根据权利要求2所述的显示模组，其中多条所述电路走线等距间隔排列。The display module according to claim 2, wherein a plurality of said circuit traces are arranged at equal intervals.
  4. 根据权利要求2所述的显示模组，其中多条所述电路走线均沿第二方向延伸，所述第二方向垂直于所述第一方向、且垂直于所述显示模组的厚度方向。The display module according to claim 2, wherein a plurality of the circuit traces all extend along a second direction, the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module .
  5. 根据权利要求2所述的显示模组，其中所述电路走线在虚拟平面上的投影位于所述第二像素子电路在所述虚拟平面上的投影中，所述虚拟平面垂直于所述显示模组的厚度方向。The display module according to claim 2, wherein the projection of the circuit trace on the virtual plane is located in the projection of the second pixel sub-circuit on the virtual plane, and the virtual plane is perpendicular to the display The thickness direction of the module.
  6. 根据权利要求1至5任一项所述的显示模组，其中所述显示模组包括：The display module according to any one of claims 1 to 5, wherein the display module comprises:
    像素定义层，设有互相隔离的多个像素开口；The pixel definition layer is provided with a plurality of pixel openings isolated from each other;
    阳极层，分别设于多个所述像素开口中；an anode layer, respectively disposed in a plurality of the pixel openings;
    发光材料层，分别设于多个所述像素开口中，且设于所述阳极层的表面；a luminescent material layer, respectively disposed in the plurality of pixel openings, and disposed on the surface of the anode layer;
    阴极层，覆盖所述发光材料层和所述像素定义层的表面；a cathode layer covering the surfaces of the luminescent material layer and the pixel definition layer;
    其中，位于同一所述像素开口中的所述阳极层、所述发光材料层和所述阴极层构成一个所述发光器件。Wherein, the anode layer, the light-emitting material layer and the cathode layer located in the same pixel opening constitute one light-emitting device.
  7. 根据权利要求6所述的显示模组，其中所述显示模组还包括：The display module according to claim 6, wherein the display module further comprises:
    像素电路层，用于设置所述像素电路阵列，所述像素电路层包括多个子功能层；A pixel circuit layer, used to set the pixel circuit array, the pixel circuit layer includes a plurality of sub-functional layers;
    平坦化层，设于所述像素电路层和所述像素定义层之间；a planarization layer disposed between the pixel circuit layer and the pixel definition layer;
    栅极线，分别与多个所述第一像素子电路的栅极信号端连接，所述电路走线与所述栅极线设于同一所述子功能层；The gate lines are respectively connected to the gate signal terminals of a plurality of the first pixel sub-circuits, and the circuit traces and the gate lines are arranged in the same sub-functional layer;
    多个第一金属化孔，各所述第一金属化孔分别沿所述显示模组的厚度方向贯穿所述像素定义层和所述平坦化层，所述第一金属化孔的一端与所述阴极层连接，所述第一金属化孔的另一端与所述电路走线连接。A plurality of first metallized holes, each of the first metallized holes penetrates through the pixel definition layer and the planarization layer along the thickness direction of the display module, one end of the first metallized hole is connected to the The cathode layer is connected, and the other end of the first metallized hole is connected to the circuit trace.
  8. 根据权利要求7所述的显示模组，其中所述电路走线与所述栅极线平行设置，一条所述电路走线设置在第二方向上相邻的两条所述栅极线之间，且所述电路走线与相邻的一条所述栅极线之间的距离和所述电路走线与相邻的另一条所述栅极线之间的距离相等。The display module according to claim 7, wherein the circuit traces are arranged parallel to the gate lines, and one of the circuit traces is arranged between two adjacent gate lines in the second direction , and the distance between the circuit trace and one adjacent gate line is equal to the distance between the circuit trace and another adjacent gate line.
  9. 根据权利要求6所述的显示模组，其中所述显示模组还包括：The display module according to claim 6, wherein the display module further comprises:
    像素电路层，用于设置所述像素电路阵列，所述像素电路层包括多个子功能层；A pixel circuit layer, used to set the pixel circuit array, the pixel circuit layer includes a plurality of sub-functional layers;
    平坦化层，设于所述像素电路层和所述像素定义层之间；a planarization layer disposed between the pixel circuit layer and the pixel definition layer;
    初始化信号线，分别与多个所述第一像素子电路的初始化信号端连接，所述电路走线与所述初始化信号线设于同一所述子功能层；The initialization signal lines are respectively connected to the initialization signal terminals of a plurality of the first pixel sub-circuits, and the circuit routing and the initialization signal lines are arranged in the same sub-functional layer;
    多个第二金属化孔，各所述第二金属化孔分别沿所述显示模组的厚度方向贯穿所述像素定义层和所述平坦化层，所述第二金属化孔的一端与所述阴极层连接，所述第二金属化孔的另一端与所述电路走线连接。A plurality of second metallization holes, each of the second metallization holes penetrates the pixel definition layer and the planarization layer along the thickness direction of the display module, one end of the second metallization hole is connected to the The cathode layer is connected, and the other end of the second metallized hole is connected to the circuit trace.
  10. 根据权利要求9所述的显示模组，其中所述电路走线与所述初始化信号线平行设置，一条所述电路走线设置在第二方向上相邻的两条所述初始化信号线之间，且所述电路走线与相邻的一条所述初始化信号线之间的距离和所述电路走线与相邻的另一条所述初始化信号线之间的距离相等。The display module according to claim 9, wherein the circuit traces are arranged parallel to the initialization signal lines, and one of the circuit traces is arranged between two adjacent initialization signal lines in the second direction , and the distance between the circuit trace and one adjacent initialization signal line is equal to the distance between the circuit trace and another adjacent initialization signal line.
  11. 根据权利要求6所述的显示模组，其中所述显示模组还包括：The display module according to claim 6, wherein the display module further comprises:
    像素电路层，用于设置所述像素电路阵列，所述像素电路层包括多个子功能层；A pixel circuit layer, used to set the pixel circuit array, the pixel circuit layer includes a plurality of sub-functional layers;
    平坦化层，设于所述像素电路层和所述像素定义层之间；a planarization layer disposed between the pixel circuit layer and the pixel definition layer;
    数据信号线，分别与多个所述第一像素子电路的数据信号端连接，所述电路走线与所述数据信号线设于同一所述子功能层；The data signal lines are respectively connected to the data signal terminals of a plurality of the first pixel sub-circuits, and the circuit traces and the data signal lines are arranged in the same sub-functional layer;
    多个第三金属化孔，各所述第三金属化孔分别沿所述显示模组的厚度方向贯穿所述像素定义层和所述平坦化层，所述第三金属化孔的一端与所述阴极层连接，所述第三金属化孔的另一端与位于所述像 素电路层中的所述电路走线连接。A plurality of third metallized holes, each of the third metallized holes penetrates through the pixel definition layer and the planarization layer along the thickness direction of the display module, one end of the third metallized hole is connected to the The cathode layer is connected, and the other end of the third metallized hole is connected to the circuit wiring in the pixel circuit layer.
  12. 根据权利要求6所述的显示模组，所述显示模组还包括：The display module according to claim 6, further comprising:
    像素电路层，用于设置所述像素电路阵列，所述像素电路层包括多个子功能层；A pixel circuit layer, used to set the pixel circuit array, the pixel circuit layer includes a plurality of sub-functional layers;
    平坦化层，设于所述像素电路层和所述像素定义层之间；a planarization layer disposed between the pixel circuit layer and the pixel definition layer;
    栅极线，分别与多个所述第一像素子电路的栅极信号端连接，所述电路走线与所述栅极线设于同一所述子功能层；The gate lines are respectively connected to the gate signal terminals of a plurality of the first pixel sub-circuits, and the circuit traces and the gate lines are arranged in the same sub-functional layer;
    多个第一金属化孔，各所述第一金属化孔分别沿所述显示模组的厚度方向贯穿所述像素定义层和所述平坦化层，所述第一金属化孔的一端与所述阴极层连接，所述第一金属化孔的另一端与所述电路走线连接；A plurality of first metallized holes, each of the first metallized holes penetrates through the pixel definition layer and the planarization layer along the thickness direction of the display module, one end of the first metallized hole is connected to the The cathode layer is connected, and the other end of the first metallized hole is connected to the circuit trace;
    数据信号线，分别与多个所述第一像素子电路的数据信号端连接，所述电路走线与所述数据信号线设于同一所述子功能层；The data signal lines are respectively connected to the data signal terminals of a plurality of the first pixel sub-circuits, and the circuit traces and the data signal lines are arranged in the same sub-functional layer;
    多个第三金属化孔，各所述第三金属化孔分别沿所述显示模组的厚度方向贯穿所述像素定义层和所述平坦化层，所述第三金属化孔的一端与所述阴极层连接，所述第三金属化孔的另一端与位于所述像素电路层中的所述电路走线连接。A plurality of third metallized holes, each of the third metallized holes penetrates through the pixel definition layer and the planarization layer along the thickness direction of the display module, one end of the third metallized hole is connected to the The cathode layer is connected, and the other end of the third metallized hole is connected to the circuit wiring in the pixel circuit layer.
  13. 根据权利要求7至12任一项所述的显示模组，所述电路走线的材料为Mg/Ag合金、Ti/Al/Ti或者Mo金属中的至少一种。According to the display module according to any one of claims 7 to 12, the material of the circuit trace is at least one of Mg/Ag alloy, Ti/Al/Ti or Mo metal.
  14. 根据权利要求11所述的显示模组，其中所述电路走线与所述数据信号线平行设置，一条所述电路走线设置在第一方向上相邻的两条所述数据信号线之间，且所述电路走线与相邻的一条所述数据信号线之间的距离和所述电路走线与相邻的另一条所述数据信号线之间的距离相等。The display module according to claim 11, wherein the circuit traces are arranged parallel to the data signal lines, and one of the circuit traces is arranged between two adjacent data signal lines in the first direction , and the distance between the circuit trace and one adjacent data signal line is equal to the distance between the circuit trace and another adjacent data signal line.
  15. 根据权利要求7所述的显示模组，其中所述平坦化层中设有多条驱动走线，多条所述驱动走线的一端分别与多个所述发光器件的阳极一一对应地连接，多条所述驱动走线的另一端分别与多个所述第一像素子电路一一对应地连接，以使多个所述发光器件的阳极与多个所述第一像素子电路一一对应地电性导通；The display module according to claim 7, wherein a plurality of driving wires are provided in the planarization layer, and one end of the plurality of driving wires is respectively connected to the anodes of the plurality of light-emitting devices in a one-to-one correspondence The other ends of the plurality of driving wires are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence, so that the anodes of the plurality of light-emitting devices are connected to the plurality of first pixel sub-circuits one by one. Corresponding to electrical conduction;
    其中，相同颜色的各所述发光器件对应的驱动走线的长度差在第一预设范围内。Wherein, the length difference of the driving wires corresponding to the light emitting devices of the same color is within a first preset range.
  16. 根据权利要求1至4任一项所述的显示模组，其中所述显示模组设有：The display module according to any one of claims 1 to 4, wherein the display module is provided with:
    第一子阵列区，所述第一子阵列区中设有多个第一像素电路和多个第二像素电路，所述第一像素电路包括多个所述第一像素子电路，所述第二像素电路包括多个所述第二像素子电路，且在所述第一方向上任意两个相邻的所述第一像素电路之间设有一个所述第二像素电路。The first sub-array area, the first sub-array area is provided with a plurality of first pixel circuits and a plurality of second pixel circuits, the first pixel circuit includes a plurality of the first pixel sub-circuits, the first pixel circuit The two-pixel circuit includes a plurality of second pixel sub-circuits, and one second pixel circuit is provided between any two adjacent first pixel circuits in the first direction.
  17. 根据权利要求16所述的显示模组，其中所述显示模组还设有：The display module according to claim 16, wherein the display module is further provided with:
    第二子阵列区，所述第二子阵列区与第一子阵列区在所述第一方向上相邻，所述第二子阵列区中设有多个所述第一像素电路。A second sub-array area, the second sub-array area is adjacent to the first sub-array area in the first direction, and a plurality of the first pixel circuits are arranged in the second sub-array area.
  18. 根据权利要求16所述的显示模组，其中所述显示模组还设有：The display module according to claim 16, wherein the display module is further provided with:
    第三子阵列区，所述第三子阵列区中设有多个重复单元和多个第三像素电路，所述重复单元包括在第一方向上相邻的一个所述第一像素电路和一个所述第二像素电路，且第三像素电路在第二方向上任意两个相邻的所述重复单元之间设有一个所述，所述第三像素电路包括沿所述第一方向排列的多个所述第二像素子电路，所述第二方向垂直于所述第一方向、且垂直于所述显示模组的厚度方向；In the third sub-array area, a plurality of repeating units and a plurality of third pixel circuits are arranged in the third sub-array area, and the repeating unit includes one first pixel circuit and one adjacent in the first direction The second pixel circuit, and the third pixel circuit is provided with one between any two adjacent repeating units in the second direction, the third pixel circuit includes A plurality of the second pixel sub-circuits, the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module;
    第四子阵列区，所述第四子阵列区与第三子阵列区在所述第一方向上相邻，所述第四子阵列区中设有多个所述第一像素电路和多个第四像素电路，且在所述第二方向上任意两个相邻的所述第一像素电路之间设有一个所述第四像素电路，所述第四像素电路包括沿所述第一方向排列的多个所述第二像素子电路，所述第四像素电路中所述第二像素子电路的数量小于所述第三像素电路中所述第二像素子电路的数量。A fourth sub-array area, the fourth sub-array area is adjacent to the third sub-array area in the first direction, and a plurality of the first pixel circuits and a plurality of A fourth pixel circuit, and one fourth pixel circuit is provided between any two adjacent first pixel circuits in the second direction, and the fourth pixel circuit includes A plurality of the second pixel sub-circuits are arranged, the number of the second pixel sub-circuits in the fourth pixel circuit is smaller than the number of the second pixel sub-circuits in the third pixel circuit.
  19. 根据权利要求18所述的显示模组，其中所述显示模组还设有：The display module according to claim 18, wherein the display module is further provided with:
    第三子阵列区，所述第三子阵列区与第一子阵列区在所述第二方向上相邻，所述第三子阵列区中设有多个重复单元和多个第三像素电路，所述重复单元包括在第一方向上相邻的一个所述第一像素电路和一个所述第二像素电路，且在所述第二方向上任意两个相邻的所述重复单元之间设有一个所述第三像素电路，所述第三像素电路包括沿所述第一方向排列的多个所述第二像素子电路；A third sub-array area, the third sub-array area is adjacent to the first sub-array area in the second direction, and a plurality of repeating units and a plurality of third pixel circuits are arranged in the third sub-array area , the repeating unit includes one of the first pixel circuits and one of the second pixel circuits adjacent in the first direction, and between any two adjacent repeating units in the second direction One third pixel circuit is provided, and the third pixel circuit includes a plurality of second pixel sub-circuits arranged along the first direction;
    所述第二方向垂直于所述第一方向、且垂直于所述显示模组的厚度方向。The second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module.
  20. 一种显示设备，其中包括：如权利要求1至19任一项所述的显示模组。A display device, comprising: the display module according to any one of claims 1-19.
PCT/CN2022/118386 2021-10-27 2022-09-13 Display module and display device WO2023071560A1 (en)

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