WO2023071078A1 - Pixel driving circuit and driving method therefor, and display screen - Google Patents

Pixel driving circuit and driving method therefor, and display screen Download PDF

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Publication number
WO2023071078A1
WO2023071078A1 PCT/CN2022/087345 CN2022087345W WO2023071078A1 WO 2023071078 A1 WO2023071078 A1 WO 2023071078A1 CN 2022087345 W CN2022087345 W CN 2022087345W WO 2023071078 A1 WO2023071078 A1 WO 2023071078A1
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Prior art keywords
tube
circuit
data
switch tube
power supply
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PCT/CN2022/087345
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French (fr)
Chinese (zh)
Inventor
谢青青
唐名剑
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问显科技(苏州)有限公司
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Priority claimed from CN202111256962.XA external-priority patent/CN116994517A/en
Application filed by 问显科技(苏州)有限公司 filed Critical 问显科技(苏州)有限公司
Publication of WO2023071078A1 publication Critical patent/WO2023071078A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the invention relates to the field of display technology, in particular to a pixel driving circuit, a driving method of the pixel driving circuit and a display screen with the pixel driving circuit.
  • a display usually includes pixels and a pixel driving circuit, and the pixel driving circuit is used to drive a light emitting device in each pixel to emit light.
  • area and power consumption are usually factors that must be considered.
  • the display In some application scenarios that require a small-sized display, such as a microdisplay used in a near-eye display scenario, the display usually needs to be small in size.
  • the pixel size is usually reduced to facilitate the arrangement of enough pixels, such as silicon-based OLED microdisplays, the pixel size is small, and the size of each sub-pixel is about 9um*3um.
  • the size of the pixel driving circuit is also reduced accordingly, so as to adapt to the corresponding pixel and drive the light emitting device inside to emit light.
  • the area and power consumption of some pixel driving circuits in the prior art are generally large, which cannot meet the requirements of small-sized displays. Therefore, there is an urgent need for a pixel driving circuit with small area and low power consumption to meet the usage requirements of small-sized displays.
  • the object of the present invention is to provide a pixel driving circuit with small area and low power consumption, and also provide a driving method of the pixel driving circuit and a display screen with the pixel driving circuit.
  • the present invention proposes a pixel driving circuit, the pixel driving circuit comprising:
  • the drive circuit is used to drive the light-emitting element to emit light, which includes a first drive tube and a second drive tube connected in series between the first power supply and the second power supply, the grid of the first drive tube is connected to the current circuit, so The first drive tube is connected to the light-emitting element through the second drive tube, and the withstand voltage values of the first drive tube and the second drive tube are both 3.2-5V;
  • the data buffer circuit is used to control the turn-on or turn-off of the second drive tube according to the stored data, which includes a first switch tube to a sixth switch tube, and the third switch tube and the fifth switch tube are connected in series to the first power supply and the first switch tube.
  • a first inverter is formed, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply, forming a second inverter, and the input of the first inverter
  • the terminal is connected to the output terminal of the second inverter, the output terminal is connected to the input terminal of the second inverter, and the output terminal is connected to the first data line through the first switch tube, and the output terminal of the second inverter is connected through the
  • the second switch tube is connected to the second data line, the gate of the sixth switch tube is connected to the gate of the second drive tube, wherein the withstand voltage values of the first switch tube to the sixth switch tube are all 0.9-1.8V .
  • both the first driving transistor and the second driving transistor are PMOS transistors.
  • the voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is non-zero.
  • the first switch tube, the second switch tube, the fifth switch tube and the sixth switch tube are all NMOS tubes, and the third switch tube and the fourth switch tube are all PMOS tubes.
  • the current circuit includes a constant current source and a seventh switch tube to a ninth switch tube, wherein the seventh switch tube and the eighth switch tube are connected in series between the first power supply and the second power supply, and the first switch tube
  • the grid of the seven switching tubes is connected to the grid of the second driving tube
  • the source of the seventh switching tube is connected to the grid
  • the ninth switching tube and the constant current source are connected in series between the first power supply and the second power supply
  • the source of the ninth switching transistor is connected to the gate.
  • the pixel drive circuit further includes:
  • the data temporary storage circuit is communicatively connected with the data buffer circuit, and is used for temporarily storing the data written into the data buffer circuit.
  • the structure of the temporary data storage circuit is the same as that of the data cache circuit.
  • the pixel drive circuit further includes:
  • the latch buffer is communicatively connected with both the data buffer circuit and the temporary data storage circuit, and is used for reading and writing the data stored in the temporary data storage circuit into the data buffer circuit.
  • one latch buffer is provided for each column of pixels.
  • each of the latch buffers simultaneously reads out the data in the corresponding data temporary storage circuit and simultaneously stores it into the corresponding data buffer circuit.
  • the present invention also discloses a driving method of a pixel driving circuit.
  • the driving method includes the following steps:
  • the output first power supply voltage controls the second drive tube to be turned off, and the light-emitting element does not emit light
  • the output second power supply voltage controls the second driving transistor to turn on, and the light-emitting element emits light.
  • the present invention also discloses a display screen, which includes the above-mentioned pixel driving circuit.
  • a data buffer circuit composed of a MOS tube with a low withstand voltage value is used to drive a MOS tube with a high withstand voltage value to be turned on or off, which can effectively reduce the area and power consumption of the pixel drive circuit, and at the same time, the PMOS tube is used as the drive tube , and can also significantly reduce the area and power consumption of the pixel driving circuit.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of data access of a pixel driving circuit
  • Fig. 3 is a timing diagram of writing data in the pixel driving circuit
  • Fig. 4 is a timing diagram of reading data by the pixel driving circuit.
  • a pixel driving circuit disclosed by the present invention can avoid the above-mentioned problems, has the advantages of small footprint and low power consumption, and is especially suitable for microdisplays.
  • Microdisplays can be used in projectors and near-eye display systems. Among them, the near-eye display systems are as follows: Head-mounted virtual display simulator, pilot helmet display system, head-mounted medical rescue diagnosis system, etc.
  • a pixel driving circuit disclosed by an embodiment of the present invention includes a light emitting element L, a current circuit 10 , a driving circuit 20 and a data buffer circuit 30 .
  • the light-emitting element L is used to emit light, and it can choose OLED or the like;
  • the current circuit 10 is connected to the driving circuit 20 to generate a constant current, and the driving circuit 20 can drive the light-emitting element L to emit light according to the generated constant current.
  • the light generated by the light-emitting element L in each pixel can be kept consistent, and the magnitude of the constant current generated by the current circuit 10 can be adjusted, so that the light-emitting element L can produce light of different brightness;
  • the driving circuit 20 is connected with the light-emitting element L, It is used to drive the light-emitting element L to emit light;
  • the data buffer circuit 30 is connected to the drive circuit 20 for buffering data and controlling whether the drive circuit 20 drives the light-emitting element L to emit light.
  • the drive circuit 20 includes a first drive tube P0 and a second drive tube P1, the first drive tube P0 and the second drive tube P1 are connected in series, and after the first drive tube P0 and the second drive tube P1 are connected in series Connected between the first power supply VDD and the second power supply VSS, the first drive transistor P0 and the second drive transistor P1 are both PMOS transistors with a withstand voltage of 3.2V-5V. Specifically, the drain of the first driving transistor P0 is connected to the first power supply VDD, the source is connected to the light emitting element L through the second driving transistor P1 , and the gate is connected to the current circuit 10 .
  • the NMOS tube is used as the driving tube, on the one hand, when it is turned on at a low voltage, such as 1.8V, the on-resistance generated by it is relatively large, and it cannot drive the light-emitting element L to emit light.
  • the resistance of the light-emitting element L is 100M
  • the source voltage of the NMOS tube increases accordingly, and the on-resistance of the NMOS tube increases.
  • the source voltage is greater than Vgs-Vth, the NMOS tube is turned off.
  • the voltage of the light-emitting element L cannot meet the actual demand and cannot generate enough light; on the other hand, if the NMOS tube is driven by high voltage, such as 3.2V ⁇ When the NMOS tube is driven by 5V, the NMOS tube cannot be turned off.
  • NMOS tubes are used as drive tubes, two types of MOS tubes are required in the branch where the drive tubes are located, that is, NMOS tubes and PMOS tubes are required. The DRC distance between these two types of MOS tubes is relatively large, and finally As a result, the area of the pixel driving circuit is larger.
  • the light-emitting element L can be driven to emit light without increasing the area of the pixel driving circuit.
  • the source and drain of the two PMOS transistors can be shared, thereby reducing the area of the pixel driving circuit; Due to the area loss caused by the industrial design rules, the problem of the DRC spacing between the NMOS transistor and the PMOS transistor is avoided, thereby reducing the area of the pixel circuit.
  • the on-resistance of the PMOS tube is small when it is turned on, which can well drive the light-emitting element L to emit light.
  • the data cache circuit 30 is an SRAM structure composed of six switch transistors, and the six switch transistors are respectively denoted as a first switch transistor M1 to a sixth switch transistor M6 .
  • the third switching tube M3 and the fifth switching tube M5 are connected in series, and after they are connected in series, they are connected between the first power supply VDD and the second power supply VSS to form a first inverter; the fourth switching tube M4 and the fifth switching tube M4 are connected in series.
  • the six switch tubes M6 are connected in series, and after the two are connected in series, they are also connected between the first power supply VDD and the second power supply VSS to form a second inverter.
  • the gate terminal of the sixth switch tube M6 is connected to the second drive tube
  • the gate terminal of P1 is connected; the input terminal of the first inverter is connected with the output terminal of the second inverter, the output terminal is connected with the input terminal of the second inverter, and the output terminal of the first inverter passes through the first
  • the switch tube M1 is connected to the first data line B0, the output terminal of the second inverter is connected to the second data line B1 through the second switch tube M2, and the input terminal of the second inverter is also connected to the gate terminal of the second drive tube P1
  • the gate ends of the first switching tube M1 and the second switching tube M2 are both connected to the scanning signal line, where the data signal line is used for inputting data signals, and the scanning signal line is used for inputting switching signals.
  • the data buffer circuit 30 can drive the second driving transistor P1 to turn on or off according to the stored voltage, so as to control whether the driving circuit 20 drives the light emitting element L to emit light.
  • the first power supply VDD voltage is set as the turn-off voltage of the second drive transistor P1 during implementation, for example, the first power supply VDD is set to 5V
  • the second power supply VSS is set as the turn-on voltage of the second drive transistor P1.
  • Voltage such as setting the second power supply VSS to 3.2V, makes the data logic 1 latched by the data buffer circuit 30 be the power supply value of the first power supply VDD, and the data logic 0 is the voltage value of the second power supply VSS.
  • the voltage of the first power supply VDD can turn off the second drive tube P1, and at this time, the light-emitting element L does not emit light; when the data buffer circuit 30 outputs data logic 0, the voltage of the second power supply VSS
  • the second drive transistor P1 can be turned on, and the current output by the current circuit 10 flows to the light-emitting element L through the first drive transistor P0 and the second drive transistor P1, so as to drive the light-emitting element L to emit light.
  • first switching tube M1 to the sixth switching tube M6 are all MOS tubes with a withstand voltage of 0.9-1.8V, wherein the first switching tube M1, the second switching tube M2, the fifth switching tube M5 and the sixth switching tube
  • the switching tube M6 is both an NMOS tube
  • the third switching tube M3 and the fourth switching tube M4 are both PMOS tubes.
  • the source of the third switching tube M3 is connected to the drain of the fifth switching tube M5 to form the output terminal of the first inverter
  • the gate of the third switching tube M3 is connected to the gate of the fifth switching tube M5 to form a input.
  • the gate of the fourth switch M4 is connected to the gate of the sixth switch M6 to form an input terminal of the second inverter, and the source of the fourth switch M4 is connected to the drain of the sixth switch M6 to form an output terminal.
  • the gate of the sixth switching transistor M6 is connected to the gate of the second driving transistor P1.
  • the data buffer circuit 30 can drive the second drive transistor P1 to turn on or off according to the stored voltage, that is to say, a MOS transistor with a low withstand voltage value is used to drive a MOS transistor with a high withstand voltage value. It is best for a MOS tube with a voltage value of 1.8V to drive a 5V PMOS tube.
  • the source of the third switching tube M3 is connected to the drain of the fifth switching tube M5 to form the output terminal of the first inverter, and the gate of the third switching tube M3 is connected to the gate of the fifth switching tube M5 to form a input.
  • the gate of the fourth switch M4 is connected to the gate of the sixth switch M6 to form an input terminal of the second inverter, and the source of the fourth switch M4 is connected to the drain of the sixth switch M6 to form an output terminal.
  • the gate of the sixth switching transistor M6 is connected to the gate of the second driving transistor P1.
  • the present invention stores data by using a data buffer circuit 30 composed of a MOS transistor with a low withstand voltage value and drives the second drive transistor P1 to turn on or off according to the stored data, that is, a MOS transistor with a low withstand voltage value is used to drive a high withstand voltage transistor.
  • the value of the MOS tube can significantly reduce power consumption. Specifically, since the lower the power supply voltage is during data writing, the lower the power consumption of the data buffer circuit 30 is, so the data buffer circuit 30 composed of MOS transistors with low withstand voltage can significantly reduce power consumption.
  • the size of the MOS tube with a low withstand voltage value is significantly smaller than that of a MOS tube with a high withstand voltage value, usually, the size of a MOS tube with a high withstand voltage value is 2 to 3 times larger than that of a MOS tube with a low withstand voltage value. Therefore, the size of the data buffer circuit 30 formed by the MOS transistor with low withstand voltage is smaller, which can significantly reduce the area of the pixel driving circuit.
  • the present invention drives a MOS tube with a high withstand voltage by using a MOS tube with a low withstand voltage value.
  • a MOS tube with a withstand voltage value of 1.8V is used to drive a MOS tube with a withstand voltage value of 5V.
  • the MOS tubes in the N well only have low withstand voltage MOS tubes and high withstand voltage PMOS tubes, but there is no NMOS tube with a high withstand voltage value that needs to be connected to 0V.
  • the current circuit 10 includes a seventh switching tube M7, an eighth switching tube M8, a ninth switching tube M9 and a constant current source I, wherein the seventh switching tube M7 and the eighth switching tube M8 are connected to the first connection point, and the two are connected in series and connected between the first power supply VDD and the second power supply VSS, the gate of the seventh switching transistor M7 and the gate of the first driving transistor P0 are connected to the second connection point, and the first connection point is connected to the second connection point; the ninth switch tube M9 is connected to the third connection point with the constant current source I, and the two are connected in series and then connected between the first power supply VDD and the second power supply VSS; the eighth switch tube M8 and the gate of the ninth switching transistor M9 are connected to the fourth connection point, and the third connection point is connected to the fourth connection point.
  • the constant current generated by the current circuit 10 flows to the light-emitting element L through the first drive transistor P0 and the second drive transistor P1, so that the light-emitting element L emits light.
  • the current circuit 10 can provide stable and consistent current for each pixel driving circuit. That is to say, when the second driving tube P1 is turned on, the current is controlled by the constant current source I, and the constant current source I can be set with multiple levels of current, so as to make the light-emitting element L generate light with different brightness.
  • the pixel driving circuit includes a data temporary storage circuit 40 , wherein the data temporary storage circuit 40 is used for temporarily storing data, and the data buffer circuit 30 is used for driving the second driving transistor P1 to be turned on or off.
  • the structures of the temporary data storage circuit 40 and the data buffer circuit 30 are the same, and reference may be made to the structure of the data buffer circuit 30 described above, which will not be repeated here.
  • the data is first stored in the data temporary storage circuit 40, and when necessary, the data is read from the first-level cache and written into the data cache circuit 30, and the data cache circuit 30 drives the opening of the second drive transistor P1 according to the data. Or turn it off, so as to control the driving circuit 20 to control whether the light-emitting element L emits light.
  • the pixel driving circuit includes a latch buffer 50 (Latch Buffer), which is used to read data from the data temporary storage circuit 40 and store it in the data buffer circuit 30.
  • latch Buffer used to read data from the data temporary storage circuit 40 and store it in the data buffer circuit 30.
  • each column of pixels corresponds to one latch buffer 50 , that is to say, all rows of pixels in each column share one latch buffer 50 .
  • the chip area under the pixel can be fully utilized, maximizing the utilization of the wafer, and at the same time, the pressure on external storage can be reduced, and the storage function can be realized under the pixel circuit.
  • the data stored in the data temporary storage circuit 40 and the data read from the first buffer circuit and stored in the data buffer circuit 30 through the latch buffer 50 are all operated simultaneously for a whole row, that is, Each row of data is stored in the temporary data storage circuit 40 at the same time, or the latch buffer 50 reads data from the first buffer circuit and writes data into the data buffer circuit 30 at the same time. If each row has 1024 pixels, then each row has 2048 data buffer circuits 30 and 1024 latch buffers 50 . When storing data, the data required by each row of pixels is stored in the data temporary storage circuit 40 at the same time, and the 1024 latch buffers 50 simultaneously read the data stored in the corresponding data temporary storage circuit 40, and write the data simultaneously into the corresponding data buffer circuit 30.
  • the storage node A is in a 1 level state, and the storage node B is in a 0 level state.
  • the output driving voltage is the voltage at point A.
  • the second drive tube P1 is turned off, and the current cannot flow to the light-emitting element L.
  • the light-emitting element L does not emit light.
  • the data line B1 is set to 1; secondly, the scanning signal line is set to a high level, at this time the first switch M1 and the second switch M2 are turned on, and the storage node A discharges to the first data line B0 through the first switch M1 , until it reaches 0 level, at this time the sixth switch tube M6 is turned off, the second data line B1 passes through the second switch tube M2, the first power supply VDD passes through the fourth switch tube M4, and charges the storage node B to 1 level, the second The fifth switching tube M5 is turned on.
  • the scanning signal line is set to low level, the first switching tube M1 and the second switching tube M2 are turned off, at this time, the storage node A is in the 0 level state, the storage node B is in the 1 level state, and the output driving voltage is the voltage at point A, when the voltage at point A is low, the second drive transistor P1 is turned on, and the current flows to the light-emitting element L, at this time the light-emitting element L emits light.
  • the data stored in the data cache circuit 30 can be read out for subsequent use, such as the latch buffer 50 reading data from the data temporary storage circuit 40 and writing it into the data cache circuit 30 and so on.
  • the process of reading data is as follows:
  • reading 1 from the data cache circuit 30 Take reading 1 from the data cache circuit 30 as an example (storage node A stores 1, and storage node B stores 0).
  • the first data line B0 and the second data line B1 are precharged to 1, at this time, the scanning signal line is set to low level, and the first switching tube M1 and the second switching tube M2 are turned off.
  • the scanning signal line is set to high level, the first switching tube M1 and the second switching tube M2 are turned on, and the second data line B1 is rapidly discharged to 0 level through the second switching tube M2 and the sixth switching tube M6,
  • the fifth switching tube M5 is still off, the first power supply VDD charges the first data line B0 through the third switching tube M3 and the first switching tube M1, so that the first data line B0 is in a 1-level state, and the sixth switching tube M6 still on.
  • the scan signal line is set to a low level, and at this time, the reading of 1 from the data buffer circuit 30 is completed.
  • the storage node A stores 0, and the storage node B stores 1).
  • the first data line B0 and the second data line B1 are precharged to 1, at this time, the scanning signal line is set to low level, and the first switching tube M1 and the second switching tube M2 are turned off.
  • the scanning signal line is set to high level, the first switching tube M1 and the second switching tube M2 are turned on, and the first data line B0 is rapidly discharged to 0 level through the first switching tube M1 and the fifth switching tube M5, The sixth switch tube M6 is still off, the first power supply VDD charges the second data line B1 through the fourth switch tube M4 and the second switch tube M2, so that the second data signal is in a 1-level state, and the fifth switch tube M5 is still conduction. Finally, the scan signal line is set to low level, and at this time, reading 0 from the data buffer circuit 30 is completed.
  • the present invention also discloses a display screen, which has the above-mentioned pixel driving circuit.
  • the present invention can effectively reduce the area and power consumption of the pixel driving circuit by using the data buffer circuit 30 composed of a MOS transistor with a low withstand voltage value to drive the MOS transistor with a high withstand voltage value to be turned on or off. Tube, can also significantly reduce the area and power consumption of the pixel driving circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Disclosed are a pixel driving circuit and a driving method therefor, and a display screen, the pixel driving circuit comprising a light emitting element, a current circuit, a driving circuit and a data buffer circuit, wherein the light emitting element is used for emitting light; the current circuit is connected to the driving circuit to generate constant current, and the driving circuit may drive the light emitting element to emit light according to constant current generated by the current circuit; and the data buffer circuit is connected to the driving circuit, and is used for buffering data and controlling whether the driving circuit drives the light emitting element to emit light. The present invention has the advantages of small area and low power consumption.

Description

一种像素驱动电路及其驱动方法、显示屏A pixel driving circuit, its driving method, and display screen 技术领域technical field
本发明涉及显示技术领域，尤其涉及一种像素驱动电路、像素驱动电路的驱动方法及具有该像素驱动电路的显示屏。The invention relates to the field of display technology, in particular to a pixel driving circuit, a driving method of the pixel driving circuit and a display screen with the pixel driving circuit.
背景技术Background technique
随着显示技术的不断发展，显示器已经在日常生活中无处不在，其广泛应用于智能手机、平板电脑、桌面显示器、电视、数据投影仪和增强现实/虚拟现实设备。显示器通常包括像素和像素驱动电路，像素驱动电路用于驱动每个像素内的发光器件发光。在设计像素电路时，面积及功耗通常是必然考虑的因素。在一些需要使用小尺寸显示器的应用场景中，如近眼显示场景使用的微显示器等，显示器通常需要做到很小的尺寸。显示器在尺寸较小时，为了达到相应的显示要求，通常会减小像素尺寸，以便于布置足够多的像素，如硅基OLED微显示器，像素尺寸较小，每个子像素尺寸约为9um*3um。在减小像素尺寸时，像素驱动电路的尺寸也相应减小，以便于与对应的像素适配，驱动其内的发光器件发光。然而，现有技术中一些像素驱动电路的面积及功耗通常较大，无法满足小尺寸显示器的使用需求。因而，亟需一种面积小、功耗低的像素驱动电路，以满足小尺寸显示器的使用需求。With the continuous development of display technology, displays have become ubiquitous in our daily life, and they are widely used in smartphones, tablets, desktop monitors, TVs, data projectors and augmented reality/virtual reality devices. A display usually includes pixels and a pixel driving circuit, and the pixel driving circuit is used to drive a light emitting device in each pixel to emit light. When designing a pixel circuit, area and power consumption are usually factors that must be considered. In some application scenarios that require a small-sized display, such as a microdisplay used in a near-eye display scenario, the display usually needs to be small in size. When the size of the display is small, in order to meet the corresponding display requirements, the pixel size is usually reduced to facilitate the arrangement of enough pixels, such as silicon-based OLED microdisplays, the pixel size is small, and the size of each sub-pixel is about 9um*3um. When the size of the pixel is reduced, the size of the pixel driving circuit is also reduced accordingly, so as to adapt to the corresponding pixel and drive the light emitting device inside to emit light. However, the area and power consumption of some pixel driving circuits in the prior art are generally large, which cannot meet the requirements of small-sized displays. Therefore, there is an urgent need for a pixel driving circuit with small area and low power consumption to meet the usage requirements of small-sized displays.
发明内容Contents of the invention
本发明的目的在于提供一种面积小，功耗低的像素驱动电路，同时还提供一种该像素驱动电路的驱动方法及具有该像素驱动电路的显示屏。The object of the present invention is to provide a pixel driving circuit with small area and low power consumption, and also provide a driving method of the pixel driving circuit and a display screen with the pixel driving circuit.
为实现上述目的，本发明提出一种像素驱动电路，所述像素驱动电路 包括：In order to achieve the above object, the present invention proposes a pixel driving circuit, the pixel driving circuit comprising:
发光件，用于发光；A luminous part for emitting light;
电流电路，用于产生恒定的电流；a current circuit for generating a constant current;
驱动电路，用于驱动发光件发光，其包括串联连接于第一电源和第二电源之间的第一驱动管和第二驱动管，所述第一驱动管的栅极与电流电路相连，所述第一驱动管通过第二驱动管与发光件相连，所述第一驱动管和第二驱动管的耐压值均为3.2～5V；The drive circuit is used to drive the light-emitting element to emit light, which includes a first drive tube and a second drive tube connected in series between the first power supply and the second power supply, the grid of the first drive tube is connected to the current circuit, so The first drive tube is connected to the light-emitting element through the second drive tube, and the withstand voltage values of the first drive tube and the second drive tube are both 3.2-5V;
数据缓存电路，用于根据存储的数据控制第二驱动管的开启或者关断，其包括第一开关管至第六开关管，第三开关管和第五开关管串联连接于第一电源和第二电源之间，形成第一反相器，第四开关管和第六开关管串联连接于第一电源和第二电源之间，形成第二反相器，所述第一反相器的输入端与第二反相器的输出端相连，输出端与第二反相器的输入端相连，且输出端通过第一开关管连接第一数据线，所述第二反相器的输出端通过第二开关管连接第二数据线，所述第六开关管的栅极与第二驱动管的栅极相连，其中，第一开关管至第六开关管的耐压值均为0.9～1.8V。The data buffer circuit is used to control the turn-on or turn-off of the second drive tube according to the stored data, which includes a first switch tube to a sixth switch tube, and the third switch tube and the fifth switch tube are connected in series to the first power supply and the first switch tube. Between the two power supplies, a first inverter is formed, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply, forming a second inverter, and the input of the first inverter The terminal is connected to the output terminal of the second inverter, the output terminal is connected to the input terminal of the second inverter, and the output terminal is connected to the first data line through the first switch tube, and the output terminal of the second inverter is connected through the The second switch tube is connected to the second data line, the gate of the sixth switch tube is connected to the gate of the second drive tube, wherein the withstand voltage values of the first switch tube to the sixth switch tube are all 0.9-1.8V .
优选地，所述第一驱动管和第二驱动管均为PMOS管。Preferably, both the first driving transistor and the second driving transistor are PMOS transistors.
优选地，所述第一电源的电压大于第二电源的电压，且第二电源的电压为非零。Preferably, the voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is non-zero.
优选地，所述第一开关管、第二开关管、第五开关管和第六开关管均为NMOS管，所述第三开关管和第四开关管均为PMOS管。Preferably, the first switch tube, the second switch tube, the fifth switch tube and the sixth switch tube are all NMOS tubes, and the third switch tube and the fourth switch tube are all PMOS tubes.
优选地，所述电流电路包括恒流源及第七开关管至第九开关管，其中，第七开关管和第八开关管串联连接于第一电源和第二电源之间，且所述第七开关管的栅极与第二驱动管的栅极相连，所述第七开关管的源极与栅极相连，第九开关管和恒流源串联连接于第一电源和第二电源之间，且所述第九开关管的源极与栅极相连。Preferably, the current circuit includes a constant current source and a seventh switch tube to a ninth switch tube, wherein the seventh switch tube and the eighth switch tube are connected in series between the first power supply and the second power supply, and the first switch tube The grid of the seven switching tubes is connected to the grid of the second driving tube, the source of the seventh switching tube is connected to the grid, and the ninth switching tube and the constant current source are connected in series between the first power supply and the second power supply , and the source of the ninth switching transistor is connected to the gate.
优选地，所述像素驱动电路还包括：Preferably, the pixel drive circuit further includes:
数据暂存电路，与数据缓存电路通信连接，用于暂时存储写入至数据缓存电路中的数据。The data temporary storage circuit is communicatively connected with the data buffer circuit, and is used for temporarily storing the data written into the data buffer circuit.
优选地，所述数据暂存电路的结构与数据缓存电路的结构相同。Preferably, the structure of the temporary data storage circuit is the same as that of the data cache circuit.
优选地，所述像素驱动电路还包括：Preferably, the pixel drive circuit further includes:
锁存缓冲器，与所述数据缓存电路和数据暂存电路均通信连接，用于将数据暂存电路中存储的数据读出并写入至数据缓存电路中。The latch buffer is communicatively connected with both the data buffer circuit and the temporary data storage circuit, and is used for reading and writing the data stored in the temporary data storage circuit into the data buffer circuit.
优选地，每列像素设置一所述锁存缓冲器。Preferably, one latch buffer is provided for each column of pixels.
优选地，每个所述锁存缓冲器同时将对应数据暂存电路中的数据读出并同时存入对应的数据缓存电路中。Preferably, each of the latch buffers simultaneously reads out the data in the corresponding data temporary storage circuit and simultaneously stores it into the corresponding data buffer circuit.
本发明还揭示了一种像素驱动电路的驱动方法，驱动方法包括如下步骤：The present invention also discloses a driving method of a pixel driving circuit. The driving method includes the following steps:
数据缓存电路输出逻辑为1时，输出的第一电源电压控制第二驱动管关断，发光件不发光；When the output logic of the data buffer circuit is 1, the output first power supply voltage controls the second drive tube to be turned off, and the light-emitting element does not emit light;
数据缓存电路输出逻辑为0时，输出的第二电源电压控制第二驱动管导通，发光件发光。When the output logic of the data buffer circuit is 0, the output second power supply voltage controls the second driving transistor to turn on, and the light-emitting element emits light.
本发明还揭示了一种显示屏，包括上述像素驱动电路。The present invention also discloses a display screen, which includes the above-mentioned pixel driving circuit.
本发明的有益效果是：The beneficial effects of the present invention are:
本发明通过采用低耐压值的MOS管构成的数据缓存电路驱动高耐压值的MOS管的开启或者关断，可有效减少像素驱动电路的面积及功耗，同时，采用PMOS管作为驱动管，也可显著减少像素驱动电路的面积及功耗。In the present invention, a data buffer circuit composed of a MOS tube with a low withstand voltage value is used to drive a MOS tube with a high withstand voltage value to be turned on or off, which can effectively reduce the area and power consumption of the pixel drive circuit, and at the same time, the PMOS tube is used as the drive tube , and can also significantly reduce the area and power consumption of the pixel driving circuit.
附图说明Description of drawings
图1是本发明一实施例中像素驱动电路结构示意图；FIG. 1 is a schematic structural diagram of a pixel driving circuit in an embodiment of the present invention;
图2是像素驱动电路的数据存取示意图；FIG. 2 is a schematic diagram of data access of a pixel driving circuit;
图3是像素驱动电路写数据时序图；Fig. 3 is a timing diagram of writing data in the pixel driving circuit;
图4是像素驱动电路读数据时序图。Fig. 4 is a timing diagram of reading data by the pixel driving circuit.
具体实施方式Detailed ways
下面将结合本发明的附图，对本发明实施例的技术方案进行清楚、完整的描述。The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.
由于现有技术中像素驱动电路存在占用面积大，功耗高的问题。本发明所揭示的一种像素驱动电路，能够避免上述问题，具有占用面积小，功耗低的优点，尤其适用于微显示器，微显示器可用于投影仪及近眼显示***，其中，近眼显示***如头戴式虚拟显示模拟器、飞行员头盔显示***、头戴式医疗救护诊断***等等。Because the pixel driving circuit in the prior art has the problems of large occupation area and high power consumption. A pixel driving circuit disclosed by the present invention can avoid the above-mentioned problems, has the advantages of small footprint and low power consumption, and is especially suitable for microdisplays. Microdisplays can be used in projectors and near-eye display systems. Among them, the near-eye display systems are as follows: Head-mounted virtual display simulator, pilot helmet display system, head-mounted medical rescue diagnosis system, etc.
如图1所示，为本发明一实施例所揭示的像素驱动电路，包括发光件L、电流电路10、驱动电路20和数据缓存电路30。其中，发光件L用于发光，其可选择OLED等；电流电路10与驱动电路20相连，用于产生恒定电流，驱动电路20可依据产生的恒定电流驱动发光件L发光，在电流电路10的作用下，每个像素中发光件L产生的光可保持一致，并且电流电路10产生的恒定电流的大小可调，可使发光件L产生不同亮度的光；驱动电路20与发光件L相连，用于驱动发光件L发光；数据缓存电路30与驱动电路20相连，用于缓存数据并控制驱动电路20是否驱动发光件L发光。As shown in FIG. 1 , a pixel driving circuit disclosed by an embodiment of the present invention includes a light emitting element L, a current circuit 10 , a driving circuit 20 and a data buffer circuit 30 . Wherein, the light-emitting element L is used to emit light, and it can choose OLED or the like; the current circuit 10 is connected to the driving circuit 20 to generate a constant current, and the driving circuit 20 can drive the light-emitting element L to emit light according to the generated constant current. Under the action, the light generated by the light-emitting element L in each pixel can be kept consistent, and the magnitude of the constant current generated by the current circuit 10 can be adjusted, so that the light-emitting element L can produce light of different brightness; the driving circuit 20 is connected with the light-emitting element L, It is used to drive the light-emitting element L to emit light; the data buffer circuit 30 is connected to the drive circuit 20 for buffering data and controlling whether the drive circuit 20 drives the light-emitting element L to emit light.
如图1所示，驱动电路20包括第一驱动管P0和第二驱动管P1，第一驱动管P0与第二驱动管P1串联连接，第一驱动管P0与第二驱动管P1串联连接后连接于第一电源VDD和第二电源VSS之间，第一驱动管P0和第二驱动管P1均为耐压值为3.2V～5V的PMOS管。具体地，第一驱动管P0的漏极与第一电源VDD相连，源极通过第二驱动管P1与发光件L相连，栅极与电流电路10相连。As shown in FIG. 1 , the drive circuit 20 includes a first drive tube P0 and a second drive tube P1, the first drive tube P0 and the second drive tube P1 are connected in series, and after the first drive tube P0 and the second drive tube P1 are connected in series Connected between the first power supply VDD and the second power supply VSS, the first drive transistor P0 and the second drive transistor P1 are both PMOS transistors with a withstand voltage of 3.2V-5V. Specifically, the drain of the first driving transistor P0 is connected to the first power supply VDD, the source is connected to the light emitting element L through the second driving transistor P1 , and the gate is connected to the current circuit 10 .
由于NMOS管作为驱动管时，一方面其在低压开启时，如1.8V开启时，其产生的导通电阻较大，无法很好的驱动发光件L发光，如以发光件L的电阻为100M欧为例，当NMOS管开启时，电流增大，则发光件L获得的电压就变大，此时NMOS管的源极电压随之增大，NMOS管的导通电 阻增大。当源极电压大于Vgs-Vth时，NMOS管关断，此时发光件L的电压无法满足实际需求，无法产生足够的光；另一方面若采用高压来驱动NMOS管时，如采用3.2V～5V来驱动NMOS管时，则NMOS管无法关断。另外，在采用NMOS管作为驱动管时，驱动管所在的支路需要两种类型的MOS管，即需要采用NMOS管和PMOS管，这两种类型的MOS管之间的DRC间距较大，最终导致像素驱动电路的面积较大。Since the NMOS tube is used as the driving tube, on the one hand, when it is turned on at a low voltage, such as 1.8V, the on-resistance generated by it is relatively large, and it cannot drive the light-emitting element L to emit light. For example, the resistance of the light-emitting element L is 100M Take Europe as an example, when the NMOS tube is turned on, the current increases, and the voltage obtained by the light-emitting element L becomes larger. At this time, the source voltage of the NMOS tube increases accordingly, and the on-resistance of the NMOS tube increases. When the source voltage is greater than Vgs-Vth, the NMOS tube is turned off. At this time, the voltage of the light-emitting element L cannot meet the actual demand and cannot generate enough light; on the other hand, if the NMOS tube is driven by high voltage, such as 3.2V~ When the NMOS tube is driven by 5V, the NMOS tube cannot be turned off. In addition, when NMOS tubes are used as drive tubes, two types of MOS tubes are required in the branch where the drive tubes are located, that is, NMOS tubes and PMOS tubes are required. The DRC distance between these two types of MOS tubes is relatively large, and finally As a result, the area of the pixel driving circuit is larger.
而本发明通过将第一驱动管P0和第二驱动管P1采用PMOS管而非采用NMO管，可很好对驱动发光件L发光并且不会导致像素驱动电路的面积增加。具体而言，在采用相同类型的PMOS管时，一方面两个PMOS管的源极和漏极可共用，进而可减少像素驱动电路的面积，另一方面，可避免NMOS管和PMOS管之间因工业设计规则所带来的面积损耗，也即避免了NMOS管和PMOS管之间需要存在DRC间距的问题，进而可减少像素电路的面积。进一步地，PMOS管在开启时其导通电阻较小，可很好的驱动发光件L发光，如PMOS管使用3.2V开启，并且第一电源VDD为5V时，Vgs＝-1.8V，Vth＝-728mV，|Vgs|-|Vth|>0，PMOS管导通，导通电阻为43K，并且在PMOS管开启时，源极和栅极电压并不随着电流增大而变化，可以稳定驱动发光件L方法。更进一步地，在选用PMOS管时，由于其栅极接电流电路10，在PMOS管开启时，栅极电位与源极电位相同，不会造成衬偏效应。However, in the present invention, by using PMOS transistors instead of NMO transistors for the first driving transistor P0 and the second driving transistor P1, the light-emitting element L can be driven to emit light without increasing the area of the pixel driving circuit. Specifically, when using the same type of PMOS transistors, on the one hand, the source and drain of the two PMOS transistors can be shared, thereby reducing the area of the pixel driving circuit; Due to the area loss caused by the industrial design rules, the problem of the DRC spacing between the NMOS transistor and the PMOS transistor is avoided, thereby reducing the area of the pixel circuit. Further, the on-resistance of the PMOS tube is small when it is turned on, which can well drive the light-emitting element L to emit light. For example, when the PMOS tube is turned on with 3.2V, and the first power supply VDD is 5V, Vgs=-1.8V, Vth= -728mV, |Vgs|-|Vth|>0, the PMOS tube is turned on, the on-resistance is 43K, and when the PMOS tube is turned on, the source and gate voltages do not change with the increase of the current, and the light can be stably driven Part L method. Furthermore, when a PMOS transistor is selected, since its gate is connected to the current circuit 10, when the PMOS transistor is turned on, the potential of the gate is the same as the potential of the source, which will not cause a lining bias effect.
如图1所示，数据缓存电路30是由6个开关管构成的SRAM结构，6个开关管分别记为第一开关管M1至第六开关管M6。其中，第三开关管M3和第五开关管M5串联连接，并且两者串联连接后连接于第一电源VDD和第二电源VSS之间，形成第一反相器；第四开关管M4和第六开关管M6串联连接，并且两者串联连接后也连接于第一电源VDD和第二电源VSS之间，形成第二反相器，同时，第六开关管M6的栅极端与第二驱动管P1的栅极端相连；第一反相器的输入端与第二反相器的输出端相连，输 出端与第二反相器的输入端相连，并且第一反相器的输出端通过第一开关管M1连接第一数据线B0，第二反相器的输出端通过第二开关管M2连接第二数据线B1，第二反相器的输入端还与第二驱动管P1的栅极端相连；第一开关管M1和第二开关管M2的栅极端均连接扫描信号线，这里的数据信号线用于输入数据信号，扫描信号线用于输入开关信号。As shown in FIG. 1 , the data cache circuit 30 is an SRAM structure composed of six switch transistors, and the six switch transistors are respectively denoted as a first switch transistor M1 to a sixth switch transistor M6 . Wherein, the third switching tube M3 and the fifth switching tube M5 are connected in series, and after they are connected in series, they are connected between the first power supply VDD and the second power supply VSS to form a first inverter; the fourth switching tube M4 and the fifth switching tube M4 are connected in series. The six switch tubes M6 are connected in series, and after the two are connected in series, they are also connected between the first power supply VDD and the second power supply VSS to form a second inverter. At the same time, the gate terminal of the sixth switch tube M6 is connected to the second drive tube The gate terminal of P1 is connected; the input terminal of the first inverter is connected with the output terminal of the second inverter, the output terminal is connected with the input terminal of the second inverter, and the output terminal of the first inverter passes through the first The switch tube M1 is connected to the first data line B0, the output terminal of the second inverter is connected to the second data line B1 through the second switch tube M2, and the input terminal of the second inverter is also connected to the gate terminal of the second drive tube P1 The gate ends of the first switching tube M1 and the second switching tube M2 are both connected to the scanning signal line, where the data signal line is used for inputting data signals, and the scanning signal line is used for inputting switching signals.
实施时，数据缓存电路30可依据存储的电压驱动第二驱动管P1开启或者关断，以控制驱动电路20是否驱动发光件L发光。具体而言，在实施时将第一电源VDD电压设置为第二驱动管P1的关断电压，如将第一电源VDD设置为5V，将第二电源VSS设置为第二驱动管P1的导通电压，如将第二电源VSS设置为3.2V，使得数据缓存电路30锁存的数据逻辑1为第一电源VDD电源值，数据逻辑0为第二电源VSS电压值。当数据缓存电路30输出数据逻辑1时，第一电源VDD电压能够使第二驱动管P1关断，此时发光件L不发光；当数据缓存电路30输出数据逻辑0时，第二电源VSS电压能够使第二驱动管P1导通，电流电路10输出的电流经第一驱动管P0、第二驱动管P1流向发光件L，以驱动发光件L发光。During implementation, the data buffer circuit 30 can drive the second driving transistor P1 to turn on or off according to the stored voltage, so as to control whether the driving circuit 20 drives the light emitting element L to emit light. Specifically, the first power supply VDD voltage is set as the turn-off voltage of the second drive transistor P1 during implementation, for example, the first power supply VDD is set to 5V, and the second power supply VSS is set as the turn-on voltage of the second drive transistor P1. Voltage, such as setting the second power supply VSS to 3.2V, makes the data logic 1 latched by the data buffer circuit 30 be the power supply value of the first power supply VDD, and the data logic 0 is the voltage value of the second power supply VSS. When the data buffer circuit 30 outputs data logic 1, the voltage of the first power supply VDD can turn off the second drive tube P1, and at this time, the light-emitting element L does not emit light; when the data buffer circuit 30 outputs data logic 0, the voltage of the second power supply VSS The second drive transistor P1 can be turned on, and the current output by the current circuit 10 flows to the light-emitting element L through the first drive transistor P0 and the second drive transistor P1, so as to drive the light-emitting element L to emit light.
进一步地，第一开关管M1至第六开关管M6均为耐压值为0.9～1.8V的MOS管，其中，第一开关管M1、第二开关管M2、第五开关管M5和第六开关管M6均为NMOS管，第三开关管M3和第四开关管M4均为PMOS管。这里的由第三开关管M3的源极和第五开关管M5的漏极连接形成第一反相器的输出端，第三开关管M3的栅极与第五开关管M5的栅极连接形成输入端。第四开关管M4的栅极和第六开关管M6的栅极连接形成第二反相器的输入端，第四开关管M4的源极和第六开关管M6的漏极连接形成输出端。第六开关管M6的栅极与第二驱动管P1的栅极相连。Further, the first switching tube M1 to the sixth switching tube M6 are all MOS tubes with a withstand voltage of 0.9-1.8V, wherein the first switching tube M1, the second switching tube M2, the fifth switching tube M5 and the sixth switching tube The switching tube M6 is both an NMOS tube, and the third switching tube M3 and the fourth switching tube M4 are both PMOS tubes. Here, the source of the third switching tube M3 is connected to the drain of the fifth switching tube M5 to form the output terminal of the first inverter, and the gate of the third switching tube M3 is connected to the gate of the fifth switching tube M5 to form a input. The gate of the fourth switch M4 is connected to the gate of the sixth switch M6 to form an input terminal of the second inverter, and the source of the fourth switch M4 is connected to the drain of the sixth switch M6 to form an output terminal. The gate of the sixth switching transistor M6 is connected to the gate of the second driving transistor P1.
由于数据缓存电路30可依据存储的电压驱动第二驱动管P1开启或者关断，也就是说采用低耐压值的MOS管驱动高耐压值的MOS管，本实施例中，以采用低耐压值1.8V的MOS管驱动5V的PMOS管为最佳。这里 的由第三开关管M3的源极和第五开关管M5的漏极连接形成第一反相器的输出端，第三开关管M3的栅极与第五开关管M5的栅极连接形成输入端。第四开关管M4的栅极和第六开关管M6的栅极连接形成第二反相器的输入端，第四开关管M4的源极和第六开关管M6的漏极连接形成输出端。第六开关管M6的栅极与第二驱动管P1的栅极相连。Since the data buffer circuit 30 can drive the second drive transistor P1 to turn on or off according to the stored voltage, that is to say, a MOS transistor with a low withstand voltage value is used to drive a MOS transistor with a high withstand voltage value. It is best for a MOS tube with a voltage value of 1.8V to drive a 5V PMOS tube. Here, the source of the third switching tube M3 is connected to the drain of the fifth switching tube M5 to form the output terminal of the first inverter, and the gate of the third switching tube M3 is connected to the gate of the fifth switching tube M5 to form a input. The gate of the fourth switch M4 is connected to the gate of the sixth switch M6 to form an input terminal of the second inverter, and the source of the fourth switch M4 is connected to the drain of the sixth switch M6 to form an output terminal. The gate of the sixth switching transistor M6 is connected to the gate of the second driving transistor P1.
本发明通过采用低耐压值的MOS管构成的数据缓存电路30来存储数据并依据存储的数据驱动第二驱动管P1开启或者关断，也即采用低耐压值的MOS管驱动高耐压值的MOS管，可显著降低功耗。具体而言，由于在数据写入时电源电压越低，数据缓存电路30产生的功耗越小，因而低耐压值的MOS管构成的数据缓存电路30可显著减少功耗。同时，由于低耐压值的MOS管的尺寸显著小于高耐压值的MOS管，通常情况下，高耐压值的MOS管的尺寸比低耐压值的MOS管的尺寸大2～3倍，因而低耐压值的MOS管形成的数据缓存电路30的尺寸更小，可显著减少像素驱动电路的面积。The present invention stores data by using a data buffer circuit 30 composed of a MOS transistor with a low withstand voltage value and drives the second drive transistor P1 to turn on or off according to the stored data, that is, a MOS transistor with a low withstand voltage value is used to drive a high withstand voltage transistor. The value of the MOS tube can significantly reduce power consumption. Specifically, since the lower the power supply voltage is during data writing, the lower the power consumption of the data buffer circuit 30 is, so the data buffer circuit 30 composed of MOS transistors with low withstand voltage can significantly reduce power consumption. At the same time, since the size of the MOS tube with a low withstand voltage value is significantly smaller than that of a MOS tube with a high withstand voltage value, usually, the size of a MOS tube with a high withstand voltage value is 2 to 3 times larger than that of a MOS tube with a low withstand voltage value. Therefore, the size of the data buffer circuit 30 formed by the MOS transistor with low withstand voltage is smaller, which can significantly reduce the area of the pixel driving circuit.
另外，本发明通过采用低耐压值的MOS管驱动高耐压值的MOS管，如采用耐压值为1.8V的MOS管驱动耐压值为5V的MOS管，可在版图设计时无需设置需接入到0V的耐压值为5V的NMOS管，即：在版图设计时，在整个像素电路下做一个深N阱，此处的衬底电压为数据逻辑0时的第二电源VSS电压(非零值)，在N阱内的MOS管只有低耐压值的MOS管和高耐压值的PMOS管，而没有需要接入到0V的高耐压值的NMOS管。In addition, the present invention drives a MOS tube with a high withstand voltage by using a MOS tube with a low withstand voltage value. For example, a MOS tube with a withstand voltage value of 1.8V is used to drive a MOS tube with a withstand voltage value of 5V. It needs to be connected to an NMOS transistor with a withstand voltage of 5V that needs to be connected to 0V, that is, in the layout design, a deep N well is made under the entire pixel circuit, and the substrate voltage here is the second power supply VSS voltage when the data logic is 0. (non-zero value), the MOS tubes in the N well only have low withstand voltage MOS tubes and high withstand voltage PMOS tubes, but there is no NMOS tube with a high withstand voltage value that needs to be connected to 0V.
如图1所示，电流电路10包括第七开关管M7、第八开关管M8、第九开关管M9和恒流源I，其中，第七开关管M7与第八开关管M8连接于第一连接点，并且两者串联连接后连接于第一电源VDD和第二电源VSS之间，第七开关管M7的栅极与第一驱动管P0的栅极连接于第二连接点，第一连接点与第二连接点相连；第九开关管M9与恒流源I连接于第三连接点，并且两者串联连接后连接于第一电源VDD和第二电源VSS之间，第 八开关管M8的栅极与第九开关管M9的栅极连接于第四连接点，第三连接点与第四连接点相连。实施时，在发光阶段，电流电路10产生的恒定电流通过第一驱动管P0、第二驱动管P1流向发光件L，以使发光件L发光。电流电路10可为每个像素驱动电路提供稳定一致的电流。也即在第二驱动管P1打开时，电流由恒流源I控制，恒流源I可设置多个档级的电流，以便于使发光件L产生不同亮度的光。As shown in FIG. 1, the current circuit 10 includes a seventh switching tube M7, an eighth switching tube M8, a ninth switching tube M9 and a constant current source I, wherein the seventh switching tube M7 and the eighth switching tube M8 are connected to the first connection point, and the two are connected in series and connected between the first power supply VDD and the second power supply VSS, the gate of the seventh switching transistor M7 and the gate of the first driving transistor P0 are connected to the second connection point, and the first connection point is connected to the second connection point; the ninth switch tube M9 is connected to the third connection point with the constant current source I, and the two are connected in series and then connected between the first power supply VDD and the second power supply VSS; the eighth switch tube M8 and the gate of the ninth switching transistor M9 are connected to the fourth connection point, and the third connection point is connected to the fourth connection point. During implementation, in the lighting phase, the constant current generated by the current circuit 10 flows to the light-emitting element L through the first drive transistor P0 and the second drive transistor P1, so that the light-emitting element L emits light. The current circuit 10 can provide stable and consistent current for each pixel driving circuit. That is to say, when the second driving tube P1 is turned on, the current is controlled by the constant current source I, and the constant current source I can be set with multiple levels of current, so as to make the light-emitting element L generate light with different brightness.
结合图1和图2所示，像素驱动电路包括数据暂存电路40，其中，数据暂存电路40用于暂时存储数据，数据缓存电路30用于驱动第二驱动管P1的开启或者关断。本实施例中，数据暂存电路40和数据缓存电路30的结构相同，可参见上述数据缓存电路30结构，在此不再一一赘述。实施时，数据先存入数据暂存电路40中，在需要时从第一级缓存中读取数据并写入到数据缓存电路30中，数据缓存电路30依据数据驱动第二驱动管P1的开启或者关断，以控制驱动电路20控制发光件L是否发光。As shown in FIG. 1 and FIG. 2 , the pixel driving circuit includes a data temporary storage circuit 40 , wherein the data temporary storage circuit 40 is used for temporarily storing data, and the data buffer circuit 30 is used for driving the second driving transistor P1 to be turned on or off. In this embodiment, the structures of the temporary data storage circuit 40 and the data buffer circuit 30 are the same, and reference may be made to the structure of the data buffer circuit 30 described above, which will not be repeated here. During implementation, the data is first stored in the data temporary storage circuit 40, and when necessary, the data is read from the first-level cache and written into the data cache circuit 30, and the data cache circuit 30 drives the opening of the second drive transistor P1 according to the data. Or turn it off, so as to control the driving circuit 20 to control whether the light-emitting element L emits light.
进一步地，像素驱动电路包括锁存缓冲器50(Latch Buffer)，用于从数据暂存电路40中读取数据并存入数据缓存电路30中。本实施例中，每列像素对应一个锁存缓冲器50，也就是说每列的所有行像素共用一个锁存缓冲器50。通过共用一个锁存缓冲器50，可充分利用像素下方的芯片面积，使得晶圆利用最大化，同时可减少外部存储的压力，可在像素电路下可实现存储功能。Further, the pixel driving circuit includes a latch buffer 50 (Latch Buffer), which is used to read data from the data temporary storage circuit 40 and store it in the data buffer circuit 30. In this embodiment, each column of pixels corresponds to one latch buffer 50 , that is to say, all rows of pixels in each column share one latch buffer 50 . By sharing one latch buffer 50 , the chip area under the pixel can be fully utilized, maximizing the utilization of the wafer, and at the same time, the pressure on external storage can be reduced, and the storage function can be realized under the pixel circuit.
进一步地，数据暂存电路40中存入的数据以及通过锁存缓冲器50从第一缓冲电路中读取并存入数据缓存电路30中的数据，均是一整行同时操作的，也即每行数据同时存储数据暂存电路40中，或者锁存缓冲器50同时从第一缓冲电路中读取数据并同时写入到数据缓存电路30中。如每行有1024个像素，则每行有2048个数据缓存电路30，锁存缓冲器50为1024个。存数据时，每行像素所需的数据同时存入数据暂存电路40中，1024 个锁存缓冲器50同时对对应的数据暂存电路40中存储的数据进行读取，并将数据同时写入对应的数据缓存电路30中。Further, the data stored in the data temporary storage circuit 40 and the data read from the first buffer circuit and stored in the data buffer circuit 30 through the latch buffer 50 are all operated simultaneously for a whole row, that is, Each row of data is stored in the temporary data storage circuit 40 at the same time, or the latch buffer 50 reads data from the first buffer circuit and writes data into the data buffer circuit 30 at the same time. If each row has 1024 pixels, then each row has 2048 data buffer circuits 30 and 1024 latch buffers 50 . When storing data, the data required by each row of pixels is stored in the data temporary storage circuit 40 at the same time, and the 1024 latch buffers 50 simultaneously read the data stored in the corresponding data temporary storage circuit 40, and write the data simultaneously into the corresponding data buffer circuit 30.
本发明所述的像素驱动电路的工作原理如下：The working principle of the pixel driving circuit described in the present invention is as follows:
以存储节点A存入数据1为例。在向数据缓存电路30写数据时，首先，将扫描信号线置为低电平，此时第一开关管M1和第二开关管M2关断，进一步将第一数据线B0置1，第二数据线B1置0：其次，将扫描信号线置为高电平，此时第一开关管M1和第二开关管M2导通，存储节点B通过第二开关管M2向第二数据线B1放电，直至到达0电平，此时第五开关管M5截止，第一数据线B0通过第一开关管M1，第一电源VDD通过第三开关管M3对存储节点A充电至1电平，此时第六开关管M6导通；最后，将扫描信号线置低电平，第一开关管M1和第二开关管M2关断，此时存储节点A处于1电平状态，存储节点B处于0电平状态，输出的驱动电压为A点电压，A点电压为高时，第二驱动管P1关断，电流无法流向发光件L，此时发光件L不发光。Take storage node A storing data 1 as an example. When writing data to the data buffer circuit 30, firstly, set the scanning signal line to low level, at this time, the first switch tube M1 and the second switch tube M2 are turned off, further set the first data line B0 to 1, and the second Data line B1 is set to 0: secondly, the scanning signal line is set to high level, at this time, the first switch M1 and the second switch M2 are turned on, and the storage node B discharges to the second data line B1 through the second switch M2 , until it reaches 0 level, at this time the fifth switch tube M5 is turned off, the first data line B0 passes through the first switch tube M1, and the first power supply VDD charges the storage node A to 1 level through the third switch tube M3, at this time The sixth switching tube M6 is turned on; finally, the scanning signal line is set to a low level, and the first switching tube M1 and the second switching tube M2 are turned off. At this time, the storage node A is in a 1 level state, and the storage node B is in a 0 level state. In the flat state, the output driving voltage is the voltage at point A. When the voltage at point A is high, the second drive tube P1 is turned off, and the current cannot flow to the light-emitting element L. At this time, the light-emitting element L does not emit light.
以存储节点A存储入数据0为例。在向数据缓存电路30写数据时，首先，将扫描信号线置为低电平，此时第一开关管M1和第二开关管M2关断，进一步将第一数据线B0置0，第二数据线B1置1；其次，将扫描信号线置为高电平，此时第一开关管M1和第二开关管M2导通，存储节点A通过第一开关管M1向第一数据线B0放电，直至达到0电平，此时第六开关管M6截止，第二数据线B1通过第二开关管M2，第一电源VDD通过第四开关管M4，对存储节点B充电至1电平，第五开关管M5导通。最后，将扫描信号线置为低电平，第一开关管M1和第二开关管M2关断，此时存储节点A处于0电平状态，存储节点B处于1电平状态，输出的驱动电压为A点电压，A点电压为低时，第二驱动管P1导通，电流流向发光件L，此时发光件L发光。Take storage node A storing data 0 as an example. When writing data to the data buffer circuit 30, first, set the scanning signal line to low level, at this time, the first switching tube M1 and the second switching tube M2 are turned off, and the first data line B0 is further set to 0, and the second switching tube M2 is turned off. The data line B1 is set to 1; secondly, the scanning signal line is set to a high level, at this time the first switch M1 and the second switch M2 are turned on, and the storage node A discharges to the first data line B0 through the first switch M1 , until it reaches 0 level, at this time the sixth switch tube M6 is turned off, the second data line B1 passes through the second switch tube M2, the first power supply VDD passes through the fourth switch tube M4, and charges the storage node B to 1 level, the second The fifth switching tube M5 is turned on. Finally, the scanning signal line is set to low level, the first switching tube M1 and the second switching tube M2 are turned off, at this time, the storage node A is in the 0 level state, the storage node B is in the 1 level state, and the output driving voltage is the voltage at point A, when the voltage at point A is low, the second drive transistor P1 is turned on, and the current flows to the light-emitting element L, at this time the light-emitting element L emits light.
进一步地，数据缓存电路30存储的数据可读出，以供后续使用，如锁 存缓冲器50从数据暂存电路40中读取数据并写入到数据缓存电路30中等。读数据过程如下：Further, the data stored in the data cache circuit 30 can be read out for subsequent use, such as the latch buffer 50 reading data from the data temporary storage circuit 40 and writing it into the data cache circuit 30 and so on. The process of reading data is as follows:
以从数据缓存电路30读取1为例(存储节点A存储1，存储节点B存储0)。在读数据时，首先，将第一数据线B0和第二数据线B1预充电到1，此时扫描信号线置为低电平，第一开关管M1和第二开关管M2关断。其次，将扫描信号线置为高电平，第一开关管M1和第二开关管M2导通，第二数据线B1通过第二开关管M2、第六开关管M6迅速放电至0电平，第五开关管M5仍然截止，第一电源VDD通过第三开关管M3、第一开关管M1对第一数据线B0进行充电，使第一数据线B0处于1电平状态，第六开关管M6仍然导通。最后，将扫描信号线置为低电平，此时完成了从数据缓存电路30中读取出1。Take reading 1 from the data cache circuit 30 as an example (storage node A stores 1, and storage node B stores 0). When reading data, firstly, the first data line B0 and the second data line B1 are precharged to 1, at this time, the scanning signal line is set to low level, and the first switching tube M1 and the second switching tube M2 are turned off. Secondly, the scanning signal line is set to high level, the first switching tube M1 and the second switching tube M2 are turned on, and the second data line B1 is rapidly discharged to 0 level through the second switching tube M2 and the sixth switching tube M6, The fifth switching tube M5 is still off, the first power supply VDD charges the first data line B0 through the third switching tube M3 and the first switching tube M1, so that the first data line B0 is in a 1-level state, and the sixth switching tube M6 still on. Finally, the scan signal line is set to a low level, and at this time, the reading of 1 from the data buffer circuit 30 is completed.
以从数据缓存电路30读取0为例(存储节点A存储0，存储节点B存储1)。在读数据时，首先，将第一数据线B0和第二数据线B1预充电到1，此时扫描信号线置为低电平，第一开关管M1和第二开关管M2关断。其次，将扫描信号线置为高电平，第一开关管M1和第二开关管M2导通，第一数据线B0通过第一开关管M1、第五开关管M5迅速放电至0电平，第六开关管M6仍然截止，第一电源VDD通过第四开关管M4、第二开关管M2对第二数据线B1进行充电，使第二数据信号处于1电平状态，第五开关管M5仍然导通。最后，将扫描信号线置为低电平，此时完成了从数据缓存电路30中读取出0。Take reading 0 from the data cache circuit 30 as an example (the storage node A stores 0, and the storage node B stores 1). When reading data, firstly, the first data line B0 and the second data line B1 are precharged to 1, at this time, the scanning signal line is set to low level, and the first switching tube M1 and the second switching tube M2 are turned off. Secondly, the scanning signal line is set to high level, the first switching tube M1 and the second switching tube M2 are turned on, and the first data line B0 is rapidly discharged to 0 level through the first switching tube M1 and the fifth switching tube M5, The sixth switch tube M6 is still off, the first power supply VDD charges the second data line B1 through the fourth switch tube M4 and the second switch tube M2, so that the second data signal is in a 1-level state, and the fifth switch tube M5 is still conduction. Finally, the scan signal line is set to low level, and at this time, reading 0 from the data buffer circuit 30 is completed.
本发明还揭示了一种显示屏，具有上述所述的像素驱动电路。The present invention also discloses a display screen, which has the above-mentioned pixel driving circuit.
本发明通过采用低耐压值的MOS管构成的数据缓存电路30驱动高耐压值的MOS管的开启或者关断，可有效减少像素驱动电路的面积及功耗，同时，采用PMOS管作为驱动管，也可显著减少像素驱动电路的面积及功耗。The present invention can effectively reduce the area and power consumption of the pixel driving circuit by using the data buffer circuit 30 composed of a MOS transistor with a low withstand voltage value to drive the MOS transistor with a high withstand voltage value to be turned on or off. Tube, can also significantly reduce the area and power consumption of the pixel driving circuit.
本发明的技术内容及技术特征已揭示如上，然而熟悉本领域的技术人 员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰，因此，本发明保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求所涵盖。The technical contents and technical characteristics of the present invention have been disclosed above, but those skilled in the art may still make various replacements and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to The content disclosed in the embodiment should include various replacements and modifications that do not depart from the present invention, and are covered by the claims of this patent application.

Claims (12)

  1. 一种像素驱动电路，其特征在于，所述像素驱动电路包括：A pixel driving circuit, characterized in that the pixel driving circuit comprises:
    发光件，用于发光；A luminous part for emitting light;
    电流电路，用于产生恒定的电流；a current circuit for generating a constant current;
    驱动电路，用于驱动发光件发光，其包括串联连接于第一电源和第二电源之间的第一驱动管和第二驱动管，所述第一驱动管的栅极与电流电路相连，所述第一驱动管通过第二驱动管与发光件相连，所述第一驱动管和第二驱动管的耐压值均为3.2～5V；The drive circuit is used to drive the light-emitting element to emit light, which includes a first drive tube and a second drive tube connected in series between the first power supply and the second power supply, the grid of the first drive tube is connected to the current circuit, so The first drive tube is connected to the light-emitting element through the second drive tube, and the withstand voltage values of the first drive tube and the second drive tube are both 3.2-5V;
    数据缓存电路，用于根据存储的数据控制第二驱动管的开启或者关断，其包括第一开关管至第六开关管，第三开关管和第五开关管串联连接于第一电源和第二电源之间，形成第一反相器，第四开关管和第六开关管串联连接于第一电源和第二电源之间，形成第二反相器，所述第一反相器的输入端与第二反相器的输出端相连，输出端与第二反相器的输入端相连，且输出端通过第一开关管连接第一数据线，所述第二反相器的输出端通过第二开关管连接第二数据线，所述第六开关管的栅极与第二驱动管的栅极相连，其中，第一开关管至第六开关管的耐压值均为0.9～1.8V。The data buffer circuit is used to control the turn-on or turn-off of the second drive tube according to the stored data, which includes a first switch tube to a sixth switch tube, and the third switch tube and the fifth switch tube are connected in series to the first power supply and the first switch tube. Between the two power supplies, a first inverter is formed, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply, forming a second inverter, and the input of the first inverter The terminal is connected to the output terminal of the second inverter, the output terminal is connected to the input terminal of the second inverter, and the output terminal is connected to the first data line through the first switch tube, and the output terminal of the second inverter is connected through the The second switch tube is connected to the second data line, the gate of the sixth switch tube is connected to the gate of the second drive tube, wherein the withstand voltage values of the first switch tube to the sixth switch tube are all 0.9-1.8V .
  2. 根据权利要求1所述的像素驱动电路，所述第一驱动管和第二驱动管均为PMOS管。According to the pixel driving circuit according to claim 1, both the first driving transistor and the second driving transistor are PMOS transistors.
  3. 根据权利要求1所述的像素驱动电路，所述第一电源的电压大于第二电源的电压，且第二电源的电压为非零。The pixel driving circuit according to claim 1, the voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is non-zero.
  4. 根据权利要求1所述的像素驱动电路，所述第一开关管、第二开关管、第五开关管和第六开关管均为NMOS管，所述第三开关管和第四开关管均为PMOS管。According to the pixel driving circuit according to claim 1, the first switch tube, the second switch tube, the fifth switch tube and the sixth switch tube are all NMOS tubes, and the third switch tube and the fourth switch tube are all PMOS tube.
  5. 根据权利要求1所述的像素驱动电路，所述电流电路包括恒流源及第七开关管至第九开关管，其中，第七开关管和第八开关管串联连接于第一电源和第二电源之间，且所述第七开关管的栅极与第二驱动管的栅极相连，所述第七开关管的源极与栅极相连，第九开关管和恒流源串联连接于第一电源和第二电源之间，且所述第九开关管的源极与栅极相连。The pixel drive circuit according to claim 1, the current circuit includes a constant current source and the seventh switch tube to the ninth switch tube, wherein the seventh switch tube and the eighth switch tube are connected in series to the first power supply and the second switch tube. Between the power supply, and the grid of the seventh switching tube is connected to the grid of the second driving tube, the source of the seventh switching tube is connected to the grid, and the ninth switching tube and the constant current source are connected in series to the second driving tube. Between the first power supply and the second power supply, and the source of the ninth switch tube is connected to the gate.
  6. 根据权利要求1所述的像素驱动电路，所述像素驱动电路还包括：The pixel driving circuit according to claim 1, further comprising:
    数据暂存电路，与数据缓存电路通信连接，用于暂时存储写入至数据缓存电路中的数据。The data temporary storage circuit is communicatively connected with the data buffer circuit, and is used for temporarily storing the data written into the data buffer circuit.
  7. 根据权利要求6所述的像素驱动电路，所述数据暂存电路的结构与数据缓存电路的结构相同。According to the pixel driving circuit according to claim 6, the structure of the temporary data storage circuit is the same as that of the data cache circuit.
  8. 根据权利要求6所述的像素驱动电路，所述像素驱动电路还包括：The pixel driving circuit according to claim 6, further comprising:
    锁存缓冲器，与所述数据缓存电路和数据暂存电路均通信连接，用于将数据暂存电路中存储的数据读出并写入至数据缓存电路中。The latch buffer is communicatively connected with both the data buffer circuit and the temporary data storage circuit, and is used for reading and writing the data stored in the temporary data storage circuit into the data buffer circuit.
  9. 根据权利要求8所述的像素驱动电路，每列像素设置一所述锁存缓冲器。According to the pixel driving circuit according to claim 8, one latch buffer is provided for each column of pixels.
  10. 根据权利要求8所述的像素驱动电路，每个所述锁存缓冲器同时将对应数据暂存电路中的数据读出并同时存入对应的数据缓存电路中。According to the pixel driving circuit according to claim 8, each of the latch buffers simultaneously reads out the data in the corresponding data temporary storage circuit and stores it in the corresponding data buffer circuit at the same time.
  11. 一种基于权利要求1～10任意一项所述的像素驱动电路的像素驱动方法，其特征在于，像素驱动方法包括如下步骤：A pixel driving method based on the pixel driving circuit according to any one of claims 1 to 10, characterized in that the pixel driving method comprises the following steps:
    数据缓存电路输出逻辑为1时，输出的第一电源电压控制第二驱动管关断，发光件不发光；When the output logic of the data buffer circuit is 1, the output first power supply voltage controls the second drive tube to be turned off, and the light-emitting element does not emit light;
    数据缓存电路输出逻辑为0时，输出的第二电源电压控制第二驱动管导通，发光件发光。When the output logic of the data buffer circuit is 0, the output second power supply voltage controls the second driving transistor to turn on, and the light-emitting element emits light.
  12. 一种显示屏，其特征在于，包括权利要求1～10任意一项所述的像素驱动电路。A display screen, characterized by comprising the pixel drive circuit according to any one of claims 1-10.
PCT/CN2022/087345 2021-10-27 2022-04-18 Pixel driving circuit and driving method therefor, and display screen WO2023071078A1 (en)

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CN109961736A (en) * 2019-04-30 2019-07-02 云谷（固安）科技有限公司 A kind of digital drive pixel circuit and its driving method and display device
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CN101470310A (en) * 2007-10-15 2009-07-01 索尼株式会社 Liquid crystal display device and image displaying method of liquid crystal display device
CN101261810A (en) * 2008-04-21 2008-09-10 上海大学 A pixel driving circuit in silicon base organic luminescent display device
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