WO2023070634A1 - 一种晶体管、集成电路以及电子设备 - Google Patents

一种晶体管、集成电路以及电子设备 Download PDF

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Publication number
WO2023070634A1
WO2023070634A1 PCT/CN2021/127784 CN2021127784W WO2023070634A1 WO 2023070634 A1 WO2023070634 A1 WO 2023070634A1 CN 2021127784 W CN2021127784 W CN 2021127784W WO 2023070634 A1 WO2023070634 A1 WO 2023070634A1
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WIPO (PCT)
Prior art keywords
source region
conductor
region
substrate
transistor
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PCT/CN2021/127784
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English (en)
French (fr)
Inventor
陆叶
万景
吴振华
陈颖欣
许俊豪
侯朝昭
吴颖
董耀旗
王嘉乐
Original Assignee
华为技术有限公司
复旦大学
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Application filed by 华为技术有限公司, 复旦大学 filed Critical 华为技术有限公司
Priority to PCT/CN2021/127784 priority Critical patent/WO2023070634A1/zh
Priority to CN202180101044.1A priority patent/CN117882177A/zh
Publication of WO2023070634A1 publication Critical patent/WO2023070634A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a transistor, an integrated circuit and an electronic device.
  • MOSFETs metal-oxide-semiconductor field effect transistors Due to the limitation of the device principle of MOSFETs (Boltzmann distribution of carriers), room temperature The theoretical minimum value of the sub-threshold swing (SS) of the lower MOSFET is 60mV/dec. A smaller value means that the switching rate of the MOSFET on and off is faster.
  • CMOS complementary metal-oxide-semiconductor
  • Embodiments of the present application provide a transistor, an integrated circuit, and an electronic device, which relate to the field of semiconductor technology and can reduce the subthreshold swing of the transistor.
  • a transistor in a first aspect, includes: a substrate; a first source region, a second source region, a channel and a drain region are sequentially arranged on the substrate along a first direction parallel to the substrate; an insulating layer is arranged on the channel; an insulating layer is arranged on the insulating layer.
  • the first gate; the drain region is provided with a drain; the first source region is provided with a source; the transistor also includes a conductor, wherein the first source region is in contact with the second source region to form a contact surface, and the conductor and the first source region and the second source region, and the contact surface is perpendicular to the conductor.
  • an energy band gap is formed between the first source and the second source, when the transistor is in a subthreshold state , the hot carriers injected from the source into the first source region are suppressed when passing through the energy band gap, so that only a part of the hot carriers can tunnel to the channel, and then diffuse from the channel to the drain region, A sub-threshold current is formed, and the sub-threshold current is much smaller than that of a normal MOSFET.
  • a buried oxide layer is further disposed on the substrate, and the first source region, the second source region, the channel and the drain region are disposed on the buried oxide layer.
  • the aforementioned transistors are provided on a silicon-on-insulator substrate.
  • the conductor at least includes one or more of the following parts: a first part, a second part, a third part and a fourth part; the first part of the conductor is disposed between the first source region and the buried oxide layer; the second part of the conductor A part is arranged above the first source region; a third part of the conductor is arranged on the buried oxide layer, and is arranged on the first side of the first source region along the first direction; a fourth part of the conductor is arranged on the buried oxide layer , and arranged on the second side of the first source region along the first direction.
  • the conductors in the transistors provided on the silicon-on-insulator substrate can select one or more parts of the conductors according to actual needs.
  • the side of the substrate away from the source is also provided with a second gate.
  • the presence of the second gate makes the corresponding speed of the transistor faster.
  • a first isolation groove and a second isolation groove are arranged in the substrate, and the openings of the first isolation groove and the second isolation groove face the same side of the substrate; the first source region, the second source region, the channel and The drain region is disposed between the first isolation groove and the second isolation groove.
  • the aforementioned transistors are provided on a bulk silicon substrate.
  • the conductor includes one or more of the following parts: a first part, a second part, a third part and a fourth part; the first part of the conductor is arranged between the first source region and the substrate; the second part of the conductor is arranged Above the first source region; the third part of the conductor is arranged on the substrate and along the first direction, arranged on the first side of the first source region; the fourth part of the conductor is arranged on the substrate and along the first direction One direction is arranged on the second side of the first source region.
  • the conductors in the transistors provided on the bulk silicon substrate can be selected according to actual needs, and one or more parts of the conductors can be selected.
  • the transistor further includes a dielectric disposed on the substrate, the dielectric is located between the first source region and the second source region; the conductor is in contact with the first source region, the dielectric and the second source region, and the dielectric is perpendicular to the conductor.
  • a dielectric disposed on the substrate, the dielectric is located between the first source region and the second source region; the conductor is in contact with the first source region, the dielectric and the second source region, and the dielectric is perpendicular to the conductor.
  • the material of the medium includes at least one or more of the following: silicon dioxide, titanium dioxide, and aluminum oxide.
  • the width of the second source region is equal to that of the drain region.
  • the second source region and the drain region are symmetrical with respect to the gate, which is favorable for manufacturing the transistor in a process.
  • a gate metal layer is further disposed on the first gate.
  • a first sidewall and a second sidewall are further arranged on the trench along the first direction, and the insulating layer and the first grid are located between the first sidewall and the second sidewall, wherein the first sidewall and the second sidewall The two source regions are in contact, and the second side wall is in contact with the drain region.
  • the embodiment of the present application provides a conductor material, and the conductor material includes at least one or more of the following: nickel silicide, titanium silicide, cobalt silicide, titanium, tungsten, titanium nitride, and graphene.
  • dopants are provided in the first source region, the second source region and the drain region, the dopant provided in the second source region and the drain region is N type, and the dopant provided in the first source region is P type; or, the dopant provided in the second source region and the drain region is P-type, and the dopant provided in the first source region is N-type.
  • the transistor may be an N-type transistor or a P-type transistor.
  • the dopant concentration of one or more of the first source region, the second source region and the drain region is greater than or equal to 1e19 atoms/cm 3 .
  • the material of the substrate includes at least one or more of the following: silicon, silicon germanium, gallium nitride, and indium gallium arsenic.
  • the material of the buried oxide layer includes at least one or more of the following: silicon dioxide, aluminum oxide, and hafnium oxide.
  • the material of the channel at least includes one or more of the following: silicon, silicon germanium, gallium nitride, and indium gallium arsenide.
  • the material of the insulating layer includes at least one or more of the following: silicon dioxide, aluminum oxide, and hafnium oxide.
  • the material of the drain electrode at least includes one or more of the following: aluminum, nickel, titanium, and metal silicide.
  • the material of the source electrode includes at least one or more of the following: aluminum, nickel, titanium, and metal silicide.
  • the material of the first gate at least includes one or more of the following: polysilicon and metal.
  • the material of the gate metal layer at least includes one or more of the following: aluminum, nickel, titanium, and metal silicide.
  • the material of the first sidewall includes at least one or more of the following: silicon dioxide, silicon nitride, silicon oxycarbide and silicon carbonitride.
  • the material of the second sidewall includes at least one or more of the following: silicon dioxide, silicon nitride, silicon oxycarbide and silicon carbonitride.
  • the material of the second gate includes at least one or more of the following: aluminum, nickel, titanium, and metal silicide.
  • the substrate is not provided with dopants, or the substrate is provided with dopants, and the concentration of the doped region is greater than or equal to 1e15 atoms/cm3 and less than or equal to 1e17 atoms/cm3.
  • the type of the dopant in the channel setting is the same as the type of the dopant in the first source region.
  • the thickness of the buried oxide layer is greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.
  • the thickness of the channel is greater than or equal to 5 nanometers and less than or equal to 500 nanometers.
  • the thickness of the insulating layer is greater than or equal to 1 nanometer and less than or equal to 30 nanometers.
  • the thickness of the first gate is greater than or equal to 10 nanometers and less than or equal to 500 nanometers.
  • the thickness of the medium is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
  • an integrated circuit in a second aspect, includes a packaging structure and one or more transistors according to any one of the above first aspect, and the transistors are packaged inside the packaging structure.
  • an electronic device in a third aspect, includes a printed circuit board and the integrated circuit as described in the second aspect above, and the integrated circuit is coupled to the printed circuit board.
  • a method for preparing a transistor comprising the following steps: forming a buried oxide layer on a substrate; forming a channel layer extending along a first direction on the buried oxide layer; forming a channel layer extending along the first direction on the channel layer.
  • An insulating layer extending in two directions, wherein the first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the buried oxide layer; making a first gate covering the insulating layer; implanting doped dopant into the channel layer Impurities form a first source region, a second source region, and a drain region; a drain is formed on the drain region, and a source is formed on the first source region; a conductor is formed, wherein the first source region and the second source region are contacted to form In the contact surface, the conductor is in contact with the first source region and the second source region, and the contact surface is perpendicular to the conductor.
  • forming the conductor includes: forming a channel layer extending along a first direction on the buried oxide layer, before forming a first part of the conductor on the buried oxide layer, wherein the channel layer covers the first part; and/or, A drain is made on the drain region, a source is made on the first source region, and then at least one or more of the following parts of the conductor are made: the second part, the third part and the fourth part; the second part of the conductor is arranged on the first above a source region; the third part of the conductor is disposed on the buried oxide layer and along the first direction on the first side of the first source region; the fourth part of the conductor is disposed on the buried oxide layer and along the first direction One direction is arranged on the second side of the first source region.
  • implanting dopants into the channel layer to form a first source region, a second source region, and a drain region specifically includes: implanting N-type dopants into the channel layer to form a second source region and a drain region; The channel layer is implanted with P-type dopants to form the first source region; or, the channel layer is implanted with P-type dopants to form the second source region and the drain region; the channel layer is implanted with N-type dopants to form first source area.
  • the method further includes: forming a gate metal layer on the first gate.
  • the first gate covering the insulating layer also includes: making a first sidewall and a second sidewall on the channel layer along the first direction, and the insulating layer and the first gate are located between the first sidewall and the second sidewall. Between the second sidewalls, the first sidewall is in contact with the second source region, and the second sidewall is in contact with the drain region.
  • the method further includes: forming a second gate on the side of the substrate away from the source.
  • fabricating the drain on the drain region, and fabricating the source on the first source region further includes: etching and forming a groove in the contact area between the first source region and the second source region; making a groove in the groove medium; making the conductor specifically includes: making a conductor on the medium; the medium is located between the first source region and the second source region; the conductor is in contact with the first source region, the medium and the second source region, and the medium is perpendicular to the conductor.
  • a method for manufacturing a transistor comprising the following steps: forming a first isolation groove and a second isolation groove on a substrate, the openings of the first isolation groove and the second isolation groove facing the same side of the substrate; Fabricate an insulating layer extending along the second direction on the substrate; fabricate a gate covering the insulating layer; inject carrier-providing dopants into the substrate to form a first source region and a second source region extending along the first direction And the drain region, the second source region is in contact with the first source region to form a contact surface, the drain region is not in contact with the second source region, and the gate is located between the drain region and the second source region, wherein the first direction is perpendicular to the second direction , and the plane formed by the first direction and the second direction is parallel to the substrate; the drain is made on the drain region, and the source is made on the first source region; a conductor is made, and the conductor is in contact with the first source region and the second source region , and
  • making the conductor includes: making at least one or more of the following parts of the conductor: a first part, a second part, a third part and a fourth part; the first part of the conductor is disposed between the first source region and the substrate; The second part of the conductor is arranged above the first source region; the third part of the conductor is arranged on the substrate, and is arranged on the first side of the first source region along the first direction; the fourth part of the conductor is arranged on the substrate and disposed on the second side of the first source region along the first direction.
  • injecting carrier-providing dopants into the substrate to form the first source region, the second source region, and the drain region specifically includes: implanting N-type dopants into the substrate to form the second source region and the drain region region; implant P-type dopants into the substrate to form a first source region; or implant P-type dopants into the substrate to form a second source region and a drain region; implant N-type dopants into the substrate to form first source area.
  • the method further includes: forming a gate metal layer on the gate.
  • the gate covering the insulating layer also includes: fabricating a first sidewall and a second sidewall along the first direction on the channel, and the insulating layer and the gate are located between the first sidewall and the second sidewall , wherein the first sidewall is in contact with the second source region, and the second sidewall is in contact with the drain region.
  • fabricating the drain on the drain region, and fabricating the source on the first source region further includes: etching and forming a groove in the contact area between the first source region and the second source region; making a groove in the groove medium; making the conductor specifically includes: making the conductor on the medium; wherein the conductor is in contact with the first source region, the medium and the second source region, and the medium is perpendicular to the conductor.
  • FIG. 1 is a schematic structural diagram of a terminal provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an NMOS provided in Embodiment 1 of the present application.
  • FIG. 4 is an energy level structure diagram of an NMOS provided in Embodiment 1 of the present application.
  • FIG. 5 is a graph showing the change of the drain current Id of the NMOS with the gate voltage Vg provided by Embodiment 1 of the present application;
  • FIG. 6 is a schematic diagram of the first structure of the transistor provided in Embodiment 2 of the present application.
  • Fig. 7 is the energy level structure diagram 1 of the transistor provided by Embodiment 2 of the present application.
  • Fig. 8 is the energy level structure diagram 2 of the transistor provided by Embodiment 2 of the present application.
  • FIG. 9 is a graph showing the change of the drain current Id of the transistor with the gate voltage Vg according to Embodiment 2 of the present application.
  • FIG. 10 is a schematic structural diagram of the first source region and the second source region in the transistor provided in Embodiment 2 of the present application;
  • FIG. 11 is a schematic diagram of the second structure of the transistor provided in Embodiment 2 of the present application.
  • FIG. 12 is a schematic diagram of the third structure of the transistor provided in Embodiment 2 of the present application.
  • FIG. 13 provides a schematic diagram of the first structure of the transistor in Embodiment 3 of the present application.
  • FIG. 14 is a schematic structural diagram of the first source region and the second source region in the transistor provided by Embodiment 3 of the present application;
  • FIG. 15 is a schematic diagram of the second structure of the transistor provided in Embodiment 3 of the present application.
  • FIG. 16 is a schematic diagram of a third structure of a transistor provided in Embodiment 3 of the present application.
  • FIG. 17 is a schematic flow chart of a method for preparing a transistor provided in Embodiment 2 of the present application.
  • FIG. 18 is a first structural schematic diagram of a transistor in the method for manufacturing a transistor provided in Embodiment 2 of the present application;
  • FIG. 19 is a second structural schematic diagram of a transistor in the method for manufacturing a transistor provided in Embodiment 2 of the present application.
  • FIG. 20 is a schematic diagram three of the structure of the transistor in the method for preparing the transistor provided in the second embodiment of the present application;
  • Fig. 21 is a schematic diagram 4 of the structure of the transistor in the method for preparing the transistor provided in the second embodiment of the present application;
  • FIG. 22 is the fifth structural schematic diagram of the transistor in the transistor manufacturing method provided in the second embodiment of the present application.
  • FIG. 23 is a sixth structural schematic diagram of a transistor in the method for manufacturing a transistor provided in Embodiment 2 of the present application.
  • FIG. 24 is a schematic structural diagram VII of the transistor in the transistor manufacturing method provided in Embodiment 2 of the present application.
  • FIG. 25 is the eighth structural schematic diagram of the transistor in the method for preparing the transistor provided in the second embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of a transistor in the transistor manufacturing method provided in Embodiment 2 of the present application (nine);
  • FIG. 27 is a schematic flowchart of a method for preparing a transistor provided in Embodiment 3 of the present application.
  • FIG. 28 is a first structural schematic diagram of a transistor in the transistor manufacturing method provided in Embodiment 3 of the present application.
  • FIG. 29 is the second structural schematic diagram of the transistor in the method for preparing the transistor provided in Embodiment 3 of the present application.
  • FIG. 30 is a schematic diagram of the third structure of the transistor in the method for preparing the transistor provided in the third embodiment of the present application.
  • FIG. 31 is a fourth structural schematic diagram of a transistor in the transistor manufacturing method provided in Embodiment 3 of the present application.
  • FIG. 32 is the fifth structural schematic diagram of the transistor in the transistor manufacturing method provided in the third embodiment of the present application.
  • FIG. 33 is a sixth structural schematic diagram of the transistor in the transistor manufacturing method provided in Embodiment 3 of the present application.
  • FIG. 34 is a seventh structural schematic diagram of a transistor in the transistor manufacturing method provided in Embodiment 3 of the present application.
  • a semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; among them, a semiconductor includes intrinsic semiconductors and impurity semiconductors.
  • a semiconductor doped with a certain amount of dopant is called an impurity semiconductor or an extrinsic semiconductor.
  • the dopant doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons), and the dopant doped in it can provide electronic impurities (such as 5-valent phosphorus)
  • the impurity semiconductor doped with a dopant that provides hole impurities is also called a hole semiconductor or P (positive, positive) type
  • doping can improve the conductivity of intrinsic semiconductors.
  • the energy bands of a semiconductor include a valence band Ev, a forbidden band, and a conduction band Ec.
  • the electrons in the valence band Ev are also called bound electrons. These electrons are strongly bound by the nucleus.
  • the electrons in the valence band Ev have low electron energy and hardly participate in conduction.
  • the electrons in the conduction band Ec are also called free electrons.
  • the electron energy of the electrons in the conduction band Ec is higher than that of the electrons in the valence band Ev, and the electrons in the conduction band Ec participate in conduction.
  • the conduction band Ec and the valence band Ev are continuous energy poles.
  • the distance between the bottom of the conduction band and the top of the valence band is called the forbidden band, and there is a Fermi level in the forbidden band.
  • the Fermi level of the semiconductor is between the conduction band Ec and the valence band Ev, wherein the Fermi level of the intrinsic semiconductor is between the conduction band Ec and the valence band Ev, and the Fermi level of the P-type semiconductor is close to the valence band Ev,
  • the Fermi level of N-type semiconductors is close to the conduction band Ec.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • words such as "first" and "second” do not limit the quantity and order.
  • the technical solutions of the present application can be applied to electronic devices, which are different types of terminals such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices.
  • the electronic equipment may also be devices such as chips and processors used in the above electronic equipment.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • FIG. 1 shows a schematic structural diagram of a terminal 100 .
  • the terminal 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 190 and display screen 191, etc.
  • a processor 110 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 190 and display screen 19
  • the structure shown in the embodiment of the present application does not constitute a specific limitation on the terminal 100 .
  • the terminal 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processing unit
  • GPU graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • baseband processor baseband processor
  • neural network processor neural-network processing unit
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is a cache memory.
  • the memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be directly recalled from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thereby improving the efficiency of the system.
  • processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input and output (general-purpose input/output, GPIO) interface, subscriber identity module (subscriber identity module, SIM) interface, and /or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input and output
  • subscriber identity module subscriber identity module
  • SIM subscriber identity module
  • USB universal serial bus
  • the charging management module 140 is configured to receive a charging input from a charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 140 can receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 may receive wireless charging input through the wireless charging coil of the terminal 100 . While the charging management module 140 is charging the battery 142 , it can also supply power to the terminal through the power management module 141 .
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the power management module 141 receives the input from the battery 142 and/or the charging management module 140 to provide power for the processor 110 , the internal memory 121 , the display screen 191 , the camera 190 , and the wireless communication module 160 .
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, and battery health status (leakage, impedance).
  • the power management module 141 may also be disposed in the processor 110 .
  • the power management module 141 and the charging management module 140 may also be set in the same device.
  • the wireless communication function of the terminal 100 can be realized by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in terminal 100 may be used to cover single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas.
  • Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network.
  • the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the terminal 100 .
  • the mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (low noise amplifier, LNA) and the like.
  • the mobile communication module 150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and send them to the modem processor for demodulation.
  • the mobile communication module 150 can also amplify the signals modulated by the modem processor, and convert them into electromagnetic waves through the antenna 1 for radiation.
  • at least part of the functional modules of the mobile communication module 150 may be set in the processor 110 .
  • at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be set in the same device.
  • a modem processor may include a modulator and a demodulator.
  • the modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator sends the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low-frequency baseband signal is passed to the application processor after being processed by the baseband processor.
  • the application processor outputs sound signals through audio equipment (not limited to speaker 170A, receiver 170B, etc.), or displays images or videos through display screen 191 .
  • the modem processor may be a stand-alone device.
  • the modem processor may be independent from the processor 110, and be set in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide wireless local area networks (wireless local area networks, WLAN) (such as wireless fidelity (Wi-Fi) network), bluetooth (bluetooth, BT), global navigation satellite system, etc. (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions.
  • the wireless communication module 160 may be one or more devices integrating one or more communication processing modules.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency-modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110 , frequency-modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.
  • the antenna 1 of the terminal 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the terminal 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and/or IR technology, etc.
  • the GNSS can include global positioning system (global positioning system, GPS), global navigation satellite system (global navigation satellite system, GLONASS), Beidou satellite navigation system (beidou navigation satellite system, BDS), quasi-zenith satellite system (quasi- zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).
  • global positioning system global positioning system, GPS
  • global navigation satellite system global navigation satellite system
  • GLONASS global navigation satellite system
  • Beidou satellite navigation system beidou navigation satellite system, BDS
  • quasi-zenith satellite system quasi-zenith satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite based augmentation systems
  • the terminal 100 realizes the display function through the GPU, the display screen 191 , and the application processor.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 191 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.
  • the display screen 191 is used to display images, videos and the like.
  • the display screen 191 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED), etc.
  • the terminal 100 may include 1 or N display screens 191, where N is a positive integer greater than 1.
  • the terminal 100 can realize the shooting function through the ISP, the camera 190 , the video codec, the GPU, the display screen 191 and the application processor.
  • the ISP is used for processing data fed back by the camera 190 .
  • the light is transmitted to the photosensitive element of the camera through the lens, and the optical signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be located in the camera 190 .
  • Camera 190 is used to capture still images or video.
  • the object generates an optical image through the lens and projects it to the photosensitive element.
  • the photosensitive element may be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor.
  • CMOS complementary metal-oxide-semiconductor
  • the photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal.
  • the ISP outputs the digital image signal to the DSP for processing.
  • DSP converts digital image signals into standard RGB, YUV and other image signals.
  • the terminal 100 may include 1 or N cameras 190, where N is a positive integer greater than 1.
  • the external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal 100.
  • the external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. Such as saving music, video and other files in the external memory card.
  • the internal memory 121 may be used to store one or more computer programs including instructions.
  • the processor 110 may execute the above-mentioned instructions stored in the internal memory 121, so that the terminal 100 executes various functional applications, data processing, and the like.
  • the internal memory 121 may include an area for storing programs and an area for storing data.
  • the stored program area can store an operating system; the stored program area can also store one or more application programs (such as a gallery, contacts, etc.) and the like.
  • the data storage area can store data created during the use of the terminal 100 (such as photos, contacts, etc.) and the like.
  • the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (universal flash storage, UFS) and the like.
  • the processor 110 enables the terminal 100 to execute various functional applications and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.
  • the terminal 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, and an application processor. Such as music playback, recording, etc.
  • the audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signal.
  • the audio module 170 may also be used to encode and decode audio signals.
  • the audio module 170 may be set in the processor 110 , or some functional modules of the audio module 170 may be set in the processor 110 .
  • Speaker 170A also referred to as a "horn" is used to convert audio electrical signals into sound signals. Terminal 100 can listen to music through speaker 170A, or listen to hands-free calls.
  • Receiver 170B also called “earpiece” is used to convert audio electrical signals into sound signals.
  • the receiver 170B can be placed close to the human ear to listen to the voice.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals.
  • the user can put his mouth close to the microphone 170C to make a sound, and input the sound signal to the microphone 170C.
  • the terminal 100 may be provided with one or more microphones 170C.
  • the terminal 100 may be provided with two microphones 170C, which may also implement a noise reduction function in addition to collecting sound signals.
  • the terminal 100 can also be equipped with three, four or more microphones 170C to realize sound signal collection, noise reduction, identify sound sources, realize directional recording functions, and the like.
  • the earphone interface 170D is used for connecting wired earphones.
  • the earphone interface 170D can be a USB interface 130, or a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.
  • OMTP open mobile terminal platform
  • CTIA cellular telecommunications industry association of the USA
  • the sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.
  • a touch sensor is also referred to as a "touch device”.
  • the touch sensor can be arranged on the display screen 191, and the touch sensor and the display screen 191 form a touch screen, also called “touch screen”.
  • the touch sensor is used to detect a touch operation on or near it.
  • the touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.
  • Visual output related to the touch operation may be provided through the display screen.
  • a touch panel with a touch sensor array formed by a plurality of touch sensors may also be installed on the surface of the display panel in a hanging form.
  • the location of the touch sensor and the display screen 191 may also be different.
  • the form of the touch sensor is not limited, for example, it may be a capacitor or a piezoresistor.
  • the above-mentioned terminal 100 may further include one or more components such as keys, motors, indicators, and a subscriber identification module (subscriber identification module, SIM) card interface, which is not limited in this embodiment of the present application.
  • SIM subscriber identification module
  • an embodiment of the present application provides an integrated circuit 20 including a transistor 21 and a packaging structure 22 , wherein the transistor 21 is packaged inside the packaging structure 22 .
  • the package structure 22 specifically includes: a heat dissipation substrate 221, wherein in order to improve the conductivity and heat dissipation of the heat dissipation substrate 221, the heat dissipation substrate 221 can be made of a composite material, such as a laminate formed of copper Cu/molybdenum Mo/copper Cu Structure; Transistor 21 is bonded on heat dissipation substrate 221 by sintering silver, wherein transistor 21 as shown in FIG.
  • the package structure 22 includes a package tube shell 222, the package tube shell 222 is bonded to the heat dissipation substrate 221 by an insulating adhesive, and one end of the pin is exposed from the package structure to connect to other circuits, wherein the transistor 21 is arranged on the package tube shell 222 In the space surrounded by the heat dissipation substrate 221 .
  • the transistors provided by the embodiments of the present application can be applied to the processor in the terminal 100 provided in FIG. 1.
  • the specific application scenarios are not limited to the terminal shown in FIG. 1 above. It can be understood that any Electronic devices all belong to the application scenarios of the embodiments of the present application.
  • the transistor provided in the embodiment of the present application may be packaged into an integrated circuit (as shown in FIG. 2 ) through packaging technology and used alone.
  • Embodiment 1 of the present application provides a schematic structural diagram of an NMOS.
  • the NMOS includes a substrate 31 provided with a low-concentration P-type dopant, and a high
  • An insulating layer 34 is also provided above the NMOS, wherein a metal is provided on the source region 32 as a source (source), and a metal is provided on the drain region 33 as a drain (drain), between the source region 32 and the drain region 33 A metal is disposed on the insulating layer 34 as a gate.
  • the working principle of the NMOS is that by controlling the voltage of the gate and connecting the source to the power supply, a current is formed between the source and the drain.
  • the sub-threshold state of NMOS has the advantages of low voltage and low power consumption, and has attracted much attention from the integrated circuit industry.
  • the subthreshold state of NMOS will be described in detail below. Referring to FIG. 3 , when the NMOS is in the subthreshold state, the source contacts the source region 32 to form a gold half-contact, and there will be carriers in the source (also known as Boltzmann thermal tail, referred to as thermal tail, also called Hot carriers) are injected into the source region 32.
  • thermal tail also called Hot carriers
  • the surface of the substrate 31 (that is, the channel surface, in this scheme, the source region 32, the drain region 33, and the channel between the source region 32 and the drain region 33 can be formed on the substrate 31.
  • the channel can also be made by a layer of material layer made separately)
  • the energy of the electrons near the lower all the above-mentioned hot carriers can tunnel into the channel, and then diffuse to the drain region 33 , forming a subthreshold current generated by hot carrier tunneling.
  • Embodiment 1 of the present application provides an energy level structure diagram of the subthreshold state of the NMOS, in which the contact between the source region 32 and the channel and between the channel and the drain region 33 generates an energy level shift
  • the dopant provided for the channel is P-type (that is, a P-type semiconductor)
  • the dopant provided for the source region 32 and the drain region 33 is N-type (that is, an N-type semiconductor)
  • its energy band shift is as follows: As shown in Figure 4, the source region 32 is in contact with the channel so that the energy level of the source region 32 moves up, and the energy level of the channel moves down; and the contact between the channel and the drain region 33 makes the energy level at the channel move down, and the energy level of the drain region moves down.
  • the energy level of 33 moves up, and the above-mentioned energy level movement will stop when the Fermi level of NMOS is equal everywhere.
  • the hot carriers are distributed on the conduction band Ec of the source region 32 of the NMOS, and the hot carriers on the conduction band Ec of the source region 32 can tunnel into the channel, and then diffuse to the drain region to form a subthreshold current.
  • Embodiment 1 of the present application shows a graph showing the change of NMOS drain current Id with the increase of gate voltage Vg, as shown in Curve 1 in FIG. 5 , wherein the gate voltage changes from 0
  • the drain current Id is almost stable, and when the gate voltage Vg continues to increase from cV, the drain current Id shows an exponential growth trend.
  • the slope of curve 1 can simply represent the subthreshold swing of NMOS. Through calculation, it can be known that the subthreshold swing SS of the NMOS is 60mV/dec, which proves that theoretically when the gate voltage increases by 60mv, the drain current Id will increase.
  • the sub-threshold current of the NMOS also makes the power consumption of the NMOS higher.
  • the working voltage of the current complementary metal oxide semiconductor CMOS can be reduced to 0.7V
  • the sub-threshold swing of the MOSFET in CMOS limits the further reduction of the working voltage of CMOS, because when the working voltage continues to be reduced, the opening of CMOS current will not be guaranteed.
  • Embodiment 2 of the present application provides a first structural schematic diagram of a transistor, which is called a cold source field effect transistor (CSFET).
  • the transistor 60 includes a substrate 601 on which an active region 603 (that is, the above-mentioned first source region) is sequentially arranged along a direction parallel to the x-axis of the substrate 601 (that is, the above-mentioned first direction).
  • a source region 604 (that is, the above-mentioned second source region), a channel 605 and a drain region 606, an insulating layer 607 is arranged on the channel 605, and a gate 608 (that is, the above-mentioned first gate) is arranged on the insulating layer 607 electrode), the drain region 606 is provided with a drain electrode 609, the source region 603 is provided with a source electrode 610, and the transistor further includes a conductor 611, wherein the source region 603 is in contact with the source region 604 to form a contact surface, and the conductor 611 is in contact with the source region 603 and The source region 604 is in contact, and the contact surface is perpendicular to the conductor 611 .
  • FIG. 6 provides a transistor 60 disposed on a silicon-on-insulator substrate, and a buried oxide layer 602, a first source region 603, a second source region 604, a channel 605, and a drain are also disposed on the substrate 601. Region 606 is disposed on buried oxide layer 602 .
  • the schematic diagram (a) in FIG. 6 is a top view of the transistor 60 .
  • Schematic diagram (b) is a cross-sectional view of transistor 60 along AA' in schematic diagram (a);
  • schematic diagram (c) is a cross-sectional view of transistor 60 along BB' in schematic diagram (a).
  • the schematic diagrams (a), schematic diagrams (b) and schematic diagrams (c) in the following Fig. 11, Fig. 12, and Fig. 18 to Fig. 26 are all the same as the schematic diagrams (a), schematic diagram (b) and schematic diagram ( The illustration of c) is the same, and will not be described in detail later.
  • the material of the substrate 601 includes at least one or more of the following: silicon Si, silicon germanium SiGe, gallium nitride GaN, indium gallium arsenide InGaAs;
  • dopants can be set in the substrate 601, usually the dopants set in the substrate 601 are P-type and can provide P-type carriers, and the doping concentration of the substrate 601 is between 1e15 atoms/cubic centimeter to Between 1e17 atoms/cubic centimeter.
  • the material of the buried oxide layer 602 includes at least one or more of the following: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium oxide HfO 2 ; the thickness of the buried oxide layer 602 is greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.
  • the material of the channel 605 includes at least one or more of the following: silicon Si, silicon germanium SiGe, gallium nitride GaN, indium gallium arsenide InGaAs; the thickness of the channel 605 is greater than or equal to 5 nanometers and less than or equal to 500 nanometers; usually, the channel The same type of dopant as the source region 603 will be provided in the track 605 .
  • the material of the insulating layer 607 includes at least one or more of the following: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium oxide HfO 2 ; the thickness of the insulating layer 607 is greater than or equal to 1 nanometer and less than or equal to 30 nanometers.
  • the material of the gate 608 includes at least one or more of the following: polysilicon, metal, or a composite structure of polysilicon and metal for the gate 608 ; the thickness of the gate 608 is greater than or equal to 10 nanometers and less than or equal to 500 nanometers.
  • the material of the source electrode 610 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the material of the drain electrode 609 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the working principle of the transistor 60 is that by controlling the gate voltage Vg of the gate 608 and connecting the source 610 of the transistor 60 to a power source, a current is formed between the source 610 and the drain 609 .
  • the gate voltage Vg set on the gate 608 is 0, the source 610 and the drain 609 of the transistor are not conducted and no current is generated.
  • the gate voltage Vg set on the gate 608 is not 0, and the gate voltage Vg is smaller than the turn-on voltage Vth of the transistor 60, the transistor is in a subthreshold state.
  • the gate voltage Vg set on the gate 608 is not 0, and the gate voltage Vg is greater than the turn-on voltage Vth of the transistor 60 , a turn-on current is generated between the source 610 and the drain 708 .
  • FIG. 7 shows the energy level structure diagram of the transistor 60 in the subthreshold state, and the dopant set in the source region 603 and the channel 605 of the transistor 60 is P-type, the source region 604 and the drain region
  • the dopant set in 606 is N-type as an example to illustrate the subthreshold state of the transistor 60 .
  • the conductor 611 since the source region 603 is in contact with the conductor 611, the conductor 611 is in contact with the source region 604, the source region 604 is in contact with the channel 605, and the channel 605 is in contact with the drain region 606, wherein the conductor 611 is not a semiconductor, and the conductor 611
  • the source region 603 and the conductor 611 The contact causes the energy level of the source region 603 to move down; since the dopant provided in the source region 604 is N-type (that is, an N-type semiconductor), the contact between the source region 604 and the conductor 611 causes the energy level of the source region 604 to move up; and
  • the source region 604 is in contact with the channel 605, the energy level of the source region 604 moves up, and the energy level of the channel 605 moves down; when the channel 605 contacts with the drain region 606, the energy level of the channel 605 moves down, and the drain region The energy level of 606 is shifted up.
  • the above energy level movement stops when the Fermi levels of the source region 603 , the conductor 611 , the source region 604 , the channel 605 and the drain region 606 in the transistor 60 are equal everywhere.
  • the conduction band Ec of the channel 605 that is, the energy level E1 shown in FIG. 7
  • the valence band Ev of the source region 603 that is, the energy level E2 shown in FIG. 7
  • the source region 603, the conductor 611, and the source region 604 in the transistor 60 form a cold source structure.
  • a gold half-contact is formed between the source 610 and the source region 603, and the carrier in the source 610 Flow carriers (also known as Boltzmann hot tails, hot tails for short, or hot carriers) are injected into the source region 603, and these hot carriers tunnel to the channel 605 and continue to diffuse to the drain region 606 In order to form a subthreshold current.
  • Flow carriers also known as Boltzmann hot tails, hot tails for short, or hot carriers
  • the transistor 60 there is an overlapping region between the valence band Ev of the source region 603 and the conduction band Ec of the source region 604, and in this overlapping region, hot carriers can tunnel from the source region 604 to the channel 605 (that is, electrons energy between the energy level E2 and the conduction band Ec of the source region 604), and then diffuse to the drain region 606;
  • the hot carriers in the area between the level E2) cannot generate the tunneling effect (that is, the hot carriers whose electron energy is between the energy level E2 and the conduction band Ec of the source region 603) tunnel to the channel 605, Therefore, it cannot further diffuse to the drain region 606 .
  • the hot carriers are generally called cold carriers, such as the cold carriers on the conduction band Ec of the source region 704 as shown in FIG. 7 .
  • the reduced number of hot carriers that can tunnel reduces the subthreshold current of the transistor 60 .
  • FIG. 8 shows an energy level structure diagram when the transistor 60 is on, and the dopant set in the source region 603 and the channel 605 of the transistor 60 is P
  • the sub-threshold state of the transistor 60 will be described as an example where the dopant provided in the source region 604 and the drain region 606 is N-type.
  • the gate voltage Vg of the transistor 60 is greater than the turn-on voltage Vth of the transistor 60, the energy level of the channel 605 moves down by a large margin, and the conduction band Ec of the channel 605 moves down from the energy level E1 to the energy level E1′ s position.
  • the energy levels of the source region 603, the conductor 611, the source region 604, the channel 605, and the drain region 606 in the transistor 60 will move until the Fermi level is equal everywhere, and stop when the energy level stops moving.
  • the conduction band Ec (that is, the energy level E1' shown in FIG. 8 ) is smaller than the valence band Ev of the source region 603 (that is, the energy level E2 shown in FIG. 8 ), and the source region 603 in the transistor 60, the conductor 611 and the source region 604 form a cold source structure.
  • a gold half-contact is formed between the source electrode 610 and the source region 603.
  • hot carriers also called hot carriers
  • the hot carriers will be injected into the source region 603 , and the hot carriers appear as cold carriers on the conduction band Ec of the source region 604 .
  • the cold carriers whose electron energy is between the energy level E2 and the energy level E1' participate in conduction to generate thermal current;
  • the cold carriers whose electron energy is between the conduction band Ec of the source region 604 and the energy level E1' can tunnel tunneling current, and the existence of conductor 611 also increases the tunneling probability of cold carriers in this region;
  • the generation of thermal current and tunneling current ensures the turn-on current of the transistor 60 .
  • FIG. 9 shows the first embodiment of the present application when the NMOS is in the sub-threshold state, the curve 1 of the change of the drain current Id with the increase of the gate voltage Vg and the curve 1 provided by the second embodiment of the present application.
  • the slope of curve 1 can simply represent the sub-threshold swing of NMOS.
  • the sub-threshold swing SS of the NMOS is at least 60mV/dec, which also proves that when the gate voltage increases by 60mv in theory, the source and drain
  • the current between the poles will increase by an order of magnitude; the slope of curve 2 can simply represent the subthreshold swing of the transistor provided by the embodiment of the present application, wherein, when the gate voltage is greater than 0 and less than or equal to 0.2V, the transistor 60 The drain current does not change; when the gate voltage is greater than 0.2V and less than or equal to hV, the drain current increases slowly; when the gate voltage is greater than hV and less than or equal to kV, the drain current increases rapidly; at the gate voltage When it is greater than kV and less than or equal to 0.5V, the drain current grows very fast.
  • the minimum subthreshold swing SS of the transistor 60 provided by the embodiment of the present application is 40mV/dec, which proves that theoretically when the gate voltage increases At 40mv, the current between source and drain will increase by an order of magnitude.
  • the transistor 60 provided in the embodiment of the present application sets the structure of the first source, the conductor and the second source so that an energy band gap is formed between the first source and the second source, and the transistor is in a subthreshold state , the hot carriers injected from the source into the first source region are suppressed when passing through the energy band gap, so that only a part of the hot carriers can tunnel to the channel, and then diffuse from the channel to the drain region , forming a sub-threshold current, which is much smaller than that of a normal MOSFET.
  • the existence of the conductor can increase the tunneling probability of the carriers in the transistor, thereby ensuring the opening of the transistor 60 current, thus enabling the transistor to have a smaller subthreshold swing.
  • the conductor in the transistor 60 provided by the embodiment of the present application includes at least one or more of the following parts: a first part, a second part, a third part and a fourth part, wherein the first part of the conductor is arranged on the first Between the source region and the buried oxide layer; the second part of the conductor is arranged above the first source region; the third part of the conductor is arranged on the buried oxide layer, and is arranged on the first part of the first source region along the first direction. side; the fourth part of the conductor is disposed on the buried oxide layer, and is disposed on the second side of the first source region along the first direction.
  • FIG. 10 a schematic structural diagram of the source region 603 (that is, the above-mentioned first source region) and the source region 604 (that is, the above-mentioned second source region) in the transistor 60 provided by Embodiment 2 of the present application, wherein , the source region 603 is in contact with the source region 604 to form a contact surface 62, and the four vertices of the contact surface 62 are a vertex 62-A, a vertex 62-B, a vertex 62-C, and a vertex 62-D.
  • the buried oxide layer 602 is located under the source region 603 , as shown in FIG.
  • the first part of the conductor 611 is disposed between the source region 603 and the buried oxide layer 602, as shown in FIG.
  • the second part of 611 is disposed above the source region 603, as shown in FIG. 10 , that is, the second part of the conductor is in contact with the apex 62-C and the apex 62-D; , and along the direction of the x-axis (that is, the above-mentioned first direction), it is arranged on the first side of the source region 603, as shown in FIG.
  • the fourth part of the conductor 611 is disposed on the buried oxide layer 602, and is disposed on the second side of the source region 603 along the direction of the x-axis (that is, the above-mentioned first direction), as shown in FIG. 10 , that is, the conductor The fourth portion is in contact with apex 62-B and apex 62-C.
  • the embodiments of the present application provide various manners of conductor arrangement, and in practical applications, one or more parts of the conductors can be selected to realize the function of the transistor 60 provided in the embodiments of the present application.
  • the embodiment of the present application provides the material of the conductor 611, and the material of the conductor 611 includes at least one or more of the following: nickel silicide NiSi2 , titanium silicide TiSi2, cobalt silicide CoSi2, titanium Ti, tungsten W, titanium nitride TiN, graphene.
  • the widths of the second source region and the drain region in the transistor 60 provided in the embodiment of the present application can be equal.
  • the width of the source region 604 and the drain region 606 are equal, that is, the source region 604 and the drain region 606 are symmetrical with respect to the gate 608 , which is helpful for manufacturing the transistor 60 in the process.
  • dopants are provided in the source region 603, source region 604, and drain region 606, wherein the dopant provided in the source region 603 is P-type, and the source region 604 and the dopant provided in the drain region 606 is N-type, then the transistor 60 constitutes an N-type transistor, and the channel 605 may also be provided with dopant, and the dopant provided in the channel 605 is P-type.
  • the dopant provided in the source region 603 is N-type
  • the dopant provided in the source region 604 and the drain region 606 is P-type
  • the transistor 60 constitutes a P-type transistor
  • the channel 605 can also be provided with a dopant
  • the dopant provided in the channel 605 is N type.
  • one or more of the source region 603 , the source region 604 and the drain region 606 is provided with a dopant concentration greater than or equal to 1e19 atoms/cm 3 .
  • concentration of the dopant provided in the channel 605 is not limited in the embodiments of the present application.
  • a gate metal layer 614 is also provided on the gate 608 , wherein the material used for the gate 608 can specifically be a composite structure of metal and polysilicon or polysilicon
  • the material of the gate metal layer 614 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, and metal silicide.
  • sidewalls 612a that is, the above-mentioned first sidewalls
  • sidewall 612b that is, the above-mentioned second sidewall
  • the insulating layer 607, the gate 608 and the gate metal layer 614 are located between the sidewall 612a and the sidewall 612b, wherein the sidewall 612a is in contact with the source region 604, and the side The wall 612b is in contact with the drain region 606 .
  • the material of the side wall 612a includes at least one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide nitride SiOCN, silicon carbon boron nitride SiBCN; the material of the side wall 612b is at least Including one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide SiOCN, silicon carbon boron nitride SiBCN.
  • the sidewall 612a and the sidewall 612b in the transistor 60 are usually made of the same material.
  • the side of the substrate 601 away from the source 610 in the transistor 60 is also provided with a gate 613 (that is, the above-mentioned second gate, also referred to as a back gate).
  • the material of the gate 613 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • Embodiment 2 of the present application provides a third structural diagram of a transistor.
  • the transistor 60 also includes a dielectric 615 disposed on the buried oxide layer 602 .
  • the dielectric 615 is located between the source region 603 and the source region. Between regions 604 ; conductor 611 is in contact with source region 603 , dielectric 615 and source region 604 , and dielectric 615 is perpendicular to conductor 611 .
  • the presence of the dielectric 615 further prevents hot carriers from tunneling from the source region 604 to the channel 605 , so that the subthreshold swing of the transistor 60 is smaller.
  • the material of the medium 615 includes at least one or more of the following: silicon dioxide SiO 2 , titanium dioxide TiO 2 , aluminum oxide Al 2 O 3 , and the thickness of the medium 615 is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
  • Embodiment 3 of the present application provides a schematic diagram of the first structure of a transistor.
  • the transistor 70 includes a substrate 701; The first direction) is sequentially provided with an active region 703 (that is, the above-mentioned first source region), a source region 704 (that is, the above-mentioned second source region), a channel 705, and a drain region 706; the channel 705 is provided with an insulating layer 707; the insulating layer 707 is provided with a gate 708 (that is, the above-mentioned first gate); the drain region 706 is provided with a drain 709; the source region 703 is provided with a source 710; the transistor 70 also includes a conductor 711, Wherein, the source region 703 is in contact with the source region 704 to form a contact surface, the conductor 711 is in contact with the source region 703 and the source region 704 , and the contact surface is perpendicular to the conductor 711 .
  • FIG. 13 provides a transistor 70 provided on a bulk silicon substrate, and an isolation trench 702a (that is, the above-mentioned first isolation trench) and an isolation trench 702b (that is, the above-mentioned second isolation trench) are provided in the substrate 701. ), the isolation groove 702a and the isolation groove 702b are collectively referred to as the isolation groove 702, and the openings of the isolation groove 702a and the isolation groove 702b face the same side of the substrate 701 (for example, the openings of the isolation groove 702a and the isolation groove 702b shown in FIG. 13 face upward) ;
  • the source region 703, the source region 704, the channel 705 and the drain region 706 are disposed between the isolation trench 702a and the isolation trench 702b.
  • the schematic diagram (a) in FIG. 13 is a top view of the transistor 70 .
  • Schematic diagram (b) is a cross-sectional view of transistor 70 along AA' in schematic diagram (a);
  • schematic diagram (c) is a cross-sectional view of transistor 70 along BB' in schematic diagram (a).
  • the schematic diagrams (a), schematic diagrams (b) and schematic diagrams (c) in the following Fig. 15, Fig. 16, and Fig. 28 to Fig. 34 are all the same as the schematic diagrams (a), schematic diagram (b) and schematic diagram ( The illustration of c) is the same, and will not be described in detail later.
  • the aforementioned channel 705 is a part of the substrate 701 , that is, the region of the substrate 701 between the source region 704 and the drain region 706 is the channel 705 .
  • dopants are provided in the substrate 701 between the source region 704 and the drain region 706 to form the channel 705 .
  • the material of the substrate 701 includes at least one or more of the following: silicon germanium SiGe, gallium nitride GaN, and indium gallium arsenide InGaAs; the substrate 701 may not be provided with dopants, Alternatively, dopants may be provided in the substrate 701 , the provided dopants may provide P-type carriers, and the doping concentration of the substrate 701 is between 1e15 atoms/cm3-1e17 atoms/cm3.
  • the material of the isolation trench 702 a and the isolation trench 702 b is silicon dioxide SiO 2 .
  • the material of the insulating layer 707 includes at least one or more of the following: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium oxide HfO 2 ; the thickness of the insulating layer 707 is greater than or equal to 1 nanometer and less than or equal to 30 nanometers.
  • the material of the gate 708 includes at least one or more of the following: polysilicon, metal, or a composite structure of polysilicon and metal for the gate; the thickness of the gate 708 is greater than or equal to 10 nanometers and less than or equal to 500 nanometers.
  • the material of the source electrode 710 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the material of the drain electrode 709 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the source region 703, the source region 704, and the conductor 711 form a cold source structure
  • the transistor 70 is a transistor composed of a bulk silicon substrate.
  • the working principle of the transistor 70 is similar to that of the transistor 60, because the transistor 70 There is a cold source structure formed by the source region 703 , the source region 704 and the conductor 711 , so the subthreshold swing of the transistor 70 is also smaller.
  • the conductor in the transistor provided by the embodiment of the present application includes at least one or more of the following parts: a first part, a second part, a third part and a fourth part, wherein the first part of the conductor is set in the first source between the region and the substrate; the second part of the conductor is arranged above the first source region; the third part of the conductor is perpendicular to the substrate and along the first direction, arranged on the first side of the first source region; the conductor's The fourth part is perpendicular to the substrate and arranged on the second side of the first source region along the first direction.
  • FIG. 14 a schematic structural diagram of the source region 703 (that is, the above-mentioned first source region) and source region 704 (that is, the above-mentioned second source region) in the transistor 70 provided by Embodiment 3 of the present application, wherein , the source region 703 is in contact with the source region 704 to form a contact surface 72, and the four vertices of the contact surface 72 are a vertex 72-A, a vertex 72-B, a vertex 72-C and a vertex 72-D.
  • the substrate 701 is located below the source region 703 , as shown in FIG.
  • the first part of the conductor 711 is disposed between the source region 703 and the substrate 701, as shown in FIG.
  • the second part is disposed above the source region 703, as shown in FIG.
  • the direction of the x-axis (that is, the above-mentioned first direction) is arranged on the first side of the source region 703, as shown in FIG.
  • the fourth part of the conductor is disposed on the substrate 701, and is disposed on the second side of the source region 703 along the direction of the x-axis (that is, the above-mentioned first direction), as shown in FIG.
  • Embodiments of the present application provide various manners of conductor arrangement, and in practical applications, one or more parts of the conductor can be selected to realize the function of the transistor 70 provided by the embodiment of the present application.
  • the embodiment of the present application provides the material of the conductor 711, and the material of the conductor 711 includes at least one or more of the following: nickel silicide NiSi2 , titanium silicide TiSi2, cobalt silicide CoSi2, titanium Ti, tungsten W, titanium nitride TiN, graphene.
  • the widths of the second source region and the drain region in the transistor 70 provided in the embodiment of the present application may be equal.
  • Embodiment 3 of the present application provides a second structural schematic diagram of the transistor 70, In the transistor 70 , the width of the source region 704 and the drain region 706 are equal, that is to say, the source region 704 and the drain region 706 are symmetrical with respect to the gate 708 , which facilitates the process of manufacturing the transistor 70 .
  • the transistor 70 in the transistor 70 shown in FIG. 13 or FIG. 15, dopants are provided in the source region 703, source region 704, and drain region 706, wherein the dopant provided in the source region 703 is P-type, and the source region 704 and the dopant provided in the drain region 706 is N-type, then the transistor 70 constitutes an N-type transistor.
  • the channel 705 may also be provided with a dopant, and the dopant provided in the channel 705 is P-type.
  • the transistor 70 constitutes a P-type transistor.
  • the channel 705 may also be provided with a dopant, and the dopant provided in the channel 705 is N type.
  • one or more of the source region 703 , the source region 704 and the drain region 706 has a dopant concentration greater than or equal to 1e19 atoms/cm 3 .
  • the concentration of the dopant provided in the channel 705 is not limited in the embodiments of the present application.
  • a gate metal layer 713 is also provided on the gate 708, wherein the material used for the gate 708 is specifically a composite structure of metal and polysilicon, and the gate
  • the material of the metal layer 713 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the channel 705 is further provided with sidewalls 712a (that is, the first sidewalls) along the direction of the x-axis (that is, the above-mentioned first direction). and sidewall 712b (that is, the above-mentioned second sidewall), the insulating layer 707, the gate 708 and the gate metal layer 713 are located between the sidewall 712a and the sidewall 712b, wherein the sidewall 712a is in contact with the source region 704, and the side Wall 712b is in contact with drain region 706 .
  • the material of the side wall 712a includes at least one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide nitride SiOCN, silicon carbon boron nitride SiBCN; the material of the side wall 712b is at least Including one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide SiOCN, silicon carbon boron nitride SiBCN.
  • the sidewall 712a and the sidewall 712b in the transistor 70 are often made of the same material.
  • Embodiment 3 of the present application provides a third schematic structural diagram of a transistor 70.
  • the transistor 70 also includes a dielectric 714 disposed on the substrate 701.
  • the dielectric 714 is located between the source region 703 and the source region. Between the regions 704 ; the conductor 711 is in contact with the source region 703 , the dielectric 714 and the source region 704 , and the dielectric 714 is perpendicular to the conductor 711 .
  • the presence of the dielectric 714 further prevents hot carriers from tunneling from the source region 704 to the channel 705 , so that the subthreshold swing of the transistor 70 is smaller.
  • the material of the medium 714 includes at least one or more of the following: silicon dioxide SiO 2 , titanium dioxide TiO 2 , aluminum oxide Al 2 O 3 , and the thickness of the medium 714 is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
  • the second embodiment of the present application provides a method for manufacturing a transistor 60.
  • the method for manufacturing the transistor 60 includes the following steps:
  • the substrate 601 required for manufacturing the transistor 60 is prepared first, wherein the material of the substrate 601 includes at least one or more of the following: silicon Si, silicon germanium SiGe, gallium nitride GaN, Indium gallium arsenide InGaAs; dopants may not be set in the substrate 601, or dopants may be set in the substrate 601, and the set dopants can provide P-type carriers, and the doping concentration of the substrate 601 is 1e15 Atoms/cubic centimeter to 1e17 atoms/cubic centimeter.
  • a buried oxide layer 602 is formed on the substrate 601.
  • the material of the buried oxide layer 602 includes at least one or more of the following: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium oxide HfO 2 ; the thickness of the buried oxide layer 602 is greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.
  • the buried oxide layer 602 can be formed on the substrate 601 by using a deposition process, a coating process and the like.
  • a channel layer 6051 is formed on the buried oxide layer 602 .
  • the material of the channel layer 6051 includes at least one or more of the following: silicon Si, silicon germanium SiGe, gallium nitride GaN, indium gallium arsenide InGaAs; the thickness of the channel layer 6051 is greater than or equal to 5 nanometers and less than or equal to 500 nanometers .
  • the channel layer 6051 can be formed on the buried oxide layer 602 of the substrate by using a deposition process, a coating process and the like. It should be noted that the currently produced channel layer 6051 completely covers the buried oxide layer 602, and such a channel layer 6051 does not meet the requirements.
  • the photoresist is used to block, and photolithography is performed to form an active region (the active region is the region where the first source region, the second source region, the channel and the drain region of the transistor 60 are located) on the channel layer 6051.
  • the active region is the region where the first source region, the second source region, the channel and the drain region of the transistor 60 are located
  • Window, the channel layer 6051 covered by the window of the active region needs to be retained, and the channel layer 6051 outside the window of the active region is etched away to form the structure of the channel layer 6052 as shown in Figure 20, the channel layer 6052 Extend along the direction of the x-axis (that is, the above-mentioned first direction).
  • etching can be done by dry etching or wet etching.
  • Dry etching generally uses fluorine-based or halogen-based gases, such as sulfur hexafluoride SF6, trifluoromethane CHF3, hydrobromic acid HBr, chlorine Cl2, etc.
  • Wet etching generally uses tetramethylammonium hydroxide C4H13NO (tetramethylammonium hydroxide, TMAH or TMAOH for short) solution or potassium hydroxide KOH solution.
  • a silicon-on-insulator wafer which includes a substrate 601 , a buried oxide layer 602 and a channel layer 6051 , and then perform etching in the silicon-on-insulator wafer to form a channel layer 6052 .
  • an insulating layer extending along the y-axis direction (that is, the above-mentioned second direction) is fabricated on the channel layer.
  • photoresist on the channel layer 6052 and the buried oxide layer 602
  • a light-shielding plate to block the photoresist
  • photolithography to form the window of the insulating layer 607
  • Photoresist deposit insulating layer material in the window of the insulating region 607
  • the material of the insulating layer 607 includes at least one or more of the following: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium oxide HfO 2 ; and insulating
  • the thickness of the layer 607 is greater than or equal to 1 nanometer and less than or equal to 30 nanometers, and the specific deposition method can be atomic layer deposition, thermal oxidation, chemical vapor deposition and the like.
  • the direction of the x-axis and the direction of the y-axis are perpendicular to each other, and the plane formed by the direction of the x-axis and the direction of the y-axis is parallel to the buried oxide layer 602 .
  • the gate 608 covering the insulating layer 607 (that is, the above-mentioned first gate) needs to be deposited on the insulating layer 607 .
  • the material of the gate 608 includes at least one or more of the following: polysilicon, metal, or a composite structure of polysilicon and metal for the gate 608; the thickness of the gate 608 is greater than or equal to 10 nanometers, and less than equal to 500 nanometers.
  • Specific deposition methods can be selected from atomic layer deposition, thermal oxidation, chemical vapor deposition, and the like.
  • a gate metal layer 614 needs to be deposited on the gate 608.
  • the material of the gate metal layer 614 Including at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the gate metal layer 614 can be deposited by evaporation or physical vapor deposition, and it needs to be annealed after the deposition is completed. Generally, the annealing temperature is between 300 degrees Celsius and 900 degrees Celsius, so that the atoms in the gate metal layer 614 are evenly distributed. .
  • a spacer 612a on the channel layer 6052 along the direction of the x-axis (that is, the above-mentioned first direction). and the sidewall 612b, the insulating layer 607 and the gate 608 are located between the sidewall 612a and the sidewall 612b, wherein the sidewall 612a is in contact with the source region 604, and the sidewall 612b is in contact with the drain region 606.
  • a layer can be deposited on the upper surface of the current transistor (that is, above the buried oxide layer 602, the channel layer 6052, and the gate metal layer 614 shown in FIG.
  • the sidewall material wherein the sidewall material at least includes one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide nitride SiOCN, silicon carbon boron nitride SiBCN.
  • the sidewall material in the window of the sidewall 612a and the window of the sidewall 612b is etched away to form the sidewall 612a and the sidewall 612b.
  • the etching here generally uses dry etching, using fluorine-based or halogen-based gases, such as sulfur hexafluoride SF6, trifluoromethane CHF 3 , hydrobromic acid HBr, chlorine Cl 2 and the like.
  • the upper surface of the transistor formed in step 804 (that is, the buried oxide layer 602, channel layer 6052, gate metal layer 614, sidewall 612a, and sidewall 612b shown in FIG. 24 above) apply photoresist, use a light-shielding plate to block the photoresist, and perform photolithography to form the window of the source region 603, and remove the photoresist in the window of the source region 603, from the window of the source region 603 to the trench
  • the channel layer 6052 is implanted with dopants that provide carriers to form the source region 603 .
  • a layer of photoresist again, use a light-shielding plate to block the photoresist, and perform photolithography to form the window of the source region 604 and the window of the drain region 606, and remove the window of the source region 604 and the window of the drain region 606
  • the photoresist in the window is injected with the dopant providing carriers from the window of the source region 604 and the window of the drain region 606 to the channel layer 6052 to form the source region 604 and the drain region 606 .
  • ion implantation can be used, wherein the implanted dopant can be boron B or boron fluoride BF 2 , and the implantation dose is between 1e13 atoms/cm2-1e16 atoms/cm2 Between 1keV and 100keV, the implantation energy is between 1keV and 100keV, and the boron B or boron fluoride BF 2 P-type dopant can provide P-type carriers, that is, the dopant set in the source region 603 is P-type; 604 and the drain region 606, ion implantation can be used, wherein the implanted dopant can be arsenic As or phosphorus P, the implantation dose is between 1e13 atoms/cm2 ⁇ 1e16 atoms/cm2, and the implantation energy is 1keV Between to 100keV, arsenic As or phosphorus P is an N-type dopant that can provide N-type carriers, that is, the do
  • ion implantation when forming the source region 603, ion implantation can be used, wherein the implanted dopant can be arsenic As or phosphorus P, and the implantation dose is between 1e13 atoms/square centimeter to 1e16 atoms/square centimeter , the implantation energy is between 1keV and 100keV, arsenic As or phosphorus P is an N-type dopant that can provide N-type carriers, that is, the dopant set in the source region 603 is N-type; when making the source region 604 and the drain In region 606, ion implantation can be used, wherein the implanted dopant can be boron B or boron fluoride BF 2 , the implant dose is between 1e13 atoms/cm2 ⁇ 1e16 atoms/cm2, and the implantation energy is 1keV Between 100keV and 100keV, the boron B or boron fluoride BF 2 P-type dopant can provide P-
  • the widths of the source region 604 and the drain region 606 may be equal, or the widths of the source region 604 and the drain region 606 may not be equal, and the embodiment of the present application does not limit the width of the source region 604 and the drain region 606, And when the widths of the source region 604 and the drain region 606 are equal, the ion implantation process used should be the same, which is beneficial to the realization of the process.
  • the channel layer 6052 shielded by the insulating layer 607 is not implanted with dopants providing carriers, and the channel layer 6052 in this region forms the channel 605 of the transistor.
  • the upper surface of the transistor formed in step 805 that is, the buried oxide layer 602, source region 603, source region 604, drain region 606, gate metal layer 614, side wall 612a and side wall 612b coated with photoresist, use a light-shielding plate to block the photoresist, and perform photolithography to form the window of the source 610 and the window of the drain 609, and remove the window of the source 610 and the window of the drain 609.
  • the photoresist in the window of the drain 609 is deposited on the window of the source 610 and the window of the drain 609 to form the source 610 and the drain 609 .
  • the material of the source electrode 610 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide
  • the material of the drain electrode 609 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the source electrode 610 and the drain electrode 609 can be deposited by evaporation or physical vapor deposition, and annealing is required after the deposition is completed. Generally, the annealing temperature is between 300 degrees Celsius and 900 degrees Celsius, so that the inside of the source electrode 610 and the drain electrode 609 The atoms are evenly distributed.
  • the window of the source electrode 610 can also be set separately to deposit the source material, and then the window of the drain electrode 609 can be set to deposit the drain material, and the source material and the drain material can be the same or different.
  • a window of the gate 613 may also be provided on the side of the substrate 601 away from the source 610, and a material is deposited in the window of the gate 613 to form the gate 613 (also It is the aforementioned second gate (also referred to as the back gate), and the material of the gate 613 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, and metal silicide.
  • the gate 613 can be deposited by evaporative deposition or physical vapor deposition, and annealing is required after the deposition is completed. Generally, the annealing temperature is between 300°C and 900°C to make the atoms in the gate 613 evenly distributed.
  • the conductor in the transistor includes at least one or more of the following parts: a first part, a second part, a third part and a fourth part, wherein the first part of the conductor is arranged in the first source region Between the buried oxide layer; the second part of the conductor is arranged above the first source region; the third part of the conductor is perpendicular to the buried oxide layer and is arranged on the first side of the first source region along the first direction; the conductor The fourth part is perpendicular to the buried oxide layer and is disposed on the second side of the first source region along the first direction.
  • the source region 603 is in contact with the source region 604 to form a contact surface
  • the conductor is in contact with the source region 603 and the source region 604
  • the contact surface is perpendicular to the conductor.
  • the conductor 611 when fabricating the first part of the conductor 611 , it is necessary to fabricate the first part of the conductor before fabricating the channel layer extending along the first direction on the buried oxide layer. Specifically, it is necessary to coat photoresist on the buried oxide layer 602 shown in FIG. , using a deposition process to deposit a conductor material in the window of the first part of the conductor, wherein the conductor material at least includes one or more of the following: nickel silicide NiSi 2 , titanium silicide TiSi2, cobalt silicide CoSi2, titanium Ti, tungsten W, nitrogen TiN, graphene.
  • the specific deposition process can be evaporative deposition or physical vapor deposition, and annealing is required after the deposition is completed.
  • the annealing temperature is between 300°C and 900°C to make the atomic distribution in the first part 711-a of the conductor uniform.
  • the third part of the conductor and the fourth part of the conductor when making the second part of the conductor, the third part of the conductor and the fourth part of the conductor at the same time, specifically, as shown in FIG. 26 , coating the photoresist covering the transistor, using The light-shielding plate blocks the photoresist, and performs photolithography to form the window of the second part of the conductor (that is, the window of the second part of the conductor can be set at the position that can cover the vertex 72-C and the vertex 72-D in FIG.
  • the window of the third part of the conductor (that is, the window of the third part of the conductor can be set at the position that can cover the vertex 72-A and the vertex 72-D in Figure 10), the window of the fourth part of the conductor (that is, it can Cover the position of the apex 72-B and apex 72-C in FIG.
  • Conductor materials are deposited in the four windows, wherein the conductor materials include at least one or more of the following: nickel silicide NiSi 2 , titanium silicide TiSi2 , cobalt silicide CoSi2 , titanium Ti, tungsten W, titanium nitride TiN, and graphene.
  • the specific deposition process can be evaporative deposition or physical vapor deposition, and annealing is required after the deposition is completed.
  • the annealing temperature is between 300 degrees Celsius and 900 degrees Celsius, so that the second part of the conductor, the third part of the conductor and the The atoms in the fourth part are evenly distributed.
  • a groove may also be formed by etching in the contact area between the source region 603 and the source region 604; and then a dielectric is formed in the groove.
  • etching generally uses dry etching, using fluorine-based or halogen-based gases, such as sulfur hexafluoride SF6, trifluoromethane CHF 3 , hydrobromic acid HBr, chlorine Cl 2 and the like.
  • the dielectric material includes at least one or more of the following: silicon dioxide SiO 2 , titanium dioxide TiO 2 , aluminum oxide Al 2 O 3 ,
  • the thickness of the medium is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
  • step 807 to form a conductor 611 on the medium, wherein the conductor 611 is in contact with the source region 603 , the medium and the source region 604 , and the medium is perpendicular to the conductor, thereby forming the transistor 60 as shown in FIG. 12 .
  • the above-mentioned annealing may be performed only once, for example, the annealing process is performed in the last step of manufacturing the transistor.
  • the steps of the above-mentioned transistor manufacturing method provided in the embodiments of the present application are only illustrative, and in practical applications, the above-mentioned steps may be more or less, and the order of the above-mentioned steps may also be adjusted as required.
  • the third embodiment of the present application provides a method for manufacturing a transistor 70.
  • the method for manufacturing the transistor 70 includes the following steps:
  • the substrate 701 required for manufacturing the transistor 70 is prepared first, wherein the material of the substrate 701 includes at least one or more of the following: silicon germanium SiGe, gallium nitride GaN, indium gallium arsenide InGaAs; no dopant may be set in the substrate 701, or a dopant may be set in the substrate 701, and the set dopant can provide P-type carriers, and the doping concentration of the substrate 701 is 1e15 atoms/cubic Between centimeters and 1e17 atoms/cubic centimeter.
  • etching can be done by dry etching or wet etching.
  • Dry etching generally uses fluorine-based or halogen-based gases, such as sulfur hexafluoride SF6, trifluoromethane CHF3, hydrobromic acid HBr, chlorine Cl2, etc.
  • Wet etching generally uses tetramethylammonium hydroxide C4H13NO (tetramethylammonium hydroxide, TMAH or TMAOH for short) solution or potassium hydroxide KOH solution.
  • the groove of the isolation groove 702a and the groove of the isolation groove 702b are formed, and then the groove of the isolation groove 702a and the groove of the isolation groove 702b
  • the groove is filled with silicon dioxide SiO 2 to form the isolation groove 702a and the isolation groove 702b, and then the isolation groove 702a and the isolation groove 702b need to be mechanically polished to make the surface of the isolation groove 702a and the isolation groove 702b flat.
  • the upper surface of the substrate 701 forms an active region pattern (that is, the pattern of the region where the source region 703, the source region 704, the channel 705, and the drain region 706 are located).
  • an insulating layer 707 extending along the y-axis direction (that is, the above-mentioned second direction) is formed on the substrate 701 .
  • photoresist above the substrate 701
  • a light-shielding plate to block the photoresist
  • photolithography to form the window of the insulating layer 707
  • the insulating layer material is deposited inside, and the material of the insulating layer 707 includes at least one or more of the following: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium oxide HfO 2 ; and the thickness of the insulating layer 707 is greater than or equal to 1 nanometer, and Less than or equal to 30 nanometers, the specific deposition method can be atomic layer deposition, thermal oxidation, chemical vapor deposition, etc.
  • a gate 708 covering the insulating layer 707 needs to be deposited on the insulating layer 707 .
  • the material of the gate 708 includes at least one or more of the following: polysilicon, metal, or a composite structure of polysilicon and metal for the gate 708; the thickness of the gate 708 is greater than or equal to 10 nanometers, and less than equal to 500 nanometers.
  • Specific deposition methods can be selected from atomic layer deposition, thermal oxidation, chemical vapor deposition, and the like.
  • a gate metal layer 713 needs to be deposited on the gate 708.
  • the material of the gate metal layer 713 Including at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the gate metal layer 713 can be deposited by evaporation or physical vapor deposition, and it needs to be annealed after the deposition is completed. Generally, the annealing temperature is between 300 degrees Celsius and 900 degrees Celsius, so that the atoms in the gate metal layer 713 are evenly distributed. .
  • the gate 708 and the gate metal layer 713 are fabricated, it is also necessary to fabricate sidewalls 712a and The sidewall 712b, the insulating layer 707 and the gate 708 are located between the sidewall 712a and the sidewall 712b, wherein the sidewall 712a is in contact with the source region 704, and the sidewall 712b is in contact with the drain region 706.
  • it can be deposited on the upper surface of the current transistor (that is, above the substrate 701, the isolation trench 702a, the isolation trench 702b, and the gate metal layer 713 shown in FIG. 31 ) by chemical vapor deposition or atomic layer deposition.
  • a layer of side wall material wherein the material of the side wall includes at least one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide nitride SiOCN, silicon carbon boron nitride SiBCN.
  • the material of the side wall includes at least one or more of the following: silicon dioxide SiO2, silicon nitride Si 3 N 4 , silicon oxycarbide nitride SiOCN, silicon carbon boron nitride SiBCN.
  • the etching here generally uses dry etching, using fluorine-based or halogen-based gases, such as sulfur hexafluoride SF6, trifluoromethane CHF 3 , hydrobromic acid HBr, chlorine Cl 2 and the like.
  • fluorine-based or halogen-based gases such as sulfur hexafluoride SF6, trifluoromethane CHF 3 , hydrobromic acid HBr, chlorine Cl 2 and the like.
  • the upper surface of the transistor formed in step 903 (that is, the substrate 701, the isolation trench 702a, the isolation trench 702b, the gate metal layer 713, the sidewall 712a and the sidewall shown in FIG. 712b) apply photoresist, use a light-shielding plate to block the photoresist, and perform photolithography to form the window of the source region 703, and remove the photoresist in the window of the source region 703, from the window of the source region 703 Dopants that provide carriers are implanted into the substrate 701 to form source regions 703 .
  • a layer of photoresist again, use a light-shielding plate to block the photoresist, and perform photolithography to form the window of the source region 704 and the window of the drain region 706, and remove the window of the source region 704 and the window of the drain region 706
  • the photoresist in the window is injected into the substrate 701 into the substrate 701 at the window of the source region 704 and the window of the drain region 706 to form the source region 704 and the drain region 706 .
  • ion implantation can be used, wherein the implanted dopant can be boron B or boron fluoride BF2, and the implantation dose is between 1e13 atoms/square centimeter to 1e16 atoms/square centimeter , the implantation energy is between 1keV and 100keV, and boron B or boron fluoride BF2 is a P-type dopant that can provide P-type carriers, that is, the dopant set in the source region 703 is P-type; and the drain region 706, the ion implantation method can be used, wherein the implanted dopant can be arsenic As or phosphorus P, the implantation dose is between 1e13 atoms/square centimeter to 1e16 atoms/square centimeter, and the implantation energy is between 1keV and Between 100keV, arsenic As or phosphorus P is an N-type dopant that can provide N-type carriers, that is,
  • the implanted dopant can be arsenic As or phosphorus P
  • the implantation dose is between 1e13 atoms/cm2 ⁇ 1e16 atoms/cm2
  • the implantation energy is 1keV To 100keV
  • arsenic As or phosphorus P is an N-type dopant that can provide N-type carriers, that is, the dopant provided in the source region 703 is N-type
  • the implanted dopant can use boron B or boron fluoride BF2
  • the implantation dose is between 1e13 atoms/cm2 ⁇ 1e16 atoms/cm2
  • the implantation energy is between 1keV and 100keV
  • boron B or boron fluoride BF2 is a P-type dopant that can provide P-type carriers, that is, the dopant provided in the source region
  • the widths of the source region 704 and the drain region 706 may be equal, or the widths of the source region 704 and the drain region 706 may not be equal, and the embodiment of the present application does not limit the width of the source region 704 and the drain region 706, And when the widths of the source region 704 and the drain region 706 are equal, the ion implantation process used should be the same, which is beneficial to the realization of the process.
  • the channel 705 Part of the substrate region between the source region 704 and the drain region 706 is the channel 705, wherein the channel 705 can be provided with dopants, and the dopant provided is the same type as the dopant provided in the source region 703. . Or the channel 705 may not be provided with dopants.
  • the upper surface of the transistor formed in step 904 (that is, the substrate 701, the isolation trench 702a, the isolation trench 702b, the gate metal layer 713, the source region 703 and the source region shown in FIG. 704, drain region 706, sidewall 712a, and sidewall 712b) are coated with photoresist, and the photoresist is blocked by a light-shielding plate, and photolithography is performed to form the window of the source electrode 710 and the window of the drain electrode 709, and The photoresist in the window of the source electrode 710 and the window of the drain electrode 709 is removed, and the same material is deposited on the window of the source electrode 710 and the window of the drain electrode 709 to form the source electrode 710 and the drain electrode 709 .
  • the material of the source electrode 710 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide
  • the material of the drain electrode 709 includes at least one or more of the following: aluminum Al, nickel Ni, titanium Ti, metal silicide.
  • the source electrode 710 and the drain electrode 709 can be deposited by evaporative deposition or physical vapor deposition, and annealing needs to be carried out after the deposition is completed. Generally, the annealing temperature is between 300 degrees Celsius and 900 degrees Celsius, so that the inside of the source electrode 710 and the drain electrode 709 The atoms are evenly distributed.
  • the source material can also be deposited on the window of the source 710 separately, and then the drain material can be deposited on the window of the drain 709, and the source material and the drain material can be the same or different.
  • the conductor 711 in the transistor provided by the embodiment of the present application includes at least one or more of the following parts: a first part, a second part, a third part and a fourth part, wherein the first part of the conductor is set in the first source between the region and the substrate; the second part of the conductor is arranged above the first source region; the third part of the conductor is perpendicular to the substrate and along the first direction, arranged on the first side of the first source region; the conductor's The fourth part is perpendicular to the substrate and arranged on the second side of the first source region along the first direction.
  • the source region 703 is in contact with the source region 704 to form a contact surface
  • the conductor is in contact with the source region 703 and the source region 704
  • the contact surface is perpendicular to the conductor.
  • the window of the third part of the conductor that is, the position of the vertex 72-A and vertex 72-D in Figure 14 can be covered to set the first part of the conductor
  • the window of the fourth part of the conductor that is, the window of the fourth part of the conductor can be set at the position that can cover the vertex 72-B and the vertex 72-C in Fig.
  • the conductor material is deposited in the window of the second part of the conductor, the window of the third part of the conductor and the window of the fourth part of the conductor, wherein the material of the conductor at least includes one or more of the following: nickel silicide NiSi 2 , titanium silicide TiSi2, Cobalt silicide CoSi2, titanium Ti, tungsten W, titanium nitride TiN, graphene.
  • the specific deposition process can be evaporative deposition or physical vapor deposition, and annealing is required after the deposition is completed. Generally, the annealing temperature is between 300 degrees Celsius and 900 degrees Celsius, so that the second part of the conductor, the third part of the conductor and the The atoms in the fourth part are evenly distributed.
  • the fabrication of the first part of the conductor needs to correspondingly etch away part of the source region 703 and part of the source region 704 in the area where the first part of the conductor is located, to form a groove of the first part of the conductor, and then to Conductive material is deposited in the trench.
  • the fabrication of the first part of the conductor needs to correspondingly etch away part of the substrate 701 in the area where the first part of the conductor is located, to form a groove of the first part of the conductor, and then deposit the conductor material in the groove of the first part of the conductor .
  • a groove may also be formed by etching in the contact area between the source region 703 and the source region 704; and then a dielectric is formed in the groove.
  • etching generally uses dry etching, using fluorine-based or halogen-based gases, such as sulfur hexafluoride SF6, trifluoromethane CHF 3 , hydrobromic acid HBr, chlorine Cl 2 and the like.
  • the dielectric material includes at least one or more of the following: silicon dioxide SiO 2 , titanium dioxide TiO 2 , aluminum oxide Al 2 O 3 ,
  • the thickness of the medium is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
  • a conductor is formed on the medium, wherein the conductor is in contact with the source region 703 , the medium and the source region 704 , and the medium is perpendicular to the conductor, thereby forming the transistor 70 as shown in FIG. 16 .
  • the above-mentioned annealing may be performed only once, for example, the annealing process is performed in the last step of manufacturing the transistor.
  • the steps of the above-mentioned transistor manufacturing method provided in the embodiments of the present application are only illustrative, and in practical applications, the above-mentioned steps may be more or less, and the order of the above-mentioned steps may also be adjusted as required.

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Abstract

本申请的实施例提供了一种晶体管、集成电路以及电子设备，涉及半导体技术领域，能够降低晶体管的亚阈值摆幅。上述的晶体管包括：衬底；衬底上沿平行于衬底的第一方向依次设置有第一源区、第二源区、沟道以及漏区；沟道上设置有绝缘层；绝缘层上设置有第一栅极；漏区上设置有漏极；第一源区上设置有源极；晶体管还包括导体，其中，第一源区与第二源区接触形成接触面，导体与第一源区以及第二源区接触，并且接触面与导体垂直。

Description

一种晶体管、集成电路以及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种晶体管、集成电路以及电子设备。
背景技术
目前，集成电路中的晶体管大多是金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)，由于MOSFET的器件原理的限制(载流子的玻尔兹曼分布)，室温下的MOSFET的亚阈值摆幅(sub-threshold swing，SS)理论最小值为60mV/dec，其中亚阈值摆幅可以衡量MOSFET的开启与关断之间相互转换的速率，并且亚阈值摆幅越小意味着MOSFET的开启与关断之间相互转换的速率越快。
随着现代电子产业的发展，集成电路的设计目标已经由追求提高性能和提高集成度转变为追求降低功耗，而降低功耗最有效的办法就是降低集成电路的工作电压，尽管目前的互补金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管的工作电压已经可以降低至0.7V，但CMOS中的MOSFET的亚阈值摆幅限制了CMOS的工作电压无法进一步缩减，因为在继续缩减工作电压时，CMOS的开启电流将无法得到保障。为了使得集成电路的工作电压进一步降低，需要设计一种亚阈值摆幅更小的晶体管。
发明内容
本申请的实施例提供了一种晶体管、集成电路以及电子设备，涉及半导体技术领域，能够降低晶体管的亚阈值摆幅。
为达到上述目的，本申请的实施例提供如下技术方案：
第一方面，提供了一种晶体管。该晶体管包括：衬底；衬底上沿平行于衬底的第一方向依次设置有第一源区、第二源区、沟道以及漏区；沟道上设置有绝缘层；绝缘层上设置有第一栅极；漏区上设置有漏极；第一源区上设置有源极；晶体管还包括导体，其中，第一源区与第二源区接触形成接触面，导体与第一源区以及第二源区接触，并且接触面与导体垂直。本申请的实施例提供的晶体管，通过设置第一源极，导体以及第二源极的结构，使得第一源极和第二源极之间形成能带间隙，在该晶体管处于亚阈值状态时，源极注入至第一源区的热载流子通过该能带间隙时得到了抑制，使得热载流子中仅有一部分可以隧穿至沟道，然后再由沟道扩散至漏区，形成亚阈值电流，该亚阈值电流相比于正常的MOSFET的亚阈值电流会小很多。同时在晶体管的栅极电压持续增大，晶体管开启时，源极和漏极之间由于存在导体，导体的存在又可以使得该晶体管内的其中的载流子的隧穿几率变大，进而保障了晶体管的开启电流，由此使得该晶体管拥有更小的亚阈值摆幅。
可选的，衬底上还设置有氧化埋层，第一源区、第二源区、沟道以及漏区设置于氧化埋层上。在该可选方案中，上述的晶体管设置在绝缘上硅衬底上。
可选的，导体至少包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分；导体的第一部分设置于第一源区与氧化埋层之间；导体的第二部分设置 于第一源区的上方；导体的第三部分设置于氧化埋层上，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分设置于氧化埋层上，并且沿第一方向，设置于第一源区的第二侧。在该可选方案中，绝缘上硅衬底上设置的晶体管，其中的导体可以根据实际需要选择设置导体的一个部分或多个部分。
可选的，衬底远离源极的一面还设置有第二栅极。在该可选方案中，第二栅极的存在使得晶体管的相应速率更快。
可选的，衬底内设置有第一隔离槽和第二隔离槽，第一隔离槽与第二隔离槽的开口朝向衬底的同一侧；第一源区、第二源区、沟道以及漏区设置于第一隔离槽与第二隔离槽之间。在该可选方案中，上述的晶体管设置在体硅衬底上。
可选的，导体包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分；导体的第一部分设置于第一源区与衬底之间；导体的第二部分设置于第一源区的上方；导体的第三部分设置于衬底上，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分设置于衬底上，并且沿第一方向，设置于第一源区的第二侧。在该可选方案中，体硅衬底上设置的晶体管，其中的导体可以根据实际需要选择设置导体的一个部分或多个部分。
可选的，晶体管还包括设置于衬底上的介质，介质位于第一源区与第二源区之间；导体与第一源区、介质以及第二源区接触，并且介质与导体垂直。在该可选方案中，由于介质的存在，进一步阻碍热载流子从第一源区通过第二源区隧穿至沟道，以使得该晶体管的亚阈值摆幅更小。
可选的，介质的材料至少包括以下一种或多种：二氧化硅，二氧化钛、氧化铝。
可选的，第二源区与漏区宽度相等。在该可选方案中，由于第二源区与漏区宽度相等，则第二源区和漏区关于栅极对称，有利于工艺上制作该晶体管。
可选的，第一栅极上还设置有栅极金属层。
可选的，沟道上沿第一方向还设置有第一侧墙和第二侧墙，绝缘层以及第一栅极位于第一侧墙与第二侧墙之间，其中第一侧墙与第二源区接触，第二侧墙与漏区接触。
可选的，本申请的实施例提供了导体的材料，导体的材料至少包括以下一种或多种：硅化镍、硅化钛、硅化钴、钛、钨、氮化钛、石墨烯。
可选的，第一源区、第二源区以及漏区内设置有掺杂物，第二源区和漏区设置的掺杂物为N型，第一源区设置的掺杂物为P型；或者，第二源区和漏区设置的掺杂物为P型，第一源区设置的掺杂物为N型。在该可选方案中，晶体管可以是N型晶体管，也可以是P型晶体管。
可选的，第一源区、第二源区以及漏区中的一个或多个设置的掺杂物的浓度大于等于1e19原子/立方厘米。
可选的，衬底的材料至少包括以下一种或多种：硅、锗硅、氮化镓、铟镓砷。
可选的，氧化埋层的材料至少包括以下一种或多种：二氧化硅、氧化铝、氧化铪。
可选的，沟道的材料至少包括以下一种或多种：硅、锗硅、氮化镓、铟镓砷。
可选的，绝缘层的材料至少包括以下一种或多种：二氧化硅、氧化铝、氧化铪。
可选的，漏极的材料至少包括以下一种或多种：铝、镍、钛、金属硅化物。
可选的，源极的材料至少包括以下一种或多种：铝、镍、钛、金属硅化物。
可选的，第一栅极的材料至少包括以下一种或多种：多晶硅、金属。
可选的，栅极金属层的材料至少包括以下一种或多种：铝、镍、钛、金属硅化物。
可选的，第一侧墙的材料至少包括以下一种或多种：二氧化硅、氮化硅、碳氧氮化硅、碳氮化硼硅。
可选的，第二侧墙的材料至少包括以下一种或多种：二氧化硅、氮化硅、碳氧氮化硅、碳氮化硼硅。
可选的，第二栅极的材料至少包括以下一种或多种：铝、镍、钛、金属硅化物。
可选的，衬底不设置掺杂物，或者，衬底设置掺杂物，掺杂区的浓度大于等于1e15原子/立方厘米，并且小于等于1e17原子/立方厘米。
可选的，沟道设置的掺杂物的类型与第一源区的掺杂物的类型相同。
可选的，氧化埋层的厚度大于等于10纳米，并且小于等于1000纳米。
可选的，沟道的厚度大于等于5纳米，并且小于等于500纳米。
可选的，绝缘层的厚度大于等于1纳米，并且小于等于30纳米。
可选的，第一栅极的厚度大于等于10纳米，并且小于等于500纳米。
可选的，介质的厚度大于等于1纳米，并且小于等于10纳米。
第二方面，提供了一种集成电路。该集成电路包括封装结构以及一个或多个如上述第一方面任一项所述的晶体管，晶体管封装于封装结构内部。
第三方面，提供了一种电子设备。该电子设备包括印刷电路板以及如上述第二方面所述的集成电路，集成电路与印刷电路板耦合。
第四方面，提供了一种晶体管的制备方法，包括如下步骤：在衬底上制作氧化埋层；在氧化埋层上制作沿第一方向延伸的沟道层；在沟道层上制作沿第二方向延伸的绝缘层，其中第一方向与第二方向垂直，并且第一方向与第二方向构成的平面平行于氧化埋层；制作覆盖绝缘层的第一栅极；对沟道层注入掺杂物形成第一源区、第二源区以及漏区；在漏区上制作漏极，在第一源区上制作源极；制作导体，其中，第一源区与第二源区接触形成接触面，导体与第一源区以及第二源区接触，并且接触面与导体垂直。
可选的，制作导体包括：在氧化埋层上制作沿第一方向延伸的沟道层，之前，在氧化埋层上制作导体的第一部分，其中沟道层覆盖第一部分；和/或，在漏区上制作漏极，在第一源区上制作源极，之后，制作导体的至少以下一个或多个部分：第二部分、第三部分以及第四部分；导体的第二部分设置于第一源区的上方；导体的第三部分设置于氧化埋层上，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分设置于氧化埋层上，并且沿第一方向，设置于第一源区的第二侧。
可选的，对沟道层注入掺杂物形成第一源区、第二源区以及漏区，具体包括：对沟道层注入N型掺杂物，形成第二源区以及漏区；对沟道层注入P型掺杂物，形成第一源区；或者，对沟道层注入P型掺杂物，形成第二源区以及漏区；对沟道层注入N型掺杂物，形成第一源区。
可选的，制作覆盖绝缘层的第一栅极之后还包括：在第一栅极上制作栅极金属层。
可选的，制作覆盖绝缘层的第一栅极之后还包括：在沟道层上沿第一方向制作第一侧墙和第二侧墙，绝缘层以及第一栅极位于第一侧墙与第二侧墙之间，其中第一侧 墙与第二源区接触，第二侧墙与漏区接触。
可选的，在漏区上制作漏极，在第一源区上制作源极之后，还包括：在衬底远离源极的一面制作第二栅极。
可选的，在漏区上制作漏极，在第一源区上制作源极之后，还包括：在第一源区与第二源区的接触区域刻蚀形成凹槽；在凹槽中制作介质；则制作导体具体包括：在介质上制作导体；介质位于第一源区与第二源区之间；导体与第一源区、介质以及第二源区接触，并且介质与导体垂直。
第五方面，提供了一种晶体管的制备方法，包括如下步骤：在衬底上制作第一隔离槽和第二隔离槽，第一隔离槽与第二隔离槽的开口朝向衬底的同一侧；在衬底上制作沿第二方向延伸的绝缘层；制作覆盖绝缘层的栅极；对衬底注入提供载流子的掺杂物形成沿第一方向延伸的第一源区、第二源区以及漏区，第二源区与第一源区接触形成接触面，漏区与第二源区不接触，栅极位于漏区与第二源区之间，其中第一方向与第二方向垂直，并且第一方向与第二方向构成的平面平行于衬底；在漏区上制作漏极，在第一源区上制作源极；制作导体，导体与第一源区以及第二源区接触，并且接触面与导体垂直。
可选的，制作导体包括：制作导体的至少以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分；导体的第一部分设置于第一源区与衬底之间；导体的第二部分设置于第一源区的上方；导体的第三部分设置于衬底上，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分设置于衬底上，并且沿第一方向，设置于第一源区的第二侧。
可选的，对衬底注入提供载流子的掺杂物形成第一源区、第二源区以及漏区，具体包括：对衬底注入N型掺杂物，形成第二源区以及漏区；对衬底注入P型掺杂物，形成第一源区；或者，对衬底注入P型掺杂物，形成第二源区以及漏区；对衬底注入N型掺杂物，形成第一源区。
可选的，制作覆盖绝缘层的栅极之后还包括：在栅极上制作栅极金属层。
可选的，制作覆盖绝缘层的栅极之后还包括：在沟道上沿第一方向制作第一侧墙和第二侧墙，绝缘层以及栅极位于第一侧墙与第二侧墙之间，其中第一侧墙与第二源区接触，第二侧墙与漏区接触。
可选的，在漏区上制作漏极，在第一源区上制作源极之后，还包括：在第一源区与第二源区的接触区域刻蚀形成凹槽；在凹槽中制作介质；则制作导体具体包括：在介质上制作导体；其中导体与第一源区、介质以及第二源区接触，并且介质与导体垂直。
其中，第二方面和第五方面中任一种可能实现方式中所带来的技术效果可参见上述第一方面中任一项不同的实现方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请的实施例提供的终端的结构示意图；
图2为本申请的实施例提供的集成电路的结构示意图；
图3为本申请的实施例一提供的NMOS的结构示意图；
图4为本申请的实施例一提供的NMOS的能级结构图；
图5为本申请的实施例一提供的NMOS的漏极电流Id随栅极电压Vg而改变的曲线图；
图6为本申请的实施例二提供的晶体管的第一种结构示意图；
图7为本申请的实施例二提供晶体管的能级结构图一；
图8为本申请的实施例二提供晶体管的能级结构图二；
图9为本申请的实施例二提供的晶体管的漏极电流Id随栅极电压Vg而改变的曲线图；
图10为本申请的实施例二提供的晶体管中的第一源区以及第二源区的结构示意图；
图11为本申请的实施例二提供的晶体管的第二种结构示意图；
图12为本申请的实施例二提供的晶体管的第三种结构示意图；
图13为本申请的实施例三提供了晶体管的第一种结构示意图；
图14为本申请的实施例三提供的晶体管中的第一源区以及第二源区的结构示意图；
图15为本申请的实施例三提供的晶体管的第二种结构示意图；
图16为本申请的实施例三提供的晶体管的第三种结构示意图；
图17为本申请的实施例二提供的晶体管的制备方法的流程示意图；
图18为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图一；
图19为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图二；
图20为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图三；
图21为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图四；
图22为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图五；
图23为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图六；
图24为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图七；
图25为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图八；
图26为本申请的实施例二提供的晶体管的制备方法中的晶体管的结构示意图九；
图27为本申请的实施例三提供的晶体管的制备方法的流程示意图；
图28为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图一；
图29为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图二；
图30为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图三；
图31为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图四；
图32为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图五；
图33为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图六；
图34为本申请的实施例三提供的晶体管的制备方法中的晶体管的结构示意图七。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下对本申请的实施例中的技术术语说明如下：
半导体：半导体是一种常温下导电性能介于导体与绝缘体之间的材料；其中，半 导体包括本征半导体和杂质半导体。不含杂质和缺陷的纯净半导体，其内部电子和空穴浓度相等，称为本征半导体。掺入一定量掺杂物的半导体称为杂质半导体或非本征半导体。其中，杂质半导体中掺入的掺杂物能够提供一定浓度的载流子(如空穴或电子)，其中掺入的掺杂物提供电子杂质(如5价的磷元素)的杂质半导体也称作电子型半导体或N(negative，负)型半导体，掺入的掺杂物提供空穴杂质(如3价的硼元素)的杂质半导体也称作空穴型半导体或P(positive，正)型半导体，掺杂能够改善本征半导体的导电性，通常掺杂物的浓度越大，载流子浓度也就越大，半导体的电阻率越低，导电性也越好。
半导体的能带包括价带Ev、禁带以及导带Ec。处于价带Ev的电子也被称为束缚电子，这些电子受原子核束缚较强，价带Ev中电子的电子能量较低，几乎不参与导电。处于导带Ec中的电子也被称为自由电子，导带Ec中电子的电子能量相对于价带Ev中电子的电子能量高，导带Ec中的电子参与导电。其中导带Ec与价带Ev都是一些连续的能量极，半导体中将导带底与价带顶之间的距离称为禁带，并且在禁带中存在费米能级。半导体的费米能级处于导带Ec与价带Ev之间，其中，本征半导体的费米能级处于导带Ec与价带Ev中间，P型半导体的费米能级靠近价带Ev，N型半导体的费米能级靠近导带Ec。其中，半导体与半导体接触或者半导体与金属接触时均会产生能级移动，能级移动直至费米能级处处相等时停止，例如N型半导体与P型半导体接触时，N型半导体的能级上移，P型半导体的能级下移，直至费米能级处处相等停止能级移动。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请中，“至少一个(层)”是指一个(层)或者多个(层)，“多个(层)”是指两个(层)或两个(层)以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的技术方案可以应用于电子设备，该电子设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的终端。电子设备也可以是用于上述电子设备中的芯片以及处理器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
如图1所示，图1示出了终端100的结构示意图。终端100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，摄像头190以及显示屏191等。
可以理解的是，本申请的实施例示意的结构并不构成对终端100的具体限定。在本申请另一些实施例中，终端100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从该存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了***的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过终端100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为终端供电。
电源管理模块141用于连接电池142，充电管理模块140与处理器110。电源管理模块141接收电池142和/或充电管理模块140的输入，为处理器110，内部存储器121，显示屏191，摄像头190，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于处理器110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
终端100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。终端100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在终端100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括一个或多个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于处理器110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与处理器110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A，受话器170B等)输出声音信号，或通过显示屏191显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在终端100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星***(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成一个或多个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，终端100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得终端100可以通过无线通信技术与网络以及其他设备通信。该无线通信技术可以包括全球移动通讯***(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。该GNSS可以包括全球卫星定位***(global positioning system，GPS)，全球导航卫星***(global navigation satellite system，GLONASS)，北斗卫星导航***(beidou navigation satellite system，BDS)，准天顶卫星***(quasi-zenith satellite system，QZSS)和/或星基增强***(satellite based augmentation systems， SBAS)。
终端100通过GPU，显示屏191，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏191和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏191用于显示图像，视频等。显示屏191包括显示面板。显示面板可以采用液晶显示屏(liquid crystal display，LCD)，有机发光二极管(organic light-emitting diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode，AMOLED)，柔性发光二极管(flex light-emitting diode，FLED)，Miniled，MicroLed，Micro-oLed，量子点发光二极管(quantum dot light emitting diodes，QLED)等。在一些实施例中，终端100可以包括1个或N个显示屏191，N为大于1的正整数。终端100可以通过ISP，摄像头190，视频编解码器，GPU，显示屏191以及应用处理器等实现拍摄功能。
ISP用于处理摄像头190反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将电信号传递给ISP处理，转化为肉眼可见的图像。ISP还可以对图像的噪点，亮度，肤色进行算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头190中。
摄像头190用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(charge coupled device，CCD)或互补金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像信号。ISP将数字图像信号输出到DSP加工处理。DSP将数字图像信号转换成标准的RGB，YUV等格式的图像信号。在一些实施例中，终端100可以包括1个或N个摄像头190，N为大于1的正整数。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展终端100的存储能力。外部存储卡通过外部存储器接口120与处理器110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储一个或多个计算机程序，该一个或多个计算机程序包括指令。处理器110可以通过运行存储在内部存储器121的上述指令，从而使得终端100执行各种功能应用和数据处理等。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作***；该存储程序区还可以存储一个或多个应用程序(比如图库、联系人等)等。存储数据区可存储终端100使用过程中所创建的数据(比如照片，联系人等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如一个或多个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。在另一些实施例中，处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，来使得终端100执行各种功能应用和数据处理。
终端100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机 接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。在一些实施例中，音频模块170可以设置于处理器110中，或将音频模块170的部分功能模块设置于处理器110中。
扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。终端100可以通过扬声器170A收听音乐，或收听免提通话。
受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。当终端100接听电话或语音信息时，可以通过将受话器170B靠近人耳接听语音。
麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风170C发声，将声音信号输入到麦克风170C。终端100可以设置一个或多个麦克风170C。在另一些实施例中，终端100可以设置两个麦克风170C，除了采集声音信号，还可以实现降噪功能。在另一些实施例中，终端100还可以设置三个，四个或更多麦克风170C，实现采集声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口170D用于连接有线耳机。耳机接口170D可以是USB接口130，也可以是3.5mm的开放移动电子设备平台(open mobile terminal platform，OMTP)标准接口，美国蜂窝电信工业协会(cellular telecommunications industry association of the USA，CTIA)标准接口。
传感器模块180可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器，加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感器，环境光传感器，骨传导传感器等。
在本申请的实施例中，触摸传感器，也称“触控器件”。触摸传感器可以设置于显示屏191，由触摸传感器与显示屏191组成触摸屏，也称“触控屏”。触摸传感器用于检测作用于其上或附近的触摸操作。触摸传感器可以将检测到的触摸操作传递给应用处理器，以确定触摸事件类型。可以通过显示屏提供与触摸操作相关的视觉输出。在另一些实施例中，也可以设置有多个触摸传感器形成的触控传感器阵列的触控面板以外挂形式设置于显示面板的表面。在另一些实施例中，触摸传感器也可以与显示屏191所处的位置不同。本申请的实施例中对触控传感器的形式不做限定，例如可以是电容、或压敏电阻等器件。
另外，上述终端100中还可以包括按键、马达、指示器以及用户标识模块(subscriber identification module，SIM)卡接口等一种或多种部件，本申请的实施例对此不做任何限制。
参照图2所示，本申请的实施例提供一种集成电路20，包括晶体管21以及封装结构22，其中晶体管21封装于封装结构22内部。如图2所示，封装结构22具体包括：散热基板221，其中为了提高散热基板221的导电性以及散热性，散热基板221可以采用复合材料，例如铜Cu/钼Mo/铜Cu形成的叠层结构；晶体管21通过烧结银粘接在散热基板221上，其中如图2所示的晶体管21，该晶体管21的晶体管的部分电极(例如可以是源极)与散热基板221导通；此外，晶体管的部分电极(例如漏极和 栅极)通过金线引线键合连接到管脚，管脚设置在绝缘层(例如可以是绝缘陶瓷)上，绝缘层通过绝缘粘接剂粘接于散热基板221上。此外，封装结构22包括封装管壳222，封装管壳222通过绝缘粘接剂与散热基板221粘接，并且管脚的一端从封装结构露出以连接其他电路，其中晶体管21设置于封装管壳222与散热基板221包围的空间中。
本申请的实施例提供的晶体管可以应用于图1提供的终端100中的处理器中，当然具体应用场景不限于上述图1示出的终端，可以理解的是，任意需要使用低功耗晶体管的电子设备均属于本申请的实施例的应用场景。或者，本申请的实施例提供的晶体管可以通过封装技术封装为集成电路(如图2所示)单独使用。
其中，MOSFET分为N沟道型(NMOS)和P沟道型(PMOS)。以NMOS为例，参照图3所示，本申请的实施例一提供了一种NMOS的结构示意图，NMOS包括设置有低浓度的P型掺杂物的衬底31，衬底31上设置的高浓度的N型掺杂物的源区32以及衬底31上设置的高浓度的N型掺杂物的漏区33，源区32与漏区33之间形成沟道(该沟道是衬底31的一部分)。在NMOS的上方还设置有绝缘层34，其中，源区32上设置金属作为源极(source)，漏区33上通过设置金属作为漏极(drain)，在源区32与漏区33之间的绝缘层34上设置金属作为栅极(gate)。该NMOS的工作原理为，通过控制栅极的电压大小，并且将源极连接电源，使得源极和漏极之间形成电流。
参照图3所示，当栅极电压Vg为0时，源极与漏极之间相当两个背靠背的PN结，尽管在源极连接电源，但是源区32与漏区33之间不导通，因此源极与漏极之间不产生电流。当栅极电压Vg不为0时，并且栅极电压Vg小于NMOS的开启电压Vth，NMOS就处于亚阈值状态。当栅极电压Vg不为0时，并且栅极电压Vg大于NMOS的开启电压Vth，源极和漏极之间产生开启电流。
其中，NMOS的亚阈值状态具有低电压和低功耗的优点，备受集成电路产业的关注。下面将详细介绍NMOS的亚阈值状态。参照图3，在NMOS处于亚阈值状态时，源极与源区32接触形成金半接触，源极中会有载流子(也被称为玻尔兹曼热尾巴，简称热尾巴，也叫热载流子)注入到源区32里面。受栅极电压Vg的作用，衬底31表面(也就是沟道表面，在该方案中可以在衬底31上对源区32、漏区33以及源区32和漏区33之间的沟道的位置分别进行掺杂，当然沟道也可以是由单独制作的一层材料层制作)附近的电子能量降低，上述的所有热载流子都可以隧穿到沟道中，然后扩散至漏区33，形成热载流子隧穿产生的亚阈电流。
参照图4所示，本申请的实施例一提供了NMOS的亚阈值状态的能级结构图，该NMOS中的源区32与沟道以及沟道与漏区33之间接触产生能级移动，其中，沟道为设置的掺杂物为P型(也就是P型半导体)，源区32与漏区33为设置的掺杂物为N型(也就是N型半导体)，其能带迁移如图4所示，源区32与沟道接触使得源区32的能级上移，沟道的能级下移；而沟道与漏区33接触使得沟道处的能级下移，漏区33的能级上移，上述的能级移动会在NMOS的费米能级处处相等时停止。其中，热载流子分布于NMOS的源区32导带Ec上，并且源区32导带Ec上的热载流子都可以隧穿到沟道中，然后扩散至漏区，形成亚阈电流。
结合图5所示，本申请的实施例一示出了NMOS的漏极电流Id随栅极电压Vg的增加而改变的曲线图，如图5所示的曲线一，其中，栅极电压由0增大至cV时，由于栅极电 压Vg比较小，因此漏极电流Id几乎趋于平稳，在栅极电压Vg从cV以后持续增长时，漏极电流Id呈指数增长趋势。曲线一的斜率可以简单表示NMOS的亚阈值摆幅，通过计算可知该NMOS的亚阈值摆幅SS为60mV/dec，也就证明理论上当栅极电压增大60mv时，漏极电流Id会增大一个数量级。同时，NMOS的亚阈值电流也使得NMOS的功耗较高。尽管目前的互补金属氧化物半导体CMOS的工作电压已经可以降低至0.7V，但CMOS中的MOSFET的亚阈值摆幅限制了CMOS的工作电压无法进一步缩减，因为在继续缩减工作电压时，CMOS的开启电流将无法得到保障。为了使得集成电路的工作电压进一步降低，需要设计一种亚阈值摆幅更小的晶体管。
参照图6所示，为解决上述问题，本申请的实施例二提供了晶体管的第一种结构示意图，该晶体管被称为冷源晶体管(cold source field effect transistor，CSFET)。该晶体管60包括衬底601，衬底601上沿平行于衬底601的x轴所示的方向(也就是上述的第一方向)依次设置有源区603(也就是上述的第一源区)、源区604(也就是上述的第二源区)、沟道605以及漏区606，沟道605上设置有绝缘层607，绝缘层607上设置有栅极608(也就是上述的第一栅极)，漏区606上设置有漏极609，源区603上设置有源极610，晶体管还包括导体611，其中，源区603与源区604接触形成接触面，导体611与源区603以及源区604接触，并且接触面与导体611垂直。源区603、导体611以及源区604构成冷源结构。其中，图6提供的是一种绝缘上硅衬底上设置的晶体管60，则衬底601上还设置有氧化埋层602，第一源区603、第二源区604、沟道605以及漏区606设置于氧化埋层602上。
图6中的示意图(a)是晶体管60的俯视图。示意图(b)是在示意图(a)中沿AA’对晶体管60的剖视图；示意图(c)是在示意图(a)中沿BB’对晶体管60的剖视图。并且下列图11、图12、以及图18至图26中的示意图(a)、示意图(b)、示意图(c)均与图(6)中的示意图(a)、示意图(b)、示意图(c)的示意相同，后续不赘述。
其中，图6所示的晶体管60中，衬底601的材料至少包括以下一种或多种：硅Si、锗硅SiGe、氮化镓GaN、铟镓砷InGaAs；衬底601中可以不设置掺杂物，或者，衬底601中可以设置掺杂物，通常衬底601中设置的掺杂物为P型可以提供P型载流子，衬底601的掺杂浓度在1e15原子/立方厘米～1e17原子/立方厘米之间。氧化埋层602的材料至少包括以下一种或多种：二氧化硅SiO 2、氧化铝Al 2O 3、氧化铪HfO 2；氧化埋层602的厚度大于等于10纳米，并且小于等于1000纳米。沟道605的材料至少包括以下一种或多种：硅Si、锗硅SiGe、氮化镓GaN、铟镓砷InGaAs；沟道605的厚度大于等于5纳米，并且小于等于500纳米；通常，沟道605中会设置与源区603相同类型的掺杂物。绝缘层607的材料至少包括以下一种或多种：二氧化硅SiO 2、氧化铝Al 2O 3、氧化铪HfO 2；绝缘层607的厚度大于等于1纳米，并且小于等于30纳米。栅极608的材料至少包括以下一种或多种：多晶硅、金属，或者栅极608使用多晶硅与金属的复合结构；栅极608的厚度大于等于10纳米，并且小于等于500纳米。源极610的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。漏极609的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。
该晶体管60的工作原理为，通过控制栅极608的栅极电压Vg大小，并将晶体管60的源极610连接电源，使得源极610和漏极609之间形成电流。当设置在栅极608的栅极电压Vg为0，则晶体管的源极610与漏极609之间不导通不产生电流。当设置在栅极608的栅极电压Vg不为0，并且栅极电压Vg小于晶体管60的开启电压Vth时，晶体管就处于亚阈值状态。当设置在栅极608的栅极电压Vg不为0，并且栅极电压Vg大于晶体管60的开启电压Vth时，源极610和漏极708之间产生开启电流。
参照图7所示，图7示出了晶体管60在亚阈值状态的能级结构图，并且以晶体管60的源区603与沟道605设置的掺杂物为P型、源区604以及漏区606设置的掺杂物为N型为例对晶体管60的亚阈值状态进行说明。参照图7所示，由于源区603与导体611接触，导体611与源区604接触，源区604与沟道605接触，沟道605与漏区606接触，其中，导体611不是半导体，导体611的导带Ec、价带Ev以及费米能级重合，其仅存在一条能级Em，由于源区603设置的掺杂物为P型(也就是P型半导体)，因此源区603与导体611接触使得源区603的能级下移；由于源区604设置的掺杂物为N型(也就是N型半导体)，因此源区604与导体611接触使得源区604的能级上移；并且源区604与沟道605接触时源区604的能级上移，沟道605的能级下移；沟道605与设置有漏区606接触时，沟道605的能级下移，漏区606的能级上移。上述的能级移动会在晶体管60中源区603、导体611、源区604、沟道605以及漏区606的费米能级处处相等时停止。在能级停止移动后，沟道605的导带Ec(也就是图7所示的能级E1处)大于源区603的价带Ev(也就是图7所示的能级E2处)，其中，晶体管60中的源区603、导体611以及源区604形成冷源结构，在该晶体管60处于亚阈值状态时，源极610与源区603之间形成金半接触，源极610中的载流子(也被称为玻尔兹曼热尾巴，简称热尾巴，也叫热载流子)会注入源区603中，这些热载流子隧穿至沟道605并且继续扩散至漏区606才能形成亚阈电流。但是，在晶体管60中，源区603的价带Ev和源区604的导带Ec存在重叠区域，在该重叠区域，热载流子可以从源区604隧穿至沟道605(也就是电子能量处于能级E2与源区604的导带Ec之间的热载流子)，进而扩散至漏区606；而处于源区603的禁带(也就是源区603的导带Ec底至能级E2之间)区域内的热载流子，无法产生隧穿效应(也就是电子能量处于能级E2与源区603的导带Ec之间的热载流子)隧穿至沟道605，因而也无法进一步扩散至漏区606。这样使得源极610注入至源极603的热载流子仅有一部分可以隧穿至沟道605，然后扩散到漏区606，形成亚阈电流，这样的晶体管60仿佛工作在低温环境下，因此这里的热载流子通常被称为冷载流子，如图7所示的源区704的导带Ec上的冷载流子。可以隧穿的热载流子的数量减少使得该晶体管60的亚阈电流降低。
同时，在晶体管60处于开启状态时，参照图8所示，图8示出了晶体管60开启时的能级结构图，并且以晶体管60的源区603与沟道605设置的掺杂物为P型、源区604以及漏区606设置的掺杂物为N型为例对晶体管60的亚阈值状态进行说明。其中，在晶体管60的栅极电压Vg大于晶体管60的开启电压Vth时，沟道605的能级下移较大的幅度，沟道605的导带Ec从能级E1下移至能级E1’的位置。其中，晶体管60中源区603、导体611、源区604、沟道605以及漏区606的能级会发生移动直至费米能级处处相等时停止，在能级停止移动后，沟道605的导带Ec(也就是图8所示的能 级E1’处)小于源区603的价带Ev(也就是图8所示的能级E2处)，并且，晶体管60中的源区603、导体611以及源区604形成冷源结构，此时的源极610与源区603之间形成金半接触，源极610中的载流子(也被称为玻尔兹曼热尾巴，简称热尾巴，也叫热载流子)会注入源区603中，热载流子在源区604的导带Ec上表现为冷载流子。其中，电子能量处于能级E2与能级E1’之间的冷载流子参与导电产生热电流；电子能量处于源区604的导带Ec与能级E1’之间的冷载流子可以隧穿产生隧穿电流，并且导体611的存在也使得该区域内的冷载流子的隧穿几率变大；电子能量处于能级E2与源区603的导带Ec之间的冷载流子不能进行隧穿不能产生电流。热电流以及隧穿电流的产生使得该晶体管60的开启电流得到了保障。
参照图9所述，图9示出了本申请的实施例一提供的NMOS处于亚阈值状态时漏极电流Id随栅极电压Vg的增加而改变的曲线一以及本申请的实施例二提供的晶体管60的处于亚阈值状态时漏极电流Id随栅极电压Vg的增加而改变的曲线二。其中，曲线一的斜率可以简单表示NMOS的亚阈值摆幅，通过计算可知该NMOS的亚阈值摆幅SS最小为60mV/dec，也就证明理论上当栅极电压增大60mv时，源极与漏极之间的电流会增大一个数量级；曲线二的斜率可以简单表示本申请的实施例提供的晶体管的亚阈值摆幅，其中，在栅极电压大于0并且小于等于0.2V时，晶体管60的漏极电流不发生改变；在栅极电压大于0.2V并且小于等于hV时，漏极电流增长比较缓慢；在栅极电压大于hV并且小于等于kV时，漏极电流增长较快；在栅极电压大于kV并且小于等于0.5V时,漏极电流增长非常快，通过计算可知本申请的实施例提供的晶体管60的亚阈值摆幅SS最小为40mV/dec，也就证明理论上当栅极电压增大40mv时，源极与漏极之间的电流会增大一个数量级。
本申请的实施例提供的晶体管60，通过设置第一源极，导体以及第二源极的结构，使得第一源极和第二源极之间形成能带间隙，在该晶体管处于亚阈值状态时，源极注入至第一源区的热载流子通过该能带间隙时得到了抑制，使得热载流子中仅有一部分可以隧穿至沟道，然后再由沟道扩散至漏区，形成亚阈值电流，该亚阈值电流相比于正常的MOSFET的亚阈值电流会小很多。同时在晶体管的栅极电压持续增大时，源极和漏极之间由于存在导体，导体的存在又可以使得该晶体管内的载流子的隧穿几率变大，进而保障了晶体管60的开启电流，由此使得该晶体管拥有更小的亚阈值摆幅。
示例性的，本申请的实施例提供的晶体管60中的导体至少包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分，其中，导体的第一部分设置于第一源区与氧化埋层之间；导体的第二部分设置于第一源区的上方；导体的第三部分设置于氧化埋层上，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分设置于氧化埋层上，并且沿第一方向，设置于第一源区的第二侧。
参照图10所示，本申请的实施例二提供的晶体管60中的源区603(也就是上述的第一源区)以及源区604(也就是上述的第二源区)的结构示意图，其中，源区603与源区604接触形成接触面62，接触面62的四个顶点分别是顶点62-A、顶点62-B、顶点62-C以及顶点62-D。氧化埋层602位于源区603的下方，如图10所示也就是氧化埋层602与顶点62-A以及顶点62-B接触。导体611的第一部分设置于源区603与氧化埋层602之间，如图10所示也就是导体的第一部分与顶点62-A以及顶点62-B 接触，并且与氧化埋层602接触；导体611的第二部分设置于源区603的上方，如图10所示也就是导体的第二部分与顶点62-C和顶点62-D接触；导体611的第三部分设置于氧化埋层602上，并且沿x轴的方向(也就是上述的第一方向)，设置于源区603的第一侧，如图10所示也就是导体的第三部分与顶点62-A和顶点62-D接触；导体611的第四部分设置于氧化埋层602上，并且沿x轴的方向(也就是上述的第一方向)，设置于源区603的第二侧，如图10所示也就是导体的第四部分与顶点62-B和顶点62-C接触。本申请的实施例中提供了多种导体设置的方式，在实际的应用中，可以任选导体的一个或多个部分以实现本申请的实施例提供的晶体管60的功能。
具体的，本申请的实施例提供了导体611的材料，导体611的材料至少包括以下一种或多种：硅化镍NiSi 2、硅化钛TiSi2、硅化钴CoSi2、钛Ti、钨W、氮化钛TiN、石墨烯。
示例性的，本申请的实施例提供的晶体管60中的第二源区与漏区的宽度可以相等，参照图11所示，本申请的实施例二提供了晶体管的第二种结构示意图，该晶体管中，源区604与漏区606的宽度相等，也就是说，源区604与漏区606关于栅极608对称，有助于工艺上制作出该晶体管60。
具体的，图6或图11所示的晶体管60中，源区603、源区604与漏区606内设置有掺杂物，其中，源区603设置的掺杂物为P型，源区604以及漏区606设置的掺杂物为N型，则该晶体管60构成N型晶体管，并且，沟道605也可以设置掺杂物，并且沟道605设置的掺杂物为P型。
或者，源区603设置的掺杂物为N型，源区604以及漏区606设置的掺杂物为P型，则该晶体管60构成P型晶体管，并且，沟道605也可以设置掺杂物，并且沟道605设置的掺杂物为N型。
示例性的，源区603、源区604以及漏区606中的一个或多个设置的掺杂物的浓度大于等于1e19原子/立方厘米。沟道605设置的掺杂物的浓度本申请的实施例不做限定。
示例性的，图6或图11所示的晶体管60中，栅极608上还设置有栅极金属层614，其中，该栅极608所使用的材料具体可以是金属与多晶硅的复合结构或者多晶硅，栅极金属层614的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。
示例性的，参照图6、图11所示的晶体管60，沟道605上沿x轴的方向(也就是上述的第一方向)还设置有侧墙612a(也就是上述的第一侧墙)和侧墙612b(也就是上述的第二侧墙)，绝缘层607以及栅极608以及栅极金属层614位于侧墙612a与侧墙612b之间，其中侧墙612a与源区604接触，侧墙612b与漏区606接触。
具体的，侧墙612a的材料至少包括以下一种或多种：二氧化硅SiO2、氮化硅Si 3N 4、碳氧氮化硅SiOCN、碳氮化硼硅SiBCN；侧墙612b的材料至少包括以下一种或多种：二氧化硅SiO2、氮化硅Si 3N 4、碳氧氮化硅SiOCN、碳氮化硼硅SiBCN。示例性的，晶体管60中的侧墙612a与侧墙612b往往采用同种材料制作。
示例性的，参照图6、图11所示的晶体管60，晶体管60中衬底601远离源极610的一面还设置有栅极613(也就是上述的第二栅极，也被称为背栅)，栅极613的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。
示例性的，参照图12所示，本申请的实施例二提供了晶体管的第三种结构示意图，该晶体管60还包括设置于氧化埋层602上的介质615，介质615位于源区603与源区604之间；导体611与源区603、介质615以及源区604接触，并且介质615与导体611垂直。该介质615的存在，进一步阻碍热载流子从源区604隧穿至沟道605，以使得该晶体管60的亚阈值摆幅更小。
具体的，介质615的材料至少包括以下一种或多种：二氧化硅SiO 2，二氧化钛TiO 2、氧化铝Al 2O 3，介质615的厚度大于等于1纳米，并且小于等于10纳米。
参照图13所示，本申请的实施例三提供了晶体管的第一种结构示意图，该晶体管70包括衬底701；衬底701上沿平行于衬底701的x轴的方向(也就是上述的第一方向)依次设置有源区703(也就是上述的第一源区)、源区704(也就是上述的第二源区)、沟道705以及漏区706；沟道705上设置有绝缘层707；绝缘层707上设置有栅极708(也就是上述的第一栅极)；漏区706上设置有漏极709；源区703上设置有源极710；晶体管70还包括导体711，其中，源区703与源区704接触形成接触面，导体711与源区703以及源区704接触，并且接触面与导体711垂直。其中，图13提供的是体硅衬底上设置的晶体管70，则衬底701内设置有隔离槽702a(也就是上述的第一隔离槽)和隔离槽702b(也就是上述的第二隔离槽)，隔离槽702a与隔离槽702b统称为隔离槽702，隔离槽702a与隔离槽702b的开口朝向衬底701的同一侧(例如图13所示的隔离槽702a与隔离槽702b的开口朝上)；源区703、源区704、沟道705以及漏区706设置于隔离槽702a与隔离槽702b之间。
图13中的示意图(a)是晶体管70的俯视图。示意图(b)是在示意图(a)中沿AA’对晶体管70的剖视图；示意图(c)是在示意图(a)中沿BB’对晶体管70的剖视图。并且下列图15、图16、以及图28至图34中的示意图(a)、示意图(b)、示意图(c)均与图(6)中的示意图(a)、示意图(b)、示意图(c)的示意相同，后续不赘述。
需要说明的是，上述的沟道705是衬底701的一部分，也就是源区704与漏区706之间的衬底701的区域即是沟道705。在一些实施例中，会在源区704与漏区706之间的衬底701中设置掺杂物，形成沟道705。
其中，图13所示的晶体管70中，衬底701的材料至少包括以下一种或多种：锗硅SiGe、氮化镓GaN、铟镓砷InGaAs；衬底701中可以不设置掺杂物，或者，衬底701中可以设置掺杂物，设置的掺杂物可以提供P型载流子，衬底701的掺杂浓度在1e15原子/立方厘米～1e17原子/立方厘米之间。隔离槽702a与隔离槽702b的材料为二氧化硅SiO 2。绝缘层707的材料至少包括以下一种或多种：二氧化硅SiO 2、氧化铝Al 2O 3、氧化铪HfO 2；绝缘层707的厚度大于等于1纳米，并且小于等于30纳米。栅极708的材料至少包括以下一种或多种：多晶硅、金属，或者栅极使用多晶硅与金属的复合结构；栅极708的厚度大于等于10纳米，并且小于等于500纳米。源极710的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。漏极709的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。
在该晶体管70中，源区703、源区704以及导体711构成冷源结构，该晶体管70是体硅衬底构成的晶体管，晶体管70的工作原理与晶体管60的工作原理类似，由于 晶体管70中存在源区703、源区704以及导体711构成的冷源结构，因此该晶体管70的亚阈值摆幅也更小。
示例性的，本申请的实施例提供的晶体管中的导体至少包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分，其中，导体的第一部分设置于第一源区与衬底之间；导体的第二部分设置于第一源区的上方；导体的第三部分垂直于衬底，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分垂直于衬底，并且沿第一方向，设置于第一源区的第二侧。
参照图14所示，本申请的实施例三提供的晶体管70中的源区703(也就是上述的第一源区)以及源区704(也就是上述的第二源区)的结构示意图，其中，源区703与源区704接触形成接触面72，接触面72的四个顶点分别是顶点72-A、顶点72-B、顶点72-C以及顶点72-D。衬底701位于源区703的下方，如图14所示也就是衬底701与顶点72-A以及顶点72-B接触。导体711的第一部分设置于源区703与衬底701之间，如图14所示也就是导体的第一部分与顶点72-A以及顶点72-B接触，并且于衬底701接触；导体711的第二部分设置于源区703的上方，如图14所示也就是导体的第二部分与顶点72-C和顶点72-D接触；导体711的第三部分设置于衬底701上，并且沿x轴的方向(也就是上述的第一方向)，设置于源区703的第一侧，如图14所示也就是导体的第三部分与顶点72-A和顶点72-D接触；导体711的第四部分设置于衬底701上，并且沿x轴的方向(也就是上述的第一方向)，设置于源区703的第二侧，如图14所示也就是导体的第四部分与顶点72-B和顶点72-C接触。本申请的实施例中提供了多种导体设置的方式，在实际的应用中，可以任选导体的一个或多个部分以实现本申请的实施例提供的晶体管70的功能。
具体的，本申请的实施例提供了导体711的材料，导体711的材料至少包括以下一种或多种：硅化镍NiSi 2、硅化钛TiSi2、硅化钴CoSi2、钛Ti、钨W、氮化钛TiN、石墨烯。
示例性的，本申请的实施例提供的晶体管70中的第二源区与漏区的宽度可以相等，参照图15所示，本申请的实施例三提供了晶体管70的第二种结构示意图，该晶体管70中，源区704与漏区706的宽度相等，也就是说，源区704与漏区706关于栅极708对称，有助于工艺上制作出该晶体管70。
具体的，图13或图15所示的晶体管70中，源区703、源区704与漏区706内设置有掺杂物，其中，源区703设置的掺杂物为P型，源区704以及漏区706设置的掺杂物为N型，则该晶体管70构成N型晶体管。其中，沟道705也可以设置掺杂物，并且沟道705设置的掺杂物为P型。
或者，源区703设置的掺杂物为N型，源区704以及漏区706设置的掺杂物为P型，则该晶体管70构成P型晶体管。其中，沟道705也可以设置掺杂物，并且沟道705设置的掺杂物为N型。
示例性的，源区703、源区704以及漏区706中的一个或多个设置的掺杂物的浓度大于等于1e19原子/立方厘米。沟道705设置的掺杂物的浓度本申请的实施例不做限定。
示例性的，图13或图15所示的晶体管70中，栅极708上还设置有栅极金属层 713，其中，该栅极708所使用的材料具体是金属与多晶硅的复合结构，栅极金属层713的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。
示例性的，参照图13或图15所示的晶体管70，沟道705上沿x轴的方向(也就是上述的第一方向)还设置有侧墙712a(也就是上述的第一侧墙)和侧墙712b(也就是上述的第二侧墙)，绝缘层707以及栅极708以及栅极金属层713位于侧墙712a与侧墙712b之间，其中侧墙712a与源区704接触，侧墙712b与漏区706接触。
具体的，侧墙712a的材料至少包括以下一种或多种：二氧化硅SiO2、氮化硅Si 3N 4、碳氧氮化硅SiOCN、碳氮化硼硅SiBCN；侧墙712b的材料至少包括以下一种或多种：二氧化硅SiO2、氮化硅Si 3N 4、碳氧氮化硅SiOCN、碳氮化硼硅SiBCN。示例性的，晶体管70中的侧墙712a与侧墙712b往往采用同种材料制作。
示例性的，参照图16所示，本申请的实施例三提供了晶体管70的第三种结构示意图，该晶体管70还包括设置于衬底701上的介质714，介质714位于源区703与源区704之间；导体711与源区703、介质714以及源区704接触，并且介质714与导体711垂直。该介质714的存在，进一步阻碍热载流子从源区704隧穿至沟道705，以使得该晶体管70的亚阈值摆幅更小。
具体的，介质714的材料至少包括以下一种或多种：二氧化硅SiO 2，二氧化钛TiO 2、氧化铝Al 2O 3，介质714的厚度大于等于1纳米，并且小于等于10纳米。
参照图17所示，本申请的实施例二提供的晶体管60的制备方法，该晶体管60的制备方法包括如下步骤：
801.在衬底上制作氧化埋层。
具体的，参照图18所示，先准备好制作晶体管60所需要的衬底601，其中，衬底601的材料至少包括以下一种或多种：硅Si、锗硅SiGe、氮化镓GaN、铟镓砷InGaAs；衬底601中可以不设置掺杂物，或者，衬底601中可以设置掺杂物，设置的掺杂物可以提供P型载流子，衬底601的掺杂浓度在1e15原子/立方厘米～1e17原子/立方厘米之间。在准备好衬底601以后，在衬底601上制作氧化埋层602，氧化埋层602的材料至少包括以下一种或多种：二氧化硅SiO 2、氧化铝Al 2O 3、氧化铪HfO 2；氧化埋层602的厚度大于等于10纳米，并且小于等于1000纳米。其中可以采用沉积工艺、涂覆工艺等工艺在衬底601上制作氧化埋层602。
802.在氧化埋层上制作沿第一方向延伸的沟道层。
具体的，参照图19所示，在氧化埋层602上制作沟道层6051。其中，沟道层6051的材料至少包括以下一种或多种：硅Si、锗硅SiGe、氮化镓GaN、铟镓砷InGaAs；沟道层6051的厚度大于等于5纳米，并且小于等于500纳米。其中可以采用沉积工艺、涂覆工艺等工艺在衬底氧化埋层602上制作沟道层6051。需要说明的是，当前制作的沟道层6051是完全覆盖氧化埋层602的，这样的沟道层6051不符合要求，因此，需要在沟道层6051上涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻使得沟道层6051上形成有源区(该有源区即是晶体管60的第一源区、第二源区、沟道以及漏区所在的区域)的窗口，该有源区的窗口覆盖的沟道层6051需要保留，刻蚀掉有源区的窗口以外的沟道层6051，形成如图20所示的沟道层6052的结构，沟道层6052沿x 轴的方向延伸(也就是上述的第一方向)。其中，刻蚀可以采用干法刻蚀或湿法刻蚀，干法刻蚀一般使用氟基或卤族气体，例如六氟化硫SF6、三氟甲烷CHF3、氢溴酸HBr、氯气Cl2等，湿法刻蚀一般使用四甲基氢氧化铵C4H13NO(tetramethylammonium hydroxide,简称TMAH或TMAOH)溶液或者氢氧化钾KOH溶液。
示例性的，也可以直接准备一个绝缘上硅晶片，该绝缘上硅晶片包括衬底601，氧化埋层602以及沟道层6051，然后在绝缘上硅晶片中进行刻蚀形成沟道层6052。
803.在沟道层上制作沿第二方向延伸的绝缘层。
具体的，在参照图21所示，在沟道层上制作沿y轴的方向(也就是上述的第二方向)延伸的绝缘层。其中，需要在沟道层6052以及氧化埋层602上方涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成绝缘层607的窗口，并去除绝缘区607的窗口内的光刻胶，在绝缘区607的窗口内沉积绝缘层材料，绝缘层607的材料至少包括以下一种或多种：二氧化硅SiO 2、氧化铝Al 2O 3、氧化铪HfO 2；并且绝缘层607的厚度大于等于1纳米，并且小于等于30纳米，具体的沉积方式可以选用原子层沉积、热氧化、化学气相沉积等。
其中，x轴的方向与y轴的方向互相垂直，并且，x轴的方向与y轴的方向构成的平面平行于氧化埋层602。
804.制作覆盖绝缘层的第一栅极。
在步骤803以后，需要在绝缘层607上沉积覆盖绝缘层607的栅极608(也就是上述的第一栅极)。参照图22所示，其中，栅极608的材料至少包括以下一种或多种：多晶硅、金属，或者栅极608使用多晶硅与金属的复合结构；栅极608的厚度大于等于10纳米，并且小于等于500纳米。具体的沉积方式可以选用原子层沉积、热氧化、化学气相沉积等。
示例性的，参照图23所示，在栅极608的材料为多晶硅或者多晶硅与金属的复合结构时，还需要在栅极608上沉积一层栅极金属层614，栅极金属层614的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。栅极金属层614的沉积方式可以选用蒸发沉积或者物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得栅极金属层614内的原子分布均匀。
示例性的，参照图23所示，在栅极608以及栅极金属层614制作完成后，还需要在沟道层6052上沿x轴的方向(也就是上述的第一方向)制作侧墙612a和侧墙612b，绝缘层607以及栅极608位于侧墙612a和侧墙612b之间，其中侧墙612a与源区604接触，所述侧墙612b与漏区606接触。具体的，可以通过化学气相沉积或者原子层沉积的方式在当前的晶体管的上表面(也就是图23所示的氧化埋层602、沟道层6052、栅极金属层614的上方)沉积一层侧墙材料，其中，侧墙的材料至少包括以下一种或多种：二氧化硅SiO2、氮化硅Si 3N 4、碳氧氮化硅SiOCN、碳氮化硼硅SiBCN。在沉积好该一层侧墙材料以后，在侧墙材料上方涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成侧墙612a的窗口以及侧墙612b的窗口，保留侧墙612a的窗口以及侧墙612b的窗口内的侧墙材料，刻蚀掉侧墙712a的窗口以及侧墙712b的窗口以外的侧墙材料，形成侧墙612a以及侧墙612b。这里的刻蚀一般使用干法刻蚀，使用氟基或卤族气体，例如六氟化硫SF6、三氟甲烷CHF 3、氢溴酸HBr、氯气Cl 2等。
805.对沟道层注入提供载流子的掺杂物形成第一源区、第二源区以及漏区。
具体的，参照图24所示，在步骤804形成的晶体管的上表面(也就是图24所示的氧化埋层602、沟道层6052、栅极金属层614、侧墙612a以及侧墙612b的上方)涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成源区603的窗口，并去除源区603的窗口内的光刻胶，从源区603的窗口向沟道层6052注入提供载流子的掺杂物，形成源区603。随后，再涂覆一层光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成源区604的窗口和漏区606的窗口，并去除源区604的窗口和漏区606的窗口内的光刻胶，从源区604的窗口和漏区606的窗口向沟道层6052注入提供载流子的掺杂物，形成源区604和漏区606。
具体的，在制作源区603时，可以使用离子注入的方式，其中，注入的掺杂物可以使用硼B或者氟化硼BF 2，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，硼B或者氟化硼BF 2P型掺杂物可以提供P型载流子，也就是源区603设置的掺杂物为P型；在制作源区604和漏区606时，可以使用离子注入的方式，其中，注入的掺杂物可以使用砷As或磷P，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，砷As或磷P是N型掺杂物可以提供N型载流子，也就是源区604和漏区606设置的掺杂物为N型。
或者，具体的，在制作源区603时，可以使用离子注入的方式，其中，注入的掺杂物可以使用砷As或磷P，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，砷As或磷P是N型掺杂物可以提供N型载流子，也就是源区603设置的掺杂物为N型；在制作源区604和漏区606时，可以使用离子注入的方式，其中，注入的掺杂物可以使用硼B或者氟化硼BF 2，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，硼B或者氟化硼BF 2P型掺杂物可以提供P型载流子，也就是源区604和漏区606设置的掺杂物为P型。
示例性的，源区604与漏区606的宽度可以相等，或者，源区604与漏区606的宽度可以不相等，本申请的实施例对源区604与漏区606的宽度不做限制，并且在源区604与漏区606的宽度相等时，所使用的的离子注入的工艺相同即可，有利于工艺上实现。
至此，沟道层6052中仅有被绝缘层607遮挡的区域内没有注入提供载流子的掺杂物，该区域的沟道层6052即形成晶体管的沟道605。
806.在漏区上制作漏极，在第一源区上制作源极。
具体的，参照图25所示，在步骤805形成的晶体管的上表面(也就是图25所示的氧化埋层602、源区603、源区604、漏区606、栅极金属层614、侧墙612a以及侧墙612b的上方)涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成源极610的窗口和漏极609的窗口，并去除源极610的窗口和漏极609的窗口内的光刻胶，在源极610的窗口和漏极609的窗口沉积同种材料形成源极610和漏极609。其中，源极610的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物，漏极609的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。源极610 和漏极609的沉积方式可以选用蒸发沉积或者物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得源极610和漏极609内的原子分布均匀。
示例性的，也可以单独设置源极610的窗口沉积源极材料，然后再设置漏极609的窗口沉积漏极材料，源极材料和漏极材料可以相同也可以不同。
示例性的，参照图25所示，在一些情况下，也可以在衬底601远离源极610的一面设置栅极613的窗口，并在栅极613的窗口中沉积材料形成栅极613(也就是上述的第二栅极，也被称为背栅)，栅极613的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。栅极613的沉积方式可以选用蒸发沉积或者物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得栅极613内的原子分布均匀。
807.制作导体。
具体的，本申请的实施例提供的晶体管中的导体至少包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分，其中，导体的第一部分设置于第一源区与氧化埋层之间；导体的第二部分设置于第一源区的上方；导体的第三部分垂直于氧化埋层，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分垂直于氧化埋层，并且沿第一方向，设置于第一源区的第二侧。其中，源区603与源区604接触形成接触面，导体与源区603以及源区604接触，并且接触面与导体垂直。
具体的，在制作导体611的第一部分时，需要在氧化埋层上制作沿第一方向延伸的沟道层之前，制作导体的第一部分。具体的，需要在图18所示的氧化埋层602上涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻使得氧化埋层602上形成导体的第一部分的窗口，然后，利用沉积工艺在导体的第一部分的窗口中沉积导体材料，其中，导体的材料至少包括以下一种或多种：硅化镍NiSi 2、硅化钛TiSi2、硅化钴CoSi2、钛Ti、钨W、氮化钛TiN、石墨烯。具体的沉积工艺可以是蒸发沉积或物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得导体的第一部分711-a内的原子分布均匀。
参照图26以及图10所示，在同时制作导体的第二部分、导体的第三部分以及导体的第四部分时，具体的，参照图26所示，涂覆覆盖晶体管的光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成导体的第二部分的窗口(也就是在可以覆盖图10中顶点72-C和顶点72-D的位置设置导体的第二部分的窗口)，导体的第三部分的窗口(也就是在可以覆盖图10中顶点72-A和顶点72-D的位置设置导体的第三部分的窗口)，导体的第四部分的窗口(也就是在可以覆盖图10中顶点72-B和顶点72-C的位置设置导体的第二部分的窗口)，然后，利用沉积工艺在导体的第二部分的窗口、导体的第三部分的窗口以及导体的第四部分的窗口中沉积导体材料，其中，导体的材料至少包括以下一种或多种：硅化镍NiSi 2、硅化钛TiSi2、硅化钴CoSi2、钛Ti、钨W、氮化钛TiN、石墨烯。具体的沉积工艺可以是蒸发沉积或物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得导体的第二部分、导体的第三部分以及导体的第四部分内的原子分布均匀。
示例性的，在步骤806执行完成后，也可以先在源区603与源区604的接触区域 刻蚀形成凹槽；然后在凹槽中制作介质。具体的，涂覆覆盖晶体管的光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成介质窗口，然后去除该介质窗口内的光刻胶，并进行刻蚀形成凹槽，这里的刻蚀一般使用干法刻蚀，使用氟基或卤族气体，例如六氟化硫SF6、三氟甲烷CHF 3、氢溴酸HBr、氯气Cl 2等。然后，利用原子层沉积或者化学气相沉积的方式，在凹槽中沉积介质材料，介质的材料至少包括以下一种或多种：二氧化硅SiO 2，二氧化钛TiO 2、氧化铝Al 2O 3，介质的厚度大于等于1纳米，并且小于等于10纳米。然后，执行步骤807在介质上制作导体611，其中导体611与源区603、介质以及源区604接触，并且介质与导体垂直，以此形成如图12所示的晶体管60。
示例性的，上述的退火也可以仅执行一次，例如在制作晶体管的最后一步进行退火工艺。本申请的实施例提供的上述晶体管的制备方法的步骤仅是示意性的，在实际的应用中，上述的步骤可以更多或更少，上述的步骤的顺序也可以按照需要进行调整。
参照图27所示，本申请的实施例三提供的晶体管70的制备方法，该晶体管70的制备方法包括如下步骤：
901.在衬底上制作第一隔离槽和第二隔离槽。
具体的，参照图28所示，先准备好制作晶体管70所需要的衬底701，其中，衬底701的材料至少包括以下一种或多种：锗硅SiGe、氮化镓GaN、铟镓砷InGaAs；衬底701中可以不设置掺杂物，或者，衬底701中可以设置掺杂物，设置的掺杂物可以提供P型载流子，衬底701的掺杂浓度在1e15原子/立方厘米～1e17原子/立方厘米之间。在准备好衬底701以后，在衬底701上涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻使得衬底701上形成隔离槽702a的窗口以及隔离槽702b的窗口，然后，去除隔离槽702a的窗口以及隔离槽702b的窗口内的光刻胶，并对隔离槽702a的窗口以及隔离槽702b的窗口内的衬底701进行刻蚀，并且当前刻蚀不能将衬底701穿透。其中，刻蚀可以采用干法刻蚀或湿法刻蚀，干法刻蚀一般使用氟基或卤族气体，例如六氟化硫SF6、三氟甲烷CHF3、氢溴酸HBr、氯气Cl2等，湿法刻蚀一般使用四甲基氢氧化铵C4H13NO(tetramethylammonium hydroxide,简称TMAH或TMAOH)溶液或者氢氧化钾KOH溶液。在刻蚀掉隔离槽702a的窗口以及隔离槽702b的窗口内的衬底701以后，形成隔离槽702a的凹槽以及隔离槽702b的凹槽，然后在隔离槽702a的凹槽以及隔离槽702b的凹槽内填充二氧化硅SiO 2，形成隔离槽702a以及隔离槽702b，然后需要对隔离槽702a以及隔离槽702b进行机械抛光，使得隔离槽702a以及隔离槽702b的表面平整。并且，此时的衬底701的上表面即形成有源区图形(也就是源区703、源区704、沟道705以及漏区706所在区域的图形)。
902.在衬底上制作沿第二方向延伸的绝缘层。
具体的，在参照图29所示，在衬底701上制作沿y轴的方向(也就是上述的第二方向)延伸的绝缘层707。其中，需要在衬底701上方涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成绝缘层707的窗口，并去除绝缘区窗口内的光刻胶，在绝缘区窗口内沉积绝缘层材料，绝缘层707的材料至少包括以下一种或多种：二氧化硅SiO 2、氧化铝Al 2O 3、氧化铪HfO 2；并且绝缘层707的厚度大于等于1纳米，并且小于等于30纳米，具体的沉积方式可以选用原子层沉积、热氧化、化学气相沉积等。
903.制作覆盖绝缘层的栅极。
在步骤902以后，需要在绝缘层707上沉积覆盖绝缘层707的栅极708。参照图30所示，其中，栅极708的材料至少包括以下一种或多种：多晶硅、金属，或者栅极708使用多晶硅与金属的复合结构；栅极708的厚度大于等于10纳米，并且小于等于500纳米。具体的沉积方式可以选用原子层沉积、热氧化、化学气相沉积等。
示例性的，参照图31所示，在栅极708的材料为多晶硅或者多晶硅与金属的复合结构时，还需要在栅极708上沉积一层栅极金属层713，栅极金属层713的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。栅极金属层713的沉积方式可以选用蒸发沉积或者物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得栅极金属层713内的原子分布均匀。
示例性的，参照图31所示，在栅极708以及栅极金属层713制作完成后，还需要在衬底701上沿x轴的方向(也就是上述的第一方向)制作侧墙712a和侧墙712b，绝缘层707以及栅极708位于侧墙712a和侧墙712b之间，其中侧墙712a与源区704接触，所述侧墙712b与漏区706接触。具体的，可以通过化学气相沉积或者原子层沉积的方式在当前的晶体管的上表面(也就是图31所示的衬底701、隔离槽702a、隔离槽702b、栅极金属层713的上方)沉积一层侧墙材料，其中，侧墙的材料至少包括以下一种或多种：二氧化硅SiO2、氮化硅Si 3N 4、碳氧氮化硅SiOCN、碳氮化硼硅SiBCN。在沉积好盖一层侧墙材料以后，在侧墙材料上方涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成侧墙712a的窗口以及侧墙712b的窗口，保留侧墙712a的窗口以及侧墙712b的窗口内的侧墙材料，刻蚀掉侧墙712a的窗口以及侧墙712b的窗口以外的侧墙材料，形成侧墙712a以及侧墙712b。这里的刻蚀一般使用干法刻蚀，使用氟基或卤族气体，例如六氟化硫SF6、三氟甲烷CHF 3、氢溴酸HBr、氯气Cl 2等。
904.对衬底注入提供载流子的掺杂物形成沿第一方向延伸的第一源区、第二源区以及漏区。
具体的，参照图32所示，在步骤903形成的晶体管的上表面(也就是图32所示的衬底701、隔离槽702a、隔离槽702b、栅极金属层713、侧墙712a以及侧墙712b的上方)涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成源区703的窗口，并去除源区703的窗口内的光刻胶，从源区703的窗口向衬底701注入提供载流子的掺杂物，形成源区703。随后，再涂覆一层光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成源区704的窗口和漏区706的窗口，并去除源区704的窗口和漏区706的窗口内的光刻胶，在源区704的窗口和漏区706的窗口向衬底701注入提供载流子的掺杂物，形成源区704和漏区706。
具体的，在制作源区703时，可以使用离子注入的方式，其中，注入的掺杂物可以使用硼B或者氟化硼BF2，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，硼B或者氟化硼BF2为P型掺杂物可以提供P型载流子，也就是源区703设置的掺杂物为P型；在制作源区704和漏区706时，可以使用离子注入的方式，其中，注入的掺杂物可以使用砷As或磷P，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，砷As或磷P是N型掺杂物可以提供N型载流子，也就是源区704和漏区706设置的掺杂物为N型。
在制作源区703时，可以使用离子注入的方式，其中，注入的掺杂物可以使用砷As或磷P，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，砷As或磷P是N型掺杂物可以提供N型载流子，也就是源区703设置的掺杂物为N型；在制作源区704和漏区706时，可以使用离子注入的方式，其中，注入的掺杂物可以使用硼B或者氟化硼BF2，注入剂量在1e13原子/平方厘米～1e16原子/平方厘米之间，注入能量在1keV至100keV之间，硼B或者氟化硼BF2为P型掺杂物可以提供P型载流子，也就是源区704和漏区706设置的掺杂物为P型。
示例性的，源区704与漏区706的宽度可以相等，或者，源区704与漏区706的宽度可以不相等，本申请的实施例对源区704与漏区706的宽度不做限制，并且在源区704与漏区706的宽度相等时，所使用的的离子注入的工艺相同即可，有利于工艺上实现。
源区704与漏区706之间的部分衬底区域即是沟道705，其中，沟道705可以设置掺杂物，设置的掺杂物与源区703设置的掺杂物的类型相同即可。或者沟道705可以不设置掺杂物。
905.在漏区上制作漏极，在第一源区上制作源极。
具体的，参照图33所示，在步骤904形成的晶体管的上表面(也就是图33所示的衬底701、隔离槽702a、隔离槽702b、栅极金属层713、源区703、源区704、漏区706、侧墙712a以及侧墙712b的上方)涂敷光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成源极710的窗口和漏极709的窗口，并去除源极710的窗口和漏极709的窗口内的光刻胶，在源极710的窗口和漏极709的窗口沉积同种材料形成源极710和漏极709。其中，源极710的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物，漏极709的材料至少包括以下一种或多种：铝Al、镍Ni、钛Ti、金属硅化物。源极710和漏极709的沉积方式可以选用蒸发沉积或者物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得源极710和漏极709内的原子分布均匀。
示例性的，也可以单独设置源极710的窗口沉积源极材料，然后在设置漏极709的窗口沉积漏极材料，源极材料和漏极材料可以相同也可以不同。
906.制作导体。
具体的，本申请的实施例提供的晶体管中的导体711至少包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分，其中，导体的第一部分设置于第一源区与衬底之间；导体的第二部分设置于第一源区的上方；导体的第三部分垂直于衬底，并且沿第一方向，设置于第一源区的第一侧；导体的第四部分垂直于衬底，并且沿第一方向，设置于第一源区的第二侧。其中，源区703与源区704接触形成接触面，导体与源区703以及源区704接触，并且接触面与导体垂直。
参照图34以及图14所示，在制作导体的第二部分、导体的第三部分以及导体的第四部分时。具体的，参照图34所示涂覆覆盖晶体管的光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成导体的第二部分的窗口(也就是在可以覆盖图14中顶点72-C和顶点72-D的位置设置导体的第二部分的窗口)，导体的第三部分的窗口(也就是在可以覆盖图14中顶点72-A和顶点72-D的位置设置导体的第三部分的窗口)， 导体的第四部分的窗口(也就是在可以覆盖图14中顶点72-B和顶点72-C的位置设置导体的第四部分的窗口)，然后，利用沉积工艺在导体的第二部分的窗口、导体的第三部分的窗口以及导体的第四部分的窗口中沉积导体材料，其中，导体的材料至少包括以下一种或多种：硅化镍NiSi 2、硅化钛TiSi2、硅化钴CoSi2、钛Ti、钨W、氮化钛TiN、石墨烯。具体的沉积工艺可以是蒸发沉积或物理气相沉积，并且需要在沉积完成以后进行退火，一般退火温度为300摄氏度至900摄氏度之间，以使得导体的第二部分、导体的第三部分以及导体的第四部分内的原子分布均匀。
其中，导体的第一部分的制作，需要相应地刻蚀掉导体的第一部分所在区域内的部分源区703和部分源区704，形成导体的第一部分的凹槽，然后在导体的第一部分的凹槽中沉积导体材料。或者，导体的第一部分的制作，需要相应地刻蚀掉导体的第一部分所在区域内的部分衬底701，形成导体的第一部分的凹槽，然后在导体的第一部分的凹槽中沉积导体材料。
示例性的，在步骤905执行完成后，也可以先在源区703与源区704的接触区域刻蚀形成凹槽；然后在凹槽中制作介质。具体的，涂覆覆盖晶体管的光刻胶，利用遮光板对光刻胶进行遮挡，并进行光刻形成介质窗口，然后去除该介质窗口内的光刻胶，并进行刻蚀形成凹槽，这里的刻蚀一般使用干法刻蚀，使用氟基或卤族气体，例如六氟化硫SF6、三氟甲烷CHF 3、氢溴酸HBr、氯气Cl 2等。然后，利用原子层沉积或者化学气相沉积的方式，在凹槽中沉积介质材料，介质的材料至少包括以下一种或多种：二氧化硅SiO 2，二氧化钛TiO 2、氧化铝Al 2O 3，介质的厚度大于等于1纳米，并且小于等于10纳米。然后，在介质上制作导体，其中导体与源区703、介质以及源区704接触，并且介质与导体垂直，以此形成如图16所示的晶体管70。
示例性的，上述的退火也可以仅执行一次，例如在制作晶体管的最后一步进行退火工艺。本申请的实施例提供的上述晶体管的制备方法的步骤仅是示意性的，在实际的应用中，上述的步骤可以更多或更少，上述的步骤的顺序也可以按照需要进行调整。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (29)

  1. 一种晶体管，其特征在于，包括：
    衬底；
    所述衬底上沿平行于所述衬底的第一方向依次设置有第一源区、第二源区、沟道以及漏区；
    所述沟道上设置有绝缘层；
    所述绝缘层上设置有第一栅极；
    所述漏区上设置有漏极；
    所述第一源区上设置有源极；
    所述晶体管还包括导体，其中，所述第一源区与所述第二源区接触形成接触面，所述导体与所述第一源区以及所述第二源区接触，并且所述接触面与所述导体垂直。
  2. 根据权利要求1所述的晶体管，其特征在于，
    所述衬底上还设置有氧化埋层，所述第一源区、所述第二源区、所述沟道以及所述漏区设置于所述氧化埋层上。
  3. 根据权利要求2所述的晶体管，其特征在于，所述导体至少包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分；
    所述导体的所述第一部分设置于所述第一源区与所述氧化埋层之间；
    所述导体的所述第二部分设置于所述第一源区的上方；
    所述导体的所述第三部分设置于所述氧化埋层上，并且沿所述第一方向，设置于所述第一源区的第一侧；
    所述导体的所述第四部分设置于所述氧化埋层上，并且沿所述第一方向，设置于所述第一源区的第二侧。
  4. 根据权利要求2或3所述的晶体管，其特征在于，所述衬底远离所述源极的一面还设置有第二栅极。
  5. 根据权利要求1所述的晶体管，其特征在于，
    所述衬底内设置有第一隔离槽和第二隔离槽，所述第一隔离槽与所述第二隔离槽的开口朝向所述衬底的同一侧；所述第一源区、所述第二源区、所述沟道以及所述漏区设置于所述第一隔离槽与所述第二隔离槽之间。
  6. 根据权利要求5所述的晶体管，其特征在于，所述导体包括以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分；
    所述导体的所述第一部分设置于所述第一源区与所述衬底之间；
    所述导体的所述第二部分设置于所述第一源区的上方；
    所述导体的所述第三部分设置于所述衬底上，并且沿所述第一方向，设置于所述第一源区的第一侧；
    所述导体的所述第四部分设置于所述衬底上，并且沿所述第一方向，设置于所述第一源区的第二侧。
  7. 根据权利要求1-6任一项所述的晶体管，其特征在于，所述晶体管还包括设置于所述衬底上的介质，所述介质位于所述第一源区与所述第二源区之间；所述导体与所述第一源区、所述介质以及所述第二源区接触，并且所述介质与所述导体垂直。
  8. 根据权利要求7所述的晶体管，其特征在于，所述介质的材料至少包括以下一种或多种：二氧化硅，二氧化钛、氧化铝。
  9. 根据权利要求1-8任一项所述的晶体管，其特征在于，所述第二源区与所述漏区宽度相等。
  10. 根据权利要求1-9任一项所述的晶体管，其特征在于，所述第一栅极上还设置有栅极金属层。
  11. 根据权利要求1-10任一项所述的晶体管，其特征在于，所述沟道上沿所述第一方向还设置有第一侧墙和第二侧墙，所述绝缘层以及所述第一栅极位于所述第一侧墙与所述第二侧墙之间，其中所述第一侧墙与所述第二源区接触，所述第二侧墙与所述漏区接触。
  12. 根据权利要求1-11任一项所述的晶体管，其特征在于，所述导体的材料至少包括以下一种或多种：硅化镍、硅化钛、硅化钴、钛、钨、氮化钛、石墨烯。
  13. 根据权利要求1-12任一项所述的晶体管，其特征在于，所述第一源区、所述第二源区以及所述漏区内设置有掺杂物，所述第二源区和所述漏区设置的所述掺杂物为N型，所述第一源区设置的所述掺杂物为P型；
    或者，
    所述第二源区和所述漏区设置的所述掺杂物为P型，所述第一源区设置的所述掺杂物为N型。
  14. 根据权利要求13所述的晶体管，其特征在于，所述第一源区、所述第二源区以及所述漏区中的一个或多个设置的所述掺杂物的浓度大于等于1e19原子/立方厘米。
  15. 一种集成电路，其特征在于，所述集成电路包括封装结构以及一个或多个如权利要求1-14任一项所述的晶体管，所述晶体管封装于所述封装结构内部。
  16. 一种电子设备，其特征在于，包括印刷电路板以及如权利要求15所述的集成电路，所述集成电路与所述印刷电路板耦合。
  17. 一种晶体管的制备方法，其特征在于，
    在衬底上制作氧化埋层；
    在所述氧化埋层上制作沿第一方向延伸的沟道层；
    在所述沟道层上制作沿第二方向延伸的绝缘层，其中所述第一方向与所述第二方向垂直，并且所述第一方向与所述第二方向构成的平面平行于所述氧化埋层；
    制作覆盖所述绝缘层的第一栅极；
    对所述沟道层注入掺杂物形成第一源区、第二源区以及漏区；
    在所述漏区上制作漏极，在所述第一源区上制作源极；
    制作导体，其中，所述第一源区与所述第二源区接触形成接触面，所述导体与所述第一源区以及所述第二源区接触，并且所述接触面与所述导体垂直。
  18. 根据权利要求17所述的晶体管的制备方法，其特征在于，
    所述制作导体包括：在所述氧化埋层上制作沿第一方向延伸的沟道层，之前，在所述氧化埋层上制作所述导体的第一部分，其中所述沟道层覆盖所述第一部分；
    和/或，
    在所述漏区上制作漏极，在所述第一源区上制作源极，之后，制作所述导体的至 少以下一个或多个部分：第二部分、第三部分以及第四部分；
    所述导体的所述第二部分设置于所述第一源区的上方；
    所述导体的所述第三部分设置于所述氧化埋层上，并且沿所述第一方向，设置于所述第一源区的第一侧；
    所述导体的所述第四部分设置于所述氧化埋层上，并且沿所述第一方向，设置于所述第一源区的第二侧。
  19. 根据权利要求17或18所述的晶体管的制备方法，其特征在于，对所述沟道层注入掺杂物形成第一源区、第二源区以及漏区，具体包括：
    对所述沟道层注入N型掺杂物，形成第二源区以及漏区；对所述沟道层注入P型掺杂物，形成第一源区；
    或者，
    对所述沟道层注入P型掺杂物，形成第二源区以及漏区；对所述沟道层注入N型掺杂物，形成第一源区。
  20. 根据权利要求17-19任一项所述的晶体管的制备方法，其特征在于，所述制作覆盖所述绝缘层的第一栅极之后还包括：在所述第一栅极上制作栅极金属层。
  21. 根据权利要求17-20任一项所述的晶体管的制备方法，其特征在于，所述制作覆盖所述绝缘层的第一栅极之后还包括：在所述沟道层上沿所述第一方向制作第一侧墙和第二侧墙，所述绝缘层以及所述第一栅极位于所述第一侧墙与所述第二侧墙之间，其中所述第一侧墙与所述第二源区接触，所述第二侧墙与所述漏区接触。
  22. 根据权利要求17-21任一项所述的晶体管的制备方法，其特征在于，所述在所述漏区上制作漏极，在所述第一源区上制作源极之后，还包括：
    在所述衬底远离所述源极的一面制作第二栅极。
  23. 根据权利要求17-22任一项所述的晶体管的制备方法，其特征在于，所述在所述漏区上制作漏极，在所述第一源区上制作源极之后，还包括：
    在所述第一源区与所述第二源区的接触区域刻蚀形成凹槽；
    在所述凹槽中制作介质；
    则所述制作导体具体包括：在所述介质上制作导体；
    所述介质位于所述第一源区与所述第二源区之间；所述导体与所述第一源区、所述介质以及所述第二源区接触，并且所述介质与所述导体垂直。
  24. 一种晶体管的制备方法，其特征在于，
    在衬底上制作第一隔离槽和第二隔离槽，所述第一隔离槽与所述第二隔离槽的开口朝向所述衬底的同一侧；
    在所述衬底上制作沿第二方向延伸的绝缘层；
    制作覆盖所述绝缘层的栅极；
    对所述衬底注入提供载流子的掺杂物形成沿第一方向延伸的第一源区、第二源区以及漏区，所述第二源区与所述第一源区接触形成接触面，所述漏区与所述第二源区不接触，所述栅极位于所述漏区与所述第二源区之间，其中所述第一方向与所述第二方向垂直，并且所述第一方向与所述第二方向构成的平面平行于所述衬底；
    在所述漏区上制作漏极，在所述第一源区上制作源极；
    制作导体，所述导体与所述第一源区以及所述第二源区接触，并且所述接触面与所述导体垂直。
  25. 根据权利要求24所述的晶体管的制备方法，其特征在于，所述制作导体包括：
    制作所述导体的至少以下一个或多个部分：第一部分、第二部分、第三部分以及第四部分；
    所述导体的所述第一部分设置于所述第一源区与所述衬底之间；
    所述导体的所述第二部分设置于所述第一源区的上方；
    所述导体的所述第三部分设置于所述衬底上，并且沿所述第一方向，设置于所述第一源区的第一侧；
    所述导体的所述第四部分设置于所述衬底上，并且沿所述第一方向，设置于所述第一源区的第二侧。
  26. 根据权利要求24或25所述的晶体管的制备方法，其特征在于，所述对所述衬底注入提供载流子的掺杂物形成第一源区、第二源区以及漏区，具体包括：
    对所述衬底注入N型掺杂物，形成第二源区以及漏区；对所述衬底注入P型掺杂物，形成第一源区；
    或者，
    对所述衬底注入P型掺杂物，形成第二源区以及漏区；对所述衬底注入N型掺杂物，形成第一源区。
  27. 根据权利要求24-26任一项所述的晶体管的制备方法，其特征在于，所述制作覆盖所述绝缘层的栅极之后还包括：在所述栅极上制作栅极金属层。
  28. 根据权利要求24-27任一项所述的晶体管的制备方法，其特征在于，所述制作覆盖所述绝缘层的栅极之后还包括：在沟道上沿所述第一方向制作第一侧墙和第二侧墙，所述绝缘层以及所述栅极位于所述第一侧墙与所述第二侧墙之间，其中所述第一侧墙与所述第二源区接触，所述第二侧墙与所述漏区接触。
  29. 根据权利要求24-28任一项所述的晶体管的制备方法，其特征在于，所述在所述漏区上制作漏极，在所述第一源区上制作源极之后，还包括：
    在所述第一源区与所述第二源区的接触区域刻蚀形成凹槽；
    在所述凹槽中制作介质；
    则所述制作导体具体包括：在所述介质上制作导体；
    其中所述导体与所述第一源区、所述介质以及所述第二源区接触，并且所述介质与所述导体垂直。
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