WO2023070301A1 - Procédé, appareil et dispositif de simulation logique - Google Patents

Procédé, appareil et dispositif de simulation logique Download PDF

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Publication number
WO2023070301A1
WO2023070301A1 PCT/CN2021/126318 CN2021126318W WO2023070301A1 WO 2023070301 A1 WO2023070301 A1 WO 2023070301A1 CN 2021126318 W CN2021126318 W CN 2021126318W WO 2023070301 A1 WO2023070301 A1 WO 2023070301A1
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WO
WIPO (PCT)
Prior art keywords
logic
time frame
output
circuit
level
Prior art date
Application number
PCT/CN2021/126318
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English (en)
Chinese (zh)
Inventor
王柳峥
黄宇
张炜铭
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180100883.1A priority Critical patent/CN117751295A/zh
Priority to PCT/CN2021/126318 priority patent/WO2023070301A1/fr
Publication of WO2023070301A1 publication Critical patent/WO2023070301A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

Definitions

  • the calculation time of these logic gates can be omitted when no calculation is required, thereby further reducing the total time of logic simulation and also reducing computing resources Consumption of limited computing resources to process other logic gates that require computation. This further reduces the overall time for logic simulation.
  • the generation unit is further configured to: sequentially calculate the output of each level circuit frame by time frame; and based on the last time frame The output of each level circuit in the logic simulation output set is generated.
  • FIG. 2 shows a schematic block diagram of a simulation process of a logic circuit according to some embodiments of the present disclosure.
  • FIG. 8 shows a schematic diagram of a simulation process executed by a graphics processor according to some embodiments of the present disclosure.
  • the ATPG device 20 is configured to generate ATPG data for logic simulation and transmit the ATPG data to the electronic device 10 .
  • the ATPG device 20 may be integrated with the electronic device 10 , which is not limited by the present disclosure.
  • the electronic device 10 may include input devices, communication devices, displays, audio devices and other components not shown here.
  • the electronic device 10 may include, for example, devices with computing functions such as desktop computers, notebooks, workstations, and servers.
  • the netlist file used to describe the logic circuit can be transmitted to the electronic device 10 in various wired or wireless ways. Alternatively, the electronic device 10 may also use a storage medium storing the netlist file to read the netlist file.
  • the ATPG device 20 can generate different ATPG data for different logic circuits.
  • FIG. 3 shows an example circuit diagram of an illustrative logic circuit 30 according to some embodiments of the present disclosure.
  • the logic circuit 30 is only used to illustrate the principle of the present disclosure, but not to limit the scope of the present disclosure. It is understood that other configurations of logic circuits are also possible.
  • the logic circuit 30 may include, for example, a first original data input PI1, an AND gate 31, a first flip-flop U1, a second original data input PI2, an inverter 32, a second flip-flop U2, a first buffer 33, a second buffer device 34 and the original output PO.
  • the input of the AND gate 31 is coupled to the first raw data input PI1 and the output of the first flip-flop U1.
  • primitive inputs, primitive outputs and sequential logic gates may be divided into different levels.
  • the original output can be concentrated in the last stage of the combinational logic gate, or it can be distributed and arranged in the next stage of the respective driving sources closely following the respective driving sources.
  • the CPU judges whether the current time frame is the last time frame? If the current time frame is the last time frame, proceed to 620 to end the logic simulation. If not the last time frame, proceed to 618. At 618, the CPU sets the next time frame as the current time frame, and loops through 608-616 until the last time frame is reached and the logic simulation ends.
  • the original input, the original output and the sequential logic gate may be divided into circuits of different levels based on their respective connection relationships.
  • the second-level circuits including combinational logic gates may also be divided into different sub-level circuits. This disclosure is not limited in this regard.
  • FIG. 13 shows a schematic block diagram of an electronic device 1300 according to some embodiments of the present disclosure.
  • the electronic device 1300 may include multiple modules for performing corresponding steps in the methods discussed in FIGS. 6-12 .
  • an electronic device 1300 includes a receiving unit 1302 and a generating unit 1304 .
  • the receiving unit 1302 is used for receiving hierarchical data of the logic circuit.
  • the hierarchical data represents multiple hierarchical circuits of the logical circuit, and the multiple hierarchical circuits are divided based on the connection relationship of multiple logic gates in the logical circuit.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé et un dispositif de simulation d'un circuit logique. Le procédé comprend : à classer un circuit logique, et effectuer un calcul parallèle sur une pluralité de portes logiques dans les étages classés à l'aide d'un vecteur de test par une GPU dans la même trame temporelle de façon à obtenir finalement un ensemble de sortie de simulation logique. Par comparaison avec une simulation série classique exécutée par une CPU telle qu'un codage dur, la GPU effectue une simulation parallèle sur une pluralité de portes logiques dans le circuit classé, de telle sorte que le temps de simulation logique peut être considérablement raccourci.
PCT/CN2021/126318 2021-10-26 2021-10-26 Procédé, appareil et dispositif de simulation logique WO2023070301A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180100883.1A CN117751295A (zh) 2021-10-26 2021-10-26 用于逻辑仿真的方法、装置及设备
PCT/CN2021/126318 WO2023070301A1 (fr) 2021-10-26 2021-10-26 Procédé, appareil et dispositif de simulation logique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/126318 WO2023070301A1 (fr) 2021-10-26 2021-10-26 Procédé, appareil et dispositif de simulation logique

Publications (1)

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WO2023070301A1 true WO2023070301A1 (fr) 2023-05-04

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CN (1) CN117751295A (fr)
WO (1) WO2023070301A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07294604A (ja) * 1994-04-28 1995-11-10 Nec Corp Ｌｓｉテスト回路
US20030110457A1 (en) * 2001-10-30 2003-06-12 Benoit Nadeau-Dostie Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby
US7181705B2 (en) * 2000-01-18 2007-02-20 Cadence Design Systems, Inc. Hierarchical test circuit structure for chips with multiple circuit blocks
CN110007200A (zh) * 2019-01-11 2019-07-12 华为技术有限公司 一种测试电路、设备及***
CN112394281A (zh) * 2021-01-20 2021-02-23 北京燧原智能科技有限公司 测试信号并行加载转换电路和***级芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07294604A (ja) * 1994-04-28 1995-11-10 Nec Corp Ｌｓｉテスト回路
US7181705B2 (en) * 2000-01-18 2007-02-20 Cadence Design Systems, Inc. Hierarchical test circuit structure for chips with multiple circuit blocks
US20030110457A1 (en) * 2001-10-30 2003-06-12 Benoit Nadeau-Dostie Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby
CN110007200A (zh) * 2019-01-11 2019-07-12 华为技术有限公司 一种测试电路、设备及***
CN112394281A (zh) * 2021-01-20 2021-02-23 北京燧原智能科技有限公司 测试信号并行加载转换电路和***级芯片

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