WO2023060649A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2023060649A1
WO2023060649A1 PCT/CN2021/126693 CN2021126693W WO2023060649A1 WO 2023060649 A1 WO2023060649 A1 WO 2023060649A1 CN 2021126693 W CN2021126693 W CN 2021126693W WO 2023060649 A1 WO2023060649 A1 WO 2023060649A1
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WIPO (PCT)
Prior art keywords
line
lines
wire
clock signal
connection
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PCT/CN2021/126693
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English (en)
French (fr)
Inventor
陈志祥
王添鸿
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2023060649A1 publication Critical patent/WO2023060649A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • the normal display of the active area is jointly controlled by the scan line (Gateline) and the data line (Dataline).
  • the voltage signal required by the pixel is jointly controlled by the scan line (Gateline) and the data line (Dataline).
  • the Gateline signal is transmitted from the bus (Busline) to the gate drive unit (GOA Circuit), and then input to the Gateline wiring in the AA area through the GOA Circuit.
  • the CKs in the Busline are sorted from the inside to the outside. Taking 8 clock signals as an example, the outermost CK8 needs to cross CK7 ⁇ CK1 to connect to the GOA unit, and CK1 does not need to cross other CKs. Therefore, there are differences in the resistance and capacitance between CK1 ⁇ 8, which in turn leads to differences in the GN waveforms of two adjacent rows of Gatelines. Because of the difference in the resistance and capacitance of adjacent CK wires, there are differences in the scanning signal waveforms output by two adjacent rows of Gatelines, resulting in significant differences in brightness due to charging differences, which in turn causes periodic horizontal dense lines to appear on the product.
  • Embodiments of the present application provide an array substrate and a display panel, which can improve lateral capacitance differences between traces.
  • An embodiment of the present application provides an array substrate, including:
  • a plurality of clock signal lines, the plurality of clock signal lines are arranged on one side of the GOA unit and arranged in sequence along the first direction;
  • a plurality of communication lines one of the communication lines is correspondingly connected to one of the clock signal lines and one of the GOA units;
  • the communication line includes a first part, a winding part and a second part connected in sequence, the first part is connected to the clock signal line, The second part is connected to the GOA unit; the winding part is arranged in the winding area;
  • the winding part includes a first connecting line, a second connecting line and a bent connecting line, and the bent connecting line is connected between the first connecting line and the second connecting line; the first connecting line set opposite to the clock signal line, and the second connection line is set opposite to the GOA unit;
  • the multiple first connection lines are respectively equal to the lateral capacitance formed by the clock signal line, and/or the multiple second connection lines are respectively equal to the lateral capacitance formed by the GOA unit.
  • the lengths of the multiple first connecting lines are the same, and/or, the multiple second connecting lines The lines are the same length.
  • the distances between the multiple first connection lines and the clock signal line are equal, and/or, the multiple second connection lines Lines are equidistant from the GOA units.
  • the multiple communication lines have the same length.
  • the first connection line includes a first line, a second line and a third line, and the first line is arranged away from the bent connection line on one side of the cable, the second wiring is spaced apart from the first wiring, the second wiring is connected to the bent connection line, and the third wiring is connected between the first wiring and the Between the second traces, the lengths of the first traces and the second traces are the same or different.
  • the second connecting wire includes a first wire, a second wire and a third wire, and the first wire is arranged on a side away from the bent connecting wire, The second wire is arranged parallel to the first wire with a gap, the second wire is connected to the bent connecting wire, and the third wire is connected between the first wire and the second wire Between, the lengths of the first wire and the second wire are the same or different.
  • each of the communication lines includes a first connection line, a second connection line, and a bent connection line.
  • each of the communication lines includes at least two of the first connection lines, at least two of the second connection lines, and one of the bent connection lines.
  • the bending connection line includes a plurality of bending units connected in sequence, and the bending units are respectively connected to the first connection line and the second connection line through wiring. connection line.
  • At least one parallel wiring is further connected to the bending unit, and the parallel wiring is arranged in parallel with the bending connection line.
  • each of the clock signal lines is connected to multiple communication lines, and a set of communication lines including at least one communication line is arranged along the clock signal line The directions are connected to the clock signal lines in turn.
  • the first portion in a second direction intersecting with the first direction, gradually increases, and the bent connection lines The bending length gradually decreases.
  • the first portion in a second direction intersecting with the first direction, gradually increases, and the bending connecting lines The bending distance between them gradually decreases.
  • the embodiment of the present application also provides a display panel, including:
  • the array substrate the array substrate
  • It includes a plurality of GOA units, a plurality of clock signal lines and a plurality of communication lines, and the plurality of clock signal lines are arranged on one side of the GOA unit and arranged in sequence along the first direction; one communication line is correspondingly connected a clock signal line and a GOA unit;
  • the communication line includes a first part, a winding part and a second part connected in sequence, the first part is connected to the clock signal line, The second part is connected to the GOA unit; the winding part is arranged in the winding area;
  • the winding part includes a first connecting line, a second connecting line and a bent connecting line, and the bent connecting line is connected between the first connecting line and the second connecting line; the first connecting line set opposite to the clock signal line, and the second connection line is set opposite to the GOA unit;
  • a plurality of the first connection lines are respectively equal to the lateral capacitance formed by the clock signal line, and/or, a plurality of the second connection lines are respectively equal to the lateral capacitance formed by the GOA unit; the opposite substrate , the opposite substrate is disposed opposite to the array substrate, and electrodes are disposed on the opposite substrate corresponding to the communication lines and the clock signal lines.
  • the lengths of the multiple first connecting lines are the same, and/or, the multiple second connecting lines The lines are the same length.
  • the distances between the multiple first connection lines and the clock signal line are equal, and/or, the multiple second connection lines Lines are equidistant from the GOA units.
  • the first connection line includes a first line, a second line and a third line, and the first line is arranged away from the bent connection line on one side of the cable, the second wiring is spaced apart from the first wiring, the second wiring is connected to the bent connection line, and the third wiring is connected between the first wiring and the Between the second traces, the lengths of the first traces and the second traces are the same or different.
  • the second connecting wire includes a first wire, a second wire and a third wire, and the first wire is arranged on a side away from the bent connecting wire, The second wire is arranged parallel to the first wire with a gap, the second wire is connected to the bent connecting wire, and the third wire is connected between the first wire and the second wire Between, the lengths of the first wire and the second wire are the same or different.
  • the bending connection line includes a plurality of bending units connected in sequence, and the bending units are respectively connected to the first connection line and the second connection line through wiring. connection line.
  • At least one parallel wiring is further connected to the bending unit, and the parallel wiring is arranged in parallel with the bending connection line.
  • the embodiment of the application discloses an array substrate and a display panel.
  • the array substrate provided by the embodiment of the present application includes multiple GOA units, multiple clock signal lines, and multiple communication lines.
  • the lengths of the multiple communication lines are the same, and there is a winding area between the clock signal line and the GOA unit.
  • the communication line is bent and set in the winding area.
  • the multiple communication lines have the same lateral capacitance on at least one side close to the clock signal line or close to the GOA unit.
  • the lateral capacitance of the communication line on the same side can be matched consistently.
  • the problem that the lateral capacitances generated by the communication lines in different rows and the surrounding wiring are different is solved.
  • the total length of the communication wires in different rows is consistent, and the problem of inconsistent resistance and capacitance of the communication wires in different rows is also solved, thereby improving the reliability of the bright and dark lines of the panel. question.
  • FIG. 1 is a schematic diagram of the first structure of an array substrate provided by an embodiment of the present application.
  • Fig. 2 is a schematic diagram of the first structure of the communication line in the array substrate provided by the embodiment of the present application;
  • Fig. 3 is a second structural schematic diagram of the communication line in the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a third structure of communication lines in an array substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the second structure of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a fourth structure of communication lines in an array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fifth structure of communication lines in an array substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a sixth structure of communication lines in an array substrate provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a fourth structure of an array substrate provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Embodiments of the present application provide an array substrate and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a first structure of a communication line in an array substrate provided by an embodiment of the present application.
  • the array substrate 10 includes multiple GOA units 101 , multiple clock signal lines 102 and multiple communication lines 103 .
  • a plurality of clock signal lines 102 are arranged on one side of the GOA unit 101 and arranged sequentially along the first direction x.
  • the first direction x is a direction extending along the x-axis in the figure, which is expressed as the first direction x in the embodiment of the present application.
  • a communication line 103 is correspondingly connected to a clock signal line 102 and a GOA unit 101 . Wherein, there is a winding area 10 a between the clock signal line 102 and the GOA unit 101 .
  • the communication line 103 includes a first part 103A, a winding part 103B and a second part 103C connected in sequence.
  • the first part 103A is connected to the clock signal line 102 .
  • the second part 103C is connected to the GOA unit 101 .
  • the wire winding portion 103B is provided in the wire winding area 10a.
  • the winding part 103B includes a first connecting wire 1031 , a second connecting wire 1032 and a bent connecting wire 1033 .
  • the bent connection line 1033 is connected between the first connection line 1031 and the second connection line 1032 .
  • the first connection line 1031 is opposite to the clock signal line 102 .
  • the second connection line 1032 is provided in pairs with the GOA unit 101 .
  • the multiple first connection lines 1031 are respectively equal to the lateral capacitance formed by the clock signal line 102
  • the multiple second connection lines 1032 are respectively equal to the lateral capacitance formed by the GOA unit 101 .
  • FIG. 1 illustrates an array substrate 10 with 8 clock signals as an example.
  • the array substrate 10 provided in the embodiment of the present application does not limit the number of clock signals. For example, it can also be applied to an array substrate with 12 clock signals. 10, or an array substrate 10 applied to 16 clock signals.
  • the clock signal lines 102 of an 8CK array substrate include CK1, CK2, CK3, CK4, CK5, CK6, CK7 and CK8.
  • the resistance and capacitance of the communication lines 103 of CK1 to CK8 are the same, which is realized by the winding compensation of the communication lines 103 in the winding area 10a.
  • CK8 Since CK8 is connected to the GOA unit 101 , it needs to cross the wiring from CK1 to CK7 , while CK1 does not need to cross other clock signal lines 102 . Therefore, if no winding compensation is performed, the trace of CK1 is the shortest, and the trace of CK8 is the longest. This will result in differences in the capacitance and resistance of the clock signal lines 102 from CK1 to CK8 . However, if the winding design is performed, the communication line 103 has a length in the second direction y, thereby increasing the direct facing area of the communication line 103 and the surrounding wiring in the second direction y.
  • the second direction y is a direction extending along the y-axis in the figure, which is expressed as the second direction y in the embodiment of the present application.
  • the first direction x and the second direction y are perpendicular to each other as an example, but it is not limited to the first direction x and the second direction y.
  • the first direction x intersects the second direction y.
  • the lateral capacitance refers to the capacitance generated in the area where the communication line 103 and the wiring in the GOA unit 101 or the clock signal line 102 are facing each other.
  • the winding area of CK1 is larger and the winding area of CK8 is smaller, so the lateral capacitance generated between CK1 to CK8 and the GOA unit 101 and the clock signal line 102 is different.
  • the difference in the lateral capacitance will also lead to the difference in the waveform of the output scanning signal, which will cause the problem of bright and dark lines on the panel display.
  • the communication line 103 and the clock signal line 102 are arranged in different layers.
  • the relative arrangement of the first connection line 1031 , the second connection line 1032 and the clock signal line 102 in the communication line 103 refers to the relative arrangement of different layers.
  • the embodiment of the present application provides an array substrate 10 .
  • the array substrate 10 includes multiple GOA units 101 , multiple clock signal lines 102 and multiple communication lines 103 .
  • the communication line 103 is bent and arranged in the winding area 10a.
  • the communication line 103 includes at least one first connection line 1031 , at least one second connection line 1032 and a bent connection line 1033 .
  • the first connection wire 1031 is disposed on a side of the winding area 10 a close to the clock signal wire 102 and opposite to the clock signal wire 102 .
  • the second connection wire 1032 is disposed on a side of the winding area 10 a close to the GOA unit 101 and opposite to the GOA unit 101 .
  • the bent connection line 1033 connects the first connection line 1031 and the second connection line 1032 .
  • the plurality of first connection lines 1031 are respectively equal to the lateral capacitance formed by the clock signal line 102
  • the plurality of second connection lines 1032 are respectively equal to the lateral capacitance formed by the GOA unit 101 .
  • the communication line 103 refers to a bus, which may also be called a communication trunk line (Busline).
  • Busline is a public communication trunk line for transmitting information between various functional components, and it is a transmission harness composed of wires.
  • the clock signal from the clock signal line 102 is transmitted to the GOA unit 101 by the communication line 103, and then the GOA unit 101 outputs the scanning signal to the scanning line of the effective display area of the panel.
  • the plurality of first connection lines 1031 described in the embodiment of the present application are respectively equal to the lateral capacitance formed by the clock signal line 102, and/or, the plurality of second connection lines 1032 are respectively equal to the lateral capacitance formed by the GOA unit 101. Capacitance is equal.
  • the lateral capacitance is mainly affected by the relative area and distance between two adjacent traces.
  • the lengths of the multiple first connecting lines 1031 are the same, and/or the lengths of the multiple second connecting lines 1032 are the same.
  • the lateral capacitance is completely positively correlated with the length of the adjacent traces. Therefore, it is ensured that the communication lines 103 on the same side have the same length and the same lateral capacitance. Therefore, in the winding area 10a, the communication lines 103 on the side close to the clock signal line 102 are designed to have the same bending length, or the communication lines 103 on the side close to the GOA unit 101 have the same bending length, so that the communication lines 103 can be At least one side of the lateral capacitance matching. Thus, the problem that the lateral capacitances generated by the communication lines 103 in different rows and the surrounding lines are different is solved.
  • FIG. 2 shows a partially enlarged schematic diagram of the first row and the second row of communication lines 103 in FIG. 1 .
  • the bending length of the first connecting lines 1031 in the first row in FIG. 2 is D1
  • the bending length of the first connecting lines 1031 in the second row is D2.
  • the lengths of D1 and D2 are the same.
  • the bending lengths of the second connecting lines 1032 in the first row and the second connecting lines 1032 in the second row may be different.
  • the bending length of the second connecting lines 1032 in the first row is Da
  • the bending length of the second connecting lines 1032 in the second row is Db.
  • the lengths of Da and Db are the same.
  • the bending lengths of the first connecting lines 1031 in the first row and the first connecting lines 1031 in the second row may be different.
  • the bending lengths of the multiple first connecting wires 1031 are the same, and the multiple second connecting wires 1032 are the same. That is, D1 and D2 have the same length, and Da and Db have the same length.
  • the bending lengths of the multiple first connecting wires 1031 and the bending lengths of the multiple second connecting wires 1032 are the same. That is, D1, D2, Da, and Db may all have the same length.
  • the distance G1 between the plurality of first connection lines 1031 and the clock signal line 102 is equal, and/or the distance G2 between the plurality of second connection lines 1032 and the GOA unit 101 is equal.
  • the lengths of the multiple communication lines 103 are the same. Since the communication lines 103 are designed to be wound in the winding area 10a, the total lengths of the communication lines 103 in different rows are consistent, and the problem of inconsistent resistance and capacitance of the communication lines 103 in different rows is also solved.
  • the array substrate 10 provided in the embodiment of the present application can improve the bright and dark lines of the panel by designing the bending manner of the communication lines 103 .
  • FIG. 3 is a second structural schematic diagram of the communication lines in the array substrate provided by the embodiment of the present application.
  • the first connecting wire 1031 includes a first routing 103 a , a second routing 103 b and a third routing 103 c , and the first routing 103 a is disposed on a side away from the bent connecting wire 1033 .
  • the second trace 103b is arranged parallel to the first trace 103a with a gap.
  • the second wiring 103b is connected to the bent connection line 1033 .
  • the third wiring 103c connects the first wiring 103a and the second wiring 103b.
  • the lengths of the first wiring 103a and the second wiring 103b are the same or different.
  • FIG. 1 and FIG. 3 show a structure in which the lengths of the first wiring 103a and the second wiring 103b are the same.
  • FIG. 4 is a schematic diagram of a third structure of a communication line in an array substrate provided by an embodiment of the present application.
  • the second connection wire 1032 includes a first wire 103d, a second wire 103e and a third wire 103f.
  • the first wire 103d is disposed on a side away from the bent connecting wire 1033 .
  • the second wire 103e is arranged parallel to the first wire 103d with a gap.
  • the second wire 103e is connected to the bent connection wire 1033 .
  • the third wire 103f connects the first wire 103d and the second wire 103e.
  • the lengths of the first wire 103d and the second wire 103e are the same or different.
  • FIG. 1 and FIG. 3 show the structure that the length of the first wire 103d is the same as that of the second wire 103e.
  • FIG. 5 is a schematic diagram of the second structure of the array substrate provided by the embodiment of the present application.
  • the difference between the embodiment shown in FIG. 5 and the embodiment shown in FIG. 1 lies in that the lengths of the first wiring 103 a and the second wiring 103 b in FIG. 5 are different.
  • each clock signal line 102 is connected to multiple communication lines 103 .
  • a group of communication lines 103 including at least one communication line 103 is sequentially connected to the clock signal line 102 along the arrangement direction of the clock signal line 102 . That is, the communication line 103 is connected to the clock signal line 102 sequentially in a periodic arrangement.
  • FIG. 1 illustrates an arrangement of communication lines 103 of one cycle. In the next cycle, the communication line 103 repeats the connection sequence shown in FIG. 1 to be connected to the clock signal line 102 . It can be understood that, in different situations, the sequence of connecting the communication lines 103 may be selected according to the clock signal lines 102 to be connected to the GOA unit 101 .
  • the connection order of the communication lines 103 is changed, the bending manner of the communication lines 103 also needs to be changed accordingly, so as to ensure that the total length of the communication lines 103 connected to different clock signal lines 102 is consistent.
  • FIG. 6 is a schematic diagram of a fourth structure of communication lines in an array substrate provided by an embodiment of the present application.
  • the first portion 103A gradually increases, and the bending length of the bent connection line 1033 gradually decreases.
  • 8CK is still taken as an example for illustration, wherein the bending lengths of the bending connecting lines 1033 corresponding to CK1, CK2, CK3, CK4, CK5, CK6, CK7 and CK8 are d1, d2, d3, d4, d5, d6, d7, and d8.
  • each group of communication lines 103 is sequentially connected to the clock signal line 102 from CK8 to CK1 along the arrangement direction of the clock signal line 102, the bending length is d8 ⁇ d7 ⁇ d6 ⁇ d5 ⁇ d4 ⁇ d3 ⁇ d2 ⁇ d1.
  • d8 may be 0, that is to say, the bent connection line 1033 of CK8 may not be bent, and directly connects the first connection line 1031 and the second connection line 1032 of CK8.
  • FIG. 7 is a schematic diagram of a fifth structure of communication lines in the array substrate provided by the embodiment of the present application.
  • the first portion 103A gradually increases, and the bending distance between the bent connection lines 1033 gradually decreases.
  • the above embodiments are described by taking the order in which the communication line 103 is sequentially connected to the clock signal lines 102 of CK8 to CK1 as an example.
  • the bending area, bending length or bending density of the communication lines 103 should be changed correspondingly.
  • any one of the bending area, bending length, and bending density is increased or decreased. It is also possible to design any two or three of the bending area, bending length and bending density.
  • the foregoing embodiments are described by using these several wire winding methods as examples. In fact, there may be other wire winding methods, as long as the total length of the communication lines of each row is consistent.
  • FIG. 8 is a schematic diagram of a sixth structure of a communication line in an array substrate provided by an embodiment of the present application. Since the size of the resistance is inversely proportional to the wiring area, in order to match the resistance of the communication lines 103 between different rows under the condition that the length of the communication lines 103 is consistent, the width of the longer communication lines 103 can also be appropriately increased to The resistance of the communication line 103 is reduced. Likewise, the width of the shorter communication line 103 can be appropriately reduced to increase the resistance of the communication line 103 . Thus, the problem of uneven resistance among the communication lines 103 in different rows is reduced.
  • multiple communication lines 103 are connected to one clock signal line 102 , and a group of communication lines 103 including at least one communication line 103 are sequentially connected to the clock signal lines 102 along the arrangement direction of the clock signal line 102 .
  • the communication line 103 connected to CK1 has the smallest line width
  • the communication line 103 connected to CK8 has the largest line width, so as to match the resistances of communication lines 103 in different rows.
  • FIG. 9 is a schematic diagram of a third structure of the array substrate provided by the embodiment of the present application.
  • the bending connection line 1033 includes a plurality of bending units 1033a connected in sequence.
  • the bending unit 1033a is respectively connected to the first connection line 1031 and the second connection line 1032 through wiring.
  • At least one parallel wiring 104 is also connected to the bending unit 1033a.
  • the parallel wiring 104 is arranged in parallel with the bent connection line 1033 .
  • the bending manner of the bending connection line 1033 may be zigzag, serpentine, pulse, concave-convex zigzag, wave or zigzag.
  • the bending connection line 1033 in the bending unit 1033a has two traces extending along the first direction, and the two traces are connected by a trace extending along the second direction.
  • These several bending forms can bend longer communication lines 103 in a small space, save the space for arranging the communication lines 103 , and are beneficial to narrow the frame of the panel.
  • the bent connection line 1033 is bent into a pulse shape for illustration.
  • the bending lengths of the plurality of first connecting lines 1031 and the bending lengths of the plurality of second connecting lines 1032 are the same, and the length of the first connecting lines 1031 is longer than that of the bending unit 1033a. length.
  • the length of the first connecting line 1031 is greater than the length of the bending unit 1033a, so that the arrangement of the first connecting line 1031 and the bending connecting line 1033 in the bending unit 1033a can be staggered, and the connection between the first connecting line 1031 and the bending can be reduced. Risk of shorting of line 1033.
  • a parallel wiring 104 is connected to the bent connection line 1033 .
  • the parallel wiring 104 is arranged in parallel with the bent connection line 1033 . Since different rows of communication wires 103 have different bending designs in the winding area 10a, uneven etching may occur during the manufacturing process. Therefore, the etching uniformity can be improved by connecting the parallel wires 104 in the middle.
  • the design of the parallel wiring 104 is equivalent to connecting a resistor in parallel with the bent connection line 1033 .
  • adding the parallel wiring 104 can also improve the connection stability of the bent connecting wire 1033 .
  • the width of the winding area 10a cannot be too large, and the bending design of the bending connection line 1033 in the winding area 10a is relatively small, and the adjacent bending connection If the distance between the lines 1033 is narrow, the problem of disconnection is likely to occur during etching.
  • Connecting at least one parallel wire 104 in the bent connection wire 1033 can avoid the problem that the signal cannot be transmitted after a section of the communication wire 103 is disconnected.
  • the number of parallel wiring 104 can be increased in areas where wiring is denser.
  • the length of the bent connection line 1033 of the communication line 103 of CK8 is shorter, and the bending density in the routing area 10 a is smaller, so the number of parallel wiring 104 can be reduced.
  • the length of the bent connecting line 1033 of the communication line 103 of CK1 is longer, and the bending density in the winding area 10 a is higher, so the number of parallel wiring 104 can be increased.
  • the number of bending columns of the communication line 103 may be considered according to the lateral distance.
  • There is no fixed standard and range for the lateral distance which needs to be considered comprehensively based on factors such as resolution and the number of clock signal lines 102 .
  • a small difference between the clock signals of the GOA has a greater impact on the pixel display, and the more the number of clock signal lines 102 is, the greater the difference in lateral capacitance will be.
  • the distance between the clock signal lines 102 needs to be reduced, that is, the bending length of the communication line 103 is higher, so the lateral facing area will become larger.
  • the width of the winding area 10a needs to be reduced. Reducing, that is, reducing the number of bending columns of the communication line 103 . Therefore, optionally, the number of clock signal lines 102 is inversely proportional to the number of bending columns of communication lines 103 .
  • each communication line 103 includes a first connection line 1031 , a second connection line 1032 and a bent connection line 1033 .
  • each communication line 103 includes two adjacent first connection lines 1031 , two adjacent second connection lines 1032 and a bent connection line 1033 .
  • FIG. 10 is a schematic diagram of a fourth structure of the array substrate provided by the embodiment of the present application. In the embodiment shown in FIG. 10 , in the winding area 10 a, the bending lengths of the first connecting wire 1031 or the second connecting wire 1032 are the same.
  • the number of bending columns, bending length, bending area, and bending density of the communication line 103 for matching the lateral capacitance there is no limitation on the number of bending columns, bending length, bending area, and bending density of the communication line 103 for matching the lateral capacitance.
  • the bending length of the communication lines 103 on the same side is the same, which can be used to improve the problem of uneven lateral capacitance.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 includes an array substrate 10 and an opposite substrate 20 .
  • the array substrate 10 is the array substrate 10 described above.
  • the array substrate includes a substrate 105 , clock signal lines 102 and communication lines 103 .
  • the opposite substrate 20 is disposed opposite to the array substrate 10 .
  • the opposite substrate 20 includes a substrate 105 , and electrodes 106 are provided on the opposite substrate 20 corresponding to the communication lines 103 and the clock signal lines 102 .
  • the communication line 103 is disposed on the array substrate 10 .
  • the bending lengths of the communication lines 103 on the same side of the winding area are the same, so that the lateral capacitance of the communication lines 103 in different rows is balanced.
  • the capacitance between the communication line 103 and the electrode 106 in different rows can be balanced, thereby also balancing the capacitance between the communication line 103 and the electrode 106. compensation.
  • array substrate 10 and the opposite substrate 20 may also include other devices, and the other devices and their assembly are technologies well known to those skilled in the art, and will not be repeated here.
  • An embodiment of the present application provides a display panel, and the display panel includes an array substrate and an opposite substrate.
  • the array substrate in the display panel provided in the embodiment of the present application has a wire-winding design for the communication lines provided on the array substrate.
  • the lengths of the multiple communication lines are the same, and there is a winding area between the clock signal line and the GOA unit.
  • the communication line is bent and set in the winding area. In the winding area, the bending lengths of the plurality of communication lines near the clock signal line or at least one side near the GOA unit are the same.
  • the communication lines are designed to have the same bending length on at least one side close to the clock signal line or close to the GOA unit, so that the lateral capacitance of the communication lines on at least one side can be matched consistently.
  • the problem that the lateral capacitances generated by the communication lines in different rows and the surrounding wiring are different is solved.
  • the total length of the communication wires in different rows is consistent, and the problem of inconsistent resistance and capacitance of the communication wires in different rows is also solved.
  • the display panel provided by the embodiment of the present application can improve the problem of bright and dark lines on the panel by designing the bending manner of the communication line.

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Abstract

本申请实施例公开了一种阵列基板及显示面板。本申请实施例提供的阵列基板包括多个GOA单元、多条时钟信号线以及多条通信线。时钟信号线与GOA单元之间具有绕线区。通信线在绕线区弯折设置。通过这样的绕线设计，可以使通信线在同侧的侧向电容匹配一致。由此，解决了不同行的通信线与周围走线产生的侧向电容不同的问题。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及显示面板。
 背景技术
面板产品中，有效显示区（Active area, AA）的正常显示由扫描线（Gateline）和数据线（Dataline）共同控制，Gateline控制像素中薄膜晶体管（Thin Film Transistor, TFT）的开关状态，Dataline传递像素需要的电压信号。
在GOA产品中，Gateline信号由总线（Busline）传递给栅极驱动单元（GOA Circuit），再通过GOA Circuit输入至AA区Gateline走线。通常Busline内CK是由内向外依次排序的。以8个时钟信号为例，处于最***的CK8接入GOA单元需要跨过CK7~CK1，而CK1并不需要跨其他CK走线。因此，CK1~8之间的电阻和电容存在差异，进而导致相邻两行Gateline的GN波形存在差异。因为相邻CK走线电阻和电容的不同使得相邻两行Gateline输出的扫描信号波形存在差异，导致充电差异使得亮度存在明显差异，进而使得产品出现周期性水平密集线。
在对现有技术的研究和实践过程中，本申请的发明人发现，在实际产品设计中会通过绕线的方式进行电容和电阻的补偿匹配，但现有的绕线补偿方式容易增加原本不存在的侧向电容。
 技术问题
本申请实施例提供一种阵列基板及显示面板，可以改善走线之间侧向电容差异。
 技术解决方案
本申请实施例提供一种阵列基板，包括：
多个GOA单元；
多条时钟信号线，多条所述时钟信号线设置在所述GOA单元的一侧，并沿第一方向依次排布；
多条通信线，一所述通信线对应连接一所述时钟信号线与一所述GOA单元；
其中，所述时钟信号线与所述GOA单元之间具有绕线区，所述通信线包括依次相连的第一部分、绕线部分和第二部分，所述第一部分连接于所述时钟信号线，所述第二部分连接于所述GOA单元；所述绕线部分设置在所述绕线区；
所述绕线部分包括第一连接线、第二连接线以及弯折连接线，所述弯折连接线连接所述第一连接线和所述第二连接线之间；所述第一连接线与所述时钟信号线相对设置，第二连接线与所述GOA单元相对设置；
多条所述第一连接线分别与所述时钟信号线形成的侧向电容相等，和/或，多条所述第二连接线分别与所述GOA单元形成的侧向电容相等。
可选的，在本申请的一些实施例中，在与所述第一方向相交的第二方向上，多条所述第一连接线的长度相同，和/或，多条所述第二连接线的长度相同。
可选的，在本申请的一些实施例中，在所述第一方向上，多条所述第一连接线到所述时钟信号线的距离相等，和/或，多条所述第二连接线到所述GOA单元的距离相等。
可选的，在本申请的一些实施例中，多条所述通信线的长度相同。
可选的，在本申请的一些实施例中，所述第一连接线包括第一走线、第二走线以及第三走线，所述第一走线设置在远离所述弯折连接线的一侧，所述第二走线与所述第一走线间隔设置，所述第二走线与所述弯折连接线连接，所述第三走线连接在所述第一走线和所述第二走线之间，所述第一走线与所述第二走线的长度相同或不同。
可选的，在本申请的一些实施例中，所述第二连接线包括第一导线、第二导线以及第三导线，所述第一导线设置在远离所述弯折连接线的一侧，所述第二导线与所述第一导线平行设置且具有间隙，所述第二导线与所述弯折连接线连接，所述第三导线连接在所述第一导线和所述第二导线之间，所述第一导线与所述第二导线的长度相同或不同。
可选的，在本申请的一些实施例中，每一所述通信线包括一所述第一连接线、一所述第二连接线以及一所述弯折连接线。
可选的，在本申请的一些实施例中，每一所述通信线包括至少两条所述第一连接线、至少两条所述第二连接线以及一所述弯折连接线。
可选的，在本申请的一些实施例中，所述弯折连接线包括依次连接的多个弯折单元，所述弯折单元通过走线分别连接所述第一连接线和所述第二连接线。
可选的，在本申请的一些实施例中，所述弯折单元上还连接有至少一条并联走线，所述并联走线与所述弯折连接线并联设置。
可选的，在本申请的一些实施例中，每一所述时钟信号线连接多条所述通信线，包括至少一所述通信线的一组所述通信线沿所述时钟信号线的设置方向依次连接所述时钟信号线。
可选的，在本申请的一些实施例中，每组所述通信线中，在与所述第一方向相交的第二方向上，所述第一部分逐渐增大，所述弯折连接线的弯折长度逐渐减小。
可选的，在本申请的一些实施例中，每组所述通信线中，在与所述第一方向相交的第二方向上，所述第一部分逐渐增大，所述弯折连接线之间的弯折间距逐渐减小。
相应的，本申请实施例还提供一种显示面板，包括：
阵列基板，所述阵列基板
包括多个GOA单元、多条时钟信号线以及多条通信线，多条所述时钟信号线设置在所述GOA单元的一侧，并沿第一方向依次排布；一所述通信线对应连接一所述时钟信号线与一所述GOA单元；
其中，所述时钟信号线与所述GOA单元之间具有绕线区，所述通信线包括依次相连的第一部分、绕线部分和第二部分，所述第一部分连接于所述时钟信号线，所述第二部分连接于所述GOA单元；所述绕线部分设置在所述绕线区；
所述绕线部分包括第一连接线、第二连接线以及弯折连接线，所述弯折连接线连接所述第一连接线和所述第二连接线之间；所述第一连接线与所述时钟信号线相对设置，第二连接线与所述GOA单元相对设置；
多条所述第一连接线分别与所述时钟信号线形成的侧向电容相等，和/或，多条所述第二连接线分别与所述GOA单元形成的侧向电容相等；对向基板，所述对向基板与所述阵列基板相对设置，所述对向基板上对应所述通信线、所述时钟信号线设置有电极。
可选的，在本申请的一些实施例中，在与所述第一方向相交的第二方向上，多条所述第一连接线的长度相同，和/或，多条所述第二连接线的长度相同。
可选的，在本申请的一些实施例中，在所述第一方向上，多条所述第一连接线到所述时钟信号线的距离相等，和/或，多条所述第二连接线到所述GOA单元的距离相等。
可选的，在本申请的一些实施例中，所述第一连接线包括第一走线、第二走线以及第三走线，所述第一走线设置在远离所述弯折连接线的一侧，所述第二走线与所述第一走线间隔设置，所述第二走线与所述弯折连接线连接，所述第三走线连接在所述第一走线和所述第二走线之间，所述第一走线与所述第二走线的长度相同或不同。
可选的，在本申请的一些实施例中，所述第二连接线包括第一导线、第二导线以及第三导线，所述第一导线设置在远离所述弯折连接线的一侧，所述第二导线与所述第一导线平行设置且具有间隙，所述第二导线与所述弯折连接线连接，所述第三导线连接在所述第一导线和所述第二导线之间，所述第一导线与所述第二导线的长度相同或不同。
可选的，在本申请的一些实施例中，所述弯折连接线包括依次连接的多个弯折单元，所述弯折单元通过走线分别连接所述第一连接线和所述第二连接线。
可选的，在本申请的一些实施例中，所述弯折单元上还连接有至少一条并联走线，所述并联走线与所述弯折连接线并联设置。
 有益效果
本申请实施例公开了一种阵列基板及显示面板。本申请实施例提供的阵列基板包括多个GOA单元、多条时钟信号线以及多条通信线。其中，多条通信线的长度相同，时钟信号线与GOA单元之间具有绕线区。通信线在绕线区弯折设置。在绕线区内，多条通信线在靠近时钟信号线或在靠近GOA单元至少一侧的侧向电容相同。通过这样的绕线设计，可以使通信线在同侧的侧向电容匹配一致。由此，解决了不同行的通信线与周围走线产生的侧向电容不同的问题。另外，由于在绕线区中对通信线进行了绕线设计，使不同行的通信线的总长度一致，也解决了不同行的通信线电阻和电容不一致的问题，从而可以改善面板明暗线的问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的第一种结构示意图；
图2是本申请实施例提供的阵列基板中通信线的第一种结构示意图；
图3是本申请实施例提供的阵列基板中通信线的第二种结构示意图；
图4是本申请实施例提供的阵列基板中通信线的第三种结构示意图；
图5是本申请实施例提供的阵列基板的第二种结构示意图；
图6是本申请实施例提供的阵列基板中通信线的第四种结构示意图；
图7是本申请实施例提供的阵列基板中通信线的第五种结构示意图；
图8是本申请实施例提供的阵列基板中通信线的第六种结构示意图；
图9是本申请实施例提供的阵列基板的第三种结构示意图；
图10是本申请实施例提供的阵列基板的第四种结构示意图；
图11是本申请实施例提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种阵列基板及显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请实施例提供一种阵列基板。请参阅图1和图2。图1是本申请实施例提供的阵列基板的第一种结构示意图。图2是本申请实施例提供的阵列基板中通信线的第一种结构示意图。阵列基板10包括多个GOA单元101、多条时钟信号线102以及多条通信线103。多条时钟信号线102设置在GOA单元101的一侧，并沿第一方向x依次排布。需要说明的是，第一方向x为沿图中x轴延伸的方向，在本申请实施例中，以第一方向x进行表述。一通信线103对应连接一时钟信号线102与一GOA单元101。其中，时钟信号线102与GOA单元101之间具有绕线区10a。通信线103包括依次相连的第一部分103A、绕线部分103B和第二部分103C。第一部分103A连接于时钟信号线102。第二部分103C连接于GOA单元101。绕线部分103B设置在绕线区10a。
绕线部分103B包括第一连接线1031、第二连接线1032以及弯折连接线1033。弯折连接线1033连接第一连接线1031和第二连接线1032之间。第一连接线1031与时钟信号线102相对设置。第二连接线1032与GOA单元101对设置。多条第一连接线1031分别与时钟信号线102形成的侧向电容相等，和/或，多条第二连接线1032分别与GOA单元101形成的侧向电容相等。
具体的，图1以8个时钟信号的阵列基板10为例进行说明，本申请实施例提供的阵列基板10对时钟信号的数量不做限制，例如，还可以应用于12个时钟信号的阵列基板10，或者应用于16个时钟信号的阵列基板10。8CK的阵列基板的时钟信号线102包括CK1、CK2、CK3、CK4、CK5、CK6、CK7和CK8。其中，CK1至CK8的通信线103的电阻和电容相同，是通过通信线103在绕线区10a的绕线补偿实现的。由于CK8连接GOA单元101需要跨过CK1至CK7的走线，而CK1不需要跨过其他时钟信号线102。因此，若不进行绕线补偿，CK1的走线最短，而CK8的走线最长。这会导致CK1至CK8各时钟信号线102的电容和电阻均产生差异。但是，若进行绕线设计，通信线103产生了第二方向y上的长度，从而增加了通信线103与周围走线在第二方向y上的正对面积。因此，容易在绕线区10a与GOA单元101或时钟信号线102产生侧向电容。其中，第二方向y为沿图中y轴延伸的方向，在本申请实施例中表述为第二方向y。本申请实施例附图中以第一方向x和第二方向y相互垂直为示例，但不作为对第一方向x和第二方向y的限制。第一方向x与第二方向y相交。
侧向电容是指通信线103与GOA单元101中的走线或时钟信号线102正对区域产生的电容。通常，CK1的绕线区域较大，CK8的绕线区域较小，则CK1至CK8与GOA单元101和时钟信号线102之间产生的侧向电容是不同的。侧向电容的区别也会导致输出的扫描信号波形差异，进而使面板显示发生明暗线的问题。
其中，通信线103与时钟信号线102不同层设置。通信线103中的第一连接线1031、第二连接线1032与时钟信号线102相对设置是指不同层的相对设置。
本申请实施例提供一种阵列基板10。阵列基板10包括多个GOA单元101、多条时钟信号线102以及多条通信线103。时钟信号线102与GOA单元101之间具有绕线区10a。通信线103在绕线区10a弯折设置。通信线103包括至少一第一连接线1031、至少一第二连接线1032以及弯折连接线1033。第一连接线1031设置在绕线区10a靠近时钟信号线102的一侧，且与时钟信号线102相对设置。第二连接线1032设置在绕线区10a靠近GOA单元101的一侧，且与GOA单元101相对设置。弯折连接线1033连接第一连接线1031和第二连接线1032。其中，多条第一连接线1031分别与时钟信号线102形成的侧向电容相等，和/或，多条第二连接线1032分别与GOA单元101形成的侧向电容相等。
其中，通信线103是指总线，也可称通信干线（Busline）。Busline是各种功能部件之间传送信息的公共通信干线，它是由导线组成的传输线束。在GOA显示产品中，时钟信号线102出的时钟信号是由通信线103传递给GOA单元101，再通过GOA单元101输出扫描信号至面板有效显示区的扫描线。
其中，本申请实施例中所述的多条第一连接线1031分别与时钟信号线102形成的侧向电容相等，和/或，多条第二连接线1032分别与GOA单元101形成的侧向电容相等。侧向电容的主要受到相邻两个走线的相对面积以及间距的影响。可选的，在与第一方向x相交的第二方向y上，多条第一连接线1031的长度相同，和/或，多条第二连接线1032的长度相同。
在金属层膜厚不变的情况下，侧向电容同相邻走线的正对长度成完全正相关。故保证同侧的通信线103的长度相同，其侧向电容也相同。因此，通过在绕线区10a中，设计为靠近时钟信号线102一侧的通信线103弯折长度相同，或靠近GOA单元101一侧的通信线103弯折长度相同，可以使通信线103在至少一侧的侧向电容匹配一致。由此，解决了不同行的通信线103与周围走线产生的侧向电容不同的问题。
如图2中所示，图2示出了图1中局部放大的第一行和第二行通信线103示意图。图2中的第一行第一连接线1031的弯折长度为D1，第二行第一连接线1031的弯折长度为D2，D1和D2的长度相同。此时，第一行第二连接线1032和第二行第二连接线1032的弯折长度可以不同。或者，请继续参阅图2，图2中的第一行第二连接线1032的弯折长度为Da，第二行第二连接线1032的弯折长度为Db，Da和Db的长度相同。此时第一行第一连接线1031和第二行第一连接线1031的弯折长度可以不同。
可选的，请继续参阅图2，在绕线区10a内，多条第一连接线1031的弯折长度相同，且多条第二连接线1032相同。即，D1和D2的长度相同，Da和Db的长度相同。
可选的，在一些实施例中，在绕线区10a内，多条第一连接线1031的弯折长度与多条第二连接线1032的弯折长度均相同。也就是说，可以是D1、D2、Da和Db的长度均相同。
在图2所示的实施例中，是以D1、D2、Da和Db的长度均相同作为示例，但不作为对本申请的限制。本申请实施例只需要保证同侧的弯折长度相同，则可以改善侧向电容对扫描信号脉冲高度的影响。
可选的，在第一方向x上，多条第一连接线1031到时钟信号线102的距离G1相等，和/或，多条第二连接线1032到GOA单元101的距离G2相等。
可选的，多条通信线103的长度相同。由于在绕线区10a中对通信线103进行了绕线设计，使不同行的通信线103的总长度一致，也解决了不同行的通信线103电阻和电容不一致的问题。本申请实施例提供的阵列基板10，通过对通信线103的弯折方式进行设计，可以改善面板明暗线的问题。
可选的，请参阅图3，图3是本申请实施例提供的阵列基板中通信线的第二种结构示意图。第一连接线1031包括第一走线103a、第二走线103b以及第三走线103c，第一走线103a设置在远离弯折连接线1033的一侧。第二走线103b与第一走线103a平行设置且具有间隙。第二走线103b与弯折连接线1033连接。第三走线103c连接第一走线103a和第二走线103b。可选的，第一走线103a与第二走线103b的长度相同或不同。图1和图3中示出了第一走线103a与第二走线103b的长度相同的结构。
可选的，请参阅图4，图4是本申请实施例提供的阵列基板中通信线的第三种结构示意图。可选的，第二连接线1032包括第一导线103d、第二导线103e以及第三导线103f。第一导线103d设置在远离弯折连接线1033的一侧。第二导线103e与第一导线103d平行设置且具有间隙。第二导线103e与弯折连接线1033连接。第三导线103f连接第一导线103d和第二导线103e。可选的，第一导线103d与第二导线103e的长度相同或不同。图1和图3中示出了第一导线103d与第二导线103e的长度相同的结构。
请同时参阅图4和图5，图5是本申请实施例提供的阵列基板的第二种结构示意图。图5所示的实施例与图1所示的实施例的区别在于，图5中第一走线103a与第二走线103b的长度不同。
可选的，每一时钟信号线102连接多条通信线103。包括至少一通信线103的一组通信线103沿时钟信号线102的设置方向依次连接时钟信号线102。即，通信线103是以周期性排列依次连接时钟信号线102。请参阅图1和图6，图1中示意了其中一个周期的通信线103的一种排列方式。在下一个周期中，通信线103重复图1中所示的连接顺序与时钟信号线102连接。可以理解的是，在不同情况下，可以根据GOA单元101需要连接的时钟信号线102来选择通信线103连接的顺序。当然，当通信线103连接的顺序发生变化之后，通信线103的弯折方式也需要相应做出变化，以保证连接不同时钟信号线102的通信线103总长度一致。
可选的，请参阅图1和图6。图6是本申请实施例提供的阵列基板中通信线的第四种结构示意图。每组通信线103中，在与第一方向x相交的第二方向y上，第一部分103A逐渐增大，弯折连接线1033的弯折长度逐渐减小。图4中仍以8CK为例进行说明，其中，对应连接CK1、CK2、CK3、CK4、CK5、CK6、CK7和CK8的弯折连接线1033的弯折长度分别为d1、d2、d3、d4、d5、d6、d7和d8。由于每组通信线103是沿时钟信号线102的设置方向由CK8至CK1依次连接时钟信号线102，则弯折长度的大小为d8＜d7＜d6＜d5＜d4＜d3＜d2＜d1。其中，d8可以为0，也就是说CK8的弯折连接线1033可以不弯折，直接连接CK8的第一连接线1031和第二连接线1032。
可选的，请参阅图1和图7，图7是本申请实施例提供的阵列基板中通信线的第五种结构示意图。每组通信线103中，在与第一方向x相交的第二方向y上，第一部分103A逐渐增大，弯折连接线1033之间的弯折间距逐渐减小。图7中仍以8CK为例进行说明，其中，由于对应连接CK1、CK2、CK3、CK4、CK5、CK6、CK7和CK8的通信线103需要绕线的长度是依次减小的，因此，连接CK1的弯折连接线1033的弯折间距是最小的，连接CK8的弯折连接线1033的弯折间距是最大的。
以上实施例均是以通信线103依次连接CK8至CK1的时钟信号线102顺序为例进行说明。当需要改变连接时钟信号线102顺序时，通信线103的弯折面积、弯折长度或弯折密度均应对应改变。另外，以上实施例是弯折面积、弯折长度和弯折密度中的任一种增大或减小。也可以是弯折面积、弯折长度和弯折密度中的任意两种或三种均进行设计。上述实施例是以这几种绕线方式作为示例进行说明，实际上还可以有其他的绕线方式，只需保证各行通信线的总长度一致即可。
可选的，请参阅图1和图8，图8是本申请实施例提供的阵列基板中通信线的第六种结构示意图。由于电阻大小与走线面积成反比，在保证通信线103长度一致的情况下，为匹配不同行之间通信线103的电阻，还可以将长度较长的通信线103的宽度适当增大，以减小通信线103的电阻。同样，可以将长度较短的通信线103的宽度适当减小，以增大通信线103的电阻。由此，减小不同行通信线103之间的电阻不均的问题。例如，在一时钟信号线102连接多条通信线103，包括至少一通信线103的一组通信线103沿时钟信号线102的设置方向依次连接时钟信号线102。此时，连接CK1的通信线103线宽最小，连接CK8的通信线103线宽最大，以匹配不同行通信线103的电阻。
可选的，请参阅图9，图9是本申请实施例提供的阵列基板的第三种结构示意图。弯折连接线1033包括依次连接的多个弯折单元1033a。弯折单元1033a通过走线分别连接第一连接线1031和第二连接线1032。弯折单元1033a上还连接有至少一条并联走线104。并联走线104与弯折连接线1033并联设置。可以理解的是，本申请实施例提供的阵列基板10中，弯折连接线1033的弯折方式可以是之字形、蛇形、脉冲形、凹凸折线形、波浪形或锯齿形。例如，弯折单元1033a内弯折连接线1033具有沿第一方向延伸两根走线，并且这两根走线通过沿第二方向延伸的走线连接。这几种弯折形态能够在较小的空间内弯折更长的通信线103，节约通信线103的排布空间，有利于面板的窄边框化。图9中以弯折连接线1033弯折为脉冲形为示意。
可选的，在一些实施例中，多条第一连接线1031的弯折长度与多条第二连接线1032的弯折长度均相同，且第一连接线1031的长度大于弯折单元1033a的长度。第一连接线1031的长度大于弯折单元1033a的长度，则可以使第一连接线1031与弯折单元1033a内的弯折连接线1033的排布错开，降低第一连接线1031与弯折连接线1033的短接风险。
可选的，弯折连接线1033上连接有一条并联走线104。并联走线104与弯折连接线1033并联设置。因为不同行的通信线103在绕线区10a的弯折设计不同，在制程中，可能会产生刻蚀不均匀。所以可以通过中间连接并联走线104的方式改善刻蚀均匀性。并联走线104的设计相当于在弯折连接线1033中并联一根电阻。通过调整并联走线104的连接位置保证通信线103的阻值不变，还增加了通信线103的绕线长度，从而对刻蚀均匀性有一定的改善。另外，增加并联走线104还可以提高弯折连接线1033的连接稳定性。为防止增大显示面板非显示区边框的宽度，绕线区10a的宽度不能过大，则在绕线区10a对弯折连接线1033进行弯折设计的区域较小，相邻的弯折连接线1033距离较窄，则刻蚀时容易发生断路的问题。在弯折连接线1033中连接至少一根并联走线104，能够避免其中一段通信线103发生断路后信号无法传输的问题。
需要说明的是，在保证通信线103长度不变的情况下，可以在布线更密集的区域增加并联走线104的数量。例如，CK8的通信线103的弯折连接线1033的长度较短，在绕线区10a中的弯折密度较小，则可以减少并联走线104的数量。CK1的通信线103的弯折连接线1033的长度较长，在绕线区10a中的弯折密度较大，则可以增大并联走线104的数量。
可选的，可根据侧向距离考虑通信线103的弯折列数。侧向距离没有固定标准和范围，这个需要根据分辨率、时钟信号线102的数量等因素进行综合考虑。因为高分辨率面板中，GOA的时钟信号间的微小差异对像素显示影响较大，而时钟信号线102的数量越多，侧向电容的差值会更大。则时钟信号线102较多时，时钟信号线102之间的距离需要缩小，即通信线103的弯折长度更高，那么侧向正对面积会变大，这时候需要将绕线区10a的宽度缩小，即减少通信线103的弯折列数。因此，可选的，时钟信号线102数量与通信线103的弯折列数成反比。
可选的，每一通信线103包括一第一连接线1031、一第二连接线1032以及一弯折连接线1033。在一些实施例中，每一通信线103包括相邻设置的两条第一连接线1031、相邻设置的两条第二连接线1032以及一弯折连接线1033。具体的，请参阅图10，图10是本申请实施例提供的阵列基板的第四种结构示意图。在图10所示的实施例中，在绕线区10a，第一连接线1031或第二连接线1032的弯折长度相同。也就是说，在本申请实施例中，对用于匹配侧向电容的通信线103弯折列数、弯折长度、弯折面积以及弯折密度均不做限制。同侧的通信线103弯折长度相同，可用于改善侧向电容不均的问题。
相应的，本申请实施例还提供一种显示面板。请参阅图11，图11是本申请实施例提供的显示面板的一种结构示意图。显示面板100包括阵列基板10和对向基板20。阵列基板10为以上所述的阵列基板10。阵列基板包括基板105、时钟信号线102和通信线103。对向基板20与阵列基板10相对设置。对向基板20包括基板105，并且对向基板20上对应通信线103、时钟信号线102设置有电极106。
本申请实施例提供的显示面板100中，阵列基板10上设置有通信线103。通信线103在绕线区的同侧弯折长度相同，则均衡了不同行的通信线103的侧向电容。又由于通信线103在靠近绕线区中轴处的弯折设计，可以对不同行的通信线103与电极106之间的电容进行平衡，从而也对通信线103与电极106之间的电容进行了补偿。
需要说明的是，阵列基板10和对向基板20还可以包括其他装置，其他装置及其装配为本领域技术人员所熟知的技术，在此不再赘述。
本申请实施例提供一种显示面板，显示面板包括阵列基板和对向基板。本申请实施例提供的显示面板中的阵列基板对设置在阵列基板上的通信线进行了绕线设计。其中，多条通信线的长度相同，时钟信号线与GOA单元之间具有绕线区。通信线在绕线区弯折设置。在绕线区内，多条通信线在靠近时钟信号线或在靠近GOA单元至少一侧的弯折长度相同。通过在绕线区中，将通信线设计为靠近时钟信号线或在靠近GOA单元至少一侧的弯折长度相同，可以使通信线在至少一侧的侧向电容匹配一致。由此，解决了不同行的通信线与周围走线产生的侧向电容不同的问题。另外，由于在绕线区中对通信线进行了绕线设计，使不同行的通信线的总长度一致，也解决了不同行的通信线电阻和电容不一致的问题。本申请实施例提供的显示面板，通过对通信线的弯折方式进行设计，可以改善面板明暗线的问题。
以上对本申请实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    多个GOA单元；
    多条时钟信号线，多条所述时钟信号线设置在所述GOA单元的一侧，并沿第一方向依次排布；
    多条通信线，一所述通信线对应连接一所述时钟信号线与一所述GOA单元；
    其中，所述时钟信号线与所述GOA单元之间具有绕线区，所述通信线包括依次相连的第一部分、绕线部分和第二部分，所述第一部分连接于所述时钟信号线，所述第二部分连接于所述GOA单元；所述绕线部分设置在所述绕线区；
    所述绕线部分包括第一连接线、第二连接线以及弯折连接线，所述弯折连接线连接所述第一连接线和所述第二连接线之间；所述第一连接线与所述时钟信号线相对设置，第二连接线与所述GOA单元相对设置；
    多条所述第一连接线分别与所述时钟信号线形成的侧向电容相等，和/或，多条所述第二连接线分别与所述GOA单元形成的侧向电容相等。
  2. 根据权利要求1所述的阵列基板，其中，在与所述第一方向相交的第二方向上，多条所述第一连接线的长度相同，和/或，多条所述第二连接线的长度相同。
  3. 根据权利要求1所述的阵列基板，其中，在所述第一方向上，多条所述第一连接线到所述时钟信号线的距离相等，和/或，多条所述第二连接线到所述GOA单元的距离相等。
  4. 根据权利要求1所述的阵列基板，其中，多条所述通信线的长度相同。
  5. 根据权利要求1所述的阵列基板，其中，所述第一连接线包括第一走线、第二走线以及第三走线，所述第一走线设置在远离所述弯折连接线的一侧，所述第二走线与所述第一走线间隔设置，所述第二走线与所述弯折连接线连接，所述第三走线连接在所述第一走线和所述第二走线之间，所述第一走线与所述第二走线的长度相同或不同。
  6. 根据权利要求1所述的阵列基板，其中，所述第二连接线包括第一导线、第二导线以及第三导线，所述第一导线设置在远离所述弯折连接线的一侧，所述第二导线与所述第一导线平行设置且具有间隙，所述第二导线与所述弯折连接线连接，所述第三导线连接在所述第一导线和所述第二导线之间，所述第一导线与所述第二导线的长度相同或不同。
  7. 根据权利要求1所述的阵列基板，其中，每一所述通信线包括一所述第一连接线、一所述第二连接线以及一所述弯折连接线。
  8. 根据权利要求1所述的阵列基板，其中，每一所述通信线包括至少两条所述第一连接线、至少两条所述第二连接线以及一所述弯折连接线。
  9. 根据权利要求1所述的阵列基板，其中，所述弯折连接线包括依次连接的多个弯折单元，所述弯折单元通过走线分别连接所述第一连接线和所述第二连接线。
  10. 根据权利要求9所述的阵列基板，其中，所述弯折单元上还连接有至少一条并联走线，所述并联走线与所述弯折连接线并联设置。
  11. 根据权利要求1所述的阵列基板，其中，每一所述时钟信号线连接多条所述通信线，包括至少一所述通信线的一组所述通信线沿所述时钟信号线的设置方向依次连接所述时钟信号线。
  12. 根据权利要求11所述的阵列基板，其中，每组所述通信线中，在与所述第一方向相交的第二方向上，所述第一部分逐渐增大，所述弯折连接线的弯折长度逐渐减小。
  13. 根据权利要求11所述的阵列基板，其中，每组所述通信线中，在于所述第一方向相交的第二方向上，所述第一部分逐渐增大，所述弯折连接线之间的弯折间距逐渐减小。
  14. 一种显示面板，其包括：
    阵列基板，所述阵列基板包括多个GOA单元、多条时钟信号线以及多条通信线，多条所述时钟信号线设置在所述GOA单元的一侧，并沿第一方向依次排布；一所述通信线对应连接一所述时钟信号线与一所述GOA单元；
    其中，所述时钟信号线与所述GOA单元之间具有绕线区，所述通信线包括依次相连的第一部分、绕线部分和第二部分，所述第一部分连接于所述时钟信号线，所述第二部分连接于所述GOA单元；所述绕线部分设置在所述绕线区；
    所述绕线部分包括第一连接线、第二连接线以及弯折连接线，所述弯折连接线连接所述第一连接线和所述第二连接线之间；所述第一连接线与所述时钟信号线相对设置，第二连接线与所述GOA单元相对设置；
    多条所述第一连接线分别与所述时钟信号线形成的侧向电容相等，和/或，多条所述第二连接线分别与所述GOA单元形成的侧向电容相等；
    对向基板，所述对向基板与所述阵列基板相对设置，所述对向基板上对应所述通信线、所述时钟信号线设置有电极。
  15. 根据权利要求14所述的显示面板，其中，在与所述第一方向相交的第二方向上，多条所述第一连接线的长度相同，和/或，多条所述第二连接线的长度相同。
  16. 根据权利要求14所述的显示面板，其中，在所述第一方向上，多条所述第一连接线到所述时钟信号线的距离相等，和/或，多条所述第二连接线到所述GOA单元的距离相等。
  17. 根据权利要求14所述的显示面板，其中，所述第一连接线包括第一走线、第二走线以及第三走线，所述第一走线设置在远离所述弯折连接线的一侧，所述第二走线与所述第一走线间隔设置，所述第二走线与所述弯折连接线连接，所述第三走线连接在所述第一走线和所述第二走线之间，所述第一走线与所述第二走线的长度相同或不同。
  18. 根据权利要求14所述的显示面板，其中，所述第二连接线包括第一导线、第二导线以及第三导线，所述第一导线设置在远离所述弯折连接线的一侧，所述第二导线与所述第一导线平行设置且具有间隙，所述第二导线与所述弯折连接线连接，所述第三导线连接在所述第一导线和所述第二导线之间，所述第一导线与所述第二导线的长度相同或不同。
  19. 根据权利要求14所述的显示面板，其中，所述弯折连接线包括依次连接的多个弯折单元，所述弯折单元通过走线分别连接所述第一连接线和所述第二连接线。
  20. 根据权利要求19所述的显示面板，其中，所述弯折单元上还连接有至少一条并联走线，所述并联走线与所述弯折连接线并联设置。
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