WO2023044909A1 - 光电检测电路及其控制方法和像素单元 - Google Patents

光电检测电路及其控制方法和像素单元 Download PDF

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Publication number
WO2023044909A1
WO2023044909A1 PCT/CN2021/120986 CN2021120986W WO2023044909A1 WO 2023044909 A1 WO2023044909 A1 WO 2023044909A1 CN 2021120986 W CN2021120986 W CN 2021120986W WO 2023044909 A1 WO2023044909 A1 WO 2023044909A1
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Prior art keywords
transistor
subcircuit
terminal
detection
circuit
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PCT/CN2021/120986
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English (en)
French (fr)
Inventor
赵方圆
王佳斌
佟月
王雷
李扬冰
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京东方科技集团股份有限公司
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Priority to PCT/CN2021/120986 priority Critical patent/WO2023044909A1/zh
Priority to US17/795,785 priority patent/US20240184405A1/en
Priority to CN202180002712.5A priority patent/CN116210033A/zh
Publication of WO2023044909A1 publication Critical patent/WO2023044909A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the present disclosure relates to the technical field of photoelectric detection, and in particular to a photoelectric detection circuit, a control method thereof, and a pixel unit.
  • photosensitive devices can be arranged in an array to collect the intensity changes of reflected light or transmitted light caused by finger textures, and photoelectric conversion can be performed using photosensitive devices. According to the electrical signal converted from the light intensity, fingerprint image collection can be realized, so as to perform optical fingerprint identification.
  • the detection effect of most detection circuits is not ideal at present.
  • An embodiment of the present disclosure provides a photoelectric detection circuit, the photoelectric detection circuit includes:
  • the detection subcircuit is connected to the detection voltage signal terminal, the bias voltage signal terminal and the input node, and is configured to respond to an optical signal to generate a flow between the bias voltage signal terminal and the input node under the control of the potential of the detection voltage signal terminal. current;
  • a storage subcircuit connected between the bias voltage signal terminal and the input node, and configured to store energy based on the current generated by the detection subcircuit
  • an integrator subcircuit having a first input, a second input and an output and configured to integrate the signal at the first input based on the potential at the second input to generate an integrated signal and output it at the output;
  • the control subcircuit is connected to the control signal terminal, the input node and the first input terminal of the integration circuit, and is configured to provide the potential of the input node to the first input terminal of the integration circuit under the control of the control signal terminal.
  • the storage sub-circuit includes a first capacitor, a first electrode of the first capacitor is connected to the bias voltage signal terminal, and a second electrode of the first capacitor is connected to the input node.
  • the photoelectric detection circuit further includes: a reset auxiliary subcircuit, the detection subcircuit is connected to the bias voltage signal terminal through the reset auxiliary subcircuit, and the reset auxiliary subcircuit is configured to Under the control of the signal terminal, the detection subcircuit is electrically connected to the bias voltage signal terminal during the detection period, and the detection subcircuit is electrically isolated from the bias voltage signal terminal during the reset period.
  • the reset auxiliary subcircuit includes a first transistor, the gate of the first transistor is connected to the reset auxiliary signal terminal, the first pole of the first transistor is connected to the bias voltage signal terminal, and the first transistor is connected to the bias voltage signal terminal.
  • the second pole of a transistor is connected with the detection sub-circuit.
  • the photodetection circuit further includes: a reset subcircuit connected to the reset signal terminal, the input node and the reset voltage terminal, and configured to provide the potential of the reset voltage terminal to the The input node, wherein the potential of the reset voltage terminal is equal to the potential of the second input terminal of the integral sub-circuit.
  • the reset sub-circuit includes a second transistor, the gate of the second transistor is connected to the reset signal terminal, the first pole of the second transistor is connected to the reset voltage terminal, and the first pole of the second transistor is connected to the reset voltage terminal.
  • a diode is connected to the input node.
  • the photodetection circuit further includes an amplifying subcircuit connected between the input node and the control subcircuit and connected to a reference voltage terminal, the amplifying subcircuit is configured to be at the potential of the input node A current flowing between the reference signal terminal and the control sub-circuit is generated under control.
  • the amplifying sub-circuit includes a third transistor, the gate of the third transistor is connected to the input node, the first electrode of the third transistor is connected to the reference voltage terminal, and the second electrode of the third transistor Pole connected to the control sub-circuit.
  • the detection sub-circuit includes a fourth transistor, the gate of the fourth transistor is connected to the detection voltage signal terminal, the first pole of the fourth transistor is connected to the bias voltage signal terminal, and the fourth transistor The second pole of the transistor is connected to the input node.
  • the photoelectric detection circuit includes a plurality of detection sub-circuits.
  • control sub-circuit includes a fifth transistor, the gate of the fifth transistor is connected to the control signal terminal, the first pole of the fifth transistor is connected to the input node, and the second pole of the fifth transistor is connected to the input node.
  • the pole is connected to the first input terminal of the integration circuit.
  • the integral subcircuit includes:
  • an operational amplifier the first input terminal of the operational amplifier is connected to the first input terminal of the integral subcircuit, the second input terminal of the operational amplifier is connected to the second input terminal of the integral subcircuit, and the operational The output end of the amplifier is connected as the output end of the integral sub-circuit;
  • a second capacitor the first electrode of the second capacitor is connected to the first input end of the operational amplifier, and the second electrode of the second capacitor is connected to the second input end of the operational amplifier.
  • the detection sub-circuit includes a fourth transistor
  • the control sub-circuit includes a fifth transistor
  • the fourth transistor and the fifth transistor are arranged on the base substrate, the first pole of the fourth transistor and the The second pole is set on the same layer as the first pole and the second pole of the fifth transistor
  • the active layer of the fourth transistor is set on the same layer as the active layer of the fifth transistor
  • the active layer of the fourth transistor is set on the same layer.
  • the gate is arranged on the side where the active layer of the fourth transistor faces the substrate
  • the gate of the fifth transistor is arranged on a side where the active layer of the fifth transistor is away from the substrate. side.
  • the fourth transistor and the fifth transistor are provided with a flat layer on the side away from the base substrate, and the first electrode of the first capacitor is located on the side of the flat layer away from the base substrate, so The second electrode of the first capacitor is located on a side of the flat layer facing the base substrate.
  • An embodiment of the present disclosure also provides a pixel unit, including:
  • each pixel circuit configured to emit light based on the pixel circuit being configured based on the data voltage
  • the pixel circuit includes a drive transistor, the drive transistor includes an active layer on the base substrate, a gate located on the side of the active layer away from the base substrate, and a gate located between the active layer and the base substrate.
  • the first gate insulating layer between the gates, the second gate insulating layer on the side of the gate away from the base substrate, the second gate insulating layer on the side away from the base substrate an interlayer dielectric layer, and a source electrode and a drain electrode located on a side of the interlayer dielectric layer away from the base substrate;
  • the detection subcircuit of the photodetection circuit includes a fourth transistor, and the control subcircuit of the photodetection circuit includes a fifth transistor, wherein the gate of the fourth transistor is located between the first gate insulating layer and the substrate Between the substrates, the first pole and the second pole of the fourth transistor are arranged on the same layer as at least one of the source and drain of the driving transistor, and the active layer of the fourth transistor is connected to the driving transistor
  • the active layer of the fifth transistor is arranged on the same layer, the gate of the fifth transistor is arranged on the same layer as the gate of the driving transistor, the first pole and the second pole of the fifth transistor are connected to the source and the source of the driving transistor At least one of the drains is arranged in the same layer, and the active layer of the fifth transistor is arranged in the same layer as the active layer of the driving transistor.
  • the pixel circuit further includes a light-emitting unit, the light-emitting unit includes an anode, a cathode, and a light-emitting layer between the anode and the cathode, wherein the side of the interlayer dielectric layer away from the base substrate is provided with a flat layer, the anode is located on a side of the flat layer away from the base substrate and is connected to the source or drain of the drive transistor through the flat layer;
  • the storage sub-circuit of the photodetection circuit includes a first capacitor, the first electrode of the first capacitor is set on the same layer as the anode, and the second electrode of the first capacitor is located on the flat layer facing the substrate side of the substrate.
  • a first passivation layer and a second passivation layer between the first passivation layer and the planar layer are further provided between the planar layer and the interlayer dielectric layer, wherein the The source and drain of the driving transistor are located between the first passivation layer and the interlayer dielectric layer, and the second electrode of the first capacitor is located between the second passivation layer and the first passivation layer. between layers.
  • An embodiment of the present disclosure also provides a method for controlling the photoelectric detection circuit as described above, including:
  • the detection subcircuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal
  • the storage subcircuit performs energy storage based on the current generated by the detection subcircuit
  • the control subcircuit provides the potential of the input node to the first input terminal of the integration circuit under the control of the control signal terminal;
  • the integrating sub-circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.
  • the photoelectric detection circuit also includes a reset auxiliary subcircuit, and the method includes:
  • the reset auxiliary subcircuit electrically connects the detection subcircuit to the bias voltage signal terminal under the control of the reset auxiliary signal terminal, and the detection subcircuit generates a bias voltage signal in response to an optical signal
  • the current flowing between the terminal and the input node, the storage subcircuit performs energy storage based on the current generated by the detection subcircuit, and the control subcircuit provides the potential of the input node to the integration circuit under the control of the control signal terminal
  • the first input terminal, the integration subcircuit integrates the signal at the first input terminal based on the potential of the second input terminal to generate an integrated signal and output it at the output terminal;
  • the reset auxiliary subcircuit electrically isolates the detection subcircuit from the bias voltage signal terminal under the control of the reset auxiliary signal terminal, and the detection subcircuit electrically isolates the bias voltage signal terminal under the control of the potential of the detection voltage signal terminal.
  • the voltage signal terminal is electrically connected to the input node, and the control subcircuit electrically connects the input node to the first input terminal of the integration circuit under the control of the control signal terminal.
  • the photoelectric detection circuit also includes a reset subcircuit, and the method includes:
  • the reset subcircuit electrically isolates the reset voltage terminal from the input node under the control of the reset signal terminal, and the detection subcircuit responds to an optical signal to generate a bias voltage between the signal terminal and the input node.
  • the current flowing between, the storage subcircuit performs energy storage based on the current generated by the detection subcircuit
  • the control subcircuit provides the potential of the input node to the first input terminal of the integration circuit under the control of the control signal terminal
  • the integration sub-circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal;
  • the reset subcircuit electrically connects the reset voltage terminal to the input node under the control of the reset signal terminal, and the control subcircuit connects the input node to the first input node of the integration circuit under the control of the control signal terminal.
  • One input is galvanically isolated.
  • the photoelectric detection circuit also includes an amplification sub-circuit, and the method includes:
  • the detection subcircuit During the detection period, the detection subcircuit generates a current flowing between the bias voltage signal terminal and the input node in response to the light signal under the control of the potential of the detection voltage signal terminal, and the storage subcircuit performs energy based on the current generated by the detection subcircuit.
  • the storage and amplifying subcircuits generate a current flowing between the reference signal terminal and the control subcircuit under the control of the potential of the input node, and the control subcircuit will amplify the current generated by the subcircuit under the control of the control signal terminal
  • the integration sub-circuit integrates the signal at the first input terminal based on the potential of the second input terminal to generate an integrated signal and output it at the output terminal;
  • the detection subcircuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal, wherein the potential of the bias voltage signal terminal in the reset period is different from the potential in the detection phase .
  • FIG. 1 is a schematic block diagram of a photoelectric detection circuit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a photoelectric detection circuit according to an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view of a photoelectric detection circuit according to an embodiment of the present disclosure.
  • FIG. 8A is a top view of a photodetection circuit according to an embodiment of the present disclosure.
  • FIG. 8B is a top view of a photodetection circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 12 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view of a pixel unit according to an embodiment of the present disclosure.
  • FIG. 14 is an operation timing diagram of a photoelectric detection circuit according to an embodiment of the present disclosure.
  • 15 is an operation timing diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • 16 is an operation timing diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • 17 is an operation timing diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • connection may refer to two components being directly connected, or may refer to two components being connected via one or more other components. Furthermore, these two components can be connected or coupled by wire or wirelessly.
  • Terminal devices such as smart phones, laptop computers, etc.
  • Terminal devices can provide users with a fingerprint identification function to identify the user.
  • photosensitive devices can be arrayed to collect reflected or transmitted optical signals under different finger regions. The photosensitive device is then used for photoelectric conversion to obtain the electrical signal converted from the optical signal. Finally, use an analog-to-digital converter (Analog-to-Digital Converter, ADC) to convert the electrical signal into a digital signal to complete fingerprint image acquisition.
  • ADC Analog-to-Digital Converter
  • PIN-type photosensitive diodes When making in-screen (under-screen) fingerprint recognition components, PIN-type photosensitive diodes are mostly used. PIN-type photodiodes have a similar structure to semiconductor diodes. The die of the PIN photodiode is a PN junction (PN Junction) with photosensitive characteristics and has unidirectional conductivity. Therefore, in the working state, it can provide the reverse voltage for the PIN type photosensitive diode. When there is no light, there is a small saturated reverse leakage current, that is, dark current, and the photodiode is cut off at this time. When illuminated, the saturated reverse leakage current increases greatly, forming a photocurrent. This photocurrent varies with the intensity of the incident light.
  • PN Junction PN junction
  • TFT Thin Film Transistor
  • TFT can save cost and reduce the number of masks required in the manufacturing process compared with PIN photodiodes.
  • charge storage cannot be realized.
  • FIG. 1 is a schematic block diagram of a photodetection circuit of an embodiment of the present disclosure.
  • the photodetection circuit 100 includes a detection subcircuit 10 , a storage subcircuit 20 , an integration subcircuit 30 and a control subcircuit 40 .
  • the detection sub-circuit 10 is connected to the detection voltage signal terminal V_S, the bias voltage signal terminal V_B and the input node PD.
  • the detection sub-circuit 10 may generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal under the control of the potential of the detection voltage signal terminal V_S.
  • the storage sub-circuit 20 is connected between the bias voltage signal terminal V_B and the input node PD.
  • the storage sub-circuit 20 can store energy based on the current generated by the detection sub-circuit 10 .
  • the storage sub-circuit 20 may include a first capacitor, a first electrode of the first capacitor is connected to the bias voltage signal terminal V_B, and a second electrode of the first capacitor is connected to the input node PD.
  • the integrating subcircuit 30 has a first input V_IN, a second input V_R and an output V_OUT.
  • the integrating sub-circuit 30 can integrate the signal of the first input terminal V_IN based on the potential of the second input terminal V_R to generate an integrated signal and output it at the output terminal V_OUT.
  • the control subcircuit 40 is connected to the control signal terminal GATE, the input node PD and the first input terminal V_IN of the integrating circuit 30 .
  • the control sub-circuit 40 can provide the potential of the input node PD to the first input terminal V_IN of the integration circuit 30 under the control of the control signal terminal GATE.
  • energy storage can be performed based on the current generated by the detection sub-circuit, thereby improving detection accuracy.
  • FIG. 2 is a circuit diagram of a photodetection circuit according to an embodiment of the disclosure.
  • the photodetection circuit 200 includes a detection subcircuit 210 , a storage subcircuit 220 , an integration subcircuit 230 and a control subcircuit 240 .
  • the above descriptions about the detection subcircuit 10, the storage subcircuit 20, the integration subcircuit 30 and the control subcircuit 40 are also applicable to this embodiment.
  • the detection sub-circuit 210 may include a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the detection voltage signal terminal V_S
  • the first pole of the fourth transistor T4 is connected to the bias voltage signal terminal V_B
  • the second pole of the fourth transistor T4 is connected to the input node PD.
  • the fourth transistor T4 is configured to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal under the control of the potential of the detection voltage signal terminal V_S.
  • the storage sub-circuit 220 may include a first capacitor C.
  • a first electrode of the first capacitor C is connected to the bias voltage signal terminal V_B, and a second electrode of the first capacitor C is connected to the input node PD.
  • the first capacitor C is configured to store energy based on the current generated by the detection sub-circuit 210 .
  • the integrator subcircuit 230 includes an operational amplifier AMP and a second capacitor CF.
  • the first input terminal of the operational amplifier AMP is connected to the first input terminal V_IN of the integral sub-circuit 230
  • the second input terminal of the operational amplifier AMP is connected to the second input terminal V_R of the integral sub-circuit 230
  • the output terminal of the operational amplifier AMP is connected to The output terminal V_OUT of the integrator sub-circuit 230 .
  • a first electrode of the second capacitor CF is connected to the first input terminal of the operational amplifier, and a second electrode of the second capacitor CF is connected to the second input terminal of the operational amplifier AMP.
  • the control subcircuit 240 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the control signal terminal GATE, the first pole of the fifth transistor T5 is connected to the input node PD, and the second pole of the fifth transistor T5 is connected to the first input terminal V_IN of the integration circuit 30 .
  • the fifth transistor T5 can be turned on or off under the control of the control signal terminal GATE.
  • the input node PD is electrically connected to the first input terminal V_IN, so that the potential of the input node PD can be provided to the first input terminal V_IN of the integration circuit 30 .
  • the fifth transistor T5 is turned off, the input node PD is electrically isolated from the first input terminal V_IN, thereby preventing the potential of the input node PD from affecting the output signal of the output terminal V_OUT.
  • FIG. 3 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • the photodetection circuit 300 includes a detection subcircuit 310 , a storage subcircuit 320 , an integration subcircuit 330 and a control subcircuit 340 .
  • the above descriptions for the detection subcircuit 210, the storage subcircuit 220, the integration subcircuit 230 and the control subcircuit 240 are also applicable to the detection subcircuit 310, the storage subcircuit 320, the integration subcircuit 330 and the control subcircuit 340, the present disclosure is herein No longer.
  • the photoelectric detection circuit 300 further includes a reset auxiliary sub-circuit 350 .
  • the detection sub-circuit 310 is connected to the bias voltage signal terminal V_B through the reset auxiliary sub-circuit 350 .
  • the reset auxiliary subcircuit 350 can electrically connect the detection subcircuit 310 to the bias voltage signal terminal V_B during the detection period under the control of the reset auxiliary signal terminal L_RST, and connect the detection subcircuit 310 to the bias voltage signal terminal V_B during the reset period.
  • the bias voltage signal terminal V_B is electrically isolated.
  • the reset auxiliary sub-circuit 350 may include a first transistor T1, the gate of the first transistor T1 is connected to the reset auxiliary signal terminal L_RST, the first pole of the first transistor T1 is connected to the bias voltage signal terminal V_B, The second pole of the first transistor T1 is connected to the detection sub-circuit 310, for example, connected to the first pole of the fourth transistor T4.
  • the charge generated by the fourth transistor T4 is stored by the first capacitor C, and the signal at the output terminal V_OUT can be read by the back-end readout circuit.
  • the charge is exported from the first capacitor C to the back-end readout circuit. Take the capacitance in the circuit.
  • the light intensity is high or the charge derivation time is not enough, if the charges on the first capacitor C are not fully derived, this part of the charges will be accumulated on C.
  • the charge left in the previous frame will be read out together, so that the readout signal has a lag.
  • the input node PD can be reset, thereby reducing the leakage current of the detection sub-circuit 310 .
  • the first transistor T1 of the reset auxiliary sub-circuit 350 is turned on under the control of the reset auxiliary signal terminal L_RST, so as to provide the bias voltage of the bias voltage signal terminal V_B to the detection sub-circuit 310 for photoelectric detection. detection.
  • the reset phase is entered, and the first transistor T1 of the reset auxiliary sub-circuit 350 is turned off under the control of the reset auxiliary signal terminal L_RST, so that the fourth The transistor T4 and the fifth transistor T5 are electrically isolated from the bias voltage signal terminal V_B.
  • both the fourth transistor T4 and the fifth transistor T5 are turned on, thereby resetting the potential of the input node PD to the voltage of the second input terminal V_R.
  • the width-to-length ratio of the first transistor T1 can be set to be smaller than the width-to-length ratio of the fourth transistor T4, so that although there is a voltage difference between the first pole and the second pole of the first transistor T1, the leakage current generated by it is small , so it has less influence on the potential at the first pole of the first transistor T1. There is no voltage difference between the first electrode and the second electrode of the fourth transistor T4 of the detection sub-circuit 310 , and leakage current cannot be formed, thereby reducing hysteresis.
  • FIG. 4 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • the photodetection circuit 400 includes a detection subcircuit 410 , a storage subcircuit 420 , an integration subcircuit 430 and a control subcircuit 440 .
  • the above descriptions for the detection subcircuit 210, storage subcircuit 220, integration subcircuit 230 and control subcircuit 240 are also applicable to the detection subcircuit 410, storage subcircuit 420, integration subcircuit 430 and control subcircuit 440, the present disclosure is herein No longer.
  • the photodetection circuit 400 may further include a reset sub-circuit 460 .
  • the reset sub-circuit 460 can be connected to the reset signal terminal RST, the input node PD and the reset voltage terminal V_RST.
  • the reset sub-circuit 460 can provide the potential of the reset voltage terminal V_RST to the input node PD under the control of the signal of the reset signal terminal RST, wherein the potential of the reset voltage terminal V_RST is equal to that of the integration sub-circuit 430 The potential of the second input terminal V_R of .
  • the reset subcircuit 460 may include a second transistor T2.
  • the gate of the second transistor T2 is connected to the reset signal terminal RST, the first pole of the second transistor T2 is connected to the reset voltage terminal V_RST, and the second pole of the second transistor T2 is connected to the input node PD.
  • the potential of the reset voltage terminal V_RST can be provided to the input node PD after the data reading is completed, so as to clear the charge on the first capacitor C.
  • the photodetection circuit 400 may further include the above-mentioned reset auxiliary sub-circuit 350 to further reduce hysteresis.
  • FIG. 5 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • the photodetection circuit 500 includes a detection subcircuit 510 , a storage subcircuit 520 , an integration subcircuit 530 and a control subcircuit 540 .
  • the above descriptions for the detection subcircuit 210, the storage subcircuit 220, the integration subcircuit 230 and the control subcircuit 240 are also applicable to the detection subcircuit 510, the storage subcircuit 520, the integration subcircuit 530 and the control subcircuit 540, and the present disclosure is herein No longer.
  • the photodetection circuit 500 may further include an amplification sub-circuit 570 .
  • the amplification sub-circuit 570 is connected between the input node PD and the control sub-circuit 540, and is connected to the reference voltage terminal V_D.
  • the amplifying subcircuit 570 can generate a current Ids flowing between the reference signal terminal V_D and the control subcircuit 540 under the control of the potential of the input node PD.
  • the amplifying sub-circuit 570 may include a third transistor T3.
  • the gate of the third transistor T3 is connected to the input node PD, the first electrode of the third transistor T3 is connected to the reference voltage terminal V_D, and the second electrode of the third transistor T3 is connected to the control sub-circuit 540 .
  • the second pole of the third transistor T3 is connected to the first pole of the fifth transistor T5 in the control sub-circuit 540 .
  • the current generated by the detection sub-circuit 510 can be amplified, for example, by 5-20 times, and the current amplification at the first input terminal V_IN of the integral sub-circuit 530 reduces the proportion of the noise signal, thereby achieving The effect of noise reduction.
  • the arrangement of the amplifying sub-circuit 570 can also realize the reset of the input node PD. For example, in the reset phase, a low level can be applied to the detection voltage signal terminal V_S and the bias voltage signal terminal V_B is switched from a bias voltage (for example -4V) to a reference voltage (for example 1.4V), so that the fourth transistor T4 is turned on.
  • the reference voltage is provided to the input node PD, and the reset of the input node PD is completed.
  • a reset circuit (such as the above reset circuit 460 ) can be added to the photodetection circuit 500 to realize the reset of the input node PD.
  • the voltage of the bias voltage signal terminal V_B may not be changed during the reset phase. In this way, the anti-interference ability of the output signal can be improved.
  • FIG. 6 is a circuit diagram of a photodetection circuit according to another embodiment of the present disclosure.
  • the photodetection circuit 600 includes a detection subcircuit 610 , a storage subcircuit 620 , an integration subcircuit 630 and a control subcircuit 640 .
  • the above descriptions for the detection subcircuit 210, the storage subcircuit 220, the integration subcircuit 230 and the control subcircuit 240 are also applicable to the detection subcircuit 610, the storage subcircuit 620, the integration subcircuit 630 and the control subcircuit 640, and the present disclosure is herein No longer.
  • the photoelectric detection circuit 600 may further include a plurality of detection sub-circuits, for example, a detection sub-circuit 611 and a detection sub-circuit 612 .
  • a detection sub-circuit 611 and a detection sub-circuit 612 .
  • the above description for the detection sub-circuit 210 is also applicable to any one of the detection sub-circuit 611 or the detection sub-circuit 612 .
  • the detection subcircuit 611 includes a fourth transistor T4, the gate of the fourth transistor T4 of the detection subcircuit 611 is connected to the detection voltage signal terminal V_S, and the first pole of the fourth transistor T4 of the detection subcircuit 611 is connected to The bias voltage signal terminal V_B, the second pole of the fourth transistor T4 of the detection sub-circuit 611 is connected to the input node PD.
  • the detection sub-circuit 612 also includes a fourth transistor T4, and the second pole of the fourth transistor T4 of the detection sub-circuit 612 is also connected to the input node PD.
  • multiple detection sub-circuits are provided to increase the photocurrent.
  • the photodetection circuit has been described above with a specific example, the embodiments of the present disclosure are not limited thereto.
  • the above-mentioned embodiments can be combined in any suitable manner as required to form a new photodetection circuit structure.
  • the above-mentioned photodetection circuit 200 may also include one or more of the above-mentioned reset auxiliary subcircuit 350, reset subcircuit 460 and amplification subcircuit 570, and the number of detection subcircuits 220 in the photoelectric detection circuit 200 may be as shown in the figure 6 to expand as needed, such as increasing to two, three or more.
  • each transistor in the detection circuit in the above embodiment such as the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor is a P-type transistor, such as a P-type TFT, but the embodiments of the present disclosure are not limited to Therefore, each transistor may be an N-type transistor.
  • FIG. 7 is a cross-sectional view of a photodetection circuit according to an embodiment of the disclosure. For ease of description, only the fourth transistor T4, the fifth transistor T5 and the first capacitor C in the above photodetection circuit are shown.
  • the detection subcircuit may include a fourth transistor T4, and the control subcircuit may include a fifth transistor T5.
  • the fourth transistor T4 and the fifth transistor T5 may be disposed on the base substrate 701.
  • the first pole 7104 and the second pole 7103 of the fourth transistor T4 are arranged on the same layer as the first pole 7123 and the second pole 7124 of the fifth transistor T5.
  • the second pole 7103 of the fourth transistor T4 is electrically connected to the first pole 7123 of the fifth transistor T5.
  • the active layer 7102 of the fourth transistor T4 is set on the same layer as the active layer 7122 of the fifth transistor T5, and the gate 7101 of the fourth transistor T4 is set on the active layer 7102 of the fourth transistor T4 Facing the side of the base substrate 701 , the gate 7121 of the fifth transistor T5 is disposed on a side of the active layer 7122 of the fifth transistor T5 away from the base substrate 701 .
  • a flat layer 708 is provided on a side of the fourth transistor T4 and the fifth transistor T5 away from the base substrate 701 .
  • the first electrode 7111 of the first capacitor C is located on the side of the planar layer 708 away from the base substrate 701
  • the second electrode 7112 of the first capacitor C is located on a side of the planar layer 708 facing the base substrate 701 . side.
  • a first gate insulating layer 703 and a second gate insulating layer 704 are further disposed on the base substrate 701, and the active layer 7102 of the fourth transistor T4 and the active layer 7122 of the fifth transistor T5 are located on the second Between a gate insulating layer 703 and the base substrate 701 .
  • the gate 7101 of the fourth transistor T4 is disposed on the side of the first gate insulating layer 703 facing the base substrate 701 .
  • the gate 7121 of the fifth transistor T5 is disposed between the first gate insulating layer 703 and the second gate insulating layer 704 .
  • the side of the second gate insulating layer 704 away from the base substrate 701 may also be provided with an interlayer dielectric layer 705 .
  • the first pole 7104 and the second pole 7103 of the fourth transistor T4 and the first pole 7123 and the second pole 7124 of the fifth transistor T5 may be located on the side of the interlayer dielectric layer 705 away from the base substrate 701 .
  • the first pole 7104 and the second pole 7103 of the fourth transistor T4 are in contact with the active layer 7101 through the via holes in the interlayer dielectric layer 705 , the second gate insulating layer 704 and the first gate insulating layer 703 .
  • the first pole 7123 and the second pole 7124 of the fifth transistor T5 are in contact with the active layer 7122 through the interlayer dielectric layer 705 , the second gate insulating layer 704 and the via holes in the first gate insulating layer 703 .
  • a first passivation layer 706 and a second passivation layer 707 may also be disposed between the interlayer dielectric layer 705 and the planarization layer 708 .
  • the second passivation layer 707 is located between the first passivation layer 706 and the planarization layer 708 .
  • the second electrode 7112 of the first capacitor C is located between the second passivation layer 707 and the first passivation layer 706 .
  • the side of the planar layer 708 away from the base substrate 701 may also be provided with an encapsulation layer 709 .
  • the first electrode 7111 of the first capacitor C may be located between the encapsulation layer 709 and the planar layer 708 .
  • the second electrode 7112 of the first capacitor C is respectively in contact with the first electrode 7103 of the fourth transistor T4 and the second electrode 7123 of the fifth transistor T5 through the via hole in the first passivation layer 706 .
  • a barrier layer 702 may also be provided between the base substrate 701 and the first gate insulating layer 702 .
  • FIG. 8A is a top view of a photodetection circuit according to an embodiment of the disclosure. For ease of description, only the fourth transistor T4, the fifth transistor T5 and the first capacitor C in the above photodetection circuit are shown.
  • FIG. 8B is a top view of a photodetection circuit according to an embodiment of the present disclosure, wherein the capacitor C is removed to clearly show the structure of the fifth transistor T5.
  • the gate 7101 of the fourth transistor T4 is connected to the detection voltage signal terminal V_S
  • the first pole of the fourth transistor T4 is connected to the bias voltage signal terminal V_B
  • the second pole of the fourth transistor T4 is connected to the first The first pole of five transistors T5.
  • the gate of the fifth transistor T5 is connected to the control signal terminal GATE.
  • the first pole of the fifth transistor T5 is connected to the second pole of the fourth transistor T4.
  • the second pole of the fifth transistor T5 is connected to the first input terminal V_IN of the integration circuit through a signal wire.
  • the first electrode 7111 of the first capacitor C is connected to the bias voltage signal terminal V_S.
  • the second electrode 7112 of the first capacitor C is connected to the input node PD.
  • the fourth transistor, the fifth transistor, and the first capacitor are shown in a specific layout in the above-mentioned embodiments, the embodiments of the present disclosure are not limited thereto, and any other suitable layout can be used to arrange the detection circuit. individual transistors.
  • FIG. 9 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure.
  • the cross-sectional view of FIG. 9 can be applied to, for example, the photodetection circuit 300 described above.
  • the photodetection circuit may further include a reset auxiliary sub-circuit, and the reset auxiliary sub-circuit may include a first transistor T1.
  • the fourth transistor T4 the fifth transistor T5 and the first transistor T1 are shown.
  • the arrangement of components in the photodetection circuit in FIG. 9 is similar to that in FIG. 7 , the difference is at least that the first transistor T1 is included in FIG. 9 .
  • the following will mainly describe the difference in detail.
  • the first transistor T1 may be disposed on the base substrate 701 .
  • the first pole 7033 and the second pole 7134 of the first transistor T1, the first pole 7104 and the second pole 7103 of the fourth transistor T4, and the first pole 7123 and the second pole 7124 of the fifth transistor T5 can be the same layer settings.
  • the active layer 7132 of the first transistor T1, the active layer 7102 of the fourth transistor T4 and the active layer 7122 of the fifth transistor T5 are arranged in the same layer.
  • the gate 7131 of the first transistor T1 is disposed on a side of the active layer 7132 of the first transistor T1 away from the substrate 701 .
  • the second pole 7134 of the first transistor T1 is electrically connected to the first pole 7104 of the fourth transistor T4.
  • FIG. 10 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure. This cross-sectional view is applicable, for example, to the electrical detection circuit 400 described above.
  • the detection circuit may further include a reset subcircuit, and the reset subcircuit 460 may include a second transistor T2.
  • the arrangement of components in the photodetection circuit in FIG. 10 is similar to that in FIG. 7 . The difference is at least that the second transistor T2 is included in FIG. 10 .
  • the second transistor T2 is included in FIG. 10 .
  • the following will mainly describe the differences in detail.
  • the second transistor T2 may be disposed on the base substrate 701 .
  • the first pole 7143 and the second pole 7144 of the second transistor T2, the first pole 7104 and the second pole 7103 of the fourth transistor T4, and the first pole 7123 and the second pole 7124 of the fifth transistor T5 may be arranged in the same layer.
  • the active layer 7122 of the second transistor T2, the active layer 7102 of the fourth transistor T4 and the active layer 7122 of the fifth transistor T5 are arranged in the same layer.
  • the gate 7141 of the second transistor T2 is disposed on the side of the active layer 7142 of the second transistor T2 away from the substrate 701 .
  • the second electrode 7144 of the second transistor T2 is electrically connected to the second electrode 7103 of the fourth transistor T4 and the first electrode 7123 of the fifth transistor T5, and the second electrode 7112 of the first capacitor C passes through the first The via in the passivation layer 706 is in contact with the second pole 7144 of the second transistor T2.
  • FIG. 11 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure. This cross-sectional view is applicable, for example, to the electrical detection circuit 400 described above.
  • the photodetection circuit may further include an amplification subcircuit, and the reset subcircuit may include a third transistor T3.
  • the arrangement of components in the photodetection circuit in FIG. 11 is similar to that in FIG. 7 . The difference is at least that a third transistor T3 is included in FIG. 11 .
  • the following will mainly describe the differences in detail.
  • the third transistor T3 may be disposed on the base substrate 701, the first pole 7153 and the second pole 7154 of the third transistor T3, the first pole 7104 and the second pole 7103 of the fourth transistor T4 and the fifth transistor
  • the first pole 7123 and the second pole 7124 of T5 can be arranged in the same layer.
  • the active layer 7152 of the third transistor T3, the active layer 7102 of the fourth transistor T4 and the active layer 7122 of the fifth transistor T5 are arranged in the same layer.
  • the gate 7151 of the third transistor T3 is disposed on the side of the active layer 7152 of the third transistor T3 away from the substrate 701 .
  • the second electrode 7154 of the third transistor T3 is electrically connected to the first electrode 7123 of the fifth transistor T5, and the second electrode 7112 of the first capacitor C passes through the first passivation layer 706 and the interlayer dielectric layer 705 And the via hole in the second gate insulating layer 704 is in contact with the gate 7151 of the third transistor T3.
  • FIG. 12 is a cross-sectional view of a photodetection circuit according to another embodiment of the present disclosure. This cross-sectional view is applicable to, for example, the photodetection circuit 600 described above.
  • the photodetection circuit may include a plurality of detection subcircuits, and each detection subcircuit may include a fourth transistor T4.
  • the arrangement of components in the photodetection circuit in FIG. 11 is similar to that in FIG. 7 , the difference is at least that there are multiple fourth transistors T4 in FIG. 12 .
  • the differences will be described in detail below.
  • each fourth transistor T4 has the same layer structure and circuit connection.
  • the descriptions of the fourth transistor T4 in the above embodiments are also applicable to this embodiment.
  • the second pole 7104 of each fourth transistor T4 is electrically connected to the first pole 7123 of the fifth transistor T5 and the second pole 7112 of the first capacitor C.
  • the second electrode 7112 of the first capacitor C is respectively in contact with the second electrodes 7104 of the plurality (two) of the fourth transistors T4 through the plurality (two) via holes of the first passivation layer 706 .
  • FIG. 13 is a cross-sectional view of a pixel unit according to an embodiment of the present disclosure.
  • the pixel unit 1300 includes at least one pixel circuit 1301 and the photodetection circuit of any of the above-mentioned embodiments. For simplicity, only the fourth transistor T4, the fifth transistor T5 and the first capacitor C1 in the photodetection circuit are shown.
  • the pixel circuit 1300 may include a driving transistor, wherein the driving transistor may include a gate 1311 , a source 1313 and a drain 1314 .
  • the driving transistor may further include an active layer 1312 on the base substrate 701 , and the gate 1311 of the driving transistor is located on a side of the active layer 1312 away from the base substrate 701 .
  • the driving transistor may further include a first gate insulating layer 703 located between the active layer 1312 and the gate 1311, a second gate insulating layer 704 located on the side of the gate 1311 away from the base substrate 701, located The second gate insulating layer 704 is away from the interlayer dielectric layer 705 on the side of the substrate 701 .
  • the source 1313 and the drain 1314 of the driving transistor are located on the side of the interlayer dielectric layer 705 away from the base substrate 701 .
  • the pixel circuit further includes a light emitting unit, and the light emitting unit includes an anode 1315 , a cathode 1316 and a light emitting layer 1317 between the anode 1315 and the cathode 1316 .
  • the side of the interlayer dielectric layer 705 away from the base substrate 701 is provided with a flat layer 708, the anode 1315 is located on the side of the flat layer 708 away from the base substrate 701 and passes through the flat layer 708 is connected to the source 1313 or the drain 1314 of the driving transistor.
  • the detection subcircuit of the photodetection circuit includes a fourth transistor T4, and the control subcircuit of the photodetection circuit includes a fifth transistor T5.
  • the gate 7101 of the fourth transistor T4 is located between the first gate insulating layer 703 and the base substrate 701, the first pole 7104 and the second pole 7103 of the fourth transistor T4 are connected to the source of the driving transistor At least one of the electrode 1313 and the drain 1314 is set on the same layer, the active layer 7102 of the fourth transistor T4 is set on the same layer as the active layer 1312 of the driving transistor, and the gate 7121 of the fifth transistor T5 is set on the same layer as The gate 1311 of the driving transistor is set on the same layer, the first pole 7124 and the second pole 7123 of the fifth transistor T5 are set on the same layer as at least one of the source 1313 and the drain 1314 of the driving transistor, so The active layer 7122 of the fifth transistor T5 is set in the same layer as the active layer 1312 of the driving transistor.
  • the storage sub-circuit of the photodetection circuit includes a first capacitor C, the first electrode 7111 of the first capacitor C is set on the same layer as the anode 1315 of the light emitting unit, and the second electrode 7112 of the first capacitor C is located on the flat layer 708 faces one side of the base substrate 701 .
  • a first passivation layer 706 and a passivation layer between the first passivation layer 706 and the planar layer 708 are further provided between the planar layer 708 and the interlayer dielectric layer 705
  • an encapsulation layer 709 is provided on a side of the planar layer 708 away from the base substrate 701 .
  • the light emitting unit and the first electrode 7111 of the first capacitor can be disposed between the encapsulation layer 709 and the flat layer 708 .
  • FIG. 14 is an operation timing diagram of a photodetection circuit according to an embodiment of the present disclosure. The operation sequence of FIG. 14 will be described below in conjunction with the above-mentioned photodetection circuit 200 .
  • the control signal terminal GATE applies a periodic signal
  • a constant voltage is applied to the detection voltage signal terminal V_S, for example, between -3V and -6V
  • a constant voltage is applied to the bias voltage signal terminal V_B, for example, between -4V and -6V.
  • the control signal terminal GATE is at a high level, and the fifth transistor T5 is turned off, thereby electrically isolating the input node PD from the first input terminal V_IN.
  • the potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B make the fourth transistor T4 in a reverse conduction state, so that the fourth transistor T4 can respond to an optical signal to generate a voltage between the bias voltage signal terminal V_B and the input node PD. flowing current.
  • the first capacitor C stores the charges generated by the fourth transistor T4.
  • the control signal terminal GATE is at a low level, so that the fifth transistor T5 is turned on, and then the input node PD is electrically connected to the first input terminal V_IN.
  • the fifth transistor T5 provides the potential of the input node PD to the first input terminal V_IN, so that the charge stored in the first capacitor C is exported to the capacitor in the back-end integral sub-circuit, and the operational amplifier AMP in the integral sub-circuit is based on the first
  • the reference level of the two input terminals V_R and the signal at the first input terminal V_IN are used to generate an integrated signal and output at the output terminal V_OUT.
  • FIG. 15 is an operation timing diagram of a photodetection circuit according to another embodiment of the present disclosure. The operation sequence of FIG. 15 will be described below in conjunction with the above-mentioned photodetection circuit 300 .
  • each detection period includes a detection period and a reset period, wherein the detection period includes periods t11, t12 and t13.
  • the auxiliary reset signal terminal L_RST is at low level, the detection voltage signal terminal V_S is at high level, and the control signal terminal GATE is at high level.
  • the auxiliary reset signal terminal L_RST is at a low level to turn on the first transistor T1 , so as to provide the bias voltage of the bias voltage signal terminal V_B to the fourth transistor T4 .
  • the potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B make the fourth transistor T4 in a reverse conduction state, so that the fourth transistor T4 generates charges in response to the light signal, and then generates charges at the bias voltage signal terminal V_B and the input node Current flowing between PDs.
  • the first capacitor C stores the charges generated by the fourth transistor T4.
  • the control signal terminal GATE is at a high level to turn off the fifth transistor T5 , so that the input node PD is electrically isolated from the integrating sub-circuit 330 .
  • the auxiliary reset signal terminal L_RST is at a high level, so that the first transistor T1 is turned off, and the presence of the first capacitor C keeps the first electrode of the fourth transistor T4 at a bias voltage.
  • the potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B remain unchanged, so that the fourth transistor T4 continues to generate charges in response to the light signal and store them in the first capacitor C.
  • the control signal terminal GATE is at a low level, so that the fifth transistor T5 is turned on, and then the input node PD is electrically connected to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN.
  • the charge stored in the first capacitor C is exported to the back-end integral sub-circuit, so that the output terminal V_OUT generates an output signal.
  • the auxiliary reset signal terminal L_RST is at high level, the detection voltage signal terminal V_S is at low level, and the control signal terminal GATE is at low level.
  • the auxiliary reset signal terminal L_RST is at a high level to turn off the first transistor T1, thereby electrically isolating the fourth transistor T4 and the fifth transistor T5 from the bias voltage signal terminal V_B.
  • the detection voltage signal terminal V_S is at a low level to turn on the fourth transistor T4, and the control signal terminal GATE is at a low level to turn on the fifth transistor T5, thereby resetting the potential of the input node PD to the voltage of the second input terminal V_R .
  • FIG. 16 is an operation timing diagram of a photodetection circuit according to another embodiment of the present disclosure. The operation sequence of FIG. 15 will be described below in conjunction with the above-mentioned photodetection circuit 400 .
  • the reset signal terminal RST is at a high level, so that the fifth transistor T5 is turned off, thereby electrically isolating the input node PD from the first input terminal V_IN.
  • the potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B cause the fourth transistor T4 to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal.
  • the first capacitor C stores the charges generated by the fourth transistor T4.
  • the fifth transistor T5 When the low level of the control signal terminal GATE arrives, the fifth transistor T5 is turned on, and then the input node PD is electrically connected to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN, the first The charge stored in the capacitor C is exported to the capacitor in the back-end integral sub-circuit, so that the output terminal V_OUT generates a low-level output signal.
  • the reset signal terminal RST is at low level, and the control signal terminal GATE is at high level.
  • the reset signal terminal RST is at a low level to turn on the second transistor T2, and the reset voltage terminal V_RST is electrically connected to the input node PD, so that the potential of the reset voltage terminal V_RST is provided to the input node PD to reset the input node PD.
  • FIG. 17 is an operation timing diagram of a photodetection circuit according to another embodiment of the present disclosure. The operation sequence of FIG. 16 will be described below in conjunction with the above-mentioned photodetection circuit 500 .
  • the potentials of the bias voltage signal terminal V_B and the detection voltage signal terminal V_S cause the fourth transistor T4 to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal, and the first capacitor C Charges generated by the fourth transistor T4 are stored.
  • the fifth transistor T5 is turned on, and the input node PD is electrically connected to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN.
  • the charge stored in the first capacitor C is exported to the capacitor in the back-end integral sub-circuit, so that the output terminal V_OUT generates an output signal.
  • the detection voltage signal terminal V_S is at a low level, and the potential of the bias voltage signal terminal V_B can change from the potential of the detection period (for example -4V) to a reference voltage, for example, it can be equal to the second input terminal V_R of the integral sub-circuit The reference voltage at 1.4V.
  • the potentials of the bias voltage signal terminal V_B and the detection voltage signal terminal V_S make the fourth transistor T4 conduct forward, so as to provide the reference voltage of the bias voltage signal terminal V_B to the input node PD to complete the reset of the input node PD.
  • the operation sequence of the above-mentioned photoelectric detection circuit 600 is similar to that of the photoelectric detection circuit 200 , and reference can be made to the operation sequence of FIG. 14 described above, which will not be repeated here.
  • FIG. 18 is a flowchart of a control method of a photodetection circuit according to an embodiment of the present disclosure.
  • the control method 1800 may include operation S1801 to operation S1804.
  • the detection subcircuit In operation S1801, the detection subcircuit generates a current flowing between the bias voltage signal terminal and the input node in response to the light signal.
  • the storage subcircuit performs energy storage based on the current generated by the detection subcircuit.
  • control subcircuit provides the potential of the input node to the first input terminal of the integration circuit under the control of the control signal terminal.
  • the integrating subcircuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.
  • the photodetection circuit further includes a reset auxiliary subcircuit, and the method includes a detection period and a reset period.
  • the reset auxiliary sub-circuit electrically connects the detection sub-circuit to the bias voltage signal end under the control of the reset auxiliary signal end, and the detection sub-circuit responds to the optical signal to generate a voltage flowing between the bias voltage signal end and the input node.
  • the storage subcircuit performs energy storage based on the current generated by the detection subcircuit
  • the control subcircuit provides the potential of the input node to the first input terminal of the integration circuit under the control of the control signal terminal
  • the integration subcircuit is based on the potential of the second input terminal
  • the signal at the first input terminal is integrated to generate an integrated signal and output at the output terminal.
  • the reset auxiliary subcircuit electrically isolates the detection subcircuit from the bias voltage signal terminal under the control of the reset auxiliary signal terminal, and the detection subcircuit electrically isolates the bias voltage signal terminal from the input node under the control of the potential of the detection voltage signal terminal.
  • the control subcircuit electrically connects the input node to the first input terminal of the integration circuit under the control of the control signal terminal.
  • the photodetection circuit further includes a reset subcircuit, and the method includes a detection period and a reset period.
  • the reset subcircuit electrically isolates the reset voltage terminal from the input node under the control of the reset signal terminal, the detection subcircuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal, and the storage subcircuit Energy storage is performed based on the current generated by the detection sub-circuit, the control sub-circuit provides the potential of the input node to the first input terminal of the integration circuit under the control of the control signal terminal, and the integration sub-circuit controls the potential of the first input terminal based on the potential of the second input terminal.
  • the signal is integrated to produce an integrated signal which is output at the output.
  • the reset subcircuit electrically connects the reset voltage terminal to the input node under the control of the reset signal terminal, and the control subcircuit electrically isolates the input node from the first input terminal of the integrating circuit under the control of the control signal terminal.
  • the photodetection circuit further includes an amplification subcircuit, and the method includes a detection period and a reset period.
  • the detection subcircuit During the detection period, the detection subcircuit generates a current flowing between the bias voltage signal terminal and the input node in response to the light signal under the control of the potential of the detection voltage signal terminal, and the storage subcircuit performs energy based on the current generated by the detection subcircuit.
  • the storage and amplifying subcircuits Under the control of the potential of the input node, the storage and amplifying subcircuits generate a current flowing between the reference signal terminal and the control subcircuit, and the control subcircuit supplies the current generated by the amplifying subcircuit to the first integration circuit under the control of the control signal terminal.
  • An input terminal, the integral sub-circuit integrates the signal at the first input terminal based on the potential of the second input terminal to generate an integrated signal and output it at the output terminal.
  • the detection subcircuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal, wherein the potential of the bias voltage signal terminal in the reset period is different from that in the detection phase.

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Abstract

提供了一种光电检测电路(100)及其控制方法、像素单元。光电检测电路(100)包括：检测子电路(10)，连接检测电压信号端(V_S)、偏置电压信号端(V_B)和输入节点(PD)，并且被配置为在检测电压信号端(V_S)的电位的控制下响应于光信号来产生在偏置电压信号端(V_B)和输入节点(PD)之间流动的电流；存储子电路(20)，连接在偏置电压信号端(V_B)与输入节点(PD)之间，并且被配置为基于检测子电路(10)产生的电流来进行能量存储；积分子电路(30)，具有第一输入端(V_IN)、第二输入端(V_R)和输出端(V_OUT)，并且被配置为基于第二输入端(V_R)的电位对第一输入端(V_IN)的信号进行积分，以产生积分信号并在输出端(V_OUT)输出；控制子电路(40)，连接至控制信号端(GATE)、输入节点(PD)和积分子电路(30)的第一输入端(V_IN)。

Description

光电检测电路及其控制方法和像素单元 技术领域
本公开涉及光电检测技术领域，尤其涉及一种光电检测电路及其控制方法和像素单元。
背景技术
通常，为了进行光学指纹识别，可以将光敏器件布置成阵列，以采集由于手指纹理导致的反射光或透射光的强度变化，并利用光敏器件进行光电转换。根据光强度转换来的电信号，能够实现指纹图像采集，从而进行光学指纹识别。但是目前大多检测电路的检测效果不理想。
发明内容
本公开实施例提供了一种光电检测电路，该光电检测电路包括：
检测子电路，连接检测电压信号端、偏置电压信号端和输入节点，并且被配置为在检测电压信号端的电位的控制下响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流；
存储子电路，连接在偏置电压信号端与输入节点之间，并且被配置为基于检测子电路产生的电流来进行能量存储；
积分子电路，具有第一输入端、第二输入端和输出端，并且被配置为基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
控制子电路，连接至控制信号端、输入节点和所述积分电路的第一输入端，并且被配置为在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端。
例如，所述存储子电路包括第一电容，所述第一电容的第一电极连接至所述偏置电压信号端，所述第一电容的第二电极连接至所述输入节点。
例如，该光电检测电路还包括：复位辅助子电路，所述检测子电路通过所述复位辅助子电路与所述偏置电压信号端连接，所述复位辅助子电路被配置为在所述复位辅助信号端的控制下在检测时段将所述检测子电路与所述偏置电压信号端电连接，在复位时段将所述检测子电路与所述偏置电压信号端电隔离。
例如，所述复位辅助子电路包括第一晶体管，所述第一晶体管的栅极连接所述复位 辅助信号端，所述第一晶体管的第一极连接所述偏置电压信号端，所述第一晶体管的第二极连接所述检测子电路。
例如，该光电检测电路还包括：复位子电路，连接复位信号端、所述输入节点和复位电压端，并且被配置为在所述复位信号端的信号的控制下将所述复位电压端的电位提供至所述输入节点，其中所述复位电压端的电位等于所述积分子电路的第二输入端的电位。
例如，所述复位子电路包括第二晶体管，所述第二晶体管的栅极连接所述复位信号端，所述第二晶体管的第一极连接所述复位电压端，所述第二晶体管的第二极连接所述输入节点。
例如，该光电检测电路还包括放大子电路，连接在所述输入节点与所述控制子电路之间，并且与参考电压端连接，所述放大子电路被配置为在所述输入节点的电位的控制下产生在所述参考信号端和所述控制子电路之间流动的电流。
例如，所述放大子电路包括第三晶体管，所述第三晶体管的栅极连接所述输入节点，所述第三晶体管的第一极连接所述参考电压端，所述第三晶体管的第二极连接所述控制子电路。
例如，所述检测子电路包括第四晶体管，所述第四晶体管的栅极连接所述检测电压信号端，所述第四晶体管的第一极连接所述偏置电压信号端，所述第四晶体管的第二极连接所述输入节点。
例如，该光电检测电路包括多个所述检测子电路。
例如，所述控制子电路包括第五晶体管，所述第五晶体管的栅极连接所述控制信号端，所述第五晶体管的第一极连接所述输入节点，所述第五晶体管的第二极连接所述积分电路的第一输入端。
例如，所述积分子电路包括：
运算放大器，所述运算放大器的第一输入端连接为所述积分子电路的第一输入端，所述运算放大器的第二输入端连接为所述积分子电路的第二输入端，所述运算放大器的输出端连接为所述积分子电路的输出端；
第二电容，所述第二电容的第一电极连接所述运算放大器的第一输入端，所述第二电容的第二电极连接所述运算放大器的第二输入端。
例如，所述检测子电路包括第四晶体管，所述控制子电路包括第五晶体管，所述第四晶体管和所述第五晶体管设置在衬底基板上，所述第四晶体管的第一极和第二极与所 述第五晶体管的第一极和第二极同层设置，所述第四晶体管的有源层与所述第五晶体管的有源层同层设置，所述第四晶体管的栅极设置在所述第四晶体管的有源层面向所述衬底基板的一侧，所述第五晶体管的栅极设置在所述第五晶体管的有源层背离所述衬底基板的一侧。
例如，所述第四晶体管和第五晶体管背离所述衬底基板的一侧设置有平坦层，所述第一电容的第一电极位于所述平坦层背离所述衬底基板的一侧，所述第一电容的第二电极位于所述平坦层面向所述衬底基板的一侧。
本公开实施例还提供了一种像素单元，包括：
至少一个像素电路，每个像素电路被配置为基于像素电路被配置为基于数据电压来进行发光；以及
如上所述的光电检测电路。
例如，所述像素电路包括驱动晶体管，所述驱动晶体管包括位于衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，位于所述有源层与所述栅极之间的第一栅绝缘层，位于所述栅极远离所述衬底基板一侧的第二栅绝缘层，位于所述第二栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的源极和漏极；
所述光电检测电路的检测子电路包括第四晶体管，所述光电检测电路的控制子电路包括第五晶体管，其中所述第四晶体管的栅极位于所述第一栅绝缘层与所述衬底基板之间，所述第四晶体管的第一极和第二极与所述驱动晶体管的源极和漏极中的至少之一同层设置，所述第四晶体管的有源层与所述驱动晶体管的有源层同层设置，所述第五晶体管的栅极与所述驱动晶体管的栅极同层设置，所述第五晶体管的第一极和第二极与所述驱动晶体管的源极和漏极中的至少之一同层设置，所述第五晶体管的有源层与所述驱动晶体管的有源层同层设置。
例如，所述像素电路还包括发光单元，所述发光单元包括阳极、阴极以及位于所述阳极和阴极之间的发光层，其中所述层间介质层远离所述衬底基板的一侧设置有平坦层，所述阳极位于所述平坦层远离所述衬底基板的一侧并且穿过所述平坦层与所述驱动晶体管的源极或漏极连接；
所述光电检测电路的存储子电路包括第一电容，所述第一电容的第一电极与所述阳极同层设置，所述第一电容的第二电极位于所述平坦层面向所述衬底基板的一侧。
例如，在所述平坦层与所述层间介质层之间还设置有第一钝化层以及位于所述第一 钝化层与所述平坦层之间的第二钝化层，其中所述驱动晶体管的源极和漏极位于所述第一钝化层与所述层间介质层之间，所述第一电容的第二电极位于所述第二钝化层与所述第一钝化层之间。
本公开实施例还提供了一种如上所述的光电检测电路的控制方法，包括：
检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流；
存储子电路基于检测子电路产生的电流来进行能量存储；
控制子电路在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端；
积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出。
例如，所述光电检测电路还包括复位辅助子电路，所述方法包括：
在检测时段，所述复位辅助子电路在复位辅助信号端的控制下将所述检测子电路与所述偏置电压信号端电连接，所述检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，所述存储子电路基于检测子电路产生的电流来进行能量存储，所述控制子电路在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端，所述积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
在复位时段，所述复位辅助子电路在复位辅助信号端的控制下将所述检测子电路与所述偏置电压信号端电隔离，所述检测子电路在检测电压信号端的电位的控制下将偏置电压信号端与输入节点电连接，所述控制子电路在控制信号端的控制下将输入节点与所述积分电路的第一输入端电连接。
例如，所述光电检测电路还包括复位子电路，所述方法包括：
在检测时段，所述复位子电路在复位信号端的控制下将所述复位电压端与所述输入节点电隔离，所述检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，所述存储子电路基于检测子电路产生的电流来进行能量存储，所述控制子电路在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端，所述积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
在复位时段，所述复位子电路在复位信号端的控制下将所述复位电压端与所述输入节点电连接，所述控制子电路在控制信号端的控制下将输入节点与所述积分电路的第一 输入端电隔离。
例如，所述光电检测电路还包括放大子电路，所述方法包括：
在检测时段，检测子电路在检测电压信号端的电位的控制下响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，存储子电路基于检测子电路产生的电流来进行能量存储，放大子电路在所述输入节点的电位的控制下产生在所述参考信号端和所述控制子电路之间流动的电流，控制子电路在控制信号端的控制下将放大子电路产生的电流提供至所述积分电路的第一输入端，积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
在复位时段，所述检测子电路在检测电压信号端的电位的控制下将偏置电压信号端与输入节点电连接，其中所述偏置电压信号端在复位时段的电位不同于在检测阶段的电位。
附图说明
图1是本公开实施例的光电检测电路的示意框图；
图2是本公开一实施例的光电检测电路的电路图；
图3是本公开另一实施例的光电检测电路的电路图；
图4是本公开另一实施例的光电检测电路的电路图；
图5是本公开另一实施例的光电检测电路的电路图；
图6是本公开另一实施例的光电检测电路的电路图；
图7是本公开一实施例的光电检测电路的截面图；
图8A是本公开一实施例的光电检测电路的俯视图；
图8B是本公开一实施例的光电检测电路的俯视图；
图9是本公开另一实施例的光电检测电路的截面图；
图10是本公开另一实施例的光电检测电路的截面图；
图11是本公开另一实施例的光电检测电路的截面图；
图12是本公开另一实施例的光电检测电路的截面图；
图13是本公开一实施例的像素单元的截面图；
图14是本公开一实施例的光电检测电路的操作时序图；
图15是本公开另一实施例的光电检测电路的操作时序图；
图16是本公开另一实施例的光电检测电路的操作时序图；
图17是本公开另一实施例的光电检测电路的操作时序图；以及
图18是本公开一实施例的光电检测电路的控制方法的流程图
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
终端设备，例如智能电话、膝上型计算机等，可以为用户提供指纹识别功能，以识别用户身份。相关技术中，为了进行光学指纹识别，可以将光敏器件阵列化，以采集不同手指区域下的反射或透射的光信号。再利用光敏器件进行光电转换，得到根据光光信号转换来的电信号。最后，利用模数转换器(Analog-to-Digital Converter，ADC)将电信号转换为数字信号，以完成指纹图像采集。
在制作屏内(屏下)指纹识别组件时，使用较多的是PIN型光敏二极管。PIN型光敏二极管与半导体二极管具有类似的结构。PIN型光敏二极管的管芯是一个具有光敏特征的PN结(PN Junction)，具有单向导电性。因此，在工作状态下，可以为PIN型光敏二极管提供反向电压。无光照时，有很小的饱和反向漏电流，即暗电流，此时光敏二极管截止。当受到光照时，饱和反向漏电流大大增加，形成光电流。该光电流随入射光强度的变化而变化。当光线照射PN结时，PN结中可以产生电子一空穴对，使少数载流子的密度增加。这些载流子在反向电压下漂移，使光电流(反向电流)增加。因此， 可以利用光照强弱来改变电路中的电流。
薄膜晶体管(Thin Film Transistor，TFT)，可以作为开关，用于控制PIN型光敏二极管中电荷的导出。在理想状况下，TFT关断时是不流过电流的。但由于漏极/源极与衬底之间是两个PN结，因此即使TFT没有沟道，漏极和源极之间还是有反向的饱和电流(漏电流)。TFT受光照时也会随光照强弱来改变其输出电流，换言之，TFT能够作为光敏器件对光照做出响应。
TFT作为光敏器件，与PIN光敏二极管相比，能够节省成本，在制作过程中减少所需的掩模数量。但是，在TFT作为光敏器件时，无法实现电荷的存储。
图1是本公开实施例的光电检测电路的示意框图。
如图1所示，光电检测电路100包括检测子电路10、存储子电路20、积分子电路30和控制子电路40。
检测子电路10连接检测电压信号端V_S、偏置电压信号端V_B和输入节点PD。检测子电路10可以在检测电压信号端V_S的电位的控制下响应于光信号来产生在偏置电压信号端V_B和输入节点PD之间流动的电流。
存储子电路20连接在偏置电压信号端V_B与输入节点PD之间。存储子电路20可以基于检测子电路10产生的电流来进行能量存储。例如，存储子电路20可以包括第一电容，第一电容的第一电极连接至所述偏置电压信号端V_B，所述第一电容的第二电极连接至所述输入节点PD。
积分子电路30具有第一输入端V_IN、第二输入端V_R和输出端V_OUT。积分子电路30可以基于第二输入端V_R的电位对所述第一输入端V_IN的信号进行积分，以产生积分信号并在输出端V_OUT输出。
控制子电路40连接至控制信号端GATE、输入节点PD和所述积分电路30的第一输入端V_IN。控制子电路40可以在控制信号端GATE的控制下将输入节点PD的电位提供至所述积分电路30的第一输入端V_IN。
根据本公开实施例，通过设置上述储能子电路，可以基于检测子电路产生的电流来进行能量存储，从而提高检测的准确性。
下面将参考图2至图7来说明本公开实施例的输出电路的一些示例。
图2是本公开一实施例的光电检测电路的电路图。
如图2所示，光电检测电路200包括检测子电路210、存储子电路220、积分子电路230和控制子电路240。以上关于检测子电路10、存储子电路20、积分子电路30和控制 子电路40的描述同样适用于本实施例。
在一些实施例中，检测子电路210可以包括第四晶体管T4。第四晶体管T4的栅极连接检测电压信号端V_S，第四晶体管T4的第一极连接至偏置电压信号端V_B，第四晶体管T4的第二极连接至输入节点PD。并且第四晶体管T4被配置为在检测电压信号端V_S的电位的控制下响应于光信号来产生在偏置电压信号端V_B和输入节点PD之间流动的电流.
在一些实施例中，存储子电路220可以包括第一电容C。第一电容C的第一电极连接至所述偏置电压信号端V_B，所述第一电容C的第二电极连接至所述输入节点PD。并且第一电容C被配置为基于检测子电路210产生的电流来进行能量存储。
在一些实施例中，积分子电路230包括运算放大器AMP和第二电容CF。运算放大器AMP的第一输入端连接为积分子电路230的第一输入端V_IN，运算放大器AMP的第二输入端连接为积分子电路230的第二输入端V_R，运算放大器AMP的输出端连接为积分子电路230的输出端V_OUT。第二电容CF的第一电极连接所述运算放大器的第一输入端，所述第二电容CF的第二电极连接所述运算放大器AMP的第二输入端。
在一些实施例中，控制子电路240包括第五晶体管T5。第五晶体管T5的栅极连接至控制信号端GATE，第五晶体管T5的第一极连接输入节点PD，第五晶体管T5的第二极连接所述积分电路30的第一输入端V_IN。第五晶体管T5可以在控制信号端GATE的控制下导通或关断。当第五晶体管T5导通时，输入节点PD与第一输入端V_IN电连接，从而可以将输入节点PD的电位提供至所述积分电路30的第一输入端V_IN。当第五晶体管T5关断时，输入节点PD与第一输入端V_IN电隔离，从而避免输入节点PD的电位影响输出端V_OUT的输出信号。
图3是根据本公开另一实施例的光电检测电路的电路图。
如图3所示，光电检测电路300包括检测子电路310、存储子电路320、积分子电路330和控制子电路340。以上对于检测子电路210、存储子电路220、积分子电路230和控制子电路240的描述同样适用于检测子电路310、存储子电路320、积分子电路330和控制子电路340，本公开在此不再赘述。
如图3所示，该光电检测电路300还包括复位辅助子电路350。
检测子电路310通过所述复位辅助子电路350与所述偏置电压信号端V_B连接。复位辅助子电路350可以在所述复位辅助信号端L_RST的控制下在检测时段将所述检测子电路310与所述偏置电压信号端V_B电连接，在复位时段将所述检测子电路310与所述 偏置电压信号端V_B电隔离。
例如，复位辅助子电路350可以包括第一晶体管T1，第一晶体管T1的栅极连接所述复位辅助信号端L_RST，所述第一晶体管T1的第一极连接所述偏置电压信号端V_B，所述第一晶体管T1的第二极连接所述检测子电路310，比如连接第四晶体管T4的第一极。
在检测过程中，第四晶体管T4产生的电荷被第一电容C存储，输出端V_OUT处的信号可以被后端读取电路读取，在读取时电荷从第一电容C导出至后端读取电路中的电容中。当光强较高或电荷导出时间不够时，若第一电容C上的电荷未全部导出，这部分电荷就会在C上累计。当下一次读出时，就会将上一帧中留下的电荷一并读出，使得读出的信号有滞后(lag)。
通过在偏置电压信号端V_B和检测子电路310之间设置复位辅助子电路350，可以实现对输入节点PD的复位，从而减小检测子电路310的漏电流。
例如，在检测阶段，复位辅助子电路350的第一晶体管T1在复位辅助信号端L_RST的控制下导通，从而将偏置电压信号端V_B的偏置电压提供至检测子电路310，以便进行光电检测。
在输出端V_OUT的数据读取完成，即第一电容C完成了放电之后，进入复位阶段，复位辅助子电路350的第一晶体管T1在复位辅助信号端L_RST的控制下关断，从而将第四晶体管T4和第五晶体管T5与偏置电压信号端V_B电隔离。在复位阶段，第四晶体管T4和第五晶体管T5均导通，从而将输入节点PD的电位重置为第二输入端V_R的电压。可以将第一晶体管T1的宽长比设置为小于第四晶体管T4的宽长比，这样虽然第一晶体管T1的第一极和第二极之间存在电压差，但其产生的漏电流较小，因此对于第一晶体管T1的第一极处的电位影响较小。检测子电路310的第四晶体管T4的第一极和第二极之间没有压差，无法形成漏电流，从而减小滞后。
图4是本公开另一实施例的光电检测电路的电路图。
如图4所示，光电检测电路400包括检测子电路410、存储子电路420、积分子电路430和控制子电路440。以上对于检测子电路210、存储子电路220、积分子电路230和控制子电路240的描述同样适用于检测子电路410、存储子电路420、积分子电路430和控制子电路440，本公开在此不再赘述。
如图4所示，该光电检测电路400还可以包括复位子电路460。
该复位子电路460可连接复位信号端RST、所述输入节点PD和复位电压端V_RST。 复位子电路460可以在所述复位信号端RST的信号的控制下将所述复位电压端V_RST的电位提供至所述输入节点PD，其中所述复位电压端V_RST的电位等于所述积分子电路430的第二输入端V_R的电位。
例如，该复位子电路460可以包括第二晶体管T2。所述第二晶体管T2的栅极连接所述复位信号端RST，所述第二晶体管T2的第一极连接所述复位电压端V_RST，所述第二晶体管T2的第二极连接所述输入节点PD。
通过设置复位子电路460，可以在数据读取完成后将所述复位电压端V_RST的电位提供至所述输入节点PD，从而清除掉第一电容C上的电荷。
在一些实施例中，该光电检测电路400还可以包括上述复位辅助子电路350，以进一步减小滞后。
图5是根据本公开另一实施例的光电检测电路的电路图。
如图5所示，光电检测电路500包括检测子电路510、存储子电路520、积分子电路530和控制子电路540。以上对于检测子电路210、存储子电路220、积分子电路230和控制子电路240的描述同样适用于检测子电路510、存储子电路520、积分子电路530和控制子电路540，本公开在此不再赘述。
如图5所示，该光电检测电路500还可以包括放大子电路570。
该放大子电路570连接在所述输入节点PD与所述控制子电路540之间，并且与参考电压端V_D连接。该放大子电路570可以在所述输入节点PD的电位的控制下产生在所述参考信号端V_D和所述控制子电路540之间流动的电流Ids。
例如，该放大子电路570可以包括第三晶体管T3。第三晶体管T3的栅极连接所述输入节点PD，所述第三晶体管T3的第一极连接所述参考电压端V_D，所述第三晶体管T3的第二极连接所述控制子电路540。例如第三晶体管T3的第二极连接控制子电路540中第五晶体管T5的第一极。
通过设置放大子电路570，可以将检测子电路510产生的电流放大，例如放大5-20倍，积分子电路530的第一输入端V_IN处的电流放大使得噪声信号的占比降低，从而起到降噪的作用。另外，放大子电路570的设置还可以实现输入节点PD的复位。例如在复位阶段，可以向检测电压信号端V_S施加低电平并且使偏置电压信号端V_B从偏置电压(例如-4V)切换成参考电压(例如1.4V)，从而使第四晶体管T4导通，将参考电压提供至输入节点PD，完成输入节点PD的复位。在一些实施例中，可以在光电检测电路500增加一个复位电路(例如上述复位电路460)来实现输入节点PD的复位。 在这种情况下，在复位阶段可以不改变偏置电压信号端V_B的电压。通过这种方式，可以提高输出信号的抗干扰能力。
图6是根据本公开另一实施例的光电检测电路的电路图。
如图6所示，光电检测电路600包括检测子电路610、存储子电路620、积分子电路630和控制子电路640。以上对于检测子电路210、存储子电路220、积分子电路230和控制子电路240的描述同样适用于检测子电路610、存储子电路620、积分子电路630和控制子电路640，本公开在此不再赘述。
如图6所示，该光电检测电路600还可以包括多个检测子电路，例如包括检测子电路611和检测子电路612。以上对于检测子电路210的描述同样适用于检测子电路611或检测子电路612中的任一个。
在一些实施例中，检测子电路611包括第四晶体管T4，检测子电路611的第四晶体管T4的栅极连接检测电压信号端V_S，检测子电路611的第四晶体管T4的第一极连接至偏置电压信号端V_B，检测子电路611的第四晶体管T4的第二极连接至输入节点PD。
检测子电路612也包括一个第四晶体管T4，检测子电路612的第四晶体管T4的第二极也连接至输入节点PD。
应该理解，图6中检测子电路的数量仅为一种示例，本公开中检测子电路的数量可以根据需要设置更多的检测子电路。
通过本公开实施例，设置了多个检测子电路，可以增大光电流。
以上虽然以特定的示例描述了光电检测电路，然而本公开的实施例不限于此。上述实施例可以根据需要以任何合适的方式组合以形成新的光电检测电路结构。例如，上述光电检测电路200还可以包括上述复位辅助子电路350、复位子电路460和放大子电路570中的一个或多个，并且光电检测电路200中的检测子电路220的数量可以按照如图6所示的方式来根据需要进行扩展，例如增加到两个、三个或更多个。
上述实施例中检测电路中的各个晶体管，例如第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管均为P型晶体管，例如P型TFT，然而本公开的实施例不限于此，各个晶体管可以为N型晶体管。
图7是根据本公开一实施例的光电检测电路的截面图。为了便于描述，仅示出了上述光电检测电路中的第四晶体管T4、第五晶体管T5和第一电容C。
如图7所示，在例如图2所示的光电检测电路中，检测子电路可以包括第四晶体管T4，控制子电路可以包括第五晶体管T5。第四晶体管T4和第五晶体管T5可以设置在 衬底基板701上。第四晶体管T4的第一极7104和第二极7103与所述第五晶体管T5的第一极7123和第二极7124同层设置。第四晶体管T4的第二极7103与第五晶体管T5的第一极7123电连接。所述第四晶体管T4的有源层7102与所述第五晶体管T5的有源层7122同层设置，所述第四晶体管T4的栅极7101设置在所述第四晶体管T4的有源层7102面向所述衬底基板701的一侧，所述第五晶体管T5的栅极7121设置在所述第五晶体管T5的有源层7122背离所述衬底基板701的一侧。
第四晶体管T4和第五晶体管T5背离所述衬底基板701的一侧设置有平坦层708。第一电容C的第一电极7111位于所述平坦层708背离所述衬底基板701的一侧，第一电容C的第二电极7112位于所述平坦层708面向所述衬底基板701的一侧。
在一些实施例中，衬底基板701上还设置有第一栅绝缘层703和第二栅绝缘层704，第四晶体管T4的有源层7102和第五晶体管T5的有源层7122均位于第一栅绝缘层703与衬底基板701之间。第四晶体管T4的栅极7101设置在第一栅绝缘层703面向衬底基板701的一侧。第五晶体管T5的栅极7121设置在第一栅绝缘层703与第二栅绝缘层704之间。
在一些实施例中，第二栅绝缘层704背离衬底基板701的一侧还可以设置有层间介质层705。第四晶体管T4的第一极7104和第二极7103以及第五晶体管T5的第一极7123和第二极7124可以均位于层间介质层705背离衬底基板701的一侧。第四晶体管T4的第一极7104和第二极7103通过层间介质层705、第二栅绝缘层704和第一栅绝缘层703中的过孔与有源层7101接触。第五晶体管T5的第一极7123和第二极7124通过层间介质层705、第二栅绝缘层704和第一栅绝缘层703中的过孔与有源层7122接触。
在一些实施例中，层间介质层705与平坦层708之间还可以设置有第一钝化层706和第二钝化层707。第二钝化层707位于第一钝化层706与平坦层708之间。第一电容C的第二电极7112位于第二钝化层707与第一钝化层706之间。在一些实施例中，平坦层708背离衬底基板701的一侧还可以设置有封装层709。第一电容C的第一电极7111可以位于封装层709与平坦层708之间。在一些实施例中，第一电容C的第二电极7112通过第一钝化层706中的过孔分别与第四晶体管T4的第一极7103和第五晶体管T5的第二极7123接触。
在一些实施例中，衬底基板701和第一栅绝缘层702之间还可以设有阻挡层702。
图8A是根据本公开一实施例的光电检测电路的俯视图。为了便于描述，仅示出了上述光电检测电路中的第四晶体管T4、第五晶体管T5和第一电容C。图8B是根据本 公开一实施例的光电检测电路的俯视图，其中去除了电容C以便清楚示出第五晶体管T5的结构。
如图8A和图8B所示，第四晶体管T4的栅极7101连接检测电压信号端V_S，第四晶体管T4的第一极连接偏置电压信号端V_B，第四晶体管T4的第二极连接第五晶体管T5的第一极。第五晶体管T5的栅极连接控制信号端GATE。第五晶体管T5的第一极连接第四晶体管T4的第二极。第五晶体管T5的第二极通过信号走线连接积分电路的第一输入端V_IN。第一电容C的第一电极7111连接偏置电压信号端V_S。第一电容C的第二电极7112连接输入节点PD。
虽然上述实施例中以特定的布局示出了第四晶体管、第五晶体管和第一电容，然而本公开的实施例不限于此，可以根据需要以任何其他合适的布局来排布检测电路中的各个晶体管。
图9是根据本公开另一实施例的光电检测电路的截面图。图9的截面图可以适用于例如上述光电检测电路300。如图9所示，光电检测电路还可以包括复位辅助子电路，该复位辅助子电路可以包括第一晶体管T1。为了便于描述，仅示出了第四晶体管T4、第五晶体管T5和第一晶体管T1。图9的光电检测电路中各元件的布置方式与图7类似，区别至少在于图9中还包括第一晶体管T1，为了简明起见，下面将主要对区别部分进行详细说明。
第一晶体管T1可以设置在衬底基板701上。第一晶体管T1的第一极7033和第二极7134、所述第四晶体管T4的第一极7104和第二极7103与所述第五晶体管T5的第一极7123和第二极7124可以同层设置。第一晶体管T1的有源层7132、所述第四晶体管T4的有源层7102与所述第五晶体管T5的有源层7122同层设置。第一晶体管T1的栅极7131设置在第一晶体管T1的有源层7132背离衬底基板701的一侧。第一晶体管T1的第二极7134与第四晶体管T4的第一极7104电连接。
图10是根据本公开另一实施例的光电检测电路的截面图。该截面图适用于例如上述电检测电路400。如图10所示，检测电路还可以包括复位子电路，该复位子电路460可以包括第二晶体管T2。图10的光电检测电路中各元件的布置方式与图7类似，区别至少在于图10中还包括第二晶体管T2，为了简明起见，下面将主要对区别部分进行详细说明。
第二晶体管T2可以设置在衬底基板701上。第二晶体管T2的第一极7143和第二极7144、第四晶体管T4的第一极7104和第二极7103与第五晶体管T5的第一极7123 和第二极7124可以同层设置。第二晶体管T2的有源层7122、第四晶体管T4的有源层7102与第五晶体管T5的有源层7122同层设置。第二晶体管T2的栅极7141设置在第二晶体管T2的有源层7142背离衬底基板701的一侧。
在一些实施例中，第二晶体管T2的第二极7144与第四晶体管T4的第二极7103和第五晶体管T5的第一极7123电连接，第一电容C的第二电极7112通过第一钝化层706中的过孔与第二晶体管T2的第二极7144接触。
图11是根据本公开另一实施例的光电检测电路的截面图。该截面图适用于例如上述电检测电路400。如图11所示，光电检测电路还可以包括放大子电路，该复位子电路可以包括第三晶体管T3。图11的光电检测电路中各元件的布置方式与图7类似，区别至少在于图11中还包括第三晶体管T3，为了简明起见，下面将主要对区别部分进行详细说明。
第三晶体管T3可以设置在衬底基板701上，第三晶体管T3的第一极7153和第二极7154、所述第四晶体管T4的第一极7104和第二极7103与所述第五晶体管T5的第一极7123和第二极7124可以同层设置。第三晶体管T3的有源层7152、第四晶体管T4的有源层7102与第五晶体管T5的有源层7122同层设置。第三晶体管T3的栅极7151设置在第三晶体管T3的有源层7152背离衬底基板701的一侧。
在一些实施例中，第三晶体管T3的第二极7154与第五晶体管T5的第一极7123电连接，第一电容C的第二电极7112通过第一钝化层706、层间介质层705和第二栅绝缘层704中的过孔与第三晶体管T3的栅极7151接触。
图12是根据本公开另一实施例的光电检测电路的截面图。该截面图适用于例如上述光电检测电路600中。如图12所示，光电检测电路可以包括多个检测子电路，每个检测子电路可以包括第四晶体管T4。图11的光电检测电路中各元件的布置方式与图7类似，区别至少在于图12中第四晶体管T4的数量是多个，为了简明起见，下面将主要对区别部分进行详细说明。
如图12所示，两个第四晶体管T4具有相同的层结构和电路连接。以上各个实施例中对于第四晶体管T4的描述同样适用于本实施例。每个第四晶体管T4的第二极7104均与第五晶体管T5的第一极7123和第一电容C的第二极7112电连接。
在一些实施例中，第一电容C的第二电极7112通过第一钝化层706的多个(两个)过孔分别与多个(两个)第四晶体管T4的第二极7104接触。
图13是根据本公开一实施例的像素单元的截面图。
如图13所示，该像素单元1300包括至少一个像素电路1301和上述任意实施例的光电检测电路。为了简明起见，仅示出了光电检测电路中的第四晶体管T4、第五晶体管T5和第一电容C1。
像素电路1300可以包括驱动晶体管，其中驱动晶体管可以包括栅极1311、源极1313和漏极1314。驱动晶体管还可以包括位于衬底基板701上的有源层1312，驱动晶体管的栅极1311位于所述有源层1312远离所述衬底基板701一侧。驱动晶体管还可以包括位于有源层1312与所述栅极1311之间的第一栅绝缘层703，位于所述栅极1311远离所述衬底基板701一侧的第二栅绝缘层704，位于所述第二栅绝缘层704远离所述衬底基板701一侧的层间介质层705。驱动晶体管的源极1313和漏极1314位于所述层间介质层705远离所述衬底基板701一侧。
在一些实施例中，所述像素电路还包括发光单元，所述发光单元包括阳极1315、阴极1316以及位于所述阳极1315和阴极1316之间的发光层1317。所述层间介质层705远离所述衬底基板701的一侧设置有平坦层708，所述阳极1315位于所述平坦层708远离所述衬底基板701的一侧并且穿过所述平坦层708与所述驱动晶体管的源极1313或漏极1314连接。
光电检测电路的检测子电路包括第四晶体管T4，光电检测电路的控制子电路包括第五晶体管T5。第四晶体管T4的栅极7101位于所述第一栅绝缘层703与所述衬底基板701之间，所述第四晶体管T4的第一极7104和第二极7103与所述驱动晶体管的源极1313和漏极1314中的至少之一同层设置，所述第四晶体管T4的有源层7102与所述驱动晶体管的有源层1312同层设置，所述第五晶体管T5的栅极7121与所述驱动晶体管的栅极1311同层设置，所述第五晶体管T5的第一极7124和第二极7123与所述驱动晶体管的源极1313和漏极1314中的至少之一同层设置，所述第五晶体管T5的有源层7122与所述驱动晶体管的有源层1312同层设置。
光电检测电路的存储子电路包括第一电容C，所述第一电容C的第一电极7111与发光单元的阳极1315同层设置，所述第一电容C的第二电极7112位于所述平坦层708面向所述衬底基板701的一侧。
在一些实施例中，在所述平坦层708与所述层间介质层705之间还设置有第一钝化层706以及位于所述第一钝化层706与所述平坦层708之间的第二钝化层707，其中所述驱动晶体管的源极1313和漏极1314位于所述第一钝化层706与所述层间介质层705之间，所述第一电容C的第二电极7112位于所述第二钝化层707与所述第一钝化层706 之间。
在一些实施例中，在平坦层708背离衬底基板701的一侧设有封装层709。发光单元和第一电容的第一电极7111可以设置在封装层709与平坦层708之间。
图14是根据本公开一实施例的光电检测电路的操作时序图。下面将结合上述光电检测电路200来对图14的操作时序进行说明。如图14所示，控制信号端GATE施加周期信号，向检测电压信号端V_S施加恒定电压，例如在-3V至-6V之间，向偏置电压信号端V_B施加恒定电压，例如在-4V至-10V之间。
在时段t1，控制信号端GATE处于高电平，第五晶体管T5关断，进而使输入节点PD与第一输入端V_IN电隔离。检测电压信号端V_S和偏置电压信号端V_B的电位使得第四晶体管T4处于反向导通状态，使得第四晶体管T4能够响应于光信号来产生在偏置电压信号端V_B和输入节点PD之间流动的电流。第一电容C存储第四晶体管T4产生的电荷。
在时段t2，控制信号端GATE处于低电平，使第五晶体管T5导通，进而使输入节点PD与第一输入端V_IN电连接。第五晶体管T5将输入节点PD的电位提供至第一输入端V_IN，从而使第一电容C存储的电荷被导出至后端积分子电路中的电容中，积分子电路中的运算放大器AMP基于第二输入端V_R的参考电平和第一输入端V_IN处的信号来产生积分信号并在输出端V_OUT输出。
图15是本公开另一实施例的光电检测电路的操作时序图。下面将结合上述光电检测电路300来对图15的操作时序进行说明。如图15所示，每个检测周期包括检测时段和复位时段，其中检测时段包括时段t11、t12和t13。
在时段t11，复位辅助信号端L_RST处于低电平，检测电压信号端V_S处于高电平，控制信号端GATE处于高电平。复位辅助信号端L_RST处于低电平使第一晶体管T1导通，从而将偏置电压信号端V_B的偏置电压提供至第四晶体管T4。检测电压信号端V_S和偏置电压信号端V_B的电位使第四晶体管T4处于反向导通状态，使得第四晶体管T4响应于光信号来产生电荷，进而产生在偏置电压信号端V_B和输入节点PD之间流动的电流。第一电容C存储第四晶体管T4产生的电荷。控制信号端GATE处于高电平使第五晶体管T5关断，从而使输入节点PD与积分子电路330电隔离。
在时段t12，复位辅助信号端L_RST处于高电平，使第一晶体管T1关断，第一电容C的存在使得第四晶体管T4的第一极保持在偏置电压。在这过程中，检测电压信号端V_S和偏置电压信号端V_B的电位保持不变，得第四晶体管T4继续响应于光信号 来产生电荷并存储在第一电容C中。
在时段t13，控制信号端GATE处于低电平，使第五晶体管T5导通，进而使输入节点PD与第一输入端V_IN电连接，从而将输入节点PD的电位提供至第一输入端V_IN。第一电容C存储的电荷被导出至后端积分子电路中，从而使输出端V_OUT产生输出信号。
在复位时段，复位辅助信号端L_RST处于高电平，检测电压信号端V_S处于低电平，控制信号端GATE处于低电平。复位辅助信号端L_RST处于高电平使第一晶体管T1关断，从而将第四晶体管T4和第五晶体管T5与偏置电压信号端V_B电隔离。检测电压信号端V_S处于低电平使第四晶体管T4导通，控制信号端GATE处于低电平使第五晶体管T5导通，从而将输入节点PD的电位重置为第二输入端V_R的电压。
图16是本公开另一实施例的光电检测电路的操作时序图。下面将结合上述光电检测电路400来对图15的操作时序进行说明。
在检测时段，复位信号端RST处于高电平，使第五晶体管T5关断，进而使输入节点PD与第一输入端V_IN电隔离。检测电压信号端V_S和偏置电压信号端V_B的电位使第四晶体管T4响应于光信号来产生在偏置电压信号端V_B和输入节点PD之间流动的电流。第一电容C存储第四晶体管T4产生的电荷。当控制信号端GATE的低电平到来时，第五晶体管T5导通，进而使输入节点PD与第一输入端V_IN电连接，从而将输入节点PD的电位提供至第一输入端V_IN，第一电容C存储的电荷被导出至后端积分子电路中的电容中，从而使输出端V_OUT产生低电平的输出信号。
在复位时段，复位信号端RST处于低电平，控制信号端GATE处于高电平。复位信号端RST处于低电平使第二晶体管T2导通，复位电压端V_RST与输入节点PD电连接，从而将复位电压端V_RST的电位提供至输入节点PD，以实现输入节点PD的复位。
图17是本公开另一实施例的光电检测电路的操作时序图。下面将结合上述光电检测电路500来对图16的操作时序进行说明。
在检测时段，偏置电压信号端V_B和检测电压信号端V_S的电位使第四晶体管T4响应于光信号来产生在偏置电压信号端V_B和输入节点PD之间流动的电流，第一电容C存储第四晶体管T4产生的电荷。当控制信号端GATE的低电平到来时，第五晶体管T5导通，使输入节点PD与第一输入端V_IN电连接，从而将输入节点PD的电位提供至第一输入端V_IN。第一电容C存储的电荷被导出至后端积分子电路中的电 容中，从而使输出端V_OUT产生的输出信号。
在复位时段，检测电压信号端V_S处于低电平，偏置电压信号端V_B的电位可以从检测时段的电位(例如-4V)变成参考电压，例如可以等于积分子电路的第二输入端V_R处的参考电压，即1.4V。偏置电压信号端V_B和检测电压信号端V_S的电位使得第四晶体管T4正向导通，从而将偏置电压信号端V_B的参考电压提供至输入节点PD，完成输入节点PD的复位。
在一些实施例中，上述光电检测电路600的操作时序与光电检测电路200的操作时序类似，可以参考前文记载的图14的操作时序，这里不再赘述。
图18是本公开一实施例的光电检测电路的控制方法的流程图。
该控制方法1800可以包括操作S1801至操作S1804。
在操作S1801，检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流。
在操作1802，存储子电路基于检测子电路产生的电流来进行能量存储。
在操作1803，控制子电路在控制信号端的控制下将输入节点的电位提供至积分电路的第一输入端。
在操作1804，积分子电路基于第二输入端的电位对第一输入端的信号进行积分，以产生积分信号并在输出端输出。
在一些实施例中，光电检测电路还包括复位辅助子电路，方法包括检测时段和复位时段。
在检测时段，复位辅助子电路在复位辅助信号端的控制下将检测子电路与偏置电压信号端电连接，检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，存储子电路基于检测子电路产生的电流来进行能量存储，控制子电路在控制信号端的控制下将输入节点的电位提供至积分电路的第一输入端，积分子电路基于第二输入端的电位对第一输入端的信号进行积分，以产生积分信号并在输出端输出。
在复位时段，复位辅助子电路在复位辅助信号端的控制下将检测子电路与偏置电压信号端电隔离，检测子电路在检测电压信号端的电位的控制下将偏置电压信号端与输入节点电连接，控制子电路在控制信号端的控制下将输入节点与积分电路的第一输入端电连接。
在一些实施例中，光电检测电路还包括复位子电路，方法包括检测时段和复位时段。
在检测时段，复位子电路在复位信号端的控制下将复位电压端与输入节点电隔离， 检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，存储子电路基于检测子电路产生的电流来进行能量存储，控制子电路在控制信号端的控制下将输入节点的电位提供至积分电路的第一输入端，积分子电路基于第二输入端的电位对第一输入端的信号进行积分，以产生积分信号并在输出端输出。
在复位时段，复位子电路在复位信号端的控制下将复位电压端与输入节点电连接，控制子电路在控制信号端的控制下将输入节点与积分电路的第一输入端电隔离。
在一些实施例中，光电检测电路还包括放大子电路，方法包括检测时段和复位时段。
在检测时段，检测子电路在检测电压信号端的电位的控制下响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，存储子电路基于检测子电路产生的电流来进行能量存储，放大子电路在输入节点的电位的控制下产生在参考信号端和控制子电路之间流动的电流，控制子电路在控制信号端的控制下将放大子电路产生的电流提供至积分电路的第一输入端，积分子电路基于第二输入端的电位对第一输入端的信号进行积分，以产生积分信号并在输出端输出。
在复位时段，检测子电路在检测电压信号端的电位的控制下将偏置电压信号端与输入节点电连接，其中偏置电压信号端在复位时段的电位不同于在检测阶段的电位。
应当注意的是，在以上的描述中，仅以示例的方式，示出了本公开实施例的技术方案，但并不意味着本公开实施例局限于上述步骤和结构。在可能的情形下，可以根据需要对步骤和结构进行调整和取舍。因此，某些步骤和单元并非实施本公开实施例的总体发明思想所必需的元素。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开实施例的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开实施例的范围不局限于上述特定实施例，而应由所附权利要求所限定。

Claims (22)

  1. 一种光电检测电路，包括：
    检测子电路，连接检测电压信号端、偏置电压信号端和输入节点，并且被配置为在检测电压信号端的电位的控制下响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流；
    存储子电路，连接在偏置电压信号端与输入节点之间，并且被配置为基于检测子电路产生的电流来进行能量存储；
    积分子电路，具有第一输入端、第二输入端和输出端，并且被配置为基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
    控制子电路，连接至控制信号端、输入节点和所述积分电路的第一输入端，并且被配置为在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端。
  2. 根据权利要求1所述的光电检测电路，其中，所述存储子电路包括第一电容，所述第一电容的第一电极连接至所述偏置电压信号端，所述第一电容的第二电极连接至所述输入节点。
  3. 根据权利要求1或2所述的光电检测电路，还包括：复位辅助子电路，所述检测子电路通过所述复位辅助子电路与所述偏置电压信号端连接，所述复位辅助子电路被配置为在所述复位辅助信号端的控制下在检测时段将所述检测子电路与所述偏置电压信号端电连接，在复位时段将所述检测子电路与所述偏置电压信号端电隔离。
  4. 根据权利要求3所述的光电检测电路，其中，所述复位辅助子电路包括第一晶体管，所述第一晶体管的栅极连接所述复位辅助信号端，所述第一晶体管的第一极连接所述偏置电压信号端，所述第一晶体管的第二极连接所述检测子电路。
  5. 根据权利要求1至4中任一项所述的光电检测电路，还包括：复位子电路，连接复位信号端、所述输入节点和复位电压端，并且被配置为在所述复位信号端的信号的控制下将所述复位电压端的电位提供至所述输入节点，其中所述复位电压端的电位等于所述积分子电路的第二输入端的电位。
  6. 根据权利要求5所述的光电检测电路，其中，所述复位子电路包括第二晶体管，所述第二晶体管的栅极连接所述复位信号端，所述第二晶体管的第一极连接所述复位电压端，所述第二晶体管的第二极连接所述输入节点。
  7. 根据权利要求1所述的光电检测电路，还包括放大子电路，连接在所述输入节点与所述控制子电路之间，并且与参考电压端连接，所述放大子电路被配置为在所述 输入节点的电位的控制下产生在所述参考信号端和所述控制子电路之间流动的电流。
  8. 根据权利要求7所述的光电检测电路，其中，所述放大子电路包括第三晶体管，所述第三晶体管的栅极连接所述输入节点，所述第三晶体管的第一极连接所述参考电压端，所述第三晶体管的第二极连接所述控制子电路。
  9. 根据权利要求1至8中任一项所述的光电检测电路，其中，所述检测子电路包括第四晶体管，所述第四晶体管的栅极连接所述检测电压信号端，所述第四晶体管的第一极连接所述偏置电压信号端，所述第四晶体管的第二极连接所述输入节点。
  10. 根据权利要求1至9中任一项所述的光电检测电路，包括多个所述检测子电路。
  11. 根据权利要求1至10中任一项所述的光电检测电路，其中，所述控制子电路包括第五晶体管，所述第五晶体管的栅极连接所述控制信号端，所述第五晶体管的第一极连接所述输入节点，所述第五晶体管的第二极连接所述积分电路的第一输入端。
  12. 根据权利要求1至11中任一项所述的光电检测电路，其中，所述积分子电路包括：
    运算放大器，所述运算放大器的第一输入端连接为所述积分子电路的第一输入端，所述运算放大器的第二输入端连接为所述积分子电路的第二输入端，所述运算放大器的输出端连接为所述积分子电路的输出端；
    第二电容，所述第二电容的第一电极连接所述运算放大器的第一输入端，所述第二电容的第二电极连接所述运算放大器的第二输入端。
  13. 根据权利要求1至11中任一项所述的光电检测电路，其中，所述检测子电路包括第四晶体管，所述控制子电路包括第五晶体管，所述第四晶体管和所述第五晶体管设置在衬底基板上，所述第四晶体管的第一极和第二极与所述第五晶体管的第一极和第二极同层设置，所述第四晶体管的有源层与所述第五晶体管的有源层同层设置，所述第四晶体管的栅极设置在所述第四晶体管的有源层面向所述衬底基板的一侧，所述第五晶体管的栅极设置在所述第五晶体管的有源层背离所述衬底基板的一侧。
  14. 根据权利要求13所述的光电检测电路，其中，所述第四晶体管和第五晶体管背离所述衬底基板的一侧设置有平坦层，所述第一电容的第一电极位于所述平坦层背离所述衬底基板的一侧，所述第一电容的第二电极位于所述平坦层面向所述衬底基板的一侧。
  15. 一种像素单元，包括：
    至少一个像素电路，每个像素电路被配置为基于像素电路被配置为基于数据电压 来进行发光；以及
    根据权利要求1至14中任一项所述的光电检测电路。
  16. 根据权利要求15所述的像素单元，其中，
    所述像素电路包括驱动晶体管，所述驱动晶体管包括位于衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，位于所述有源层与所述栅极之间的第一栅绝缘层，位于所述栅极远离所述衬底基板一侧的第二栅绝缘层，位于所述第二栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的源极和漏极；
    所述光电检测电路的检测子电路包括第四晶体管，所述光电检测电路的控制子电路包括第五晶体管，其中所述第四晶体管的栅极位于所述第一栅绝缘层与所述衬底基板之间，所述第四晶体管的第一极和第二极与所述驱动晶体管的源极和漏极中的至少之一同层设置，所述第四晶体管的有源层与所述驱动晶体管的有源层同层设置，所述第五晶体管的栅极与所述驱动晶体管的栅极同层设置，所述第五晶体管的第一极和第二极与所述驱动晶体管的源极和漏极中的至少之一同层设置，所述第五晶体管的有源层与所述驱动晶体管的有源层同层设置。
  17. 根据权利要求16所述的像素单元，其中，
    所述像素电路还包括发光单元，所述发光单元包括阳极、阴极以及位于所述阳极和阴极之间的发光层，其中所述层间介质层远离所述衬底基板的一侧设置有平坦层，所述阳极位于所述平坦层远离所述衬底基板的一侧并且穿过所述平坦层与所述驱动晶体管的源极或漏极连接；
    所述光电检测电路的存储子电路包括第一电容，所述第一电容的第一电极与所述阳极同层设置，所述第一电容的第二电极位于所述平坦层面向所述衬底基板的一侧。
  18. 根据权利要求17所述的像素单元，其中，在所述平坦层与所述层间介质层之间还设置有第一钝化层以及位于所述第一钝化层与所述平坦层之间的第二钝化层，其中所述驱动晶体管的源极和漏极位于所述第一钝化层与所述层间介质层之间，所述第一电容的第二电极位于所述第二钝化层与所述第一钝化层之间。
  19. 一种如权利要求1至14中任一项所述的光电检测电路的控制方法，包括：
    检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流；
    存储子电路基于检测子电路产生的电流来进行能量存储；
    控制子电路在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一 输入端；
    积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出。
  20. 根据权利要求19所述的方法，其中，所述光电检测电路还包括复位辅助子电路，所述方法包括：
    在检测时段，所述复位辅助子电路在复位辅助信号端的控制下将所述检测子电路与所述偏置电压信号端电连接，所述检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，所述存储子电路基于检测子电路产生的电流来进行能量存储，所述控制子电路在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端，所述积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
    在复位时段，所述复位辅助子电路在复位辅助信号端的控制下将所述检测子电路与所述偏置电压信号端电隔离，所述检测子电路在检测电压信号端的电位的控制下将偏置电压信号端与输入节点电连接，所述控制子电路在控制信号端的控制下将输入节点与所述积分电路的第一输入端电连接。
  21. 根据权利要求19所述的方法，其中，所述光电检测电路还包括复位子电路，所述方法包括：
    在检测时段，所述复位子电路在复位信号端的控制下将所述复位电压端与所述输入节点电隔离，所述检测子电路响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，所述存储子电路基于检测子电路产生的电流来进行能量存储，所述控制子电路在控制信号端的控制下将输入节点的电位提供至所述积分电路的第一输入端，所述积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
    在复位时段，所述复位子电路在复位信号端的控制下将所述复位电压端与所述输入节点电连接，所述控制子电路在控制信号端的控制下将输入节点与所述积分电路的第一输入端电隔离。
  22. 根据权利要求19所述的方法，其中，所述光电检测电路还包括放大子电路，所述方法包括：
    在检测时段，检测子电路在检测电压信号端的电位的控制下响应于光信号来产生在偏置电压信号端和输入节点之间流动的电流，存储子电路基于检测子电路产生的电 流来进行能量存储，放大子电路在所述输入节点的电位的控制下产生在所述参考信号端和所述控制子电路之间流动的电流，控制子电路在控制信号端的控制下将放大子电路产生的电流提供至所述积分电路的第一输入端，积分子电路基于第二输入端的电位对所述第一输入端的信号进行积分，以产生积分信号并在输出端输出；
    在复位时段，所述检测子电路在检测电压信号端的电位的控制下将偏置电压信号端与输入节点电连接，其中所述偏置电压信号端在复位时段的电位不同于在检测阶段的电位。
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