WO2023038580A2

WO2023038580A2 - Asymmetric floating gate device

Info

Publication number: WO2023038580A2
Application number: PCT/SG2022/050646
Authority: WO
Inventors: Tengyu JIN; Wei Chen
Original assignee: National University Of Singapore
Priority date: 2021-09-10
Filing date: 2022-09-09
Publication date: 2023-03-16
Also published as: WO2023038580A3

Abstract

An asymmetric floating gate (AFG) device and a method of fabricating the AFG device. The method comprises the steps of providing the source electrode; providing the drain electrode; providing the floating gate structure; and providing the channel structure comprising the 2-D material; wherein the source and drain electrodes are disposed on one side of the channel structure in first and second portions of the channel structure, respectively, and the floating gate structure is disposed on the other side of the channel structure with the first portion of the channel structure disposed between the floating gate structure and the source electrode; wherein the floating gate structure comprises a floating gate layer and a tunneling dielectric layer disposed between the floating gate layer and the channel structure; and wherein the second portion of the channel structure and the floating gate structure are disposed side-by-side on a control gate structure of the device.

Description

ASYMMETRIC FLOATING GATE DEVICE

FIELD OF INVENTION

The present invention relates broadly to an asymmetric floating gate device and to a method of fabricating an asymmetric floating gate device, and to two-dimensional reconfigurable electronics enabled thereby.

BACKGROUND

Any mention and/or discussion of prior art throughout the specification should not be considered, in any way, as an admission that this prior art is well known or forms part of common general knowledge in the field.

Reconfigurable devices with customized functionalities hold great potential in addressing the scaling limits of silicon-based field-effect transistors. The conventional reconfigurable fieldeffect transistors are limited to the applications in logic circuits, and the commonly used multigate programming strategies often lead to high power consumption and device complexity.

In more detail, silicon based field effect transistors (FETs) face the challenges in continuous scaling down to extend Moore’s Law. Devices based on emerging technologies or new materials are required to produce new breakthroughs in electronics. Unlike conventional electronic devices that operate with unchangeable characteristics, reconfigurable devices allow the reconfiguration of every elementary unit to different functions after manufacturing or even at runtime, thereby showing the potential to realize more complex systems with a lower device count. Most previous reports focused on logic circuits based on reconfigurable FETs, which exhibit tunable polarity (n-type or p-type) of the device channel by applying electrical signals at the programming gate terminal. However, constantly applied programming voltage to maintain the required functionalities of these transistors bring the issues of high power consumption, and additional programming gates lead to high device complexity. Therefore, it is important to investigate nonvolatile components that maintain the programmed states after the voltage pulses, such as ferroelectric dielectrics and charge-trapping materials. This could not only eliminate the requirement of continuous electrical bias, but also enable the implementation of reconfigurable memory devices with desirable performance.

Layered two-dimensional (2D) materials are promising emerging materials for functional electronic devices due to their exotic electronic/optoelectronic properties. More importantly, some ambipolar 2D semiconductors with a few atomic layer thickness and sizeable bandgap exhibit excellent electrostatic controllability, where the carrier concentration and carrier type can be more effectively tuned by the external electric field than those of three-dimensional semiconductors. This makes 2D semiconductors an appealing alternative for constructing electrically tunable p-n homojunctions, which are key building blocks for reconfigurable devices to demonstrate multifunctions, such as memory, logic circuit, photovoltaic cells, and photodetectors.

Embodiments of the present invention seek to address at least one of the above needs.

SUMMARY

In accordance with a first aspect of the present invention, there is provided an asymmetric floating gate (AFG) device comprising: a source electrode; a drain electrode; a floating gate structure; and a channel structure comprising a first 2-dimensional, 2-D, material; wherein the source and drain electrodes are disposed on one side of the channel structure in first and second portions of the channel structure, respectively, and the floating gate structure is disposed on the other side of the channel structure with the first portion of the channel structure disposed between the floating gate structure and the source electrode; wherein the floating gate structure comprises a floating gate layer and a tunneling dielectric layer disposed between the floating gate layer and the channel structure; and wherein the second portion of the channel structure and the floating gate structure are disposed side-by-side on a control gate structure of the device.

In accordance with a second aspect of the present invention, there is provided a method of fabricating the asymmetric floating gate device of the first aspect, comprising the steps of: providing the source electrode; providing the drain electrode; providing the floating gate structure; and providing the channel structure comprising the 2-D material; wherein the source and drain electrodes are disposed on one side of the channel structure in first and second portions of the channel structure, respectively, and the floating gate structure is disposed on the other side of the channel structure with the first portion of the channel structure disposed between the floating gate structure and the source electrode; wherein the floating gate structure comprises a floating gate layer and a tunneling dielectric layer disposed between the floating gate layer and the channel structure; and wherein the second portion of the channel structure and the floating gate structure are disposed side-by-side on a control gate structure of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A shows a schematic structure of an AFG device according to an example embodiment implemented adjacent a conventional floating gate (CFG) device.

Figure IB shows an optical image of a fabricated device according to the structure of Figure 1A.

Figure 1C shows an atomic force microscopy (AFM) image and height profile along the white dashed lines in the AFM image, of the device of Figure IB

Figure ID shows a high resolution transmission electron microscopy (HRTEM) cross-sectional image and elemental profile of the WSe2/HfO_x/HfS2 heterostructure in the device in Figure IB.

Figure 2 A shows operation diagrams of the WSe2 AFG device according to an example embodiment at off/on states and the band diagrams of the p-n/n-n⁺ junctions.

Figure 2B shows transfer characteristics of the AFG device according to an example embodiment at different Eds (-1 V and +1 V).

Figure 2C shows the on-state and off-state output curves of the AFG device according to an example embodiment.

Figure 2D shows operation diagrams of the CFG device at on/off states and the corresponding band diagrams.

Figure 2E shows transfer characteristics of the CFG device at different Eds (^_1 V and +1 V).

Figure 2F shows the on-state and off-state output curves of the CFG device. Insert: linear scale plot.

Figure 3A shows transfer characteristics (when Eds = 1 V) of the MoTe2 FET with MoTe2 channel on bare Si/SiC>2 surface.

Figure 3B shows transfer characteristics of the MoTe2 AFG device according to an example embodiment at Eds = +1 V and -1 V. The four points denoted by ‘ 1’, ‘2’, ‘3’, ‘4’ correspond with four points shown in Figures 3E and 3F.

Figure 3C shows an operation diagram and band diagram of the MoTe2 AFG device at off state according to an example embodiment when reading at E_g = +20 V after applying a +60 V E_g pulse (pulse width: 2s).

Figure 3D shows an operation diagram and band diagram of the MoTe2 AFG device at off state according to an example embodiment when reading at E_g = -20 V after applying a -60 V E_g pulse (pulse width: 2s). Figure 3E shows the output curve of the AFG device in the operation state of Figure 3C.

Figure 3F shows the output curve of the AFG device in the operation state of Figure 3D.

Figure 3G shows schematics of transfer curves of FET, CFG, and AFG devices based on electron-dominant (\VSe2), hole-dominant (predicted), and balanced ambipolar materials (MoTe2), and output curves of p-n homojunctions (off state of the devices) formed in different AFG devices according to example embodiments. The solid curves are drawn according to the experimental data (as shown in Figure 2C, Figure 3E and F), while the dashed curves are drawn according to predicted results.

Figure 4A shows the output characteristic of the p-n homojunction in the WSe2 AFG device according to an example embodiment, with the fitted curve, indicating an ideality factor of 1.25.

Figure 4B shows the schematic energy band diagram of lateral WSe2 homojunction photodiode under light illumination.

Figure 4C shows Ids-Fds curves of the p-n junction in the WSe2 AFG device according to an example embodiment under different laser powers (laser wavelength 515 nm).

Figure 4D shows the photoresponse switched on and off under increasing laser power for the WSe2 AFG device according to an example embodiment (laser wavelength 515 nm).

Figure 4E shows the enlarged photoresponse curve showing the rise time (x_r) and fall time (if) (laser wavelength 515 nm, laser power: 0.89 nW).

Figure 4F shows the short-circuit current (Z_Sc) for the WSe2 AFG device according to an example embodiment at different laser powers (laser wavelength 515 nm). Inset: Open-circuit voltage (Foe) at different laser powers.

Figure 4G shows the electrical power P_ei as a function of Fds for the WSe2 AFG device according to an example embodiment at different incident laser powers (laser wavelength 515 nm).

Figure 4H shows fill factor (FF), external quantum efficiency (EQE), and power conversion efficiency (PCE) for the WSe2 AFG device according to an example embodiment as a function of laser powers laser wavelength 515 nm).

Figure 41 shows wavelength-dependent responsivity (R) and EQE of the WSe2 AFG device according to an example embodiment.

Figure 5 A shows transfer characteristics of the WSe2 AFG device according to an example embodiment with 50 cyclic scans at Fds = +1 V.

Figure 5B shows transfer characteristics of the WSe2 AFG device according to an example embodiment with 50 cyclic scans at Fds = ^_1 V. Figure 5C shows endurance performance of the WSe2 AFG device according to an example embodiment.

Figure 5D shows four distinct current states of the WSe2 AFG device according to an example embodiment under different V_g pulses (pulse width: 500 ms) and Fds.

Figure 5E shows retention performance of the WSe2 AFG device according to an example embodiment.

Figure 6A shows a schematic illustration of a biological synapse and the artificial synapse.

Figure 6B shows excitatory postsynaptic current (EPSC) generated by single V_g pulse with different widths and amplitudes in the artificial synapse according to an example embodiment.

Figure 6C shows inhibitory postsynaptic current (IPSC) generated by single V_g pulse with different widths and amplitudes in the artificial synapse according to an example embodiment.

Figure 6D shows Extracted PPF index (( - 7i)/Zi) versus pulse time interval At, where h and h are the current values of the first and second EPSC peaks, respectively, as illustrated in the inset, in the artificial synapse according to an example embodiment. The solid line is the fitting curve based on the double exponential function.

Figure 6E shows the dependence of the EPSC amplitude on the rate of presynaptic pulses (20, 33, 40 Hz) in the artificial synapse according to an example embodiment. Ten pulses are used to stimulate the device.

Figure 6F shows the potentiation and depression processes measured in the artificial synapse according to an example embodiment at Fds = +1 V and Fds = ^_1 V.

Figure 6G shows the potentiation and depression processes measured in the artificial synapse according to an example embodiment at Fds = +1 V under dark condition and light illumination.

Figure 7 shows a schematic, cross-sectional view drawing of an asymmetric floating gate (AFG) device according to an example embodiment.

Figure 8 shows a flowchart illustrating a method of fabricating the asymmetric floating gate device according to an example embodiment.

DETAILED DESCRIPTION

An example embodiment of the present invention provides a reconfigurable WSe2 optoelectronic device that can function as photodiode, 2-bit memory, and artificial synapse in a single device, enabled by an asymmetric floating gate (AFG) that can continuously program the device into different homojunction modes. The lateral p-n homojunction formed in the AFG device according to an example embodiment exhibits high-performance self-powered photodetection, with a responsivity over 0.17 AAV and a wide detection spectral range from violet to near-infrared region. When working as 2-bit memory via the transition between n-n⁺ and p-n homojunctions, the AFG device according to an example embodiment shows four distinct conductive states with a high on/off current ratio over 10⁶, good repeatability, and long retention time. Moreover, the AFG device according to an example embodiment can work as an artificial synapse to emulate basic synaptic functions and achieve distinct potentiation/depression behaviors under the modulation of both drain-source bias and light illumination. Combining reduced processing complexity and reconfigurable functionalities, the AFG devices according to example embodiments demonstrate great potential towards high performance photoelectrical interconnected circuits.

In one example embodiment, a reconfigurable device is provided with an AFG configuration that can reversibly program the device in a nonvolatile manner. In a non-limiting example embodiment, an ambipolar 2D semiconductor WSe2 (multilayer) acts as the channel, HfS2 and its native oxide HfO_x act as the floating gate and the tunneling dielectric, respectively. It is demonstrated that a lateral homojunction in W Se2 can be modulated and retained by the voltage pulses at the control gate and stored carriers in the floating gate, respectively. This enables the device according to an example embodiment to achieve three reconfigurable functionalities: photodiode, 2-bit memory and artificial synapse. When operating as a nonvolatile p-n homojunction, the device exhibits excellent rectifying characteristics and high responsivity under light illumination. The transition between p-n and n-n⁺ junctions further makes the device a good choice as a 2-bit memory with four distinguishable resistance states that show good endurance and long retention time. Furthermore, the reconfigurable device according to an example embodiment can also work as an artificial synapse to emulate the basic synaptic functions, such as short-term plasticity (STP) and long-term plasticity (LTP). Specifically, the device according to an example embodiment exhibits light-facilitated modulation of synaptic plasticity with the help of the p-n homojunction, demonstrating promising potential to improve the learning ability of artificial synapses.

Structure of the floating gate device according to an example embodiment

Figure 1A shows the schematic structure of an AFG device according to an example embodiment (Device 1 with source, drain 1) implemented adjacent a CFG device (Device2 with source, drain2). WSe2, an ambipolar semiconductor with high carrier mobility and excellent stability is chosen as the channel material in a non-limiting example embodiment. HfS2 and its native oxide (HfO_x) act as the floating gate and the tunneling dielectric, respectively, in a nonlimiting example embodiment. Note that in the Device 1 denoted as the AFG device only about half of the area of the WSe2 channel lies on the HfO_x/HfS2 surface and the other about half lies directly on the control or bottom gate structure comprising the SiCF as the control gate dielectric layer and Si as the control gate layer, in this example embodiment. By contrast, in the CFG device2 the whole channel lies above the floating gate. It is noted that other ratios may also be used. Preferably, the length of the channel lying on the HfO_x/HfS2 surface and that lying directly on SiCh are both chosen to be at least 1 pm, to form the p-n junction.

The spatial asymmetry of the floating gate results in that only about half side of the channel can be modulated by the underlying floating gate, so that the AFG device 1 according to an example embodiment can realize reconfigurable functionalities. Figure IB shows the optical image of the AFG device 1 implemented adjacent the CFG device2. Dark and white lines mark the positions of WSe2 and HfO_x/HfS2 flakes, respectively. The channel of the AFG devicel has a total length of ~3.1 pm, with ~1.6 pm lying on the HfO_x/HfS2 flake and ~1.5 pm lying on SiCh. To determine the thickness of each layer, the atomic force microscopy (AFM) image of the device area and height profiles along the white dashed lines in the AFM image are shown in Figure 1C. The height profiles indicate a ~33.9 nm-thick HfO_x/HfS2 flake and a ~14.1 nm- thick WSe2 flake in this non-limiting example embodiment.

The integration of native oxide with 2D materials according to an example embodiment eliminates the usage of conventional insulators such as AI2O3 and hexagonal boron nitride (h- BN) fabricated by deposition or transfer methods, which bring various challenges in device compatibility and fabrication complexity. To better understand the oxidation process and the properties of the interfaces of the HfO_x/HfS2 and WSe2/HfO_x heterostructures, the cross section of the device2 was investigated by high-resolution transmission electron microscopy (HRTEM) and energy profile from energy-dispersive X-ray spectroscopy (EDS) measurements, as shown in Figure ID. One can observe atomically sharp and clean interfaces with no apparent defects or disorder at both HfO_x/HfS2 and WSe2/HfO_x heterostructures. The unconverted HfS2 retains its original lattice structure with an interlayer distance of ~0.59 nm and WSe2 shows an interlayer distance of ~0.66 nm, consistent with previous reports. However, the region between HfS2 and WSe2, with a thickness of ~14 nm, exhibits no obvious crystalline structure, indicating that HfS2 was fully oxidized into amorphous HfO_x. The elemental compositions of the heterostructure region from the EDS profile plot further confirms this conclusion, i.e., the region between crystalline HfS2 and WSe2 has a high concentration of O but low concentration of S, and the Hf concentration throughout the region of HfO_x/HfS2 is almost constant.

The potential of the native oxide HfO_x as dielectric in an electronic device was further evaluated by measuring the breakdown voltage of HfO_x using a vertical electron tunneling device with the structure of Au/HfOx (5 nm)/Ti/Au . The exponentially increasing drain-source current (/ds) under an increasing drain-source bias (Fds) can be well fitted by the Fowler- Nordheim tunneling model before breakdown. When the bias reaches the so-called breakdown point (~2.88 V), the current suddenly rises to the compliance level of the voltage source meter. The calculated breakdown field value, ~0.58 V/nm, is comparable to those of atomic layer deposited (ALD) HfO_x (~0.61 V/nm) and 2D h-BN (~1 V/nm) reported previously, indicating a good insulating property. Thus, the native oxide HfO_x can be a good candidate for dielectrics in electronic devices because its native oxide HfO_x is a “perfect” insulator, which can make it preferred over other 2-D materials. The native oxide HfO_x serves well as the tunneling dielectric, and simplifies the device fabrication process at the same time.

Working mechanism of the reconfigurable device according to an example embodiment

Both AFG device 1 according to an example embodiment and CFG device2 work based on the tunneling of carriers between the channel and the floating gate. For the writing process (gatesource bias (Fg) equals +60 V), electrons tunnel from the WSe2 channel into the HfS2 floating gate through the HfO_x layer. After removing the V_g bias, the electrons are trapped in the floating gate due to the high barrier of the tunneling dielectric. They then act as an effective negative local gate to deplete the electrons in the channel, resulting in the off state. Due to a high conductance of WSe2 FET at Pg = 0 V, the channel conductance is dominated by electrons: when electrons are depleted in the channel, this is denoted as off state; when electrons return back to the channel, this is denoted as on state. By contrast, for the erasing process (F_g = -60 V), electrons detrap from the floating gate into the channel and holes can also tunnel into the floating gate, and then the holes act as an effective positive local gate to set the channel to on state. Although the writing and erasing processes of AFG device 1 according to an example embodiment and CFG device2 are similar, the on-state and off-state characteristics are different because of the position of the floating gate.

The differences in working mechanisms of the AFG device 200 according to an example embodiment and the CFG device 250 are illustrated in Figure 2. With reference to Figure 2A, for the off state of the AFG device 200, due to the stored electrons in the floating gate 202, the channel 204a above the floating gate 202 is turned into hole-rich region (p-type), while the channel 204b on the left is electron-rich region (n-type), due to the observed electron-dominant behavior for WSe2 FET. The two regions 204a, b then form a p-n homojunction. In comparison, the CFG device 250 reaches the off state simply because of the depletion of its majority carriers (electrons) in the channel 254 under the negative local gate 252, see Figure 2D. One advantage of the AFG device 200 is that it has a much lower off-state current when Eds is positive, because of the reversely biased p-n junction. However, the CFG device 250 may suffer from a high off-state current because electrons in the floating gate 252 will further induce holes and WSe2 has relatively better hole transport behavior than n-type semiconductors. For the on state of the AFG device 200, the stored holes in the floating gate 202 turn the channel 204a above into electron-rich region (n⁺ region), see Figure 2A. It then forms a n-n⁺ junction with the left unaffected region 204b. The n-n⁺ junction induces a small barrier (Fb) for electrons transporting from the right to the left. For the CFG device 250, the on state is obtained mainly by releasing trapped electrons back into the channel 254, see Figure 2D.

The transfer and output curves of the AFG device according to an example embodiment and the CFG device confirm the aforementioned mechanism. As shown in Figure 2B, the AFG device according to an example embodiment exhibits two distinctly different transfer characteristics as Fds varies from -1 V to +1 V, due to the AFG induced homojunctions in the device. Accordingly, the off state of the AFG device exhibits typical I-V curve 209 of a diode, and the on state I-V curve 208 shows asymmetry due to the existence of Vb (Figure 2C) (Note that as shown in Figure 2A, the drain side is n-type and the source side is p-/n⁺- type. As a result, for the p-n junction, the diode is reversely biased when Fds is positive, and forward biased when Fds is negative; for the n-n⁺ junction, the electron transport should overcome V when Fds is positive, leading to a lower current than the negative Fds case.). The transfer (Figure 2E) and output (Figure 2F) curves 257, 256 of the CFG device are apparently different from those of the AFG device according to an example embodiment, as the transfer curves are independent of Fds bias, and the output curves are both symmetric and nearly linearly dependent on the bias voltage. It is noted that the AFG device configuration according to an example embodiment was also applied to another 2D ambipolar semiconductor, MoTe2, according to another example embodiment. Interestingly, two different p-n homojunctions with opposite direction when reading at V_g = +20 V/-20 V after applying a +60 V/-60 V V_g pulse, respectively, were observed, due to the balanced electron- and hole-transport in the MoTe2 channel (Figure 3A). First, two symmetric transfer curves for the MoTe2 AFG device 272 are obtained at Ids = +1 V and - I V (Figure 3B). Then, when read at V_g = +20 V/-20 V after applying a +60 V/-60 V V_g pulse, respectively, two output curves 274, 276 are obtained (Figures 3E and F), with the four points denoted by ‘ 1 ’, ‘2’, ‘3’, ‘4’ in Figure 3B corresponding to the four points in Figures 3E and F.

The two different output curves 274, 276 indicate that different p-n homojunctions with opposite direction can be achieved in the MoTe2 AFG device according to an example embodiment. When reading at V_g = +20 V after applying a +60 V V_g pulse (Figure 3C), electrons are induced by positive V_g at the left region, while holes are induced by electrons stored in the floating gate 270 at the right region, thus a p-n junction forms and it is reversely biased when Eds is positive. In contrast, when reading at V_g = -20 V after applying a -60 V V_g pulse (Figure 3D), holes are induced by negative V_g at the left region, while electrons are induced by holes stored in the floating gate at the right region, thus a p-n junction with an opposite direction forms. Due to the balanced electron- and hole-transport in MoTe2, the transport behavior of the whole channel is affected by the applied reading gate bias and the trapped carriers in the floating gate simultaneously. As a result, it is hard to achieve significant n-n⁺ or p-p⁺ junctions. This is why points ‘5-8’ in Figure 3B have almost the same value of current. Meanwhile, the MoTe2 device according to an example embodiment still has both on state and off state. When reading at V_g = +20 V, a positive V_g pulse (prior to reading at Vg = +20V) leads to off state (points ‘ 1’,’2’ in Figure 3E) while a negative V_g pulse (prior to reading at Vg = +20V) leads to on state (points ‘5’, ’6’ in Figure B). By contrast, when reading at V_g = -20 V, a positive V_g pulse (prior to reading at Vg = -20V) leads to on state (points ‘7’, ’8’ in Figure 3B) while a negative V_g pulse (prior to reading at Vg = - 20V) leads to off state (points ‘3’, ’4’ in Figure 3B).

It is expected that the AFG device configuration according to example embodiments is also appliable to other ambipolar 2-D materials whose conductance is dominated by holes, such as black phosphorus (BP). In this case, the device would still have both on state and off state when reading at zero V_g bias, just like WSe2 device. For on state, the electrons in the floating gate set the BP region above the floating gate to p⁺ type, and the unaffected BP region remains p type, resulting in a p-p⁺ junction. For off state, the holes in the floating gate set the BP region above the floating gate to n type, and the unaffected BP region remains p type, resulting in a p-n junction.

The results illustrate that the AFG device configuration according to example embodiments is applicable to 2D ambipolar semiconductor in achieving nonvolatile programmable homojunctions. Figure 3 G shows a summary and comparison of the schematic transfer and off- state output curves for an FET device and an CFG device, and for the AFG devices according to example embodiments, including based on the measured electron dominant AFG device (WSe2), the measured balanced AFG device (MoTe2) and based on predictions for a hole dominant AFG device according to another example embodiment. Indicated by the circles in Figure 3G are distinct conductive states in the AFG devices according to example embodiments, which may be used in device applications as will be described in more detail below.

Photodiode according to an example embodiment

The typical diode-like I-V curve 209 of the WSe2 AFG device according to an example embodiment at off state (Figure 2C) inspires to explore the potential of the AFG device according to an example embodiment in self-powered photodetection, i.e. no Ids bias is needed during the photodetection, after setting it to off state. The performance of the p-n homojunction was first evaluated by fitting the I-V curve 209 with the Shockley diode equation including a series resistance (P_s):

where fe, e, T, W, Io, Rs, and n are the Boltzmann constant, electron charge, temperature, Lambert W function, reverse saturation current, series resistance, and the ideal factor, respectively. Figure 4A shows both linear and semilogarithmic plots of the I-V curve in the off- state and the fitted result, where an ideality factor of 1.25 and a series resistance of 0.42 M are obtained. The extracted ideality factor is closer to 1 than to 2, implying that the transport in the p-n junction is dominated by diffusion process of majority carrier rather than carrier recombination via trap states within the band gap. It is worth noting that the highest rectification ratio (Uds(fds = ^_1 V)/7ds(Ids = 1 V)|) is up to 1.6 * 10⁵, and the series resistance is smaller compared with previous work, indicating that the device according to an example embodiment possesses a high-quality p-n junction for efficient photodetection. It is noted that the homojunction shows a long retention time by maintaining a high rectification ratio over 5 x 10⁴ after 3600s.

Figure 4B shows the schematic energy band diagram of lateral WSe2 homojunction photodiode under light illumination, according to an example embodiment.

The self-powered photodiode according to an example embodiment operates based on the photovoltaic effect: photogenerated electrons and holes are separated by the built-in electric field in the p-n homojunction, then accumulate at drain D and source S, respectively, to form electromotive force. The optoelectronic properties of the WSe2 p-n homojunction were first explored under the illumination of a laser beam at a fixed wavelength of 515 nm but varying the power density (Pd). The I-V curves shift upwards with increasing incident laser power (Pin, given by Pin = Pd ^x A, where A should be the total area of the homojunction (Figure 4C). For simplification, the value of the channel area was used as A. It is determined to be -21.1 pm² from Figure 1C, with an obvious photoresponse observed even when Pin is as low as 0.16 nW (Figure 4C), revealing the high sensitivity. Figure 4D shows the photoresponse switching dynamics under increasing laser powers at Fds = 0 V. The photocurrent was generated immediately with the light turned on and rapidly disappeared with the light turned off under every laser power. The enlarged photoresponse curve in Figure 4E further indicates good switching behaviors of the device according to an example embodiment, with the rise time (r_r) and fall time (rr) determined to be as short as 4.7 and 2.3 ms, respectively, where r_r and Tf are defined as the time for the photocurrent to rise from 10% to 90% and fall from 90% to 10% of the peak, respectively.

The relationship between short circuit current (/_Sc) and in extracted from Figure 4C is shown in Figure 4F. The experimental data are fitted according to the power-law relationship I_sc = P“, where a equals 1 for an ideal p-n junction photodiode with photocurrent depending linearly on the illumination power density. A near-unity exponent value of 1.002 was obtained for the device according to an example embodiment, implying that the photocurrent shows a good linear behavior upon altering the irradiation power density over 5 orders of magnitude from 0.16 nW to 11.39 pW. This corresponds to a linear dynamic range (LDR) of at least 97 dB according to:

sat and Plow are the light intensity values from which the photocurrent begins to deviate from linearity. Clearly, the large LDR of the WSe2 homojunction represents a significant advantage for practical application in the future. On other hand, the open circuit voltage (Foe) initially increases with the larger Pin but tends to be saturated to around 0.56 V and then declines with a further increase in Pin (Inset in Figure 4F). The decline of Foe is attributed to the high Pin induced temperature rise of the device, as reported in previous works for solar cells. The responsivity (P) of the photodetector follows the relationship of R = Isc/Pin. Since I_sc depends linearly on Pin, R maintains an almost constant value of -0.17 A/W with different Pin. This value is outstanding compared with other 2D materials based homojunction devices. Specific detectivity (£>*), which represents the ability in weak signal detection, is another key parameter of photodetectors. Assuming the dark current dominates the photodetector noise, D* can be given by:

where A is the effective area and e is the electronic charge. A value of -6.77 x io¹⁰ Jones irrespective to the light power is obtained for the WSe2 p-n homojunction, which is close to the commercially available silicon and InGaAs based photodiodes (£>* ~ 10¹² Jones).

Photo-generated output electrical power (P_ei) according to the equation P_ei = |7ds ^x Fds I, increases with increased Pin, as displayed in Figure 4G. Figure 4H demonstrates three important parameters for the photodiode according to an example embodiment as a function of the light power: fill factor (FF), external quantum efficiency (EQE), and power conversion efficiency (PCE). EQE is given by EQE = Rhde/.. where h is Planck’s constant, c the speed of light, and 2 is the light wavelength; FF is expressed as FF = P_ei,MAx/( >c ^x Pc); and PCE is defined as PCE = P_ei,MAx/Pin. A maximum EQE of -51%, FF -67% of and PCE of -5.62% can be obtained for the p-n homojunction, which are superior to the values for most reported 2D p-n homojunctions. The decrease in PCE for weak light intensities is due to the exponential power dependence of Foe, and that for strong light intensities is attributed to the high temperature induced Foe decline.

The wavelength-dependent responsivity and EQE of the homojunction were further tested, as shown in Figure 41. The homojunction demonstrates a wide detection spectral range from violet (405 nm) to near-infrared region (the cutoff near 1100 nm) and maintains high responsivity over 100 mA/W for all the wavelengths. The WSe2 AFG device according to an example embodiment has comparable or better performance compared with the state-of-the-art works in rectification ratio, ideality factor, R, D*, and response time. These advantages together with wide detection spectral range that was rarely investigated in previous works, suggest that the AFG device according to an example embodiment is promising for self-powered weak signal photodetection.

It is noted that because the MoTe2 device according to an example embodiment also shows typical diode-like I-V curves at off state (Figures 3E and F), and the bandgap is suitable (-1.01 eV for multilayer) the MoTe2 device can also be used as self-powered photodiode according to an example embodiment.

2-bit nonvolatile memory according to an example embodiment

Multi -bit memory has shown great potential in increasing the storage density and reducing the integration complexity. In principle, each P-bit memory (P > 2) single unit has 2¹' distinguishable states. For the same storage capacity the required device area will scale with 1/p compared with 2-state memory.

As aforementioned, the WSe2 AFG device according to an example embodiment can be effectively reconfigured between the n-n⁺ junction (on state) and the p-n junction (off state); both the on state and off state also possess two different conductive states for Fds = +1 V and -1 V (Figure 2B). Therefore, the WSe2 AFG device according to an example embodiment has four distinct conductive states in total. This makes it a good choice for a 2-bit memory. By contrast, the CFG device only possesses two conductive states in total because of the symmetric output characteristics with Fds (Figure 2F). The four conductive states of the AFG device according to an example embodiment can also be validated from transfer characteristics shown in Figures 5A and B. The device shows two distinctly different transfer characteristics as Fds varies from +1 V (Figure 5A) to -1 V (Figure 5B), resulting in four conductive states (indicated as circles in Figures 5A and B) at the reading process (Fg = 0 V). The two transfer characteristics exhibit negligible changes in 50 repeated sweeping cycles, suggesting a good device operation stability.

To further investigate the performance of the 2-bit memory according to an example embodiment, its dynamic characteristics were studied (Figure 5C). The detailed switch between the four states is shown as a function of time in the enlarged portion shown in Figure 5D. At Fds = +1 V (see signal curve 510), a positive pulse (+60 V, 500 ms) was applied for setting the device to the off state, followed by a negative pulse (-60 V, 500 ms) to set the device to the on state, see signal curve 512. The same process was carried out at Pds = -1 V (see signal curvea 510, 512), resulting in another two states. As indicated in Figure 5D, the four different states can be denoted as 00, 01, 10, and 11 states, respectively. The highest on/off ratio ( n/ oo) of the 2-bit memory according to an example embodiment exceeds 10⁶, and every two states are distinguishable to each other. Figure 5C demonstrates the reliable endurance cycles of these four states. All the states stay almost unchanged after over 220 cycles and the hi/Ioo ratio maintains ~10⁶ during this operation. The retention performance of the four states was also tested, as shown in Figure 4F. The current states were read after applying a -60 V or +60 V V_g pulse (pulse width: 500 ms). During the reading process, keep V_g =0 V. The data integrity was not compromised as the high In/ho ratio was maintained even after 2000 s, see Figure 5E. Highly distinguishable states, good endurance in dynamic operation, and long retention time reveal the excellent performance of the 2-bit memory according to an example embodiment.

It should be noted that some previously reported multibit memories achieve multi-states by modulating the pulse width and amplitude to change the amount of trapped carriers in the floating gate. This method makes it hard to get stable and independent conductive states, and to easily achieve direct transition from one state to another. In contrast, in the device according to an example embodiment, multi-states are realized by switching the homojunction modes and tuning the polarity of Eds, instead of changing the amount of trapped carriers in the floating gate. The 00, 01, 10, and 11 states correspond to the conditions of reversed bias of the p-n junction, forward bias of the p-n junction, reversed bias of the n-n+ junction, and forward bias of the n-n⁺ junction, respectively, which are independent of each other. Therefore, the switch between them is direct and robust.

It is also noted that it is possible to achieve memory with more than 2 states, for example with a MoTe2 device according to an example embodiment. As Figure 3B shows, when reading at V_g = +20 V or -20 V, and in combination with changing between Eds = +/-1 V, at least 3 distinguishable states can be achieved for each of Eg = +20 V and -20 V. It is noted that the n- n+ or p-p+ junction in the MoTe2 device is not strong enough (compare points 5/6 and 7/8), so the on state-current doesn’t show apparent difference with different Ids polarity, see also Figure 3B, and therefor 3 distinguishable states for each of Eg = +20 V and -20 V are considered to be achievable, not 4, namely points 1, 2, 5/6 at Eg = +20 V, and points 3, 4, 7/8 for Eg = -20 V).

Artificial synapse according to an example embodiment

The nonvolatility of the AFG device configuration according to an example embodiment possesses the essential characteristics to emulate an artificial synapse, which is promising in the realization of complex learning and flexible plasticity. Artificial synapses that mimic the biological synaptic functions are considered as building blocks for electrically driven neuromorphic computing systems that has the potential to address the challenges in traditional FET-based computing systems at the architectural level. As shown in Figure 6A, biological synapses 600 connecting the presynaptic and postsynaptic neurons are the functional units to deliver information from presynaptic to postsynaptic neurons by inducing a postsynaptic current (PSC) in the postsynaptic neuron. Similarly, the artificial synapse 602 according to an example embodiment can mimic the generation of PSC by the change of /ds after receiving the stimuli pulse from the gate terminal 604 (Pg), with the conductance of the channel 606 reflecting the synaptic weight. The change of synaptic weight can be classified into short-term plasticity (STP) and long-term plasticity (LTP) depending on the retention time. The former lasts on a time scale of seconds, while the latter lasts from minutes to hours. Determined by the increase or decrease of the synaptic weight, the PSC is further assigned as excitatory PSC (EPSC) or inhibitory PSC (IPSC). According to an example embodiment, for EPSC, the WSe2 AFG device is set at off state, and working at Eds=+1 V, while for IPSC, the WSe2 device is set at on state, and working at Ed_S=+l V.

EPSC and IPSC were investigated by applying single negative/positive presynaptic E_g pulses with different widths and amplitudes to simulate STP (keeping Eds = +1 V), as shown in Figure 6B, C. As the pulse duration increases from 100 ms to 2 s (Figure 6B, amplitude fixed at -50 V), or the amplitude increasing from -35 to -60 V (Figure 6C, width fixed at 1 ms), the peak value of EPSC becomes significantly enhanced and shows an increasingly longer decay time. Similarly, the IPSC value decreases significantly and experiences a longer time to return to the original state with the increased pulse width and amplitude. These results reveal that the potentiation and depression of the synaptic weight update can be realized by modulating the polarity, amplitude, and width of the E_g pulse. Also, Figure 6D shows the EPSC induced paired pulse facilitation (PPF) characteristics of STP (keeping Eds = +1 V, pulse width fixed at 20 ms, amplitude fixed at -50 V). The PPF index is defined by (h ~ I\)/h, where h and h. are the peak values of EPSC after the first and second pulses, respectively. The relationship between the PPF index and the time interval (At) between the two pulses is given by:

PPF index

Where n, T2 are two relaxation time constants. The PPF index gradually decreases from ~90% to ~8% with the increasing At, and the well fitted PPF index curve in Figure 6D determines n = 5 ms and T2 = 119 ms, matching well with those of a biological synapse reported previously. LTP behavior of the device according to an example embodiment was then investigated by stimulating with multiple pulses. Figure 6E depicts the spike rating-dependent plasticity (SRDP), where the EPSC gain is proportional to the pulse frequency (keeping Eds = +1 V, pulse width fixed at 20 ms, amplitude fixed at -50 V). For the relatively high-frequency stimulation (40 Hz), it shows a strong excitatory effect with higher EPSC peak and retained value after decay, but for the relatively low-frequency pulse input (20 Hz), the excitatory effect is weak.

Long-term potentiation and depression with linear and symmetric synaptic weight update are crucial for achieving high learning accuracy in artificial neural network (ANN) for neuromorphic computing. The potentiation/depression of the synaptic device according to an example embodiment was investigated by applying 50 identical negative/positive V_g pulses (pulse amplitude: -20 V/+15 V, pulse width: 20 ms, time interval: 40 ms) under both Eds = +1 V and Eds = -1 V cases. As distinctly different transfer characteristics appear for Eds = +1 V and Eds = -1 V cases in Figures 5A, B, different potentiation/depression behavior are expected for these two cases. As shown in Figure 6F, a significant increase in the mean value of conductance (G, G = PSC/Eds) can be achieved in the Eds = -1 V case, corresponding to a higher off-state current for the AFG device according to an example embodiment. Meanwhile, the low mean PSC for the Fds = +1 V case is due to a low off-state current of the AFG device according to an example embodiment. Since a strong photoresponse has been observed when the AFG device according to an example embodiment is at off state (Figure 4), it is possible for the artificial synapse according to an example embodiment to be stimulated by optical and electrical stimuli simultaneously. In Figure 5G, the light-facilitated potentiation/depression behaviors for Ids = +1 V case were investigated. Under constant light illumination (515 nm laser, 90 mW/cm²), both potentiation and depression processes show significantly higher G value accompanied with better linearity and symmetry. The linearity and symmetry was then quantitatively analyzed by fitting the experimental data with equations:

where A_p and Ad represent nonlinearity (A) for potentiation and depression processes, respectively, and G(n) is the channel conductance value after the n^th excitatory or inhibitory pulse. Linearity of potentiation/depression is better when A_p and Ad values are close to 0. A_p and Ai for the light-facilitated potentiation/depression case are -0.17 and 2.21, respectively, which are much closer to 0 than those for the dark case (-0.91 and 3.41), indicating higher linearity characteristics. The asymmetric ratio (A) is defined by the following equation:

50. (7) where A should be zero for an ideal symmetric case. The calculated A value for the light on case (0.37) is much lower than the light off case (0.66). The improved linearity and symmetry for the light-facilitated potentiation/depression reveal the important role of light in achieving high-performance synaptic weight update, making light-facilitated artificial synapse according to an example embodiment a promising candidate for high-accuracy neuromorphic computing.

It is noted that it is also possible to achieve artificial synapse with a MoTe2 device according to an example embodiment, reading at Fg = +20 V, Fds = +1 V, or reading at Fg = -20 V, Fds = -1 V.

As described in the example embodiments above, reconfigurable functionalities including photodiode, 2-bit memory, and artificial synapses have been realized in a single AFG device according to an example embodiment. The device channel in the WSe2 AFG device according to an example embodiment can be reversibly programmed into p-n or n-n⁺ homojunction and retain for a long time by the trapped carriers in the AFG. By setting the WSe2 AFG device to p-n homojunction, it enables high performance photodetection, with a high LDR of 97 dB, a high responsivity over 0.17 A/W, and a wide detection spectral range from violet to nearinfrared region. A 2-bit memory with four distinct conductive states and high on/off ratio over 10⁶ has been demonstrated by dynamically tuning the carrier type in the floating gate and the bias polarity at the drain terminal, in the WSe2 AFG device according to an example embodiment. Furthermore, the AFG device according to an example embodiment can simulate synaptic behaviors of STP and LTP, and achieve reconfigurable potentiation/depression behavior under the modulation of both ds bias and light illumination. The example embodiments open a route to 2D devices in various embodiments of the present invention that can be dynamically programmed or erased, and stably operated with distinct functions, revealing the great potential of the AFG device according to example embodiment in creating advanced sensors and processors and with simplified circuits.

Figure 7 shows a schematic, cross-sectional view drawing of an asymmetric floating gate (AFG) device 700 according to an example embodiment. The device comprises a source electrode 702; a drain electrode 704; a floating gate structure 706; and a channel structure 708 comprising a first 2-dimensional, 2-D, material; wherein the source and drain electrodes 702, 704 are disposed on one side of the channel structure 708 on first and second portions 710, 712 of the channel structure 708, respectively, and the floating gate structure 706 is disposed on the other side of the channel structure 708 with the first portion 710 of the channel structure 708 disposed between the floating gate structure 706 and the source electrode 702; wherein the floating gate structure 706 comprises a floating gate layer 714 and a tunneling dielectric layer 716 disposed between the floating gate layer 714 and the channel structure 708; and wherein the second portion 712 of the channel structure 708 and the floating gate structure 706 are disposed side-by-side on a control gate structure 718 of the device 700.

The control gate structure 718 may comprise a control gate layer 720 and a control gate dielectric layer 722.

The floating gate structure 706 may comprise a second 2-D material. The tunneling dielectric layer 716 may comprise a native oxide layer on the second 2-D material as the floating gate layer 714.

The first 2-D material may comprise WSe2 or MoTe2, black phosphorus or other ambipolar 2- D materials.

The second 2-D material may comprise HfS2.

The device 700 may be re-configurable.

The device 700 may be re-configurable between first and second states based on a voltage pulse applied to the floating gate structure 706 for configuration.

The first state may comprise the channel structure 708 being configured as a p-n junction formed by the first and second portions 710, 712 of the channel structure 708 and the second state may comprise the channel structure 708 being configured as a n-n⁺ junction formed by the first and second portions 710, 712 of the channel structure 708. The first and second states may comprise two p-n junctions with opposite directions. The first state may comprise the channel structure 708 being configured as a p-n junction having a first direction and formed by the first and second portions 710, 712 of the channel structure 708 and the second state may comprise the channel structure 708 being configured as a p-n junction having a second direction opposite to the first state and formed by the first and second portions 710, 712 of the channel structure 708.

The first and second states may be retainable after application of the voltage pulse.

The device 700 may be re-configurable between different sub-states in both the first and the second state based on a voltage applied between the source and drain electrodes 702, 704. The different sub-states may be characterized by different conductivities of the device 700.

The device 700 may be configurable as a self-powered photodiode.

The device 700 may be configurable as a nonvolatile memory.

The device 700 may be configurable as an artificial synapse. Synaptic weights may be configurable by gate voltage pulses of different duration and/or amplitude applied to the floating gate structure 706.

Figure 8 shows a flowchart 800 illustrating a method of fabricating the asymmetric floating gate device according to an example embodiment; at step 802, the source electrode is provided. At step 804, the drain electrode is provided; at step 806, the floating gate structure is provided; at step 808, the channel structure comprising the 2-D material is provided; wherein the source and drain electrodes are disposed on one side of the channel structure in first and second portions of the channel structure, respectively, and the floating gate structure is disposed on the other side of the channel structure with the first portion of the channel structure disposed between the floating gate structure and the source electrode; wherein the floating gate structure 706 comprises a floating gate layer and a tunneling dielectric layer disposed between the floating gate layer and the channel structure; and wherein the second portion of the channel structure and the floating gate structure are disposed side-by-side on a control gate structure of the device.

Methodology

Sample Characterization.

AFM characterization were performed using AFM Bruker Fastscan. The cross-section samples were prepared using dual beam focused ion beam (FIB) system (FEI Helios Nanolab 450S). TEM characterization was performed using FEI Titan 80-300 TEM system operating at 200 kV. STEM-HAADF and EDS analyses were performed on Tecnai 20F, which is equipped with an Oxford EDX detector and a Gatan Imaging Filter (GIF). AFG Device Fabrication according to an example embodiment

HfS2 flakes were mechanically exfoliated from bulk crystals (HQ graphene) by using Scotch tape and transferred onto a degenerately p-doped Si wafer with 300 nm oxides. The flake was then treated with O2 plasma (power of 20 W, flow rate of 20 seem) for 10 minutes in a vacuum chamber (~10^-5 mbar) to form a ~14 nm-thick HfO_x layer using Vita-Mini RIE system. For the preparation of stacked structures, multilayer WSe2 flake were then exfoliated on polydimethylsiloxane (PDMS) and sequentially transferred onto HfO_x/HfS2 to form the vertically stacked WSe2/HfO_x/HfS2 structure. Photoresist poly(m ethyl methacrylate) (PMMA) was spin-coated onto the sample. The source and drain electrodes were precisely patterned on the flake using the conventional e-beam lithography technique, followed by thermal evaporation of Ti (5 nm) and Au (60 nm) as the metal contacts. After liftoff, the as-made devices were wire bonded onto chip carriers and loaded in a home-made vacuum system for in situ electrical measurements. The MoTe2 based AFG device follows the same fabrication method except different channel flake.

Photoelectrical and electrical Characterization

The devices were characterized in a high vacuum chamber (~10^-7 mbar). Four laser beams (638, 515, 473, 405 nm) and an exon light source configured with a monochromator were used to illuminate the device. The light intensity was calibrated by THORLABS GmbH (PM 100A) power meter. The electrical measurements were conducted by using an Agilent 2912A source measure unit.

Embodiments of the present invention can have one or more of the following features and associated benefits/advantages:

Aspects of the systems and methods described herein, such as the control of the AFG device and the processing of its associated signals, may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits (ASICs). Some other possibilities for implementing aspects of the system include: microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc. Furthermore, aspects of the system may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies like complementary metal-oxide semiconductor (CMOS), bipolar technologies like emitter- coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal- conjugated polymer-metal structures), mixed analog and digital, etc.

The various functions or processes disclosed herein may be described as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. When received into any of a variety of circuitry (e.g. a computer), such data and/or instruction may be processed by a processing entity (e.g., one or more processors).

The above description of illustrated embodiments of the systems and methods is not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed. While specific embodiments of, and examples for, the systems components and methods are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the systems, components and methods, as those skilled in the relevant art will recognize. The teachings of the systems and methods provided herein can be applied to other processing systems and methods, not only for the systems and methods described above.

It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive. Also, the invention includes any combination of features described for different embodiments, including in the summary section, even if the feature or combination of features is not explicitly specified in the claims or the detailed description of the present embodiments.

In general, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the systems and methods are not limited by the disclosure, but instead the scope of the systems and methods is to be determined entirely by the claims.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words "herein," "hereunder," "above," "below," and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word "or" is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

Claims

1. An asymmetric floating gate (AFG) device comprising: a source electrode; a drain electrode; a floating gate structure; and a channel structure comprising a first 2-dimensional, 2-D, material; wherein the source and drain electrodes are disposed on one side of the channel structure in first and second portions of the channel structure, respectively, and the floating gate structure is disposed on the other side of the channel structure with the first portion of the channel structure disposed between the floating gate structure and the source electrode; wherein the floating gate structure comprises a floating gate layer and a tunneling dielectric layer disposed between the floating gate layer and the channel structure; and wherein the second portion of the channel structure and the floating gate structure are disposed side-by-side on a control gate structure of the device.

2. The device of claim 1, wherein the floating gate structure comprises a second 2-D material.

3. The device of claim 2, wherein the tunneling dielectric layer comprises a native oxide layer on the second 2-D material as the floating gate layer.

4. The device of any one of the preceding claims, wherein the first 2-D material comprises WSe2 or MoTe2, black phosphorus or other ambipolar 2-D materials.

5. The device of any one of the preceding claims, wherein the second 2-D material comprises Hflk.

6. The device of any one of the preceding claims, wherein the device is re-configurable.

7. The device of claim 6, the device being re-configurable between first and second states based on a voltage pulse applied to the floating gate structure for configuration.

8. The device of claim 7, wherein the first state comprises the channel structure being configured as a p-n junction formed by the first and second portions of the channel structure and the second state comprises the channel structure being configured as a n-n⁺ junction formed by the first and second portions of the channel structure.

9. The device of claims 6 or 7, wherein the first and second states comprise two p-n junctions with opposite directions.

10. The device of claim 9, wherein the first state comprises the channel structure being configured as a p-n junction having a first direction and formed by the first and second portions of the channel structure and the second state comprises the channel structure being configured as a p-n junction having a second direction opposite to the first state and formed by the first and second portions of the channel structure.

11. The device of any one of claims 7 to 10, wherein the first and second states are retainable after application of the voltage pulse.

12. The device of any one of claims 7 to 11, the device being re-configurable between different sub-states in both the first and the second state based on a voltage applied between the source and drain electrodes.

13. The device of claim 12, wherein the different sub-states are characterized by different conductivities of the device.

14. The device of any one of the preceding claims, wherein the device is configurable as a self-powered photodiode.

15. The device of any one of the preceding claims, wherein the device is configurable as a nonvolatile memory.

16. The device of any one of the preceding claims, wherein the device is configurable as an artificial synapse.

17. The device of claim 16, wherein synaptic weights are configurable by gate voltage pulses of different duration and/or amplitude applied to the floating gate structure.

18. A method of fabricating the asymmetric floating gate device of any one of the preceding claims, comprising the steps of: providing the source electrode; providing the drain electrode; providing the floating gate structure; and providing the channel structure comprising the 2-D material; wherein the source and drain electrodes are disposed on one side of the channel structure in first and second portions of the channel structure, respectively, and the floating gate structure is disposed on the other side of the channel structure with the first portion of the channel structure disposed between the floating gate structure and the source electrode; wherein the floating gate structure comprises a floating gate layer and a tunneling dielectric layer disposed between the floating gate layer and the channel structure; and wherein the second portion of the channel structure and the floating gate structure are disposed side-by-side on a control gate structure of the device.