WO2023037414A1 - Control device - Google Patents

Control device Download PDF

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Publication number
WO2023037414A1
WO2023037414A1 PCT/JP2021/032866 JP2021032866W WO2023037414A1 WO 2023037414 A1 WO2023037414 A1 WO 2023037414A1 JP 2021032866 W JP2021032866 W JP 2021032866W WO 2023037414 A1 WO2023037414 A1 WO 2023037414A1
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Prior art keywords
access frequency
shared variable
shared
unit
access
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PCT/JP2021/032866
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French (fr)
Japanese (ja)
Inventor
拓哉 坂上
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ファナック株式会社
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Priority to PCT/JP2021/032866 priority Critical patent/WO2023037414A1/en
Publication of WO2023037414A1 publication Critical patent/WO2023037414A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Definitions

  • the present invention relates to a control device.
  • FIG. 14 is a diagram illustrating an example of shared variables linked between applications.
  • the control device C1 has, for example, a plurality of processor modules PM1, PM2, PM3, etc., and the plurality of processor modules PM1, PM2, PM3, etc. are connected via a bus (or network).
  • the processor module PM1 has a CPU1A and a memory M1
  • the processor module PM2 has a CPU2A and a memory M2
  • the processor module PM3 has a CPU3A and a memory M3.
  • the CPU 1A then executes the application AP1 and accesses the shared variable x stored in the memory M1.
  • the CPU 2A also executes the application AP2 and accesses the shared variable y stored in the memory M2.
  • the CPU 3A also executes the application AP3 and accesses the shared variable z stored in the memory M3.
  • the application AP2 executed by the CPU2A accesses the shared variable x stored in the memory M1 of the processor module PM1 via the bus (or network), thereby enabling the sharing between the application AP1 and the application AP2. Realize the variable x.
  • the CPU 2A frequently accesses the shared variable x stored in the memory M1 of the processor module PM1, there is a problem that the processing time increases due to an increase in the number of accesses to the memory M1.
  • control device of the present disclosure is a control device having a plurality of processors and a plurality of local memories accessed by each of the plurality of processors, wherein a shared memory including at least a virtual address of a shared variable and a physical address of a shared variable is provided.
  • a storage unit for storing variable information; an access frequency evaluation unit for evaluating frequency of access to the shared variable included in the shared variable information for each execution program executed by each of the plurality of processors; and a memory placement optimization unit that changes the local memory in which the shared variables are placed.
  • the access frequency of an application executed by each CPU to a shared variable, and allocate shared variables with a high access frequency to the local memory of the CPU executing the application.
  • the number of accesses via the bus (or network) is reduced, which has the effect of shortening the application processing time.
  • FIG. 1 is a functional block diagram showing a functional configuration example of a numerical controller according to a first embodiment
  • FIG. FIG. 4 is a diagram showing an example of shared variable information
  • FIG. 5 is a diagram showing an example of access frequency for each shared variable in an axis control application
  • FIG. 10 is a diagram showing an example of access frequency for each shared variable in a display control application
  • FIG. 10 is a diagram showing an example of access frequency for each shared variable in a peripheral device control application
  • FIG. 10 is a diagram showing an example of access frequency after correction for each shared variable in an axis control application;
  • FIG. 10 is a diagram showing an example of access frequency after correction for each shared variable in the display control application;
  • FIG. 10 is a diagram showing an example of corrected access frequency for each shared variable in a peripheral device control application; 4 is a flowchart for explaining placement optimization processing of a numerical control device;
  • FIG. 7 is a functional block diagram showing a functional configuration example of a numerical controller according to a second embodiment;
  • 2 is a functional block diagram showing a functional configuration example of an information processing device;
  • FIG. FIG. 11 is a functional block diagram showing a functional configuration example of a numerical controller according to a third embodiment;
  • 2 is a functional block diagram showing a functional configuration example of an information processing device;
  • FIG. It is a figure which shows an example of the evaluation parameter stored in an evaluation parameter memory
  • FIG. 1 is a functional block diagram showing a functional configuration example of a control device.
  • the control device 1 controls, for example, machine tools, robots, etc., and has a control module 2, n processor modules 3-1 to 3-n, and a storage unit 4 (n is 2 is an integer greater than or equal to ).
  • the control module 2, processor modules 3-1 to 3-n, and storage unit 4 are communicably connected via a bus 5.
  • FIG. 1 is a functional block diagram showing a functional configuration example of a control device.
  • the control device 1 controls, for example, machine tools, robots, etc., and has a control module 2, n processor modules 3-1 to 3-n, and a storage unit 4 (n is 2 is an integer greater than or equal to ).
  • the control module 2, processor modules 3-1 to 3-n, and storage unit 4 are communicably connected via a bus 5.
  • FIG. 1 is a functional block diagram showing a functional configuration example of a control device.
  • the control device 1 controls, for example, machine tools, robots,
  • the storage unit 4 is a main memory such as a ROM (Read Only Memory), and stores a system program and an application program executed by the control module 2, as well as n executions executed by each of the processor modules 3-1 to 3-n described later. format execution programs 40-1 to 40-n may be stored.
  • the storage unit 4 also includes shared variable information 41 .
  • the shared variable information 41 includes, for example, information on shared variables including at least virtual addresses of shared variables and physical addresses of shared variables for cooperative operation among the execution programs 40-1 to 40-n.
  • the processor modules 3-1 to 3-n have, for example, a CPU 30 and a local memory 22, and execute execution programs 40-1 to 40 for axis control, display control, etc. based on control instructions from the control module 2, which will be described later. -n each run.
  • the control module 2 has a CPU 21 and a local memory 22 such as a RAM (Random Access Memory).
  • the CPU 21 is a processor that controls the control device 1 as a whole.
  • the CPU 21 reads, via the bus 5, a system program stored in the storage unit 4, which is a main memory, and an application program for executing a function unit described later, loads them into the local memory 22, and stores the system program and the application program.
  • the entire control device 1 is controlled according to. Thereby, as shown in FIG. 1, the CPU 21 is configured to implement the functions of the access frequency evaluation unit 21-1 and the memory allocation optimization unit 21-2.
  • the access frequency evaluation unit 21-1 calculates the frequency of access to the shared variables included in the shared variable information 41 for each of the execution programs 40-1 to 40-n executed by the CPUs 30 of the processor modules 3-1 to 3-n. Evaluate.
  • the memory allocation optimization unit 21-2 changes the local memory 31 in which the shared variables are allocated among the processor modules 3-1 to 3-n based on the access frequency evaluated by the access frequency evaluation unit 21-1. By doing so, the control device 1 can analyze the access frequency of the application executed by each CPU 30 to the shared variable, and arrange the shared variable with high access frequency in the local memory of the CPU executing the application. .
  • the basic operation of the control device has been described above.
  • control device a specific embodiment of the control device will be described by exemplifying a numerical control device as the control device.
  • the present invention is not limited to numerical control devices, but can also be applied to robot control devices having a plurality of processors that control industrial robots, for example. It is also applicable to any control device with multiple processors.
  • an axis control application, a display control application, and a peripheral device control application will be exemplified as execution programs to be executed in each of a plurality of processors, the present invention can also be applied to execution programs of arbitrary applications other than these. . Note that each processor may execute a plurality of programs.
  • FIG. 2 is a functional block diagram showing a functional configuration example of the numerical controller according to the first embodiment.
  • the axis control application, the display control application, and the peripheral device control application are exemplified as described above.
  • the present invention is not limited to axis control applications, display control applications, and peripheral device control applications, and can be applied to arbitrary applications other than axis control applications, display control applications, and peripheral device control applications. As shown in FIG.
  • the numerical control device 10 is a numerical control device known to those skilled in the art. Send commands to a machine tool (not shown). Thereby, the numerical controller 10 controls the operation of the machine tool (not shown). If the machine tool (not shown) is a robot or the like, the numerical controller 10 may be a robot controller or the like.
  • the numerical controller 10 has a system control module 110 , an axis control module 120 , a display control module 130 , a peripheral device control module 140 and a storage section 150 .
  • the system control module 110 , the axis control module 120 , the display control module 130 , the peripheral device control module 140 and the storage unit 150 are communicably connected via the bus 160 .
  • the system control module 110 has a CPU 111 and a local memory 112 .
  • the CPU 111 also has an access frequency evaluation unit 1111 and a memory allocation optimization unit 1112 .
  • the axis control module 120 also has a CPU 121 and a local memory 122 .
  • the display control module 130 has a CPU 131 and a local memory 132 .
  • the peripheral device control module 140 has a CPU 141 and a local memory 142 .
  • the storage unit 150 is a main memory such as a ROM (Read Only Memory).
  • the storage unit 150 may store a system program and a plurality of application programs (eg, axis control application 151, display control application 152, peripheral device control application 153).
  • the storage unit 150 also includes shared variable information 154, which will be described later.
  • the axis control application 151 is, for example, an execution program that controls a spindle or the like included in a machine tool (not shown), and is loaded into the axis control module 120 described later and executed.
  • the display control application 152 is, for example, an execution program that controls the display of a display device such as an LCD (Liquid Crystal Display) included in the numerical controller 10, and is loaded into the display control module 130 described later and executed.
  • a display device such as an LCD (Liquid Crystal Display) included in the numerical controller 10
  • LCD Liquid Crystal Display
  • the peripheral device control application 153 is, for example, an execution program that controls peripheral devices arranged around a machine tool (not shown), and is loaded into the peripheral device control module 140 described later and executed.
  • the shared variable information 154 includes, for example, information on shared variables for cooperative operation among the axis control application 151, the display control application 152, and the peripheral device control application 153, for example. Specifically, the shared variable specified when each application accesses the shared variable, the virtual address used when referencing the value of the shared variable, and the physical address where the value of the shared variable is actually stored , and the corresponding relationship.
  • FIG. 3 is a diagram showing an example of the shared variable information 154. As shown in FIG. As shown in FIG.
  • the shared variable information 154 has storage areas for "shared variables,””virtualaddresses," and "physical addresses.”
  • shared variables such as "x", "y”, and "z” are stored.
  • virtual address in the shared variable information 154, for example, the shared variable x assigned for cooperative operation among the axis control application 151, the display control application 152, and the peripheral device control application 153, Virtual addresses such as "aaaaaaa”, “bbbbbbbb”, “ccccccccccccc" corresponding to y and z are stored.
  • the system control module 110 is a module that controls the entire numerical controller 10 and has a CPU 111 and a local memory 112 .
  • the local memory 112 is composed of a RAM (Random Access Memory) or the like.
  • a CPU 111 is a processor that controls the numerical controller 10 as a whole.
  • the CPU 111 reads, via the bus 160, a system program stored in the storage unit 150, which is a main memory, and an application program for executing a function unit described later, loads the system program and the application program into the local memory 112, and loads the system program and the application program into the local memory 112.
  • the entire numerical controller 10 is controlled according to the following. Thereby, as shown in FIG. 2, the CPU 111 is configured to implement the functions of the access frequency evaluation unit 1111 and the memory allocation optimization unit 1112 .
  • the access frequency evaluation unit 1111 includes, for example, the axis control application 151, the display control application 152, the peripheral device control, and the CPU 121 of the axis control module 120, the CPU 131 of the display control module 130, and the CPU 141 of the peripheral device control module 140, which will be described later.
  • the frequency of access to the shared variables x, y, z, etc. included in the shared variable information 154 is evaluated for each application 153 .
  • the access frequency evaluation unit 1111 detects that the axis control application 151 is, for example, the shared variable x , y, and z in each execution cycle (access frequency).
  • the CPU 131 which will be described later, develops (loads) a display control application 152, which is an execution program for controlling the display of the display device, stored in the storage unit 150 into the local memory 132, the access frequency evaluation unit 1111
  • the display control application 152 acquires, for example, the number of accesses (access frequency) per execution cycle for each of the shared variables x, y, and z.
  • a peripheral device control application 153 which is an execution program for controlling a peripheral device stored in the storage unit 150, into the local memory 142, the access frequency evaluation unit 1111
  • the device control application 153 acquires, for example, the number of accesses per execution cycle (access frequency) for each of the shared variables x, y, and z.
  • the access frequency evaluation unit 1111 may include a reference instruction execution recording unit 1113 .
  • each of the CPU 121 of the axis control module 120, the CPU 131 of the display control module 130, and the CPU 141 of the peripheral device control module 140 executes the axis control application 151, which is an execution program for controlling the spindle and the like.
  • a display control application 152 which is an execution program for controlling the display of the display device, is expanded (loaded) into the local memory 122, and a peripheral device control application 153, which is an execution program for controlling peripheral devices, into the local memory 142.
  • the axis control application 151, the display control application 152, and the peripheral device control application 153 record the number of accesses to the respective shared variables x, y, and z per execution cycle.
  • the access frequency evaluation unit 1111 calculates the number of times the axis control application 151 accesses each of the shared variables x, y, and z in one execution cycle, and The number of accesses per execution cycle is stored as the access frequency to the shared variables of the axis control application 151 .
  • the access frequency evaluation unit 1111 calculates the number of times the display control application 152 accesses each of the shared variables x, y, and z per execution cycle, The number of accesses per unit is stored as the frequency of access to the shared variable of the display control application 152 .
  • the access frequency evaluation unit 1111 calculates the number of times the peripheral device control application 153 accesses each of the shared variables x, y, and z in one execution cycle, and calculates one execution for each of the shared variables x, y, and z.
  • the number of accesses per period is stored as the access frequency to the shared variable of the peripheral device control application 153 .
  • the number of accesses to the shared variables of each execution program per execution cycle is defined as the frequency of access to the shared variables of the axis control application 151. may be stored as By doing so, the memory allocation optimization unit 1112, which will be described later, can calculate the frequency of access to the shared variables of the processor.
  • FIG. 4A is a diagram showing an example of the access frequency for each shared variable in the axis control application 151.
  • FIG. FIG. 4B is a diagram showing an example of the access frequency for each shared variable in the display control application 152.
  • FIG. 4C is a diagram showing an example of the access frequency for each shared variable in the peripheral device control application 153.
  • the access frequency to the shared variable x is 80 times/cycle per execution cycle.
  • the access frequency to the shared variable y is 60 times/cycle per one execution period.
  • the access frequency to the shared variable z is 50 times/cycle per one execution period.
  • the axis control application 151, the display control application 152, and the peripheral device control application 153 have different execution cycles.
  • the matching time T is obtained by multiplying one execution cycle by an integer, and based on the frequency of access to the shared variables x, y, z, etc. for each application in the obtained time T, each shared variable x, y, z, etc. (also referred to as "access frequency in the same processing time", “corrected access frequency”, or simply “access frequency” unless otherwise specified), and based on the corrected access frequency, A reorganization of the physical addresses at which the values of shared variables are stored can be done.
  • the memory allocation optimization unit 1112 changes the local memory in which shared variables are allocated based on the corrected access frequency (hereinafter also referred to as “access frequency” unless otherwise specified).
  • 6A, 6B, and 6C show corrected access frequencies (access frequencies) of the axis control application 151, the display control application 152, and the peripheral device control application 153, respectively.
  • the memory allocation optimization unit 1112 stores the shared variable x, which has the highest access frequency in the axis control application 151, in the local memory 122 of the axis control module 120 (to be described later) that executes the axis control application 151, which is the allocation destination.
  • Obtain a physical address eg, "AAAAAAA"
  • the memory allocation optimizing unit 1112 changes the physical address of the shared variable x to be allocated, which is stored in the shared variable information 154, from, for example, “XXXXXXX” to “AAAAAAAAA”, and moves the shared variable x to the physical address of the local memory 122. It is placed at the address "AAAAAAAA”.
  • the memory allocation optimization unit 1112 stores the shared variable y with the highest access frequency in the display control application 152 in the local memory 132 of the later-described display control module 130 that executes the display control application 152, which is the allocation destination.
  • the memory allocation optimization unit 1112 changes the physical address of the shared variable y to be allocated, which is stored in the shared variable information 154 , from “YYYYYYY” to “BBBBBBBB”, for example, and places the shared variable y in the physical address of the local memory 132 . It is placed at the address "BBBBBBBB”.
  • the memory allocation optimizing unit 1112 stores the shared variable z, which has the highest access frequency in the peripheral device control application 153, in the local memory 142 of the peripheral device control module 140 (to be described later) that executes the peripheral device control application 153, which is the allocation destination.
  • Get a physical address eg, "CCCCCCCC" to store in the .
  • the memory allocation optimization unit 1112 changes the physical address of the shared variable z to be allocated, which is stored in the shared variable information 154 , from “ZZZZZZZZZZ” to “CCCCCC”, for example, and changes the shared variable z to the physical address of the local memory 142 . It is placed at the address "CCCCCCCC". By doing so, the CPUs 121, 131, and 141 can reduce the access to the local memory via the bus 160 and shorten the processing time.
  • the axis control module 120 has a CPU 121 and a local memory 122 .
  • the CPU 121 controls the three axes of the X, Y, and Z axes that change the position and inclination of the spindle and table included in the machine tool (not shown), and the X and Y axes. , Z-axis, A-axis, and B-axis.
  • the local memory 122 is a RAM or the like, in which the axis control application 151 executed by the CPU 121 is loaded, and can access the shared variable x optimally allocated by the memory allocation optimization unit 1112 during execution.
  • the axis control module 120 controls three axes of the X axis, the Y axis, and the Z axis, or five axes of the X axis, the Y axis, the Z axis, the A axis, and the B axis, etc.
  • the axis control module 120 is not limited to this.
  • the numerical controller 10 may have multiple axis control modules 120 that control each axis.
  • the display control module 130 has a CPU 131 and a local memory 132 .
  • the CPU 131 executes the display control application 152 to control the display of the display device of the machine tool (not shown).
  • the local memory 132 is a RAM or the like, loads the display control application 152 executed by the CPU 131, and can access the shared variable y optimally allocated by the memory allocation optimization unit 1112 during execution.
  • the peripheral device control module 140 has a CPU 141 and a local memory 142 .
  • the CPU 141 controls peripheral devices arranged around the machine tool (not shown) by executing the peripheral device control application 153 .
  • the local memory 142 is a RAM or the like, loads the peripheral device control application 153 executed by the CPU 141, and can access the shared variable z optimally allocated by the memory allocation optimization unit 1112 during execution.
  • FIG. 7 is a flowchart for explaining the placement optimization processing of the numerical controller 10. As shown in FIG. The flow shown here is repeatedly executed when the numerical controller 10 loads an application.
  • step S11 the access frequency evaluation unit 1111 determines whether the CPU 121 of the axis control module 120, the CPU 131 of the display control module 130, or the CPU 141 of the peripheral device control module 140 stores the axis control application 151 and the display control application 152 in the storage unit 150. , the frequency of access to each of the shared variables x, y, and z per one execution cycle is calculated when the peripheral device control application 153 is developed in the local memory.
  • step S12 the access frequency evaluation unit 1111 determines whether or not the access frequencies of all applications have been calculated. When the access frequencies of all applications have been calculated, the process proceeds to step S13. On the other hand, if the access frequencies of all applications have not been calculated, the process returns to step S11.
  • step S13 the memory allocation optimization unit 1112 acquires the application access frequency of the axis control application 151, the display control application 152, or the peripheral device control application 153 calculated in step S11.
  • step S14 the memory allocation optimization unit 1112 compares the frequency of access to the shared variables acquired in step S13 among the applications, identifies the application with the highest access frequency to the shared variable, and executes the application.
  • the memory placement optimization unit 1112 changes the physical address of the shared variable to be placed stored in the shared variable information 154 to the acquired physical address, and places the shared variable in the local memory.
  • step S15 the memory placement optimization unit 1112 determines whether all shared variables have been placed in the local memory. When all shared variables have been placed in the local memory, the placement optimization process ends. On the other hand, if all shared variables have not been placed in the local memory, the process returns to step S13.
  • the numerical controller 10 analyzes the frequency of access to the shared variables of the axis control application 151, the display control application 152, and the peripheral device control application 153 executed by the respective CPUs 121, 131, and 141, Shared variables with high access frequency can be placed in the local memory of the CPU where the application is executed. In addition, the numerical controller 10 can reduce access to the storage unit 150 and shorten the processing time.
  • the first embodiment has been described above.
  • the numerical controller 10A acquires from an external device the number of reference instructions to shared variables from the source programs of the axis control application 151, the display control application 152, and the peripheral device control application 153, and is different from the first embodiment in that the access frequency to the shared variable is evaluated based on .
  • the numerical controller 10A of the second embodiment analyzes the frequency of access to the shared variables of the applications executed by each CPU, and arranges the shared variables with high access frequency in the local memory of the CPU executing the applications. can do.
  • a second embodiment will be described below.
  • FIG. 8 is a functional block diagram showing a functional configuration example of a numerical controller 10A according to the second embodiment. Elements having functions similar to those of the numerical control device 10 in FIG. As shown in FIG. 8, the numerical control device 10A may be directly connected to the information processing device 20 via a connection interface (not shown). Further, the numerical control device 10A may be connected to the information processing device 20 via a network (not shown) such as a LAN (Local Area Network) or the Internet. In this case, the numerical control device 10A and the information processing device 20 are provided with a communication section (not shown) for mutual communication through such connection. Although the numerical control device 10A is connected to one information processing device 20, it may be connected to a plurality of information processing devices 20. FIG.
  • FIG. 9 is a functional block diagram showing a functional configuration example of the information processing device 20.
  • the information processing device 20 has a control section 210 and a storage section 220 .
  • the control unit 210 has an analysis unit 211 and a compilation unit 212 .
  • the storage unit 220 is a RAM, HDD (Hard Disk Drive), or the like, and may store a system program and a plurality of application programs.
  • the storage unit 220 includes an axis control source program 221 , a display control source program 222 and a peripheral device control source program 223 .
  • the axis control source program 221 is the source program of the axis control application 151 stored in the storage unit 150 of the numerical controller 10A.
  • the display control source program 222 is the source program of the display control application 152 stored in the storage unit 150 of the numerical controller 10A.
  • the peripheral device control source program 223 is the source program of the peripheral device control application 153 stored in the storage unit 150 of the numerical controller 10A.
  • the control unit 210 has a CPU, a ROM, a RAM, a CMOS (Complementary Metal-Oxide-Semiconductor) memory, etc., which are known to those skilled in the art and are configured to communicate with each other via a bus.
  • the CPU is a processor that controls the information processing device 20 as a whole.
  • the CPU reads the system program stored in the ROM and the application program for executing the function units described later via the bus, loads them into a memory (not shown), and executes the information processing apparatus according to the system program and the application program. 20 as a whole.
  • the control unit 210 is configured to implement the functions of the analysis unit 211 and the compilation unit 212 .
  • CMOS memory is backed up by a battery (not shown) and configured as a non-volatile memory that retains the memory state even when the information processing apparatus 20 is powered off.
  • the analysis unit 211 receives, for example, an axis control source program 221, a display control source program 222, and a peripheral device control source program 223 from a user via an input device (not shown) such as a keyboard or touch panel included in the information processing device 20.
  • an analysis instruction for a source program is received, each source program is analyzed, and the number of control statements that refer to shared variables x, y, z, etc. from the beginning to the end of the source program (that is, one execution cycle) is shared. Obtained as the number of reference instructions for each variable.
  • the analysis unit 211 may store the obtained number of reference instructions such as the shared variables x, y, and z of each program in the execution format of each program, for example. By doing so, when the execution program is expanded (loaded) into respective local memories (to be described later) in the numerical control device 10A, the numerical control device 10A (access frequency evaluation unit) uses shared variables x, y , z, etc. can be obtained.
  • the compiling unit 212 receives an instruction to compile the axis control source program 221, the display control source program 222, or the peripheral device control source program 223 from the user via the input device (not shown) of the information processing device 20,
  • the axis control source program 221, the display control source program 222, or the peripheral device control source program 223 is compiled to generate the axis control application 151, the display control application 152, or the peripheral device control application 153 of the execution program.
  • the compiling unit 212 transmits the generated display control application 152 or peripheral device control application 153 to the numerical controller 10A.
  • the compilation unit 212 may have the function of the analysis unit 211 .
  • the compiling unit 212 calculates the number of reference instructions such as the shared variables x, y, and z of each program, and calculates the number of reference instructions of each program as described above. It can be stored in an executable program.
  • the numerical controller 10A has a system control module 110a, an axis control module 120, a display control module 130, a peripheral device control module 140, and a storage section 150, as shown in FIG.
  • the system control module 110 a has a CPU 111 a and a local memory 112 .
  • the CPU 111 a also has an access frequency evaluation unit 1111 a and a memory allocation optimization unit 1112 .
  • the memory layout optimization unit 1112 has functions equivalent to those of the memory layout optimization unit 1112 in the first embodiment.
  • the CPU 111a is a processor that controls the numerical controller 10A as a whole, like the CPU 111 of the first embodiment.
  • the CPU 111a reads, via the bus 160, a system program stored in the storage unit 150, which is a main memory, and an application program for executing a function unit described later, loads them into the local memory 112, and stores the system program and the application program.
  • the entire numerical controller 10A is controlled according to the following. Thereby, as shown in FIG. 8, the CPU 111a is configured to implement the functions of the access frequency evaluation unit 1111a and the memory allocation optimization unit 1112.
  • FIG. 8 the CPU 111a is configured to implement the functions of the access frequency evaluation unit 11
  • the access frequency evaluation unit 1111a is an axis control source program 221, a display control source program 222, and a peripheral device, which are source programs for the axis control application 151, the display control application 152, and the peripheral device control application 153.
  • the number of reference instructions to the shared variables x, y, z, etc. obtained from the analysis of the control source program 223 is acquired from the information processing device 20 .
  • the access frequency evaluation unit 1111a per execution cycle based on the number of reference instructions to the shared variables x, y, z, etc. in each of the acquired execution programs, that is, the axis control application 151, the display control application 152, and the peripheral device control application 153. Evaluate the frequency of access to shared variables x, y, z, etc. in .
  • the arrangement optimization processing of the numerical control device 10A is the same as the processing shown in FIG. 7 except that the access frequency evaluation unit 1111a acquires the number of reference instructions from the information processing device 20, and detailed description thereof will be omitted.
  • the numerical control device 10A includes the axis control source program 221, which is the source program of the axis control application 151, the display control application 152, and the peripheral device control application 153, and the display control source program.
  • the frequency of access to the shared variables obtained from the analysis of the peripheral device control source program 223 is acquired from the information processing device 20 .
  • the numerical controller 10A can place the shared variable with the highest access frequency in the local memory of the CPU executing the application.
  • the CPUs 121, 131, and 141 can reduce the access to the local memory via the bus 160 and shorten the processing time.
  • the second embodiment has been described above.
  • the numerical controller 10A has the access frequency evaluation unit 1111a, it is not limited to this.
  • the information processing device 20 may have an access frequency evaluation unit 1111a.
  • the analysis unit 211 has the function of the access frequency evaluation unit 1111a, and calculates the shared variables x, y, z, etc. based on the number of reference instructions to the shared variables x, y, z, etc. obtained from the analysis of each source program.
  • the access frequency may be evaluated, and the evaluated access frequency may be stored, for example, in the executable form of each program. By doing so, when the execution program is developed (loaded) into each local memory in the numerical control device 10A, the numerical control device 10A (memory allocation optimization unit) can set the shared variables x, y, z etc. can be placed in the optimal local memory.
  • the numerical controller 10B stores an evaluation parameter used for evaluating the access frequency, and when acquiring the number of reference instructions to the shared variable from the information processing device 20B as an external device, The difference from the first and second embodiments is that the number of reference instructions for each control statement is weighted and corrected by an evaluation parameter, and the frequency of access to shared variables is evaluated based on the corrected number of reference instructions. do.
  • the numerical controller 10B of the third embodiment analyzes the frequency of access to the shared variables of the applications executed by each CPU, and arranges shared variables with high access frequency in the local memory of the CPU executing the applications. can do.
  • a third embodiment will be described below.
  • FIG. 10 is a functional block diagram showing a functional configuration example of a numerical controller 10B according to the third embodiment. Elements having functions similar to those of the numerical control device 10 in FIG. As shown in FIG. 10, the numerical control device 10B may be directly connected to the information processing device 20B via a connection interface (not shown), similarly to the numerical control device 10A according to the second embodiment. Further, the numerical control device 10B may be connected to the information processing device 20B via a network (not shown) such as a LAN (Local Area Network) or the Internet.
  • a network not shown
  • LAN Local Area Network
  • FIG. 11 is a functional block diagram showing a functional configuration example of the information processing device 20B. Elements having functions similar to those of the information processing apparatus 20 shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the information processing device 20B has a control section 210b and a storage section 220.
  • the control unit 210b has an analysis unit 211b and a compilation unit 212 .
  • the control unit 210b has a CPU, a ROM, a RAM, a CMOS memory, etc., which are configured to communicate with each other via a bus. It is.
  • the CPU is a processor that controls the information processing device 20B as a whole.
  • the CPU reads the system program stored in the ROM and the application program for executing the function units described later via the bus, loads them into a memory (not shown), and executes the information processing apparatus according to the system program and the application program. 20B as a whole.
  • the control unit 210b is configured to implement the functions of the analysis unit 211b and the compilation unit 212.
  • the compiling unit 212 has functions equivalent to those of the compiling unit 212 in the second embodiment.
  • the analysis unit 211b receives an analysis instruction for the source programs of the axis control source program 221, the display control source program 222, and the peripheral device control source program 223 from the user via the input device (not shown) of the information processing device 20B.
  • type of control statements in each source program for example, "plain text", “IF statement”, “For statement”, etc.
  • the analysis unit 211b may store the obtained type of each control statement and the number of reference instructions for each control statement in, for example, an executable program of each program.
  • the numerical control device 10B determines the type of each control statement of each program and the number of reference instructions such as shared variables x, y, and z for each control statement.
  • the analysis unit 211 b may be included in the compilation unit 212 .
  • the numerical controller 10B has a system control module 110b, an axis control module 120, a display control module 130, a peripheral device control module 140, and a storage section 150, as shown in FIG.
  • the system control module 110 b has a CPU 111 b and a local memory 112 .
  • the CPU 111b also has an access frequency evaluation unit 1111b and a memory allocation optimization unit 1112 .
  • the access frequency evaluation unit 1111b also has an evaluation parameter storage unit 1114.
  • the memory layout optimization unit 1112 has functions equivalent to those of the memory layout optimization unit 1112 in the first embodiment.
  • the CPU 111b is a processor that controls the numerical controller 10B as a whole, like the CPU 111 of the first embodiment.
  • the CPU 111b reads, via the bus 160, a system program stored in the storage unit 150, which is a main memory, and an application program for executing a function unit (to be described later), loads them into the local memory 112, and stores the system program and the application program in question.
  • the entire numerical controller 10B is controlled according to the following. Thereby, as shown in FIG. 10, the CPU 111b is configured to implement the functions of the access frequency evaluation unit 1111b and the memory allocation optimization unit 1112. FIG. Also, the access frequency evaluation unit 1111b is configured to realize the function of the evaluation parameter storage unit 1114.
  • the evaluation parameter storage unit 1114 stores, for example, the value of the evaluation parameter used for evaluating the access frequency for each control statement forming the source program of the application.
  • FIG. 12 is a diagram showing an example of evaluation parameters stored in the evaluation parameter storage unit 1114. As shown in FIG. As shown in FIG. 12, when the control statement is plain text, the evaluation parameter is set to a value such as "1.0", for example. Also, if the control statement is an IF statement, the evaluation parameter may not be executed depending on the conditions, so the evaluation parameter is set to a smaller value (for example, "0.8", etc.) than in the case of plain text.
  • the evaluation parameter is set to a larger value (for example, "10") than in the case of plain text because the control statement is repeatedly executed a plurality of times in one execution cycle.
  • the value of the evaluation parameter may be set in advance by the user via an input device (not shown) such as a keyboard or touch panel included in the numerical controller 10B.
  • the access frequency evaluation unit 1111b for example, the axis control source program 221, the display control source program 222, which are the source programs of the axis control application 151, the display control application 152, and the peripheral device control application 153 by the analysis unit 211 of the information processing device 20B,
  • the type of each control statement and the number of reference instructions for each control statement obtained from the analysis of the peripheral device control source program 223 are acquired from the information processing device 20B.
  • the access frequency evaluation unit 1111b weights and corrects the number of reference instructions for each control statement in the source program using an evaluation parameter corresponding to the type of control statement stored in the evaluation parameter storage unit 1114, and corrects the corrected number of reference instructions. Evaluate access frequency to shared variables based on . FIG.
  • FIG. 13 is a diagram showing an example explaining the operation of the access frequency evaluation unit 1111b.
  • the analysis unit 211b of the information processing device 20B analyzes the source code stored in the storage unit 220, and determines the type of each control statement and the number of reference instructions "1" per execution cycle. stored in the program of The access frequency evaluation unit 1111b of the numerical controller 10B determines the value of the evaluation parameter according to the type of the control statement for the number of reference instructions "1" for each control statement stored in the execution program received from the information processing device 20B. is weighted to correct the number of reference instructions.
  • the access frequency evaluation unit 1111b weights and corrects the number of reference instructions "1" of the first and second plaintext control statements with the evaluation parameter "1.0", and corrects the number per execution cycle. Then, the number of reference instructions "1" is calculated. Further, the access frequency evaluation unit 1111b weights and corrects the number of reference instructions of the control statement of the third IF statement "1" by weighting the evaluation parameter "0.8", and corrects the reference instruction count per one execution cycle. Calculate the number "0.8”. Further, the access frequency evaluation unit 1111b weights and corrects the reference instruction count “1” of the control statement of the fourth For statement with the evaluation parameter “10”, and corrects the corrected reference instruction count “1” per execution cycle. 10" is calculated.
  • the access frequency evaluation unit 1111b adds the corrected number of reference instructions to each of the shared variables x, y, and z in each of the axis control application 151, the display control application 152, and the peripheral device control application 153. Evaluate the frequency of access to shared variables x, y, z per By doing so, when executing the axis control application 151, the display control application 152, and the peripheral device control application 153, the numerical controller 10B can accurately evaluate the access frequency to the shared variables x, y, z, and the like. , and shared variables can be optimally placed in local memory 122 , 132 , 142 .
  • the access frequency evaluation unit 1111b acquires the number of reference instructions from the information processing device 20B and corrects it with an evaluation parameter. Description is omitted.
  • the numerical controller 10B includes the axis control source program 221, the display control source program 222, and the peripheral device control source program 221, which are the source programs of the axis control application 151, the display control application 152, and the peripheral device control application 153.
  • the type of each control statement of the source program 223 and the number of reference instructions for each control statement are obtained from the information processing device 20B.
  • the numerical controller 10B corrects the obtained number of reference instructions for each control statement by weighting it with an evaluation parameter according to the type of the control statement, and evaluates the access frequency to the shared variable based on the corrected number of reference instructions.
  • the shared variables with the highest access frequency can be placed in the local memory of the CPU where the application is executed.
  • the CPUs 121, 131, and 141 can reduce the access to the local memory via the bus 160 and shorten the processing time.
  • the third embodiment has been described above.
  • the numerical controller 10B according to the third embodiment has the access frequency evaluation unit 1111b and the evaluation parameter storage unit 1114, but is not limited to this.
  • the information processing device 20B may have an access frequency evaluation unit 1111a and an evaluation parameter storage unit 1114.
  • the analysis unit 211b has the function of the access frequency evaluation unit 1111b, and obtains the type of each control statement and the number of reference instructions for each control statement obtained from the analysis of each source program.
  • the analysis unit 211b corrects the obtained number of reference instructions for each control statement in the source program by weighting it with an evaluation parameter corresponding to the type of control statement stored in the evaluation parameter storage unit 1114, and corrects the corrected number of reference instructions.
  • the numerical control device 10B may be used to evaluate the access frequency to the shared variable based on and store the evaluated access frequency in, for example, the executable program of each program. By doing so, when the execution program is expanded (loaded) into each local memory in the numerical control device 10B, the numerical control device 10B (memory allocation optimization unit) can set the shared variables x, y, z etc. can be placed in the optimal local memory.
  • the first embodiment, the second embodiment, the modification of the second embodiment, the third embodiment, and the modification of the third embodiment have been described above. It is not limited to the embodiment, and includes modifications, improvements, etc. within a range that can achieve the purpose.
  • the axis control module 120 and the display control module of the numerical controllers 10, 10A, and 10B 130 and the peripheral device control module 140 each executed one of the axis control application 151, the display control application 152, and the peripheral device control application 153, but is not limited to this.
  • the CPU 121 of the axis control module 120 of the numerical controllers 10, 10A, and 10B executes a plurality of applications such as an application for acquiring the position coordinates of the spindle of a machine tool (not shown) together with the axis control application 151. good too.
  • the access frequency to the shared variables in the axis control module 120 may be the sum of the access frequencies to the shared variables of these multiple applications.
  • the CPU 131 of the display control module 130 may execute a plurality of applications such as an application for obtaining execution lines of a machining program for operating a machine tool (not shown) together with the display control application 152 .
  • the access frequency to the shared variable in the display control module 130 may be the sum of the access frequencies to the shared variable of these multiple applications.
  • the CPU 141 of the peripheral device control module 140 may execute a plurality of applications such as an application for monitoring whether or not a worker is around the peripheral device together with the peripheral device control application 153 .
  • the frequency of access to shared variables in peripheral device control module 140 may be the sum of the access frequencies of these multiple applications to shared variables.
  • the local memories 122, 132 of the numerical controllers 10, 10A, 10B , 142 are shared variables with the highest access frequency among the shared variables x, y, z, etc., but are not limited to this.
  • shared variables having a predetermined access frequency or higher among the shared variables x, y, z, etc. may be allocated.
  • the information processing apparatuses 20 and 20B have the analysis units 211 and 221b set the axis control application 151 , the display control application 152, and the peripheral device control application 153 have been analyzed, but the present invention is not limited to this.
  • the compilation unit 212 may have the functions of the analysis units 211 and 211b.
  • each function included in the numerical controllers 10, 10A, and 10B according to the first embodiment, the second embodiment, the modification of the second embodiment, the third embodiment, and the modification of the third embodiment is Each can be implemented by hardware, software, or a combination thereof.
  • “implemented by software” means implemented by a computer reading and executing a program.
  • Non-transitory computer-readable media include various types of tangible storage media.
  • Examples of non-transitory computer-readable media include magnetic recording media (e.g., flexible discs, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical discs), CD-ROMs (Read Only Memory), CD- R, CD-R/W, semiconductor memory (eg, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM).
  • the program may also be supplied to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired communication channels, such as wires and optical fibers, or wireless communication channels.
  • steps of writing a program recorded on a recording medium include not only processes that are executed chronologically in order, but also processes that are executed in parallel or individually, even if they are not necessarily processed chronologically. It also includes
  • control device of the present disclosure can take various embodiments having the following configurations.
  • the control device 1 of the present disclosure is a control device having a plurality of CPUs 30 and a plurality of local memories 31 accessed by each of the plurality of CPUs 30, and includes at least virtual addresses of shared variables and physical addresses of shared variables.
  • a storage unit 4 that stores shared variable information 41, and an access frequency evaluation unit that evaluates the frequency of access to shared variables included in the shared variable information 41 for each of the execution programs 40-1 to 40-n executed by each of the plurality of CPUs 30. 21-1, and a memory placement optimization unit 21-2 that changes the local memory 31 in which shared variables are placed based on the access frequency.
  • this control device 1 it is possible to analyze the access frequency of an application executed by each CPU to a shared variable, and arrange shared variables with a high access frequency in the local memory of the CPU executing the application.
  • the access frequency evaluation unit 1111 counts the number of executions of instructions that refer to shared variables when each of the CPUs 121, 131, and 141 executes an execution program. , 131, and 141, and the access frequency evaluation unit 1111 calculates a shared variable may be evaluated, and the memory placement optimizer 1112 may place shared variables in the local memory accessed by the processor with the highest evaluated access frequency. By doing so, the numerical controller 10 can accurately evaluate the access frequency and further optimize the allocation of shared variables.
  • the access frequency evaluation unit 1111a acquires the number of reference instructions to the shared variable for each execution program executed by each of the plurality of CPUs 121, 131, and 141, or acquires the number of information processing
  • the number of reference instructions to the shared variable obtained from the analysis of the source program of the execution program by the device 20 is acquired from the information processing device 20, the frequency of access to the shared variable is evaluated based on the acquired number of reference instructions, and the memory allocation is optimized.
  • the modifier 1112 may place the shared variables in the local memory accessed by the CPU with the highest evaluated access frequency. By doing so, the numerical controller 10A can achieve the same effect as (2).
  • the access frequency evaluation unit 1111b includes an evaluation parameter storage unit 1114 that stores evaluation parameters used for evaluating the access frequency, and the access frequency evaluation unit 1111b stores the reference instruction
  • the number of reference instructions for each control statement in the source program is weighted and corrected by the evaluation parameter stored in the evaluation parameter storage unit 1114, and shared based on the corrected number of reference instructions.
  • the frequency of access to variables may be evaluated. By doing so, the numerical controller 10B can accurately evaluate the access frequency to the shared variable without executing the application.
  • control device 2 control module 21 CPU 21-1 access frequency evaluation unit 21-2 memory allocation optimization unit 22 local memory 3-1 to 3-n processor module 30
  • Peripheral device control module 141 CPU 142 local memory 150 storage unit 151 axis control application 152 display control application 153 peripheral device control application 154 shared variable information 160 bus 20, 20B information processing device 210, 210b control unit 211, 211b analysis unit 212 compilation unit 220 storage unit 221 axis control Source program 222 Display control source program 223 Peripheral device control source program

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Abstract

The present invention analyzes the frequency of access to a shared variable by an application executed by each CPU, and places a shared variable with a high access frequency in the local memory of the CPU executing the application.　Provided is a control device equipped with a plurality of processors and a plurality of local memories accessed by the plurality of processors, respectively, the control device comprising: a storage unit that stores shared variable information including at least the virtual address of the shared variable and the physical address of the shared variable; an access frequency evaluation unit that evaluates the frequency of access to the shared variable included in the shared variable information for each execution program executed by each of the plurality of processors; and a memory placement optimization unit that changes the local memory in which the shared variable is placed on the basis of the access frequency.

Description

制御装置Control device
　本発明は、制御装置に関する。 The present invention relates to a control device.
　多数の機能を持つ複雑な制御装置では、複数のＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）を使用してそれぞれ別のアプリケーションプログラム（以下、「アプリ」ともいう）を動作させている。また、処理の高速化のため、各ＣＰＵはローカルメモリを持ち、それらをネットワーク（又はバス）で結合している。
　この点、データベース・リソースのアクセス状況に応じて、共用型のインテグリテイ保証又は局所型のインテグリテイ保証が自動的に選択され、リソース管理の最適配置により、アクセスの高速化及び通信オーバヘッドの削減等の処理コストの低下を図る技術が知られている。例えば、特許文献１参照。 2. Description of the Related Art In a complicated control device having many functions, a plurality of CPUs (Central Processing Units) are used to run separate application programs (hereinafter also referred to as "applications"). In addition, each CPU has a local memory and is connected by a network (or bus) to speed up processing.
In this regard, shared integrity assurance or local integrity assurance is automatically selected according to the access status of database resources, and the optimal arrangement of resource management increases access speed and reduces communication overhead. Techniques for reducing processing costs are known. See Patent Document 1, for example.
特開平２－２４７７４８号公報JP-A-2-247748
　複数のＣＰＵそれぞれで実行されるアプリを、アプリ間で連携して動作させるために共有変数が使用されている。
　図１４は、アプリ間で連携される共有変数の一例を示す図である。
　図１４に示すように、制御装置Ｃ１は、例えば、複数のプロセッサモジュールＰＭ１、ＰＭ２、ＰＭ３等を有し、複数のプロセッサモジュールＰＭ１、ＰＭ２、ＰＭ３等は、バス（又はネットワーク）で接続されている。また、プロセッサモジュールＰＭ１は、ＣＰＵ１Ａ、及びメモリＭ１を有し、プロセッサモジュールＰＭ２は、ＣＰＵ２Ａ、及びメモリＭ２を有し、プロセッサモジュールＰＭ３は、ＣＰＵ３Ａ、及びメモリＭ３を有する。そして、ＣＰＵ１Ａは、アプリＡＰ１を実行し、メモリＭ１に格納された共有変数ｘにアクセスする。また、ＣＰＵ２Ａは、アプリＡＰ２を実行し、メモリＭ２に格納された共有変数ｙにアクセスする。また、ＣＰＵ３Ａは、アプリＡＰ３を実行し、メモリＭ３に格納された共有変数ｚにアクセスする。
　図１４の場合、例えば、ＣＰＵ２Ａで実行されるアプリＡＰ２が、プロセッサモジュールＰＭ１のメモリＭ１に格納された共有変数ｘをバス（又はネットワーク）経由でアクセスすることで、アプリＡＰ１とアプリＡＰ２間の共有変数ｘを実現する。
　しかしながら、ＣＰＵ２ＡがプロセッサモジュールＰＭ１のメモリＭ１に格納された共有変数ｘに頻繁にアクセスすると、メモリＭ１へのアクセス回数が増えることにより処理時間が長くなるという問題がある。 A shared variable is used to coordinate and operate applications executed by each of a plurality of CPUs.
FIG. 14 is a diagram illustrating an example of shared variables linked between applications.
As shown in FIG. 14, the control device C1 has, for example, a plurality of processor modules PM1, PM2, PM3, etc., and the plurality of processor modules PM1, PM2, PM3, etc. are connected via a bus (or network). . The processor module PM1 has a CPU1A and a memory M1, the processor module PM2 has a CPU2A and a memory M2, and the processor module PM3 has a CPU3A and a memory M3. The CPU 1A then executes the application AP1 and accesses the shared variable x stored in the memory M1. The CPU 2A also executes the application AP2 and accesses the shared variable y stored in the memory M2. The CPU 3A also executes the application AP3 and accesses the shared variable z stored in the memory M3.
In the case of FIG. 14, for example, the application AP2 executed by the CPU2A accesses the shared variable x stored in the memory M1 of the processor module PM1 via the bus (or network), thereby enabling the sharing between the application AP1 and the application AP2. Realize the variable x.
However, if the CPU 2A frequently accesses the shared variable x stored in the memory M1 of the processor module PM1, there is a problem that the processing time increases due to an increase in the number of accesses to the memory M1.
　そこで、各ＣＰＵが実行するアプリの共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数を当該アプリが実行されるＣＰＵのローカルメモリに配置することが望まれている。 Therefore, it is desirable to analyze the access frequency of an application executed by each CPU to a shared variable and to allocate shared variables with a high access frequency to the local memory of the CPU executing the application.
　本開示の制御装置の一態様は、複数のプロセッサと前記複数のプロセッサそれぞれがアクセスする複数のローカルメモリとを有する制御装置であって、少なくとも共有変数の仮想アドレス及び共有変数の物理アドレスを含む共有変数情報を格納する記憶部と、前記複数のプロセッサそれぞれが実行する実行プログラム毎に前記共有変数情報に含まれる前記共有変数へのアクセス頻度を評価するアクセス頻度評価部と、前記アクセス頻度に基づいて前記共有変数を配置する前記ローカルメモリを変更するメモリ配置最適化部と、を備える。 One aspect of the control device of the present disclosure is a control device having a plurality of processors and a plurality of local memories accessed by each of the plurality of processors, wherein a shared memory including at least a virtual address of a shared variable and a physical address of a shared variable is provided. a storage unit for storing variable information; an access frequency evaluation unit for evaluating frequency of access to the shared variable included in the shared variable information for each execution program executed by each of the plurality of processors; and a memory placement optimization unit that changes the local memory in which the shared variables are placed.
　一態様によれば、各ＣＰＵが実行するアプリの共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数を当該アプリが実行されるＣＰＵのローカルメモリに配置することができる。その結果、バス（又はネットワーク）経由のアクセスが減少し、アプリの処理時間の短縮という効果を奏する。 According to one aspect, it is possible to analyze the access frequency of an application executed by each CPU to a shared variable, and allocate shared variables with a high access frequency to the local memory of the CPU executing the application. As a result, the number of accesses via the bus (or network) is reduced, which has the effect of shortening the application processing time.
制御装置の機能的構成例を示す機能ブロック図である。It is a functional block diagram showing an example of functional composition of a control device. 第１実施形態に係る数値制御装置の機能的構成例を示す機能ブロック図である。1 is a functional block diagram showing a functional configuration example of a numerical controller according to a first embodiment; FIG. 共有変数情報の一例を示す図である。FIG. 4 is a diagram showing an example of shared variable information; 軸制御アプリにおける共有変数毎のアクセス頻度の一例を示す図である。FIG. 5 is a diagram showing an example of access frequency for each shared variable in an axis control application; 表示制御アプリにおける共有変数毎のアクセス頻度の一例を示す図である。FIG. 10 is a diagram showing an example of access frequency for each shared variable in a display control application; 周辺機器制御アプリにおける共有変数毎のアクセス頻度の一例を示す図である。FIG. 10 is a diagram showing an example of access frequency for each shared variable in a peripheral device control application; アプリ毎の実行周期の一例を示す図である。It is a figure which shows an example of the execution period for every application. 軸制御アプリにおける共有変数毎の補正後のアクセス頻度の一例を示す図である。FIG. 10 is a diagram showing an example of access frequency after correction for each shared variable in an axis control application; 表示制御アプリにおける共有変数毎の補正後のアクセス頻度の一例を示す図である。FIG. 10 is a diagram showing an example of access frequency after correction for each shared variable in the display control application; 周辺機器制御アプリにおける共有変数毎の補正後のアクセス頻度の一例を示す図である。FIG. 10 is a diagram showing an example of corrected access frequency for each shared variable in a peripheral device control application; 数値制御装置の配置最適化処理について説明するフローチャートである。4 is a flowchart for explaining placement optimization processing of a numerical control device; 第２実施形態に係る数値制御装置の機能的構成例を示す機能ブロック図である。FIG. 7 is a functional block diagram showing a functional configuration example of a numerical controller according to a second embodiment; 情報処理装置の機能的構成例を示す機能ブロック図である。2 is a functional block diagram showing a functional configuration example of an information processing device; FIG. 第３実施形態に係る数値制御装置の機能的構成例を示す機能ブロック図である。FIG. 11 is a functional block diagram showing a functional configuration example of a numerical controller according to a third embodiment; 情報処理装置の機能的構成例を示す機能ブロック図である。2 is a functional block diagram showing a functional configuration example of an information processing device; FIG. 評価パラメータ記憶部に格納される評価パラメータの一例を示す図である。It is a figure which shows an example of the evaluation parameter stored in an evaluation parameter memory|storage part. アクセス頻度評価部の動作を説明する一例を示す図である。It is a figure which shows an example explaining operation|movement of an access frequency evaluation part. アプリ間で連携される共有変数の一例を示す図である。It is a figure which shows an example of the shared variable linked between applications.
　制御装置の具体的な実施形態について説明するにあたり、最初に制御装置の基本動作について説明する。
　図１は、制御装置の機能的構成例を示す機能ブロック図である。
　図１に示すように、制御装置１は、例えば、工作機械やロボット等を制御し、制御モジュール２、ｎ個のプロセッサモジュール３－１～３－ｎ、及び記憶部４を有する（ｎは２以上の整数である）。制御モジュール２、プロセッサモジュール３－１～３－ｎ、及び記憶部４は、バス５を介して通信可能に接続される。 Before describing a specific embodiment of the control device, the basic operation of the control device will be described first.
FIG. 1 is a functional block diagram showing a functional configuration example of a control device.
As shown in FIG. 1, the control device 1 controls, for example, machine tools, robots, etc., and has a control module 2, n processor modules 3-1 to 3-n, and a storage unit 4 (n is 2 is an integer greater than or equal to ). The control module 2, processor modules 3-1 to 3-n, and storage unit 4 are communicably connected via a bus 5. FIG.
　記憶部４は、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）等のメインメモリであり、制御モジュール２が実行するシステムプログラム及びアプリケーションプログラムとともに、後述するプロセッサモジュール３－１～３－ｎそれぞれが実行するｎ個の実行形式の実行プログラム４０－１～４０－ｎが格納されてもよい。また、記憶部４は、共有変数情報４１を含む。
　共有変数情報４１は、例えば、実行プログラム４０－１～４０－ｎの間で連携して動作させるための少なくとも共有変数の仮想アドレス及び共有変数の物理アドレスを含む共有変数に関する情報を含む。 The storage unit 4 is a main memory such as a ROM (Read Only Memory), and stores a system program and an application program executed by the control module 2, as well as n executions executed by each of the processor modules 3-1 to 3-n described later. format execution programs 40-1 to 40-n may be stored. The storage unit 4 also includes shared variable information 41 .
The shared variable information 41 includes, for example, information on shared variables including at least virtual addresses of shared variables and physical addresses of shared variables for cooperative operation among the execution programs 40-1 to 40-n.
　プロセッサモジュール３－１～３－ｎは、例えば、ＣＰＵ３０、及びローカルメモリ２２を有し、後述する制御モジュール２の制御指示に基づいて、例えば軸制御や表示制御等の実行プログラム４０－１～４０－ｎそれぞれを実行する。 The processor modules 3-1 to 3-n have, for example, a CPU 30 and a local memory 22, and execute execution programs 40-1 to 40 for axis control, display control, etc. based on control instructions from the control module 2, which will be described later. -n each run.
　制御モジュール２は、ＣＰＵ２１と、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）等のローカルメモリ２２と、を有する。
　ＣＰＵ２１は制御装置１を全体的に制御するプロセッサである。ＣＰＵ２１は、メインメモリである記憶部４に格納されたシステムプログラム及び後述する機能部を実行するためのアプリケーションプログラムを、バス５を介して読み出し、ローカルメモリ２２にロードし、システムプログラム及び当該アプリケーションプログラムに従って制御装置１全体を制御する。これにより、図１に示すように、ＣＰＵ２１が、アクセス頻度評価部２１－１、及びメモリ配置最適化部２１－２の機能を実現するように構成される。 The control module 2 has a CPU 21 and a local memory 22 such as a RAM (Random Access Memory).
The CPU 21 is a processor that controls the control device 1 as a whole. The CPU 21 reads, via the bus 5, a system program stored in the storage unit 4, which is a main memory, and an application program for executing a function unit described later, loads them into the local memory 22, and stores the system program and the application program. The entire control device 1 is controlled according to. Thereby, as shown in FIG. 1, the CPU 21 is configured to implement the functions of the access frequency evaluation unit 21-1 and the memory allocation optimization unit 21-2.
　アクセス頻度評価部２１－１は、例えば、プロセッサモジュール３－１～３－ｎのＣＰＵ３０それぞれが実行する実行プログラム４０－１～４０－ｎ毎に共有変数情報４１に含まれる共有変数へのアクセス頻度を評価する。 The access frequency evaluation unit 21-1, for example, calculates the frequency of access to the shared variables included in the shared variable information 41 for each of the execution programs 40-1 to 40-n executed by the CPUs 30 of the processor modules 3-1 to 3-n. Evaluate.
　メモリ配置最適化部２１－２は、アクセス頻度評価部２１－１により評価されたアクセス頻度に基づいて共有変数を、プロセッサモジュール３－１～３－ｎのうち配置するローカルメモリ３１を変更する。
　そうすることにより、制御装置１は、各ＣＰＵ３０が実行するアプリの共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数を当該アプリが実行されるＣＰＵのローカルメモリに配置することができる。
　以上、制御装置の基本動作について説明した。 The memory allocation optimization unit 21-2 changes the local memory 31 in which the shared variables are allocated among the processor modules 3-1 to 3-n based on the access frequency evaluated by the access frequency evaluation unit 21-1.
By doing so, the control device 1 can analyze the access frequency of the application executed by each CPU 30 to the shared variable, and arrange the shared variable with high access frequency in the local memory of the CPU executing the application. .
The basic operation of the control device has been described above.
　次に、制御装置の具体的な実施形態について、制御装置として数値制御装置を例示して説明する。なお、本発明は、数値制御装置に限定されず、例えば産業用ロボット等を制御する、複数のプロセッサを備えるロボット制御装置に対しても適用可能である。また、複数のプロセッサを備える、任意の制御装置に対しても適用可能である。
　また、複数のプロセッサそれぞれにおいて実行する実行プログラムとして、軸制御アプリ、表示制御アプリ、周辺機器制御アプリを例示して説明するが、これ以外の任意のアプリの実行プログラムに対しても適用可能である。なお、各プロセッサにおいて、複数のプログラムを実行させるようにしてもよい。また、ロボット制御装置、及び任意の制御装置において、各プロセッサにおいて複数のプログラムを実行させる場合にも適用される。
　まず、第１実施形態について説明する。
＜第１実施形態＞
　図２は、第１実施形態に係る数値制御装置の機能的構成例を示す機能ブロック図である。
　また、複数のＣＰＵそれぞれが実行するアプリとして、前述したように軸制御アプリ、表示制御アプリ、周辺機器制御アプリを例示する。なお、本発明は、軸制御アプリ、表示制御アプリ、周辺機器制御アプリに限定されず、軸制御アプリ、表示制御アプリ、周辺機器制御アプリ以外の任意のアプリに対しても適用可能である。
　図２に示すように、数値制御装置１０は、当業者にとって公知の数値制御装置であり、例えば、図示しないＣＡＤ／ＣＡＭ装置等から取得した加工プログラムに基づいて動作指令を生成し、生成した動作指令を工作機械（図示しない）に送信する。これにより、数値制御装置１０は、図示しない工作機械の動作を制御する。なお、図示しない工作機械がロボット等の場合、数値制御装置１０は、ロボット制御装置等でもよい。 Next, a specific embodiment of the control device will be described by exemplifying a numerical control device as the control device. It should be noted that the present invention is not limited to numerical control devices, but can also be applied to robot control devices having a plurality of processors that control industrial robots, for example. It is also applicable to any control device with multiple processors.
Further, although an axis control application, a display control application, and a peripheral device control application will be exemplified as execution programs to be executed in each of a plurality of processors, the present invention can also be applied to execution programs of arbitrary applications other than these. . Note that each processor may execute a plurality of programs. Moreover, in a robot control device and an arbitrary control device, the present invention can be applied to the case where each processor executes a plurality of programs.
First, the first embodiment will be explained.
<First embodiment>
FIG. 2 is a functional block diagram showing a functional configuration example of the numerical controller according to the first embodiment.
Also, as applications executed by each of the plurality of CPUs, the axis control application, the display control application, and the peripheral device control application are exemplified as described above. The present invention is not limited to axis control applications, display control applications, and peripheral device control applications, and can be applied to arbitrary applications other than axis control applications, display control applications, and peripheral device control applications.
As shown in FIG. 2, the numerical control device 10 is a numerical control device known to those skilled in the art. Send commands to a machine tool (not shown). Thereby, the numerical controller 10 controls the operation of the machine tool (not shown). If the machine tool (not shown) is a robot or the like, the numerical controller 10 may be a robot controller or the like.
　図２に示すように、数値制御装置１０は、システム制御モジュール１１０、軸制御モジュール１２０、表示制御モジュール１３０、周辺機器制御モジュール１４０、及び記憶部１５０を有する。システム制御モジュール１１０、軸制御モジュール１２０、表示制御モジュール１３０、周辺機器制御モジュール１４０、及び記憶部１５０は、バス１６０を介して通信可能に接続される。
　システム制御モジュール１１０は、ＣＰＵ１１１、及びローカルメモリ１１２を有する。また、ＣＰＵ１１１は、アクセス頻度評価部１１１１、及びメモリ配置最適化部１１１２を有する。また、軸制御モジュール１２０は、ＣＰＵ１２１、及びローカルメモリ１２２を有する。また、表示制御モジュール１３０は、ＣＰＵ１３１、及びローカルメモリ１３２を有する。また、周辺機器制御モジュール１４０は、ＣＰＵ１４１、及びローカルメモリ１４２を有する。 As shown in FIG. 2 , the numerical controller 10 has a system control module 110 , an axis control module 120 , a display control module 130 , a peripheral device control module 140 and a storage section 150 . The system control module 110 , the axis control module 120 , the display control module 130 , the peripheral device control module 140 and the storage unit 150 are communicably connected via the bus 160 .
The system control module 110 has a CPU 111 and a local memory 112 . The CPU 111 also has an access frequency evaluation unit 1111 and a memory allocation optimization unit 1112 . The axis control module 120 also has a CPU 121 and a local memory 122 . Also, the display control module 130 has a CPU 131 and a local memory 132 . Also, the peripheral device control module 140 has a CPU 141 and a local memory 142 .
＜記憶部１５０＞
　記憶部１５０は、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）等のメインメモリである。記憶部１５０は、システムプログラム及び複数のアプリケーションプログラム（例えば、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３）が格納されてもよい。また、記憶部１５０は、後述する共有変数情報１５４を含む。 <Storage unit 150>
The storage unit 150 is a main memory such as a ROM (Read Only Memory). The storage unit 150 may store a system program and a plurality of application programs (eg, axis control application 151, display control application 152, peripheral device control application 153). The storage unit 150 also includes shared variable information 154, which will be described later.
　軸制御アプリ１５１は、例えば、工作機械（図示しない）に含まれる主軸等を制御する実行プログラムであり、後述する軸制御モジュール１２０にロードされ実行される。 The axis control application 151 is, for example, an execution program that controls a spindle or the like included in a machine tool (not shown), and is loaded into the axis control module 120 described later and executed.
　表示制御アプリ１５２は、例えば、数値制御装置１０に含まれるＬＣＤ（Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ　Ｄｉｓｐｌａｙ）等の表示装置の表示を制御する実行プログラムであり、後述する表示制御モジュール１３０にロードされ実行される。 The display control application 152 is, for example, an execution program that controls the display of a display device such as an LCD (Liquid Crystal Display) included in the numerical controller 10, and is loaded into the display control module 130 described later and executed.
　周辺機器制御アプリ１５３は、例えば、工作機械（図示しない）の周辺に配置された周辺機器を制御する実行プログラムであり、後述する周辺機器制御モジュール１４０にロードされ実行される。 The peripheral device control application 153 is, for example, an execution program that controls peripheral devices arranged around a machine tool (not shown), and is loaded into the peripheral device control module 140 described later and executed.
　共有変数情報１５４は、例えば、軸制御アプリ１５１、表示制御アプリ１５２、及び周辺機器制御アプリ１５３それぞれのアプリ間で、例えば連携して動作させるための共有変数に関する情報を含む。具体的には、それぞれのアプリが共有変数にアクセスするときに指定する共有変数と、当該共有変数の値を参照する際の仮想アドレスと、当該共有変数の値が実際に記憶されている物理アドレスと、の対応関係を含む。
　図３は、共有変数情報１５４の一例を示す図である。
　図３に示すように、共有変数情報１５４は、「共有変数」、「仮想アドレス」、及び「物理アドレス」の格納領域を有する。
　共有変数情報１５４内の「共有変数」の格納領域には、例えば、「ｘ」、「ｙ」、「ｚ」等の共有変数が格納される。
　共有変数情報１５４内の「仮想アドレス」の格納領域には、例えば、軸制御アプリ１５１、表示制御アプリ１５２、及び周辺機器制御アプリ１５３間で連携して動作するために割り当てられた共有変数ｘ、ｙ、ｚそれぞれに対応する仮想アドレス「ａａａａａａａａ」、「ｂｂｂｂｂｂｂｂ」、「ｃｃｃｃｃｃｃｃ」等が格納される。
　共有変数情報１５４内の「物理アドレス」の格納領域には、例えば、共有変数ｘ、ｙ、ｚ等それぞれが記憶されたローカルメモリに割り振られた際の実際の物理アドレス「ＸＸＸＸＸＸＸＸ」、「ＹＹＹＹＹＹＹＹ」、「ＺＺＺＺＺＺＺＺ」等が格納される。 The shared variable information 154 includes, for example, information on shared variables for cooperative operation among the axis control application 151, the display control application 152, and the peripheral device control application 153, for example. Specifically, the shared variable specified when each application accesses the shared variable, the virtual address used when referencing the value of the shared variable, and the physical address where the value of the shared variable is actually stored , and the corresponding relationship.
FIG. 3 is a diagram showing an example of the shared variable information 154. As shown in FIG.
As shown in FIG. 3, the shared variable information 154 has storage areas for "shared variables,""virtualaddresses," and "physical addresses."
In the storage area of "shared variables" in the shared variable information 154, shared variables such as "x", "y", and "z" are stored.
In the storage area of the "virtual address" in the shared variable information 154, for example, the shared variable x assigned for cooperative operation among the axis control application 151, the display control application 152, and the peripheral device control application 153, Virtual addresses such as "aaaaaaaa", "bbbbbbbb", "cccccccc" corresponding to y and z are stored.
In the "physical address" storage area in the shared variable information 154, for example, the actual physical addresses "XXXXXXXXX" and "YYYYYYYY" when allocated to the local memory storing the shared variables x, y, z, etc., respectively. , “ZZZZZZZZ” and the like are stored.
　＜システム制御モジュール１１０＞
　システム制御モジュール１１０は、数値制御装置１０全体を制御するモジュールであり、ＣＰＵ１１１と、ローカルメモリ１１２と、を有する。
　ローカルメモリ１１２は、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）等により構成される。
　ＣＰＵ１１１は数値制御装置１０を全体的に制御するプロセッサである。ＣＰＵ１１１は、メインメモリである記憶部１５０に格納されたシステムプログラム及び後述する機能部を実行するためのアプリケーションプログラムを、バス１６０を介して読み出し、ローカルメモリ１１２にロードし、システムプログラム及び当該アプリケーションプログラムに従って数値制御装置１０全体を制御する。これにより、図２に示すように、ＣＰＵ１１１が、アクセス頻度評価部１１１１、及びメモリ配置最適化部１１１２の機能を実現するように構成される。 <System control module 110>
The system control module 110 is a module that controls the entire numerical controller 10 and has a CPU 111 and a local memory 112 .
The local memory 112 is composed of a RAM (Random Access Memory) or the like.
A CPU 111 is a processor that controls the numerical controller 10 as a whole. The CPU 111 reads, via the bus 160, a system program stored in the storage unit 150, which is a main memory, and an application program for executing a function unit described later, loads the system program and the application program into the local memory 112, and loads the system program and the application program into the local memory 112. The entire numerical controller 10 is controlled according to the following. Thereby, as shown in FIG. 2, the CPU 111 is configured to implement the functions of the access frequency evaluation unit 1111 and the memory allocation optimization unit 1112 .
　アクセス頻度評価部１１１１は、例えば、後述する軸制御モジュール１２０のＣＰＵ１２１、表示制御モジュール１３０のＣＰＵ１３１、及び周辺機器制御モジュール１４０のＣＰＵ１４１それぞれが実行する軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３毎に共有変数情報１５４に含まれる共有変数ｘ、ｙ、ｚ等へのアクセス頻度を評価する。
　具体的には、アクセス頻度評価部１１１１は、主軸等を制御する実行プログラムである軸制御アプリ１５１をローカルメモリ１２２に展開（ロード）した際に、当該軸制御アプリ１５１が、例えば、共有変数ｘ、ｙ、ｚそれぞれに対する１実行周期あたりのアクセス回数（アクセス頻度）を取得する。
　同様に、アクセス頻度評価部１１１１は、後述するＣＰＵ１３１が記憶部１５０に記憶された、表示装置の表示を制御する実行プログラムである表示制御アプリ１５２をローカルメモリ１３２に展開（ロード）した際に、当該表示制御アプリ１５２が、例えば、共有変数ｘ、ｙ、ｚそれぞれに対する１実行周期あたりのアクセス回数（アクセス頻度）を取得する。
　同様に、アクセス頻度評価部１１１１は、後述するＣＰＵ１４１が記憶部１５０に記憶された周辺機器を制御する実行プログラムである周辺機器制御アプリ１５３をローカルメモリ１４２に展開（ロード）した際に、当該周辺機器制御アプリ１５３が、例えば、共有変数ｘ、ｙ、ｚそれぞれに対する１実行周期あたりのアクセス回数（アクセス頻度）を取得する。 The access frequency evaluation unit 1111 includes, for example, the axis control application 151, the display control application 152, the peripheral device control, and the CPU 121 of the axis control module 120, the CPU 131 of the display control module 130, and the CPU 141 of the peripheral device control module 140, which will be described later. The frequency of access to the shared variables x, y, z, etc. included in the shared variable information 154 is evaluated for each application 153 .
Specifically, when the axis control application 151, which is an execution program for controlling the spindle and the like, is expanded (loaded) into the local memory 122, the access frequency evaluation unit 1111 detects that the axis control application 151 is, for example, the shared variable x , y, and z in each execution cycle (access frequency).
Similarly, when the CPU 131, which will be described later, develops (loads) a display control application 152, which is an execution program for controlling the display of the display device, stored in the storage unit 150 into the local memory 132, the access frequency evaluation unit 1111 The display control application 152 acquires, for example, the number of accesses (access frequency) per execution cycle for each of the shared variables x, y, and z.
Similarly, when the CPU 141 (to be described later) develops (loads) a peripheral device control application 153, which is an execution program for controlling a peripheral device stored in the storage unit 150, into the local memory 142, the access frequency evaluation unit 1111 The device control application 153 acquires, for example, the number of accesses per execution cycle (access frequency) for each of the shared variables x, y, and z.
　このため、アクセス頻度評価部１１１１は、参照命令実行記録部１１１３を備えるようにしてもよい。
　ここで、参照命令実行記録部１１１３は、軸制御モジュール１２０のＣＰＵ１２１、表示制御モジュール１３０のＣＰＵ１３１、及び周辺機器制御モジュール１４０のＣＰＵ１４１それぞれが、主軸等を制御する実行プログラムである軸制御アプリ１５１をローカルメモリ１２２に、表示装置の表示を制御する実行プログラムである表示制御アプリ１５２をローカルメモリ１３２に、及び周辺機器を制御する実行プログラムである周辺機器制御アプリ１５３をローカルメモリ１４２に、展開（ロード）した際に、軸制御アプリ１５１、表示制御アプリ１５２、及び周辺機器制御アプリ１５３が、それぞれ１実行周期あたりにそれぞれの共有変数ｘ、ｙ、ｚにアクセスするアクセス回数を記録する。 Therefore, the access frequency evaluation unit 1111 may include a reference instruction execution recording unit 1113 .
Here, in the reference instruction execution recording unit 1113, each of the CPU 121 of the axis control module 120, the CPU 131 of the display control module 130, and the CPU 141 of the peripheral device control module 140 executes the axis control application 151, which is an execution program for controlling the spindle and the like. A display control application 152, which is an execution program for controlling the display of the display device, is expanded (loaded) into the local memory 122, and a peripheral device control application 153, which is an execution program for controlling peripheral devices, into the local memory 142. ), the axis control application 151, the display control application 152, and the peripheral device control application 153 record the number of accesses to the respective shared variables x, y, and z per execution cycle.
　そうすることで、アクセス頻度評価部１１１１は、当該軸制御アプリ１５１が１実行周期あたりにそれぞれの共有変数ｘ、ｙ、ｚにアクセスするアクセス回数を算出し、共有変数ｘ、ｙ、ｚそれぞれに対する１実行周期あたりのアクセス回数を軸制御アプリ１５１の共有変数へのアクセス頻度として記憶する。
　同様に、アクセス頻度評価部１１１１は、表示制御アプリ１５２が１実行周期あたりにそれぞれの共有変数ｘ、ｙ、ｚにアクセスするアクセス回数を算出し、共有変数ｘ、ｙ、ｚそれぞれに対する１実行周期あたりのアクセス回数を表示制御アプリ１５２の共有変数へのアクセス頻度として記憶する。
　同様に、アクセス頻度評価部１１１１は、周辺機器制御アプリ１５３が１実行周期あたりにそれぞれの共有変数ｘ、ｙ、ｚにアクセスするアクセス回数を算出し、共有変数ｘ、ｙ、ｚそれぞれに対する１実行周期あたりのアクセス回数を周辺機器制御アプリ１５３の共有変数へのアクセス頻度として記憶する。
　なお、１つのモジュール（例えば軸制御モジュール１２０）上で、複数の実行プログラムを実行する場合、各実行プログラムの共有変数に対する１実行周期あたりのアクセス回数を軸制御アプリ１５１の共有変数へのアクセス頻度として記憶するようにしてもよい。そうすることで、後述するメモリ配置最適化部１１１２は、当該プロセッサの共有変数へのアクセス頻度を算出することができる。 By doing so, the access frequency evaluation unit 1111 calculates the number of times the axis control application 151 accesses each of the shared variables x, y, and z in one execution cycle, and The number of accesses per execution cycle is stored as the access frequency to the shared variables of the axis control application 151 .
Similarly, the access frequency evaluation unit 1111 calculates the number of times the display control application 152 accesses each of the shared variables x, y, and z per execution cycle, The number of accesses per unit is stored as the frequency of access to the shared variable of the display control application 152 .
Similarly, the access frequency evaluation unit 1111 calculates the number of times the peripheral device control application 153 accesses each of the shared variables x, y, and z in one execution cycle, and calculates one execution for each of the shared variables x, y, and z. The number of accesses per period is stored as the access frequency to the shared variable of the peripheral device control application 153 .
Note that when a plurality of execution programs are executed on one module (for example, the axis control module 120), the number of accesses to the shared variables of each execution program per execution cycle is defined as the frequency of access to the shared variables of the axis control application 151. may be stored as By doing so, the memory allocation optimization unit 1112, which will be described later, can calculate the frequency of access to the shared variables of the processor.
　図４Ａは、軸制御アプリ１５１における共有変数毎のアクセス頻度の一例を示す図である。図４Ｂは、表示制御アプリ１５２における共有変数毎のアクセス頻度の一例を示す図である。図４Ｃは、周辺機器制御アプリ１５３における共有変数毎のアクセス頻度の一例を示す図である。
　図４Ａに示すように、軸制御アプリ１５１の場合には、共有変数ｘへのアクセス頻度は１実行周期あたり８０回／ｃｙｃｌｅである。また、図４Ｂに示すように、表示制御アプリ１５２の場合には、共有変数ｙへのアクセス頻度は、１実行周期あたり６０回／ｃｙｃｌｅである。また、図４Ｃに示すように、周辺機器制御アプリ１５３の場合には、共有変数ｚへのアクセス頻度は、１実行周期あたり５０回／ｃｙｃｌｅである。 FIG. 4A is a diagram showing an example of the access frequency for each shared variable in the axis control application 151. FIG. FIG. 4B is a diagram showing an example of the access frequency for each shared variable in the display control application 152. As shown in FIG. FIG. 4C is a diagram showing an example of the access frequency for each shared variable in the peripheral device control application 153. As shown in FIG.
As shown in FIG. 4A, in the case of the axis control application 151, the access frequency to the shared variable x is 80 times/cycle per execution cycle. Further, as shown in FIG. 4B, in the case of the display control application 152, the access frequency to the shared variable y is 60 times/cycle per one execution period. Also, as shown in FIG. 4C, in the case of the peripheral device control application 153, the access frequency to the shared variable z is 50 times/cycle per one execution period.
　なお、図５に示すように、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３毎に１実行周期が異なることから、後述するように、メモリ配置最適化部１１１２は、各アプリの１実行周期を整数倍することにより一致する時間Ｔを求め、求めた時間Ｔにおけるアプリ毎の共有変数ｘ、ｙ、ｚ等へのアクセス頻度に基づいて、各共有変数ｘ、ｙ、ｚ等への時間Ｔにおけるアクセス回数を算出し（「同一処理時間におけるアクセス頻度」、「補正後アクセス頻度」、又は、特に断らない限り単に「アクセス頻度」ともいう）、当該補正後アクセス頻度に基づいて、共有変数の値が記憶される物理アドレスの再編成を行うことができる。 As shown in FIG. 5, the axis control application 151, the display control application 152, and the peripheral device control application 153 have different execution cycles. The matching time T is obtained by multiplying one execution cycle by an integer, and based on the frequency of access to the shared variables x, y, z, etc. for each application in the obtained time T, each shared variable x, y, z, etc. (also referred to as "access frequency in the same processing time", "corrected access frequency", or simply "access frequency" unless otherwise specified), and based on the corrected access frequency, A reorganization of the physical addresses at which the values of shared variables are stored can be done.
　メモリ配置最適化部１１１２は、補正後のアクセス頻度（以下、特に断らない限り「アクセス頻度」ともいう）に基づいて共有変数を配置するローカルメモリを変更する。図６Ａ、図６Ｂ、及び図６Ｃに、それぞれ軸制御アプリ１５１、表示制御アプリ１５２、及び周辺機器制御アプリ１５３の補正後のアクセス頻度（アクセス頻度）を図示する。
　具体的には、メモリ配置最適化部１１１２は、軸制御アプリ１５１において最もアクセス頻度が高かった共有変数ｘを、配置先である軸制御アプリ１５１を実行する後述する軸制御モジュール１２０のローカルメモリ１２２に記憶するための物理アドレス（例えば、「ＡＡＡＡＡＡＡＡ」）を取得する。メモリ配置最適化部１１１２は、共有変数情報１５４に格納されている、配置対象の共有変数ｘの物理アドレスを、例えば「ＸＸＸＸＸＸＸＸ」から「ＡＡＡＡＡＡＡＡ」に変更し、共有変数ｘをローカルメモリ１２２の物理アドレス「ＡＡＡＡＡＡＡＡ」に配置する。
　また、メモリ配置最適化部１１１２は、表示制御アプリ１５２において最もアクセス頻度が高かった共有変数ｙを、配置先である表示制御アプリ１５２を実行する後述する表示制御モジュール１３０のローカルメモリ１３２に記憶するための物理アドレス（例えば、「ＢＢＢＢＢＢＢＢＢＢ」）を取得する。メモリ配置最適化部１１１２は、共有変数情報１５４に格納されている、配置対象の共有変数ｙの物理アドレスを、例えば「ＹＹＹＹＹＹＹＹ」から「ＢＢＢＢＢＢＢＢ」に変更し、共有変数ｙをローカルメモリ１３２の物理アドレス「ＢＢＢＢＢＢＢＢ」に配置する。
　また、メモリ配置最適化部１１１２は、周辺機器制御アプリ１５３において最もアクセス頻度が高かった共有変数ｚを、配置先である周辺機器制御アプリ１５３を実行する後述する周辺機器制御モジュール１４０のローカルメモリ１４２に記憶するための物理アドレス（例えば、「ＣＣＣＣＣＣＣＣ」）を取得する。メモリ配置最適化部１１１２は、共有変数情報１５４に格納されている、配置対象の共有変数ｚの物理アドレスを、例えば「ＺＺＺＺＺＺＺＺ」から「ＣＣＣＣＣＣＣＣ」に変更し、共有変数ｚをローカルメモリ１４２の物理アドレス「ＣＣＣＣＣＣＣＣ」に配置する。
　そうすることで、ＣＰＵ１２１、１３１、１４１は、バス１６０を経由したローカルメモリへのアクセスが減少し、処理時間を短縮することができる。 The memory allocation optimization unit 1112 changes the local memory in which shared variables are allocated based on the corrected access frequency (hereinafter also referred to as “access frequency” unless otherwise specified). 6A, 6B, and 6C show corrected access frequencies (access frequencies) of the axis control application 151, the display control application 152, and the peripheral device control application 153, respectively.
Specifically, the memory allocation optimization unit 1112 stores the shared variable x, which has the highest access frequency in the axis control application 151, in the local memory 122 of the axis control module 120 (to be described later) that executes the axis control application 151, which is the allocation destination. Obtain a physical address (eg, "AAAAAAA") to store in the . The memory allocation optimizing unit 1112 changes the physical address of the shared variable x to be allocated, which is stored in the shared variable information 154, from, for example, “XXXXXXXXX” to “AAAAAAAAA”, and moves the shared variable x to the physical address of the local memory 122. It is placed at the address "AAAAAAAA".
In addition, the memory allocation optimization unit 1112 stores the shared variable y with the highest access frequency in the display control application 152 in the local memory 132 of the later-described display control module 130 that executes the display control application 152, which is the allocation destination. Get a physical address (eg, “BBBBBBBBBB”) for The memory allocation optimization unit 1112 changes the physical address of the shared variable y to be allocated, which is stored in the shared variable information 154 , from “YYYYYYYY” to “BBBBBBBB”, for example, and places the shared variable y in the physical address of the local memory 132 . It is placed at the address "BBBBBBBB".
In addition, the memory allocation optimizing unit 1112 stores the shared variable z, which has the highest access frequency in the peripheral device control application 153, in the local memory 142 of the peripheral device control module 140 (to be described later) that executes the peripheral device control application 153, which is the allocation destination. Get a physical address (eg, "CCCCCCCC") to store in the . The memory allocation optimization unit 1112 changes the physical address of the shared variable z to be allocated, which is stored in the shared variable information 154 , from “ZZZZZZZZZZ” to “CCCCCCCC”, for example, and changes the shared variable z to the physical address of the local memory 142 . It is placed at the address "CCCCCCCC".
By doing so, the CPUs 121, 131, and 141 can reduce the access to the local memory via the bus 160 and shorten the processing time.
＜軸制御モジュール１２０＞
　軸制御モジュール１２０は、ＣＰＵ１２１と、ローカルメモリ１２２と、を有する。
　ＣＰＵ１２１は、軸制御アプリ１５１を実行することにより、工作機械（図示しない）に含まれる主軸やテーブルの位置及び傾きを変化させるＸ軸、Ｙ軸、Ｚ軸の３軸や、Ｘ軸、Ｙ軸、Ｚ軸、Ａ軸、Ｂ軸の５軸等それぞれを制御する。
　ローカルメモリ１２２は、ＲＡＭ等であり、ＣＰＵ１２１により実行される軸制御アプリ１５１がロードされ、実行時には、メモリ配置最適化部１１１２により最適配置された共有変数ｘにアクセスすることができる。
　なお、軸制御モジュール１２０は、Ｘ軸、Ｙ軸、Ｚ軸の３軸、又はＸ軸、Ｙ軸、Ｚ軸、Ａ軸、Ｂ軸の５軸等それぞれを制御するとしたが、これに限定されない。例えば、数値制御装置１０は、各軸を制御する複数の軸制御モジュール１２０を有してもよい。 <Axis control module 120>
The axis control module 120 has a CPU 121 and a local memory 122 .
By executing the axis control application 151, the CPU 121 controls the three axes of the X, Y, and Z axes that change the position and inclination of the spindle and table included in the machine tool (not shown), and the X and Y axes. , Z-axis, A-axis, and B-axis.
The local memory 122 is a RAM or the like, in which the axis control application 151 executed by the CPU 121 is loaded, and can access the shared variable x optimally allocated by the memory allocation optimization unit 1112 during execution.
Although the axis control module 120 controls three axes of the X axis, the Y axis, and the Z axis, or five axes of the X axis, the Y axis, the Z axis, the A axis, and the B axis, etc., the axis control module 120 is not limited to this. . For example, the numerical controller 10 may have multiple axis control modules 120 that control each axis.
＜表示制御モジュール１３０＞
　表示制御モジュール１３０は、ＣＰＵ１３１と、ローカルメモリ１３２と、を有する。
　ＣＰＵ１３１は、表示制御アプリ１５２を実行することにより、工作機械（図示しない）の表示装置の表示を制御する。
　ローカルメモリ１３２は、ＲＡＭ等であり、ＣＰＵ１３１により実行される表示制御アプリ１５２がロードされ、実行時には、メモリ配置最適化部１１１２により最適配置された共有変数ｙにアクセスすることができる。 <Display control module 130>
The display control module 130 has a CPU 131 and a local memory 132 .
The CPU 131 executes the display control application 152 to control the display of the display device of the machine tool (not shown).
The local memory 132 is a RAM or the like, loads the display control application 152 executed by the CPU 131, and can access the shared variable y optimally allocated by the memory allocation optimization unit 1112 during execution.
＜周辺機器制御モジュール１４０＞
　周辺機器制御モジュール１４０は、ＣＰＵ１４１と、ローカルメモリ１４２と、を有する。
　ＣＰＵ１４１は、周辺機器制御アプリ１５３を実行することにより、工作機械（図示しない）の周辺に配置された周辺機器を制御する。
　ローカルメモリ１４２は、ＲＡＭ等であり、ＣＰＵ１４１により実行される周辺機器制御アプリ１５３がロードされ、実行時には、メモリ配置最適化部１１１２により最適配置された共有変数ｚにアクセスすることができる。 <Peripheral Device Control Module 140>
The peripheral device control module 140 has a CPU 141 and a local memory 142 .
The CPU 141 controls peripheral devices arranged around the machine tool (not shown) by executing the peripheral device control application 153 .
The local memory 142 is a RAM or the like, loads the peripheral device control application 153 executed by the CPU 141, and can access the shared variable z optimally allocated by the memory allocation optimization unit 1112 during execution.
＜数値制御装置１０の配置最適化処理＞
　次に、図７を参照しながら、数値制御装置１０の配置最適化処理の流れを説明する。
　図７は、数値制御装置１０の配置最適化処理について説明するフローチャートである。ここで示すフローは、数値制御装置１０がアプリをロードする際に、繰り返し実行される。 <Placement Optimization Processing of Numerical Control Device 10>
Next, with reference to FIG. 7, the flow of the arrangement optimization processing of the numerical controller 10 will be described.
FIG. 7 is a flowchart for explaining the placement optimization processing of the numerical controller 10. As shown in FIG. The flow shown here is repeatedly executed when the numerical controller 10 loads an application.
　ステップＳ１１において、アクセス頻度評価部１１１１は、軸制御モジュール１２０のＣＰＵ１２１、表示制御モジュール１３０のＣＰＵ１３１、又は周辺機器制御モジュール１４０のＣＰＵ１４１が記憶部１５０に記憶された軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３をローカルメモリに展開する際に、１実行周期あたりの共有変数ｘ、ｙ、ｚそれぞれへのアクセス頻度を算出する。 In step S11, the access frequency evaluation unit 1111 determines whether the CPU 121 of the axis control module 120, the CPU 131 of the display control module 130, or the CPU 141 of the peripheral device control module 140 stores the axis control application 151 and the display control application 152 in the storage unit 150. , the frequency of access to each of the shared variables x, y, and z per one execution cycle is calculated when the peripheral device control application 153 is developed in the local memory.
　ステップＳ１２において、アクセス頻度評価部１１１１は、全てのアプリのアクセス頻度を算出したか否かを判定する。全てのアプリのアクセス頻度を算出した場合、処理はステップＳ１３に進む。一方、全てのアプリのアクセス頻度を算出していない場合、処理はステップＳ１１に戻る。 In step S12, the access frequency evaluation unit 1111 determines whether or not the access frequencies of all applications have been calculated. When the access frequencies of all applications have been calculated, the process proceeds to step S13. On the other hand, if the access frequencies of all applications have not been calculated, the process returns to step S11.
　ステップＳ１３において、メモリ配置最適化部１１１２は、ステップＳ１１で算出した軸制御アプリ１５１、表示制御アプリ１５２、又は周辺機器制御アプリ１５３のアプリのアクセス頻度を取得する。 In step S13, the memory allocation optimization unit 1112 acquires the application access frequency of the axis control application 151, the display control application 152, or the peripheral device control application 153 calculated in step S11.
　ステップＳ１４において、メモリ配置最適化部１１１２は、ステップＳ１３で取得した共有変数へのアクセス頻度をアプリ間で比較し、当該共有変数へのアクセス頻度が最も高いアプリを特定し、当該アプリを実行する軸制御モジュール１２０のローカルメモリ１２２、表示制御モジュール１３０のローカルメモリ１３２、又は周辺機器制御モジュール１４０のローカルメモリ１４２の物理アドレスを取得する。メモリ配置最適化部１１１２は、共有変数情報１５４に格納されている配置対象の共有変数の物理アドレスを取得した物理アドレスに変更して、共有変数をローカルメモリに配置する。 In step S14, the memory allocation optimization unit 1112 compares the frequency of access to the shared variables acquired in step S13 among the applications, identifies the application with the highest access frequency to the shared variable, and executes the application. Obtain the physical address of the local memory 122 of the axis control module 120 , the local memory 132 of the display control module 130 , or the local memory 142 of the peripheral device control module 140 . The memory placement optimization unit 1112 changes the physical address of the shared variable to be placed stored in the shared variable information 154 to the acquired physical address, and places the shared variable in the local memory.
　ステップＳ１５において、メモリ配置最適化部１１１２は、全ての共有変数をローカルメモリに配置したか否かを判定する。全ての共有変数をローカルメモリに配置した場合、配置最適化処理は終了する。一方、全ての共有変数をローカルメモリに配置していない場合、処理はステップＳ１３に戻る。 In step S15, the memory placement optimization unit 1112 determines whether all shared variables have been placed in the local memory. When all shared variables have been placed in the local memory, the placement optimization process ends. On the other hand, if all shared variables have not been placed in the local memory, the process returns to step S13.
　以上により、第１実施形態に係る数値制御装置１０は、各ＣＰＵ１２１、１３１、１４１が実行する軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３の共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数をアプリが実行されるＣＰＵのローカルメモリに配置することができる。
　そして、数値制御装置１０は、記憶部１５０へのアクセスが減少し、処理時間を短縮することができる。
　以上、第１実施形態について説明した。 As described above, the numerical controller 10 according to the first embodiment analyzes the frequency of access to the shared variables of the axis control application 151, the display control application 152, and the peripheral device control application 153 executed by the respective CPUs 121, 131, and 141, Shared variables with high access frequency can be placed in the local memory of the CPU where the application is executed.
In addition, the numerical controller 10 can reduce access to the storage unit 150 and shorten the processing time.
The first embodiment has been described above.
＜第２実施形態＞
　次に、第２実施形態について説明する。第２実施形態では、数値制御装置１０Ａは、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３のソースプログラムから共有変数への参照命令数を外部装置から取得し、取得した参照命令数に基づいて共有変数へのアクセス頻度を評価する点で、第１実施形態と相違する。
　これにより、第２実施形態の数値制御装置１０Ａは、各ＣＰＵが実行するアプリの共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数を当該アプリが実行されるＣＰＵのローカルメモリに配置することができる。
　以下に、第２実施形態について説明する。 <Second embodiment>
Next, a second embodiment will be described. In the second embodiment, the numerical controller 10A acquires from an external device the number of reference instructions to shared variables from the source programs of the axis control application 151, the display control application 152, and the peripheral device control application 153, and is different from the first embodiment in that the access frequency to the shared variable is evaluated based on .
As a result, the numerical controller 10A of the second embodiment analyzes the frequency of access to the shared variables of the applications executed by each CPU, and arranges the shared variables with high access frequency in the local memory of the CPU executing the applications. can do.
A second embodiment will be described below.
　図８は、第２実施形態に係る数値制御装置１０Ａの機能的構成例を示す機能ブロック図である。なお、図２の数値制御装置１０の要素と同様の機能を有する要素については、同じ符号を付し、詳細な説明は省略する。
　図８に示すように、数値制御装置１０Ａは、情報処理装置２０と図示しない接続インタフェースを介して互いに直接接続されてもよい。また、数値制御装置１０Ａは、情報処理装置２０とＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）やインターネット等の図示しないネットワークを介して接続されていてもよい。この場合、数値制御装置１０Ａ、及び情報処理装置２０は、かかる接続によって相互に通信を行うための図示しない通信部を備えている。
　なお、数値制御装置１０Ａは、１つの情報処理装置２０と接続されているが、複数の情報処理装置２０と接続されてもよい。 FIG. 8 is a functional block diagram showing a functional configuration example of a numerical controller 10A according to the second embodiment. Elements having functions similar to those of the numerical control device 10 in FIG.
As shown in FIG. 8, the numerical control device 10A may be directly connected to the information processing device 20 via a connection interface (not shown). Further, the numerical control device 10A may be connected to the information processing device 20 via a network (not shown) such as a LAN (Local Area Network) or the Internet. In this case, the numerical control device 10A and the information processing device 20 are provided with a communication section (not shown) for mutual communication through such connection.
Although the numerical control device 10A is connected to one information processing device 20, it may be connected to a plurality of information processing devices 20. FIG.
＜情報処理装置２０＞
　情報処理装置２０は、例えば、コンピュータやタブレット端末等である。
　図９は、情報処理装置２０の機能的構成例を示す機能ブロック図である。
　図９に示すように、情報処理装置２０は、制御部２１０、及び記憶部２２０を有する。さらに、制御部２１０は、解析部２１１、及びコンパイル部２１２を有する。 <Information processing device 20>
The information processing device 20 is, for example, a computer, a tablet terminal, or the like.
FIG. 9 is a functional block diagram showing a functional configuration example of the information processing device 20. As shown in FIG.
As shown in FIG. 9 , the information processing device 20 has a control section 210 and a storage section 220 . Furthermore, the control unit 210 has an analysis unit 211 and a compilation unit 212 .
＜記憶部２２０＞
　記憶部２２０は、ＲＡＭやＨＤＤ（Ｈａｒｄ　Ｄｉｓｋ　Ｄｒｉｖｅ）等であり、システムプログラム及び複数のアプリケーションプログラムが格納されてもよい。記憶部２２０は、軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、及び周辺機器制御ソースプログラム２２３を含む。
　軸制御ソースプログラム２２１は、数値制御装置１０Ａの記憶部１５０に記憶される軸制御アプリ１５１のソースプログラムである。
　表示制御ソースプログラム２２２は、数値制御装置１０Ａの記憶部１５０に記憶される表示制御アプリ１５２のソースプログラムである。
　周辺機器制御ソースプログラム２２３は、数値制御装置１０Ａの記憶部１５０に記憶される周辺機器制御アプリ１５３のソースプログラムである。 <Storage unit 220>
The storage unit 220 is a RAM, HDD (Hard Disk Drive), or the like, and may store a system program and a plurality of application programs. The storage unit 220 includes an axis control source program 221 , a display control source program 222 and a peripheral device control source program 223 .
The axis control source program 221 is the source program of the axis control application 151 stored in the storage unit 150 of the numerical controller 10A.
The display control source program 222 is the source program of the display control application 152 stored in the storage unit 150 of the numerical controller 10A.
The peripheral device control source program 223 is the source program of the peripheral device control application 153 stored in the storage unit 150 of the numerical controller 10A.
＜制御部２１０＞
　制御部２１０は、ＣＰＵ、ＲＯＭ、ＲＡＭ、ＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）メモリ等を有し、これらはバスを介して相互に通信可能に構成される、当業者にとって公知のものである。
　ＣＰＵは情報処理装置２０を全体的に制御するプロセッサである。ＣＰＵは、ＲＯＭに格納されたシステムプログラム及び後述する機能部を実行するためのアプリケーションプログラムを、バスを介して読み出し、メモリ（図示せず）にロードし、システムプログラム及び当該アプリケーションプログラムに従って情報処理装置２０全体を制御する。これにより、図９に示すように、制御部２１０が、解析部２１１、及びコンパイル部２１２の機能を実現するように構成される。ＲＡＭには一時的な計算データや表示データ等の各種データが格納される。また、ＣＭＯＳメモリは図示しないバッテリでバックアップされ、情報処理装置２０の電源がオフされても記憶状態が保持される不揮発性メモリとして構成される。 <Control unit 210>
The control unit 210 has a CPU, a ROM, a RAM, a CMOS (Complementary Metal-Oxide-Semiconductor) memory, etc., which are known to those skilled in the art and are configured to communicate with each other via a bus.
The CPU is a processor that controls the information processing device 20 as a whole. The CPU reads the system program stored in the ROM and the application program for executing the function units described later via the bus, loads them into a memory (not shown), and executes the information processing apparatus according to the system program and the application program. 20 as a whole. Thereby, as shown in FIG. 9, the control unit 210 is configured to implement the functions of the analysis unit 211 and the compilation unit 212 . Various data such as temporary calculation data and display data are stored in the RAM. Further, the CMOS memory is backed up by a battery (not shown) and configured as a non-volatile memory that retains the memory state even when the information processing apparatus 20 is powered off.
　解析部２１１は、例えば、情報処理装置２０に含まれるキーボードやタッチパネル等の入力装置（図示しない）を介してユーザから軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、及び周辺機器制御ソースプログラム２２３のソースプログラムに対する解析指示を受け付けた場合、各ソースプログラムを解析し、ソースプログラムの最初から最後まで（すなわち、１実行周期）における共有変数ｘ、ｙ、ｚ等それぞれを参照する制御文の数を共有変数毎に参照命令数として求める。解析部２１１は、求めた各プログラムの共有変数ｘ、ｙ、ｚ等の参照命令数を、例えば各プログラムの実行形式のプログラムに格納するようにしてもよい。そうすることで、当該実行プログラムを数値制御装置１０Ａにおける、後述するそれぞれのローカルメモリに展開（ロード）した際に、数値制御装置１０Ａ（アクセス頻度評価部）は、各プログラムの共有変数ｘ、ｙ、ｚ等の参照命令数を取得することができる。 The analysis unit 211 receives, for example, an axis control source program 221, a display control source program 222, and a peripheral device control source program 223 from a user via an input device (not shown) such as a keyboard or touch panel included in the information processing device 20. When an analysis instruction for a source program is received, each source program is analyzed, and the number of control statements that refer to shared variables x, y, z, etc. from the beginning to the end of the source program (that is, one execution cycle) is shared. Obtained as the number of reference instructions for each variable. The analysis unit 211 may store the obtained number of reference instructions such as the shared variables x, y, and z of each program in the execution format of each program, for example. By doing so, when the execution program is expanded (loaded) into respective local memories (to be described later) in the numerical control device 10A, the numerical control device 10A (access frequency evaluation unit) uses shared variables x, y , z, etc. can be obtained.
　コンパイル部２１２は、例えば、情報処理装置２０の入力装置（図示しない）を介してユーザから軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、又は周辺機器制御ソースプログラム２２３のコンパイル指示を受け付けた場合、軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、又は周辺機器制御ソースプログラム２２３をコンパイルし、実行プログラムの軸制御アプリ１５１、表示制御アプリ１５２、又は周辺機器制御アプリ１５３を生成する。コンパイル部２１２は、生成した表示制御アプリ１５２、又は周辺機器制御アプリ１５３を数値制御装置１０Ａに送信する。
　なお、コンパイル部２１２は、解析部２１１の機能を有してもよい。そうすることで、コンパイル部２１２は、コンパイル指示を受け付けた場合に、前述したように、各プログラムの共有変数ｘ、ｙ、ｚ等の参照命令数を算出し、参照命令数を、各プログラムの実行形式のプログラムに格納することができる。 For example, when the compiling unit 212 receives an instruction to compile the axis control source program 221, the display control source program 222, or the peripheral device control source program 223 from the user via the input device (not shown) of the information processing device 20, The axis control source program 221, the display control source program 222, or the peripheral device control source program 223 is compiled to generate the axis control application 151, the display control application 152, or the peripheral device control application 153 of the execution program. The compiling unit 212 transmits the generated display control application 152 or peripheral device control application 153 to the numerical controller 10A.
Note that the compilation unit 212 may have the function of the analysis unit 211 . By doing so, when receiving a compilation instruction, the compiling unit 212 calculates the number of reference instructions such as the shared variables x, y, and z of each program, and calculates the number of reference instructions of each program as described above. It can be stored in an executable program.
＜数値制御装置１０Ａ＞
　数値制御装置１０Ａは、図８に示すように、システム制御モジュール１１０ａ、軸制御モジュール１２０、表示制御モジュール１３０、周辺機器制御モジュール１４０、及び記憶部１５０を有する。 <Numerical control device 10A>
The numerical controller 10A has a system control module 110a, an axis control module 120, a display control module 130, a peripheral device control module 140, and a storage section 150, as shown in FIG.
　＜システム制御モジュール１１０ａ＞
　システム制御モジュール１１０ａは、ＣＰＵ１１１ａと、ローカルメモリ１１２と、を有する。また、ＣＰＵ１１１ａは、アクセス頻度評価部１１１１ａ、及びメモリ配置最適化部１１１２を有する。
　メモリ配置最適化部１１１２は、第１実施形態におけるメモリ配置最適化部１１１２と同等の機能を有する。
　ＣＰＵ１１１ａは、第１実施形態のＣＰＵ１１１と同様に、数値制御装置１０Ａを全体的に制御するプロセッサである。ＣＰＵ１１１ａは、メインメモリである記憶部１５０に格納されたシステムプログラム及び後述する機能部を実行するためのアプリケーションプログラムを、バス１６０を介して読み出し、ローカルメモリ１１２にロードし、システムプログラム及び当該アプリケーションプログラムに従って数値制御装置１０Ａ全体を制御する。これにより、図８に示すように、ＣＰＵ１１１ａが、アクセス頻度評価部１１１１ａ、及びメモリ配置最適化部１１１２の機能を実現するように構成される。 <System Control Module 110a>
The system control module 110 a has a CPU 111 a and a local memory 112 . The CPU 111 a also has an access frequency evaluation unit 1111 a and a memory allocation optimization unit 1112 .
The memory layout optimization unit 1112 has functions equivalent to those of the memory layout optimization unit 1112 in the first embodiment.
The CPU 111a is a processor that controls the numerical controller 10A as a whole, like the CPU 111 of the first embodiment. The CPU 111a reads, via the bus 160, a system program stored in the storage unit 150, which is a main memory, and an application program for executing a function unit described later, loads them into the local memory 112, and stores the system program and the application program. The entire numerical controller 10A is controlled according to the following. Thereby, as shown in FIG. 8, the CPU 111a is configured to implement the functions of the access frequency evaluation unit 1111a and the memory allocation optimization unit 1112. FIG.
　アクセス頻度評価部１１１１ａは、情報処理装置２０の解析部２１１による軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３のソースプログラムである軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、周辺機器制御ソースプログラム２２３の解析から求めた共有変数ｘ、ｙ、ｚ等への参照命令数を情報処理装置２０から取得する。
　アクセス頻度評価部１１１１ａは、取得した実行プログラム、すなわち軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３それぞれにおける共有変数ｘ、ｙ、ｚ等への参照命令数に基づいて１実行周期あたりの共有変数ｘ、ｙ、ｚ等へのアクセス頻度を評価する。 The access frequency evaluation unit 1111a is an axis control source program 221, a display control source program 222, and a peripheral device, which are source programs for the axis control application 151, the display control application 152, and the peripheral device control application 153. The number of reference instructions to the shared variables x, y, z, etc. obtained from the analysis of the control source program 223 is acquired from the information processing device 20 .
The access frequency evaluation unit 1111a per execution cycle based on the number of reference instructions to the shared variables x, y, z, etc. in each of the acquired execution programs, that is, the axis control application 151, the display control application 152, and the peripheral device control application 153. Evaluate the frequency of access to shared variables x, y, z, etc. in .
　なお、数値制御装置１０Ａの配置最適化処理は、アクセス頻度評価部１１１１ａが情報処理装置２０から参照命令数を取得する点を除き図７に示す処理と同様であり、詳細な説明は省略する。 Note that the arrangement optimization processing of the numerical control device 10A is the same as the processing shown in FIG. 7 except that the access frequency evaluation unit 1111a acquires the number of reference instructions from the information processing device 20, and detailed description thereof will be omitted.
　以上により、第２実施形態に係る数値制御装置１０Ａは、情報処理装置２０による軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３のソースプログラムである軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、周辺機器制御ソースプログラム２２３の解析から求めた共有変数へのアクセス頻度を情報処理装置２０から取得する。数値制御装置１０Ａは、取得した各共有変数へのアクセス頻度を評価することで、アクセス頻度が最も高い共有変数をアプリが実行されるＣＰＵのローカルメモリに配置することができる。
　そして、ＣＰＵ１２１、１３１、１４１は、バス１６０を経由したローカルメモリへのアクセスが減少し、処理時間を短縮することができる。
　以上、第２実施形態について説明した。 As described above, the numerical control device 10A according to the second embodiment includes the axis control source program 221, which is the source program of the axis control application 151, the display control application 152, and the peripheral device control application 153, and the display control source program. 222 , the frequency of access to the shared variables obtained from the analysis of the peripheral device control source program 223 is acquired from the information processing device 20 . By evaluating the frequency of access to each acquired shared variable, the numerical controller 10A can place the shared variable with the highest access frequency in the local memory of the CPU executing the application.
The CPUs 121, 131, and 141 can reduce the access to the local memory via the bus 160 and shorten the processing time.
The second embodiment has been described above.
＜第２実施形態の変形例＞
　第２実施形態に係る数値制御装置１０Ａは、アクセス頻度評価部１１１１ａを有したが、これに限定されない。例えば、情報処理装置２０は、アクセス頻度評価部１１１１ａを有してもよい。
　例えば、解析部２１１は、アクセス頻度評価部１１１１ａの機能を有し、各ソースプログラムの解析から求めた共有変数ｘ、ｙ、ｚ等への参照命令数に基づいて共有変数ｘ、ｙ、ｚ等へのアクセス頻度を評価し、評価したアクセス頻度を、例えば各プログラムの実行形式のプログラムに格納するようにしてもよい。そうすることで、当該実行プログラムを数値制御装置１０Ａにおける、それぞれのローカルメモリに展開（ロード）した際に、数値制御装置１０Ａ（メモリ配置最適化部）は、各プログラムの共有変数ｘ、ｙ、ｚ等を最適なローカルメモリに配置することができる。 <Modification of Second Embodiment>
Although the numerical controller 10A according to the second embodiment has the access frequency evaluation unit 1111a, it is not limited to this. For example, the information processing device 20 may have an access frequency evaluation unit 1111a.
For example, the analysis unit 211 has the function of the access frequency evaluation unit 1111a, and calculates the shared variables x, y, z, etc. based on the number of reference instructions to the shared variables x, y, z, etc. obtained from the analysis of each source program. The access frequency may be evaluated, and the evaluated access frequency may be stored, for example, in the executable form of each program. By doing so, when the execution program is developed (loaded) into each local memory in the numerical control device 10A, the numerical control device 10A (memory allocation optimization unit) can set the shared variables x, y, z etc. can be placed in the optimal local memory.
＜第３実施形態＞
　次に、第３実施形態について説明する。第３実施形態では、数値制御装置１０Ｂは、アクセス頻度の評価に用いる評価パラメータを格納し、共有変数への参照命令数を外部装置としての情報処理装置２０Ｂから取得する場合、アプリのソースプログラム中の制御文毎の参照命令数を評価パラメータによる重み付けを行い補正し、補正した参照命令数に基づいて共有変数へのアクセス頻度を評価する点で、第１実施形態、及び第２実施形態と相違する。
　これにより、第３実施形態の数値制御装置１０Ｂは、各ＣＰＵが実行するアプリの共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数を当該アプリが実行されるＣＰＵのローカルメモリに配置することができる。
　以下に、第３実施形態について説明する。 <Third Embodiment>
Next, a third embodiment will be described. In the third embodiment, the numerical controller 10B stores an evaluation parameter used for evaluating the access frequency, and when acquiring the number of reference instructions to the shared variable from the information processing device 20B as an external device, The difference from the first and second embodiments is that the number of reference instructions for each control statement is weighted and corrected by an evaluation parameter, and the frequency of access to shared variables is evaluated based on the corrected number of reference instructions. do.
As a result, the numerical controller 10B of the third embodiment analyzes the frequency of access to the shared variables of the applications executed by each CPU, and arranges shared variables with high access frequency in the local memory of the CPU executing the applications. can do.
A third embodiment will be described below.
　図１０は、第３実施形態に係る数値制御装置１０Ｂの機能的構成例を示す機能ブロック図である。なお、図２の数値制御装置１０の要素と同様の機能を有する要素については、同じ符号を付し、詳細な説明は省略する。
　図１０に示すように、数値制御装置１０Ｂは、第２実施形態に係る数値制御装置１０Ａと同様に、情報処理装置２０Ｂと図示しない接続インタフェースを介して互いに直接接続されてもよい。また、数値制御装置１０Ｂは、情報処理装置２０ＢとＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）やインターネット等の図示しないネットワークを介して接続されていてもよい。 FIG. 10 is a functional block diagram showing a functional configuration example of a numerical controller 10B according to the third embodiment. Elements having functions similar to those of the numerical control device 10 in FIG.
As shown in FIG. 10, the numerical control device 10B may be directly connected to the information processing device 20B via a connection interface (not shown), similarly to the numerical control device 10A according to the second embodiment. Further, the numerical control device 10B may be connected to the information processing device 20B via a network (not shown) such as a LAN (Local Area Network) or the Internet.
＜情報処理装置２０Ｂ＞
　図１１は、情報処理装置２０Ｂの機能的構成例を示す機能ブロック図である。なお、図９の情報処理装置２０の要素と同様の機能を有する要素については、同じ符号を付し、詳細な説明は省略する。
　図１１に示すように、情報処理装置２０Ｂは、制御部２１０ｂ、及び記憶部２２０を有する。また、制御部２１０ｂは、解析部２１１ｂ、及びコンパイル部２１２を有する。 <Information processing device 20B>
FIG. 11 is a functional block diagram showing a functional configuration example of the information processing device 20B. Elements having functions similar to those of the information processing apparatus 20 shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.
As shown in FIG. 11, the information processing device 20B has a control section 210b and a storage section 220. As shown in FIG. Also, the control unit 210b has an analysis unit 211b and a compilation unit 212 .
　制御部２１０ｂは、第２実施形態の制御部２１０と同様に、ＣＰＵ、ＲＯＭ、ＲＡＭ、ＣＭＯＳメモリ等を有し、これらはバスを介して相互に通信可能に構成される、当業者にとって公知のものである。
　ＣＰＵは情報処理装置２０Ｂを全体的に制御するプロセッサである。ＣＰＵは、ＲＯＭに格納されたシステムプログラム及び後述する機能部を実行するためのアプリケーションプログラムを、バスを介して読み出し、メモリ（図示せず）にロードし、システムプログラム及び当該アプリケーションプログラムに従って情報処理装置２０Ｂ全体を制御する。これにより、図１１に示すように、制御部２１０ｂが、解析部２１１ｂ、及びコンパイル部２１２の機能を実現するように構成される。
　コンパイル部２１２は、第２実施形態におけるコンパイル部２１２と同等の機能を有する。 As with the control unit 210 of the second embodiment, the control unit 210b has a CPU, a ROM, a RAM, a CMOS memory, etc., which are configured to communicate with each other via a bus. It is.
The CPU is a processor that controls the information processing device 20B as a whole. The CPU reads the system program stored in the ROM and the application program for executing the function units described later via the bus, loads them into a memory (not shown), and executes the information processing apparatus according to the system program and the application program. 20B as a whole. Thereby, as shown in FIG. 11, the control unit 210b is configured to implement the functions of the analysis unit 211b and the compilation unit 212. FIG.
The compiling unit 212 has functions equivalent to those of the compiling unit 212 in the second embodiment.
　解析部２１１ｂは、例えば、情報処理装置２０Ｂの入力装置（図示しない）を介してユーザから軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、及び周辺機器制御ソースプログラム２２３のソースプログラムに対する解析指示を受け付けた場合、各ソースプログラムの制御文それぞれの種類（例えば、「平文」、「ＩＦ文」、「Ｆｏｒ文」等）と、制御文毎に共有変数ｘ、ｙ、ｚ等を参照する参照命令数と、を求める。解析部２１１ｂは、求めた各制御文の種類と制御文毎の参照命令数とを、例えば各プログラムの実行形式のプログラムに格納するようにしてもよい。そうすることで、当該実行プログラムを数値制御装置１０Ｂにおける、後述するそれぞれのローカルメモリに展開（ロード）した際に、数値制御装置１０Ｂ（アクセス頻度評価部）は、各プログラムの各制御文の種類と制御文毎の共有変数ｘ、ｙ、ｚ等の参照命令数とを取得することができる。
　なお、解析部２１１ｂは、コンパイル部２１２に含まれてもよい。 For example, the analysis unit 211b receives an analysis instruction for the source programs of the axis control source program 221, the display control source program 222, and the peripheral device control source program 223 from the user via the input device (not shown) of the information processing device 20B. type of control statements in each source program (for example, "plain text", "IF statement", "For statement", etc.) and the number of reference instructions that refer to shared variables x, y, z, etc. for each control statement And ask. The analysis unit 211b may store the obtained type of each control statement and the number of reference instructions for each control statement in, for example, an executable program of each program. By doing so, when the execution program is developed (loaded) into each local memory described later in the numerical control device 10B, the numerical control device 10B (access frequency evaluation unit) determines the type of each control statement of each program and the number of reference instructions such as shared variables x, y, and z for each control statement.
Note that the analysis unit 211 b may be included in the compilation unit 212 .
＜数値制御装置１０Ｂ＞
　数値制御装置１０Ｂは、図１０に示すように、システム制御モジュール１１０ｂ、軸制御モジュール１２０、表示制御モジュール１３０、周辺機器制御モジュール１４０、及び記憶部１５０を有する。 <Numerical control device 10B>
The numerical controller 10B has a system control module 110b, an axis control module 120, a display control module 130, a peripheral device control module 140, and a storage section 150, as shown in FIG.
　＜システム制御モジュール１１０ｂ＞
　システム制御モジュール１１０ｂは、ＣＰＵ１１１ｂと、ローカルメモリ１１２と、を有する。また、ＣＰＵ１１１ｂは、アクセス頻度評価部１１１１ｂ、及びメモリ配置最適化部１１１２を有する。また、アクセス頻度評価部１１１１ｂは、評価パラメータ記憶部１１１４を有する。
　メモリ配置最適化部１１１２は、第１実施形態におけるメモリ配置最適化部１１１２と同等の機能を有する。
　ＣＰＵ１１１ｂは、第１実施形態のＣＰＵ１１１と同様に、数値制御装置１０Ｂを全体的に制御するプロセッサである。ＣＰＵ１１１ｂは、メインメモリである記憶部１５０に格納されたシステムプログラム及び後述する機能部を実行するためのアプリケーションプログラムを、バス１６０を介して読み出し、ローカルメモリ１１２にロードし、システムプログラム及び当該アプリケーションプログラムに従って数値制御装置１０Ｂ全体を制御する。これにより、図１０に示すように、ＣＰＵ１１１ｂが、アクセス頻度評価部１１１１ｂ、及びメモリ配置最適化部１１１２の機能を実現するように構成される。また、アクセス頻度評価部１１１１ｂが、評価パラメータ記憶部１１１４の機能を実現するように構成される。 <System control module 110b>
The system control module 110 b has a CPU 111 b and a local memory 112 . The CPU 111b also has an access frequency evaluation unit 1111b and a memory allocation optimization unit 1112 . The access frequency evaluation unit 1111b also has an evaluation parameter storage unit 1114. FIG.
The memory layout optimization unit 1112 has functions equivalent to those of the memory layout optimization unit 1112 in the first embodiment.
The CPU 111b is a processor that controls the numerical controller 10B as a whole, like the CPU 111 of the first embodiment. The CPU 111b reads, via the bus 160, a system program stored in the storage unit 150, which is a main memory, and an application program for executing a function unit (to be described later), loads them into the local memory 112, and stores the system program and the application program in question. The entire numerical controller 10B is controlled according to the following. Thereby, as shown in FIG. 10, the CPU 111b is configured to implement the functions of the access frequency evaluation unit 1111b and the memory allocation optimization unit 1112. FIG. Also, the access frequency evaluation unit 1111b is configured to realize the function of the evaluation parameter storage unit 1114. FIG.
　評価パラメータ記憶部１１１４は、例えば、アプリのソースプログラムを構成する制御文毎にアクセス頻度の評価に用いる評価パラメータの値を格納する。
　図１２は、評価パラメータ記憶部１１１４に格納される評価パラメータの一例を示す図である。
　図１２に示すように、制御文が平文の場合、評価パラメータは、例えば、「１．０」等の値に設定される。また、制御文がＩＦ文の場合、評価パラメータは、条件によっては実行されない場合もあるため、平文の場合と比べて小さい値（例えば、「０．８」等）に設定される。また、制御文がＦｏｒ文の場合、評価パラメータは、１実行周期で複数回繰り返し実行されることから、平文の場合と比べて大きい値（例えば、「１０」等）に設定される。
　なお、評価パラメータの値は、数値制御装置１０Ｂに含まれるキーボードやタッチパネル等の入力装置（図示しない）を介してユーザにより予め設定されてもよい。 The evaluation parameter storage unit 1114 stores, for example, the value of the evaluation parameter used for evaluating the access frequency for each control statement forming the source program of the application.
FIG. 12 is a diagram showing an example of evaluation parameters stored in the evaluation parameter storage unit 1114. As shown in FIG.
As shown in FIG. 12, when the control statement is plain text, the evaluation parameter is set to a value such as "1.0", for example. Also, if the control statement is an IF statement, the evaluation parameter may not be executed depending on the conditions, so the evaluation parameter is set to a smaller value (for example, "0.8", etc.) than in the case of plain text. Also, when the control statement is a For statement, the evaluation parameter is set to a larger value (for example, "10") than in the case of plain text because the control statement is repeatedly executed a plurality of times in one execution cycle.
The value of the evaluation parameter may be set in advance by the user via an input device (not shown) such as a keyboard or touch panel included in the numerical controller 10B.
　アクセス頻度評価部１１１１ｂは、例えば、情報処理装置２０Ｂの解析部２１１による軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３のソースプログラムである軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、周辺機器制御ソースプログラム２２３の解析から求めた各制御文の種類と制御文毎の参照命令数とを情報処理装置２０Ｂから取得する。アクセス頻度評価部１１１１ｂは、ソースプログラム中の制御文毎の参照命令数を、評価パラメータ記憶部１１１４に格納された制御文の種類に応じた評価パラメータによる重み付けを行い補正し、補正した参照命令数に基づいて共有変数へのアクセス頻度を評価する。
　図１３は、アクセス頻度評価部１１１１ｂの動作を説明する一例を示す図である。
　図１３に示すように、情報処理装置２０Ｂの解析部２１１ｂは、記憶部２２０に記憶されたソースコードを解析し、制御文それぞれの種類と１実行周期あたり参照命令数「１」とを実行形式のプログラムに格納する。
　数値制御装置１０Ｂのアクセス頻度評価部１１１１ｂは、情報処理装置２０Ｂから受信した実行プログラムに格納された制御文毎の参照命令数「１」に対して当該制御文の種類に応じた評価パラメータの値を重み付けすることで参照命令数を補正する。例えば、アクセス頻度評価部１１１１ｂは、１つ目及び２つ目の平文の制御文の参照命令数「１」に対して評価パラメータ「１．０」で重み付けして補正し、１実行周期あたり補正した参照命令数「１」を算出する。また、アクセス頻度評価部１１１１ｂは、３つ目のＩＦ文の制御文の参照命令数「１」に対して評価パラメータ「０．８」で重み付けして補正し、１実行周期あたり補正した参照命令数「０．８」を算出する。また、アクセス頻度評価部１１１１ｂは、４つ目のＦｏｒ文の制御文の参照命令数「１」に対して評価パラメータ「１０」で重み付けして補正し、１実行周期あたり補正した参照命令数「１０」を算出する。
　そして、アクセス頻度評価部１１１１ｂは、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３それぞれにおいて、補正した参照命令数を共有変数ｘ、ｙ、ｚ毎に加算することで、１実行周期あたりの共有変数ｘ、ｙ、ｚへのアクセス頻度を評価する。
　そうすることで、数値制御装置１０Ｂは、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３を実行するにあたり、共有変数ｘ、ｙ、ｚ等へのアクセス頻度を精度良く評価することができ、共有変数をローカルメモリ１２２、１３２、１４２に最適配置することができる。 The access frequency evaluation unit 1111b, for example, the axis control source program 221, the display control source program 222, which are the source programs of the axis control application 151, the display control application 152, and the peripheral device control application 153 by the analysis unit 211 of the information processing device 20B, The type of each control statement and the number of reference instructions for each control statement obtained from the analysis of the peripheral device control source program 223 are acquired from the information processing device 20B. The access frequency evaluation unit 1111b weights and corrects the number of reference instructions for each control statement in the source program using an evaluation parameter corresponding to the type of control statement stored in the evaluation parameter storage unit 1114, and corrects the corrected number of reference instructions. Evaluate access frequency to shared variables based on .
FIG. 13 is a diagram showing an example explaining the operation of the access frequency evaluation unit 1111b.
As shown in FIG. 13, the analysis unit 211b of the information processing device 20B analyzes the source code stored in the storage unit 220, and determines the type of each control statement and the number of reference instructions "1" per execution cycle. stored in the program of
The access frequency evaluation unit 1111b of the numerical controller 10B determines the value of the evaluation parameter according to the type of the control statement for the number of reference instructions "1" for each control statement stored in the execution program received from the information processing device 20B. is weighted to correct the number of reference instructions. For example, the access frequency evaluation unit 1111b weights and corrects the number of reference instructions "1" of the first and second plaintext control statements with the evaluation parameter "1.0", and corrects the number per execution cycle. Then, the number of reference instructions "1" is calculated. Further, the access frequency evaluation unit 1111b weights and corrects the number of reference instructions of the control statement of the third IF statement "1" by weighting the evaluation parameter "0.8", and corrects the reference instruction count per one execution cycle. Calculate the number "0.8". Further, the access frequency evaluation unit 1111b weights and corrects the reference instruction count “1” of the control statement of the fourth For statement with the evaluation parameter “10”, and corrects the corrected reference instruction count “1” per execution cycle. 10" is calculated.
Then, the access frequency evaluation unit 1111b adds the corrected number of reference instructions to each of the shared variables x, y, and z in each of the axis control application 151, the display control application 152, and the peripheral device control application 153. Evaluate the frequency of access to shared variables x, y, z per
By doing so, when executing the axis control application 151, the display control application 152, and the peripheral device control application 153, the numerical controller 10B can accurately evaluate the access frequency to the shared variables x, y, z, and the like. , and shared variables can be optimally placed in local memory 122 , 132 , 142 .
　なお、数値制御装置１０Ｂの配置最適化処理は、アクセス頻度評価部１１１１ｂが情報処理装置２０Ｂから参照命令数を取得し評価パラメータで補正する点を除き図７に示す処理と同様であり、詳細な説明は省略する。 7 except that the access frequency evaluation unit 1111b acquires the number of reference instructions from the information processing device 20B and corrects it with an evaluation parameter. Description is omitted.
　以上により、第３実施形態に係る数値制御装置１０Ｂは、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３のソースプログラムである軸制御ソースプログラム２２１、表示制御ソースプログラム２２２、周辺機器制御ソースプログラム２２３の各制御文の種類と制御文毎の参照命令数とを情報処理装置２０Ｂから取得する。数値制御装置１０Ｂは、取得した制御文毎の参照命令数を制御文の種類に応じた評価パラメータによる重み付けを行い補正し、補正した参照命令数に基づいて共有変数へのアクセス頻度を評価することで、アクセス頻度が最も高い共有変数をアプリが実行されるＣＰＵのローカルメモリに配置することができる。
　そして、ＣＰＵ１２１、１３１、１４１は、バス１６０を経由したローカルメモリへのアクセスが減少し、処理時間を短縮することができる。
　以上、第３実施形態について説明した。 As described above, the numerical controller 10B according to the third embodiment includes the axis control source program 221, the display control source program 222, and the peripheral device control source program 221, which are the source programs of the axis control application 151, the display control application 152, and the peripheral device control application 153. The type of each control statement of the source program 223 and the number of reference instructions for each control statement are obtained from the information processing device 20B. The numerical controller 10B corrects the obtained number of reference instructions for each control statement by weighting it with an evaluation parameter according to the type of the control statement, and evaluates the access frequency to the shared variable based on the corrected number of reference instructions. , the shared variables with the highest access frequency can be placed in the local memory of the CPU where the application is executed.
The CPUs 121, 131, and 141 can reduce the access to the local memory via the bus 160 and shorten the processing time.
The third embodiment has been described above.
＜第３実施形態の変形例＞
　第３実施形態に係る数値制御装置１０Ｂは、アクセス頻度評価部１１１１ｂ及び評価パラメータ記憶部１１１４を有したが、これに限定されない。例えば、情報処理装置２０Ｂは、アクセス頻度評価部１１１１ａ及び評価パラメータ記憶部１１１４を有してもよい。
　例えば、解析部２１１ｂは、アクセス頻度評価部１１１１ｂの機能を有し、各ソースプログラムの解析から求めた各制御文の種類と制御文毎の参照命令数とを求める。解析部２１１ｂは、求めたソースプログラム中の制御文毎の参照命令数を、評価パラメータ記憶部１１１４に格納された制御文の種類に応じた評価パラメータによる重み付けを行い補正し、補正した参照命令数に基づいて共有変数へのアクセス頻度を評価し、評価したアクセス頻度を、例えば各プログラムの実行形式のプログラムに格納するようにしてもよい。そうすることで、当該実行プログラムを数値制御装置１０Ｂにおける、それぞれのローカルメモリに展開（ロード）した際に、数値制御装置１０Ｂ（メモリ配置最適化部）は、各プログラムの共有変数ｘ、ｙ、ｚ等を最適なローカルメモリに配置することができる。 <Modified example of the third embodiment>
The numerical controller 10B according to the third embodiment has the access frequency evaluation unit 1111b and the evaluation parameter storage unit 1114, but is not limited to this. For example, the information processing device 20B may have an access frequency evaluation unit 1111a and an evaluation parameter storage unit 1114. FIG.
For example, the analysis unit 211b has the function of the access frequency evaluation unit 1111b, and obtains the type of each control statement and the number of reference instructions for each control statement obtained from the analysis of each source program. The analysis unit 211b corrects the obtained number of reference instructions for each control statement in the source program by weighting it with an evaluation parameter corresponding to the type of control statement stored in the evaluation parameter storage unit 1114, and corrects the corrected number of reference instructions. may be used to evaluate the access frequency to the shared variable based on and store the evaluated access frequency in, for example, the executable program of each program. By doing so, when the execution program is expanded (loaded) into each local memory in the numerical control device 10B, the numerical control device 10B (memory allocation optimization unit) can set the shared variables x, y, z etc. can be placed in the optimal local memory.
　以上、第１実施形態、第２実施形態、第２実施形態の変形例、第３実施形態、及び第３実施形態の変形例について説明したが、数値制御装置１０、１０Ａ、１０Ｂは、上述の実施形態に限定されるものではなく、目的を達成できる範囲での変形、改良等を含む。 The first embodiment, the second embodiment, the modification of the second embodiment, the third embodiment, and the modification of the third embodiment have been described above. It is not limited to the embodiment, and includes modifications, improvements, etc. within a range that can achieve the purpose.
＜変形例１＞
　第１実施形態、第２実施形態、第２実施形態の変形例、第３実施形態、及び第３実施形態の変形例では、数値制御装置１０、１０Ａ、１０Ｂの軸制御モジュール１２０、表示制御モジュール１３０、周辺機器制御モジュール１４０それぞれは、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３の１つを実行したが、これに限定されない。例えば、数値制御装置１０、１０Ａ、１０Ｂの軸制御モジュール１２０のＣＰＵ１２１は、軸制御アプリ１５１とともに、工作機械（図示しない）の主軸等の位置座標を取得するアプリ等、複数のアプリを実行してもよい。この場合、軸制御モジュール１２０における共有変数へのアクセス頻度は、これら複数のアプリの共有変数へのアクセス頻度を合計したものとしてもよい。また、表示制御モジュール１３０のＣＰＵ１３１は、表示制御アプリ１５２とともに、工作機械（図示しない）を動作させる加工プログラムの実行行を取得するアプリ等、複数のアプリを実行してもよい。この場合、表示制御モジュール１３０における共有変数へのアクセス頻度は、これら複数のアプリの共有変数へのアクセス頻度を合計したものとしてもよい。また、周辺機器制御モジュール１４０のＣＰＵ１４１は、周辺機器制御アプリ１５３とともに、作業員が周辺機器の周りにいるか否かを監視するアプリ等、複数のアプリを実行してもよい。この場合、周辺機器制御モジュール１４０における共有変数へのアクセス頻度は、これら複数のアプリの共有変数へのアクセス頻度を合計したものとしてもよい。 <Modification 1>
In the first embodiment, the second embodiment, the modification of the second embodiment, the third embodiment, and the modification of the third embodiment, the axis control module 120 and the display control module of the numerical controllers 10, 10A, and 10B 130 and the peripheral device control module 140 each executed one of the axis control application 151, the display control application 152, and the peripheral device control application 153, but is not limited to this. For example, the CPU 121 of the axis control module 120 of the numerical controllers 10, 10A, and 10B executes a plurality of applications such as an application for acquiring the position coordinates of the spindle of a machine tool (not shown) together with the axis control application 151. good too. In this case, the access frequency to the shared variables in the axis control module 120 may be the sum of the access frequencies to the shared variables of these multiple applications. In addition, the CPU 131 of the display control module 130 may execute a plurality of applications such as an application for obtaining execution lines of a machining program for operating a machine tool (not shown) together with the display control application 152 . In this case, the access frequency to the shared variable in the display control module 130 may be the sum of the access frequencies to the shared variable of these multiple applications. In addition, the CPU 141 of the peripheral device control module 140 may execute a plurality of applications such as an application for monitoring whether or not a worker is around the peripheral device together with the peripheral device control application 153 . In this case, the frequency of access to shared variables in peripheral device control module 140 may be the sum of the access frequencies of these multiple applications to shared variables.
＜変形例２＞
　また例えば、第１実施形態、第２実施形態、第２実施形態の変形例、第３実施形態、及び第３実施形態の変形例では、数値制御装置１０、１０Ａ、１０Ｂのローカルメモリ１２２、１３２、１４２は、共有変数ｘ、ｙ、ｚ等のうちアクセス頻度が最も高い共有変数が配置されたが、これに限定されない。例えば、ローカルメモリ１２２、１３２、１４２には、共有変数ｘ、ｙ、ｚ等のうちアクセス頻度が予め設定された所定値以上の共有変数が配置されてもよい。 <Modification 2>
Further, for example, in the first embodiment, the second embodiment, the modified example of the second embodiment, the third embodiment, and the modified example of the third embodiment, the local memories 122, 132 of the numerical controllers 10, 10A, 10B , 142 are shared variables with the highest access frequency among the shared variables x, y, z, etc., but are not limited to this. For example, in the local memories 122, 132, 142, shared variables having a predetermined access frequency or higher among the shared variables x, y, z, etc. may be allocated.
＜変形例３＞
　また例えば、第２実施形態、第２実施形態の変形例、第３実施形態、及び第３実施形態の変形例では、情報処理装置２０、２０Ｂは、解析部２１１、２２１ｂが、軸制御アプリ１５１、表示制御アプリ１５２、周辺機器制御アプリ１５３のソースプログラムを解析したが、これに限定されない。例えば、コンパイル部２１２が、解析部２１１、２１１ｂの機能を有してもよい。 <Modification 3>
Further, for example, in the second embodiment, the modified example of the second embodiment, the third embodiment, and the modified example of the third embodiment, the information processing apparatuses 20 and 20B have the analysis units 211 and 221b set the axis control application 151 , the display control application 152, and the peripheral device control application 153 have been analyzed, but the present invention is not limited to this. For example, the compilation unit 212 may have the functions of the analysis units 211 and 211b.
　なお、第１実施形態、第２実施形態、第２実施形態の変形例、第３実施形態、及び第３実施形態の変形例に係る数値制御装置１０、１０Ａ、１０Ｂに含まれる各機能は、ハードウェア、ソフトウェア又はこれらの組み合わせによりそれぞれ実現することができる。ここで、ソフトウェアによって実現されるとは、コンピュータがプログラムを読み込んで実行することにより実現されることを意味する。 Note that each function included in the numerical controllers 10, 10A, and 10B according to the first embodiment, the second embodiment, the modification of the second embodiment, the third embodiment, and the modification of the third embodiment is Each can be implemented by hardware, software, or a combination thereof. Here, "implemented by software" means implemented by a computer reading and executing a program.
　プログラムは、様々なタイプの非一時的なコンピュータ可読媒体（Ｎｏｎ－ｔｒａｎｓｉｔｏｒｙ　ｃｏｍｐｕｔｅｒ　ｒｅａｄａｂｌｅ　ｍｅｄｉｕｍ）を用いて格納され、コンピュータに供給することができる。非一時的なコンピュータ可読媒体は、様々なタイプの実体のある記録媒体（Ｔａｎｇｉｂｌｅ　ｓｔｏｒａｇｅ　ｍｅｄｉｕｍ）を含む。非一時的なコンピュータ可読媒体の例は、磁気記録媒体（例えば、フレキシブルディスク、磁気テープ、ハードディスクドライブ）、光磁気記録媒体（例えば、光磁気ディスク）、ＣＤ－ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、ＣＤ－Ｒ、ＣＤ－Ｒ／Ｗ、半導体メモリ（例えば、マスクＲＯＭ、ＰＲＯＭ（Ｐｒｏｇｒａｍｍａｂｌｅ　ＲＯＭ）、ＥＰＲＯＭ（Ｅｒａｓａｂｌｅ　ＰＲＯＭ）、フラッシュＲＯＭ、ＲＡＭ）を含む。また、プログラムは、様々なタイプの一時的なコンピュータ可読媒体（Ｔｒａｎｓｉｔｏｒｙ　ｃｏｍｐｕｔｅｒ　ｒｅａｄａｂｌｅ　ｍｅｄｉｕｍ）によってコンピュータに供給されてもよい。一時的なコンピュータ可読媒体の例は、電気信号、光信号、及び電磁波を含む。一時的なコンピュータ可読媒体は、電線及び光ファイバ等の有線通信路、又は、無線通信路を介して、プログラムをコンピュータに供給できる。 Programs can be stored and supplied to computers using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., flexible discs, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical discs), CD-ROMs (Read Only Memory), CD- R, CD-R/W, semiconductor memory (eg, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM). The program may also be supplied to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired communication channels, such as wires and optical fibers, or wireless communication channels.
　なお、記録媒体に記録されるプログラムを記述するステップは、その順序に沿って時系列的に行われる処理はもちろん、必ずしも時系列的に処理されなくとも、並列的あるいは個別に実行される処理をも含むものである。 It should be noted that the steps of writing a program recorded on a recording medium include not only processes that are executed chronologically in order, but also processes that are executed in parallel or individually, even if they are not necessarily processed chronologically. It also includes
　以上を換言すると、本開示の制御装置は、次のような構成を有する各種各様の実施形態を取ることができる。 In other words, the control device of the present disclosure can take various embodiments having the following configurations.
　（１）本開示の制御装置１は、複数のＣＰＵ３０と複数のＣＰＵ３０それぞれがアクセスする複数のローカルメモリ３１とを有する制御装置であって、少なくとも共有変数の仮想アドレス及び共有変数の物理アドレスを含む共有変数情報４１を格納する記憶部４と、複数のＣＰＵ３０それぞれが実行する実行プログラム４０－１～４０－ｎ毎に共有変数情報４１に含まれる共有変数へのアクセス頻度を評価するアクセス頻度評価部２１－１と、アクセス頻度に基づいて共有変数を配置するローカルメモリ３１を変更するメモリ配置最適化部２１－２と、を備える。
　この制御装置１によれば、各ＣＰＵが実行するアプリの共有変数へのアクセス頻度を解析し、アクセス頻度が高い共有変数を当該アプリが実行されるＣＰＵのローカルメモリに配置することができる。 (1) The control device 1 of the present disclosure is a control device having a plurality of CPUs 30 and a plurality of local memories 31 accessed by each of the plurality of CPUs 30, and includes at least virtual addresses of shared variables and physical addresses of shared variables. A storage unit 4 that stores shared variable information 41, and an access frequency evaluation unit that evaluates the frequency of access to shared variables included in the shared variable information 41 for each of the execution programs 40-1 to 40-n executed by each of the plurality of CPUs 30. 21-1, and a memory placement optimization unit 21-2 that changes the local memory 31 in which shared variables are placed based on the access frequency.
According to this control device 1, it is possible to analyze the access frequency of an application executed by each CPU to a shared variable, and arrange shared variables with a high access frequency in the local memory of the CPU executing the application.
　（２）　（１）に記載の数値制御装置１０において、アクセス頻度評価部１１１１は、複数のＣＰＵ１２１、１３１、１４１それぞれによる実行プログラムの実行時に、共有変数を参照する命令の実行回数を複数のＣＰＵ１２１、１３１、１４１毎に記録する参照命令実行記録部１１１３を備え、アクセス頻度評価部１１１１は、参照命令実行記録部１１１３に記録された複数のＣＰＵ１２１、１３１、１４１毎の実行回数に基づいて共有変数へのアクセス頻度を評価し、メモリ配置最適化部１１１２は、評価されたアクセス頻度が最も高いプロセッサがアクセスするローカルメモリに共有変数を配置してもよい。
　そうすることで、数値制御装置１０は、アクセス頻度を精度良く評価することができ、共有変数の配置をより最適化することができる。 (2) In the numerical control device 10 described in (1), the access frequency evaluation unit 1111 counts the number of executions of instructions that refer to shared variables when each of the CPUs 121, 131, and 141 executes an execution program. , 131, and 141, and the access frequency evaluation unit 1111 calculates a shared variable may be evaluated, and the memory placement optimizer 1112 may place shared variables in the local memory accessed by the processor with the highest evaluated access frequency.
By doing so, the numerical controller 10 can accurately evaluate the access frequency and further optimize the allocation of shared variables.
　（３）　（１）に記載の数値制御装置１０Ａにおいて、アクセス頻度評価部１１１１ａは、複数のＣＰＵ１２１、１３１、１４１それぞれが実行する実行プログラム毎に共有変数への参照命令数を取得、又は情報処理装置２０による実行プログラムのソースプログラムの解析から求めた共有変数への参照命令数を情報処理装置２０から取得し、取得した参照命令数に基づいて共有変数へのアクセス頻度を評価し、メモリ配置最適化部１１１２は、評価されたアクセス頻度が最も高いＣＰＵがアクセスするローカルメモリに共有変数を配置してもよい。
　そうすることで、数値制御装置１０Ａは、（２）と同様の効果を奏することができる。 (3) In the numerical controller 10A described in (1), the access frequency evaluation unit 1111a acquires the number of reference instructions to the shared variable for each execution program executed by each of the plurality of CPUs 121, 131, and 141, or acquires the number of information processing The number of reference instructions to the shared variable obtained from the analysis of the source program of the execution program by the device 20 is acquired from the information processing device 20, the frequency of access to the shared variable is evaluated based on the acquired number of reference instructions, and the memory allocation is optimized. The modifier 1112 may place the shared variables in the local memory accessed by the CPU with the highest evaluated access frequency.
By doing so, the numerical controller 10A can achieve the same effect as (2).
　（４）　（３）に記載の数値制御装置１０Ｂにおいて、アクセス頻度評価部１１１１ｂは、アクセス頻度の評価に用いる評価パラメータを格納する評価パラメータ記憶部１１１４を備え、アクセス頻度評価部１１１１ｂは、参照命令数を情報処理装置２０Ｂから取得する場合、ソースプログラム中の制御文毎の参照命令数を評価パラメータ記憶部１１１４に格納された評価パラメータによる重み付けを行い補正し、補正した参照命令数に基づいて共有変数へのアクセス頻度を評価してもよい。
　そうすることで、数値制御装置１０Ｂは、アプリを実行しなくても、共有変数へのアクセス頻度を精度良く評価できる。 (4) In the numerical controller 10B described in (3), the access frequency evaluation unit 1111b includes an evaluation parameter storage unit 1114 that stores evaluation parameters used for evaluating the access frequency, and the access frequency evaluation unit 1111b stores the reference instruction When acquiring the number from the information processing device 20B, the number of reference instructions for each control statement in the source program is weighted and corrected by the evaluation parameter stored in the evaluation parameter storage unit 1114, and shared based on the corrected number of reference instructions. The frequency of access to variables may be evaluated.
By doing so, the numerical controller 10B can accurately evaluate the access frequency to the shared variable without executing the application.
　１　制御装置
　２　制御モジュール
　２１　ＣＰＵ
　２１－１　アクセス頻度評価部
　２１－２　メモリ配置最適化部
　２２　ローカルメモリ
　３－１～３－ｎ　プロセッサモジュール
　３０　ＣＰＵ
　３１　ローカルメモリ
　４　記憶部
　４０－１～４０－ｎ　実行プログラム
　４１　共有変数情報
　５　バス
　１０、１０Ａ、１０Ｂ　数値制御装置
　１１０、１１０ａ、１１０ｂ　システム制御モジュール
　１１１、１１１ａ、１１１ｂ　ＣＰＵ
　１１１１、１１１１ａ、１１１１ｂ　アクセス頻度評価部
　１１１２　メモリ配置最適化部
　１１１３　参照命令実行記録部
　１１１４　評価パラメータ記憶部
　１２０　軸制御モジュール
　１２１　ＣＰＵ
　１２２　ローカルメモリ
　１３０　表示制御モジュール
　１３１　ＣＰＵ
　１３２　ローカルメモリ
　１４０　周辺機器制御モジュール
　１４１　ＣＰＵ
　１４２　ローカルメモリ
　１５０　記憶部
　１５１　軸制御アプリ
　１５２　表示制御アプリ
　１５３　周辺機器制御アプリ
　１５４　共有変数情報
　１６０　バス
　２０、２０Ｂ　情報処理装置
　２１０、２１０ｂ　制御部
　２１１、２１１ｂ　解析部
　２１２　コンパイル部
　２２０　記憶部
　２２１　軸制御ソースプログラム
　２２２　表示制御ソースプログラム
　２２３　周辺機器制御ソースプログラム 1 control device 2 control module 21 CPU
21-1 access frequency evaluation unit 21-2 memory allocation optimization unit 22 local memory 3-1 to 3-n processor module 30 CPU
31 local memory 4 storage unit 40-1 to 40-n execution program 41 shared variable information 5 bus 10, 10A, 10B numerical controller 110, 110a, 110b system control module 111, 111a, 111b CPU
1111, 1111a, 1111b access frequency evaluation unit 1112 memory allocation optimization unit 1113 reference instruction execution recording unit 1114 evaluation parameter storage unit 120 axis control module 121 CPU
122 local memory 130 display control module 131 CPU
132 Local memory 140 Peripheral device control module 141 CPU
142 local memory 150 storage unit 151 axis control application 152 display control application 153 peripheral device control application 154 shared variable information 160 bus 20, 20B information processing device 210, 210b control unit 211, 211b analysis unit 212 compilation unit 220 storage unit 221 axis control Source program 222 Display control source program 223 Peripheral device control source program

Claims (4)

  1. 　複数のプロセッサと前記複数のプロセッサそれぞれがアクセスする複数のローカルメモリとを有する制御装置であって、
    　少なくとも共有変数の仮想アドレス及び共有変数の物理アドレスを含む共有変数情報を格納する記憶部と、
    　前記複数のプロセッサそれぞれが実行する実行プログラム毎に前記共有変数情報に含まれる前記共有変数へのアクセス頻度を評価するアクセス頻度評価部と、
    　前記アクセス頻度に基づいて前記共有変数を配置する前記ローカルメモリを変更するメモリ配置最適化部と、
    　を備える制御装置。     A controller having a plurality of processors and a plurality of local memories accessed by each of the plurality of processors,
    a storage unit for storing shared variable information including at least the virtual address of the shared variable and the physical address of the shared variable;
    an access frequency evaluation unit that evaluates the frequency of access to the shared variables included in the shared variable information for each execution program executed by each of the plurality of processors;
    a memory placement optimization unit that changes the local memory in which the shared variables are placed based on the access frequency;
    A control device comprising:
  2. 　前記アクセス頻度評価部は、前記複数のプロセッサそれぞれによる前記実行プログラムの実行時に、前記共有変数を参照する命令の実行回数を前記複数のプロセッサ毎に記録する参照命令実行記録部を備え、
    　前記アクセス頻度評価部は、前記参照命令実行記録部に記録された前記複数のプロセッサ毎の前記実行回数に基づいて前記共有変数へのアクセス頻度を評価し、
    　前記メモリ配置最適化部は、評価された前記アクセス頻度が最も高いプロセッサがアクセスするローカルメモリに前記共有変数を配置する、請求項１に記載の制御装置。     The access frequency evaluation unit includes a reference instruction execution recording unit that records, for each of the plurality of processors, the number of times an instruction that references the shared variable is executed when the execution program is executed by each of the plurality of processors,
    The access frequency evaluation unit evaluates the frequency of access to the shared variable based on the number of executions for each of the plurality of processors recorded in the reference instruction execution recording unit,
    2. The control device according to claim 1, wherein said memory allocation optimizing unit allocates said shared variables in a local memory accessed by said processor evaluated to have the highest access frequency.
  3. 　前記アクセス頻度評価部は、前記複数のプロセッサそれぞれが実行する実行プログラム毎に前記共有変数への参照命令数を取得、又は外部装置による前記実行プログラムのソースプログラムの解析から求めた前記共有変数への参照命令数を前記外部装置から取得し、取得した参照命令数に基づいて前記共有変数へのアクセス頻度を評価し、
    　前記メモリ配置最適化部は、評価された前記アクセス頻度が最も高いプロセッサがアクセスするローカルメモリに前記共有変数を配置する、請求項１に記載の制御装置。     The access frequency evaluation unit acquires the number of instructions referring to the shared variable for each execution program executed by each of the plurality of processors, or obtains the number of instructions to the shared variable obtained from analysis of the source program of the execution program by an external device. obtaining the number of reference instructions from the external device, evaluating the frequency of access to the shared variable based on the obtained number of reference instructions;
    2. The control device according to claim 1, wherein said memory allocation optimizing unit allocates said shared variables in a local memory accessed by said processor evaluated to have the highest access frequency.
  4. 　前記アクセス頻度評価部は、前記アクセス頻度の評価に用いる評価パラメータを格納する評価パラメータ記憶部を備え、
    　前記アクセス頻度評価部は、前記参照命令数を前記外部装置から取得する場合、前記ソースプログラム中の制御文毎の前記参照命令数を前記評価パラメータ記憶部に格納された前記評価パラメータによる重み付けを行い補正し、補正した前記参照命令数に基づいて前記共有変数へのアクセス頻度を評価する、請求項３に記載の制御装置。     The access frequency evaluation unit includes an evaluation parameter storage unit that stores evaluation parameters used to evaluate the access frequency,
    When the number of reference instructions is obtained from the external device, the access frequency evaluation unit weights the number of reference instructions for each control statement in the source program by the evaluation parameter stored in the evaluation parameter storage unit. 4. The control device according to claim 3, wherein the access frequency to the shared variable is evaluated based on the corrected number of reference instructions.
PCT/JP2021/032866 2021-09-07 2021-09-07 Control device WO2023037414A1 (en)

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JP2016224882A (en) * 2015-06-04 2016-12-28 富士通株式会社 Parallel calculation device, compilation device, parallel processing method, compilation method, parallel processing program, and compilation program
US20210055967A1 (en) * 2019-08-19 2021-02-25 Research & Business Foundation Sungkyunkwan University Method and apparatus for memory allocation in a multi-core processor system, and recording medium therefor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016224882A (en) * 2015-06-04 2016-12-28 富士通株式会社 Parallel calculation device, compilation device, parallel processing method, compilation method, parallel processing program, and compilation program
US20210055967A1 (en) * 2019-08-19 2021-02-25 Research & Business Foundation Sungkyunkwan University Method and apparatus for memory allocation in a multi-core processor system, and recording medium therefor

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