WO2023029402A1 - 半导体结构及制备方法 - Google Patents

半导体结构及制备方法 Download PDF

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WO2023029402A1
WO2023029402A1 PCT/CN2022/077805 CN2022077805W WO2023029402A1 WO 2023029402 A1 WO2023029402 A1 WO 2023029402A1 CN 2022077805 W CN2022077805 W CN 2022077805W WO 2023029402 A1 WO2023029402 A1 WO 2023029402A1
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substrate
vertical
semiconductor structure
gate electrode
vertical transistors
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PCT/CN2022/077805
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English (en)
French (fr)
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王晓光
曾定桂
李辉辉
曹堪宇
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长鑫存储技术有限公司
北京超弦存储器研究院
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Priority to US17/808,372 priority Critical patent/US20230066016A1/en
Publication of WO2023029402A1 publication Critical patent/WO2023029402A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

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  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method.
  • Magnetic random access memory Magnetic Random Access Memory
  • MRAM Magnetic Random Access Memory
  • the combination of MTJ (Magnetic Tunnel Junction, magnetic tunnel junction) and transistors is used to increase the capacity of MRAM, so that the capacity of MRAM is expanded from the MB range to the GB range.
  • the driving current of the transistor is small, making it difficult for the transistor to drive the MARM memory array.
  • An embodiment of the present disclosure provides a semiconductor structure, including:
  • the channel material of the vertical transistor includes a single crystal semiconductor.
  • the single crystal semiconductor includes single crystal silicon or single crystal germanium.
  • the vertical transistors of the plurality of memory cells are arranged in a staggered array structure on the substrate.
  • a single connection pad is connected to one end of three vertical transistors.
  • the cross section of the vertical transistor along the direction of the substrate surface is circular
  • the cross section of the connection pad along the direction of the substrate surface is triangular
  • the apexes of the triangles are respectively located at midpoints of the circular cross section.
  • the projection of the magnetic tunnel junction on the substrate is inside the projection of the connection pad on the substrate.
  • the vertical transistors in two adjacent rows of memory cells are located in three consecutive rows of the array structure.
  • the semiconductor structure further includes:
  • a plurality of word lines are arranged at intervals, and the extending direction of the word lines is the same as the direction of one side length of the triangle.
  • the word line includes a gate electrode portion and a wire portion
  • the gate electrode part is connected to the channel of the vertical transistor in a single memory cell, and the wire part is connected to a plurality of gate electrode parts.
  • the projections of the gate electrode portion and the connection pad on the substrate surface coincide.
  • the gate electrode portion and the wire portion are formed in the same etching step.
  • the width of the word line portion is smaller than the pitch between the vertical transistors.
  • Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • a substrate is provided, and a plurality of vertical transistors are formed on the substrate; wherein, the channel material of the vertical transistors includes a single crystal semiconductor;
  • connection pads above the plurality of vertical transistors away from the substrate, so that a projection of a connection pad on the substrate overlaps with a projection of an odd number of vertical transistors;
  • a magnetic tunnel junction is formed above each connection pad away from the vertical transistor.
  • a plurality of vertical transistors are formed on the substrate, specifically including:
  • a drain plate is formed on the surface of each vertical channel away from the common source plate.
  • the gate electrode part connecting the odd number of vertical channels and the wire part connecting the gate electrode part are formed on the common source plate, specifically including:
  • the semiconductor structure includes a plurality of memory cells arranged in a cross, each memory cell includes an odd number of vertical transistors, connection pads, and a magnetic tunnel junction, and one end of the odd number of vertical transistors is connected to the Pad connection, a magnetic tunnel junction is provided on the connection pad, and an odd number of vertical transistors is used to provide a write current when writing data or reading data to the magnetic tunnel junction. Due to the use of an odd number of vertical transistors, it is possible to provide more for the magnetic tunnel junction. large write current.
  • the channel material of each vertical transistor is a single crystal semiconductor, which can further increase the write current of the vertical transistor, thereby improving the driving capability of the storage unit, and can be applied to high-density magnetic random access memory.
  • FIG. 1 is a top view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a semiconductor structure provided by another embodiment of the present disclosure.
  • FIG. 3 is a positional relationship diagram of word lines, vertical transistors and connection pads provided by the embodiment shown in FIG. 2;
  • FIG. 4 and FIG. 5 are process diagrams for preparing a channel of a vertical transistor according to an embodiment of the present disclosure
  • 6 and 7 are process diagrams for preparing word lines according to an embodiment of the present disclosure.
  • FIG. 8, FIG. 9 and FIG. 10 provide process diagrams for preparing word lines according to an embodiment of the present disclosure
  • FIG. 11 is a process diagram for preparing connection pads, magnetic tunnel junctions and bit lines according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a semiconductor structure, including a substrate 400 and a plurality of memory cells disposed on the substrate 400 .
  • the substrate 400 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator, silicon on insulator) substrate or a GOI (Germanium On Insulator, on an insulator). Silicon), etc.
  • the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, or SiC. It can also be a laminated structure, such as Si/SiGe and the like. It can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator, silicon germanium on insulator), etc.
  • the substrate 400 may be a single crystal silicon substrate for supporting device structures thereon.
  • a plurality of memory cells are arranged in a staggered manner on the substrate 400 .
  • the staggered arrangement of a plurality of memory cells may refer to the staggered arrangement of the memory cells in two adjacent rows or two adjacent columns, as shown in Figure 1, and may also refer to the memory cells in two adjacent rows or two adjacent columns.
  • the units are arranged relative to each other, as shown in Figure 2.
  • the memory cell includes an odd number of vertical transistors 110 , connection pads 120 and a magnetic tunnel junction 130 . That is, each memory cell may include 3 vertical transistors 110 , 5 vertical transistors 110 , . . . or 2n ⁇ 1 vertical transistors 110 , where n is a positive integer.
  • connection pad 120 is connected to one end of the odd number of vertical transistors 110 , and one magnetic tunnel junction 130 is located on one connection pad 120 , so that the odd number of vertical transistors 110 are connected to one magnetic tunnel junction 130 through the connection pad 120 .
  • the vertical transistor includes a source, a drain, a gate and a channel, and multiple vertical transistors can share one source plate 111 to simplify the manufacturing process.
  • a source plate 111 is formed on the substrate 400.
  • the source plate 111 is the source of each vertical transistor.
  • the material of the source plate 111 can be indium tin metal oxide (ITO ), Molybdenum (Mo), Aluminum (Al), Titanium Aluminum Alloy (Ti/Al), etc.
  • a plurality of channels 112 are formed on the source plate 111 , and a plurality of word lines 200 arranged at intervals are formed around the channel 113 .
  • an isolation layer 501 is further provided between the source plate 111 and the word line 200.
  • the isolation layer 501 is used to isolate the source plate 111 from the word line 200.
  • the material of the isolation layer 501 may be silicon oxide.
  • the material of the channel 112 may include a single crystal semiconductor, such as single crystal silicon or single crystal germanium, so as to improve the conductivity of the vertical transistor, so that the vertical transistor 110 can provide a larger write current and improve the memory cell. driving ability.
  • a drain is formed on each channel 112 . Then a channel 112, the word line 200 where the channel 112 is located, the source plate 111 and the drain on the channel 112 form a vertical transistor, and the word line 200 where the channel is located is the gate of the vertical transistor.
  • the end of the channel 112 in contact with the source plate 111 is called the bottom of the channel 112 , and the end opposite to the bottom is called the top of the channel 112 , and the drain of the vertical transistor is formed on the top of the channel 112 .
  • a dielectric layer 113 is formed between the channel 112 and the word line 200, between the channel 112 and the source plate 111, and between the channel 112 and the drain.
  • the material of the dielectric layer 113 includes a high-k oxide, such as an oxide Hafnium (HfO 2 ), zirconium oxide (ZrO 2 ), hafnium oxynitride (HfON), etc.
  • connection pad 120 is formed above the odd number of vertical transistors 110, so that one end of the odd number of vertical transistors 110 is connected to a connection pad 120, and a magnetic tunnel junction 130 is formed on each connection pad 120, and an odd number of vertical Transistor 110 is connected to a magnetic tunnel junction 130 via connection pad 120 .
  • a single connection pad 120 is connected to one end of three vertical transistors 110 .
  • the cross section of the vertical transistor 110 along the direction of the surface of the substrate 400 is circular, the cross section of the connection pad 120 along the direction of the surface of the substrate 400 is triangular, and the vertices of the triangle are respectively located at the midpoint of the circular cross section. That is, the vertex a of the triangle is located at the midpoint of the circular section of the first vertical transistor 110, the vertex b of the triangle is located at the midpoint of the circular section of the second vertical transistor 110, and the vertex c of the triangle is located at the third vertical transistor 110 in order to realize the interconnection between the connection pad 120 and the three vertical transistors 110 .
  • the projection of the magnetic tunnel junction 130 on the substrate 400 is located inside the projection of the connection pad 120 on the substrate 400 , so as to realize the connection between one magnetic tunnel junction 130 and one connection pad 120 .
  • connection pad 120 on the substrate 400 By making the projection of the connection pad 120 on the substrate 400 a triangular shape, the midpoints of the circular cross-sections of the three vertical transistors 110 are located at the three vertices of the triangle.
  • the area of the tunnel junction 130 on the substrate 400 may also be larger.
  • the vertical transistors 110 in two adjacent rows of memory cells are located in three consecutive rows of the array structure. That is, three consecutive rows in the array of vertical transistors 110 are marked as (i-1)th row, i-th row and (i+1)th row. Mark two consecutive rows in the memory cell array as the (j-1)th row and the jth row.
  • the vertical transistor 110 in the memory cell of the (j-1)th row is located in the (i-1)th row and the i-th row in the vertical transistor 110 array, and the vertical transistor 110 in the j-th row of the memory cell is located in the vertical transistor 110 array row i and row (i+1).
  • the semiconductor structure further includes a plurality of word lines 200 arranged at intervals, and the extending direction of the word lines 200 is the same as the direction of one side of the triangle.
  • the extending direction of the word line 200 is along a straight line passing through point d and point e
  • the projection of connection pad 120 on substrate 400 is a triangle abc
  • the straight line passing through point d and point e is the same as passing through point a parallel to the line at point c.
  • the word line 200 includes a gate electrode part 201 and a wire part 202, the gate electrode part 201 is connected to the channel of the vertical transistor 110 in a single memory cell, the wire part 202 is connected to a plurality of gate electrode parts 201, and the gate electrode part 201 and the projections of the connection pads 120 on the surface of the substrate 400 coincide. That is, when the projection of the gate electrode portion is a triangle, the projection of the connection pad 120 is also a triangle, and the two triangles have the same size, and the gate electrode portion is located directly below the connection pad 120 .
  • the gate electrode part 201 and the wire part 202 are formed in the same etching step. With such an arrangement, the connection between the gate electrode part and the wire part 202 can be achieved through one-step etching without making connection holes.
  • the width d1 of the part of the word line 200 is smaller than the distance d2 between the vertical transistors 110 , so that the distance between the two word lines 200 is relatively large, and the patterning process of the word line 200 can be simplified.
  • a magnetic tunnel junction 130 is formed above the connection pad 120, and the magnetic tunnel junction 130 includes a fixed layer, an insulating layer and a free layer stacked in sequence.
  • the magnetization direction of the fixed layer is fixed, while the magnetization direction of the free layer is easily changed under the action of a magnetic field or a spin-polarized current, and the insulating layer is used to isolate the fixed layer and the free layer.
  • the materials of the fixed layer and the free layer can be the same or different, for example, iron (Fe), cobalt (Co), nickel (Ni) or their alloys.
  • the thickness of the fixed layer and the free layer can be the same or different, the size can be the same or different, and the shape can be the same or different, for example, they can be cylindrical or square.
  • a plurality of bit lines 300 can also be formed on the magnetic tunnel junction 130 to improve the problem of high resistance of buried bit lines.
  • the direction in which the word lines 200 extend is called the first direction
  • the direction in which the bit lines 300 extend is called the second direction
  • a plurality of bit lines 300 extending in the second direction are formed on the magnetic tunnel junction 130, and each bit line 300 may connect a plurality of magnetic tunnel junctions 130, and the first direction and the second direction may be perpendicular.
  • a voltage to the word line 200 and the bit line 300 , a current is generated to generate a magnetic field, and the magnetization direction of the free layer is changed, so as to realize reading and writing of the MRAM.
  • a memory cell in which an odd number of vertical transistors 110 drives a magnetic tunnel junction 130 has greater driving capability.
  • the channel material of the vertical transistor 110 includes a single crystal semiconductor, and the conductivity of the vertical transistor 110 is higher, so as to improve the driving capability of the vertical transistor 110 and further improve the driving capability of the memory cell.
  • Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • the substrate 400 is a semiconductor substrate, and the source plate 111 is formed on the substrate 400 , as shown in FIG. 4 .
  • a conductive material is deposited on the substrate 400 by atomic layer deposition or chemical vapor deposition, such as indium tin oxide (ITO), molybdenum (Mo), aluminum (Al), titanium aluminum alloy (Ti /Al) etc.
  • ITO indium tin oxide
  • Mo molybdenum
  • Al aluminum
  • Ti /Al titanium aluminum alloy
  • a single crystal semiconductor material such as single crystal silicon or single crystal germanium
  • a planarization process is performed on the deposited semiconductor material to form a channel layer on the isolation layer.
  • a plurality of vertical channels 112 are formed.
  • a high-k dielectric layer 113 such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), hafnium oxynitride (HfON), etc. is formed outside the trench 112 .
  • a dielectric material such as silicon oxide, silicon nitride, etc. is deposited on the source plate 111 , and a planarization process is performed on the deposited dielectric material to form an isolation layer 501 on the source plate 111 .
  • word lines 200 arranged at intervals are formed on the isolation layer 501 .
  • metal material is deposited on the isolation layer 501, such as tungsten (W), molybdenum (Mo), etc., and a planarization process is performed on the metal material to form the word line plate 200' on the isolation layer 501.
  • a plurality of triangular mask patterns are formed on the grid plate, and the projections of the three vertical channels on the mask patterns are located inside the triangular mask patterns.
  • a plurality of striped mask patterns are formed on the grid plate, and the striped mask patterns and the triangular mask patterns are overlapped with each other.
  • Use the mask pattern as a shield to etch the gate plate to form a word line and obtain the structures shown in Figures 7 to 9, Figure 7 is a top view of the word line, Figure 8 is a cross-sectional view of the position of the i-th row of vertical transistors, Figure 9 is a cross-sectional view of the position of the vertical transistor in row i+1.
  • SADP Self-aligned Double Patterning
  • SAQP Self-aligned Quadruple Patterning
  • a dielectric material is deposited on the surface of the word line 200 to form a covering layer 502 to protect the word line 200 .
  • drains are formed on the channels 112, and each channel 112 has a corresponding drain.
  • the method of forming the drains may be to remove the top part of the single crystal semiconductor material of the channel 112 to form a groove in the channel 112. , fill the groove with conductive material to form the drain.
  • the method of forming the drain can also be to deposit a conductive material on the channel 112 and the cover layer 502 , and then remove the conductive material on the cover layer 502 to form the drain on the channel 112 .
  • connection pads 120 above the plurality of vertical transistors 110 away from the substrate 400 , so that a projection of one connection pad 120 on the substrate 400 overlaps with a projection of an odd number of vertical transistors 110 .
  • a metal layer is formed above the plurality of vertical transistors 110 away from the substrate 400, a mask pattern is formed on the metal layer, and the projection of an odd number of vertical transistors 110 on the mask pattern is located inside the mask pattern, and then The mask pattern is used to shield the metal layer to etch the connection pad 120 to obtain the connection pad 120, as shown in FIG.
  • a dielectric material such as an oxide, is deposited over the connection pad 120 and the cover layer 502 to form a dielectric layer 503 covering the connection pad 120, and then a fixed layer 131, an insulating layer 132 and a free layer 133 are sequentially formed on the dielectric layer 503, and the fixed layer 131 In contact with the upper side of the connection pad 120 , the end of the fixed layer 131 in contact with the connection pad 120 is referred to as the upper side of the connection pad 120 .
  • the two directions parallel to the substrate 400 are respectively referred to as the X direction and the Y direction
  • the fixed laminate, the insulating laminate and the free laminate are sequentially formed on the dielectric layer 503, and the fixed laminates are aligned in the X direction and the Y direction.
  • the laminate, the insulating laminate and the free laminate are all patterned to obtain a fixed layer 131 , an insulating layer 132 and a free layer 133 stacked in sequence.
  • a third photoresist layer is formed on the free layer, the third photoresist layer includes a plurality of strip structures arranged at intervals in the X direction, and a third mask layer is formed on the sidewall of the third photoresist layer , remove the third photoresist layer, and use the third mask layer as a shield to etch the free layer board, the insulating layer board and the fixed layer board until the connection pad 120, so that the free layer board, the insulating layer board and the fixed layer board are in the
  • the X direction includes a plurality of strip structures, and the strip structures extend in the Y direction.
  • the fourth photoresist layer includes a plurality of striped structures in the Y direction, and the striped structures in the X direction
  • the size is the same as the size of the third mask layer in the X direction
  • a fourth mask layer is formed on the sidewall on the fourth photoresist layer
  • the third photoresist layer is removed and the fourth mask layer is used as a shield
  • the engraving Etch the free laminate, the insulating laminate and the fixed laminate to the connection pad 120 thereby forming a magnetic tunnel junction on each connection pad 120, that is, a fixed layer 131, an insulating layer 132 and a free layer 133 stacked in sequence, as shown in FIG. 11 shown.
  • multiple bit lines 300 can be formed on the magnetic tunnel junction 113 to improve the problem of high resistance of buried bit lines.
  • the direction in which the word lines 200 extend is called the first direction
  • the direction in which the bit lines 300 extend is called the second direction
  • a plurality of bit lines 300 extending in the second direction are formed on the magnetic tunnel junction 113, and each bit line 300 may connect a plurality of magnetic tunnel junctions 113, and the first direction and the second direction may be perpendicular.
  • a voltage to the word line 200 and the bit line 300 , a current is generated to generate a magnetic field, and the magnetization direction of the free layer 133 is changed, so as to realize reading and writing of the MRAM.
  • a plurality of vertical transistors 110 are formed on the substrate 400, and a plurality of connection pads 120 are formed above the plurality of vertical transistors 110 away from the substrate 400, so that one connection pad 120 is in phase with an odd number of vertical transistors 110.
  • a magnetic tunnel junction 130 is formed above each connection pad 120 away from the vertical transistor 110, so that an odd number of vertical transistors 110 is connected to a magnetic tunnel junction 130 through the connection pad 120, and an odd number of vertical transistors 110 is a magnetic tunnel
  • the junction 130 provides write current to improve the driving capability of the memory cell, and the channel material of the vertical transistor 110 is a single crystal semiconductor, which can further improve the driving capability of the memory cell.

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Abstract

本公开提供一种半导体结构及制备方法，设置于衬底上的多个呈交错排布的存储单元，存储单元包括奇数个垂直晶体管、连接奇数个垂直晶体管一端的连接垫，以及位于连接垫上的一个磁性隧道结；其中，垂直晶体管的沟道材料包括单晶半导体。由奇数个垂直晶体管为磁性隧道结提供更大的写入电流，且每个垂直晶体管的沟道材料为单晶半导体，可以进一步提升垂直晶体管的写入电流，从而提升存储单元的驱动能力，可以适用于高密度磁性随机存储器。

Description

半导体结构及制备方法
本公开要求于2021年09月01日提交中国专利局、申请号为202111020494.6、申请名称为“半导体结构及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及制备方法。
背景技术
磁性随机存储器(Magnetoresistive Random Access Memory，简称：MRAM)拥有静态随机存储器的高度读写能力，以及动态随机存储器的高集成度，而且可以无限次地重复写入。
目前，利用MTJ(Magnetic Tunnel Junction，磁性隧道结)与晶体管结合增大MRAM的容量，使得MRAM的容量从MB范围扩大至GB范围。但是，晶体管的驱动电流较小，导致晶体管难以驱动MARM存储阵列。
发明内容
本公开一实施例提供一种半导体结构，包括：
设置于衬底上的多个呈交错排布的存储单元，存储单元包括奇数个垂直晶体管、连接奇数个垂直晶体管一端的连接垫，以及位于连接垫上的一个磁性隧道结；
其中，垂直晶体管的沟道材料包括单晶半导体。
在一实施例中，单晶半导体包括单晶硅或单晶锗。
在一实施例中，多个存储单元的垂直晶体管在衬底上呈交错排布的阵列结构。
在一实施例中，单个连接垫与三个垂直晶体管的一端相连。
在一实施例中，垂直晶体管沿衬底表面方向上的截面呈圆形，连接垫沿衬底表面方向上的截面呈三角形，三角形的顶点分别位于圆形截面的中点。
在一实施例中，磁性隧道结在衬底上的投影位于连接垫位于衬底上的投影内部。
在一实施例中，相邻两行存储单元中的垂直晶体管位于阵列结构的连 续三行中。
在一实施例中，半导体结构还包括：
多个间隔排布的字线，字线的延伸方向与三角形的其中一个边长方向相同。
在一实施例中，字线包括栅电极部分和导线部分；
栅电极部分连接单个存储单元中的垂直晶体管的沟道，导线部分连接多个栅电极部分。
在一实施例中，栅电极部分和连接垫在衬底表面上的投影重合。
在一实施例中，栅电极部分和导线部分在同一刻蚀步骤中形成。
在一实施例中，字线部分的宽度小于垂直晶体管之间的间距。
本公开另一实施例提供一种半导体结构的制造方法，包括：
提供衬底，在衬底上形成多个垂直晶体管；其中，垂直晶体管的沟道材料包括单晶半导体；
在多个垂直晶体管远离衬底的上方形成多个连接垫，以使一个连接垫在衬底上的投影与奇数个垂直晶体管的投影重叠；
在每个连接垫远离垂直晶体管的上方形成一个磁性隧道结。
在一实施例中，在衬底上形成多个垂直晶体管，具体包括：
在衬底上形成共源极板；
在共源极板上形成多个呈着阵列排布的垂直沟道；
在共源极板上形成连接奇数个的垂直沟道的栅电极部分和连接栅电极部分的导线部分；
在每个垂直沟道远离共源极板的表面形成漏极板。
在一实施例中，在共源极板上形成连接奇数个的垂直沟道的栅电极部分和连接栅电极部分的导线部分，具体包括：
在共源极板远离衬底的表面沉积金属材料，以形成栅极板；
在栅极板形成多个呈三角形的掩膜图形，并使三个垂直沟道在掩膜图形上的投影位于三角形的掩膜图形的内部；
在栅极板形成多个呈条状的掩膜图形，并使条状的掩膜图形与三角形的掩膜图形相互重叠；
对栅极板进行刻蚀，形成栅电极部分和连接栅电极部分的导线部分。
本申请实施例提供的半导体结构及制备方法，半导体结构包括多个交叉排布的存储单元，每个存储单元包括奇数个垂直晶体管、连接垫以及一个磁性隧道结，奇数个垂直晶体管的一端与连接垫连接，连接垫上设有一个磁性隧道结，奇数个垂直晶体管用于在向磁性隧道结写入数据或者读出数据时提供写入电流，由于使用奇数个垂直晶体管，可以为磁性隧道结提供更大的写入电流。其中，每个垂直晶体管的沟道材料为单晶半导体，可以进一步提升垂直晶体管的写入电流，从而提升存储单元的驱动能力，可以适用于高密度磁性随机存储器。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为本公开一实施例提供的半导体结构的俯视图；
图2为本公开另一实施例提供的半导体结构的俯视图；
图3为图2所示实施例提供的字线、垂直晶体管以及连接垫的位置关系图；
图4和图5为本公开一实施例提供制备垂直晶体管的沟道的工艺图；
图6和图7为本公开一实施例提供制备字线的工艺图；
图8、图9和图10为本公开一实施例提供制备字线的工艺图；
图11为本公开一实施例提供制备连接垫、磁性隧道结以及位线的工艺图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
如图1至图3所示，本公开一实施例提供一种半导体结构，包括衬底400和设置于衬底400上的多个存储单元。
本公开实施例中，衬底400为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(Silicon On Insulator，绝缘体上硅)衬底或GOI(Germanium On Insulato，绝缘体上硅)等。在其他实施例中，半导体衬底还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等。还可以为叠层结构，例如Si/SiGe等。还可以为其他外延结构，例如SGOI(Silicon Germanium On Insulator，绝缘体上硅锗)等。本实施例中，衬底400可以为单晶硅衬底，用于支撑在其上的器件结构。
其中，多个存储单元交错排布于衬底400上。其中，多个存储单元呈交错排布可以是指相邻两行或者相邻两列的存储单元错开排布，如图1所示，还可以是指相邻两行或者相邻两列的存储单元相对排布，如图2所示。
存储单元包括奇数个垂直晶体管110、连接垫120以及一个磁性隧道结130。也就是每个存储单元可以包含3个垂直晶体管110、5个垂直晶体管110、……或者2n-1个垂直晶体管110，其中，n为正整数。
其中，连接垫120与奇数个垂直晶体管110一端的连接，一个磁性隧道结130位于一个连接垫120上，以使奇数个垂直晶体管110通过连接垫120与一个磁性隧道结130相连。
垂直晶体管包括源极、漏极、栅极和沟道，多个垂直晶体管可以共用一个源极板111，以简化制造工艺。具体的，参考图4所示，在衬底400上形成有源极板111，源极板111即为每一个垂直晶体管的源极，源极板111的材料可以为铟锡金属氧化物(ITO)、钼(Mo)、铝(Al)、钛铝合金(Ti/Al)等。
在源极板111上形成有多个沟道112，在沟道的周围113形成有多个间隔排布的字线200。其中，在源极板111和字线200之间还设有隔离层501，隔离层501用于将源极板111和字线200隔离开，隔离层501的材料可以为氧化硅。沟道112的材料可以包括单晶半导体，单晶半导体例如可以为单晶硅或单晶锗，以提高垂直晶体管的导电性，以使垂直晶体管110可以提供更大的写入电流，提升存储单元的驱动能力。在每一个沟道112上形成有漏极。则一个沟道112、该沟道112所在的字线200、源极板111以及该沟道 112上的漏极形成一个垂直晶体管，沟道所在的字线200即为垂直晶体管的栅极。
将沟道112与源极板111接触的一端称为沟道112的底端，将与底端相对的一端称为沟道112的顶端，则垂直晶体管的漏极形成于沟道112的顶端。在沟道112和字线200之间、沟道112和源极板111之间，沟道112和漏极之间均形成有介质层113，介质层113的材料包括高k氧化物，例如氧化铪(HfO 2)、氧化锆(ZrO 2)、氮氧化铪(HfON)等。
在奇数个垂直晶体管110的上方形成有一个连接垫120，以使奇数个垂直晶体管110的一端与一个连接垫120连接，在每个连接垫120上形成有一个磁性隧道结130，以奇数个垂直晶体管110通过连接垫120与一个磁性隧道结130连接。
在一实施例中，参考图3，单个连接垫120与三个垂直晶体管110的一端相连。垂直晶体管110沿衬底400表面方向上的截面呈圆形，连接垫120沿衬底400表面方向上的截面呈三角形，且三角形的顶点分别位于圆形截面的中点。也就是三角形的顶点a位于第一个垂直晶体管110的圆形截面的中点，三角形的顶点b位于第二个垂直晶体管110的圆形截面的中点，三角形的顶点c位于第三个垂直晶体管110的圆形截面的中点，以实现连接垫120与三个垂直晶体管110的相互连接。磁性隧道结130在衬底400上的投影位于连接垫120位于衬底400上的投影内部，以实现一个磁性隧道结130和一个连接垫120的连接。
通过让连接垫120在衬底400上的投影呈三角形，让三个垂直晶体管110的圆形截面的中点位于三角形的三个顶点，三角形连接垫120面积更大，位于连接垫120上的磁性隧道结130在衬底400上的面积也可以更大。
在一实施例中，相邻两行存储单元中的垂直晶体管110位于阵列结构的连续三行中。也就是，将垂直晶体管110阵列中连续三行依次标记为第(i-1)行、第i行以及第(i+1)行。将存储单元阵列中连续两行依次标记为第(j-1)行以及第j行。第(j-1)行的存储单元内的垂直晶体管110位于垂直晶体管110阵列中第(i-1)行和第i行，第j行的存储单元内的垂直晶体管110位于垂直晶体管110阵列中第i行和第(i+1)行。通过如此设置，使得半导体的图形版面更均匀，有利于半导体的制作。
在一实施例中，半导体结构还包括多个字线200，多个字线200呈间隔排布，字线200的延伸方向与三角形的其中一个边长方向相同。如图3所示，字线200的延伸方向为沿着经过点d和点e的直线，连接垫120在衬底400上的投影为三角形abc，经过点d和点e的直线与经过点a和点c的直线平行。通过如此设置，使得相邻的两个字线200之间的距离比较大，可以简化字线200图形化工艺。
在一实施例中，字线200包括栅电极部分201和导线部分202，栅电极部分201连接单个存储单元中的垂直晶体管110的沟道，导线部分202连接多个栅电极部分201，栅电极部分201和连接垫120在衬底400表面上的投影重合。也就是当栅电极部分的投影为三角形时，连接垫120的投影也为三角形，且两个三角形尺寸大小相同，且栅电极部分位于连接垫120的正下方。
在一实施例中，栅电极部分201和导线部分202在同一刻蚀步骤中形成，通过如此设置，通过一步刻蚀可以实现栅电极部分同导线部分202的连接，无需再制作连接孔。
在一实施例中，字线200部分的宽度d1小于垂直晶体管110之间的间距d2，通过如此设置，使得两个字线200之间的间隔比较大，可以简化字线200图形化工艺。
在连接垫120上方形成磁性隧道结130，磁性隧道结130包括依次层叠的固定层、绝缘层和自由层。固定层的磁化方向是固定的，而自由层的磁化方向是在磁场或自旋极化电流作用下容易改变，绝缘层用于隔离固定层和自由层。固定层和自由层的材料可以采用相同或不同的材料，例如可以为铁(Fe)、钴(Co)、镍(Ni)或他们的合金。固定层和自由层的厚度可以相同也可以不同，尺寸可以相同也可以不同、形状可以相同也可以不同，例如可以为圆柱状或方柱状。
当电流从固定层流入自由层时，使得自由层的磁化方向和固定层的磁化方向平行，磁性隧道结的电阻较小，存储单元完成写入数据“0”。当电流由自由层流向固定层时，使得自由层的磁化方向和固定层的磁化方向反向平行，磁性隧道结的电阻较大，存储单元完成写入数据“1”。
还可以在磁性隧道结130上形成多个位线300，以改善埋入式位线电阻 较高的问题。将字线200延伸的方向称为第一方向，将位线300延伸的方向称为第二方向，则在磁性隧道结130上形成多个沿第二方向延伸的位线300，每一个位线300可以连接多个磁性隧道结130，第一方向和第二方向可以垂直。而后，通过对字线200和位线300施加电压，产生电流进而产生磁场，改变自由层的磁化方向，以实现磁性随机存储器的读写。
本公开提供的一种半导体结构，相较于单个垂直晶体管110驱动一个磁性隧道结130，由奇数个垂直晶体管110驱动一个磁性隧道结130的存储单元，其驱动能力更大。其中，垂直晶体管110的沟道材料包括单晶半导体，垂直晶体管110的导电性能更高，以提高垂直晶体管110的驱动能力，可以进一步提高存储单元的驱动能力。
本公开另一实施例提供一种半导体结构的制造方法，包括：
S51、提供衬底400，在衬底400上形成多个垂直晶体管110。
其中，衬底400为半导体衬底，在衬底400上形成源极板111，如图4所示。具体的，利用原子层沉积方法或化学气相沉积方法等在衬底400上沉积导电材料，例如可以为铟锡金属氧化物(ITO)、钼(Mo)、铝(Al)、钛铝合金(Ti/Al)等。对沉积的导电材料进行平坦化工艺，以在衬底400上形成源极板111。参考图4和图5，在源极板111沉积单晶半导体材料，例如单晶硅、单晶锗，并对沉积的半导体材料进行平坦化工艺，以在隔离层上形成沟道层。在对沟道层进行刻蚀，形成多个垂直的沟道112。参考图6，在沟道112外面形成高k介质层113，例如氧化铪(HfO 2)、氧化锆(ZrO 2)、氮氧化铪(HfON)等。
而后，继续参考图6，在源极板111上沉积介质材料，例如氧化硅、氮化硅等，并对沉积的介质材料进行平坦化工艺，以在源极板111上形成隔离层501。而后，在隔离层501上形成间隔排布的字线200。首先，在隔离层501上沉积金属材料，金属材料例如可以为钨(W)、钼(Mo)等，并对金属材料进行平坦化工艺，以在隔离层501上形成字线板200’。
在栅极板形成多个呈三角形的掩膜图形，并使三个垂直沟道在掩膜图形上的投影位于三角形的掩膜图形的内部。在栅极板形成多个呈条状的掩膜图形，并使条状的掩膜图形与三角形的掩膜图形相互重叠。以掩膜图形为遮蔽对栅极板进行刻蚀形成字线，得到图7至图9的结构，图7为字线的俯视图， 图8为在第i行垂直晶体管的位置的剖视图，图9为在第i+1行垂直晶体管的位置的剖视图。
在在栅极板上进行图形化时，可以使用常规图形化工艺，也可以使用精度更高的自对准双重成像技术(Self-aligned Double Patterning，简称：SADP)或者自对准双重成像技术(Self-aligned Quadruple Patterning，简称：SAQP)。
随后，在字线200表面沉积介质材料，以形成覆盖层502，以达到保护字线200的目的。而后，在沟道112上形成漏极，每一个沟道112具有对应的漏极，形成漏极的方法可以为，去除沟道112顶部部分单晶半导体材料，以在沟道112中形成凹槽，在凹槽内填充导电材料形成漏极。形成漏极的方法还可以为在沟道112以及覆盖层502上沉积导电材料，而后去除覆盖层502上的导电材料，以在沟道112上形成漏极。
S52、在多个垂直晶体管110远离衬底400的上方形成多个连接垫120，以使一个连接垫120在衬底400上的投影与奇数个垂直晶体管110的投影重叠。
其中，在多个垂直晶体管110远离衬底400的上方形成金属层，在金属层上形成掩膜图形，并使奇数个垂直晶体管110在掩膜图形上的投影位于掩膜图形的内部，再以掩膜图形为遮挡对金属层进行刻蚀即可获得连接垫120，如图10所示，从而实现奇数个垂直晶体管110的漏极和连接垫120之间连接。
S53、在每个连接垫120远离垂直晶体管110的上方形成一个磁性隧道结130。
在连接垫120以及覆盖层502上方沉积介质材料，例如氧化物，形成覆盖连接垫120的介质层503，而后在介质层503上依次形成固定层131、绝缘层132和自由层133，固定层131与连接垫120上方接触，此处将成固定层131与连接垫120接触的一端称为连接垫120的上方。
具体的，将平行于衬底400的两个方向分别称为X方向和Y方向，在介质层503上依次形成固定层板、绝缘层板和自由层板，在X方向和Y方向上对固定层板、绝缘层板和自由层板均进行图案化处理，以得到依次层叠的固定层131、绝缘层132和自由层133。
例如，在自由层板上形成第三光阻层，第三光阻层在X方向上包括多个间隔排布的条状结构，在第三光阻层的侧壁上形成第三掩模层，去除第三光 阻层，并以第三掩模层为遮蔽，刻蚀自由层板、绝缘层板以及固定层板直至连接垫120，从而使得自由层板、绝缘层板以及固定层板在X方向上包括多个条状结构，条状结构在Y方向上延伸。去除第三掩膜层，随后，分别在多个条状结构上形成第四光阻层，第四光阻层在Y方向上包括多个条状结构，且该条状结构在X方向上的尺寸与第三掩膜层在X方向上的尺寸相同，在第四光阻层上的侧壁上形成第四掩模层，去除第三光阻层并以第四掩模层为遮蔽，刻蚀自由层板、绝缘层板以及固定层板至连接垫120，从而在每一个连接垫120上形成一个磁性隧道结，即依次层叠的固定层131、绝缘层132和自由层133，如图11所示。
继续参考图11，可以在磁性隧道结113上形成多个位线300，以改善埋入式位线电阻较高的问题。将字线200延伸的方向称为第一方向，将位线300延伸的方向称为第二方向，则在磁性隧道结113上形成多个沿第二方向延伸的位线300，每一个位线300可以连接多个磁性隧道结113，第一方向和第二方向可以垂直。而后，通过对字线200和位线300施加电压，产生电流进而产生磁场，改变自由层133的磁化方向，以实现磁性随机存储器的读写。
在上述技术方案中，在衬底400上形成多个垂直晶体管110，在多个垂直晶体管110远离衬底400的上方形成多个连接垫120，以使一个连接垫120与奇数个垂直晶体管110相连接，在每个连接垫120远离垂直晶体管110的上方形成一个磁性隧道结130，以实现奇数个垂直晶体管110通过连接垫120与一个磁性隧道结130连接，由奇数个垂直晶体管110为一个磁性隧道结130提供写入电流，以提高存储单元的驱动能力，且垂直晶体管110的沟道材料为单晶半导体，可以进一步提高存储单元的驱动能力。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅 由所附的权利要求书来限制。

Claims (15)

  1. 一种半导体结构，包括：
    设置于衬底上的多个呈交错排布的存储单元，所述存储单元包括奇数个垂直晶体管、连接所述奇数个垂直晶体管一端的连接垫，以及位于所述连接垫上的一个磁性隧道结；
    其中，所述垂直晶体管的沟道材料包括单晶半导体。
  2. 根据权利要求1所述的半导体结构，其中，所述单晶半导体包括单晶硅或单晶锗。
  3. 根据权利要求1所述的半导体结构，其中，多个所述存储单元的所述垂直晶体管在所述衬底上呈交错排布的阵列结构。
  4. 根据权利要求3所述的半导体结构，其中，单个所述连接垫与三个所述垂直晶体管的一端相连。
  5. 根据权利要求3所述的半导体结构，其中，所述垂直晶体管沿所述衬底表面方向上的截面呈圆形，所述连接垫沿所述衬底表面方向上的截面呈三角形，所述三角形的顶点分别位于所述圆形截面的中点。
  6. 根据权利要求5所述的半导体结构，其中，所述磁性隧道结在所述衬底上的投影位于所述连接垫位于所述衬底上的投影内部。
  7. 根据权利要求4所述的半导体结构，其中，相邻两行所述存储单元中的所述垂直晶体管位于所述阵列结构的连续三行中。
  8. 根据权利要求5所述的半导体结构，其中，还包括：
    多个间隔排布的字线，所述字线的延伸方向与所述三角形的其中一个边长方向相同。
  9. 根据权利要求8所述的半导体结构，其中，所述字线包括栅电极部分和导线部分；
    所述栅电极部分连接单个存储单元中的所述垂直晶体管的所述沟道，所述导线部分连接多个所述栅电极部分。
  10. 根据权利要求9所述的半导体结构，其中，所述栅电极部分和所述连接垫在所述衬底表面上的投影重合。
  11. 根据权利要求10所述的半导体结构，其中，所述栅电极部分和所述导线部分在同一刻蚀步骤中形成。
  12. 根据权利要求9所述的半导体结构，其中，所述字线部分的宽度小于所述垂直晶体管之间的间距。
  13. 一种半导体结构的制造方法，包括：
    提供衬底，在所述衬底上形成多个垂直晶体管；其中，所述垂直晶体管的沟道材料包括单晶半导体；
    在所述多个垂直晶体管远离所述衬底的上方形成多个连接垫，以使一个连接垫在所述衬底上的投影与奇数个垂直晶体管的投影重叠；
    在每个所述连接垫远离所述垂直晶体管的上方形成一个磁性隧道结。
  14. 根据权利要求13所述的制造方法，其中，在所述衬底上形成多个垂直晶体管，具体包括：
    在所述衬底上形成共源极板；
    在所述共源极板上形成多个呈着阵列排布的垂直沟道；
    在所述共源极板上形成连接奇数个的垂直沟道的栅电极部分和连接所述栅电极部分的导线部分；
    在每个所述垂直沟道远离所述共源极板的表面形成漏极板。
  15. 根据权利要求14所述的制造方法，其中，在所述共源极板上形成连接奇数个的垂直沟道的栅电极部分和连接所述栅电极部分的导线部分，具体包括：
    在所述共源极板远离所述衬底的表面沉积金属材料，以形成栅极板；
    在所述栅极板形成多个呈三角形的掩膜图形，并使三个垂直沟道在所述掩膜图形上的投影位于所述三角形的掩膜图形的内部；
    在所述栅极板形成多个呈条状的掩膜图形，并使条状的掩膜图形与三角形的掩膜图形相互重叠；
    对所述栅极板进行刻蚀，形成栅电极部分和连接所述栅电极部分的导线部分。
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US20070080385A1 (en) * 2005-10-10 2007-04-12 Samsung Electronics Co., Ltd. Semiconductor device having vertical transistor and method of fabricating the same
CN109461756A (zh) * 2017-09-06 2019-03-12 中国科学院微电子研究所 Mram及其制造方法及包括mram的电子设备
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US20070080385A1 (en) * 2005-10-10 2007-04-12 Samsung Electronics Co., Ltd. Semiconductor device having vertical transistor and method of fabricating the same
CN109461756A (zh) * 2017-09-06 2019-03-12 中国科学院微电子研究所 Mram及其制造方法及包括mram的电子设备
CN111816673A (zh) * 2019-04-10 2020-10-23 长鑫存储技术有限公司 磁性随机存储器及其形成方法

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