WO2023028884A1 - Circuit de calcul de nombre à virgule flottante et procédé de calcul de nombre à virgule flottante - Google Patents

Circuit de calcul de nombre à virgule flottante et procédé de calcul de nombre à virgule flottante Download PDF

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Publication number
WO2023028884A1
WO2023028884A1 PCT/CN2021/115811 CN2021115811W WO2023028884A1 WO 2023028884 A1 WO2023028884 A1 WO 2023028884A1 CN 2021115811 W CN2021115811 W CN 2021115811W WO 2023028884 A1 WO2023028884 A1 WO 2023028884A1
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mantissa
floating
point number
circuit
split
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PCT/CN2021/115811
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English (en)
Chinese (zh)
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毛伟
余浩
谢环
董镇江
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华为技术有限公司
南方科技大学
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Priority to CN202180096895.1A priority Critical patent/CN117178253A/zh
Priority to PCT/CN2021/115811 priority patent/WO2023028884A1/fr
Publication of WO2023028884A1 publication Critical patent/WO2023028884A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations

Definitions

  • the embodiment of the present application relates to the computer field, and further relates to the application of artificial intelligence (AI) technology in the computer field, especially a floating-point number calculation circuit and a floating-point number calculation method.
  • AI artificial intelligence
  • Artificial Intelligence is a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.
  • artificial intelligence is the branch of computer science that attempts to understand the nature of intelligence and produce a new class of intelligent machines that respond in ways similar to human intelligence.
  • Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that the machines have the functions of perception, reasoning and decision-making.
  • Research in the field of artificial intelligence includes robotics, natural language processing, computer vision, decision-making and reasoning, human-computer interaction, recommendation and search, basic AI theory, etc.
  • Convolution neural network is currently widely used in various types of image processing applications.
  • FP floating point
  • FP16 data Insufficient precision will lead to non-convergence or slow convergence of network training, so it is necessary to use higher-precision FP32 data to ensure the effect of network training.
  • higher-precision FP64 data In addition, in supercomputing applications, it is necessary to use higher-precision FP64 data for numerical calculations.
  • a multiplier with a smaller number of digits can be used to calculate a floating-point number with a larger number of digits.
  • FP64 type floating-point data can be calculated by a multiplier used to calculate FP32 data.
  • the network device splits the FP64 floating-point data into smaller floating-point numbers for multiplication, and then adds the results of the multiplication through the adder to obtain the product of the FP64 floating-point data.
  • the number of bits of the adder required to add the results of the multiplication operation is large, and the cost of hardware design is high, which is not conducive to technology promotion.
  • the embodiment of the present application provides a floating-point number calculation circuit and a floating-point number calculation method.
  • the floating-point number calculation circuit can split a floating-point number with a large number of digits into a floating-point number with a small number of digits. Therefore, the floating-point number calculation circuit
  • the timing overhead is short, the hardware design cost is low, and the calculation performance of the multiplier is reasonably utilized.
  • the first aspect of the present application provides a floating-point number calculation circuit, the floating-point number calculation circuit is used to calculate the product of a first floating-point number and a second floating-point number, the first floating-point number includes a first exponent and a first mantissa, The second floating-point number includes a second exponent and a second mantissa, and the floating-point number calculation circuit includes: an exponent processing circuit and a calculation circuit; an output terminal of the exponent processing circuit is electrically connected to an input terminal of the calculation circuit;
  • the index processing circuit is used to obtain a first shift number according to the first index and the second index, and the first shift number is used to represent the product between the first split mantissa and the second split mantissa
  • the number of shifts, the first split mantissa is obtained by splitting the first mantissa, and the second split mantissa is obtained by splitting the second mantissa; the calculation circuit is used to select and output multiple Part of the data in the first
  • the calculation circuit in the floating-point number calculation circuit may select to output some data in the multiple first operation results to obtain multiple first addition data and multiple second addition data.
  • the calculation circuit splits the multiple first calculation results with higher digits into multiple first addition data and multiple second addition data with lower digits by selecting part of the data in the first calculation results, and then, by The adder with a smaller bit width sums the plurality of first addition data, the plurality of second addition data and the plurality of first operation results with a lower number of bits to obtain the product of the first mantissa and the second mantissa.
  • the bit width of the adder used when calculating the product of the mantissa part of the first floating point number and the second floating point number is small, and the hardware design cost is low, which is more conducive to technology promotion.
  • the calculation circuit includes a multiplication circuit, an addition circuit, and a first selection circuit; the output terminal of the exponent processing circuit is electrically connected to the input terminal of the multiplication circuit; the first The input end of a selection circuit is electrically connected to the output end of the multiplication circuit, and the output end of the first selection circuit is electrically connected to the input end of the addition circuit; the first selection circuit is used to select and output a plurality of The low-order data in the first operation result obtains a plurality of the first addition data, and selects and outputs the high-order data in the first operation result to obtain a plurality of the second addition data; the addition circuit uses After adding a plurality of the first addition data and a plurality of the first operation results to obtain a low addition result and carry data, for the carry data, the plurality of second addition data and the plurality of first The operation results are added to obtain a high-order addition result, and the product of the first mantissa and the second mantissa is
  • the first selection circuit can select to output the low-order data in the plurality of first operation results to obtain a plurality of first addition data, and select to output a plurality of first addition data.
  • the high-order data in the operation result obtains a plurality of second addition data.
  • the first selection circuit may split the first operation result with a large number of bits into first addition data and second addition data with a small number of bits. Further, the first addition data and the second addition data are respectively summed with the corresponding first operation result to obtain a low bit addition result and a high bit addition result. Since the bit width of the low-order addition result and the high-order addition result is small, the adder used for calculating the low-order addition result and the high-order addition result has a small bit width, which reduces the construction cost of the calculation circuit.
  • the adding circuit includes a first adder and an accumulator; the input end of the first adder is electrically connected to the output end of the first selection circuit, and the first The output end of an adder is electrically connected to the input end of the accumulator; the first adder is used to compare a plurality of first addition data and a plurality of first operation results in a first calculation cycle adding the low-order addition result and the carry data, and adding the carry data, a plurality of the second addition data, and a plurality of the first operation results in a second calculation cycle to obtain the high-order addition result;
  • the accumulator is configured to accumulate the low-order addition result and the high-order addition result to obtain a product of the first mantissa and the second mantissa.
  • the length of the mantissa part of the FP64 floating point number is 53 bits. Therefore, the total length of the mantissa obtained after calculating A_mantissa*B_mantissa is 106 bits. If you want to directly complete the calculation of the mantissa part of a pair of FP64 type floating-point numbers in a calculation unit (PE unit), the adder (the first adder) needs to be expanded into an adder that supports data calculations with a length of 106 bits. The area cost and timing cost of the subsequent adder are too high.
  • the multiplication of a pair of FP64 mantissa can be selected and split into two parts (part1 and part2) by the first selection circuit, and the first adder calculates the part1 part in the first calculation cycle to obtain the low addition result, and in the second cycle Calculate part2 to get the high-order addition result.
  • the accumulator accumulates the results of the two calculation cycles to obtain the product of the first mantissa and the second mantissa. Since the bit width of the low-order addition result and the high-order addition result is small, the adder used for calculating the low-order addition result and the high-order addition result has a small bit width, which reduces the construction cost of the floating-point number calculation circuit.
  • the floating-point number calculation circuit further includes a splitting circuit; the output end of the splitting circuit is electrically connected to the input end of the exponent processing circuit and the input end of the multiplication circuit connection; the splitting circuit is used to split the first mantissa into the first split mantissa, the first split mantissa includes a first high-order mantissa and a first low-order mantissa, and the second The mantissa is split into the second split mantissa, the second split mantissa includes a second high-order mantissa and a second low-order mantissa, and the first shift number is used to indicate the highest bit of each high-order mantissa and each low-order mantissa The shift difference between the highest bits of .
  • the floating-point number calculation circuit can split the mantissa part with the larger number of digits of the first floating-point number into the first high-order mantissa and the first low-order mantissa with smaller digits, and the second The mantissa part with a large number of floating-point numbers is split into the second high-order mantissa and the second low-order mantissa with a smaller number of digits, so that a multiplier with a smaller number of digits is used to calculate the product of each split mantissa part, reducing the The design cost of the hardware rationally utilizes the computing performance of the multiplier.
  • the first high-order mantissa includes a third mantissa
  • the first low-order mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa
  • the first The second high order mantissa includes the eighth mantissa
  • the second low order mantissa includes the ninth mantissa, the tenth mantissa, the eleventh mantissa and the twelfth mantissa.
  • a specific splitting method for the first mantissa and the second mantissa is provided. After splitting the mantissa part of the FP64 floating-point number using this splitting method, you can use FP32 After the mantissa part of the FP128 type floating-point number is split by this split method, the FP64 type multiplier can be used for calculation.
  • This splitting method can realize the multiplication of the first mantissa and the second mantissa by using a multiplier with a smaller number of digits. The construction cost of the floating-point number calculation circuit is reduced, and it is more conducive to technology promotion.
  • the floating-point number calculation circuit further includes a storage circuit; the output terminal of the splitting circuit is electrically connected to the input terminal of the storage circuit; the input terminal of the exponent processing circuit It is electrically connected to the first output end of the storage circuit; the input end of the calculation circuit is electrically connected to the second output end of the storage circuit; the storage circuit is used to store the first split mantissa, the The second split mantissa, the first exponent, the second exponent, the third shift number and the fourth shift number, the third shift number is used to represent the shift of the first split mantissa number of digits, the fourth shift digit is used to represent the shift digit of the second split mantissa.
  • This possible implementation method provides a specific implementation method for storing temporary data in a floating-point number calculation circuit, which improves the feasibility of the solution.
  • the exponent processing circuit includes a second adder, a second selection circuit, and a third adder; the input terminal of the second adder is connected to the first The output end is electrically connected, the output end of the second adder is electrically connected to the first input end of the third adder; the second input end of the third adder is connected to the output end of the second selection circuit Electrically connected, the output end of the third adder is electrically connected to the first input end of the calculation circuit; the second adder is used to combine the first index, the second index, the first Three shift numbers and the fourth shift number are added to obtain a plurality of second operation results; the second selection circuit is used to select a maximum value among the plurality of second operation results; the third addition and a device, configured to subtract the maximum value among the plurality of second operation results from each second operation result to obtain the first shift number.
  • This possible implementation method provides a specific implementation form of the index processing circuit, which improves the feasibility of the solution.
  • the multiplication circuit includes a multiplier and a shift register; the input end of the multiplier is electrically connected to the second output end of the storage circuit, and the output end of the multiplier end is electrically connected with the first input end of the shift register; the second input end of the shift register is electrically connected with the output end of the third adder; the output end of the shift register is electrically connected with the first input end of the shift register
  • the input terminal of an adder is electrically connected; the multiplier is used to multiply the first split mantissa and the second split mantissa to obtain a plurality of third operation results;
  • the first shift number performs shift processing on a plurality of the third operation results to obtain a plurality of the first operation results.
  • This possible implementation method provides a specific implementation form of the multiplication circuit, which improves the feasibility of the solution.
  • the floating-point number calculation circuit further includes a memory controller; the output terminal of the memory controller is electrically connected to the input terminal of the splitting circuit; the memory controller, It is used to obtain the first floating point number and the second floating point number, and send the first floating point number and the second floating point number to the splitting circuit.
  • This possible implementation manner provides a specific implementation form of a hardware structure capable of obtaining the first floating-point number and the second floating-point number, which improves the feasibility of the solution.
  • the first floating-point number further includes a first sign bit
  • the second floating-point number further includes a second sign bit
  • the second aspect of the present application provides a floating-point number calculation method for calculating the product of a first floating-point number and a second floating-point number, the first floating-point number includes a first exponent and a first mantissa, and the second floating-point number Including a second exponent and a second mantissa, the method includes: obtaining a first shift number according to the first exponent and the second exponent, and the first shift number is used to represent the first split mantissa and the second mantissa
  • the shift number of the product between the two split mantissas, the first split mantissa is obtained by splitting the first mantissa
  • the second split mantissa is obtained by splitting the second mantissa; select and output multiple Part of the data in the first operation result obtains a plurality of first addition data and a plurality of second addition data, based on a plurality of the first addition data, a plurality of the second addition data, and a plurality of
  • partial data in multiple first operation results may be selected to be output to obtain multiple first addition data and multiple second addition data.
  • a plurality of first operation results with a higher number of digits are split into a plurality of first addition data and a plurality of second addition data with a lower number of digits, and then, by bit width
  • the smaller adder sums the plurality of first addition data, the plurality of second addition data and the plurality of first operation results with lower digits to obtain the product of the first mantissa and the second mantissa.
  • the bit width of the adder used when calculating the product of the mantissa part of the first floating point number and the second floating point number is small, and the hardware design cost is low, which is more conducive to technology promotion.
  • partial data in the multiple first operation results may be selected to be output to obtain multiple first addition data and multiple second addition data.
  • a plurality of first operation results with higher digits are split into a plurality of first addition data and a plurality of second addition data with lower number of digits, and then, by bit The adder with smaller width sums the multiple first addition data, the multiple second addition data and the multiple first operation results with lower number of digits to obtain the product of the first mantissa and the second mantissa.
  • the bit width of the adder used when calculating the product of the mantissa part of the first floating point number and the second floating point number is small, and the hardware design cost is low, which is more conducive to technology promotion.
  • the selecting and outputting part of the data in the multiple first operation results obtains multiple first addition data and multiple second addition data, and according to the multiple first addition data
  • Obtaining the product of the first mantissa and the second mantissa for a plurality of second addition data and a plurality of first operation results includes: selecting and outputting low-order data in a plurality of first operation results to obtain A plurality of the first addition data, select and output the high-order data in the plurality of first operation results to obtain a plurality of the second addition data; for the plurality of the first addition data and the plurality of the first operation The results are added to obtain a low-order addition result and carry data, and the carry data, a plurality of the second addition data and a plurality of the first operation results are added to obtain a high-order addition result, and the high-order addition result and the The product of the first mantissa and the second mantissa is obtained after the low-order addition results are accumulated.
  • the addition of the plurality of first addition data and the plurality of first operation results obtains the low-order addition result and carry data, and the carry data, the plurality of Adding the second addition data and a plurality of the first operation results to obtain a high-order addition result, and accumulating the high-order addition result and the low-order addition result to obtain a product of the first mantissa and the second mantissa , including: adding a plurality of first addition data and a plurality of first operation results in a first calculation cycle to obtain the low-order addition result and the carry data, and adding the carry data in a second calculation cycle , adding a plurality of the second addition data and a plurality of the first operation results to obtain the high-order addition result; accumulating the low-order addition result and the high-order addition result to obtain the first mantissa and the The product of the second mantissa.
  • both the first floating point number and the second floating point number are FP64 floating point numbers. Since the length of the mantissa part of the FP64 floating point number is 53 bits. Therefore, the total length of the mantissa obtained after calculating A_mantissa*B_mantissa is 106 bits. If you want to directly complete the calculation of the mantissa part of a pair of FP64 type floating-point numbers in a calculation unit (PE unit), the adder (the first adder) needs to be expanded into an adder that supports data calculations with a length of 106 bits. The area cost and timing cost of the subsequent adder are too high.
  • the method further includes: splitting the first mantissa into the first split mantissa, the first split mantissa includes the first high order mantissa and the first a low mantissa, splitting the second mantissa into the second split mantissa, the second split mantissa includes a second high mantissa and a second low mantissa, and the first shift number is used to indicate each high bit The shifted difference between the most significant bit of the mantissa and the most significant bit of each lower mantissa.
  • the mantissa part of the first floating-point number with a large number of digits can be split into the first high-order mantissa and the first low-order mantissa with a small number of digits, and the mantissa with a large second floating-point number The part is split into the second high-order mantissa and the second low-order mantissa with a smaller number of digits, so that a multiplier with a smaller number of digits is used to calculate the product of each mantissa after splitting, which reduces the design cost of the hardware and makes reasonable use of performance of the multiplier.
  • the first high-order mantissa includes a third mantissa
  • the first low-order mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa
  • the first The second high order mantissa includes the eighth mantissa
  • the second low order mantissa includes the ninth mantissa, the tenth mantissa, the eleventh mantissa and the twelfth mantissa.
  • a specific splitting method for the first mantissa and the second mantissa is provided. After splitting the mantissa part of the FP64 floating-point number using this splitting method, you can use FP32 After the mantissa part of the FP128 type floating-point number is split by this split method, the FP64 type multiplier can be used for calculation.
  • This splitting method can realize the multiplication of the first mantissa and the second mantissa by using a multiplier with a smaller number of digits. The construction cost of the floating-point number calculation circuit is reduced, and it is more conducive to technology promotion.
  • the method further includes: storing the first split mantissa, the second split mantissa, the first exponent, the second exponent, the third shift number of digits and a fourth shift digit, the third shift digit is used to represent the shift digit of the first split mantissa, and the fourth shift digit is used to represent the shift digit of the second split mantissa digits.
  • This possible implementation method provides a specific implementation method for storing temporary data in a floating-point number calculation method, which improves the feasibility of the solution.
  • the obtaining the first shift number according to the first index and the second index includes: selecting a maximum value among the plurality of second operation results; The maximum value in the second operation results is respectively subtracted from the second operation results to obtain the first shift number.
  • This possible implementation manner provides a specific implementation form for obtaining the first shift number, which improves the feasibility of the solution.
  • the method further includes: multiplying the first split mantissa and the second split mantissa to obtain multiple third operation results; A shift number performs shift processing on a plurality of the third operation results to obtain a plurality of the first operation results.
  • This possible implementation manner provides a specific implementation form for obtaining the first operation result, which improves the feasibility of the solution.
  • the method further includes: acquiring the first floating point number and the second floating point number.
  • the first floating-point number further includes a first sign bit
  • the second floating-point number further includes a second sign bit
  • the third aspect of the present application provides a floating-point number calculation circuit
  • the floating-point number calculation circuit includes: an index processing circuit and a calculation circuit, the calculation circuit includes a first multiplication circuit, a first selector and an addition circuit; the index The output end of the processing circuit is electrically connected to the input end of the first multiplication circuit; the output end of the first multiplication circuit is electrically connected to the input end of the first selector; the output end of the first selector is electrically connected to the input end of the first selector.
  • the input end of the adding circuit is electrically connected.
  • the first multiplication circuit in the process of calculating the product of the mantissa parts of two floating-point numbers by the calculation circuit in the floating-point number calculation circuit, the first multiplication circuit will output multiple calculation results, and the first selector can place multiple calculation results in The operation result with a larger number is split into the first addition data and the second addition data with a smaller number of digits, and then, in the addition circuit, a plurality of first addition data with lower digits can be combined by an adder with a smaller bit width. and summing the plurality of second addition data and the plurality of first operation results to obtain a product of the first mantissa and the second mantissa.
  • the bit width of the adder used when calculating the product of the mantissa part of the first floating point number and the second floating point number is small, and the hardware design cost is low, which is more conducive to technology promotion.
  • the floating-point number calculation circuit is used to calculate the product of the first floating-point number and the second floating-point number, and the first floating-point number includes the first exponent, the first mantissa, and the first Sign bit, the second floating point number includes a second exponent, a second mantissa and a second sign bit; the input end of the exponent processing circuit is used to receive the first exponent and the second exponent; the calculation circuit The input terminal of is used to receive the first mantissa and the second mantissa.
  • the adding circuit includes a first adder and an accumulator; the input end of the first adder is electrically connected to the output end of the first selector, and the first adder The output of an adder is electrically connected to the input of the accumulator.
  • the first adder can use the first addition data and multiple unsplit
  • the low-order addition result is obtained from the operation result
  • the high-order addition result is obtained according to the second addition data and the multiple divided operation results.
  • the accumulator sums the low-order addition result and the high-order addition result to obtain the product of the first mantissa and the second mantissa. Since the bit width of the low-order addition result and the high-order addition result is small, the first adder used for calculating the low-order addition result and the high-order addition result has a small bit width, which reduces the construction cost of the calculation circuit.
  • the first multiplication circuit includes a first multiplier and a first shift register; the first input terminal of the first shift register is connected to the output of the exponent processing circuit The terminal is electrically connected, the second input terminal of the first shift register is electrically connected to the output terminal of the first multiplier, and the output terminal of the first shift register is electrically connected to the input terminal of the first selector. connect.
  • the first multiplier can calculate the product between the split first mantissa and the split second mantissa, and the first shift register can be based on the shift number output by the exponent processing circuit. The result output by the first multiplier is shifted, and the operation result is output after the shift.
  • This possible implementation provides a specific implementation of the multiplication circuit, which improves the feasibility of the solution.
  • the exponent processing circuit includes a second adder, a second selector, and a third adder; the output terminal of the second adder is connected to the first The first input end of the three adders is electrically connected; the second input end of the third adder is electrically connected to the output end of the second selector, and the output end of the third adder is electrically connected to the first shifter.
  • the first input terminal of the bit register is electrically connected.
  • This possible implementation method provides a specific implementation form of the index processing circuit, which improves the feasibility of the solution.
  • the calculation circuit further includes a second multiplication circuit, and the second multiplication circuit includes a second multiplier and a second shift register; the second shift register of the second shift register An input terminal is electrically connected to the output terminal of the index processing circuit, a second input terminal of the second shift register is electrically connected to the output terminal of the second multiplier, and an output terminal of the second shift register It is electrically connected with the input terminal of the first adder.
  • the second multiplier in the second multiplication circuit multiplies the split first mantissa and the split second mantissa, and the second shift register is based on the shift output from the exponent processing circuit.
  • the number shifts the result output by the second multiplier to obtain multiple operation results.
  • the second shift register directly inputs a plurality of operation results to the first adder, so that the first adder can combine the first addition result output in the first multiplication circuit, the second addition result and the multiplication result output by the second shift register.
  • the results of two operations are summed to obtain the product of the first mantissa and the second mantissa.
  • the floating-point number calculation circuit further includes a memory controller, a third selector, and a register; the input end of the third selector is electrically connected to the output end of the memory controller The output end of the third selector is electrically connected to the input end of the register; the first output end of the register is electrically connected to the input end of the index processing circuit, and the second output end of the register is electrically connected to the input end of the index processing circuit.
  • the input terminals of the calculation circuit are electrically connected.
  • the memory controller transmits the first floating-point number and the second floating-point number acquired at the memory to the third selector, and the third selector splits the first mantissa and the second mantissa and then inputs them to the register save.
  • This possible implementation improves the feasibility of the solution.
  • a third aspect of the embodiments of the present application provides a computing device, and the computing device includes a control circuit and a floating-point number computing circuit.
  • the floating-point number calculation circuit calculates data under the control of the control circuit, and the floating-point number calculation circuit is the floating-point number calculation circuit described in the first aspect or any possible implementation of the first aspect, or,
  • the floating-point number calculation circuit is the floating-point number calculation circuit described in the third aspect or any possible implementation manner of the third aspect.
  • Fig. 1 is the processing schematic diagram of the convolutional neural network provided by the present application.
  • Fig. 2 is the composition schematic diagram of the floating-point number of FP32 type that the embodiment of the present application provides;
  • FIG. 3 is a schematic structural diagram of a floating-point number calculation circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a computing circuit provided by an embodiment of the present application.
  • Fig. 5 is another schematic structural diagram of a computing circuit provided by an embodiment of the present application.
  • Fig. 6 is another schematic structural diagram of a computing circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the mantissa part of the first floating-point number and the second floating-point number provided in the present application;
  • FIG. 8 is a schematic structural diagram of a computing circuit provided in this application.
  • FIG. 9 is a schematic diagram of an operation process of a computing circuit provided in the present application.
  • FIG. 10 is a schematic diagram of an embodiment of a floating-point number calculation circuit provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a split circuit provided by the present application.
  • FIG. 14 is a schematic structural diagram of a first mantissa and a second mantissa provided by the present application;
  • FIG. 15 is a schematic structural diagram of a storage circuit provided by the present application.
  • FIG. 16 is a schematic diagram of a connection relationship between a memory controller and memory provided by the present application.
  • FIG. 17 is a schematic structural diagram of an index processing circuit provided in this application.
  • FIG. 18 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • FIG. 19 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • FIG. 20 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • FIG. 21 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • Artificial Intelligence is a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.
  • artificial intelligence is the branch of computer science that attempts to understand the nature of intelligence and produce a new class of intelligent machines that respond in ways similar to human intelligence.
  • Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that the machines have the functions of perception, reasoning and decision-making.
  • Research in the field of artificial intelligence includes robotics, natural language processing, computer vision, decision-making and reasoning, human-computer interaction, recommendation and search, basic AI theory, etc.
  • Fig. 1 is a processing schematic diagram of the convolutional neural network provided by the present application.
  • Convolutional neural network has broad application prospects in image, speech recognition and other fields.
  • the convolutional neural network needs to perform convolution operations on multiple convolution kernels and one or more feature maps. Specifically, for each convolution kernel, start from the first pixel of the feature map, and move pixel by pixel in the row direction. When the end of the row is reached, move down one pixel in the column direction, and return to the row direction starting point, and repeat the process of moving in the row direction until all pixels of the feature map are traversed.
  • the parameters in the convolution kernel and the data in the corresponding position of the feature map are used as the two parts of the convolution operation to perform the convolution operation (multiply two by two and then accumulate the products one by one), After the convolution result is obtained, the convolution result is output.
  • Convolution neural network is currently widely used in various types of image processing applications.
  • image processing applications use floating point (floating point, FP) 16 types of data to perform network training on the model
  • FP16 floating point
  • FP32 floating point
  • the floating-point calculation circuit involved in the present invention can be applied not only in the field of artificial intelligence, but also in the field of data signal processing, such as image processing systems, radar systems and communication systems.
  • the circuit and method can optimize the performance of digital signal processing (DSP) or other digital devices.
  • DSP digital signal processing
  • LTE long term evolution
  • UMTS universal mobile telecommunications system
  • GSM global system for mobile communications
  • a multiplier with a smaller number of digits can be used to calculate a floating-point number with a larger number of digits.
  • FP64 type floating-point data can be calculated by a multiplier used to calculate FP32 data.
  • the network device splits the FP64 floating-point data into smaller floating-point numbers for multiplication, and then adds the results of the multiplication through the adder to obtain the product of the FP64 floating-point data.
  • the bit width of the adder required for adding the multiplication results is large, and the hardware design cost is high, which is not conducive to technology promotion.
  • the embodiments of the present application provide a floating-point number calculation circuit, a floating-point number calculation method, and a calculation device.
  • the bit width of the adder used when calculating the product of the mantissa part of the first floating point number and the second floating point number is small, and the hardware design cost is low, which is more conducive to technology promotion.
  • each floating-point number consists of three parts, namely the sign bit (sign), the exponent bit (exp) and the mantissa bit (mantissa).
  • sign the sign bit
  • exp the exponent bit
  • mantissa the mantissa bit
  • the actual value of a floating point number is equal to sign*2 exp *mantissa.
  • FIG. 2 is a schematic diagram of composition of FP32 type floating-point numbers provided by the embodiment of the present application.
  • the FP32 floating-point number has 1-bit sign, 8-bit exp and 24-bit mantissa, displaying a total of 32 bits stored. Among them, the highest bit of mantissa is implicitly stored (if exp is not 0, the hiden bit is 1, otherwise the hiden bit is 0), and the three parts total 32 bits.
  • the floating-point number calculation circuit, floating-point number calculation method and calculation device provided by the application will be introduced in detail below in conjunction with the accompanying drawings in the application. First, the floating-point number calculation circuit provided by the application will be introduced.
  • FIG. 3 is a schematic structural diagram of a floating-point number calculation circuit provided by an embodiment of the present application.
  • the floating-point number calculation circuit includes at least an exponent processing circuit 101 and a calculation circuit 102 .
  • the output end of the index processing circuit 101 is electrically connected to the input end of the calculation circuit 102 .
  • the floating-point number calculation circuit is used to calculate the product of the first floating-point number and the second floating-point number.
  • the first floating point number includes a first exponent and a first mantissa
  • the second floating point number includes a second exponent and a second mantissa.
  • the exponent processing circuit 101 and the calculation circuit 102 can calculate the product of the mantissa part of the first floating point number and the second floating point number according to the first floating point number and the second floating point number. This calculation process will be explained below.
  • the exponent processing circuit 101 may obtain the first shift number according to the first exponent and the second exponent.
  • the first shift number is used to represent the shift number of the product between the first split mantissa and the second split mantissa.
  • the first split mantissa is obtained by splitting the first split mantissa, and the second split mantissa is split by the second split mantissa. Get it.
  • the calculation circuit 102 may select to output part of the data in the multiple first calculation results to obtain the multiple first addition data and the multiple second addition data.
  • the multiple first addition data the multiple second addition data and Multiple first operation results obtain the product of the first mantissa and the second mantissa, and the first operation result is used to represent the data obtained after the product of the first split mantissa and the second split mantissa is shifted according to the first shift number .
  • the calculation circuit in the floating-point number calculation circuit may select to output some data in the multiple first operation results to obtain multiple first addition data and multiple second addition data.
  • the calculation circuit splits the multiple first calculation results with higher digits into multiple first addition data and multiple second addition data with lower digits by selecting part of the data in the first calculation results, and then, by The adder with a smaller bit width sums the plurality of first addition data, the plurality of second addition data and the plurality of first operation results with lower bits to obtain the product of the first mantissa and the second mantissa.
  • the bit width of the adder used when calculating the product of the mantissa part of the first floating point number and the second floating point number is small, and the hardware design cost is low, which is more conducive to technology promotion.
  • FIG. 4 is a schematic structural diagram of a calculation circuit 102 provided in an embodiment of the present application.
  • the calculation circuit 102 may include a multiplication circuit 201 , a first selection circuit 202 and an addition circuit 203 .
  • the output terminal of the exponent processing circuit 101 is electrically connected to the input terminal of the multiplication circuit 201 .
  • the input end of the first selection circuit 202 is electrically connected to the output end of the multiplication circuit 201
  • the output end of the first selection circuit 202 is electrically connected to the input end of the addition circuit 203 .
  • the first selection circuit 202 may select and output low-order data among the multiple first operation results to obtain multiple first addition data, and select and output high-order data among the multiple first operation results to obtain multiple second addition data.
  • the addition circuit 203 can add a plurality of first addition data and a plurality of first operation results to obtain a low-order addition result and carry data, and add the carry data, a plurality of second addition data and a plurality of first operation results to obtain a high-order addition As a result, the product of the first mantissa and the second mantissa is obtained after the high-order addition result and the low-order addition result are accumulated.
  • the addition circuit 203 and/or more first selection circuits 202 are not limited here.
  • the adding circuit 203 has a specific implementation manner. The following will take FIG. 5 as an example to illustrate a specific implementation form of the adding circuit 203 provided in the present application.
  • FIG. 5 is another schematic structural diagram of a computing circuit provided by an embodiment of the present application.
  • the adding circuit 203 may include a first adder 301 and an accumulator 302 .
  • the input end of the first adder 301 is electrically connected to the output end of the first selection circuit 202
  • the output end of the first adder 301 is electrically connected to the input end of the accumulator 302 .
  • the first adder 301 can add a plurality of first addition data and a plurality of first operation results in the first calculation cycle to obtain the low-order addition result and carry data, and in the second calculation cycle, the carry data and the plurality of second addition data and adding the multiple first operation results to obtain a high-order addition result.
  • the accumulator 302 may accumulate the low bit addition result and the high bit addition result to obtain the product of the first mantissa and the second mantissa.
  • the numbers of the first adder 301 and the number of accumulators 302 included in the adding circuit 203 shown in FIG. 5 are only for illustration.
  • the adding circuit 203 may include more first adders 301 and/or more accumulators 302, which are not limited here.
  • the multiplication circuit 201 has a specific implementation manner. The following will take FIG. 6 as an example to illustrate a specific implementation form of the multiplication circuit 201 provided in this application.
  • FIG. 6 is another schematic structural diagram of a computing circuit provided by an embodiment of the present application.
  • the multiplication circuit 201 includes a multiplier 303 and a shift register 304;
  • the input terminal of the multiplier 303 is electrically connected to the output terminal of the exponent processing circuit 101 , and the output terminal of the multiplier 303 is electrically connected to the input terminal of the shift register 304 .
  • the multiplier 303 may multiply the first split mantissa and the second split mantissa to obtain multiple third operation results.
  • the shift register 304 can perform shift processing on multiple third operation results according to the multiple first shift numbers to obtain multiple first operation results.
  • the format of the mantissa part of the first floating point number and the second floating point number is first introduced.
  • Fig. 7 is a schematic diagram of mantissa parts of the first floating point number and the second floating point number provided in this application.
  • the calculation circuit can split the mantissa part (first mantissa) of the first floating-point number A into five parts a0, a1, a2, a3, and a4.
  • the mantissa part (second mantissa) of the second floating point number B is split into five parts b0, b1, b2, b3 and b4.
  • a0, a1, a2, a3, and a4 are the first split mantissas
  • b0, b1, b2, b3, b4 are the second split mantissas.
  • the digits of a1, a2, a3, a4, b1, b2, b3, and b4 are all 12 bits
  • the digits of a0 and b0 are 5 bits.
  • the multiplication of the mantissa part of the first floating point number A and the mantissa part of the second floating point number B can be expressed as Formula 1 when the calculation circuit 102 performs operations.
  • the adder (the first adder) needs to be expanded into an adder that supports data calculations with a length of 106 bits.
  • the area cost and timing cost of the subsequent adder are too high. Therefore, you can choose to divide the multiplication of a pair of FP64 mantissa into two parts, calculate the first part (part1) in the above formula in the first calculation cycle, and calculate the second part (part2) in the second calculation cycle.
  • FIG. 8 is a schematic structural diagram of a computing circuit provided in this application.
  • each calculation module respectively calculate the product between the first split mantissa and the second split mantissa such as a0*b4, a4*b0, a1*b3, a3*b1, a2*b2,
  • the a0*b4, a4*b0, a1*b3, a3*b1, and a2*b2 mentioned above are for example illustration.
  • the multiplier will divide the 5 first split mantissas and the 5 second split mantissas into two All the products between the two are calculated, and 25 third operation results are obtained.
  • the first operation result can be obtained.
  • 48bit is the following third operation results a0*b4, a4*b0 , the first shift number of a1*b3, a3*b1, a2*b2.
  • the multiple shift registers can perform shift processing on the multiple third operation results according to the first shift number.
  • the third operation result and the corresponding 48-bit shift number described in the above example are only illustrative. In the actual calculation process, the shift register can shift more third operation results according to other first shift numbers. , the first shift number may also be other shift numbers, which are not limited here.
  • the first selection circuit in the first calculation module and the second calculation module receives the shifted a2*b2, a1*b3, a3*b1, a0*b4 and a4*b0 (the first calculation result ). Since the length of the shifted results of a2*b2, a1*b3, a3*b1, a0*b4, and a4*b0 is 24 bits, the first selection circuit can output the lower 12 bits (first addition data) in the first calculation cycle , through a plurality of 52bit adders (first adder), the lower 12bit and the shifted a1*b4, a4*b1, a2*b3, a3*b2, a3*b3, a2*b4, a4* Add b2, a3*b4, a4*b3, and a4*b4 (the first operation result) to obtain the low-order addition result and carry data, where the carry data refers to the data generated by carry after multiple addition results are calculated.
  • the first selection circuit in the first calculation module and the second calculation module receives a2*b2, a1*b3, a3*b1, a0*b4 and a4*b0 (the first operation result ).
  • the first selection circuit can output the high-order 12 bits (second addition data) in the second calculation cycle , through a plurality of 52-bit adders (first adder), the high-order 12bit and the shifted a0*b0, a0*b1, a1*b0, a0*b2, a2*b0, a1*b1, a0* Add b3, a3*b0, a1*b2 and a2*b1 (the first operation result) and the carry data to obtain the high-order addition result.
  • first adder 52-bit adders
  • the accumulator accumulates the low bit addition result and the high bit addition result to obtain the product of the first mantissa and the second mantissa.
  • the above example illustrates the operation process of the calculation circuit 102 in conjunction with the specific hardware structure in FIG. 8 .
  • the calculation circuit 102 obtains the low-order addition in the first calculation cycle according to the first addition data and the first operation result.
  • FIG. 9 is a schematic diagram of an operation process of a calculation circuit provided in this application.
  • FIG. 9 in which PP1 to PP25 respectively represent a plurality of first operation results, wherein a2*b2, a1*b3, a3*b1, a0*b4 and a4*b0 respectively correspond to PP11 to PP15 in the figure.
  • the sum of the low-order mantissa parts of PP11 to PP15 and other first operation results is calculated in the first calculation cycle, and the sum of the high-order mantissa parts of the carry data PP00, PP11 to PP15 and other first operation results is calculated in the second calculation cycle.
  • the first calculation cycle calculates the sum of 15 groups of low-bit bits, and the low 12 bits of PP1 are taken as the [11:0] bits of the final 106-bit result, and the high 12 bits of PP1 are used as the addition tree. Input for the lower 12 bits. Take the lower 12 bits of PP11 to PP15 as the upper 12 bits in the input 48-bit addition tree, and PP2 to PP10 are as shown in the figure, and the [59:12] bits after the interception and shift are the input of the addition tree, here In the first calculation cycle, the 15 groups of low-bit bits are calculated and accumulated to obtain a 52-bit result.
  • the 48-bit result of [47:0] is the [59:12] bit of the final 106-bit result, and the high-order 4 Bits [51:48] are used as carry data.
  • the second calculation cycle take the high 12 bits of PP11 to PP15 as the low 12 bits in the input 48-bit addition tree, and get the low 12 bits of PP25 as the high 12 bits of the input 48-bit addition tree, here
  • the bit width of PP25 is only 10 bits, so the upper 12 bits of PP25, that is, [23:12] can be ignored, and PP16 to PP24 are as shown in the figure, and the bits [59:12] after interception and shifting are
  • the input of the addition tree is added with the carry signal of the first calculation cycle to obtain a 52-bit result.
  • bit width of the addition tree can be achieved 48bit. It is also possible to completely use the addition tree to cover the carry. At this time, the bit width of the addition tree needs to be 52 bits. Specifically, there is no limitation here.
  • FIG. 10 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • FIG. 10 they are the corresponding positions in the addition tree of the first operation results obtained after the calculation of each part of part1 and part2.
  • the 60bit addition tree can cover the calculation of part1.
  • the addition tree for calculating the low-order addition result (Part1) requires a 52-bit bit width, and the addition tree can completely cover the 4-bit carry of the Part1 part.
  • the addition tree for calculating the high-order addition result (Part2) requires a 48-bit bit width. In this way, for each Part, the addition tree only needs 52 bits at most to realize the multiplication operation between the first mantissa and the second mantissa.
  • FIG. 11 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • the black parts in the figure are the corresponding positions of the first operation results in part1 in the addition tree.
  • the lower 12 bits of a2*b2, a1*b3, a3*b1, a0*b4 and a4*b0 shifted according to the first shift number are located at 48bit-60bit.
  • the shifted a1*b4, a4*b1, a2*b3, and a3*b2 are located at 36bit-60bit.
  • the shifted a3*b3, a2*b4, and a4*b2 are located at 24bit-48bit.
  • the shifted a3*b4 and a4*b3 are located at 12bit-36bit.
  • the shifted a4*b4 is located at 0bit-24bit.
  • FIG. 12 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • the black parts in the figure are the corresponding positions of the first operation results in part2 in the addition tree.
  • the high-order 12 bits of a0*b4 and a4*b0 shifted according to the first shift number are located at 60bit-72bit.
  • the high-order 12 bits of a2*b2, a1*b3, and a3*b1 shifted according to the first shift number are located at 60bit-72bit.
  • a0*b3 and a3*b0 shifted according to the first shift number are located at 60bit-77bit.
  • the shifted a1*b2 and a2*b1 according to the first shift number are located at 60bit-84bit.
  • the shifted a0*b2 and a2*b0 according to the first shift number are located at 72bit-89bit.
  • a1*b1 shifted according to the first shift number is located at 72bit-96bit.
  • the shifted a0*b1 and a1*b0 according to the first shift number are located at 84bit-101bit.
  • the a0*b0 shifted according to the first shift number is located at 96bit-106bit.
  • the floating-point number calculation circuit may also include a splitting circuit.
  • FIG. 13 is a schematic structural diagram of a splitting circuit provided in the present application.
  • the output terminal of the splitting circuit is electrically connected with the input terminal of the exponent processing circuit and the input terminal of the multiplication circuit.
  • the splitting circuit may include a first selector and a register, and an output end of the first selector is electrically connected to an input end of the register.
  • the first selector inputs the first floating-point number and the second floating-point number, and the first selector stores the results obtained after splitting the first floating-point number and the second floating-point number into corresponding registers.
  • FIG. 14 is a schematic structural diagram of a first mantissa and a second mantissa provided by the present application.
  • multiple first selectors in the splitting circuit can split the first mantissa into the first split mantissa, the first split mantissa includes the first high order mantissa and the first low order mantissa, and the first split mantissa
  • the two-mantissa is split into the second split mantissa, the second split mantissa includes the second high-order mantissa and the second low-order mantissa
  • the first shift number is used to indicate the difference between the highest bit of each high-order mantissa and the highest bit of each low-order mantissa shift difference.
  • the first high-order mantissa includes the third mantissa
  • the first low-order mantissa includes the fourth mantissa
  • the fifth mantissa includes the sixth mantissa
  • the second high-order mantissa includes the eighth mantissa
  • the second low-order mantissa includes Ninth mantissa, tenth mantissa, eleventh mantissa, and twelfth mantissa.
  • multiple first selectors in the splitting circuit can split the first mantissa of the first floating-point number into the third mantissa and the fourth mantissa , the fifth mantissa, the sixth mantissa, and the seventh mantissa.
  • the first selector may split the second mantissa of the second floating-point number into an eighth mantissa, a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa.
  • the splitting circuit can split the mantissa part of the first floating-point number into the third mantissa 10001 with a length of 5 bits, the fourth mantissa with a length of 12 bits 100000000001, the fifth mantissa with a length of 12 bits 100000000011, and the sixth mantissa with a length of 12 bits 100000000111 and the seventh mantissa 100000001111 with a length of 12 bits.
  • the third mantissa belongs to the first high mantissa
  • the fourth mantissa, the fifth mantissa, the sixth mantissa, and the seventh mantissa belong to the first low mantissa.
  • the first shift number is used to indicate the shift difference between the highest bit of the high-order mantissa and the highest bit of each low-order mantissa, that is, the first shift number of the first mantissa is 0, and the first shift number of the fourth mantissa is the first
  • the shift difference between the first digit of the four mantissa and the first digit of the third mantissa is 5 bits, which is the same as the number of digits of the third mantissa, so the first shift digit of the fourth mantissa is a right shift of 5 bits.
  • the first shift digit of the fifth mantissa is the 17-bit shift difference between the first digit of the fifth mantissa and the first digit of the third mantissa, which is the same as the sum of the shift digits of the third mantissa and the fourth mantissa, so the fifth The first shift of the mantissa is a right shift of 17 bits.
  • the first shift of the sixth mantissa is the shift difference of 29 bits between the first digit of the sixth mantissa and the first digit of the third mantissa, which is the same as the sum of the shift digits of the third mantissa, the fourth mantissa, and the fifth mantissa , so the first shift of the sixth mantissa is a right shift of 29 bits.
  • the first shift digit of the seventh mantissa is the shift difference of 41 bits between the first digit of the seventh mantissa and the first digit of the third mantissa, and the third digit, the fourth digit, the fifth digit and the sixth digit
  • the sum of the shift digits is the same, so the first shift digit of the seventh mantissa is shifted right by 41 bits.
  • the first high-order mantissa and the second high-order mantissa can also have other different splitting methods, for example, the length of the first digit is 9 bits, and the second mantissa, the third mantissa, the fourth mantissa and the fifth mantissa are all It is 11bit, which is not limited here.
  • the splitting manner of the second high-order mantissa is similar to that of the first high-order mantissa, and the splitting manner of the second low-order mantissa is similar to that of the first low-order mantissa, and details are not described here.
  • the first floating-point number can be a floating-point number of type FP32, the first floating-point number can also be a floating-point number of type FP64, and the first floating-point number can also be a floating-point number of type FP128.
  • the number of points is not limited here.
  • the mantissa part of the first floating-point number may be split into two parts, or may be split into multiple parts, which is not specifically limited here.
  • the number of digits of each mantissa part after splitting may be equal, or the number of digits of each mantissa part after splitting may be unequal, which is not specifically limited here.
  • the floating-point number calculation circuit may further include a storage circuit.
  • the output end of the splitting circuit is electrically connected to the input end of the storage circuit
  • the input end of the index processing circuit is electrically connected to the first output end of the storage circuit.
  • the input terminal of the calculation circuit is electrically connected with the second output terminal of the storage circuit.
  • FIG. 15 is a schematic structural diagram of a storage circuit provided in the present application.
  • a plurality of registers are included in the storage circuit for storing the first split mantissa, the second split mantissa, the first exponent, the second exponent, the third shift number and the fourth shift number, the third The number of shifts is used to represent the number of shifts in the mantissa of the first split, and the fourth number of shifts is used to represent the number of shifts in the mantissa of the second split.
  • the number of registers included in the storage circuit in FIG. 15 is only for illustration.
  • the storage circuit may include more registers than those shown in FIG. 15 , and the storage circuit may include fewer registers than those shown in FIG. 15 , which are not specifically limited here.
  • the floating-point number calculation circuit may further include a memory controller.
  • FIG. 16 is a schematic diagram of a connection relationship between a memory controller and memory provided by the present application.
  • the input end of the memory controller is connected to the output end of the memory, and the output end of the memory controller is electrically connected to the input end of the split circuit.
  • the first floating point number and the second floating point number are stored in the memory, and the memory controller can obtain the first floating point number and the second floating point number, and send the first floating point number and the second floating point number to the splitting circuit.
  • the memory may be a double data rate (DDR) memory, or other memory, which is not specifically limited here.
  • the memory controller may be a DDR controller, or other types of memory controllers, which are not specifically limited here.
  • the index processing circuit 101 has a specific implementation method.
  • the index processing circuit 101 can obtain the first shift number according to the first index and the second index. There is also a specific calculation method. The specific method of the index processing circuit 101 will be described below in conjunction with FIG. 17 Implementation and operation process of the exponent processing circuit 101.
  • FIG. 17 is a schematic structural diagram of an index processing circuit provided in this application.
  • the exponent processing circuit 101 includes at least a second adder 401 , a second selection circuit 402 and a third adder 403 .
  • the input end of the second adder 401 is electrically connected to the first output end of the storage circuit, and the output end of the second adder 401 is electrically connected to the first input end of the third adder 403 .
  • the second input end of the third adder 403 is electrically connected to the output end of the second selection circuit, and the output end of the third adder 403 is electrically connected to the first input end of the calculation circuit 102 .
  • the second adder 401 may add the first exponent, the second exponent, the third shift number and the fourth shift number to obtain multiple second operation results.
  • the second selection circuit 402 may select the maximum value among the multiple second operation results.
  • the third adder 403 subtracts the maximum value among the multiple second operation results from each second operation result to obtain the first shift number.
  • the present application also provides a floating-point number calculation method.
  • the specific implementation of the floating-point number calculation method can be understood with reference to the above-mentioned floating-point number calculation circuits described in FIG. 3 to FIG. 17 , and details are not repeated here.
  • the present application also provides another floating-point number calculation circuit.
  • the specific implementation of the floating-point number calculation method can be understood with reference to the above-mentioned floating-point number calculation circuit described in Figures 3 to 17, and details will not be repeated here.
  • FIG. 18 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • Step 1 Please refer to FIG. 18, the second floating point number B is the data in the filter matrix.
  • the DDR controller memory controller
  • X in Figure 10 is the A_MSB and A_LSB obtained after the mantissa split of each first floating-point number A , and the exponent part EXP corresponding to each A_MSB, A_LSB, the mantissa part of the second floating point number B is split into two parts, MSB and LSB, and stored in the weight RAM (storage circuit), among 1, 2, and N in Fig. 18
  • the included content is B_MSB and B_LSB obtained after splitting the mantissa of each second floating point number B, and the exponent part EXP corresponding to each B_MSB and B_LSB.
  • FIG. 19 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • Step 2 Please refer to Figure 19, the split mantissa in the weight RAM is preloaded into the convolution calculation unit, and at the same time EXP (the exponent part corresponding to each mantissa part after splitting) is processed by EXP offset (the second adder) , which is also preloaded into the convolution computing unit.
  • EXP the exponent part corresponding to each mantissa part after splitting
  • FIG. 20 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • Step 3 Please refer to Figure 20, extract the first segment of mantissa data (Part I) from the data RAM, and the same EXP part is also first processed by exp offset, and then placed in the convolution calculation unit, and the preloaded parameters (Part I) ) to calculate and get the result.
  • FIG. 21 is a schematic diagram of another embodiment of the floating-point number calculation circuit provided by the embodiment of the present application.
  • Step 4 Please refer to FIG. 21 , the convolution processing unit 1 forwards the first piece of data (Part I) to the calculation unit 2, and obtains the second piece of data (Part II) from the data RAM. After the calculation unit 1 acquires the data of the II part, the calculation unit 2 completes the operation and generates the result after acquiring the data of the I part. After each clock, computing units 2-N forward the data processed by the previous clock to the next computing unit, and computing unit 1 acquires new data from the data RAM each time.
  • Step 5 Repeat step 4 until all the data is calculated and the result is generated.

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Abstract

Circuit de calcul de nombre à virgule flottante, procédé de calcul de nombre à virgule flottante et appareil de calcul. Un circuit de calcul dans le circuit de calcul de nombre à virgule flottante peut sélectionner et délivrer une partie de données dans de multiples premiers résultats d'opération pour obtenir de multiples premières données additives et de multiples secondes données additives. Au moyen de la sélection d'une partie de données dans les premiers résultats d'opération, le circuit de calcul divise les multiples premiers résultats d'opération ayant un nombre élevé de bits en de multiples premières données additives et de multiples secondes données additives ayant un faible nombre de bits, puis au moyen d'un additionneur qui a une petite largeur de bits, ajoute les multiples premières données additives et les multiples secondes données additives ayant un faible nombre de bits et les multiples premiers résultats d'opération pour obtenir le produit d'une première mantisse et d'une seconde mantisse. L'additionneur utilisé lors du calcul du produit de parties mantisse d'un premier nombre à virgule flottante et d'un second nombre à virgule flottante a une petite largeur de bits et de faibles coûts de conception de matériel, et convient mieux ainsi à une popularisation technologique.
PCT/CN2021/115811 2021-08-31 2021-08-31 Circuit de calcul de nombre à virgule flottante et procédé de calcul de nombre à virgule flottante WO2023028884A1 (fr)

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